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Revision tags: v6.15, v6.15-rc7, v6.15-rc6, v6.15-rc5, v6.15-rc4, v6.15-rc3, v6.15-rc2, v6.15-rc1, v6.14, v6.14-rc7, v6.14-rc6, v6.14-rc5, v6.14-rc4, v6.14-rc3, v6.14-rc2, v6.14-rc1, v6.13, v6.13-rc7, v6.13-rc6, v6.13-rc5, v6.13-rc4, v6.13-rc3, v6.13-rc2, v6.13-rc1, v6.12, v6.12-rc7 |
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| #
ebac87cd |
| 04-Nov-2024 |
Duje Mihanović <[email protected]> |
clk: mmp: Add Marvell PXA1908 MPMU driver
Add driver for the MPMU controller block on Marvell's PXA1908 SoC. The driver is incomplete, currently only supporting the fixed PLL1; dynamic PLLs 2-4 and
clk: mmp: Add Marvell PXA1908 MPMU driver
Add driver for the MPMU controller block on Marvell's PXA1908 SoC. The driver is incomplete, currently only supporting the fixed PLL1; dynamic PLLs 2-4 and CPU/DDR/AXI clock support is missing.
Signed-off-by: Duje Mihanović <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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03437e85 |
| 04-Nov-2024 |
Duje Mihanović <[email protected]> |
clk: mmp: Add Marvell PXA1908 APMU driver
Add driver for the APMU controller block found on Marvell's PXA1908 SoC. This driver is incomplete, lacking support for (at least) GPU, VPU, DSI and CCIC (c
clk: mmp: Add Marvell PXA1908 APMU driver
Add driver for the APMU controller block found on Marvell's PXA1908 SoC. This driver is incomplete, lacking support for (at least) GPU, VPU, DSI and CCIC (camera related) clocks.
Signed-off-by: Duje Mihanović <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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a89233db |
| 04-Nov-2024 |
Duje Mihanović <[email protected]> |
clk: mmp: Add Marvell PXA1908 APBCP driver
Add driver for the APBCP controller block found on Marvell's PXA1908 SoC.
Signed-off-by: Duje Mihanović <[email protected]> Link: https://lore.kerne
clk: mmp: Add Marvell PXA1908 APBCP driver
Add driver for the APBCP controller block found on Marvell's PXA1908 SoC.
Signed-off-by: Duje Mihanović <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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51ce5591 |
| 04-Nov-2024 |
Duje Mihanović <[email protected]> |
clk: mmp: Add Marvell PXA1908 APBC driver
Add driver for the APBC controller block found on Marvell's PXA1908 SoC.
Signed-off-by: Duje Mihanović <[email protected]> Link: https://lore.kernel.
clk: mmp: Add Marvell PXA1908 APBC driver
Add driver for the APBC controller block found on Marvell's PXA1908 SoC.
Signed-off-by: Duje Mihanović <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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Revision tags: v6.12-rc6, v6.12-rc5, v6.12-rc4, v6.12-rc3, v6.12-rc2, v6.12-rc1, v6.11, v6.11-rc7, v6.11-rc6, v6.11-rc5, v6.11-rc4, v6.11-rc3, v6.11-rc2, v6.11-rc1, v6.10, v6.10-rc7, v6.10-rc6, v6.10-rc5, v6.10-rc4, v6.10-rc3, v6.10-rc2, v6.10-rc1, v6.9, v6.9-rc7, v6.9-rc6, v6.9-rc5, v6.9-rc4, v6.9-rc3, v6.9-rc2, v6.9-rc1, v6.8, v6.8-rc7, v6.8-rc6, v6.8-rc5, v6.8-rc4, v6.8-rc3, v6.8-rc2, v6.8-rc1, v6.7, v6.7-rc8, v6.7-rc7, v6.7-rc6, v6.7-rc5, v6.7-rc4, v6.7-rc3, v6.7-rc2, v6.7-rc1, v6.6, v6.6-rc7, v6.6-rc6, v6.6-rc5, v6.6-rc4, v6.6-rc3, v6.6-rc2, v6.6-rc1, v6.5, v6.5-rc7, v6.5-rc6, v6.5-rc5 |
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979663c3 |
| 04-Aug-2023 |
Duje Mihanović <[email protected]> |
clk: mmp: Remove old non-OF clock drivers
There are no MMP2, PXA168 or PXA910 boards still using board files which would use these drivers, so remove them.
Signed-off-by: Duje Mihanović <duje.mihan
clk: mmp: Remove old non-OF clock drivers
There are no MMP2, PXA168 or PXA910 boards still using board files which would use these drivers, so remove them.
Signed-off-by: Duje Mihanović <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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Revision tags: v6.5-rc4, v6.5-rc3, v6.5-rc2, v6.5-rc1, v6.4, v6.4-rc7, v6.4-rc6, v6.4-rc5, v6.4-rc4, v6.4-rc3, v6.4-rc2, v6.4-rc1, v6.3, v6.3-rc7, v6.3-rc6, v6.3-rc5, v6.3-rc4, v6.3-rc3, v6.3-rc2, v6.3-rc1, v6.2, v6.2-rc8, v6.2-rc7, v6.2-rc6, v6.2-rc5, v6.2-rc4, v6.2-rc3, v6.2-rc2, v6.2-rc1, v6.1, v6.1-rc8, v6.1-rc7, v6.1-rc6, v6.1-rc5, v6.1-rc4, v6.1-rc3, v6.1-rc2, v6.1-rc1, v6.0, v6.0-rc7, v6.0-rc6, v6.0-rc5, v6.0-rc4, v6.0-rc3, v6.0-rc2, v6.0-rc1, v5.19, v5.19-rc8, v5.19-rc7, v5.19-rc6, v5.19-rc5, v5.19-rc4, v5.19-rc3, v5.19-rc2, v5.19-rc1, v5.18, v5.18-rc7, v5.18-rc6, v5.18-rc5, v5.18-rc4, v5.18-rc3, v5.18-rc2, v5.18-rc1, v5.17, v5.17-rc8, v5.17-rc7, v5.17-rc6, v5.17-rc5, v5.17-rc4, v5.17-rc3, v5.17-rc2, v5.17-rc1, v5.16, v5.16-rc8, v5.16-rc7, v5.16-rc6, v5.16-rc5, v5.16-rc4, v5.16-rc3, v5.16-rc2, v5.16-rc1, v5.15, v5.15-rc7, v5.15-rc6, v5.15-rc5, v5.15-rc4, v5.15-rc3, v5.15-rc2, v5.15-rc1, v5.14, v5.14-rc7, v5.14-rc6, v5.14-rc5, v5.14-rc4, v5.14-rc3, v5.14-rc2, v5.14-rc1, v5.13, v5.13-rc7, v5.13-rc6, v5.13-rc5, v5.13-rc4, v5.13-rc3, v5.13-rc2, v5.13-rc1, v5.12, v5.12-rc8, v5.12-rc7, v5.12-rc6, v5.12-rc5, v5.12-rc4, v5.12-rc3, v5.12-rc2, v5.12-rc1, v5.12-rc1-dontuse, v5.11, v5.11-rc7, v5.11-rc6, v5.11-rc5, v5.11-rc4, v5.11-rc3, v5.11-rc2, v5.11-rc1, v5.10, v5.10-rc7, v5.10-rc6, v5.10-rc5, v5.10-rc4, v5.10-rc3, v5.10-rc2, v5.10-rc1, v5.9, v5.9-rc8, v5.9-rc7, v5.9-rc6, v5.9-rc5, v5.9-rc4, v5.9-rc3, v5.9-rc2, v5.9-rc1, v5.8, v5.8-rc7, v5.8-rc6, v5.8-rc5, v5.8-rc4, v5.8-rc3, v5.8-rc2, v5.8-rc1, v5.7, v5.7-rc7 |
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725262d2 |
| 19-May-2020 |
Lubomir Rintel <[email protected]> |
clk: mmp2: Add audio clock controller driver
This is a driver for a block that generates master and bit clocks for the I2S interface. It's separate from the PMUs that generate clocks for the periphe
clk: mmp2: Add audio clock controller driver
This is a driver for a block that generates master and bit clocks for the I2S interface. It's separate from the PMUs that generate clocks for the peripherals.
Signed-off-by: Lubomir Rintel <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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ee4df236 |
| 19-May-2020 |
Lubomir Rintel <[email protected]> |
clk: mmp2: Add support for power islands
Apart from the clocks and resets, the PMU hardware also controls power to peripherals that are on separate power islands. On MMP2, that's the GC860 GPU and t
clk: mmp2: Add support for power islands
Apart from the clocks and resets, the PMU hardware also controls power to peripherals that are on separate power islands. On MMP2, that's the GC860 GPU and the SSPA audio interface, while on MMP3 also the camera interface is on a separate island, along with the pair of GC2000 and GC300 GPUs and the SSPA.
Signed-off-by: Lubomir Rintel <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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Revision tags: v5.7-rc6, v5.7-rc5, v5.7-rc4, v5.7-rc3, v5.7-rc2, v5.7-rc1, v5.6, v5.6-rc7, v5.6-rc6 |
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5d34d0b3 |
| 09-Mar-2020 |
Lubomir Rintel <[email protected]> |
clk: mmp2: Add support for PLL clock sources
The clk-of-mmp2 driver pretends that the clock outputs from the PLLs are constant, but in fact they are configurable.
Add logic for obtaining the actual
clk: mmp2: Add support for PLL clock sources
The clk-of-mmp2 driver pretends that the clock outputs from the PLLs are constant, but in fact they are configurable.
Add logic for obtaining the actual clock rates on MMP2 as well as MMP3. There is no documentation for either SoC, but the "systemsetting" drivers from Marvell GPL code dump provide some clue as far as MPMU registers on MMP2 [1] and MMP3 [2] go.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp2_systemsetting.c [2] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp3_systemsetting.c
A separate commit will adjust the clk-of-mmp2 driver.
Tested on a MMP3-based Dell Wyse 3020 as well as MMP2-based OLPC XO-1.75 laptop.
Signed-off-by: Lubomir Rintel <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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Revision tags: v5.6-rc5, v5.6-rc4, v5.6-rc3, v5.6-rc2, v5.6-rc1, v5.5, v5.5-rc7, v5.5-rc6, v5.5-rc5, v5.5-rc4, v5.5-rc3, v5.5-rc2, v5.5-rc1, v5.4, v5.4-rc8, v5.4-rc7, v5.4-rc6, v5.4-rc5, v5.4-rc4, v5.4-rc3, v5.4-rc2, v5.4-rc1, v5.3, v5.3-rc8, v5.3-rc7, v5.3-rc6, v5.3-rc5, v5.3-rc4, v5.3-rc3, v5.3-rc2, v5.3-rc1, v5.2, v5.2-rc7, v5.2-rc6, v5.2-rc5, v5.2-rc4, v5.2-rc3, v5.2-rc2, v5.2-rc1 |
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| #
a9372a5f |
| 16-May-2019 |
Lubomir Rintel <[email protected]> |
ARM: mmp: add support for MMP3 SoC
Similar to MMP2, which this patch is based on. Known differencies from MMP2 are:
* Two PJ4B cores instead of one PJ4 * Tauros 3 L2 cache controller instead of Tau
ARM: mmp: add support for MMP3 SoC
Similar to MMP2, which this patch is based on. Known differencies from MMP2 are:
* Two PJ4B cores instead of one PJ4 * Tauros 3 L2 cache controller instead of Tauros 2 * A GIC interrupt controller optionally used instead of the MMP one * A TWD local timer * Different USB2 PHY * A USB3 SS controller * More interrupt muxes
Hard to tell what else is different, because documentation is not available.
Signed-off-by: Lubomir Rintel <[email protected]>
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Revision tags: v5.1, v5.1-rc7, v5.1-rc6, v5.1-rc5, v5.1-rc4, v5.1-rc3, v5.1-rc2, v5.1-rc1, v5.0, v5.0-rc8, v5.0-rc7, v5.0-rc6, v5.0-rc5, v5.0-rc4, v5.0-rc3, v5.0-rc2, v5.0-rc1, v4.20, v4.20-rc7, v4.20-rc6, v4.20-rc5, v4.20-rc4, v4.20-rc3, v4.20-rc2, v4.20-rc1, v4.19, v4.19-rc8, v4.19-rc7, v4.19-rc6, v4.19-rc5, v4.19-rc4, v4.19-rc3, v4.19-rc2, v4.19-rc1, v4.18, v4.18-rc8, v4.18-rc7, v4.18-rc6, v4.18-rc5, v4.18-rc4, v4.18-rc3, v4.18-rc2, v4.18-rc1, v4.17, v4.17-rc7, v4.17-rc6, v4.17-rc5, v4.17-rc4, v4.17-rc3, v4.17-rc2, v4.17-rc1, v4.16, v4.16-rc7, v4.16-rc6, v4.16-rc5, v4.16-rc4, v4.16-rc3, v4.16-rc2, v4.16-rc1, v4.15, v4.15-rc9, v4.15-rc8, v4.15-rc7, v4.15-rc6, v4.15-rc5, v4.15-rc4, v4.15-rc3, v4.15-rc2, v4.15-rc1, v4.14, v4.14-rc8 |
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| #
b2441318 |
| 01-Nov-2017 |
Greg Kroah-Hartman <[email protected]> |
License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine
License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license identifiers to apply.
- when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary:
SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became the concluded license(s).
- when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time.
In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related.
Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches.
Reviewed-by: Kate Stewart <[email protected]> Reviewed-by: Philippe Ombredanne <[email protected]> Reviewed-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Revision tags: v4.14-rc7, v4.14-rc6, v4.14-rc5, v4.14-rc4, v4.14-rc3, v4.14-rc2, v4.14-rc1, v4.13, v4.13-rc7, v4.13-rc6, v4.13-rc5, v4.13-rc4, v4.13-rc3, v4.13-rc2, v4.13-rc1, v4.12, v4.12-rc7, v4.12-rc6, v4.12-rc5, v4.12-rc4, v4.12-rc3, v4.12-rc2, v4.12-rc1, v4.11, v4.11-rc8, v4.11-rc7, v4.11-rc6, v4.11-rc5, v4.11-rc4, v4.11-rc3, v4.11-rc2, v4.11-rc1, v4.10, v4.10-rc8, v4.10-rc7, v4.10-rc6, v4.10-rc5, v4.10-rc4, v4.10-rc3, v4.10-rc2, v4.10-rc1, v4.9, v4.9-rc8, v4.9-rc7, v4.9-rc6, v4.9-rc5, v4.9-rc4, v4.9-rc3, v4.9-rc2, v4.9-rc1, v4.8, v4.8-rc8, v4.8-rc7, v4.8-rc6, v4.8-rc5, v4.8-rc4, v4.8-rc3, v4.8-rc2, v4.8-rc1, v4.7, v4.7-rc7, v4.7-rc6, v4.7-rc5, v4.7-rc4, v4.7-rc3, v4.7-rc2, v4.7-rc1, v4.6, v4.6-rc7, v4.6-rc6, v4.6-rc5, v4.6-rc4, v4.6-rc3, v4.6-rc2, v4.6-rc1, v4.5, v4.5-rc7, v4.5-rc6, v4.5-rc5, v4.5-rc4, v4.5-rc3, v4.5-rc2, v4.5-rc1, v4.4, v4.4-rc8, v4.4-rc7, v4.4-rc6, v4.4-rc5, v4.4-rc4, v4.4-rc3, v4.4-rc2, v4.4-rc1, v4.3, v4.3-rc7, v4.3-rc6, v4.3-rc5, v4.3-rc4, v4.3-rc3, v4.3-rc2, v4.3-rc1, v4.2, v4.2-rc8, v4.2-rc7, v4.2-rc6, v4.2-rc5, v4.2-rc4, v4.2-rc3, v4.2-rc2, v4.2-rc1, v4.1, v4.1-rc8, v4.1-rc7, v4.1-rc6, v4.1-rc5, v4.1-rc4 |
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df5338d9 |
| 11-May-2015 |
Rob Herring <[email protected]> |
clk: mmp: add PXA1928 clock support
Add initial clock support for Marvell PXA1928. The PXA1928 is a mobile SOC and is similar to other MMP/PXA series of SOCs, so a lot of the existing infrastructure
clk: mmp: add PXA1928 clock support
Add initial clock support for Marvell PXA1928. The PXA1928 is a mobile SOC and is similar to other MMP/PXA series of SOCs, so a lot of the existing infrastructure is reused here.
Currently the PLLs are just fixed clocks, and not all leaf clocks are implemented.
Signed-off-by: Rob Herring <[email protected]> Cc: Mike Turquette <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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Revision tags: v4.1-rc3, v4.1-rc2, v4.1-rc1, v4.0, v4.0-rc7, v4.0-rc6, v4.0-rc5, v4.0-rc4, v4.0-rc3, v4.0-rc2, v4.0-rc1, v3.19, v3.19-rc7, v3.19-rc6, v3.19-rc5, v3.19-rc4, v3.19-rc3, v3.19-rc2, v3.19-rc1, v3.18, v3.18-rc7, v3.18-rc6, v3.18-rc5, v3.18-rc4, v3.18-rc3 |
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| #
1ec770d9 |
| 31-Oct-2014 |
Chao Xie <[email protected]> |
clk: mmp: add mmp2 DT support for clock driver
It adds the DT support for mmp2 clock subsystem.
Signed-off-by: Chao Xie <[email protected]> Acked-by: Haojian Zhuang <[email protected]> Si
clk: mmp: add mmp2 DT support for clock driver
It adds the DT support for mmp2 clock subsystem.
Signed-off-by: Chao Xie <[email protected]> Acked-by: Haojian Zhuang <[email protected]> Signed-off-by: Michael Turquette <[email protected]>
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2bc61da9 |
| 31-Oct-2014 |
Chao Xie <[email protected]> |
clk: mmp: add pxa910 DT support for clock driver
It adds the DT support for pxa910 clock subsystem.
Signed-off-by: Chao Xie <[email protected]> Acked-by: Haojian Zhuang <[email protected]
clk: mmp: add pxa910 DT support for clock driver
It adds the DT support for pxa910 clock subsystem.
Signed-off-by: Chao Xie <[email protected]> Acked-by: Haojian Zhuang <[email protected]> Signed-off-by: Michael Turquette <[email protected]>
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| #
ab08aefc |
| 31-Oct-2014 |
Chao Xie <[email protected]> |
clk: mmp: add pxa168 DT support for clock driver
It adds the DT support for pxa168 clock subsystem.
Signed-off-by: Chao Xie <[email protected]> Acked-by: Haojian Zhuang <[email protected]
clk: mmp: add pxa168 DT support for clock driver
It adds the DT support for pxa168 clock subsystem.
Signed-off-by: Chao Xie <[email protected]> Acked-by: Haojian Zhuang <[email protected]> Signed-off-by: Michael Turquette <[email protected]>
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| #
ae32a5b3 |
| 31-Oct-2014 |
Chao Xie <[email protected]> |
clk: mmp: add reset support
Some clock control regsiter has bit to reset the cotroller. So before enable the clock, we need deassert the reset pin. Make use of reset controller framework to export r
clk: mmp: add reset support
Some clock control regsiter has bit to reset the cotroller. So before enable the clock, we need deassert the reset pin. Make use of reset controller framework to export reset interface for device drivers, then device driver can control the reset action.
Signed-off-by: Chao Xie <[email protected]> Acked-by: Haojian Zhuang <[email protected]> Signed-off-by: Michael Turquette <[email protected]>
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| #
4661fda1 |
| 31-Oct-2014 |
Chao Xie <[email protected]> |
clk: mmp: add basic support functions for DT support
In order to support DT for mmp SOC clocks, it defines some basic APIs which are shared by all mmp SOC clock units.
Signed-off-by: Chao Xie <chao
clk: mmp: add basic support functions for DT support
In order to support DT for mmp SOC clocks, it defines some basic APIs which are shared by all mmp SOC clock units.
Signed-off-by: Chao Xie <[email protected]> Acked-by: Haojian Zhuang <[email protected]> Signed-off-by: Michael Turquette <[email protected]>
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| #
cdce3546 |
| 31-Oct-2014 |
Chao Xie <[email protected]> |
clk: mmp: add mmp private gate clock
Some SOCes have this kind of the gate clock 1. There are some bits to control the gate not only one bit. 2. It is not always that "1" is to enable while "0" is t
clk: mmp: add mmp private gate clock
Some SOCes have this kind of the gate clock 1. There are some bits to control the gate not only one bit. 2. It is not always that "1" is to enable while "0" is to disable when write register.
So we have to define the "mask", "enable_val", "disable_val" for this kind of gate clock.
Signed-off-by: Chao Xie <[email protected]> Acked-by: Haojian Zhuang <[email protected]> Signed-off-by: Michael Turquette <[email protected]>
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| #
ee81f4ee |
| 31-Oct-2014 |
Chao Xie <[email protected]> |
clk: mmp: add clock type mix
The clock type mix is a kind of clock combines "div" and "mux". This kind of clock can not allow to change div first then mux or change mux first or div. The reason is 1
clk: mmp: add clock type mix
The clock type mix is a kind of clock combines "div" and "mux". This kind of clock can not allow to change div first then mux or change mux first or div. The reason is 1. Some clock has frequency change bit. Each time want to change the frequency, there are some operations based on this bit, and these operations are time-cost. Seperating div and mux change will make the process longer, and waste more time. 2. Seperting the div and mux may generate middle clock that the peripharals do not support. It may make the peripharals hang.
There are three kinds of this type of clock in all SOCes. 1. The clock has bit to trigger the frequency change. 2. Same as #1, but the operations for the bit is different 3. Do not have frequency change bit.
So this type of clock has implemented the callbacks ->determine_rate ->set_rate_and_parent These callbacks can help to change the div and mux together.
Signed-off-by: Chao Xie <[email protected]> Acked-by: Haojian Zhuang <[email protected]> Signed-off-by: Michael Turquette <[email protected]>
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Revision tags: v3.18-rc2, v3.18-rc1, v3.17, v3.17-rc7, v3.17-rc6, v3.17-rc5, v3.17-rc4, v3.17-rc3, v3.17-rc2, v3.17-rc1, v3.16, v3.16-rc7, v3.16-rc6, v3.16-rc5, v3.16-rc4, v3.16-rc3, v3.16-rc2, v3.16-rc1, v3.15, v3.15-rc8, v3.15-rc7, v3.15-rc6, v3.15-rc5, v3.15-rc4, v3.15-rc3, v3.15-rc2, v3.15-rc1, v3.14, v3.14-rc8, v3.14-rc7, v3.14-rc6, v3.14-rc5, v3.14-rc4, v3.14-rc3, v3.14-rc2, v3.14-rc1, v3.13, v3.13-rc8, v3.13-rc7, v3.13-rc6, v3.13-rc5, v3.13-rc4, v3.13-rc3, v3.13-rc2, v3.13-rc1, v3.12, v3.12-rc7, v3.12-rc6, v3.12-rc5, v3.12-rc4, v3.12-rc3, v3.12-rc2, v3.12-rc1, v3.11, v3.11-rc7, v3.11-rc6, v3.11-rc5, v3.11-rc4, v3.11-rc3, v3.11-rc2, v3.11-rc1, v3.10, v3.10-rc7, v3.10-rc6, v3.10-rc5, v3.10-rc4, v3.10-rc3, v3.10-rc2, v3.10-rc1, v3.9, v3.9-rc8, v3.9-rc7, v3.9-rc6, v3.9-rc5, v3.9-rc4, v3.9-rc3, v3.9-rc2, v3.9-rc1, v3.8, v3.8-rc7, v3.8-rc6, v3.8-rc5, v3.8-rc4, v3.8-rc3, v3.8-rc2, v3.8-rc1, v3.7, v3.7-rc8, v3.7-rc7, v3.7-rc6, v3.7-rc5, v3.7-rc4, v3.7-rc3, v3.7-rc2, v3.7-rc1, v3.6, v3.6-rc7, v3.6-rc6, v3.6-rc5, v3.6-rc4, v3.6-rc3 |
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| #
4c5bca34 |
| 20-Aug-2012 |
Chao Xie <[email protected]> |
clk: mmp: add clock definition for mmp2
Initialize the clocks for mmp2
Signed-off-by: Chao Xie <[email protected]> Reviewed-by: Arnd Bergmann <[email protected]> Acked-by: Haojian Zhuang <haojian.
clk: mmp: add clock definition for mmp2
Initialize the clocks for mmp2
Signed-off-by: Chao Xie <[email protected]> Reviewed-by: Arnd Bergmann <[email protected]> Acked-by: Haojian Zhuang <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
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| #
84a62e6e |
| 20-Aug-2012 |
Chao Xie <[email protected]> |
clk: mmp: add clock definition for pxa910
Initialize the clocks for pxa910
Signed-off-by: Chao Xie <[email protected]> Reviewed-by: Arnd Bergmann <[email protected]> Acked-by: Haojian Zhuang <haoj
clk: mmp: add clock definition for pxa910
Initialize the clocks for pxa910
Signed-off-by: Chao Xie <[email protected]> Reviewed-by: Arnd Bergmann <[email protected]> Acked-by: Haojian Zhuang <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
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| #
e1b53b3d |
| 20-Aug-2012 |
Chao Xie <[email protected]> |
clk: mmp: add clock definition for pxa168
Initialize the clocks for pxa168
Signed-off-by: Chao Xie <[email protected]> Reviewed-by: Arnd Bergmann <[email protected]> Acked-by: Haojian Zhuang <haoj
clk: mmp: add clock definition for pxa168
Initialize the clocks for pxa168
Signed-off-by: Chao Xie <[email protected]> Reviewed-by: Arnd Bergmann <[email protected]> Acked-by: Haojian Zhuang <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
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| #
6b63f023 |
| 20-Aug-2012 |
Chao Xie <[email protected]> |
clk: mmp: add mmp specific clocks
add mmp specific clocks including apbc cloks, apmu clocks, and pll2, fraction clocks
Signed-off-by: Chao Xie <[email protected]> Reviewed-by: Arnd Bergmann <a
clk: mmp: add mmp specific clocks
add mmp specific clocks including apbc cloks, apmu clocks, and pll2, fraction clocks
Signed-off-by: Chao Xie <[email protected]> Reviewed-by: Arnd Bergmann <[email protected]> Acked-by: Haojian Zhuang <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
show more ...
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