| 72151193 | 22-Jan-2024 |
Conor Dooley <[email protected]> |
clk: microchip: mpfs: convert MSSPLL outputs to clk_divider
After splitting the MSSPLL in two, the PLL outputs have become
open-coded versions of clk_divider. Drop the custom clk ops structs, and
in
clk: microchip: mpfs: convert MSSPLL outputs to clk_divider
After splitting the MSSPLL in two, the PLL outputs have become
open-coded versions of clk_divider. Drop the custom clk ops structs, and
instead use the generic clk_divider_ops.
Signed-off-by: Conor Dooley <[email protected]>
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| b67dae39 | 22-Jan-2024 |
Conor Dooley <[email protected]> |
clk: microchip: mpfs: add missing MSSPLL outputs
The MSSPLL has 4 outputs, of which only the cpu/axi/ahb clock parent is
currently implemented.
Add the CAN clock too, as that'll be needed by the dri
clk: microchip: mpfs: add missing MSSPLL outputs
The MSSPLL has 4 outputs, of which only the cpu/axi/ahb clock parent is
currently implemented.
Add the CAN clock too, as that'll be needed by the driver for the CAN
controller and uses output 3.
While we are here, the other two missing clocks, used by the eMMC/SD
controller and by the "user crypto".
Signed-off-by: Conor Dooley <[email protected]>
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| 66736997 | 22-Jan-2024 |
Conor Dooley <[email protected]> |
clk: microchip: mpfs: setup for using other mss pll outputs
Now that the MSSPLL is split, and the "postdiv" divider of the
cpu/AHB/AXI bus clock is represented by its own "hw" struct, make the
shift
clk: microchip: mpfs: setup for using other mss pll outputs
Now that the MSSPLL is split, and the "postdiv" divider of the
cpu/AHB/AXI bus clock is represented by its own "hw" struct, make the
shifts, register offset and width a parameter of the initialisation
macro, rather than using defines that only work for one of the four
outputs.
Configuring this at initialisaion paves the way for using the other
three output clocks, where the register offset, and the bit shift
within that register, will differ.
Signed-off-by: Conor Dooley <[email protected]>
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| a3198851 | 10-Mar-2023 |
Rob Herring <[email protected]> |
clk: microchip: Use of_property_read_bool() for boolean properties
It is preferred to use typed property access functions (i.e.
of_property_read_<type> functions) rather than low-level
of_get_proper
clk: microchip: Use of_property_read_bool() for boolean properties
It is preferred to use typed property access functions (i.e.
of_property_read_<type> functions) rather than low-level
of_get_property/of_find_property functions for reading properties.
Convert reading boolean properties to to of_property_read_bool().
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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| 3c79ace9 | 23-Nov-2022 |
Conor Dooley <[email protected]> |
clk: microchip: enable the MPFS clk driver by default if SOC_MICROCHIP_POLARFIRE
With the intent of removing driver selects from Kconfig.socs in
arch/riscv, essential drivers that were being selecte
clk: microchip: enable the MPFS clk driver by default if SOC_MICROCHIP_POLARFIRE
With the intent of removing driver selects from Kconfig.socs in
arch/riscv, essential drivers that were being selected there could
instead by enabled by defaulting them to the value of the SoC's Kconfig
symbol.
Do so here & drop the depend on RISC-V - the SOC_ symbols are only
defined there anyway.
Signed-off-by: Conor Dooley <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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| d39fb172 | 08-Sep-2022 |
Conor Dooley <[email protected]> |
clk: microchip: add PolarFire SoC fabric clock support
Add a driver to support the PLLs in PolarFire SoC's Clock Conditioning
Circuitry, an instance of which is located in each ordinal corner of
the
clk: microchip: add PolarFire SoC fabric clock support
Add a driver to support the PLLs in PolarFire SoC's Clock Conditioning
Circuitry, an instance of which is located in each ordinal corner of
the FPGA. Only get_rate() is supported as these clocks are intended to
be statically configured by the FPGA design. Currently, the DLLs are
not supported by this driver. For more information on the hardware, see
"PolarFire SoC FPGA Clocking Resources" in the link below.
Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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| d325268b | 09-Sep-2022 |
Conor Dooley <[email protected]> |
clk: microchip: mpfs: update module authorship & licencing
Padmarao wrote the driver in its original, pre upstream form.
Daire & myself have been responsible for getting it upstreamable and
subseque
clk: microchip: mpfs: update module authorship & licencing
Padmarao wrote the driver in its original, pre upstream form.
Daire & myself have been responsible for getting it upstreamable and
subsequent development.
Move Daire out of the blurb & into a MODULE_AUTHOR entry & add entries
for myself and Padmarao.
While we are at it, convert the MODULE_LICENSE field to its preferred
form of "GPL".
Reviewed-by: Daire McNamara <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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| d8155697 | 09-Sep-2022 |
Conor Dooley <[email protected]> |
clk: microchip: mpfs: convert periph_clk to clk_gate
With the reset code moved to the recently added reset controller, there
is no need for custom ops any longer. Remove the custom ops and the
custo
clk: microchip: mpfs: convert periph_clk to clk_gate
With the reset code moved to the recently added reset controller, there
is no need for custom ops any longer. Remove the custom ops and the
custom struct by converting to a clk_gate.
Reviewed-by: Daire McNamara <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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| 4da2404b | 09-Sep-2022 |
Conor Dooley <[email protected]> |
clk: microchip: mpfs: convert cfg_clk to clk_divider
The cfg_clk struct is now just a redefinition of the clk_divider struct
with custom implentations of the ops, that implement an extra level of
re
clk: microchip: mpfs: convert cfg_clk to clk_divider
The cfg_clk struct is now just a redefinition of the clk_divider struct
with custom implentations of the ops, that implement an extra level of
redirection. Remove the custom struct and replace it with clk_divider.
Reviewed-by: Daire McNamara <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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| 5fa27b77 | 09-Sep-2022 |
Conor Dooley <[email protected]> |
clk: microchip: mpfs: simplify control reg access
The control reg addresses are known when the clocks are registered, so
we can, instead of assigning a base pointer to the structs, assign the
contro
clk: microchip: mpfs: simplify control reg access
The control reg addresses are known when the clocks are registered, so
we can, instead of assigning a base pointer to the structs, assign the
control reg addresses directly. Accordingly, remove the interim
variables used during reads/writes to those registers.
Reviewed-by: Daire McNamara <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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| 52fe6b52 | 09-Sep-2022 |
Conor Dooley <[email protected]> |
clk: microchip: mpfs: move id & offset out of clock structs
The id and offset are the only thing differentiating the clock structs
from "regular" clock structures. On the pretext of converting to mo
clk: microchip: mpfs: move id & offset out of clock structs
The id and offset are the only thing differentiating the clock structs
from "regular" clock structures. On the pretext of converting to more
normal structures, move the id and offset out of the clock structs and
into the hw structs instead.
Reviewed-by: Daire McNamara <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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| 14016e4a | 09-Sep-2022 |
Conor Dooley <[email protected]> |
clk: microchip: mpfs: add MSS pll's set & round rate
The MSS pll is not a fixed frequency clock, so add set() & round_rate()
support.
Control is limited to a 7 bit output divider as other devices on
clk: microchip: mpfs: add MSS pll's set & round rate
The MSS pll is not a fixed frequency clock, so add set() & round_rate()
support.
Control is limited to a 7 bit output divider as other devices on the
FPGA occupy the other three outputs of the PLL & prevent changing
the multiplier.
Reviewed-by: Daire McNamara <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Claudiu Beznea <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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