| 65c1f037 | 05-May-2023 |
Maxime Ripard <[email protected]> |
clk: ingenic: tcu: Switch to determine_rate
The Ingenic TCU clocks implements a mux with a set_parent hook, but
doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent(
clk: ingenic: tcu: Switch to determine_rate
The Ingenic TCU clocks implements a mux with a set_parent hook, but
doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies,
change the parent of a clock. However, the most likely candidate to
trigger that parent change is a call to clk_set_rate(), with
determine_rate() figuring out which parent is the best suited for a
given rate.
The other trigger would be a call to clk_set_parent(), but it's far less
used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an
oversight. However, it could also be an explicit decision by the
original author to avoid any reparenting but through an explicit call to
clk_set_parent().
The driver does implement round_rate() though, which means that we can
change the rate of the clock, but we will never get to change the
parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's
convert the round_rate() implementation to a determine_rate(), which
will also make the current behavior explicit. And if it was an
oversight, the clock behaviour can be adjusted later on.
Cc: Paul Cercueil <[email protected]>
Cc: [email protected]
Signed-off-by: Maxime Ripard <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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|
| 662e8ed7 | 26-Oct-2022 |
Aidan MacDonald <[email protected]> |
clk: ingenic: Add X1000 audio clocks
The X1000's CGU supplies the I2S system clock to the AIC module
and ultimately the audio codec, represented by the "i2s" clock.
It is a simple mux which can eith
clk: ingenic: Add X1000 audio clocks
The X1000's CGU supplies the I2S system clock to the AIC module
and ultimately the audio codec, represented by the "i2s" clock.
It is a simple mux which can either pass through EXCLK or a PLL
multiplied by a fractional divider (the "i2s_pll" clock).
The AIC contains a separate 1/N divider controlled by the I2S
driver, which generates the bit clock from the system clock.
The frame clock is always fixed to 1/64th of the bit clock.
Signed-off-by: Aidan MacDonald <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Paul Cercueil <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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|
| c799a777 | 26-Oct-2022 |
Aidan MacDonald <[email protected]> |
clk: ingenic: Add .set_rate_hook() for PLL clocks
The set rate hook is called immediately after updating the clock
register but before the spinlock is released. This allows another
register to be up
clk: ingenic: Add .set_rate_hook() for PLL clocks
The set rate hook is called immediately after updating the clock
register but before the spinlock is released. This allows another
register to be updated alongside the main one, which is needed to
handle the I2S divider on some SoCs.
Signed-off-by: Aidan MacDonald <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Paul Cercueil <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
show more ...
|
| d84bf9d6 | 26-Oct-2022 |
Aidan MacDonald <[email protected]> |
clk: ingenic: Make PLL clock enable_bit and stable_bit optional
When the enable bit is undefined, the clock is assumed to be always
on and enable/disable is a no-op. When the stable bit is undefined
clk: ingenic: Make PLL clock enable_bit and stable_bit optional
When the enable bit is undefined, the clock is assumed to be always
on and enable/disable is a no-op. When the stable bit is undefined,
the PLL stable check is a no-op.
Signed-off-by: Aidan MacDonald <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Paul Cercueil <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
show more ...
|
| e98839fb | 12-Apr-2022 |
Aidan MacDonald <[email protected]> |
clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCs
The TCU clock gate on X1000 wasn't requested by the driver and could
be gated automatically later on in boot, which prevents timers from
runnin
clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCs
The TCU clock gate on X1000 wasn't requested by the driver and could
be gated automatically later on in boot, which prevents timers from
running and breaks PWM.
Add a workaround to support old device trees that don't specify the
"tcu" clock gate. In this case the kernel will print a warning and
attempt to continue without the clock, which is wrong, but it could
work if "clk_ignore_unused" is in the kernel arguments.
Signed-off-by: Aidan MacDonald <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Paul Cercueil <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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|
| ca54d06f | 28-Apr-2022 |
Aidan MacDonald <[email protected]> |
clk: ingenic: Mark critical clocks in Ingenic SoCs
Consider CPU, L2 cache, and memory clocks as critical to prevent
them -- and the parent clocks -- from being automatically gated,
since nothing cal
clk: ingenic: Mark critical clocks in Ingenic SoCs
Consider CPU, L2 cache, and memory clocks as critical to prevent
them -- and the parent clocks -- from being automatically gated,
since nothing calls clk_get() on these clocks.
Gating the CPU clock hangs the processor, and gating memory makes
external DRAM inaccessible. Normal kernel code can't hope to deal
with either situation so those clocks have to be critical.
The L2 cache is required only if caches are running, and could be
gated if the kernel takes care to flush and disable caches before
gating the clock. There's no mechanism to do this, and probably no
reason to do it, so it's simpler to mark the L2 cache as critical.
Signed-off-by: Aidan MacDonald <[email protected]>
Reviewed-by: Paul Cercueil <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Tested-by: 周琰杰 (Zhou Yanjie) <[email protected]> # On X1000 and X1830
Signed-off-by: Stephen Boyd <[email protected]>
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| 1a3c4dd4 | 03-Sep-2020 |
Paul Cercueil <[email protected]> |
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
Clocks that don't have a divider are in our case all marked with the
CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation
s
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
Clocks that don't have a divider are in our case all marked with the
CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation
should modify the value pointed to by parent_rate, in order to propagate
the rate change to the parent, as explained in the documentation of
clk_set_rate().
Signed-off-by: Paul Cercueil <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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| 2e4ee634 | 03-Sep-2020 |
Paul Cercueil <[email protected]> |
clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
The custom clocks have custom functions to round, get or set their rate.
Therefore, we can't assume that they need the CLK_SET_RATE_PAR
clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
The custom clocks have custom functions to round, get or set their rate.
Therefore, we can't assume that they need the CLK_SET_RATE_PARENT flag.
Signed-off-by: Paul Cercueil <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
show more ...
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