clk: imx: add i.MX95 BLK CTL clk driver

i.MX95 has BLK CTL modules in various MIXes, the BLK CTL modules
support clock features such as mux/gate/div. This patch
is to add the clock feature of BLK CT

clk: imx: add i.MX95 BLK CTL clk driver

i.MX95 has BLK CTL modules in various MIXes, the BLK CTL modules
support clock features such as mux/gate/div. This patch
is to add the clock feature of BLK CTL modules

Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>

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clk: imx: imx8: add audio clock mux driver

The Audio Clock Mux (ACM) is a collection of control registers
and multiplexers that are used to route the audio source clocks
to the audio peripherals.

E

clk: imx: imx8: add audio clock mux driver

The Audio Clock Mux (ACM) is a collection of control registers
and multiplexers that are used to route the audio source clocks
to the audio peripherals.

Each audio peripheral has its dedicated audio clock mux
(which differ based on usage) and control register.

Signed-off-by: Shengjiu Wang <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>

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clk: imx: imx8mp: Add audiomix block control

Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
series of clock gates and muxes. Model it as a large static table of
gates and mux

clk: imx: imx8mp: Add audiomix block control

Unlike the other block control IPs in i.MX8M, the audiomix is mostly a
series of clock gates and muxes. Model it as a large static table of
gates and muxes with one exception, which is the PLL14xx . The PLL14xx
SAI PLL has to be registered separately.

Reviewed-by: Marco Felsch <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Tested-by: Adam Ford <[email protected]> #imx8mp-beacon-kit
Tested-by: Alexander Stein <[email protected]>
Tested-by: Luca Ceresoli <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Tested-by: Richard Leitner <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clk: imx: add clk-gpr-mux driver

Almost(?) every i.MX variant has clk mux for ethernet (rgmii/rmii) reference
clock located in the GPR1 register. So far this clk is configured in
different ways:
- m

clk: imx: add clk-gpr-mux driver

Almost(?) every i.MX variant has clk mux for ethernet (rgmii/rmii) reference
clock located in the GPR1 register. So far this clk is configured in
different ways:
- mach-imx6q is doing mux configuration based on ptp vs enet_ref clk
comparison.
- mach-imx7d is setting mux to PAD for all boards
- mach-imx6ul is setting mux to internal clock for all boards.

Since we have imx7d and imx6ul board variants which do not work with
configurations forced by kernel mach code, we need to implement this clk
mux properly as part of the clk framework. Which is done by this patch.

Signed-off-by: Oleksij Rempel <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clk: imx: add i.MX93 clk gate

i.MX93 LPCG is different from i.MX8M CCGR. Although imx_clk_hw_gate4_flags
is used here, it not strictly match i.MX93. i.MX93 has such design:
- LPCG_DIRECT use BIT0 a

clk: imx: add i.MX93 clk gate

i.MX93 LPCG is different from i.MX8M CCGR. Although imx_clk_hw_gate4_flags
is used here, it not strictly match i.MX93. i.MX93 has such design:
- LPCG_DIRECT use BIT0 as on/off gate when LPCG_AUTHEN CPU_LPM is 0
- LPCG_LPM_CUR use BIT[2:0] as on/off gate when LPCG_AUTHEN CPU_LPM is 1

The current implementation suppose CPU_LPM is 0, and use LPCG_DIRECT
BIT[1:0] as on/off gate. Although BIT1 is touched, actually BIT1 is
reserved.

And imx_clk_hw_gate4_flags use mask 0x3 to determine whether the clk
is enabled or not, but i.MX93 LPCG only use BIT0 to control when CPU_LPM
is 0. So clk disabled unused during kernel boot not able to gate off
the unused clocks.

To match i.MX93 LPCG, introduce imx93_clk_gate.

Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Ye Li <[email protected]>
Reviewed-by: Jacky Bai <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clk: imx: add i.MX93 clk

Add i.MX93 clk driver. i.MX93 clk hardware design is different compared
with i.MX8M. It supports 4 sources for each clk root and the sources
are separated into a few groups,

clk: imx: add i.MX93 clk

Add i.MX93 clk driver. i.MX93 clk hardware design is different compared
with i.MX8M. It supports 4 sources for each clk root and the sources
are separated into a few groups, low speed/fast io/audio and etc.

Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: Added missing module license and description]
Signed-off-by: Abel Vesa <[email protected]>

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clk: imx: support fracn gppll

This PLL module is a Fractional-N synthesizer,
supporting 30-bit numerator and denominator. Numerator is a signed
number. It has feature to adjust fractional portion of

clk: imx: support fracn gppll

This PLL module is a Fractional-N synthesizer,
supporting 30-bit numerator and denominator. Numerator is a signed
number. It has feature to adjust fractional portion of feedback
divider dynamically. This fracn gppll is used in i.MX93.

Reviewed-by: Abel Vesa <[email protected]>
Reviewed-by: Sascha Hauer <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>

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clk: imx: add i.MX93 composite clk

i.MX93 CCM ROOT clock has a mux, gate and divider in one register, here
is to combine all these into one composite clk and simplify clk tree.
i.MX93 CCM is a new I

clk: imx: add i.MX93 composite clk

i.MX93 CCM ROOT clock has a mux, gate and divider in one register, here
is to combine all these into one composite clk and simplify clk tree.
i.MX93 CCM is a new IP compared with i.MX8M, so introduce a new file.

Reviewed-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>

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clk: imx: Add imx8dxl clk driver

Add files for imx8dxl clk driver which is based on imx8qxp clock driver.

Signed-off-by: Jacky Bai <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
Ac

clk: imx: Add imx8dxl clk driver

Add files for imx8dxl clk driver which is based on imx8qxp clock driver.

Signed-off-by: Jacky Bai <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clk: imx: Add initial support for i.MXRT1050 clock driver

Add clock driver support for i.MXRT1050.

Signed-off-by: Jesse Taube <[email protected]>
Suggested-by: Giulio Benetti <giulio.benetti@

clk: imx: Add initial support for i.MXRT1050 clock driver

Add clock driver support for i.MXRT1050.

Signed-off-by: Jesse Taube <[email protected]>
Suggested-by: Giulio Benetti <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>

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clk: imx: Add clock driver for imx8ulp

Add clock driver for i.MX8ULP.

Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Jacky Bai <[email protected]>
Reviewed-by: Abel Vesa <[email protected]

clk: imx: Add clock driver for imx8ulp

Add clock driver for i.MX8ULP.

Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Jacky Bai <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>

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clk: imx8qm: add clock valid resource checking

Add imx8qm clock valid resource checking mechanism

Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signe

clk: imx8qm: add clock valid resource checking

Add imx8qm clock valid resource checking mechanism

Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>

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clk: imx8qxp: add clock valid checking mechnism

clk-imx8qxp is a common SCU clock driver used by both QM and QXP
platforms. The clock numbers vary a bit between those two platforms.
This patch intro

clk: imx8qxp: add clock valid checking mechnism

clk-imx8qxp is a common SCU clock driver used by both QM and QXP
platforms. The clock numbers vary a bit between those two platforms.
This patch introduces a mechanism to only register the valid clocks
for one platform by checking the clk resource id table.

Signed-off-by: Dong Aisheng <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Abel Vesa <[email protected]>

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clk: imx: imx21: Remove clock driver

As i.MX21 support has been removed, get rid of its clock driver too.

Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
S

clk: imx: imx21: Remove clock driver

As i.MX21 support has been removed, get rid of its clock driver too.

Signed-off-by: Fabio Estevam <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>

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clk: imx8qxp: Support building i.MX8QXP clock driver as module

Change configuration to "tristate", add module author, description and
license to support building i.MX8QXP clock drivers as module.

S

clk: imx8qxp: Support building i.MX8QXP clock driver as module

Change configuration to "tristate", add module author, description and
license to support building i.MX8QXP clock drivers as module.

Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>

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clk: imx: Add clock configuration for ARMv7 platforms

Add CONFIG_CLK_xxx for i.MX ARMv7 platforms, and use it as build option
instead of CONFIG_SOC_xxx, the CONFIG_CLK_xxx will be selected by defaul

clk: imx: Add clock configuration for ARMv7 platforms

Add CONFIG_CLK_xxx for i.MX ARMv7 platforms, and use it as build option
instead of CONFIG_SOC_xxx, the CONFIG_CLK_xxx will be selected by default
according to CONFIG_SOC_xxx.

Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>

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clk: imx: Support building i.MX common clock driver as module

There are more and more requirements of building SoC specific drivers
as modules, add support for building i.MX common clock driver as m

clk: imx: Support building i.MX common clock driver as module

There are more and more requirements of building SoC specific drivers
as modules, add support for building i.MX common clock driver as module
to meet the requirement.

Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>

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clk: imx: Add support for i.MX8MP clock driver

Add clock driver support for i.MX8MP which is a new SoC of i.MX8M
family.

Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Abel Vesa <abe

clk: imx: Add support for i.MX8MP clock driver

Add clock driver support for i.MX8MP which is a new SoC of i.MX8M
family.

Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>

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clk: imx: Rename the SCCG to SSCG

According to the manual the acronym stands for
Spread Sprectum Clock Generator.

Signed-off-by: Abel Vesa <[email protected]>
Signed-off-by: Shawn Guo <shawnguo@ker

clk: imx: Rename the SCCG to SSCG

According to the manual the acronym stands for
Spread Sprectum Clock Generator.

Signed-off-by: Abel Vesa <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>

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clk: imx: Add support for i.MX8MN clock driver

This patch adds i.MX8MN clock driver support.

Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>

clk: imx: rename clk-imx51-imx53.c to clk-imx5.c

As the driver is handling all i.MX5 series SoCs inlcuding i.MX50, rather
than just i.MX51 and i.MX53, let's rename it to clk-imx5.c.

Signed-off-by:

clk: imx: rename clk-imx51-imx53.c to clk-imx5.c

As the driver is handling all i.MX5 series SoCs inlcuding i.MX50, rather
than just i.MX51 and i.MX53, let's rename it to clk-imx5.c.

Signed-off-by: Shawn Guo <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>

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clk: imx: Add clock driver support for imx8mm

Add clock driver support for i.MX8MM SOC.

Signed-off-by: Bai Ping <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

clk: imx: Add PLLs driver for imx8mm soc

New PLLs are introduced on i.MX8M Mini SOC.
PLL1416X is Integer PLL, PLL1443X is a Frac PLL.

Signed-off-by: Bai Ping <[email protected]>
Signed-off-by: Steph

clk: imx: Add PLLs driver for imx8mm soc

New PLLs are introduced on i.MX8M Mini SOC.
PLL1416X is Integer PLL, PLL1443X is a Frac PLL.

Signed-off-by: Bai Ping <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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clk: imx: add imx8qxp lpcg driver

Add imx8qxp lpcg driver support

Cc: Stephen Boyd <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam

clk: imx: add imx8qxp lpcg driver

Add imx8qxp lpcg driver support

Cc: Stephen Boyd <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Michael Turquette <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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clk: imx: add lpcg clock support

The Low-Power Clock Gate (LPCG) modules contain a local programming
model to control the clock gates for the peripherals. An LPCG module
is used to locally gate the

clk: imx: add lpcg clock support

The Low-Power Clock Gate (LPCG) modules contain a local programming
model to control the clock gates for the peripherals. An LPCG module
is used to locally gate the clocks for the associated peripheral.
And they're bedind the SCU clock.

Cc: Stephen Boyd <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Michael Turquette <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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