clk: lan966x: make it selectable for ARCH_LAN969X

LAN969x uses the same LAN966x clock driver so make it selectable for
ARCH_LAN969X.

Signed-off-by: Robert Marko <[email protected]>
Link: http

clk: lan966x: make it selectable for ARCH_LAN969X

LAN969x uses the same LAN966x clock driver so make it selectable for
ARCH_LAN969X.

Signed-off-by: Robert Marko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: eyeq: add driver

Add Mobileye EyeQ5, EyeQ6L and EyeQ6H clock controller driver. It is
both a platform driver and a hook onto of_clk_init() used for clocks
required early (GIC timer, UARTs).

Fo

clk: eyeq: add driver

Add Mobileye EyeQ5, EyeQ6L and EyeQ6H clock controller driver. It is
both a platform driver and a hook onto of_clk_init() used for clocks
required early (GIC timer, UARTs).

For some compatible, it is both at the same time. eqc_early_init()
initialises early PLLs and exposes its own clock provider. It marks
other clocks as deferred. eqc_probe() adds all remaining clocks using
another clock provider.

It exposes read-only PLLs derived from the main crystal on board.
It also exposes another type of clocks: divider clocks.
They always have even divisors and have one PLL as parent.

This driver also bears the responsability for optional reset and pinctrl
auxiliary devices. The match data attached to the devicetree node
compatible indicate if such devices should be created. They all get
passed a pointer to the start of the OLB region.

Signed-off-by: Théo Lebrun <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: Allow kunit tests to run without OF_OVERLAY enabled

Some configurations want to enable CONFIG_KUNIT without enabling
CONFIG_OF_OVERLAY. The kunit overlay code already skips if
CONFIG_OF_OVERLAY

clk: Allow kunit tests to run without OF_OVERLAY enabled

Some configurations want to enable CONFIG_KUNIT without enabling
CONFIG_OF_OVERLAY. The kunit overlay code already skips if
CONFIG_OF_OVERLAY isn't enabled, so these selects here aren't really
doing anything besides making it easier to run the tests without them
skipping. Remove the select and move the config setting to the
drivers/clk/.kunitconfig file so that the clk tests can be run with or
without CONFIG_OF_OVERLAY set to test either behavior.

Fixes: 5776526beb95 ("clk: Add KUnit tests for clk fixed rate basic type")
Fixes: 274aff8711b2 ("clk: Add KUnit tests for clks registered with struct clk_parent_data")
Signed-off-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clk: npcm8xx: add clock controller

Add auxiliary driver to support Nuvoton Arbel BMC NPCM8XX contains an
integrated clock controller which generates and supplies clocks to all
modules within the BMC

clk: npcm8xx: add clock controller

Add auxiliary driver to support Nuvoton Arbel BMC NPCM8XX contains an
integrated clock controller which generates and supplies clocks to all
modules within the BMC.

The NPCM8xx clock controller is created using the auxiliary device
framework and set up in the npcm reset driver since the NPCM8xx clock is
using the same register region.

Signed-off-by: Tomer Maimon <[email protected]>
Tested-by: Benjamin Fair <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: twl: add TWL6030 support

The TWL6030 has similar clocks, so add support for it. Take care of the
resource grouping handling needed.

Signed-off-by: Andreas Kemnade <[email protected]>
Link:

clk: twl: add TWL6030 support

The TWL6030 has similar clocks, so add support for it. Take care of the
resource grouping handling needed.

Signed-off-by: Andreas Kemnade <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Roger Quadros <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

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clk: ep93xx: add DT support for Cirrus EP93xx

Rewrite EP93xx clock driver located in arch/arm/mach-ep93xx/clock.c
trying to do everything the device tree way:

- provide clock acces via of
- drop cl

clk: ep93xx: add DT support for Cirrus EP93xx

Rewrite EP93xx clock driver located in arch/arm/mach-ep93xx/clock.c
trying to do everything the device tree way:

- provide clock acces via of
- drop clk_hw_register_clkdev
- drop init code and use module_auxiliary_driver

Co-developed-by: Alexander Sverdlin <[email protected]>
Signed-off-by: Alexander Sverdlin <[email protected]>
Signed-off-by: Nikita Shubin <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>

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clk: Add KUnit tests for clks registered with struct clk_parent_data

Test that clks registered with 'struct clk_parent_data' work as
intended and can find their parents.

Cc: Christian Marangi <ansu

clk: Add KUnit tests for clks registered with struct clk_parent_data

Test that clks registered with 'struct clk_parent_data' work as
intended and can find their parents.

Cc: Christian Marangi <[email protected]>
Cc: Brendan Higgins <[email protected]>
Reviewed-by: David Gow <[email protected]>
Cc: Rae Moar <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clk: Add KUnit tests for clk fixed rate basic type

Test that the fixed rate basic type clk works as intended.

Cc: Brendan Higgins <[email protected]>
Cc: David Gow <[email protected]>
Cc:

clk: Add KUnit tests for clk fixed rate basic type

Test that the fixed rate basic type clk works as intended.

Cc: Brendan Higgins <[email protected]>
Cc: David Gow <[email protected]>
Cc: Rae Moar <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks

Add support for the AP sub-system clock controller in the T-Head TH1520.
This include CPU, DPU, GMAC and TEE PLLs.

Link: https://openbeagl

clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks

Add support for the AP sub-system clock controller in the T-Head TH1520.
This include CPU, DPU, GMAC and TEE PLLs.

Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
Co-developed-by: Yangtao Li <[email protected]>
Signed-off-by: Yangtao Li <[email protected]>
Co-developed-by: Jisheng Zhang <[email protected]>
Signed-off-by: Jisheng Zhang <[email protected]>
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: disable clk gate tests for s390

Currently clk-gate tests for s390 fail as the tests create a pretend
clk-gate and use a "fake_reg" to emulate the expected behavior of the
clk_gate->reg. I added

clk: disable clk gate tests for s390

Currently clk-gate tests for s390 fail as the tests create a pretend
clk-gate and use a "fake_reg" to emulate the expected behavior of the
clk_gate->reg. I added some debug statements to the driver and noticed
that the reg changes after initialization to -1, which is coming from an
error coming from zpci_load(). This is likely because the test is using
fake iomem and the s390 architecture likely isn't designed to handle
that. Turn off the clk-gate tests for s390 for now as there is no clear
work around for this problem as discussed in upstream conversation [1].

[1] https://lore.kernel.org/all/[email protected]/T/#t

Signed-off-by: Audra Mitchell <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: sophgo: Add clock support for CV1800 SoC

Add clock definition and driver code for CV1800 SoC.

Signed-off-by: Inochi Amaoto <[email protected]>
Link: https://github.com/milkv-duo/duo-files/

clk: sophgo: Add clock support for CV1800 SoC

Add clock definition and driver code for CV1800 SoC.

Signed-off-by: Inochi Amaoto <[email protected]>
Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV180X-Clock-v1.xlsx
Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf
Link: https://lore.kernel.org/r/IA1PR20MB49534F37F802CAF117364D66BB262@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Stephen Boyd <[email protected]>

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clk: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210

Since SOC_FOO should be deprecated from patch [1], and cleanup for other
SoCs is already in the mailing list [2,3,4], we remove the use of
SOC

clk: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210

Since SOC_FOO should be deprecated from patch [1], and cleanup for other
SoCs is already in the mailing list [2,3,4], we remove the use of
SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers,

Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select
when it has the symbol SOC_CANAAN_K210.

[1] https://lore.kernel.org/linux-riscv/[email protected]/
[2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
[3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
[4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/

Signed-off-by: Yangyu Chen <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>

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clk: stm32mp1: move stm32mp1 clock driver into stm32 directory

Move all STM32MP clock drivers into same directory (stm32).

Signed-off-by: Gabriel Fernandez <[email protected]>
Link: htt

clk: stm32mp1: move stm32mp1 clock driver into stm32 directory

Move all STM32MP clock drivers into same directory (stm32).

Signed-off-by: Gabriel Fernandez <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: twl: add clock driver for TWL6032

The TWL6032 has some clock outputs which are controlled like
fixed-voltage regulators, in some drivers for these chips
found in the wild, just the regulator ap

clk: twl: add clock driver for TWL6032

The TWL6032 has some clock outputs which are controlled like
fixed-voltage regulators, in some drivers for these chips
found in the wild, just the regulator api is abused for controlling
them, so simply use something similar to the regulator functions.
Due to a lack of hardware available for testing, leave out the
TWL6030-specific part of those functions.

Signed-off-by: Andreas Kemnade <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: fractional-divider: tests: Add test suite for edge cases

In light of the recent discovery that the fractional divisor
approximation does not utilize the full available range for clocks that
are

clk: fractional-divider: tests: Add test suite for edge cases

In light of the recent discovery that the fractional divisor
approximation does not utilize the full available range for clocks that
are flagged CLK_FRAC_DIVIDER_ZERO_BASED [1], implement tests for the
edge cases of this clock type.

Signed-off-by: Frank Oltmanns <[email protected]>
Link: https://lore.kernel.org/lkml/[email protected] [1]
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: Rename suite and tests slightly, drop unused
includes, store parent rate to compare instead of repeating equation]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: Add support for versa3 clock driver

Add support for Renesas versa3 clock driver(5p35023).
The clock generator provides 6 output clocks.

Signed-off-by: Biju Das <[email protected]>
Lin

clk: Add support for versa3 clock driver

Add support for Renesas versa3 clock driver(5p35023).
The clock generator provides 6 output clocks.

Signed-off-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: Add newline to printk]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: oxnas: remove obsolete clock driver

Due to lack of maintenance and stall of development for a few years now,
and since no new features will ever be added upstream, remove support
for OX810 and

clk: oxnas: remove obsolete clock driver

Due to lack of maintenance and stall of development for a few years now,
and since no new features will ever be added upstream, remove support
for OX810 and OX820 clock driver.

Acked-by: Linus Walleij <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Daniel Golle <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/20230630-topic-oxnas-upstream-remove-v2-1-fb6ab3dea87c@linaro.org
Signed-off-by: Stephen Boyd <[email protected]>

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clk: fixed-mmio: make COMMON_CLK_FIXED_MMIO depend on HAS_IOMEM

On s390 systems (aka mainframes), it has classic channel devices for
networking and permanent storage that are currently even more com

clk: fixed-mmio: make COMMON_CLK_FIXED_MMIO depend on HAS_IOMEM

On s390 systems (aka mainframes), it has classic channel devices for
networking and permanent storage that are currently even more common
than PCI devices. Hence it could have a fully functional s390 kernel
with CONFIG_PCI=n, then the relevant iomem mapping functions
[including ioremap(), devm_ioremap(), etc.] are not available.

Here let COMMON_CLK_FIXED_MMIO depend on HAS_IOMEM so that it won't
be built to cause below compiling error if PCI is unset:

------
ld: drivers/clk/clk-fixed-mmio.o: in function `fixed_mmio_clk_setup':
clk-fixed-mmio.c:(.text+0x5e): undefined reference to `of_iomap'
ld: clk-fixed-mmio.c:(.text+0xba): undefined reference to `iounmap'
------

Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Signed-off-by: Baoquan He <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: nuvoton: Add clock driver for ma35d1 clock controller

The clock controller generates clocks for the whole chip, including
system clocks and all peripheral clocks. This driver support ma35d1
clo

clk: nuvoton: Add clock driver for ma35d1 clock controller

The clock controller generates clocks for the whole chip, including
system clocks and all peripheral clocks. This driver support ma35d1
clock gating, divider, and individual PLL configuration.

There are 6 PLLs in ma35d1 SoC:
- CA-PLL for the two Cortex-A35 CPU clock
- SYS-PLL for system bus, which comes from the companion MCU
and cannot be programmed by clock controller.
- DDR-PLL for DDR
- EPLL for GMAC and GFX, Display, and VDEC IPs.
- VPLL for video output pixel clock
- APLL for SDHC, I2S audio, and other IPs.
CA-PLL has only one operation mode.
DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3
operation modes: integer mode, fraction mode, and spread specturm mode.

Signed-off-by: Jacky Huang <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>

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mfd: rk808: Split into core and i2c

Split rk808 into a core and an i2c part in preparation for
SPI support.

Acked-by: Alexandre Belloni <[email protected]> # for RTC
Tested-by: Diederik

mfd: rk808: Split into core and i2c

Split rk808 into a core and an i2c part in preparation for
SPI support.

Acked-by: Alexandre Belloni <[email protected]> # for RTC
Tested-by: Diederik de Haas <[email protected]> # Rock64, Quartz64 Model A + B
Tested-by: Vincent Legoll <[email protected]> # Pine64 QuartzPro64
Signed-off-by: Sebastian Reichel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Lee Jones <[email protected]>

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clk: clk-loongson2: add clock controller driver support

This driver provides support for clock controller on Loongson-2 SoC,
the Loongson-2 SoC uses a 100MHz clock as the PLL reference clock,
there

clk: clk-loongson2: add clock controller driver support

This driver provides support for clock controller on Loongson-2 SoC,
the Loongson-2 SoC uses a 100MHz clock as the PLL reference clock,
there are five independent PLLs inside, each of which PLL can
provide up to three sets of frequency dependent clock outputs.

Signed-off-by: Yinbo Zhu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators

Add driver for the Skyworks Si521xx PCIe clock generators. Supported models
are Si52144/Si52146/Si52147, tested model is Si5

clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators

Add driver for the Skyworks Si521xx PCIe clock generators. Supported models
are Si52144/Si52146/Si52147, tested model is Si52144. It should be possible
to add Si5213x series as well.

Signed-off-by: Marek Vasut <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[[email protected]: Make clk_ops const]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: Add Sunplus SP7021 clock driver

Add clock driver for Sunplus SP7021 SoC.

Signed-off-by: Qin Jian <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

clk: Add Sunplus SP7021 clock driver

Add clock driver for Sunplus SP7021 SoC.

Signed-off-by: Qin Jian <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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clk: HI655X: select REGMAP instead of depending on it

REGMAP is a hidden (not user visible) symbol. Users cannot set it
directly thru "make *config", so drivers should select it instead of
depending

clk: HI655X: select REGMAP instead of depending on it

REGMAP is a hidden (not user visible) symbol. Users cannot set it
directly thru "make *config", so drivers should select it instead of
depending on it if they need it.

Consistently using "select" or "depends on" can also help reduce
Kconfig circular dependency issues.

Therefore, change the use of "depends on REGMAP" to "select REGMAP".

Fixes: 3a49afb84ca0 ("clk: enable hi655x common clk automatically")
Signed-off-by: Randy Dunlap <[email protected]>
Cc: Riku Voipio <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: [email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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drivers/clk: Remove "select SRCU"

Now that the SRCU Kconfig option is unconditionally selected, there is
no longer any point in selecting it. Therefore, remove the "select SRCU"
Kconfig statements.

drivers/clk: Remove "select SRCU"

Now that the SRCU Kconfig option is unconditionally selected, there is
no longer any point in selecting it. Therefore, remove the "select SRCU"
Kconfig statements.

Signed-off-by: Paul E. McKenney <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

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