|
Revision tags: v6.15, v6.15-rc7, v6.15-rc6, v6.15-rc5, v6.15-rc4, v6.15-rc3, v6.15-rc2, v6.15-rc1, v6.14, v6.14-rc7, v6.14-rc6, v6.14-rc5, v6.14-rc4, v6.14-rc3, v6.14-rc2, v6.14-rc1, v6.13, v6.13-rc7, v6.13-rc6, v6.13-rc5, v6.13-rc4, v6.13-rc3, v6.13-rc2, v6.13-rc1, v6.12, v6.12-rc7, v6.12-rc6, v6.12-rc5, v6.12-rc4, v6.12-rc3, v6.12-rc2, v6.12-rc1, v6.11, v6.11-rc7, v6.11-rc6, v6.11-rc5, v6.11-rc4, v6.11-rc3, v6.11-rc2, v6.11-rc1, v6.10, v6.10-rc7, v6.10-rc6, v6.10-rc5, v6.10-rc4, v6.10-rc3, v6.10-rc2, v6.10-rc1, v6.9, v6.9-rc7, v6.9-rc6, v6.9-rc5, v6.9-rc4 |
|
| #
6b0856ee |
| 10-Apr-2024 |
Samuel Holland <[email protected]> |
cache: sifive_ccache: Silence unused variable warning
With W=1 and CONFIG_RISCV_NONSTANDARD_CACHE_OPS=n, GCC warns:
drivers/cache/sifive_ccache.c: In function 'sifive_ccache_init':
drivers/cache/si
cache: sifive_ccache: Silence unused variable warning
With W=1 and CONFIG_RISCV_NONSTANDARD_CACHE_OPS=n, GCC warns:
drivers/cache/sifive_ccache.c: In function 'sifive_ccache_init':
drivers/cache/sifive_ccache.c:293:23: warning: variable 'quirks' set but not used [-Wunused-but-set-variable]
293 | unsigned long quirks;
| ^~~~~~
This is expected, since QUIRK_NONSTANDARD_CACHE_OPS is the only quirk
still handled in this function.
Fixes: c90847bcbfb6 ("cache: sifive_ccache: Partially convert to a platform driver")
Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
show more ...
|
|
Revision tags: v6.9-rc3, v6.9-rc2 |
|
| #
c90847bc |
| 27-Mar-2024 |
Samuel Holland <[email protected]> |
cache: sifive_ccache: Partially convert to a platform driver
Commit 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a
platform driver") broke ccache initialization because the PLIC IRQ
cache: sifive_ccache: Partially convert to a platform driver
Commit 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a
platform driver") broke ccache initialization because the PLIC IRQ
domain is no longer available during an arch_initcall:
[ 0.087229] irq: no irq domain found for interrupt-controller@c000000 !
[ 0.087255] CCACHE: Could not request IRQ 0
Fix this by moving the IRQ handling code to a platform driver.
Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver")
Signed-off-by: Samuel Holland <[email protected]>
Tested-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
show more ...
|
|
Revision tags: v6.9-rc1, v6.8, v6.8-rc7, v6.8-rc6, v6.8-rc5, v6.8-rc4, v6.8-rc3, v6.8-rc2, v6.8-rc1, v6.7, v6.7-rc8, v6.7-rc7, v6.7-rc6, v6.7-rc5, v6.7-rc4, v6.7-rc3, v6.7-rc2, v6.7-rc1 |
|
| #
0d5701dc |
| 31-Oct-2023 |
Emil Renner Berthing <[email protected]> |
soc: sifive: ccache: Add StarFive JH7100 support
This adds support for the StarFive JH7100 SoC which also features this
SiFive cache controller.
The JH7100 has non-coherent DMAs but predate the sta
soc: sifive: ccache: Add StarFive JH7100 support
This adds support for the StarFive JH7100 SoC which also features this
SiFive cache controller.
The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom
exension, so instead we need to use this cache controller for
non-standard cache management operations.
Unfortunately the interrupt for uncorrected data is broken on the JH7100
and fires continuously, so add a quirk to not register a handler for it.
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
show more ...
|
|
Revision tags: v6.6, v6.6-rc7, v6.6-rc6 |
|
| #
971f128b |
| 12-Oct-2023 |
Conor Dooley <[email protected]> |
soc: sifive: shunt ccache driver to drivers/cache
Move the ccache driver over to drivers/cache, out of the drivers/soc
dumping ground, to this new collection point for cache controller
drivers.
Rev
soc: sifive: shunt ccache driver to drivers/cache
Move the ccache driver over to drivers/cache, out of the drivers/soc
dumping ground, to this new collection point for cache controller
drivers.
Reviewed-by: Samuel Holland <[email protected]>
Tested-by: Samuel Holland <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
show more ...
|