History log of /linux-6.15/drivers/base/regmap/regcache.c (Results 1 – 25 of 131)
Revision (<<< Hide revision tags) (Show revision tags >>>) Date Author Comments
Revision tags: v6.15, v6.15-rc7, v6.15-rc6, v6.15-rc5, v6.15-rc4, v6.15-rc3, v6.15-rc2, v6.15-rc1, v6.14, v6.14-rc7, v6.14-rc6, v6.14-rc5, v6.14-rc4
# fd80df35 17-Feb-2025 Charles Keepax <[email protected]>

regcache: Add support for sorting defaults arrays

The defaults array in regcache must be sorted into ascending register
address order, because binary search is used to locate values in
the array. Ad

regcache: Add support for sorting defaults arrays

The defaults array in regcache must be sorted into ascending register
address order, because binary search is used to locate values in
the array. Add a helper to sort the register defaults array which
can be useful for systems that dynamically create a defaults array
based on external information.

Signed-off-by: Charles Keepax <[email protected]>
Reviewed-by: Pierre-Louis Bossart <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v6.14-rc3, v6.14-rc2, v6.14-rc1, v6.13, v6.13-rc7, v6.13-rc6, v6.13-rc5, v6.13-rc4, v6.13-rc3, v6.13-rc2, v6.13-rc1
# 4a3aafe0 21-Nov-2024 Andy Shevchenko <[email protected]>

regmap: cache: Use BITS_TO_BYTES()

BITS_TO_BYTES() is the existing macro which takes care about full
bytes that may fully hold the given amount of bits. Use it.

Signed-off-by: Andy Shevchenko <andr

regmap: cache: Use BITS_TO_BYTES()

BITS_TO_BYTES() is the existing macro which takes care about full
bytes that may fully hold the given amount of bits. Use it.

Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v6.12, v6.12-rc7, v6.12-rc6, v6.12-rc5, v6.12-rc4, v6.12-rc3, v6.12-rc2, v6.12-rc1, v6.11, v6.11-rc7, v6.11-rc6, v6.11-rc5
# fd4ebc07 22-Aug-2024 Mark Brown <[email protected]>

regmap: Hold the regmap lock when allocating and freeing the cache

For the benefit of the maple tree's lockdep checking hold the lock while
creating and exiting the cache.

Signed-off-by: Mark Brown

regmap: Hold the regmap lock when allocating and freeing the cache

For the benefit of the maple tree's lockdep checking hold the lock while
creating and exiting the cache.

Signed-off-by: Mark Brown <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v6.11-rc4, v6.11-rc3, v6.11-rc2, v6.11-rc1, v6.10, v6.10-rc7, v6.10-rc6, v6.10-rc5, v6.10-rc4, v6.10-rc3
# f755d695 06-Jun-2024 Andy Shevchenko <[email protected]>

regmap: cache: Switch to use kmemdup_array()

Let the kememdup_array() take care about multiplication and possible
overflows.

Signed-off-by: Andy Shevchenko <[email protected]>
Link:

regmap: cache: Switch to use kmemdup_array()

Let the kememdup_array() take care about multiplication and possible
overflows.

Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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# 354662dc 06-Jun-2024 Andy Shevchenko <[email protected]>

regmap: cache: Use correct type of the rb_for_each() parameter

Compiler is not happy:

regcache.c:410:9: warning: Using plain integer as NULL pointer

Replace integer 0 by NULL.

Signed-off-by: An

regmap: cache: Use correct type of the rb_for_each() parameter

Compiler is not happy:

regcache.c:410:9: warning: Using plain integer as NULL pointer

Replace integer 0 by NULL.

Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v6.10-rc2, v6.10-rc1, v6.9, v6.9-rc7, v6.9-rc6, v6.9-rc5, v6.9-rc4, v6.9-rc3, v6.9-rc2, v6.9-rc1, v6.8, v6.8-rc7, v6.8-rc6, v6.8-rc5, v6.8-rc4, v6.8-rc3, v6.8-rc2
# 0ec74ad3 26-Jan-2024 Jan Dakinevich <[email protected]>

regmap: rework ->max_register handling

When regmap consists of single register, 'regmap' subsystem is unable to
understand whether ->max_register is set or not, because in both cases it
is equal to

regmap: rework ->max_register handling

When regmap consists of single register, 'regmap' subsystem is unable to
understand whether ->max_register is set or not, because in both cases it
is equal to zero. It leads to that the logic based on value of
->max_register doesn't work. For example using of REGCACHE_FLAT fails.

This patch introduces an extra parameter to regmap config, indicating
that zero value in ->max_register is authentic.

Signed-off-by: Jan Dakinevich <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v6.8-rc1, v6.7, v6.7-rc8, v6.7-rc7, v6.7-rc6, v6.7-rc5
# fea88064 03-Dec-2023 Matthias Reichl <[email protected]>

regmap: fix bogus error on regcache_sync success

Since commit 0ec7731655de ("regmap: Ensure range selector registers
are updated after cache sync") opening pcm512x based soundcards fail
with EINVAL

regmap: fix bogus error on regcache_sync success

Since commit 0ec7731655de ("regmap: Ensure range selector registers
are updated after cache sync") opening pcm512x based soundcards fail
with EINVAL and dmesg shows sync cache and pm_runtime_get errors:

[ 228.794676] pcm512x 1-004c: Failed to sync cache: -22
[ 228.794740] pcm512x 1-004c: ASoC: error at snd_soc_pcm_component_pm_runtime_get on pcm512x.1-004c: -22

This is caused by the cache check result leaking out into the
regcache_sync return value.

Fix this by making the check local-only, as the comment above the
regcache_read call states a non-zero return value means there's
nothing to do so the return value should not be altered.

Fixes: 0ec7731655de ("regmap: Ensure range selector registers are updated after cache sync")
Cc: [email protected]
Signed-off-by: Matthias Reichl <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v6.7-rc4, v6.7-rc3, v6.7-rc2, v6.7-rc1, v6.6
# 0ec77316 26-Oct-2023 Mark Brown <[email protected]>

regmap: Ensure range selector registers are updated after cache sync

When we sync the register cache we do so with the cache bypassed in order
to avoid overhead from writing the synced values back i

regmap: Ensure range selector registers are updated after cache sync

When we sync the register cache we do so with the cache bypassed in order
to avoid overhead from writing the synced values back into the cache. If
the regmap has ranges and the selector register for those ranges is in a
register which is cached this has the unfortunate side effect of meaning
that the physical and cached copies of the selector register can be out of
sync after a cache sync. The cache will have whatever the selector was when
the sync started and the hardware will have the selector for the register
that was synced last.

Fix this by rewriting all cached selector registers after every sync,
ensuring that the hardware and cache have the same content. This will
result in extra writes that wouldn't otherwise be needed but is simple
so hopefully robust. We don't read from the hardware since not all
devices have physical read support.

Given that nobody noticed this until now it is likely that we are rarely if
ever hitting this case.

Reported-by: Hector Martin <[email protected]>
Cc: [email protected]
Signed-off-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v6.6-rc7, v6.6-rc6, v6.6-rc5, v6.6-rc4, v6.6-rc3, v6.6-rc2, v6.6-rc1, v6.5, v6.5-rc7, v6.5-rc6, v6.5-rc5, v6.5-rc4, v6.5-rc3
# b460a522 18-Jul-2023 Mark Brown <[email protected]>

regcache: Push async I/O request down into the rbtree cache

Currently the regcache core unconditionally enables async I/O for all cache
types, causing problems for the maple tree cache which dynamic

regcache: Push async I/O request down into the rbtree cache

Currently the regcache core unconditionally enables async I/O for all cache
types, causing problems for the maple tree cache which dynamically allocates
the buffers used to write registers to the device since async requires the
buffers to be kept around until the I/O has been completed.

This use of async I/O is mainly for the rbtree cache which stores data in
a format directly usable for regmap_raw_write(), though there is a special
case for single register writes which would also have allowed it to be used
with the flat cache. It is a bit of a landmine for other caches since it
implicitly converts sync operations to async, and with modern hardware it
is not clear that async I/O is actually a performance win as shown by the
performance work David Jander did with SPI. In multi core systems the cost
of managing concurrency ends up swamping the performance benefit and almost
all modern systems are multi core.

Address this by pushing the enablement of async I/O down into the rbtree
cache where it is actively used, avoiding surprises for other cache
implementations.

Reported-by: Charles Keepax <[email protected]>
Fixes: bfa0b38c1483 ("regmap: maple: Implement block sync for the maple tree cache")
Reviewed-by: Charles Keepax <[email protected]>
Tested-by: Charles Keepax <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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# 78908f45 17-Jul-2023 Mark Brown <[email protected]>

regmap: Let users check if a register is cached

The HDA driver has a use case for checking if a register is cached which
it bodges in awkwardly and unclearly. Provide an API which allows it to
direc

regmap: Let users check if a register is cached

The HDA driver has a use case for checking if a register is cached which
it bodges in awkwardly and unclearly. Provide an API which allows it to
directly do what it's trying to do.

Reviewed-by: Takashi Iwai <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v6.5-rc2, v6.5-rc1, v6.4
# 039fd2e4 22-Jun-2023 Andy Shevchenko <[email protected]>

regmap: cache: Revert "Add 64-bit mode support"

There is no support for 64-bit data size in regmap, so
there is no point to have it in regmap cache.

This reverts commit 8b7663de6e2bfe3c40e1846e1c46

regmap: cache: Revert "Add 64-bit mode support"

There is no support for 64-bit data size in regmap, so
there is no point to have it in regmap cache.

This reverts commit 8b7663de6e2bfe3c40e1846e1c4625f33d138757.

Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v6.4-rc7
# 44e46572 13-Jun-2023 Takashi Iwai <[email protected]>

regmap: regcache: Don't sync read-only registers

regcache_maple_sync() tries to sync all cached values no matter
whether it's writable or not. OTOH, regache_sync_val() does care the
wrtability and

regmap: regcache: Don't sync read-only registers

regcache_maple_sync() tries to sync all cached values no matter
whether it's writable or not. OTOH, regache_sync_val() does care the
wrtability and returns -EIO for a read-only register. This results in
an error message like:
snd_hda_codec_realtek hdaudioC0D0: Unable to sync register 0x2f0009. -5
and the sync loop is aborted incompletely.

This patch adds the writable register check to regcache_sync_val() for
addressing the bug above.

Note that, although we may add the check in the caller side
(regcache_maple_sync()), here we put in regcache_sync_val(), so that a
similar case like this can be avoided in future.

Fixes: f033c26de5a5 ("regmap: Add maple tree based register cache")
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Takashi Iwai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v6.4-rc6
# d32758ac 10-Jun-2023 Mark Brown <[email protected]>

regmap: Don't check for changes in regcache_set_val()

The only user of regcache_set_val() ignores the return value so we may as
well not bother checking if the value we are trying to set is the same

regmap: Don't check for changes in regcache_set_val()

The only user of regcache_set_val() ignores the return value so we may as
well not bother checking if the value we are trying to set is the same as
the value already stored.

Signed-off-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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# bfa0b38c 11-Jun-2023 Mark Brown <[email protected]>

regmap: maple: Implement block sync for the maple tree cache

For register maps where we can write multiple values in a single bus
operation it is generally much faster to do so. Improve the performa

regmap: maple: Implement block sync for the maple tree cache

For register maps where we can write multiple values in a single bus
operation it is generally much faster to do so. Improve the performance of
maple tree cache syncs on such devices by identifying blocks of adjacent
registers that need to be written out and combining them into a single
operation.

Combining writes does mean that we need to allocate a scratch buffer and
format the data into it but it is expected that for most cases where caches
are in use the cost of I/O will be much greater than the cost of doing the
allocation and format.

Signed-off-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v6.4-rc5, v6.4-rc4, v6.4-rc3, v6.4-rc2, v6.4-rc1, v6.3, v6.3-rc7, v6.3-rc6, v6.3-rc5
# f033c26d 30-Mar-2023 Mark Brown <[email protected]>

regmap: Add maple tree based register cache

The current state of the art for sparse register maps is the
rbtree cache. This works well for most applications but isn't
always ideal for sparser regis

regmap: Add maple tree based register cache

The current state of the art for sparse register maps is the
rbtree cache. This works well for most applications but isn't
always ideal for sparser register maps since the rbtree can get
deep, requiring a lot of walking. Fortunately the kernel has a
data structure intended to address this very problem, the maple
tree. Provide an initial implementation of a register cache
based on the maple tree to start taking advantage of it.

The entries stored in the maple tree are arrays of register
values, with the maple tree keys holding the register addresses.
We store data in host native format rather than device native
format as we do for rbtree, this will be a benefit for devices
where we don't marshal data within regmap and simplifies the code
but will result in additional CPU overhead when syncing the cache
on devices where we do marshal data in regmap.

This should work well for a lot of devices, though there's some
additional areas that could be looked at such as caching the
last accessed entry like we do for rbtree and trying to minimise
the maple tree level locking. We should also use bulk writes
rather than single register writes when resyncing the cache where
possible, even if we don't store in device native format.

Very small register maps may continue to to better with rbtree
longer term.

Signed-off-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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# 05933e2d 30-Mar-2023 Mark Brown <[email protected]>

regmap: Factor out single value register syncing

In order to support sparse caches that don't store data in raw format
factor out the parts of the raw block sync implementation that deal with
writin

regmap: Factor out single value register syncing

In order to support sparse caches that don't store data in raw format
factor out the parts of the raw block sync implementation that deal with
writing a single register via _regmap_write().

Signed-off-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v6.3-rc4
# 1e2bae6a 24-Mar-2023 Mark Brown <[email protected]>

regmap: Removed compressed cache support

The compressed register cache support has assumptions that make it hard to
cover in testing, mainly that it requires raw registers defaults be
provided. Rath

regmap: Removed compressed cache support

The compressed register cache support has assumptions that make it hard to
cover in testing, mainly that it requires raw registers defaults be
provided. Rather than either address these assumptions or leave it untested
by the forthcoming KUnit tests let's remove it, the use case is quite thin
and there are no current users.

Signed-off-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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# 2d38e861 24-Mar-2023 Mark Brown <[email protected]>

regmap: Clarify error for unknown cache types

The error message printed when we fail to locate the cache type the map
requested says it can't find a compress type rather than a cache type,
fix that.

regmap: Clarify error for unknown cache types

The error message printed when we fail to locate the cache type the map
requested says it can't find a compress type rather than a cache type,
fix that. Since the compressed type is the only one currently compiled
conditionally it's likely to be the missing type but that might not always
be true and is still unclear.

Signed-off-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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# 2c89db8f 25-Mar-2023 Mark Brown <[email protected]>

regmap: Handle sparse caches in the default sync

If there is no cache entry available we will get -ENOENT from the cache
implementation, handle this gracefully and skip rather than treating it as
an

regmap: Handle sparse caches in the default sync

If there is no cache entry available we will get -ENOENT from the cache
implementation, handle this gracefully and skip rather than treating it as
an error.

Signed-off-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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Revision tags: v6.3-rc3
# 24d80fde 13-Mar-2023 Alexander Stein <[email protected]>

regmap: cache: Silence checkpatch warning

checkpatch.pl warned:
WARNING: ENOSYS means 'invalid syscall nr' and nothing else
Align the return value to regcache_drop_region().

Signed-off-by: Alexande

regmap: cache: Silence checkpatch warning

checkpatch.pl warned:
WARNING: ENOSYS means 'invalid syscall nr' and nothing else
Align the return value to regcache_drop_region().

Signed-off-by: Alexander Stein <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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# fd883d79 13-Mar-2023 Alexander Stein <[email protected]>

regmap: cache: Return error in cache sync operations for REGCACHE_NONE

There is no sense in doing a cache sync on REGCACHE_NONE regmaps.
Instead of panicking the kernel due to missing cache_ops, ret

regmap: cache: Return error in cache sync operations for REGCACHE_NONE

There is no sense in doing a cache sync on REGCACHE_NONE regmaps.
Instead of panicking the kernel due to missing cache_ops, return an error
to client driver.

Signed-off-by: Alexander Stein <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v6.3-rc2, v6.3-rc1, v6.2, v6.2-rc8, v6.2-rc7, v6.2-rc6, v6.2-rc5, v6.2-rc4, v6.2-rc3, v6.2-rc2, v6.2-rc1, v6.1, v6.1-rc8, v6.1-rc7, v6.1-rc6, v6.1-rc5, v6.1-rc4, v6.1-rc3, v6.1-rc2, v6.1-rc1, v6.0, v6.0-rc7, v6.0-rc6, v6.0-rc5, v6.0-rc4, v6.0-rc3, v6.0-rc2, v6.0-rc1, v5.19, v5.19-rc8, v5.19-rc7, v5.19-rc6, v5.19-rc5
# a5201d42 29-Jun-2022 Schspa Shi <[email protected]>

regmap: cache: Add extra parameter check in regcache_init

When num_reg_defaults > 0 but reg_defaults is NULL, there will be a
NULL pointer exception.

Current code has no such usage, but as addition

regmap: cache: Add extra parameter check in regcache_init

When num_reg_defaults > 0 but reg_defaults is NULL, there will be a
NULL pointer exception.

Current code has no such usage, but as additional hardening, also
check this to prevent any chance of crashing.

Signed-off-by: Schspa Shi <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v5.19-rc4
# 3d0afe9c 22-Jun-2022 Mark Brown <[email protected]>

regmap: Don't warn about cache only mode for devices with no cache

For devices with no cache it can make sense to use cache only mode as a
mechanism for trapping writes to hardware which is inaccess

regmap: Don't warn about cache only mode for devices with no cache

For devices with no cache it can make sense to use cache only mode as a
mechanism for trapping writes to hardware which is inaccessible but since
no cache is equivalent to cache bypass we force such devices into bypass
mode. This means that our check that bypass and cache only mode aren't both
enabled simultanously is less sensible for devices without a cache so relax
it.

Signed-off-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v5.19-rc3, v5.19-rc2, v5.19-rc1
# 72607f37 04-Jun-2022 Xiang wangx <[email protected]>

regmap: cache: Fix syntax errors in comments

Delete the redundant word 'the'.

Signed-off-by: Xiang wangx <[email protected]>
Link: https://lore.kernel.org/r/20220604041603.9697-1-wangxiang@cdjrl

regmap: cache: Fix syntax errors in comments

Delete the redundant word 'the'.

Signed-off-by: Xiang wangx <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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Revision tags: v5.18, v5.18-rc7, v5.18-rc6, v5.18-rc5
# d6409475 25-Apr-2022 Jeongtae Park <[email protected]>

regmap: cache: set max_register with reg_stride

Current logic does not consider multi-stride cases,
the max_register have to calculate with reg_stride
because it is a kind of address range.

Signed-

regmap: cache: set max_register with reg_stride

Current logic does not consider multi-stride cases,
the max_register have to calculate with reg_stride
because it is a kind of address range.

Signed-off-by: Jeongtae Park <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

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