sh: remove sh5 support

sh5 never became a product and has probably never really worked.

Remove it by recursively deleting all associated Kconfig options
and all corresponding files.

Reviewed-by: G

sh: remove sh5 support

sh5 never became a product and has probably never really worked.

Remove it by recursively deleting all associated Kconfig options
and all corresponding files.

Reviewed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
Signed-off-by: Rich Felker <[email protected]>

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sh: cpu: convert to SPDX identifiers

Update license to use SPDX-License-Identifier instead of verbose license
text.

Link: http://lkml.kernel.org/r/[email protected]
Sig

sh: cpu: convert to SPDX identifiers

Update license to use SPDX-License-Identifier instead of verbose license
text.

Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Kuninori Morimoto <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Cc: Rich Felker <[email protected]>
Cc: Yoshinori Sato <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>

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Replace <asm/uaccess.h> with <linux/uaccess.h> globally

This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*<asm/uaccess.h>'
sed -i -e "s!$PA

Replace <asm/uaccess.h> with <linux/uaccess.h> globally

This was entirely automated, using the script by Al:

PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*<asm/uaccess.h>'
sed -i -e "s!$PATT!#include <linux/uaccess.h>!" \
$(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h)

to do the replacement at the end of the merge window.

Requested-by: Al Viro <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>

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sh: add support for J-Core J2 processor

At the CPU/ISA level, the J2 is compatible with SH-2, and thus the
changes to add J2 support build on existing SH-2 support. However, J2
does not duplicate th

sh: add support for J-Core J2 processor

At the CPU/ISA level, the J2 is compatible with SH-2, and thus the
changes to add J2 support build on existing SH-2 support. However, J2
does not duplicate the memory-mapped SH-2 features like the cache
interface. Instead, the cache interfaces is described in the device
tree, and new code is added to be able to access the flat device tree
at early boot before it is unflattened.

Support is also added for receiving interrupts on trap numbers in the
range 16 to 31, since the J-Core aic1 interrupt controller generates
these traps. This range was unused but nominally for hardware
exceptions on SH-2, and a few values in this range were used for
exceptions on SH-2A, but SH-2A has its own version of the relevant
code.

No individual cpu subtypes are added for J2 since the intent moving
forward is to represent SoCs with device tree rather than as
hard-coded subtypes in the kernel. The CPU_SUBTYPE_J2 Kconfig item
exists only to fit into the existing cpu selection mechanism until it
is overhauled.

Signed-off-by: Rich Felker <[email protected]>

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sh: disable aliased page logic on NOMMU models

SH3/4 (with MMU) have a virtually indexed cache, requiring explicit
work to avoid consistency problems arising from having the same
physical address ra

sh: disable aliased page logic on NOMMU models

SH3/4 (with MMU) have a virtually indexed cache, requiring explicit
work to avoid consistency problems arising from having the same
physical address range cached in multiple cache lines. This is
unneeded for the NOMMU case, and some of the resulting code paths
(kmap_coherent) don't work. SH2 only avoided this problem by having a
4-way associative cache with way size equal to the page size (4k),
yielding no cache index bits outside of the page offset and thus no
aliases.

Signed-off-by: Rich Felker <[email protected]>

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sh: prefix sh-specific "CCR" and "CCR2" by "SH_"

Commit bcf24e1daa94 ("mmc: omap_hsmmc: use the generic config for
omap2plus devices"), enabled the build for other platforms for compile
testing.

sh

sh: prefix sh-specific "CCR" and "CCR2" by "SH_"

Commit bcf24e1daa94 ("mmc: omap_hsmmc: use the generic config for
omap2plus devices"), enabled the build for other platforms for compile
testing.

sh-allmodconfig now fails with:

include/linux/omap-dma.h:171:8: error: expected identifier before numeric constant
make[4]: *** [drivers/mmc/host/omap_hsmmc.o] Error 1

This happens because SuperH #defines "CCR", which is one of the enum
values in include/linux/omap-dma.h. There's a similar issue with "CCR2"
on sh2a.

As "CCR" and "CCR2" are too generic names for global #defines, prefix
them with "SH_" to fix this.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>

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sh: delete __cpuinit usage from all sh files

The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost an

sh: delete __cpuinit usage from all sh files

The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.

After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.

Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
are flagged as __cpuinit -- so if we remove the __cpuinit from
arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
content into no-ops as early as possible, since that will get rid
of these warnings. In any case, they are temporary and harmless.

This removes all the arch/sh uses of the __cpuinit macros from
all C files. Currently sh does not have any __CPUINIT used in
assembly files.

[1] https://lkml.org/lkml/2013/5/20/589

Cc: Paul Mundt <[email protected]>
Cc: [email protected]
Signed-off-by: Paul Gortmaker <[email protected]>

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Disintegrate asm/system.h for SH

Disintegrate asm/system.h for SH.

Signed-off-by: David Howells <[email protected]>
cc: [email protected]

sh: Expose physical addressing mode through cpuinfo.

CPUs can be in either the legacy 29-bit or 32-bit physical addressing
modes. This follows the x86 approach of tracking the phys bits in cpuinfo
a

sh: Expose physical addressing mode through cpuinfo.

CPUs can be in either the legacy 29-bit or 32-bit physical addressing
modes. This follows the x86 approach of tracking the phys bits in cpuinfo
and exposing it to userspace through procfs.

This change was requested to permit kexec-tools to detect the physical
addressing mode in order to determine the appropriate address mangling.

Signed-off-by: Paul Mundt <[email protected]>

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sh: __cpuinit annotate the CPU init path.

All of the regular CPU init path needs to be __cpuinit annotated for CPU
hotplug.

Signed-off-by: Paul Mundt <[email protected]>

sh: Tidy CPU probing and fixup section annotations.

This does a detect_cpu_and_cache_system() -> cpu_probe() rename, tidies
up the unused return value, and stuffs it under __cpuinit in preparation
f

sh: Tidy CPU probing and fixup section annotations.

This does a detect_cpu_and_cache_system() -> cpu_probe() rename, tidies
up the unused return value, and stuffs it under __cpuinit in preparation
for CPU hotplug.

Signed-off-by: Paul Mundt <[email protected]>

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sh: Setup boot CPU VBR early to enable early page faults.

vmemmap and the vmsplit code amongst others need to be able to take page
faults much earlier than trap_init() time, so move this in to the e

sh: Setup boot CPU VBR early to enable early page faults.

vmemmap and the vmsplit code amongst others need to be able to take page
faults much earlier than trap_init() time, so move this in to the early
CPU initialization. VBR setup for secondary CPUs is already handled
through start_secondary(), so we only need to do this for the boot CPU.

Signed-off-by: Paul Mundt <[email protected]>

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sh: Mass ctrl_in/outX to __raw_read/writeX conversion.

The old ctrl in/out routines are non-portable and unsuitable for
cross-platform use. While drivers/sh has already been sanitized, there
is stil

sh: Mass ctrl_in/outX to __raw_read/writeX conversion.

The old ctrl in/out routines are non-portable and unsuitable for
cross-platform use. While drivers/sh has already been sanitized, there
is still quite a lot of code that is not. This converts the arch/sh/ bits
over, which permits us to flag the routines as deprecated whilst still
building with -Werror for the architecture code, and to ensure that
future users are not added.

Signed-off-by: Paul Mundt <[email protected]>

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sh: Kill off the special uncached section and fixmap.

Now that cached_to_uncached works as advertized in 32-bit mode and we're
never going to be able to map < 16MB anyways, there's no need for the
s

sh: Kill off the special uncached section and fixmap.

Now that cached_to_uncached works as advertized in 32-bit mode and we're
never going to be able to map < 16MB anyways, there's no need for the
special uncached section. Kill it off.

Signed-off-by: Paul Mundt <[email protected]>

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sh: Move over to dynamically allocated FPU context.

This follows the x86 xstate changes and implements a task_xstate slab
cache that is dynamically sized to match one of hard FP/soft FP/FPU-less.

T

sh: Move over to dynamically allocated FPU context.

This follows the x86 xstate changes and implements a task_xstate slab
cache that is dynamically sized to match one of hard FP/soft FP/FPU-less.

This also tidies up and consolidates some of the SH-2A/SH-4 FPU
fragmentation. Now fpu state restorers are commonly defined, with the
init_fpu()/fpu_init() mess reworked to follow the x86 convention.
The fpu_init() register initialization has been replaced by xstate setup
followed by writing out to hardware via the standard restore path.

As init_fpu() now performs a slab allocation a secondary lighterweight
restorer is also introduced for the context switch.

In the future the DSP state will be rolled in here, too.

More work remains for math emulation and the SH-5 FPU, which presently
uses its own special (UP-only) interfaces.

Signed-off-by: Paul Mundt <[email protected]>

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sh: Kill off dead UBC headers.

Nothing is using these now, so kill them all off.

Signed-off-by: Paul Mundt <[email protected]>

sh: Make associative cache writes fatal on all SH-4A parts.

Now that associative cache writes are no longer needed by the SH-4/SH-4A
cache flush code, associative write support can be explicitly dis

sh: Make associative cache writes fatal on all SH-4A parts.

Now that associative cache writes are no longer needed by the SH-4/SH-4A
cache flush code, associative write support can be explicitly disabled
for all SH-4A parts. This makes any associative write throw an exception,
as this behaviour can not be assumed to exist on future parts.

Signed-off-by: Paul Mundt <[email protected]>

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sh: Minor optimisations to FPU handling

A number of small optimisations to FPU handling, in particular:

- move the task USEDFPU flag from the thread_info flags field (which
is accessed asynchro

sh: Minor optimisations to FPU handling

A number of small optimisations to FPU handling, in particular:

- move the task USEDFPU flag from the thread_info flags field (which
is accessed asynchronously to the thread) to a new status field,
which is only accessed by the thread itself. This allows locking to
be removed in most cases, or can be reduced to a preempt_lock().
This mimics the i386 behaviour.

- move the modification of regs->sr and thread_info->status flags out
of save_fpu() to __unlazy_fpu(). This gives the compiler a better
chance to optimise things, as well as making save_fpu() symmetrical
with restore_fpu() and init_fpu().

- implement prepare_to_copy(), so that when creating a thread, we can
unlazy the FPU prior to copying the thread data structures.

Also make sure that the FPU is disabled while in the kernel, in
particular while booting, and for newly created kernel threads,

In a very artificial benchmark, the execution time for 2500000
context switches was reduced from 50 to 45 seconds.

Signed-off-by: Stuart Menefy <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>

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sh: Kill off legacy UBC wakeup cruft.

This code was added for some ancient SH-4 solution engines with peculiar
boot ROMs that did silly things to the UBC MSTP bits. None of these have
been in the wi

sh: Kill off legacy UBC wakeup cruft.

This code was added for some ancient SH-4 solution engines with peculiar
boot ROMs that did silly things to the UBC MSTP bits. None of these have
been in the wild for years, and these days the clock framework wraps up
the MSTP bits, meaning that the UBC code is one of the few interfaces
that is stomping MSTP bits underneath the clock framework. At this point
the risks far outweigh any benefit this code provided, so just kill it
off.

Signed-off-by: Paul Mundt <[email protected]>

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sh: rework nommu for generic cache.c use.

This does a bit of reorganizing for allowing nommu to use the new
and generic cache.c, no functional changes.

Signed-off-by: Paul Mundt <[email protected]

sh: rework nommu for generic cache.c use.

This does a bit of reorganizing for allowing nommu to use the new
and generic cache.c, no functional changes.

Signed-off-by: Paul Mundt <[email protected]>

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sh: delay slot future proofing via EXPMASK on SH-4A parts.

This implements EXPMASK initialization code for SH-4A parts, where it is
possible to disable compat features that will go away in newer cor

sh: delay slot future proofing via EXPMASK on SH-4A parts.

This implements EXPMASK initialization code for SH-4A parts, where it is
possible to disable compat features that will go away in newer cores.
Presently this includes disabling support for non-nop instructions in the
rte delay slot, as well as a sleep instruction being placed in a delay
slot (neither of which the kernel does any longer). As a result of this,
any future offenders will have illegal slot exceptions generated for
them.

Associative writes for the memory-mapped cache array are still left
enabled, until such a point that special cache operations for SH-4A are
provided to move off of the current (and rather dated) SH-4 versions.

Signed-off-by: Paul Mundt <[email protected]>

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sh: add weak l2_cache_init function.

Signed-off-by: Kuninori Morimoto <[email protected]>
Signed-off-by: Paul Mundt <[email protected]>

sh: Move arch_get_unmapped_area() in to arch/sh/mm/mmap.c.

Now that arch/sh/mm/mmap.c exists, move arch_get_unmapped_area() there.
Follows the ARM change.

Signed-off-by: Paul Mundt <lethal@linux-sh

sh: Move arch_get_unmapped_area() in to arch/sh/mm/mmap.c.

Now that arch/sh/mm/mmap.c exists, move arch_get_unmapped_area() there.
Follows the ARM change.

Signed-off-by: Paul Mundt <[email protected]>

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sh: Fix up section mismatches.

Signed-off-by: Paul Mundt <[email protected]>

sh: Encode L1/L2 cache shape in auxvt.

This adds in the L1I/L1D/L2 cache shape support to their respective
entries in the ELF auxvt, based on the Alpha implementation. We use
this on the userspace l

sh: Encode L1/L2 cache shape in auxvt.

This adds in the L1I/L1D/L2 cache shape support to their respective
entries in the ELF auxvt, based on the Alpha implementation. We use
this on the userspace libc side for calculating a tightly packed
SHMLBA amongst other things.

Signed-off-by: Paul Mundt <[email protected]>

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