openrisc: Add missing prototypes for assembly called fnctions

These functions are all called from assembly files so there is no need
for a prototype in a header file, but when compiling with W=1 ena

openrisc: Add missing prototypes for assembly called fnctions

These functions are all called from assembly files so there is no need
for a prototype in a header file, but when compiling with W=1 enabling
-Wmissing-prototypes the compiler warns:

arch/openrisc/kernel/ptrace.c:191:17: error: no previous prototype for 'do_syscall_trace_enter' [-Werror=missing-prototypes]
arch/openrisc/kernel/ptrace.c:210:17: error: no previous prototype for 'do_syscall_trace_leave' [-Werror=missing-prototypes]
arch/openrisc/kernel/signal.c:293:1: error: no previous prototype for 'do_work_pending' [-Werror=missing-prototypes]
arch/openrisc/kernel/signal.c:68:17: error: no previous prototype for '_sys_rt_sigreturn' [-Werror=missing-prototypes]
arch/openrisc/kernel/time.c:111:25: error: no previous prototype for 'timer_interrupt' [-Werror=missing-prototypes]
arch/openrisc/kernel/traps.c:239:17: error: no previous prototype for 'unhandled_exception' [-Werror=missing-prototypes]
arch/openrisc/kernel/traps.c:246:17: error: no previous prototype for 'do_fpe_trap' [-Werror=missing-prototypes]
arch/openrisc/kernel/traps.c:268:17: error: no previous prototype for 'do_trap' [-Werror=missing-prototypes]
arch/openrisc/kernel/traps.c:273:17: error: no previous prototype for 'do_unaligned_access' [-Werror=missing-prototypes]
arch/openrisc/kernel/traps.c:286:17: error: no previous prototype for 'do_bus_fault' [-Werror=missing-prototypes]
arch/openrisc/kernel/traps.c:462:17: error: no previous prototype for 'do_illegal_instruction' [-Werror=missing-prototypes]
arch/openrisc/mm/fault.c:44:17: error: no previous prototype for 'do_page_fault' [-Werror=missing-prototypes]

Since these are not needed in header files, fix these by adding
prototypes to the top of the respective C files.

Reported-by: Arnd Bergmann <[email protected]>
Closes: https://lore.kernel.org/linux-kernel/[email protected]/
Signed-off-by: Stafford Horne <[email protected]>

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openrisc/time: Fix symbol scope warnings

Spare reported the following warnings:
arch/openrisc/kernel/time.c:64:1: warning: symbol 'clockevent_openrisc_timer' was not declared. Should it be stati

openrisc/time: Fix symbol scope warnings

Spare reported the following warnings:
arch/openrisc/kernel/time.c:64:1: warning: symbol 'clockevent_openrisc_timer' was not declared. Should it be static?
arch/openrisc/kernel/time.c:66:6: warning: symbol 'openrisc_clockevent_init' was not declared. Should it be static?

This patch fixes by:

- Add static declaration to clockevent_openrisc_timer as it's used only in
this file.
- Add include for asm/time.h for openrisc_clockevent_init declaration.

Signed-off-by: Stafford Horne <[email protected]>

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openrisc: init: Add support for common clk

When testing the new litex_mmc driver it was found to not work on
OpenRISC due to missing support for common clk. This patch does the
basic initialization

openrisc: init: Add support for common clk

When testing the new litex_mmc driver it was found to not work on
OpenRISC due to missing support for common clk. This patch does the
basic initialization to allow OpenRISC to use the common clk framework.

Signed-off-by: Stafford Horne <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>

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openrisc: time: don't mark comment as kernel-doc

Fix a kernel-doc warning by unmarking the comment as being in
kernel-doc notation.

Fixes this warning:
arch/openrisc/kernel/time.c:137: warning: exp

openrisc: time: don't mark comment as kernel-doc

Fix a kernel-doc warning by unmarking the comment as being in
kernel-doc notation.

Fixes this warning:
arch/openrisc/kernel/time.c:137: warning: expecting prototype for Clocksource(). Prototype was for openrisc_timer_read() instead

Fixes: b731fbbd246e ("OpenRISC: Timekeeping")
Signed-off-by: Randy Dunlap <[email protected]>
Reported-by: kernel test robot <[email protected]>
Cc: Jonas Bonn <[email protected]>
Cc: Stefan Kristiansson <[email protected]>
Cc: Stafford Horne <[email protected]>
Cc: [email protected]
Signed-off-by: Stafford Horne <[email protected]>

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of th

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 3029 file(s).

Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Allison Randal <[email protected]>
Cc: [email protected]
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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openrisc: add tick timer multi-core sync logic

In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main c

openrisc: add tick timer multi-core sync logic

In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu. This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.

This synchronization routine heavily borrows from mips implementation that
does something similar.

Signed-off-by: Stafford Horne <[email protected]>

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openrisc: initial SMP support

This patch introduces the SMP support for the OpenRISC architecture.
The SMP architecture requires cores which have multi-core features which
have been introduced a few

openrisc: initial SMP support

This patch introduces the SMP support for the OpenRISC architecture.
The SMP architecture requires cores which have multi-core features which
have been introduced a few years back including:

- New SPRS SPR_COREID SPR_NUMCORES
- Shadow SPRs
- Atomic Instructions
- Cache Coherency
- A wired in IPI controller

This patch adds all of the SMP specific changes to core infrastructure,
it looks big but it needs to go all together as its hard to split this
one up.

Boot loader spinning of second cpu is not supported yet, it's assumed
that Linux is booted straight after cpu reset.

The bulk of these changes are trivial changes to refactor to use per cpu
data structures throughout. The addition of the smp.c and changes in
time.c are the changes. Some specific notes:

MM changes
----------
The reason why this is created as an array, and not with DEFINE_PER_CPU
is that doing it this way, we'll save a load in the tlb-miss handler
(the load from __per_cpu_offset).

TLB Flush
---------
The SMP implementation of flush_tlb_* works by sending out a
function-call IPI to all the non-local cpus by using the generic
on_each_cpu() function.

Currently, all flush_tlb_* functions will result in a flush_tlb_all(),
which has always been the behaviour in the UP case.

CPU INFO
--------
This creates a per cpu cpuinfo struct and fills it out accordingly for
each activated cpu. show_cpuinfo is also updated to reflect new version
information in later versions of the spec.

SMP API
-------
This imitates the arm64 implementation by having a smp_cross_call
callback that can be set by set_smp_cross_call to initiate an IPI and a
handle_IPI function that is expected to be called from an IPI irqchip
driver.

Signed-off-by: Stefan Kristiansson <[email protected]>
[[email protected]: added cpu stop, checkpatch fixes, wrote commit message]
Signed-off-by: Stafford Horne <[email protected]>

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clocksource: Use a plain u64 instead of cycle_t

There is no point in having an extra type for extra confusion. u64 is
unambiguous.

Conversion was done with the following coccinelle script:

@rem@
@

clocksource: Use a plain u64 instead of cycle_t

There is no point in having an extra type for extra confusion. u64 is
unambiguous.

Conversion was done with the following coccinelle script:

@rem@
@@
-typedef u64 cycle_t;

@fix@
typedef cycle_t;
@@
-cycle_t
+u64

Signed-off-by: Thomas Gleixner <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: John Stultz <[email protected]>

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openrisc/time: Migrate to new 'set-state' interface

Migrate openrisc driver to the new 'set-state' interface provided by
clockevents core, the earlier 'set-mode' interface is marked obsolete
now.

T

openrisc/time: Migrate to new 'set-state' interface

Migrate openrisc driver to the new 'set-state' interface provided by
clockevents core, the earlier 'set-mode' interface is marked obsolete
now.

This also enables us to implement callbacks for new states of clockevent
devices, for example: ONESHOT_STOPPED.

We weren't doing anything in the ->set_mode() callback. So, this patch
doesn't provide any set-state callbacks.

Cc: Jonas Bonn <[email protected]>
Cc: [email protected]
Signed-off-by: Viresh Kumar <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>

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openrisc: Set shortest clock event to 100 ticks

It takes a couple of instructions to actually configure a clock event
so setting an alarm just 1 clock cycle in the future isn't going to work;
doing

openrisc: Set shortest clock event to 100 ticks

It takes a couple of instructions to actually configure a clock event
so setting an alarm just 1 clock cycle in the future isn't going to work;
doing so results in setting an alarm in the "past" in which case the event
won't fire until the timer overflows and rolls back around to the "current
time".

Not quite sure how many clock cycles it actually takes to get through to
actually writing the register, but 100 seems to work reliably.

Use generic helper to set up the clock event while we're at it.

Reported-by: Jan Schulte <[email protected]>
Signed-off-by: Jonas Bonn <[email protected]>

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OpenRISC: Timekeeping

Implements support for the OpenRISC timer which is a 28 bit cycle counter
that can be read out of a special purpose register. This counter is
used as a both a clock event and

OpenRISC: Timekeeping

Implements support for the OpenRISC timer which is a 28 bit cycle counter
that can be read out of a special purpose register. This counter is
used as a both a clock event and clocksource device.

Signed-off-by: Jonas Bonn <[email protected]>
Cc: [email protected]
Reviewed-by: Arnd Bergmann <[email protected]>

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