MIPS: CPS: Introduce struct cluster_boot_config

In preparation for supporting multi-cluster systems, introduce a struct
cluster_boot_config as an extra layer in the boot configuration
maintained by

MIPS: CPS: Introduce struct cluster_boot_config

In preparation for supporting multi-cluster systems, introduce a struct
cluster_boot_config as an extra layer in the boot configuration
maintained by the MIPS Coherent Processing System (CPS) SMP
implementation. For now only one struct cluster_boot_config will be
allocated & we'll simply defererence its core_config field to find the
struct core_boot_config array which can be used to boot as usual.

Signed-off-by: Paul Burton <[email protected]>
Signed-off-by: Dragan Mladjenovic <[email protected]>
Signed-off-by: Aleksandar Rikalo <[email protected]>
Tested-by: Serge Semin <[email protected]>
Tested-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>

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MIPS: cps-vec: Use macros for 64bits access

Some access are 32 bits only while they seems better to be done in
64bis for 64 bit kernel.

This was extract from an initial patch from Jiaxun

Co-develo

MIPS: cps-vec: Use macros for 64bits access

Some access are 32 bits only while they seems better to be done in
64bis for 64 bit kernel.

This was extract from an initial patch from Jiaxun

Co-developed-by: Jiaxun Yang <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>

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MIPS: Allows relocation exception vectors everywhere

Now the exception vector for CPS systems are allocated on-fly
with memblock as well.

It will try to allocate from KSEG1 first, and then try to a

MIPS: Allows relocation exception vectors everywhere

Now the exception vector for CPS systems are allocated on-fly
with memblock as well.

It will try to allocate from KSEG1 first, and then try to allocate
in low 4G if possible.

The main reset vector is now generated by uasm, to avoid tons
of patches to the code. Other vectors are copied to the location
later.

move 64bits fix in an other patch
fix cache issue with mips_cps_core_entry
rewrite the patch to reduce the diff stat
move extern in header
use cache address for copying vector

gc: use the new macro CKSEG[0A1]DDR_OR_64BIT()
Signed-off-by: Jiaxun Yang <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>

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MIPS: smp-cps: Disable coherence setup for unsupported ISA

We don't know how to do coherence setup on ISA before MIPS
Release 1.

As CPS support only servers simulation purpose on those cores,
and s

MIPS: smp-cps: Disable coherence setup for unsupported ISA

We don't know how to do coherence setup on ISA before MIPS
Release 1.

As CPS support only servers simulation purpose on those cores,
and simulators are always coherent, just disable initialization
code and provide user a warning in case coherence is not setup
properly.

Signed-off-by: Jiaxun Yang <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>

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MIPS: smp-cps: Don't rely on CP0_CMGCRBASE

CP0_CMGCRBASE is not always available on CPS enabled system
such as early proAptiv.

For early SMP bring up where we can't safely access memeory,
we patch

MIPS: smp-cps: Don't rely on CP0_CMGCRBASE

CP0_CMGCRBASE is not always available on CPS enabled system
such as early proAptiv.

For early SMP bring up where we can't safely access memeory,
we patch the entry of CPS NMI vector to inject CMGCR address
directly into register during early core bringup.

For VPE bringup as the core is already coherenct at that point
we just read the variable to obtain the address.

Signed-off-by: Jiaxun Yang <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>

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MIPS: CPS: don't create redundant .text.cps-vec section

A number of symbols from arch/mips/kernel/cps-vec.S is explicitly
placed into '.text.cps-vec' section.
There are no direct references to this

MIPS: CPS: don't create redundant .text.cps-vec section

A number of symbols from arch/mips/kernel/cps-vec.S is explicitly
placed into '.text.cps-vec' section.
There are no direct references to this section, so there's no need
to form it. '.balign 0x1000' directive will work anyway.

Moreover, this section was being placed in vmlinux differently
depending on CONFIG_LD_DEAD_CODE_DATA_ELIMINATION:
- with this option enabled, '.text.cps-vec' was being caught
by '.text.[0-9a-zA-Z_]*' from include/asm-generic/vmlinux.lds.h;
- without this option, '.text.cps-vec' was being caught
by discouraging '.text.*' from arch/mips/kernel/vmlinux.lds.S.

'.text.*' should not be used in vmlinux linker scripts at all as it
silently catches any orphan text sections.
So, remove both '.section .text.cps-vec' and '.text.*' from cps-vec.S
and vmlinux.lds.S respectively. As said, this does not affect related
functions alignment:

80116000 T mips_cps_core_entry
80116028 t not_nmi
80116200 T excep_tlbfill
80116280 T excep_xtlbfill
80116300 T excep_cache
80116380 T excep_genex
80116400 T excep_intex
80116480 T excep_ejtag
80116490 T mips_cps_core_init

Signed-off-by: Alexander Lobakin <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of th

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 3029 file(s).

Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Allison Randal <[email protected]>
Cc: [email protected]
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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MIPS: CPS: Fix MIPS_ISA_LEVEL_RAW fallout

Commit 17278a91e04f ("MIPS: CPS: Fix r1 .set mt assembler warning")
added .set MIPS_ISA_LEVEL_RAW to silence warnings about .set mt on r1,
however this can

MIPS: CPS: Fix MIPS_ISA_LEVEL_RAW fallout

Commit 17278a91e04f ("MIPS: CPS: Fix r1 .set mt assembler warning")
added .set MIPS_ISA_LEVEL_RAW to silence warnings about .set mt on r1,
however this can result in a MOVE being encoded as a 64-bit DADDU
instruction on certain version of binutils (e.g. 2.22), and reserved
instruction exceptions at runtime on 32-bit hardware.

Reduce the sizes of the push/pop sections to include only instructions
that are part of the MT ASE or which won't convert to 64-bit
instructions after .set mips64r2/mips64r6.

Reported-by: Greg Ungerer <[email protected]>
Fixes: 17278a91e04f ("MIPS: CPS: Fix r1 .set mt assembler warning")
Signed-off-by: James Hogan <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: [email protected]
Cc: <[email protected]> # 4.15
Tested-by: Greg Ungerer <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/18578/

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MIPS: CPS: Fix r1 .set mt assembler warning

MIPS CPS has a build warning on kernels configured for MIPS32R1 or
MIPS64R1, due to the use of .set mt without a prior .set mips{32,64}r2:

arch/mips/kern

MIPS: CPS: Fix r1 .set mt assembler warning

MIPS CPS has a build warning on kernels configured for MIPS32R1 or
MIPS64R1, due to the use of .set mt without a prior .set mips{32,64}r2:

arch/mips/kernel/cps-vec.S Assembler messages:
arch/mips/kernel/cps-vec.S:238: Warning: the `mt' extension requires MIPS32 revision 2 or greater

Add .set MIPS_ISA_LEVEL_RAW before .set mt to silence the warning.

Fixes: 245a7868d2f2 ("MIPS: smp-cps: rework core/VPE initialisation")
Signed-off-by: James Hogan <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: James Hogan <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17699/
Signed-off-by: Ralf Baechle <[email protected]>

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Update MIPS email addresses

MIPS will soon not be a part of Imagination Technologies, and as such
many @imgtec.com email addresses will no longer be valid. This patch
updates the addresses for those

Update MIPS email addresses

MIPS will soon not be a part of Imagination Technologies, and as such
many @imgtec.com email addresses will no longer be valid. This patch
updates the addresses for those who:

- Have 10 or more patches in mainline authored using an @imgtec.com
email address, or any patches dated within the past year.

- Are still with Imagination but leaving as part of the MIPS business
unit, as determined from an internal email address list.

- Haven't already updated their email address (ie. JamesH) or expressed
a desire to be excluded (ie. Maciej).

- Acked v2 or earlier of this patch, which leaves Deng-Cheng, Matt &
myself.

New addresses are of the form [email protected], and all
verified against an internal email address list. An entry is added to
.mailmap for each person such that get_maintainer.pl will report the new
addresses rather than @imgtec.com addresses which will soon be dead.

Instances of the affected addresses throughout the tree are then
mechanically replaced with the new @mips.com address.

Signed-off-by: Paul Burton <[email protected]>
Cc: Deng-Cheng Zhu <[email protected]>
Cc: Deng-Cheng Zhu <[email protected]>
Acked-by: Dengcheng Zhu <[email protected]>
Cc: Matt Redfearn <[email protected]>
Cc: Matt Redfearn <[email protected]>
Acked-by: Matt Redfearn <[email protected]>
Cc: Andrew Morton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Linus Torvalds <[email protected]>

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Update MIPS email addresses

MIPS will soon not be a part of Imagination Technologies, and as such
many @imgtec.com email addresses will no longer be valid. This patch
updates the addresses for those

Update MIPS email addresses

MIPS will soon not be a part of Imagination Technologies, and as such
many @imgtec.com email addresses will no longer be valid. This patch
updates the addresses for those who:

- Have 10 or more patches in mainline authored using an @imgtec.com
email address, or any patches dated within the past year.

- Are still with Imagination but leaving as part of the MIPS business
unit, as determined from an internal email address list.

- Haven't already updated their email address (ie. JamesH) or expressed
a desire to be excluded (ie. Maciej).

- Acked v2 or earlier of this patch, which leaves Deng-Cheng, Matt &
myself.

New addresses are of the form [email protected], and all
verified against an internal email address list. An entry is added to
.mailmap for each person such that get_maintainer.pl will report the new
addresses rather than @imgtec.com addresses which will soon be dead.

Instances of the affected addresses throughout the tree are then
mechanically replaced with the new @mips.com address.

Signed-off-by: Paul Burton <[email protected]>
Cc: Deng-Cheng Zhu <[email protected]>
Cc: Deng-Cheng Zhu <[email protected]>
Acked-by: Dengcheng Zhu <[email protected]>
Cc: Matt Redfearn <[email protected]>
Cc: Matt Redfearn <[email protected]>
Acked-by: Matt Redfearn <[email protected]>
Cc: Andrew Morton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17540/
Signed-off-by: James Hogan <[email protected]>

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MIPS: CPS: Use GlobalNumber macros rather than magic numbers

We now have definitions for the GlobalNumber register in asm/mipsregs.h,
so use them in place of magic numbers in cps-vec.S.

Signed-off-

MIPS: CPS: Use GlobalNumber macros rather than magic numbers

We now have definitions for the GlobalNumber register in asm/mipsregs.h,
so use them in place of magic numbers in cps-vec.S.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17008/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: CPS: Handle spurious VP starts more gracefully

On pre-r6 systems with the MT ASE the CPS SMP code included checks to
halt the VPE running mips_cps_boot_vpes() if its bit in the struct
core_boo

MIPS: CPS: Handle spurious VP starts more gracefully

On pre-r6 systems with the MT ASE the CPS SMP code included checks to
halt the VPE running mips_cps_boot_vpes() if its bit in the struct
core_boot_config vpe_mask field is clear. This was largely done in order
to allow us to start arbitrary VPEs within a core despite the fact that
hardware is typically configured to run only VPE0 after powering up a
core. VPE0 would start the desired other VPEs, halt itself, and the fact
that VPE0 started would be largely hidden & irrelevant.

In MIPSr6 multithreading we have control over which VPs start executing
when a core powers up via the cores CPC registers accessed remotely
through the redirect block. For this reason the MIPSr6 multithreading
path in mips_cps_boot_vpes() hasn't bothered up until now to handle
halting the VP running it.

However it is possible to power up cores entirely in hardware by using a
pwr_up pin associated with the core. Unfortunately some systems wire
this pin to a logic 1, which means that it is possible for a core to
power up at a point that software doesn't expect. The result is that we
generally go execute the kernel on a CPU that ought not to be running &
the results can be unpredictable.

Handle this case by stopping VPs that we don't expect to be running in
mips_cps_boot_vpes() - with this change even if a core powers up it will
do nothing useful & all VPs within it will stop running before they
proceed to run general kernel code & do any damage. Ideally we would
produce some sort of warning here, but given the stage of core bringup
this happens at that would be non-trivial. We also will only hit this if
a core starts up after being offlined via hotplug, and when that happens
we will already produce a warning that the CPU didn't power down in
cps_cpu_die() which seems sufficient.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/16198/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: smp-cps: Fix retrieval of VPE mask on big endian CPUs

The vpe_mask member of struct core_boot_config is of type atomic_t,
which is a 32bit type. In cps-vec.S this member was being retrieved by

MIPS: smp-cps: Fix retrieval of VPE mask on big endian CPUs

The vpe_mask member of struct core_boot_config is of type atomic_t,
which is a 32bit type. In cps-vec.S this member was being retrieved by a
PTR_L macro, which on 64bit systems is a 64bit load. On little endian
systems this is OK, since the double word that is retrieved will have
the required less significant word in the correct position. However, on
big endian systems the less significant word of the load is retrieved
from address+4, and the more significant from address+0. The destination
register therefore ends up with the required word in the more
significant word
e.g. when starting the second VP of a big endian 64bit system, the load

PTR_L ta2, COREBOOTCFG_VPEMASK(a0)

ends up setting register ta2 to 0x0000000300000000

When this value is written to the CPC it is ignored, since it is
invalid to write anything larger than 4 bits. This results in any VP
other than VP0 in a core failing to start in 64bit big endian systems.

Change the load to a 32bit load word instruction to fix the bug.

Fixes: f12401d7219f ("MIPS: smp-cps: Pull boot config retrieval out of mips_cps_boot_vpes")
Signed-off-by: Matt Redfearn <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/15787/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: CPS: Copy EVA configuration when starting secondary VPs.

When starting secondary VPEs which support EVA and the SegCtl registers,
copy the memory segmentation configuration from the running VP

MIPS: CPS: Copy EVA configuration when starting secondary VPs.

When starting secondary VPEs which support EVA and the SegCtl registers,
copy the memory segmentation configuration from the running VPE to ensure
that all VPEs in the core have a consistent virtual memory map.

The EVA configuration of secondary cores is dealt with when starting the
core via the CM.

Signed-off-by: Matt Redfearn <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/13291/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: smp-cps: Stop printing EJTAG exceptions to UART

When CONFIG_MIPS_CPS_NS16550 is enabled, some register state is dumped
to the UART when an exception is taken via the BEV on secondary cores.
EJ

MIPS: smp-cps: Stop printing EJTAG exceptions to UART

When CONFIG_MIPS_CPS_NS16550 is enabled, some register state is dumped
to the UART when an exception is taken via the BEV on secondary cores.
EJTAG exceptions are architecturally expected to be handled by the BEV
even when Status.BEV is 0. This effectively means that if userland
executes an sdbbp instruction on a secondary core then the kernel dumps
register state to the UART even though the exception is perfectly normal
& expected. Prevent this by simply not dumping information to the UART
for EJTAG exceptions.

Fixes: 609cf6f2291a ("MIPS: CPS: Early debug using an ns16550-compatible UART")
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12341/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: smp-cps: Support MIPSr6 Virtual Processors

Introduce support for bringing up Virtual Processors in MIPSr6 systems
as CPUs, much like their VPE parallel from the now-deprecated MT ASE.
The exis

MIPS: smp-cps: Support MIPSr6 Virtual Processors

Introduce support for bringing up Virtual Processors in MIPSr6 systems
as CPUs, much like their VPE parallel from the now-deprecated MT ASE.
The existing mips_cps_boot_vpes function fits the MIPSr6 architecture
pretty well - it can now simply write the mask of running VPs to the
VC_RUN register, rather than looping through each & starting or stopping
as appropriate as is done for VPEs from the MT ASE. Thus the VP support
is in general an extension & simplification of the existing MT ASE VPE
(aka SMVP) support.

Signed-off-by: Paul Burton <[email protected]>
Cc: Matt Redfearn <[email protected]>
Cc: Rusty Russell <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Cc: Niklas Cassel <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12339/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: smp-cps: Skip core setup if coherent

In preparation for supporting MIPSr6 multithreading (ie. VPs) which will
begin execution from the core reset vector, skip core level setup if the
core is a

MIPS: smp-cps: Skip core setup if coherent

In preparation for supporting MIPSr6 multithreading (ie. VPs) which will
begin execution from the core reset vector, skip core level setup if the
core is already coherent. This is never the case when a core is first
started, since boot_core explicitly clears the cores GCR_Cx_COH_EN
register, and always the case when secondary VPs start since the first
VP to start will have enabled coherence after initialising the core &
its caches.

One notable side effect of this patch is that eva_init gets called
slightly earlier, prior to mips_cps_core_init rather than after it.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12338/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: smp-cps: Pull boot config retrieval out of mips_cps_boot_vpes

The mips_cps_boot_vpes function previously included code to retrieve
pointers to the core & VPE boot configuration structs. These

MIPS: smp-cps: Pull boot config retrieval out of mips_cps_boot_vpes

The mips_cps_boot_vpes function previously included code to retrieve
pointers to the core & VPE boot configuration structs. These structures
were used both by mips_cps_boot_vpes and by its mips_cps_core_entry
callsite. In preparation for skipping the call to mips_cps_boot_vpes on
some invocations of mips_cps_core_entry, pull the calculation of those
pointers out into a separate function such that it can continue to be
shared.

Signed-off-by: Paul Burton <[email protected]>
Cc: Rusty Russell <[email protected]>
Cc: Matt Redfearn <[email protected]>
Cc: Niklas Cassel <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12337/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: smp-cps: Pull cache init into a function

In preparation for further modifications to mips_cps_core_entry, pull
the L1 cache initialisation out into a separate function. This both
makes the cod

MIPS: smp-cps: Pull cache init into a function

In preparation for further modifications to mips_cps_core_entry, pull
the L1 cache initialisation out into a separate function. This both
makes the code in mips_cps_core_entry read more clearly, particularly
when modifying it, and shortens it which will become important as code
is added that needs to continue to fit within the reset vector.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12336/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: CPS: drop .set mips64r2 directives

Commit 977e043d5ea1 ("MIPS: kernel: cps-vec: Replace mips32r2 ISA level
with mips64r2") leads to .set mips64r2 directives being present in 32
bit (ie. CONFIG

MIPS: CPS: drop .set mips64r2 directives

Commit 977e043d5ea1 ("MIPS: kernel: cps-vec: Replace mips32r2 ISA level
with mips64r2") leads to .set mips64r2 directives being present in 32
bit (ie. CONFIG_32BIT=y) kernels. This is incorrect & leads to MIPS64
instructions being emitted by the assembler when expanding
pseudo-instructions. For example the "move" instruction can legitimately
be expanded to a "daddu". This causes problems when the kernel is run on
a MIPS32 CPU, as CONFIG_32BIT kernels of course often are...

Fix this by dropping the .set <ISA> directives entirely now that Kconfig
should be ensuring that kernels including this code are built with a
suitable -march= compiler flag.

Signed-off-by: Paul Burton <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: James Hogan <[email protected]>
Cc: <[email protected]> # 3.16+
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10869/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: CPS: Skip Config1 presence check

The Config1 register is architecturally defined as required, and is thus
present in all systems which may make use of cps-vec.S. Skip the check
for its presenc

MIPS: CPS: Skip Config1 presence check

The Config1 register is architecturally defined as required, and is thus
present in all systems which may make use of cps-vec.S. Skip the check
for its presence via the Config.M bit.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Markos Chandras <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/11204/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: CPS: Read CM GCR base from cop0

Rather than patching the start of mips_cps_core_entry to provide the
base address of the CM GCRs, simply read that base address from the cop0
CMGCRBase register

MIPS: CPS: Read CM GCR base from cop0

Rather than patching the start of mips_cps_core_entry to provide the
base address of the CM GCRs, simply read that base address from the cop0
CMGCRBase register, converting from the physical address to an uncached
virtual address.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Rusty Russell <[email protected]>
Cc: Andrew Bresticker <[email protected]>
Cc: [email protected]
Cc: Niklas Cassel <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Cc: Markos Chandras <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/11203/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: CPS: Early debug using an ns16550-compatible UART

Provide support for outputting early debug information, in the form of
various register values should an exception occur, during the early
bri

MIPS: CPS: Early debug using an ns16550-compatible UART

Provide support for outputting early debug information, in the form of
various register values should an exception occur, during the early
bringup of secondary cores. This code requires an ns16550-compatible
UART accessible from the secondary core, and is written in assembly due
to the environment in which such early exceptions occur where way may
not have a stack, be coherent or even have initialised caches.

[[email protected]: Fix merge conflict.]

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Steven J. Hill <[email protected]>
Cc: Andrew Bresticker <[email protected]>
Cc: Leonid Yegoshin <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: [email protected]
Cc: James Hogan <[email protected]>
Cc: Markos Chandras <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/11202/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: CPS: Set Status.KX on entry for MIPS64 kernels

If the kernel may make use of 64 bit addresses outside of the
compatibility address space then we need to set KX such that those
accesses can suc

MIPS: CPS: Set Status.KX on entry for MIPS64 kernels

If the kernel may make use of 64 bit addresses outside of the
compatibility address space then we need to set KX such that those
accesses can succeed. Do so for MIPS64 kernels.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Markos Chandras <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/11201/
Signed-off-by: Ralf Baechle <[email protected]>

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