MIPS: Remove VR41xx support

No (active) developer owns this hardware, so let's remove Linux support.

Signed-off-by: Thomas Bogendoerfer <[email protected]>

MIPS: Remove TX39XX support

No (active) developer owns this hardware, so let's remove Linux support.

Signed-off-by: Thomas Bogendoerfer <[email protected]>
Acked-by: Guenter Roeck <linux@ro

MIPS: Remove TX39XX support

No (active) developer owns this hardware, so let's remove Linux support.

Signed-off-by: Thomas Bogendoerfer <[email protected]>
Acked-by: Guenter Roeck <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Tested-by: Geert Uytterhoeven <[email protected]>
Acked-by: Atsushi Nemoto <[email protected]>

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MIPS: Remove NETLOGIC support

No (active) developer owns this hardware, so let's remove Linux support.

Signed-off-by: Thomas Bogendoerfer <[email protected]>

Revert "MIPS: Remove unused R4300 CPU support"

This reverts commit f9065b54d437c4660e3d974ad9ce5188c068cd76.

We're adding Nintendo 64 support, so the VR4300 is no longer unused.

Signed-off-by: Lau

Revert "MIPS: Remove unused R4300 CPU support"

This reverts commit f9065b54d437c4660e3d974ad9ce5188c068cd76.

We're adding Nintendo 64 support, so the VR4300 is no longer unused.

Signed-off-by: Lauri Kasanen <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>

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MIPS: Add the missing 'CPU_1074K' into __get_cpu_type()

Commit 442e14a2c55e ("MIPS: Add 1074K CPU support explicitly.") split
1074K from the 74K as an unique CPU type, while it missed to add the
'CP

MIPS: Add the missing 'CPU_1074K' into __get_cpu_type()

Commit 442e14a2c55e ("MIPS: Add 1074K CPU support explicitly.") split
1074K from the 74K as an unique CPU type, while it missed to add the
'CPU_1074K' in __get_cpu_type(). So let's add it back.

Fixes: 442e14a2c55e ("MIPS: Add 1074K CPU support explicitly.")
Signed-off-by: Wei Li <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>

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mips: Add MIPS Release 5 support

There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as ma

mips: Add MIPS Release 5 support

There are five MIPS32/64 architecture releases currently available:
from 1 to 6 except fourth one, which was intentionally skipped.
Three of them can be called as major: 1st, 2nd and 6th, that not only
have some system level alterations, but also introduced significant
core/ISA level updates. The rest of the MIPS architecture releases are
minor.

Even though they don't have as much ISA/system/core level changes
as the major ones with respect to the previous releases, they still
provide a set of updates (I'd say they were intended to be the
intermediate releases before a major one) that might be useful for the
kernel and user-level code, when activated by the kernel or compiler.
In particular the following features were introduced or ended up being
available at/after MIPS32/64 Release 5 architecture:
+ the last release of the misaligned memory access instructions,
+ virtualisation - VZ ASE - is optional component of the arch,
+ SIMD - MSA ASE - is optional component of the arch,
+ DSP ASE is optional component of the arch,
+ CP0.Status.FR=1 for CP1.FIR.F64=1 (pure 64-bit FPU general registers)
must be available if FPU is implemented,
+ CP1.FIR.Has2008 support is required so CP1.FCSR.{ABS2008,NAN2008} bits
are available.
+ UFR/UNFR aliases to access CP0.Status.FR from user-space by means of
ctc1/cfc1 instructions (enabled by CP0.Config5.UFR),
+ CP0.COnfig5.LLB=1 and eretnc instruction are implemented to without
accidentally clearing LL-bit when returning from an interrupt,
exception, or error trap,
+ XPA feature together with extended versions of CPx registers is
introduced, which needs to have mfhc0/mthc0 instructions available.

So due to these changes GNU GCC provides an extended instructions set
support for MIPS32/64 Release 5 by default like eretnc/mfhc0/mthc0. Even
though the architecture alteration isn't that big, it still worth to be
taken into account by the kernel software. Finally we can't deny that
some optimization/limitations might be found in future and implemented
on some level in kernel or compiler. In this case having even
intermediate MIPS architecture releases support would be more than
useful.

So the most of the changes provided by this commit can be split into
either compile- or runtime configs related. The compile-time related
changes are caused by adding the new CONFIG_CPU_MIPS32_R5/CONFIG_CPU_MIPSR5
configs and concern the code activating MIPSR2 or MIPSR6 already
implemented features (like eretnc/LLbit, mthc0/mfhc0). In addition
CPU_HAS_MSA can be now freely enabled for MIPS32/64 release 5 based
platforms as this is done for CPU_MIPS32_R6 CPUs. The runtime changes
concerns the features which are handled with respect to the MIPS ISA
revision detected at run-time by means of CP0.Config.{AT,AR} bits. Alas
these fields can be used to detect either r1 or r2 or r6 releases.
But since we know which CPUs in fact support the R5 arch, we can manually
set MIPS_CPU_ISA_M32R5/MIPS_CPU_ISA_M64R5 bit of c->isa_level and then
use cpu_has_mips32r5/cpu_has_mips64r5 where it's appropriate.

Since XPA/EVA provide too complex alterationss and to have them used with
MIPS32 Release 2 charged kernels (for compatibility with current platform
configs) they are left to be setup as a separate kernel configs.

Co-developed-by: Alexey Malahov <[email protected]>
Signed-off-by: Alexey Malahov <[email protected]>
Signed-off-by: Serge Semin <[email protected]>
Cc: Thomas Bogendoerfer <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Signed-off-by: Thomas Bogendoerfer <[email protected]>

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MIPS: Fix boot on Fuloong2 systems

Commit 268a2d60013049 ("MIPS: Loongson64: Rename CPU TYPES") changed
Kconfig symbols as follows:
CPU_LOONGSON2 to CPU_LOONGSON2EF
CPU_LOONGSON3 to CPU_LOONGSON64

MIPS: Fix boot on Fuloong2 systems

Commit 268a2d60013049 ("MIPS: Loongson64: Rename CPU TYPES") changed
Kconfig symbols as follows:
CPU_LOONGSON2 to CPU_LOONGSON2EF
CPU_LOONGSON3 to CPU_LOONGSON64
SYS_HAS_CPU_LOONGSON3 to SYS_HAS_CPU_LOONGSON64

It did not touch SYS_HAS_CPU_LOONGSON2E or SYS_HAS_CPU_LOONGSON2F.
However, the patch changed a conditional from

#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \
defined(CONFIG_SYS_HAS_CPU_LOONGSON2F)

to

#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2EF)

SYS_HAS_CPU_LOONGSON2EF does not exist, resulting in boot failures
with the qemu fulong2e emulation. Revert to the original code.

Fixes: 268a2d60013049 ("MIPS: Loongson64: Rename CPU TYPES")
Cc: Jiaxun Yang <[email protected]>
Signed-off-by: Guenter Roeck <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: [email protected]
Cc: [email protected]

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MIPS: Loongson: Rename LOONGSON1 to LOONGSON32

Now old Loongson-2E/2F use LOONGSON2EF and will be removed in future,
newer Loongson-2/3 use LOONGSON64. So rename LOONGSON1 to LOONGSON32
will make th

MIPS: Loongson: Rename LOONGSON1 to LOONGSON32

Now old Loongson-2E/2F use LOONGSON2EF and will be removed in future,
newer Loongson-2/3 use LOONGSON64. So rename LOONGSON1 to LOONGSON32
will make the naming style more unified.

Signed-off-by: Huacai Chen <[email protected]>
[[email protected]: Fix checkpatch whitespace warning in irqflags.h]
Signed-off-by: Paul Burton <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Cc: Huacai Chen <[email protected]>

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MIPS: Loongson64: Rename CPU TYPES

CPU_LOONGSON2 -> CPU_LOONGSON2EF
CPU_LOONGSON3 -> CPU_LOONGSON64

As newer loongson-2 products (2G/2H/2K1000) can share kernel
implementation with loongson-3 while

MIPS: Loongson64: Rename CPU TYPES

CPU_LOONGSON2 -> CPU_LOONGSON2EF
CPU_LOONGSON3 -> CPU_LOONGSON64

As newer loongson-2 products (2G/2H/2K1000) can share kernel
implementation with loongson-3 while 2E/2F are less similar with
other LOONGSON64 products.

Signed-off-by: Jiaxun Yang <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]

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MIPS: Remove unused R8000 CPU support

Our R8000 CPU support can only be included if a system selects
CONFIG_SYS_HAS_CPU_R8000. No system does, making all R8000-related CPU
support dead code. Remove

MIPS: Remove unused R8000 CPU support

Our R8000 CPU support can only be included if a system selects
CONFIG_SYS_HAS_CPU_R8000. No system does, making all R8000-related CPU
support dead code. Remove it.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]

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MIPS: Remove unused R5432 CPU support

Our R5432 CPU support can only be included if a system selects
CONFIG_SYS_HAS_CPU_R5432. No system does, making all R5432-related CPU
support dead code. Remove

MIPS: Remove unused R5432 CPU support

Our R5432 CPU support can only be included if a system selects
CONFIG_SYS_HAS_CPU_R5432. No system does, making all R5432-related CPU
support dead code. Remove it.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]

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MIPS: Remove unused R4300 CPU support

Our R4300 CPU support can only be included if a system selects
CONFIG_SYS_HAS_CPU_R4300. No system does, making all R4300-related CPU
support dead code. Remove

MIPS: Remove unused R4300 CPU support

Our R4300 CPU support can only be included if a system selects
CONFIG_SYS_HAS_CPU_R4300. No system does, making all R4300-related CPU
support dead code. Remove it.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]

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MIPS: Rename JZRISC to XBURST

The real name of the CPU present in the JZ line of SoCs from Ingenic is
XBurst, not JZRISC.

Signed-off-by: Paul Cercueil <[email protected]>
[[email protected]:

MIPS: Rename JZRISC to XBURST

The real name of the CPU present in the JZ line of SoCs from Ingenic is
XBurst, not JZRISC.

Signed-off-by: Paul Cercueil <[email protected]>
[[email protected]: Leave /proc/cpuinfo string as-is.]
Signed-off-by: Paul Burton <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]

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MIPS: Remove unused R6000 support

The kernel contains a small amount of incomplete code aimed at
supporting old R6000 CPUs. This is:

- Unused, as no machine selects CONFIG_SYS_HAS_CPU_R6000.

-

MIPS: Remove unused R6000 support

The kernel contains a small amount of incomplete code aimed at
supporting old R6000 CPUs. This is:

- Unused, as no machine selects CONFIG_SYS_HAS_CPU_R6000.

- Broken, since there are glaring errors such as r6000_fpu.S moving
the FCSR register to t1, then ignoring it & instead saving t0 into
struct sigcontext...

- A maintenance headache, since it's code that nobody can test which
nevertheless imposes constraints on code which it shares with other
machines.

Remove this incomplete & broken R6000 CPU support in order to clean up
and in preparation for changes which will no longer need to consider
dragging the pretense of R6000 support along with them.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/16236/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: Probe the I6500 CPU

Introduce the I6500 PRID & probe it just the same way as I6400. The MIPS
I6500 is the latest in Imagination Technologies' I-Class range of CPUs,
with a focus on scalability

MIPS: Probe the I6500 CPU

Introduce the I6500 PRID & probe it just the same way as I6400. The MIPS
I6500 is the latest in Imagination Technologies' I-Class range of CPUs,
with a focus on scalability & heterogeneity. It introduces the notion of
multiple clusters to the MIPS Coherent Processing System, allowing for a
far higher total number of cores & threads in a system when compared
with its predecessors. Clusters don't need to be identical, and may
contain differing numbers of cores & IOCUs, or cores with differing
properties.

This patch alone adds the basic support for booting Linux on an I6500
CPU without support for any of its new functionality, for which support
will be introduced in further patches.

Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/16190/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: Add CPU support for Loongson1C

Loongson1C is a 32-bit SoC designed by Loongson Technology Co., Ltd,
with many features similar to Loongson1B.

Signed-off-by: Yang Ling <[email protected]>
Cc:

MIPS: Add CPU support for Loongson1C

Loongson1C is a 32-bit SoC designed by Loongson Technology Co., Ltd,
with many features similar to Loongson1B.

Signed-off-by: Yang Ling <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/13303/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: Add M6250 cases to CPU switch statements

Add casses supporting the M6250 CPU to various switch statements in the
core MIPS kernel code that define behaviour dependent upon the CPU.

Signed-off

MIPS: Add M6250 cases to CPU switch statements

Add casses supporting the M6250 CPU to various switch statements in the
core MIPS kernel code that define behaviour dependent upon the CPU.

Signed-off-by: Paul Burton <[email protected]>
Cc: Joshua Kinard <[email protected]>
Cc: Leonid Yegoshin <[email protected]>
Cc: Paul Gortmaker <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12374/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: Add P6600 cases to CPU switch statements

Add cases supporting the P6600 CPU to various switch statements in
core MIPS kernel code that define behaviour dependent upon the CPU.

Signed-off-by:

MIPS: Add P6600 cases to CPU switch statements

Add cases supporting the P6600 CPU to various switch statements in
core MIPS kernel code that define behaviour dependent upon the CPU.

Signed-off-by: Paul Burton <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Joshua Kinard <[email protected]>
Cc: Andrzej Hajda <[email protected]>
Cc: Leonid Yegoshin <[email protected]>
Cc: Paul Gortmaker <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>
Cc: Ingo Molnar <[email protected]>
Cc: Petri Gynther <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/12343/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: Add cases for CPU_I6400

Add a CPU_I6400 case to various switch statements, doing the same thing
as for CPU_P5600.

Signed-off-by: Markos Chandras <[email protected]>
Cc: linux-mips@li

MIPS: Add cases for CPU_I6400

Add a CPU_I6400 case to various switch statements, doing the same thing
as for CPU_P5600.

Signed-off-by: Markos Chandras <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10635/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: ingenic: Initial JZ4780 support

Support the Ingenic JZ4780 SoC using the existing code under
arch/mips/jz4740 now that it has been generalised sufficiently.

Signed-off-by: Paul Burton <paul.b

MIPS: ingenic: Initial JZ4780 support

Support the Ingenic JZ4780 SoC using the existing code under
arch/mips/jz4740 now that it has been generalised sufficiently.

Signed-off-by: Paul Burton <[email protected]>
Cc: Ian Campbell <[email protected]>
Cc: Kumar Gala <[email protected]>
Cc: Lars-Peter Clausen <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Joshua Kinard <[email protected]>
Cc: Leonid Yegoshin <[email protected]>
Cc: Deng-Cheng Zhu <[email protected]>
Cc: [email protected]
Cc: Markos Chandras <[email protected]>
Cc: Andreas Herrmann <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10164/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: Add R16000 detection

This allows the kernel to correctly detect an R16000 MIPS CPU on systems that
have those. Otherwise, such systems will detect the CPU as an R14000, due to
similarities in

MIPS: Add R16000 detection

This allows the kernel to correctly detect an R16000 MIPS CPU on systems that
have those. Otherwise, such systems will detect the CPU as an R14000, due to
similarities in the CPU PRId value.

Signed-off-by: Joshua Kinard <[email protected]>
Cc: Linux MIPS List <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9092/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: Add cases for CPU_QEMU_GENERIC

Add a CPU_QEMU_GENERIC case to various switch statements.

Signed-off-by: Leonid Yegoshin <[email protected]>
Signed-off-by: Markos Chandras <markos.cha

MIPS: Add cases for CPU_QEMU_GENERIC

Add a CPU_QEMU_GENERIC case to various switch statements.

Signed-off-by: Leonid Yegoshin <[email protected]>
Signed-off-by: Markos Chandras <[email protected]>

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MIPS: OCTEON: Add OCTEON3 to __get_cpu_type

Otherwise __builtin_unreachable might be called.

Signed-off-by: Andreas Herrmann <[email protected]>
Cc: [email protected]
Cc:

MIPS: OCTEON: Add OCTEON3 to __get_cpu_type

Otherwise __builtin_unreachable might be called.

Signed-off-by: Andreas Herrmann <[email protected]>
Cc: [email protected]
Cc: David Daney <[email protected]>
Cc: James Hogan <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/7014/
Signed-off-by: Ralf Baechle <[email protected]>

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MIPS: Remove code protected by CONFIG_SYS_HAS_CPU_RM9000.

RM9000 support was removed a while ago but this bit crept back in through
commit 69f24d17 [MIPS: Optimize current_cpu_type() for better code

MIPS: Remove code protected by CONFIG_SYS_HAS_CPU_RM9000.

RM9000 support was removed a while ago but this bit crept back in through
commit 69f24d17 [MIPS: Optimize current_cpu_type() for better code.] which
had been developed before but merged after RM9000 support was removed.

Signed-off-by: Ralf Baechle <[email protected]>
Reported-by: Paul Bolle <[email protected]>

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MIPS: Loongson: Add basic Loongson-3 CPU support

Basic Loongson-3 CPU support include CPU probing and TLB/cache
initializing.

Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang

MIPS: Loongson: Add basic Loongson-3 CPU support

Basic Loongson-3 CPU support include CPU probing and TLB/cache
initializing.

Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang Tao <[email protected]>
Signed-off-by: Hua Yan <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6630
Signed-off-by: Ralf Baechle <[email protected]>

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