microblaze: Prevent the overflow of the start

In case the start + cache size is more than the max int the
start overflows.
Prevent the same.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xi

microblaze: Prevent the overflow of the start

In case the start + cache size is more than the max int the
start overflows.
Prevent the same.

Signed-off-by: Shubhrajyoti Datta <[email protected]>
Signed-off-by: Michal Simek <[email protected]>

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microblaze: Use unsigned type for limit comparison in cache.c

The patch removes warnings:
arch/microblaze/kernel/cpu/cache.c:146:14: warning: comparison of
unsigned expression < 0 is always false [-

microblaze: Use unsigned type for limit comparison in cache.c

The patch removes warnings:
arch/microblaze/kernel/cpu/cache.c:146:14: warning: comparison of
unsigned expression < 0 is always false [-Wtype-limits]

Signed-off-by: Michal Simek <[email protected]>

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microblaze: Initialize temp variable to remove compilation warning

Compilation warning:
arch/microblaze/kernel/cpu/cache.c:148:2: warning:
'temp' is used uninitialized in this function [-Wuninitial

microblaze: Initialize temp variable to remove compilation warning

Compilation warning:
arch/microblaze/kernel/cpu/cache.c:148:2: warning:
'temp' is used uninitialized in this function [-Wuninitialized]

Signed-off-by: Michal Simek <[email protected]>

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microblaze: Fix coding style issues

Fix coding style issues reported by checkpatch.pl.

Signed-off-by: Michal Simek <[email protected]>

Fix common misspellings

Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi <[email protected]>

microblaze: Fix sparse warnings - cache.c

Warning log:
CHECK arch/microblaze/kernel/cpu/cache.c
arch/microblaze/kernel/cpu/cache.c:522:21: warning: symbol 'wb_msr' was not declared. Should it be s

microblaze: Fix sparse warnings - cache.c

Warning log:
CHECK arch/microblaze/kernel/cpu/cache.c
arch/microblaze/kernel/cpu/cache.c:522:21: warning: symbol 'wb_msr' was not declared. Should it be static?
arch/microblaze/kernel/cpu/cache.c:538:21: warning: symbol 'wb_nomsr' was not declared. Should it be static?
arch/microblaze/kernel/cpu/cache.c:554:21: warning: symbol 'wt_msr' was not declared. Should it be static?
arch/microblaze/kernel/cpu/cache.c:569:21: warning: symbol 'wt_nomsr' was not declared. Should it be static?
arch/microblaze/kernel/cpu/cache.c:585:21: warning: symbol 'wt_msr_noirq' was not declared. Should it be static?
arch/microblaze/kernel/cpu/cache.c:600:21: warning: symbol 'wt_nomsr_noirq' was not declared. Should it be static?

Signed-off-by: Michal Simek <[email protected]>

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microblaze: Label MB 7.20.d as broken with WB cache

MB version 7.20.d contains fault which is related with WB that's why
error message will be shown.

Signed-off-by: Michal Simek <[email protected]>

microblaze: Remove compilation warnings in cache macro

CC arch/microblaze/kernel/cpu/cache.o
arch/microblaze/kernel/cpu/cache.c: In function '__invalidate_dcache_range_wb':
arch/microblaze/kern

microblaze: Remove compilation warnings in cache macro

CC arch/microblaze/kernel/cpu/cache.o
arch/microblaze/kernel/cpu/cache.c: In function '__invalidate_dcache_range_wb':
arch/microblaze/kernel/cpu/cache.c:398: warning: ISO C90 forbids mixed declarations and code
arch/microblaze/kernel/cpu/cache.c: In function '__flush_dcache_range_wb':
arch/microblaze/kernel/cpu/cache.c:509: warning: ISO C90 forbids mixed declara

Signed-off-by: Michal Simek <[email protected]>

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microblaze: Optimize CACHE_LOOP_LIMITS and CACHE_RANGE_LOOP macros

1. Remove CACHE_ALL_LOOP2 macro because it is identical to CACHE_ALL_LOOP
2. Change BUG_ON to WARN_ON
3. Remove end aligned from CA

microblaze: Optimize CACHE_LOOP_LIMITS and CACHE_RANGE_LOOP macros

1. Remove CACHE_ALL_LOOP2 macro because it is identical to CACHE_ALL_LOOP
2. Change BUG_ON to WARN_ON
3. Remove end aligned from CACHE_LOOP_LIMITS.
C implementation do not need aligned end address and ASM code do aligned
in their macros
4. ASM optimized CACHE_RANGE_LOOP_1/2 macros needs to get aligned end address.
Because end address is compound from start + size, end address is the first address
which is exclude.

Here is the corresponding code which describe it.
+ int align = ~(line_length - 1);
+ end = ((end & align) == end) ? end - line_length : end & align;

a) end is aligned:
it is necessary to subtruct line length because we don't want to work with
next cacheline
b) end address is not aligned:
Just align it to be ready for ASM code.

Signed-off-by: Michal Simek <[email protected]>

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microblaze: Fix typo fault in cache code

Copy & paste error.

Signed-off-by: Michal Simek <[email protected]>

microblaze: Add define for ASM_LOOP

It is default option but both options must be measured.

Signed-off-by: Michal Simek <[email protected]>

microblaze: remove trailing space in messages

Signed-off-by: Frans Pop <[email protected]>
Cc: [email protected]
Cc: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <mons

microblaze: remove trailing space in messages

Signed-off-by: Frans Pop <[email protected]>
Cc: [email protected]
Cc: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>

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microblaze: Move cache function to cache.c

It is better to have init cache handling on one place.

Signed-off-by: Michal Simek <[email protected]>

microblaze: Fix cache loop function for cache range

I create wrong asm code but none test shows that this part of code is wrong.
I am not convinces that were good idea to create asm optimized macros

microblaze: Fix cache loop function for cache range

I create wrong asm code but none test shows that this part of code is wrong.
I am not convinces that were good idea to create asm optimized macros
for caches. The reason is that there is not optimization with previous code
that's why make sense to add old code and do some benchmarking which
functions are faster.

Signed-off-by: Michal Simek <[email protected]>

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microblaze: Support for WB cache

Microblaze version 7.20.d is the first MB version which can be run
on MMU linux. Please do not used previous version because they contain
HW bug.
Based on WB support

microblaze: Support for WB cache

Microblaze version 7.20.d is the first MB version which can be run
on MMU linux. Please do not used previous version because they contain
HW bug.
Based on WB support was necessary to redesign whole cache design.
Microblaze versions from 7.20.a don't need to disable IRQ and cache
before working with them that's why there are special structures for it.

Signed-off-by: Michal Simek <[email protected]>

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microblaze: Fix cache_line_lenght

We used cache_line as cache_line_lenght. For this reason
we did cache flushing 4 times longer than was necessary.

Signed-off-by: Michal Simek <[email protected]>

microblaze: Do not check use_dcache

It is not necessary to check cpuinfo.use_dcache because
this checking is done in function which call that functions

Signed-off-by: Michal Simek <[email protected]>

microblaze_v8: cache support

Reviewed-by: Ingo Molnar <[email protected]>
Acked-by: Stephen Neuendorffer <[email protected]>
Acked-by: John Linn <[email protected]>
Acked-by: John Willi

microblaze_v8: cache support

Reviewed-by: Ingo Molnar <[email protected]>
Acked-by: Stephen Neuendorffer <[email protected]>
Acked-by: John Linn <[email protected]>
Acked-by: John Williams <[email protected]>
Signed-off-by: Michal Simek <[email protected]>

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