ARM: bcm: Support BCMBCA debug UART

The debug UART on the BCMBCA SoCs are in a different place
than on the other BCM platforms. Support this with a static
map when debugging is explicitly configured

ARM: bcm: Support BCMBCA debug UART

The debug UART on the BCMBCA SoCs are in a different place
than on the other BCM platforms. Support this with a static
map when debugging is explicitly configured.

Right now I can only test this on BCM6846 so this is the
only compatible I list for the debug boardfile, but other
compatibles from the BCMBCA family can be added to get
LL_DEBUG support.

Signed-off-by: Linus Walleij <[email protected]>
Acked-by: William Zhang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Florian Fainelli <[email protected]>

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arm: bcmbca: Move BCM63138 ARCH_BCM_63XX to ARCH_BCMBCA

Remove ARCH_BCM_63XX Kconfig for BCM63138 and merge its selections to
ARCH_BCMBCA. Delete bcm63xx.c as it is no longer needed.

Signed-off-by:

arm: bcmbca: Move BCM63138 ARCH_BCM_63XX to ARCH_BCMBCA

Remove ARCH_BCM_63XX Kconfig for BCM63138 and merge its selections to
ARCH_BCMBCA. Delete bcm63xx.c as it is no longer needed.

Signed-off-by: William Zhang <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>

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treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_30.RULE (part 1)

Based on the normalized pattern:

this program is free software you can redistribute it and/or modify it
un

treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_30.RULE (part 1)

Based on the normalized pattern:

this program is free software you can redistribute it and/or modify it
under the terms of the gnu general public license as published by the
free software foundation version 2 this program is distributed as is
without any warranty of any kind whether express or implied without
even the implied warranty of merchantability or fitness for a
particular purpose see the gnu general public license for more details

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference.

Reviewed-by: Allison Randal <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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ARM: mach-bcm: disable ftrace in SMC invocation routines

The SMC calling convention uses R7 as an argument register, which
conflicts with its use as a frame pointer when building in Thumb2 mode.
Giv

ARM: mach-bcm: disable ftrace in SMC invocation routines

The SMC calling convention uses R7 as an argument register, which
conflicts with its use as a frame pointer when building in Thumb2 mode.
Given that Clang with ftrace does not permit frame pointers to be
disabled, let's omit this compilation unit from ftrace instrumentation.

Signed-off-by: Ard Biesheuvel <[email protected]>
Acked-by: Nick Desaulniers <[email protected]>

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ARM: bcm: Add support for BCM2711 SoC

Add the BCM2711 to ARCH_BCM2835, but use new machine board code
because of the differences.

Signed-off-by: Stefan Wahren <[email protected]>
Reviewed-by: Eric A

ARM: bcm: Add support for BCM2711 SoC

Add the BCM2711 to ARCH_BCM2835, but use new machine board code
because of the differences.

Signed-off-by: Stefan Wahren <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Acked-by: Florian Fanelli <[email protected]>

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ARM: use arch_extension directive instead of arch argument

The LLVM Target parser currently does not allow to specify the security
extension as part of -march (see also LLVM Bug 40186 [0]). When try

ARM: use arch_extension directive instead of arch argument

The LLVM Target parser currently does not allow to specify the security
extension as part of -march (see also LLVM Bug 40186 [0]). When trying
to use Clang with LLVM's integrated assembler, this leads to build
errors such as this:
clang-8: error: the clang compiler does not support '-Wa,-march=armv7-a+sec'

Use ".arch_extension sec" to enable the security extension in a more
portable fasion. Also make sure to use ".arch armv7-a" in case a v6/v7
multi-platform kernel is being built.

Note that this is technically not exactly the same as the old code
checked for availabilty of the security extension by calling as-instr.
However, there are already other sites which use ".arch_extension sec"
unconditionally, hence de-facto we need an assembler capable of
".arch_extension sec" already today (arch/arm/mm/proc-v7.S). The
arch extension "sec" is available since binutils 2.21 according to
its documentation [1].

[0] https://bugs.llvm.org/show_bug.cgi?id=40186
[1] https://sourceware.org/binutils/docs-2.21/as/ARM-Options.html

Signed-off-by: Stefan Agner <[email protected]>
Acked-by: Mans Rullgard <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>

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ARM: bcm: Add support for Broadcom Hurricane 2 SoC

Add a Kconfig entry point and basic machine board code for the Broadcom
Hurricane 2 SoCs used in switching products.

Acked-by: Jon Mason <jon.maso

ARM: bcm: Add support for Broadcom Hurricane 2 SoC

Add a Kconfig entry point and basic machine board code for the Broadcom
Hurricane 2 SoCs used in switching products.

Acked-by: Jon Mason <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>

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irqchip: bcm2836: Move SMP startup code to arch/arm (v2)

In order to easily provide SMP for BCM2837 on 32-bit and 64-bit
the SMP startup code was placed in irq-bcm2836. That's not the
right approach

irqchip: bcm2836: Move SMP startup code to arch/arm (v2)

In order to easily provide SMP for BCM2837 on 32-bit and 64-bit
the SMP startup code was placed in irq-bcm2836. That's not the
right approach. So move this code where it belongs.

Signed-off-by: Stefan Wahren <[email protected]>
Fixes: 41f4988cc287 ("irqchip/bcm2836: Add SMP support for the 2836")
Tested-by: Eric Anholt <[email protected]>
Acked-by: Marc Zyngier <[email protected]>

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ARM: Add support for Broadcom BCM23550 SoC

BCM23550 is a quad-A7 SoC used on the Broadcom "Sparrow" board.
It shares many IP blocks with other Broadcom Kona chips.

Signed-off-by: Chris Brand <chris

ARM: Add support for Broadcom BCM23550 SoC

BCM23550 is a quad-A7 SoC used on the Broadcom "Sparrow" board.
It shares many IP blocks with other Broadcom Kona chips.

Signed-off-by: Chris Brand <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>

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ARM: BCM: Add SMP support for Broadcom 4708

Add SMP support for Broadcom's 4708 SoCs.

Signed-off-by: Jon Mason <[email protected]>
Acked-by: Hauke Mehrtens <[email protected]>
Tested-by: Hauke M

ARM: BCM: Add SMP support for Broadcom 4708

Add SMP support for Broadcom's 4708 SoCs.

Signed-off-by: Jon Mason <[email protected]>
Acked-by: Hauke Mehrtens <[email protected]>
Tested-by: Hauke Mehrtens <[email protected]>
Signed-off-by: Kapil Hali <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>

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ARM: BCM: Add SMP support for Broadcom NSP

Add SMP support for Broadcom's Northstar Plus SoC
cpu enable method. This changes also consolidates
iProc family's - BCM NSP and BCM Kona, platform
SMP han

ARM: BCM: Add SMP support for Broadcom NSP

Add SMP support for Broadcom's Northstar Plus SoC
cpu enable method. This changes also consolidates
iProc family's - BCM NSP and BCM Kona, platform
SMP handling in a common file.

Northstar Plus SoC is based on ARM Cortex-A9
revision r3p0 which requires configuration for ARM
Errata 764369 for SMP. This change adds the needed
configuration option.

Signed-off-by: Kapil Hali <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>

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ARM: NSP: Add basic support for Broadcom Northstar Plus SoC

Broadcom Northstar Plus family of SoCs are used for switching
control and management applications as well as residential
router/gateway ap

ARM: NSP: Add basic support for Broadcom Northstar Plus SoC

Broadcom Northstar Plus family of SoCs are used for switching
control and management applications as well as residential
router/gateway applications. The SoC features dual core Cortex
A9 ARM CPUs, integrating several peripheral interfaces including
multiple Gigabit Ethernet PHYs, DDR3 memory, PCIE Gen-2, USB 2.0
and USB 3.0, serial and NAND flash, SATA and several other IO
controllers.

Signed-off-by: Kapil Hali <[email protected]>
Signed-off-by: Jon Mason <[email protected]>
Acked-by: Scott Branden <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>

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ARM: BCM63xx: Remove custom secondary_startup function

With commit 02b4e2756e01c623cc4dbceae4b07be75252db5b ("ARM: v7 setup
function should invalidate L1 cache"), the default secondary_startup
funct

ARM: BCM63xx: Remove custom secondary_startup function

With commit 02b4e2756e01c623cc4dbceae4b07be75252db5b ("ARM: v7 setup
function should invalidate L1 cache"), the default secondary_startup
function for ARMv7 CPUs does invalidate the L1 cache, which was the sole
reason why BCM63xx had to have its own secondary_startup implementation.

Now that the secondary_startup takes care of this, we can completely
remove that code.

Signed-off-by: Florian Fainelli <[email protected]>

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ARM: v7 setup function should invalidate L1 cache

All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU. This is because the L1
cache shou

ARM: v7 setup function should invalidate L1 cache

All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU. This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.

This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.

ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state. Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.

Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.

Reviewed-by: Florian Fainelli <[email protected]>
Tested-by: Florian Fainelli <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Tested-by: Dinh Nguyen <[email protected]>
Acked-by: Sebastian Hesselbarth <[email protected]>
Tested-by: Sebastian Hesselbarth <[email protected]>
Acked-by: Shawn Guo <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Tested-by: Geert Uytterhoeven <[email protected]>
Tested-by: Michal Simek <[email protected]>
Tested-by: Wei Xu <[email protected]>
Signed-off-by: Russell King <[email protected]>

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ARM: BCM63xx: Add SMP support for BCM63138

Add support for booting the secondary CPU on BCM63138, this involves:

- locating the bootlut to write the reset vector
- powering up the second CPU when w

ARM: BCM63xx: Add SMP support for BCM63138

Add support for booting the secondary CPU on BCM63138, this involves:

- locating the bootlut to write the reset vector
- powering up the second CPU when we need to using the DT-supplied PMB
references
- disabling VFP when enabled such that we can keep having SMP

Signed-off-by: Florian Fainelli <[email protected]>

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ARM: cygnus: Initial support for Broadcom Cygnus SoC

Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.

Reviewed-by: Ray Jui <[email protected]>
Reviewed-by: Desmond Liu <des

ARM: cygnus: Initial support for Broadcom Cygnus SoC

Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.

Reviewed-by: Ray Jui <[email protected]>
Reviewed-by: Desmond Liu <[email protected]>
Reviewed-by: JD (Jiandong) Zheng <[email protected]>
Tested-by: Jonathan Richardson <[email protected]>
Signed-off-by: Scott Branden <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>

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ARM: brcmstb: reintroduce SMP support

Support for SMP bringup of the B15 CPUs on Broadcom STB chips was added
in commit 4fbe66d9903425156c193ae44c81c0f7557755c4 but was reverted in
commit fc3e825fa9

ARM: brcmstb: reintroduce SMP support

Support for SMP bringup of the B15 CPUs on Broadcom STB chips was added
in commit 4fbe66d9903425156c193ae44c81c0f7557755c4 but was reverted in
commit fc3e825fa91636a5d1b992e769b2d8279877bfad to address some late
review comments. This reintroduces SMP support.

Signed-off-by: Marc Carino <[email protected]>
Signed-off-by: Brian Norris <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>

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ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC

This patch adds basic support for the Broadcom BCM63138 DSL SoC which is
using a dual-core Cortex A9 system. Add the very minimum re

ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC

This patch adds basic support for the Broadcom BCM63138 DSL SoC which is
using a dual-core Cortex A9 system. Add the very minimum required code
boot Linux on this SoC.

Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>

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ARM: brcmstb: revert SMP support

There were several issues (of varying degree of importance) pointed out
with this code late in the review cycle, yet the code was still merged.
Let's rip it out for

ARM: brcmstb: revert SMP support

There were several issues (of varying degree of importance) pointed out
with this code late in the review cycle, yet the code was still merged.
Let's rip it out for now and look at resubmitting at a later time.

This reverts most of commit 4fbe66d9903425156c193ae44c81c0f7557755c4.

Signed-off-by: Brian Norris <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>

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ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs

The BCM7xxx series of Broadcom SoCs are used primarily in set-top boxes.

This patch adds machine support for the ARM-based Broadcom

ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs

The BCM7xxx series of Broadcom SoCs are used primarily in set-top boxes.

This patch adds machine support for the ARM-based Broadcom SoCs.

Signed-off-by: Marc Carino <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Brian Norris <[email protected]>
Signed-off-by: Matt Porter <[email protected]>

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ARM: add SMP support for Broadcom mobile SoCs

This patch adds SMP support for BCM281XX and BCM21664 family SoCs.

This feature is controlled with a distinct config option such that
an SMP-enabled mu

ARM: add SMP support for Broadcom mobile SoCs

This patch adds SMP support for BCM281XX and BCM21664 family SoCs.

This feature is controlled with a distinct config option such that
an SMP-enabled multi-v7 binary can be configured to run these SoCs
in uniprocessor mode. Since this SMP functionality is used for
multiple Broadcom mobile chip families the config option is called
ARCH_BCM_MOBILE_SMP (for lack of a better name).

On SoCs of this type, the secondary core is not held in reset on
power-on. Instead it loops in a ROM-based holding pen. To release
it, one must write into a special register a jump address whose
low-order bits have been replaced with a secondary core's id, then
trigger an event with SEV. On receipt of an event, the ROM code
will examine the register's contents, and if the low-order bits
match its cpu id, it will clear them and write the value back to the
register just prior to jumping to the address specified.

The location of the special register is defined in the device tree
using a "secondary-boot-reg" property in a node whose "enable-method"
matches.

Derived from code originally provided by Ray Jui <[email protected]>

Signed-off-by: Alex Elder <[email protected]>
Signed-off-by: Matt Porter <[email protected]>

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ARM: bcm: rename "kona.h" and "kona.c"

These source files contain only level-2 cache initialization code,
so rename them to make that fact more obvious.

Signed-off-by: Alex Elder <[email protected]>

ARM: bcm: rename "kona.h" and "kona.c"

These source files contain only level-2 cache initialization code,
so rename them to make that fact more obvious.

Signed-off-by: Alex Elder <[email protected]>
Reviewed-by: Tim Kryger <[email protected]>
Reviewed-by: Markus Mayer <[email protected]>
Reviewed-by: Matt Porter <[email protected]>
Signed-off-by: Matt Porter <[email protected]>

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ARM: bcm: use inline assembly for "smc" request

Move the code that implements the "smc" call into a C function that
uses inline assembly. This allows us to make that function private,
and enables u

ARM: bcm: use inline assembly for "smc" request

Move the code that implements the "smc" call into a C function that
uses inline assembly. This allows us to make that function private,
and enables us to get rid of "arch/arm/mach-bcm/bcm_kona_smc_asm.S".
Rename what had been the "buffer_addr" argument to be "buffer_phys"
so it's consistent with other usage in this file.

Since it's now easy to do, verify that r12 contains SEC_EXIT_NORMAL
upon completion of the SMC. There really isn't a good way to handle
the abnormal completion of a secure monitor request.

Since "bcm_kona_smc.h" is now only included from C files, eliminate
the #ifndef __ASSEMBLY__.

Signed-off-by: Alex Elder <[email protected]>
Reviewed-by: Tim Kryger <[email protected]>
Reviewed-by: Markus Mayer <[email protected]>
Reviewed-by: Matt Porter <[email protected]>
Signed-off-by: Matt Porter <[email protected]>

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ARM: bcm: config option for l2 cache support

Add a new config option ARCH_BCM_MOBILE_L2_CACHE that allows support
for level-2 cache to be enabled or disabled at build time for
BCM218XX and BCM21664

ARM: bcm: config option for l2 cache support

Add a new config option ARCH_BCM_MOBILE_L2_CACHE that allows support
for level-2 cache to be enabled or disabled at build time for
BCM218XX and BCM21664 family SoCs.

Build support for SMC only if it's required (currently it's only
required for to support level 2 cache control).

If arch/arm/mach-bcm/kona.c gets compiled, ARCH_BCM_MOBILE_L2_CACHE
must have been selected, which implies CONFIG_CACHE_L2X0 is set.
There is therefore no need to check CONFIG_CACHE_L2X0 at the top
of kona_l2_cache_init(), so get rid of that check.

Signed-off-by: Alex Elder <[email protected]>
Reviewed-by: Tim Kryger <[email protected]>
Reviewed-by: Markus Mayer <[email protected]>
Reviewed-by: Matt Porter <[email protected]>
Signed-off-by: Matt Porter <[email protected]>

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ARM: bcm: clean up config and build targets

Currently CONFIG_ARCH_BCM_MOBILE is used to select all (both)
Broadcom mobile SoC families. Instead, use that only as a config
menu switch, and define sp

ARM: bcm: clean up config and build targets

Currently CONFIG_ARCH_BCM_MOBILE is used to select all (both)
Broadcom mobile SoC families. Instead, use that only as a config
menu switch, and define specific symbols like ARCH_BCM_281XX to
select a particular SoC family. If ARCH_BCM_MOBILE is selected, all
of the SoCs will be selected by default, but this way each can be
disabled individually as well.

Note that BCM281xx and BCM21664 both require the SMC and L2 cache
control code, so that code will be built based on ARCH_BCM_MOBILE.

Signed-off-by: Alex Elder <[email protected]>
[mporter: added ARM: to the description]
Signed-off-by: Matt Porter <[email protected]>

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