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Revision tags: v6.15, v6.15-rc7, v6.15-rc6, v6.15-rc5, v6.15-rc4, v6.15-rc3, v6.15-rc2, v6.15-rc1, v6.14, v6.14-rc7, v6.14-rc6, v6.14-rc5, v6.14-rc4, v6.14-rc3, v6.14-rc2, v6.14-rc1, v6.13, v6.13-rc7, v6.13-rc6, v6.13-rc5, v6.13-rc4, v6.13-rc3, v6.13-rc2, v6.13-rc1, v6.12, v6.12-rc7, v6.12-rc6, v6.12-rc5, v6.12-rc4, v6.12-rc3, v6.12-rc2, v6.12-rc1, v6.11, v6.11-rc7, v6.11-rc6, v6.11-rc5, v6.11-rc4, v6.11-rc3, v6.11-rc2, v6.11-rc1, v6.10, v6.10-rc7, v6.10-rc6, v6.10-rc5, v6.10-rc4, v6.10-rc3, v6.10-rc2, v6.10-rc1, v6.9, v6.9-rc7, v6.9-rc6, v6.9-rc5, v6.9-rc4, v6.9-rc3, v6.9-rc2, v6.9-rc1, v6.8, v6.8-rc7, v6.8-rc6, v6.8-rc5, v6.8-rc4, v6.8-rc3 |
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3992d06c |
| 29-Jan-2024 |
Florian Fainelli <[email protected]> |
ARM: brcmstb: Add debug UART entry for 74165
BCM74165 uses the same address map as the 7278 family (v7 memory map) therefore re-use that constant and shift down the other labels to keep numerical or
ARM: brcmstb: Add debug UART entry for 74165
BCM74165 uses the same address map as the 7278 family (v7 memory map) therefore re-use that constant and shift down the other labels to keep numerical ordering.
Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Florian Fainelli <[email protected]>
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Revision tags: v6.8-rc2, v6.8-rc1, v6.7, v6.7-rc8, v6.7-rc7, v6.7-rc6, v6.7-rc5, v6.7-rc4, v6.7-rc3, v6.7-rc2, v6.7-rc1, v6.6, v6.6-rc7, v6.6-rc6, v6.6-rc5, v6.6-rc4, v6.6-rc3, v6.6-rc2, v6.6-rc1, v6.5, v6.5-rc7, v6.5-rc6, v6.5-rc5, v6.5-rc4, v6.5-rc3, v6.5-rc2, v6.5-rc1, v6.4, v6.4-rc7, v6.4-rc6, v6.4-rc5, v6.4-rc4, v6.4-rc3, v6.4-rc2, v6.4-rc1, v6.3, v6.3-rc7, v6.3-rc6, v6.3-rc5, v6.3-rc4, v6.3-rc3, v6.3-rc2, v6.3-rc1, v6.2, v6.2-rc8, v6.2-rc7, v6.2-rc6, v6.2-rc5, v6.2-rc4, v6.2-rc3, v6.2-rc2, v6.2-rc1, v6.1, v6.1-rc8, v6.1-rc7, v6.1-rc6, v6.1-rc5, v6.1-rc4, v6.1-rc3, v6.1-rc2, v6.1-rc1, v6.0, v6.0-rc7, v6.0-rc6, v6.0-rc5, v6.0-rc4, v6.0-rc3, v6.0-rc2, v6.0-rc1, v5.19, v5.19-rc8, v5.19-rc7, v5.19-rc6, v5.19-rc5, v5.19-rc4, v5.19-rc3, v5.19-rc2 |
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52e6676e |
| 07-Jun-2022 |
Thomas Gleixner <[email protected]> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_30.RULE (part 1)
Based on the normalized pattern:
this program is free software you can redistribute it and/or modify it un
treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_30.RULE (part 1)
Based on the normalized pattern:
this program is free software you can redistribute it and/or modify it under the terms of the gnu general public license as published by the free software foundation version 2 this program is distributed as is without any warranty of any kind whether express or implied without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Reviewed-by: Allison Randal <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Revision tags: v5.19-rc1, v5.18, v5.18-rc7, v5.18-rc6, v5.18-rc5, v5.18-rc4, v5.18-rc3, v5.18-rc2, v5.18-rc1, v5.17, v5.17-rc8, v5.17-rc7, v5.17-rc6, v5.17-rc5, v5.17-rc4, v5.17-rc3, v5.17-rc2, v5.17-rc1, v5.16, v5.16-rc8, v5.16-rc7, v5.16-rc6, v5.16-rc5, v5.16-rc4, v5.16-rc3, v5.16-rc2, v5.16-rc1, v5.15, v5.15-rc7, v5.15-rc6, v5.15-rc5, v5.15-rc4, v5.15-rc3, v5.15-rc2, v5.15-rc1, v5.14, v5.14-rc7, v5.14-rc6, v5.14-rc5, v5.14-rc4, v5.14-rc3, v5.14-rc2, v5.14-rc1, v5.13, v5.13-rc7, v5.13-rc6, v5.13-rc5, v5.13-rc4, v5.13-rc3, v5.13-rc2, v5.13-rc1, v5.12, v5.12-rc8, v5.12-rc7, v5.12-rc6, v5.12-rc5, v5.12-rc4, v5.12-rc3, v5.12-rc2, v5.12-rc1, v5.12-rc1-dontuse, v5.11, v5.11-rc7, v5.11-rc6, v5.11-rc5 |
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d5d5b7f3 |
| 20-Jan-2021 |
Florian Fainelli <[email protected]> |
ARM: brcmstb: Add debug UART entry for 72116
72116 has the same memory map as 7255 and the same physical address for the UART, alias the definition accordingly.
Reviewed-by: Linus Walleij <linus.wa
ARM: brcmstb: Add debug UART entry for 72116
72116 has the same memory map as 7255 and the same physical address for the UART, alias the definition accordingly.
Reviewed-by: Linus Walleij <[email protected]> Signed-off-by: Florian Fainelli <[email protected]>
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Revision tags: v5.11-rc4, v5.11-rc3, v5.11-rc2, v5.11-rc1, v5.10, v5.10-rc7, v5.10-rc6, v5.10-rc5, v5.10-rc4, v5.10-rc3, v5.10-rc2, v5.10-rc1, v5.9, v5.9-rc8, v5.9-rc7, v5.9-rc6, v5.9-rc5, v5.9-rc4, v5.9-rc3 |
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2c50a570 |
| 27-Aug-2020 |
Linus Walleij <[email protected]> |
ARM: 9004/1: debug: Split waituart to CTS and TXRDY
This patch was triggered by a remark from Russell that introducing a call to the waituart (needed to fix debug prints on the Qualcomm platforms) w
ARM: 9004/1: debug: Split waituart to CTS and TXRDY
This patch was triggered by a remark from Russell that introducing a call to the waituart (needed to fix debug prints on the Qualcomm platforms) was dangerous because in some cases this will involve waiting for a modem CTS (clear to send) signal, and debug messages would maybe not work on platforms with no modem connected to the UART port: they will just hang waiting for the modem to assert CTS and this might never happen.
Looking through all UART debug drivers implementing the waituart macro I discovered that all users except two actually use this macro to check if the UART is ready for TX, let's call this TXRDY.
Only two debug UART drivers actually check for CTS: - arch/arm/include/debug/8250.S - arch/arm/include/debug/tegra.S
The former is very significant since the 8250 is possibly the most common UART on the planet.
We have the following problem: the semantics of waituart are ambiguous making it dangerous to introduce the macro to debug code fixing debug prints for Qualcomm. To start to pry this problem apart, this patch does the following:
- Convert all debug UART drivers to define two macros:
- waituartcts with the clear semantic to wait for CTS to be asserted
- waituarttxrdy with the clear semantic to wait for the TX capability of the UART to be ready
- When doing this take care to assign the right function to each drivers macro, so they now do exactly the above.
- Update the three sites in the kernel invoking the waituart macro to call waituartcts/waituarttxrdy in sequence, so that the functional impact on the kernel should be zero.
After this we can start to change the code sites using this code to do the right thing.
Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Russell King <[email protected]>
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Revision tags: v5.9-rc2, v5.9-rc1, v5.8, v5.8-rc7, v5.8-rc6, v5.8-rc5, v5.8-rc4, v5.8-rc3, v5.8-rc2, v5.8-rc1, v5.7, v5.7-rc7, v5.7-rc6, v5.7-rc5, v5.7-rc4, v5.7-rc3, v5.7-rc2, v5.7-rc1, v5.6, v5.6-rc7, v5.6-rc6, v5.6-rc5, v5.6-rc4 |
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4e5cafa8 |
| 28-Feb-2020 |
Florian Fainelli <[email protected]> |
ARM: brcmstb: Add debug UART entry for 72615
72165 has the same memory map as 7278 and the same physical address for the UART, alias the definition accordingly.
Signed-off-by: Florian Fainelli <f.f
ARM: brcmstb: Add debug UART entry for 72615
72165 has the same memory map as 7278 and the same physical address for the UART, alias the definition accordingly.
Signed-off-by: Florian Fainelli <[email protected]>
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Revision tags: v5.6-rc3 |
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6b84ca26 |
| 19-Feb-2020 |
Florian Fainelli <[email protected]> |
ARM: brcmstb: Add debug UART entry for 72614
72164 has the same memory map as 7278 and the same physical address for the UART, alias the definition accordingly.
Signed-off-by: Florian Fainelli <f.f
ARM: brcmstb: Add debug UART entry for 72614
72164 has the same memory map as 7278 and the same physical address for the UART, alias the definition accordingly.
Signed-off-by: Florian Fainelli <[email protected]>
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Revision tags: v5.6-rc2, v5.6-rc1, v5.5, v5.5-rc7, v5.5-rc6, v5.5-rc5, v5.5-rc4, v5.5-rc3, v5.5-rc2 |
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064f42b2 |
| 10-Dec-2019 |
Justin Chen <[email protected]> |
ARM: brcmstb: Add debug UART entry for 7216
7216 has the same memory map as 7278 and the same physical address for the UART, alias the definition accordingly.
Signed-off-by: Justin Chen <justinpopo
ARM: brcmstb: Add debug UART entry for 7216
7216 has the same memory map as 7278 and the same physical address for the UART, alias the definition accordingly.
Signed-off-by: Justin Chen <[email protected]> [florian: expand commit message] Signed-off-by: Florian Fainelli <[email protected]>
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Revision tags: v5.5-rc1, v5.4, v5.4-rc8, v5.4-rc7, v5.4-rc6, v5.4-rc5, v5.4-rc4, v5.4-rc3, v5.4-rc2, v5.4-rc1, v5.3, v5.3-rc8, v5.3-rc7, v5.3-rc6, v5.3-rc5, v5.3-rc4, v5.3-rc3, v5.3-rc2, v5.3-rc1, v5.2, v5.2-rc7, v5.2-rc6, v5.2-rc5, v5.2-rc4, v5.2-rc3, v5.2-rc2, v5.2-rc1, v5.1, v5.1-rc7, v5.1-rc6, v5.1-rc5, v5.1-rc4, v5.1-rc3, v5.1-rc2, v5.1-rc1, v5.0, v5.0-rc8, v5.0-rc7, v5.0-rc6, v5.0-rc5, v5.0-rc4, v5.0-rc3, v5.0-rc2, v5.0-rc1, v4.20, v4.20-rc7, v4.20-rc6, v4.20-rc5, v4.20-rc4, v4.20-rc3, v4.20-rc2, v4.20-rc1, v4.19, v4.19-rc8, v4.19-rc7, v4.19-rc6, v4.19-rc5, v4.19-rc4, v4.19-rc3, v4.19-rc2, v4.19-rc1, v4.18, v4.18-rc8, v4.18-rc7, v4.18-rc6, v4.18-rc5, v4.18-rc4, v4.18-rc3, v4.18-rc2, v4.18-rc1, v4.17, v4.17-rc7, v4.17-rc6, v4.17-rc5, v4.17-rc4, v4.17-rc3, v4.17-rc2, v4.17-rc1, v4.16, v4.16-rc7, v4.16-rc6, v4.16-rc5, v4.16-rc4, v4.16-rc3, v4.16-rc2, v4.16-rc1, v4.15, v4.15-rc9, v4.15-rc8, v4.15-rc7, v4.15-rc6, v4.15-rc5, v4.15-rc4, v4.15-rc3, v4.15-rc2, v4.15-rc1, v4.14 |
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8f34fe4a |
| 10-Nov-2017 |
Justin Chen <[email protected]> |
ARM: brcmstb: Add entry for 7255
Add in BCM7255 entry and reorder entries to keep ascending order. Also moved 7278 cause it was out of order.
Signed-off-by: Justin Chen <[email protected]> Sign
ARM: brcmstb: Add entry for 7255
Add in BCM7255 entry and reorder entries to keep ascending order. Also moved 7278 cause it was out of order.
Signed-off-by: Justin Chen <[email protected]> Signed-off-by: Florian Fainelli <[email protected]>
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56e4446d |
| 23-Feb-2018 |
Doug Berger <[email protected]> |
ARM: brcmstb: Add support for the V7 memory map
The 7278 device is the first device that includes support for the V7 memory map developed for use in 64-bit architecture brcmstb devices. This map rel
ARM: brcmstb: Add support for the V7 memory map
The 7278 device is the first device that includes support for the V7 memory map developed for use in 64-bit architecture brcmstb devices. This map relocates the register physical offset from 0xF0000000 to 0x0000000008000000.
Since the ARM PERIPHBASE value is also relocated in the V7 memory map we can use its value to determine whether this device uses the new V7 memory map and therefore where to look for the SUN_TOP_CTRL register used to identify the chip family.
Signed-off-by: Doug Berger <[email protected]> Signed-off-by: Florian Fainelli <[email protected]>
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Revision tags: v4.14-rc8, v4.14-rc7, v4.14-rc6, v4.14-rc5, v4.14-rc4, v4.14-rc3, v4.14-rc2, v4.14-rc1, v4.13 |
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c1496352 |
| 29-Aug-2017 |
Florian Fainelli <[email protected]> |
ARM: brcmstb: Add appropriate ARM_BE8() macros for swapping
Building a big-endian kernel for ARCH_BRCMSTB revealed that we would not be correctly polling for the right bit in the busyuart macro, tur
ARM: brcmstb: Add appropriate ARM_BE8() macros for swapping
Building a big-endian kernel for ARCH_BRCMSTB revealed that we would not be correctly polling for the right bit in the busyuart macro, turns out there are a few transformations needed to work with big-endian kernels. First we need to swap the value we read from SUN_TOP_CTRL to properly compare it against our local tables. Then, just like 8250.S we need to swap the value before storing it, and conversely swap it after a load.
Signed-off-by: Florian Fainelli <[email protected]>
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Revision tags: v4.13-rc7, v4.13-rc6, v4.13-rc5, v4.13-rc4, v4.13-rc3, v4.13-rc2, v4.13-rc1, v4.12, v4.12-rc7, v4.12-rc6, v4.12-rc5, v4.12-rc4, v4.12-rc3, v4.12-rc2, v4.12-rc1, v4.11, v4.11-rc8, v4.11-rc7, v4.11-rc6, v4.11-rc5, v4.11-rc4, v4.11-rc3, v4.11-rc2 |
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d47b51ad |
| 09-Mar-2017 |
Florian Fainelli <[email protected]> |
ARM: brcmstb: Add entry for 7260
BCM7260 has the same UART base address as 7268, order the entries by ascending chip number and alias the 7268 definition to the 7260 definition.
Signed-off-by: Flor
ARM: brcmstb: Add entry for 7260
BCM7260 has the same UART base address as 7268, order the entries by ascending chip number and alias the 7268 definition to the 7260 definition.
Signed-off-by: Florian Fainelli <[email protected]>
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Revision tags: v4.11-rc1, v4.10, v4.10-rc8, v4.10-rc7, v4.10-rc6, v4.10-rc5, v4.10-rc4, v4.10-rc3, v4.10-rc2, v4.10-rc1, v4.9, v4.9-rc8, v4.9-rc7, v4.9-rc6, v4.9-rc5, v4.9-rc4, v4.9-rc3, v4.9-rc2, v4.9-rc1, v4.8, v4.8-rc8, v4.8-rc7, v4.8-rc6, v4.8-rc5, v4.8-rc4, v4.8-rc3, v4.8-rc2, v4.8-rc1, v4.7, v4.7-rc7, v4.7-rc6 |
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d0cf9d8a |
| 28-Jun-2016 |
Florian Fainelli <[email protected]> |
ARM: brcmstb: Add earlyprintk support using run-time checks
The SUN_TOP_CTRL_FAMILY_ID register is at a fixed absolute address for all of our supported chips, so utilize its value to determine what
ARM: brcmstb: Add earlyprintk support using run-time checks
The SUN_TOP_CTRL_FAMILY_ID register is at a fixed absolute address for all of our supported chips, so utilize its value to determine what the UARTA base address should be based on the value we read.
Since the code is called both during decompressor when the MMU is off, and after the MMU has been turned on in the kernel, and we want to do the lookup only once, we use the same technique as tegra.S and have a shared storage location between the decompressor and the kernel.
Signed-off-by: Florian Fainelli <[email protected]>
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