irqdomain: Rename irq_set_default_host() to irq_set_default_domain()

Naming interrupt domains host is confusing at best and the irqdomain code
uses both domain and host inconsistently.

Therefore re

irqdomain: Rename irq_set_default_host() to irq_set_default_domain()

Naming interrupt domains host is confusing at best and the irqdomain code
uses both domain and host inconsistently.

Therefore rename irq_set_default_host() to irq_set_default_domain().

Signed-off-by: Jiri Slaby (SUSE) <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Link: https://lore.kernel.org/all/[email protected]

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arch/arc/kernel/: fix misspellings using codespell tool

Some typos are found out by codespell tool:

./intc-compact.c:145: prioity ==> priority
./smp.c:286: recevier ==> receiver
./stacktrace.c:152

arch/arc/kernel/: fix misspellings using codespell tool

Some typos are found out by codespell tool:

./intc-compact.c:145: prioity ==> priority
./smp.c:286: recevier ==> receiver
./stacktrace.c:152 prelogue ==> prologue

Fix typos found by codespell.

Reported-by: Zeal Robot <[email protected]>
Signed-off-by: Changcheng Deng <[email protected]>
Signed-off-by: Yi Wang <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of th

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Enrico Weigelt <[email protected]>
Reviewed-by: Kate Stewart <[email protected]>
Reviewed-by: Allison Randal <[email protected]>
Cc: [email protected]
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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ARCv2: SMP: Mask only private-per-core IRQ lines on boot at core intc

Recent commit a8ec3ee861b6 "arc: Mask individual IRQ lines during core
INTC init" breaks interrupt handling on ARCv2 SMP systems

ARCv2: SMP: Mask only private-per-core IRQ lines on boot at core intc

Recent commit a8ec3ee861b6 "arc: Mask individual IRQ lines during core
INTC init" breaks interrupt handling on ARCv2 SMP systems.

That commit masked all interrupts at onset, as some controllers on some
boards (customer as well as internal), would assert interrutps early
before any handlers were installed. For SMP systems, the masking was
done at each cpu's core-intc. Later, when the IRQ was actually
requested, it was unmasked, but only on the requesting cpu.

For "common" interrupts, which were wired up from the 2nd level IDU
intc, this was as issue as they needed to be enabled on ALL the cpus
(given that IDU IRQs are by default served Round Robin across cpus)

So fix that by NOT masking "common" interrupts at core-intc, but instead
at the 2nd level IDU intc (latter already being done in idu_of_init())

Fixes: a8ec3ee861b6 ("arc: Mask individual IRQ lines during core INTC init")
Signed-off-by: Alexey Brodkin <[email protected]>
[vgupta: reworked changelog, removed the extraneous idu_irq_mask_raw()]
Signed-off-by: Vineet Gupta <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>

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arc: Mask individual IRQ lines during core INTC init

ARC cores on reset have all interrupt lines of built-in INTC enabled.
Which means once we globally enable interrupts (very early on boot)
faulty

arc: Mask individual IRQ lines during core INTC init

ARC cores on reset have all interrupt lines of built-in INTC enabled.
Which means once we globally enable interrupts (very early on boot)
faulty hardware blocks may trigger an interrupt that Linux kernel
cannot handle yet as corresponding handler is not yet installed.

In that case system falls in "interrupt storm" and basically never
does anything useful except entering and exiting generic IRQ handling
code.

One real example of that kind of problematic hardware is DW GMAC which
also has interrupts enabled on reset and if Ethernet PHY informs GMAC
about link state, GMAC immediately reports that upstream to ARC core
and here we are.

Now with that change we mask all individual IRQ lines making entire
system more fool-proof.

[This patch was motivated by Adaptrum platform support]

Signed-off-by: Alexey Brodkin <[email protected]>
Cc: Eugeniy Paltsev <[email protected]>
Tested-by: Alexandru Gagniuc <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: [intc-*]: confine NR_CPU_IRQS to intc code

And even this willl change in subsequent patches where we resort to
using run time info instead...

Signed-off-by: Vineet Gupta <[email protected]>

ARC: IRQ: Use hwirq instead of virq in mask/unmask

It is necessary to use hwirq instead of virq when you communicate
with an interrupt controller since there is no guaranty that virq
numbers match h

ARC: IRQ: Use hwirq instead of virq in mask/unmask

It is necessary to use hwirq instead of virq when you communicate
with an interrupt controller since there is no guaranty that virq
numbers match hwirq numbers.

Signed-off-by: Yuriy Kolerov <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: [intc-compact] simplify code for 2 priority levels

ARC700 support for 2 interrupt priorities historically allowed even slow
perpherals such as emac and uart to setup high priority interrupts
wh

ARC: [intc-compact] simplify code for 2 priority levels

ARC700 support for 2 interrupt priorities historically allowed even slow
perpherals such as emac and uart to setup high priority interrupts
which was wrong from the beginning as they could possibly delay the more
critical timer interrupt.

The hardware support for 2 level interrupts in ARCompact is less than
ideal anyways (judging from the "hacks" in low level entry code and thus
is not used in productions systems I know of.

So reduce the scope of this to timer only, thereby reducing a bunch of
complexity.

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: [intc-*] switch to linear domain

Now that we have Timers probed from DT, don't need legacy domain

This however requires mapping to be called explicitly for the IRQ which
still can't (and proba

ARC: [intc-*] switch to linear domain

Now that we have Timers probed from DT, don't need legacy domain

This however requires mapping to be called explicitly for the IRQ which
still can't (and probably never) be probed from DT such as IPI and
SOFTIRQ

Acked-by: Marc Zyngier <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: [intc-*] Do a domain lookup in primary handler for hwirq -> linux virq

The primary interrupt handler arch_do_IRQ() was passing hwirq as linux
virq to core code. This was fragile and worked so f

ARC: [intc-*] Do a domain lookup in primary handler for hwirq -> linux virq

The primary interrupt handler arch_do_IRQ() was passing hwirq as linux
virq to core code. This was fragile and worked so far as we only had legacy/linear
domains.

This came out of a rant by Marc Zyngier.
http://lists.infradead.org/pipermail/linux-snps-arc/2015-December/000298.html

Cc: Marc Zyngier <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Noam Camus <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: clockevent: DT based probe

- timer frequency is derived from DT (no longer rely on top level
DT "clock-frequency" probed early and exported by asm/clk.h)

- TIMER0_IRQ need not be exported

ARC: clockevent: DT based probe

- timer frequency is derived from DT (no longer rely on top level
DT "clock-frequency" probed early and exported by asm/clk.h)

- TIMER0_IRQ need not be exported across arch code, confined to intc as
it is property of same

- Any failures in clockevent setup are considered pedantic and system
panic()'s as there is no generic fallback (unlike clocksource where
a jiffies based soft clocksource always exists)

Acked-by: Daniel Lezcano <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: [intc-compact] setup TIMER as percpu_dev

This removes the quirk from arc_request_percpu_irq() and paves way for
future simplifications

Signed-off-by: Vineet Gupta <[email protected]>

ARC: [intc-compact] Remove IPI setup from ARCompact port

There is no real ARC700 based SMP SoC so remove IPI definition.
EZChip's SMP ARC700 is going to use a different intc and IPI provider
anyways

ARC: [intc-compact] Remove IPI setup from ARCompact port

There is no real ARC700 based SMP SoC so remove IPI definition.
EZChip's SMP ARC700 is going to use a different intc and IPI provider
anyways.

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: smp: irqchip: handle IPI as percpu irq like timer

The reason this was not done so far was lack of genuine IPI_IRQ for
ARC700, as we don't have a SMP version of core yet (which might change
soon

ARC: smp: irqchip: handle IPI as percpu irq like timer

The reason this was not done so far was lack of genuine IPI_IRQ for
ARC700, as we don't have a SMP version of core yet (which might change
soon thx to EZChip). Nevertheles to increase the build coverage, we
need to allow CONFIG_SMP for ARC700 and still be able to run it on a
UP platform (nsim or AXS101) with a UP Device Tree (SMP-on-UP)

The build itself requires some define for IPI_IRQ and even a dummy
value is fine since that code won't run anyways.

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: [arcompact] don't check for hard isr calling local_irq_enable()

Historically this was done by ARC IDE driver, which is long gone.
IRQ core is pretty robust now and already checks if IRQs are en

ARC: [arcompact] don't check for hard isr calling local_irq_enable()

Historically this was done by ARC IDE driver, which is long gone.
IRQ core is pretty robust now and already checks if IRQs are enabled
in hard ISRs. Thus no point in checking this in arch code, for every
call of irq enabled.

Further if some driver does do that - let it bring down the system so we
notice/fix this sooner than covering up for sucker

This makes local_irq_enable() - for L1 only case atleast simple enough
so we can inline it.

Signed-off-by: Vineet Gupta <[email protected]>

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arc:irqchip: prepare for drivers/irqchip/irqchip.h removal

The IRQCHIP_DECLARE macro migrated to 'include/linux/irqchip.h'.

See commit 91e20b5040c67c51aad88cf87db4305c5bd7f79d
("irqchip: Move IRQCH

arc:irqchip: prepare for drivers/irqchip/irqchip.h removal

The IRQCHIP_DECLARE macro migrated to 'include/linux/irqchip.h'.

See commit 91e20b5040c67c51aad88cf87db4305c5bd7f79d
("irqchip: Move IRQCHIP_DECLARE macro to include/linux/irqchip.h").

This patch removes the inclusions of private header 'drivers/irqchip/irqchip.h'
and if necessary replaces them with inclusions of 'include/linux/irqchip.h'.

Signed-off-by: Joel Porquet <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: intc: split into ARCompact ISA specific, common bits

Signed-off-by: Vineet Gupta <[email protected]>