ARC: __switch_to: asm with dwarf ops (vs. inline asm)

__switch_to() is final step of context switch, swapping kernel modes
stack (and callee regs) of outgoing task with next task.

It is also the st

ARC: __switch_to: asm with dwarf ops (vs. inline asm)

__switch_to() is final step of context switch, swapping kernel modes
stack (and callee regs) of outgoing task with next task.

It is also the starting point of stack unwinging of a sleeping task and
captures SP, FP, BLINK and the corresponding dwarf info. Back when
dinosaurs still roamed around, ARC gas didn't support CFI pseudo ops and
gcc was responsible for generating dwarf info. Thus it had to be written
in "C" with inline asm to do the hand crafting of stack. The function
prologue (and crucial saving of blink etc) was still gcc generated but
not visible in code. Likewise dwarf info was missing.

Now with modern tools, we can make things more obvious by writing the
code in asm and adding approproate dwarf cfi pseudo ops.

This is mostly non functional change, except for slight chnages to asm

- ARCompact doesn't support MOV_S fp, sp, so we use MOV

Signed-off-by: Vineet Gupta <[email protected]>

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kbuild: use obj-y instead extra-y for objects placed at the head

The objects placed at the head of vmlinux need special treatments:

- arch/$(SRCARCH)/Makefile adds them to head-y in order to place

kbuild: use obj-y instead extra-y for objects placed at the head

The objects placed at the head of vmlinux need special treatments:

- arch/$(SRCARCH)/Makefile adds them to head-y in order to place
them before other archives in the linker command line.

- arch/$(SRCARCH)/kernel/Makefile adds them to extra-y instead of
obj-y to avoid them going into built-in.a.

This commit gets rid of the latter.

Create vmlinux.a to collect all the objects that are unconditionally
linked to vmlinux. The objects listed in head-y are moved to the head
of vmlinux.a by using 'ar m'.

With this, arch/$(SRCARCH)/kernel/Makefile can consistently use obj-y
for builtin objects.

There is no *.o that is directly linked to vmlinux. Drop unneeded code
in scripts/clang-tools/gen_compile_commands.py.

$(AR) mPi needs 'T' to workaround the llvm-ar bug. The fix was suggested
by Nathan Chancellor [1].

[1]: https://lore.kernel.org/llvm/[email protected]/

Signed-off-by: Masahiro Yamada <[email protected]>
Tested-by: Nick Desaulniers <[email protected]>
Reviewed-by: Nicolas Schier <[email protected]>

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arc: ptrace: hard-code "arc" instead of UTS_MACHINE

ARC uses the UTS_MACHINE defined in the top Makefile as follows:

UTS_MACHINE := $(ARCH)

We know it is "arc" when we are building the kerne

arc: ptrace: hard-code "arc" instead of UTS_MACHINE

ARC uses the UTS_MACHINE defined in the top Makefile as follows:

UTS_MACHINE := $(ARCH)

We know it is "arc" when we are building the kernel for ARC.
Hard-code user_regset_view::name, like many other architectures do.

Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARCv2: fpu: preserve userspace fpu state

Signed-off-by: Vineet Gupta <[email protected]>

ARC: ARCv2: jump label: implement jump label patching

Implement jump label patching for ARC. Jump labels provide
an interface to generate dynamic branches using
self-modifying code.

This allows us

ARC: ARCv2: jump label: implement jump label patching

Implement jump label patching for ARC. Jump labels provide
an interface to generate dynamic branches using
self-modifying code.

This allows us to implement conditional branches where
changing branch direction is expensive but branch selection
is basically 'free'

This implementation uses 32-bit NOP and BRANCH instructions
which forced to be aligned by 4 to guarantee that they don't
cross L1 cache line boundary and can be update atomically.

Signed-off-by: Eugeniy Paltsev <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of th

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Enrico Weigelt <[email protected]>
Reviewed-by: Kate Stewart <[email protected]>
Reviewed-by: Allison Randal <[email protected]>
Cc: [email protected]
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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ARC: Remove empty kernel/pcibios.c

ARC requires no arch-specific pcibios hooks, so delete this empty file.

Signed-off-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Bjorn Helgaas <bhelgaas@

ARC: Remove empty kernel/pcibios.c

ARC requires no arch-specific pcibios hooks, so delete this empty file.

Signed-off-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>

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clocksource: import ARC timer driver

This adds support for

- CONFIG_ARC_TIMERS : legacy 32-bit TIMER0 and TIMER1 which count UP
from @CNT to @LIMIT, before optionally triggering an interrupt.

clocksource: import ARC timer driver

This adds support for

- CONFIG_ARC_TIMERS : legacy 32-bit TIMER0 and TIMER1 which count UP
from @CNT to @LIMIT, before optionally triggering an interrupt.
These are programmed using ARC auxiliary register interface.
These are present in all ARC cores (ARC700 and ARC HS38)
TIMER0 serves as clockevent for all ARC linux builds.
TIMER1 is used for clocksource in arc700 builds.

- CONFIG_ARC_TIMERS_64BIT: 64-bit counters, RTC and GFRC found in
ARC HS38 cores. These are independnet IP blocks with different
programming model respectively.

Link: http://lkml.kernel.org/r/20161111231132.GA4186@mai
Acked-by: Daniel Lezcano <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: RIP arc_{get|set}_core_freq() clk API

There are no more users of this - so RIP!

Signed-off-by: Alexey Brodkin <[email protected]>
[vgupta: update changelog]
Signed-off-by: Vineet Gupta <vg

ARC: RIP arc_{get|set}_core_freq() clk API

There are no more users of this - so RIP!

Signed-off-by: Alexey Brodkin <[email protected]>
[vgupta: update changelog]
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: Add PCI support

Add PCI support to ARC and update drivers/pci Makefile enabling the ARC
arch to use the generic PCI setup functions.

[bhelgaas: fold in Joao's pci-dma-compat.h & pci-bridge.h b

ARC: Add PCI support

Add PCI support to ARC and update drivers/pci Makefile enabling the ARC
arch to use the generic PCI setup functions.

[bhelgaas: fold in Joao's pci-dma-compat.h & pci-bridge.h build fix (I
should have caught this myself, sorry]
Signed-off-by: Joao Pinto <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Vineet Gupta <[email protected]>

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ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al

Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

ARCv2: Support for ARCv2 ISA and HS38x cores

The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Archit

ARCv2: Support for ARCv2 ISA and HS38x cores

The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: intc: split into ARCompact ISA specific, common bits

Signed-off-by: Vineet Gupta <[email protected]>

ARC: entry.S: split into ARCompact ISA specific, common bits

Signed-off-by: Vineet Gupta <[email protected]>

ARC: rename kconfig option for unaligned emulation

Signed-off-by: Vineet Gupta <[email protected]>

ARC: Add perf support for ARC700 cores

This adds basic perf support for ARC700 cores. Most PERF_COUNT_HW* events
are supported now.

Signed-off-by: Mischa Jonker <[email protected]>
Acked-by: Pet

ARC: Add perf support for ARC700 cores

This adds basic perf support for ARC700 cores. Most PERF_COUNT_HW* events
are supported now.

Signed-off-by: Mischa Jonker <[email protected]>
Acked-by: Peter Zijlstra <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: Hostlink Pseudo-Driver for Metaware Debugger

This allows ARC Target to do I/O to host in absence of any peripherals
whatsoever, assisted by Metaware Hostlink facility.

Further we have a FUSE b

ARC: Hostlink Pseudo-Driver for Metaware Debugger

This allows ARC Target to do I/O to host in absence of any peripherals
whatsoever, assisted by Metaware Hostlink facility.

Further we have a FUSE based filesystem which makes us mount/access host
filesystem on target and do fops.

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: kgdb support

Signed-off-by: Mischa Jonker <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>
Cc: Jason Wessel <[email protected]>
Acked-by: Jason Wessel <jason.we

ARC: kgdb support

Signed-off-by: Mischa Jonker <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>
Cc: Jason Wessel <[email protected]>
Acked-by: Jason Wessel <[email protected]>

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ARC: Unaligned access emulation

ARC700 doesn't natively support unaligned access, but can be emulated
-Unaligned Access Exception
-Disassembly at the Fault address to find the exact insn (long/short

ARC: Unaligned access emulation

ARC700 doesn't natively support unaligned access, but can be emulated
-Unaligned Access Exception
-Disassembly at the Fault address to find the exact insn (long/short)

Also per Arnd's comment, we runtime control it using 2 sysctl knobs:
* SYSCTL_ARCH_UNALIGN_ALLOW: Runtime enable/disble
* SYSCTL_ARCH_UNALIGN_NO_WARN: Warn on each emulation attempt

Originally contributed by Tim Yao <[email protected]>

Signed-off-by: Vineet Gupta <[email protected]>
Cc: Tim Yao <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>

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ARC: kprobes support

Origin port done by Rajeshwar Ranga

Signed-off-by: Vineet Gupta <[email protected]>
Cc: Rajeshwar Ranga <[email protected]>

ARC: disassembly (needed by kprobes/kgdb/unaligned-access-emul)

In-kernel disassembler

Due Credits
* Orig written by Rajeshwar Ranga
* Consolidation/cleanups by Mischa Jonker

Signed-off-by: Vineet

ARC: disassembly (needed by kprobes/kgdb/unaligned-access-emul)

In-kernel disassembler

Due Credits
* Orig written by Rajeshwar Ranga
* Consolidation/cleanups by Mischa Jonker

Signed-off-by: Vineet Gupta <[email protected]>
Cc: Rajeshwar Ranga <[email protected]>
Cc: Mischa Jonker <[email protected]>

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ARC: DWARF2 .debug_frame based stack unwinder

-Originally written by Rajeshwar Ranga
-Derived off of generic unwinder in 2.6.19 and adapted to ARC

Signed-off-by: Vineet Gupta <[email protected]>

ARC: DWARF2 .debug_frame based stack unwinder

-Originally written by Rajeshwar Ranga
-Derived off of generic unwinder in 2.6.19 and adapted to ARC

Signed-off-by: Vineet Gupta <[email protected]>
Cc: Rajeshwar Ranga <[email protected]>

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ARC: SMP support

ARC common code to enable a SMP system + ISS provided SMP extensions.

ARC700 natively lacks SMP support, hence some of the core features are
are only enabled if SoCs have the neces

ARC: SMP support

ARC common code to enable a SMP system + ISS provided SMP extensions.

ARC700 natively lacks SMP support, hence some of the core features are
are only enabled if SoCs have the necessary h/w pixie-dust. This
includes:
-Inter Processor Interrupts (IPI)
-Cache coherency
-load-locked/store-conditional
...

The low level exception handling would be completely broken in SMP
because we don't have hardware assisted stack switching. Thus a fair bit
of this code is repurposing the MMU_SCRATCH reg for event handler
prologues to keep them re-entrant.

Many thanks to Rajeshwar Ranga for his initial "major" contributions to
SMP Port (back in 2008), and to Noam Camus and Gilad Ben-Yossef for help
with resurrecting that in 3.2 kernel (2012).

Note that this platform code is again singleton design pattern - so
multiple SMP platforms won't build at the moment - this deficiency is
addressed in subsequent patches within this series.

Signed-off-by: Vineet Gupta <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Rajeshwar Ranga <[email protected]>
Cc: Noam Camus <[email protected]>
Cc: Gilad Ben-Yossef <[email protected]>

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ARC: Module support

Signed-off-by: Vineet Gupta <[email protected]>

ARC: ptrace support

Signed-off-by: Vineet Gupta <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>