ARC: Fix typos

Fix typos, most reported by "codespell arch/arc". Only touches comments,
no code changes.

Signed-off-by: Bjorn Helgaas <[email protected]>
Signed-off-by: Vineet Gupta <vgupta@kern

ARC: Fix typos

Fix typos, most reported by "codespell arch/arc". Only touches comments,
no code changes.

Signed-off-by: Bjorn Helgaas <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: entry: move ARCompact specific bits out of entry.h

- PUSHAUX/POPAUX helpers to ARCompact entry
- use gas provided "push"/pop pseudo instructions

Signed-off-by: Vineet Gupta <[email protected]

ARC: entry: move ARCompact specific bits out of entry.h

- PUSHAUX/POPAUX helpers to ARCompact entry
- use gas provided "push"/pop pseudo instructions

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: entry: SAVE_ABI_CALLEE_REG: ISA/ABI specific helper

And for ARcompact variant replace the PUSH/POP macros with gas provided
push/pop pseudo-instructions

This allows ISA specific implementation

ARC: entry: SAVE_ABI_CALLEE_REG: ISA/ABI specific helper

And for ARcompact variant replace the PUSH/POP macros with gas provided
push/pop pseudo-instructions

This allows ISA specific implementation

e.g. Current ARCv2 PUSH/POP could be replaced with STD/LDL to save 2
registers at a time (w/o bothering with SP update each time) or
perhaps use ENTER_S/LEAVE_S to reduce code size

For ARCv3 ABI changed so callee regs are now r14-r26 (vs. r13-r25)
thus would need a different implementation.

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: entry: Add more common chores to EXCEPTION_PROLOGUE

THe high level structure of most ARC exception handlers is
1. save regfile with EXCEPTION_PROLOGUE
2. setup r0: EFA (not part of pt_regs)

ARC: entry: Add more common chores to EXCEPTION_PROLOGUE

THe high level structure of most ARC exception handlers is
1. save regfile with EXCEPTION_PROLOGUE
2. setup r0: EFA (not part of pt_regs)
3. setup r1: pointer to pt_regs (SP)
4. drop down to pure kernel mode (from exception)
5. call the Linux "C" handler

Remove the boiler plate code by moving #2, #3, #4 into #1.

The exceptions to most exceptions are syscall Trap and Machine check
which don't do some of above for various reasons, so call a newly
introduced variant EXCEPTION_PROLOGUE_KEEP_AE (same as original
EXCEPTION_PROLOGUE)

Tested-by: Pavel Kozlov <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: entry: rework (non-functional)

- comments update
- rename syscall_trace_entry
- use PT_xxx in entry code

Signed-off-by: Vineet Gupta <[email protected]>

ARC: entry: use gp to cache task pointer (vs. r25)

The motivation is eventual ABI considerations for ARCv3 but even without
it this change us worthwhile as diffstat reduces 100 net lines

r25 is a c

ARC: entry: use gp to cache task pointer (vs. r25)

The motivation is eventual ABI considerations for ARCv3 but even without
it this change us worthwhile as diffstat reduces 100 net lines

r25 is a callee saved register, normally not saved by entry code in
pt_regs. However because of its usage in CONFIG_ARC_CURR_IN_REG it needs
to be. This in turn requires a whole bunch of special casing when we
need to access r25. Then there is distinction between user mode r25 vs.
kernel mode r25 - hence distinct SAVE_CALLEE_SAVED_{USER,KERNEL}

Instead use gp which is a scratch register and thus saved already in entry
code. This cleans things up significantly and much nocer on eyes:

- SAVE_CALLEE_SAVED_{USER,KERNEL} are now exactly same
- no special user_r25 slot in pt_reggs

Note that typical global asm registers are callee-saved (r25), but gp is
not callee-saved thus needs additional -ffixed-<reg> toggle

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: Fix comment typo

Change 'seperate' to 'separate'.

Signed-off-by: Zhang Jiaming <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only

MMU SCRATCH_DATA0 register is intended to cache task pgd. However in
ARC700 SMP port, it has to be repurposed for re-entrant inter

ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only

MMU SCRATCH_DATA0 register is intended to cache task pgd. However in
ARC700 SMP port, it has to be repurposed for re-entrant interrupt
handling, while UP port doesn't. We currently handle these use-cases
using a fabricated #define which has usual issues of dependency nesting
and obvious ugliness.

So clean this up: for ARC700 don't use to cache pgd (even in UP) and do
the opposite for ARCv2.

And while here, switch to canonical pgd_offset().

Acked-by: Mike Rapoport <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARC: [plat-eznps]: Drop support for EZChip NPS platform

NPS customers are no longer doing active development, as evident from
rand config build failures reported in recent times, so drop support
for

ARC: [plat-eznps]: Drop support for EZChip NPS platform

NPS customers are no longer doing active development, as evident from
rand config build failures reported in recent times, so drop support
for NPS platform.

Tested-by: kernel test robot <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg

ARC700 exception (and intr handling) didn't have auto stack switching
thus had to rely on stashing a reg temporarily (t

ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg

ARC700 exception (and intr handling) didn't have auto stack switching
thus had to rely on stashing a reg temporarily (to free it up) at a
known place in memory, allowing to code up the low level stack switching.
This however was not re-entrant in SMP which thus had to repurpose the
per-cpu MMU SCRATCH DATA register otherwise used to "cache" the task pdg
pointer (vs. reading it from mm struct)

The newer HS cores do have auto-stack switching and thus even SMP builds
can use the MMU SCRATCH reg as originally intended.

This patch fixes the restriction to ARC700 SMP builds only

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: entry: EV_Trap expects r10 (vs. r9) to have exception cause

avoids 1 MOV instruction in light of double load/store code

Signed-off-by: Vineet Gupta <[email protected]>

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of th

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Enrico Weigelt <[email protected]>
Reviewed-by: Kate Stewart <[email protected]>
Reviewed-by: Allison Randal <[email protected]>
Cc: [email protected]
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>

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ARC: [arcompact] entry.S: minor code movement

This is a non functional code changw, which moves r25 restore from macro
into the caller of macro

Signed-off-by: Vineet Gupta <[email protected]>

ARC: [plat-eznps] handle extra aux regs #2: kernel/entry exit

Preserve eflags and gpa1 aux during entry/exit into kernel as these
could be modified by kernel mode

These registers used by compare ex

ARC: [plat-eznps] handle extra aux regs #2: kernel/entry exit

Preserve eflags and gpa1 aux during entry/exit into kernel as these
could be modified by kernel mode

These registers used by compare exchange instructions.
- GPA1 is used for compare value,
- EFLAGS got bit reflects atomic operation response.

EFLAGS is zeroed for each new user task so it won't get its
parent value.

Signed-off-by: Liav Rehana <[email protected]>
Signed-off-by: Noam Camus <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

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Fix typos

Signed-off-by: Andrea Gelmini <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

ARC: [plat-eznps] Use dedicated identity auxiliary register.

With generic "identity" num of CPUs is limited to 256 (8 bit).
We use our alternative AUX register GLOBAL_ID (12 bit).
Now we can support

ARC: [plat-eznps] Use dedicated identity auxiliary register.

With generic "identity" num of CPUs is limited to 256 (8 bit).
We use our alternative AUX register GLOBAL_ID (12 bit).
Now we can support up to 4096 CPUs.

Signed-off-by: Noam Camus <[email protected]>

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ARC: Fix misspellings in comments.

Signed-off-by: Adam Buchbinder <[email protected]>
Signed-off-by: Vineet Gupta <[email protected]>

ARC: [arcompact] entry.S: Improve early return from exception

The requirement is to
- Reenable Exceptions (AE cleared)
- Reenable Interrupts (E1/E2 set)

We need to do wiggle these bits into ERSTA

ARC: [arcompact] entry.S: Improve early return from exception

The requirement is to
- Reenable Exceptions (AE cleared)
- Reenable Interrupts (E1/E2 set)

We need to do wiggle these bits into ERSTATUS and call RTIE.

Prev version used the pre-exception STATUS32 as starting point for what
goes into ERSTATUS. This required explicit fixups of U/DE/L bits.

Instead, use the current (in-exception) STATUS32 as starting point.
Being in exception handler U/DE/L can be safely assumed to be correct.
Only AE/E1/E2 need to be fixed.

So the new implementation is slightly better
-Avoids read form memory
-Is 4 bytes smaller for the typical 1 level of intr configuration
-Depicts the semantics more clearly

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: intc: split into ARCompact ISA specific, common bits

Signed-off-by: Vineet Gupta <[email protected]>

ARC: entry.S: [arcompact] simplify SWITCH_TO_KERNEL_STK

Previously this macro was overloaded with stack switching, saving SP at right
slot in pt_regs, saving/setup of r25 and setting SP baseline to

ARC: entry.S: [arcompact] simplify SWITCH_TO_KERNEL_STK

Previously this macro was overloaded with stack switching, saving SP at right
slot in pt_regs, saving/setup of r25 and setting SP baseline to where
pt_regs->sp is saved (vs. bottom of pt_regs)

Now it only does SP switch, and leaves SP pointing to bottom of pt_regs.

r25 saving is no longer done here to allow for future reordering of
regfile in pt_regs w/o touching this macro

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: entry.S: micro-optimize Trap handler

Elide the need to re-read ECR in Trap handler by ensuring that
EXCEPTION_PROLOGUE does that at the very end just before returning
to Trap handler

ARCv2 EXC

ARC: entry.S: micro-optimize Trap handler

Elide the need to re-read ECR in Trap handler by ensuring that
EXCEPTION_PROLOGUE does that at the very end just before returning
to Trap handler

ARCv2 EXCEPTION_PROLOGUE already did that, so same for ARcompact and the
common trap handler adjusted to use cached ECR

Signed-off-by: Vineet Gupta <[email protected]>

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ARC: entry.S: split into ARCompact ISA specific, common bits

Signed-off-by: Vineet Gupta <[email protected]>