| 352f4a6b | 06-Mar-2025 |
Frank Li <[email protected]> |
dt-bindings: iio: adc: Add i.MX94 and i.MX95 support
Add compatible string "nxp,imx94-adc" and "nxp,imx95-adc", which is
backward compatible with i.MX93. Set it to fall back to "nxp,imx93-adc".
Sig
dt-bindings: iio: adc: Add i.MX94 and i.MX95 support
Add compatible string "nxp,imx94-adc" and "nxp,imx95-adc", which is
backward compatible with i.MX93. Set it to fall back to "nxp,imx93-adc".
Signed-off-by: Frank Li <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Jonathan Cameron <[email protected]>
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| f52b5daf | 28-Feb-2025 |
Alisa-Dariana Roman <[email protected]> |
dt-bindings: iio: adc: add AD7191
AD7191 is a pin-programmable, ultra-low noise 24-bit sigma-delta ADC
designed for precision bridge sensor measurements. It features two
differential analog input ch
dt-bindings: iio: adc: add AD7191
AD7191 is a pin-programmable, ultra-low noise 24-bit sigma-delta ADC
designed for precision bridge sensor measurements. It features two
differential analog input channels, selectable output rates,
programmable gain, internal temperature sensor and simultaneous
50Hz/60Hz rejection.
Signed-off-by: Alisa-Dariana Roman <[email protected]>
Reviewed-by: Rob Herring (Arm) <[email protected]>
Reviewed-by: David Lechner<[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Jonathan Cameron <[email protected]>
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| 94e4fc40 | 27-Feb-2025 |
Kever Yang <[email protected]> |
dt-bindings: iio: adc: Add rockchip,rk3562-saradc string
Add rockchip,rk3562-saradc compatible string.
The saradc on rk3562 is v2 controller, with 10bit width which is different
with rk3588.
Signed
dt-bindings: iio: adc: Add rockchip,rk3562-saradc string
Add rockchip,rk3562-saradc compatible string.
The saradc on rk3562 is v2 controller, with 10bit width which is different
with rk3588.
Signed-off-by: Kever Yang <[email protected]>
Acked-by: Rob Herring (Arm) <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Jonathan Cameron <[email protected]>
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| f3255b0e | 13-Feb-2025 |
Tobias Sperling <[email protected]> |
dt-bindings: iio: adc: Introduce ADS7138
Add documentation for the driver of ADS7128 and ADS7138 12-bit, 8-channel
analog-to-digital converters. These ADCs have a wide operating range and
a wide fea
dt-bindings: iio: adc: Introduce ADS7138
Add documentation for the driver of ADS7128 and ADS7138 12-bit, 8-channel
analog-to-digital converters. These ADCs have a wide operating range and
a wide feature set. Communication is based on the I2C interface.
ADS7128 differs in the addition of further hardware features, like a
root-mean-square (RMS) and a zero-crossing-detect (ZCD) module.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Tobias Sperling <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Jonathan Cameron <[email protected]>
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| 8de148c0 | 14-Feb-2025 |
Esteban Blanc <[email protected]> |
dt-bindings: iio: adc: add ADI ad4030, ad4630 and ad4632
This adds a binding specification for the Analog Devices Inc. AD4030,
AD4630 and AD4632 families of ADCs.
- ad4030-24 is a 1 channel SAR ADC
dt-bindings: iio: adc: add ADI ad4030, ad4630 and ad4632
This adds a binding specification for the Analog Devices Inc. AD4030,
AD4630 and AD4632 families of ADCs.
- ad4030-24 is a 1 channel SAR ADC with 24 bits of precision and a
sampling rate of 2M samples per second
- ad4032-24 is a 1 channel SAR ADC with 24 bits of precision and a
sampling rate of 500K samples per second
- ad4630-16 is a 2 channels SAR ADC with 16 bits of precision and a
sampling rate of 2M samples per second
- ad4630-24 is a 2 channels SAR ADC with 24 bits of precision and a
sampling rate of 2M samples per second
- ad4632-16 is a 2 channels SAR ADC with 16 bits of precision and a
sampling rate of 500K samples per second
- ad4632-24 is a 2 channels SAR ADC with 24 bits of precision and a
sampling rate of 500K samples per second
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Esteban Blanc <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Jonathan Cameron <[email protected]>
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| 4831509f | 14-Feb-2025 |
Antoniu Miclaus <[email protected]> |
dt-bindings: iio: adc: add ad485x axi variant
Add a new compatible and related bindings for the fpga-based
AD485x AXI IP core, a variant of the generic AXI ADC IP.
The AXI AD485x IP is a very simil
dt-bindings: iio: adc: add ad485x axi variant
Add a new compatible and related bindings for the fpga-based
AD485x AXI IP core, a variant of the generic AXI ADC IP.
The AXI AD485x IP is a very similar HDL (fpga) variant of the
generic AXI ADC IP, intended to control ad485x family.
Although this is not preferred, the wildcard naming is used to
match the published firmware under the same name.
Signed-off-by: Antoniu Miclaus <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Jonathan Cameron <[email protected]>
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| f2ae1809 | 10-Feb-2025 |
Guillaume Stols <[email protected]> |
dt-bindings: iio: dac: adi-axi-adc: add ad7606 variant
A new compatible is added to reflect the specialized version of the HDL.
We use the parallel interface to write the ADC's registers, and
access
dt-bindings: iio: dac: adi-axi-adc: add ad7606 variant
A new compatible is added to reflect the specialized version of the HDL.
We use the parallel interface to write the ADC's registers, and
accessing this interface requires to use ADI_AXI_REG_CONFIG_RD,
ADI_AXI_REG_CONFIG_WR and ADI_AXI_REG_CONFIG_CTRL in a custom fashion.
Reviewed-by: Rob Herring (Arm) <[email protected]>
Signed-off-by: Guillaume Stols <[email protected]>
Co-developed-by: Angelo Dureghello <[email protected]>
Signed-off-by: Angelo Dureghello <[email protected]>
Link: https://patch.msgid.link/20250210-wip-bl-ad7606_add_backend_sw_mode-v4-1-160df18b1da7@baylibre.com
Signed-off-by: Jonathan Cameron <[email protected]>
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| c54b9094 | 02-Dec-2024 |
Marcelo Schmitt <[email protected]> |
dt-bindings: iio: adc: adi,ad4000: Add PulSAR
Extend the AD4000 series device tree documentation to also describe
PulSAR devices.
The single-channel series of PulSAR devices is similar to the AD400
dt-bindings: iio: adc: adi,ad4000: Add PulSAR
Extend the AD4000 series device tree documentation to also describe
PulSAR devices.
The single-channel series of PulSAR devices is similar to the AD4000 series
except PulSAR devices sample at slower rates and don't have a
configuration register. Because PulSAR devices don't have a configuration
register, they don't support all features of AD4000 devices and thus fewer
interfaces are provided to user space. Also, while AD4000 may have their
SDI pin connected to SPI host MOSI line, PulSAR SDI pin is never connected
to MOSI.
Some devices within the PulSAR series are just faster versions of others.
>From fastest to slowest, AD7980, AD7988-5, AD7686, AD7685, and AD7988-1 are
all 16-bit pseudo-differential pin-for-pin compatible ADCs. Devices that
only vary on the sample rate are documented with a common fallback
compatible.
Signed-off-by: Marcelo Schmitt <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://patch.msgid.link/cc05f1471c409ab38722cd0e80fd5857ff9ce5db.1733147444.git.marcelo.schmitt@analog.com
Signed-off-by: Jonathan Cameron <[email protected]>
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| fa6068fb | 06-Dec-2024 |
Uwe Kleine-König <[email protected]> |
dt-bindings: iio: adc: adi,ad7{124,173,192,780}: Allow specifications of a gpio for irq line
For the AD7124 chip and some of its cousins the logical irq line (R̅D̅Y̅)
is physically on the same pin a
dt-bindings: iio: adc: adi,ad7{124,173,192,780}: Allow specifications of a gpio for irq line
For the AD7124 chip and some of its cousins the logical irq line (R̅D̅Y̅)
is physically on the same pin as the spi MISO output (DOUT) and so
reading a register might trigger an interrupt. For correct operation
it's critical that the actual state of the pin can be read to judge if
an interrupt event is a real one or just a spurious one triggered by
toggling the line in its MISO mode.
Allow specification of an "rdy-gpios" property that references a GPIO
that can be used for that purpose. While this is typically the same GPIO
also used (implicitly) as interrupt source, it is still supposed that
the interrupt is specified as before and usual.
Acked-by: Conor Dooley <[email protected]>
Signed-off-by: Uwe Kleine-König <[email protected]>
Link: https://patch.msgid.link/7fc92a8539e55802d514332e70ee836a3ed08b66.1733504533.git.u.kleine-koenig@baylibre.com
Signed-off-by: Jonathan Cameron <[email protected]>
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| 19406b0a | 30-Oct-2024 |
Julien Stephan <[email protected]> |
dt-bindings: iio: adc: ad7380: add adaq4370-4 and adaq4380-4 compatible parts
adaq4370-4 (2MSPS) and adaq4380-4 (4MSPS) are quad-channel precision data
acquisition signal chain μModule solutions com
dt-bindings: iio: adc: ad7380: add adaq4370-4 and adaq4380-4 compatible parts
adaq4370-4 (2MSPS) and adaq4380-4 (4MSPS) are quad-channel precision data
acquisition signal chain μModule solutions compatible with the ad738x
family, with the following differences:
- pin selectable gain in front of each 4 adc
- internal reference is 3V derived from refin-supply (5V)
- additional supplies
To select the gain a new patternProperties is added to describe each
channel. It is restricted to adaq devices.
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Julien Stephan <[email protected]>
Reviewed-by: David Lechner <[email protected]>
Link: https://patch.msgid.link/20241030-ad7380-add-adaq4380-4-support-v4-1-864ff02babae@baylibre.com
Signed-off-by: Jonathan Cameron <[email protected]>
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| 7c2357b1 | 15-Oct-2024 |
Guillaume Stols <[email protected]> |
dt-bindings: iio: adc: ad7606: Add iio backend bindings
Add the required properties for iio-backend support, as well as an
example and the conditions to mutually exclude interruption and
conversion
dt-bindings: iio: adc: ad7606: Add iio backend bindings
Add the required properties for iio-backend support, as well as an
example and the conditions to mutually exclude interruption and
conversion trigger with iio-backend.
The iio-backend's function is to controls the communication, and thus the
interruption pin won't be available anymore.
As a consequence, the conversion pin must be controlled externally since
we will miss information about when every single conversion cycle (i.e
conversion + data transfer) ends, hence a PWM is introduced to trigger
the conversions.
Reviewed-by: Rob Herring (Arm) <[email protected]>
Signed-off-by: Guillaume Stols <[email protected]>
Link: https://patch.msgid.link/20241015-ad7606_add_iio_backend_support-v5-2-654faf1ae08c@baylibre.com
Signed-off-by: Jonathan Cameron <[email protected]>
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