| 944b074f | 11-Mar-2025 |
Andreas Kemnade <[email protected]> |
dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema
Convert the TI clkctrl clock device tree binding to json-schema.
Specify the creator of the original binding as a maintainer.
reg prope
dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema
Convert the TI clkctrl clock device tree binding to json-schema.
Specify the creator of the original binding as a maintainer.
reg property is used mostly with one item, in am3xxx also with
an arbitrary number of items, so divert from the original binding
specifying two (probably meaning one address and one size).
The consumer part of the example is left out because the full consumer
node would be needed.
Signed-off-by: Andreas Kemnade <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Rob Herring (Arm) <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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| 52dbf848 | 07-Mar-2025 |
Andre Przywara <[email protected]> |
dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs
The Allwinner A523/T527 SoCs have four CCUs, this adds the binding for
the main and the PRCM R-CCU.
The source clock list differs in som
dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs
The Allwinner A523/T527 SoCs have four CCUs, this adds the binding for
the main and the PRCM R-CCU.
The source clock list differs in some annoying details, and folding this
into the existing Allwinner CCU clock binding document gets quite
unwieldy, so create a new document for these CCUs.
Add the new compatible string, along with the required input clock
lists. This conditionally describes the input clock lists, to make
adding support for the other two CCUs easier.
Also add the DT binding headers, listing all the clocks with their ID
numbers.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Rob Herring (Arm) <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Chen-Yu Tsai <[email protected]>
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| d5992f1a | 18-Feb-2025 |
Ahmad Fatoum <[email protected]> |
dt-bindings: clock: imx8m: document nominal/overdrive properties
The imx8m-clock.yaml binding covers the clock controller inside all
of the i.MX8M Q/M/N/P SoCs. All of them have in common that they
dt-bindings: clock: imx8m: document nominal/overdrive properties
The imx8m-clock.yaml binding covers the clock controller inside all
of the i.MX8M Q/M/N/P SoCs. All of them have in common that they
support two operating modes: nominal and overdrive mode.
While the overdrive mode allows for higher frequencies for many IPs,
the nominal mode needs a lower SoC voltage, thereby reducing
heat generation and power usage.
As increasing clock rates beyond the maximum permitted by the supplied
SoC voltage can lead to difficult to debug issues, device tree consumers
would benefit from knowing what mode is active to enforce the clock rate
limits that come with it.
To facilitate this, extend the clock controller bindings with an
optional fsl,operating-mode property. This intentionally allows the
absence of the property, because there is no default suitable for all
boards:
For i.MX8M Mini and Nano, the kernel SoC DTSIs has assigned-clock-rates
that are all achievable in nominal mode. For i.MX8MP, there are some
rates only validated for overdrive mode.
But even for the i.MX8M Mini/Nano boards, we don't know what rates they
may configure at runtime, so it has not been possible so far to infer from
just the device tree what the mode is.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Ahmad Fatoum <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>
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| 2471a101 | 26-Feb-2025 |
Laurentiu Mihalcea <[email protected]> |
dt-bindings: clock: imx8mp: add axi clock
Some components of AUDIOMIX (i.e: DSP, OCRAM_A) are clocked by
AUDIO_AXI_CLK_ROOT. Since the AUDIOMIX block control manages the clock
gates for those compon
dt-bindings: clock: imx8mp: add axi clock
Some components of AUDIOMIX (i.e: DSP, OCRAM_A) are clocked by
AUDIO_AXI_CLK_ROOT. Since the AUDIOMIX block control manages the clock
gates for those components, include their root clock in the list of clocks
consumed by the IP.
Fixes: 95a0aa7bb10e ("dt-bindings: clock: imx8mp: Add audiomix block control")
Signed-off-by: Laurentiu Mihalcea <[email protected]>
Reviewed-by: Iuliana Prodan <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Abel Vesa <[email protected]>
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| 35b2b332 | 01-Mar-2025 |
Kaustabh Chakraborty <[email protected]> |
dt-bindings: clock: add clock definitions and documentation for exynos7870 CMU
Add unique identifiers for exynos7870 clocks for every bank. It adds all
clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_I
dt-bindings: clock: add clock definitions and documentation for exynos7870 CMU
Add unique identifiers for exynos7870 clocks for every bank. It adds all
clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and
CMU_PERI. Document the devicetree bindings as well.
Signed-off-by: Kaustabh Chakraborty <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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| 6662c09c | 23-Feb-2025 |
Ivaylo Ivanov <[email protected]> |
dt-bindings: clock: add Exynos2200 SoC
Provide dt-schema documentation for Exynos2200 SoC clock controller.
Add device tree clock binding definitions for the following CMU blocks:
- CMU_ALIVE
- CMU_
dt-bindings: clock: add Exynos2200 SoC
Provide dt-schema documentation for Exynos2200 SoC clock controller.
Add device tree clock binding definitions for the following CMU blocks:
- CMU_ALIVE
- CMU_CMGP
- CMU_HSI0
- CMU_PERIC0/1/2
- CMU_PERIS
- CMU_TOP
- CMU_UFS
- CMU_VTS
Signed-off-by: Ivaylo Ivanov <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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| 9a5cd596 | 21-Feb-2025 |
Friday Yang <[email protected]> |
dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188
On the MediaTek platform, some SMI LARBs are directly connected to
the SMI Common, while others are connected to the SMI Sub-Common,
whic
dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188
On the MediaTek platform, some SMI LARBs are directly connected to
the SMI Common, while others are connected to the SMI Sub-Common,
which in turn is connected to the SMI Common. The hardware block
diagram can be described as follows.
SMI-Common(Smart Multimedia Interface Common)
|
+----------------+------------------+
| | |
| | |
| | |
| | |
| | |
larb0 SMI-Sub-Common0 SMI-Sub-Common1
| | | | |
larb1 larb2 larb3 larb7 larb9
For previous discussion on the direction of the code modifications,
please refer to:
https://lore.kernel.org/all/CAFGrd9qZhObQXvm2_abqaX83xMLqxjQETB2=
[email protected]/
https://lore.kernel.org/all/CAPDyKFpokXV2gJDgowbixTvOH_5VL3B5H8ey
[email protected]/
On the MediaTek MT8188 SoC platform, we encountered power-off failures
and SMI bus hang issues during camera stress tests. The issue arises
because bus glitches are sometimes produced when MTCMOS powers on or
off. While this is fairly normal, the software must handle these
glitches to avoid mistaking them for transaction signals. What's
more, this issue emerged only after the initial upstreaming of this
binding. Without these patches, the SMI becomes unstable during camera
stress tests.
The software solutions can be summarized as follows:
1. Use CLAMP to disable the SMI sub-common port after turning off the
LARB CG and before turning off the LARB MTCMOS.
2. Use CLAMP to disable/enable the SMI sub-common port.
3. Implement an AXI reset for SMI LARBs.
This patch add '#reset-cells' for the clock controller located in image,
camera and IPE subsystems.
Signed-off-by: Friday Yang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Conor Dooley <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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| e0c0a97b | 17-Feb-2025 |
Yao Zi <[email protected]> |
dt-bindings: clock: Document clock and reset unit of RK3528
There are two types of clocks in RK3528 SoC, CRU-managed and
SCMI-managed. Independent IDs are assigned to them.
For the reset part, diff
dt-bindings: clock: Document clock and reset unit of RK3528
There are two types of clocks in RK3528 SoC, CRU-managed and
SCMI-managed. Independent IDs are assigned to them.
For the reset part, differing from previous Rockchip SoCs and
downstream bindings which embeds register offsets into the IDs, gapless
numbers starting from zero are used.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
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| 7fa119f5 | 04-Jan-2025 |
Igor Belwon <[email protected]> |
dt-bindings: clock: exynos990: Add CMU_PERIS block
Add CMU_PERIS block compatible, and clock definitions.
CMU_PERIS requires one bus clock dependency, and it's used for i.e the MCT.
Signed-off-by:
dt-bindings: clock: exynos990: Add CMU_PERIS block
Add CMU_PERIS block compatible, and clock definitions.
CMU_PERIS requires one bus clock dependency, and it's used for i.e the MCT.
Signed-off-by: Igor Belwon <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/20250104-exynos990-cmu-v1-1-9f54d69286d6@mentallysanemainliners.org
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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| 3e86e573 | 09-Jan-2025 |
Imran Shaik <[email protected]> |
dt-bindings: clock: qcom: Add QCS8300 video clock controller
The QCS8300 video clock controller is a derivative of SA8775P, but
QCS8300 has minor difference. Hence, reuse the SA8775P videocc binding
dt-bindings: clock: qcom: Add QCS8300 video clock controller
The QCS8300 video clock controller is a derivative of SA8775P, but
QCS8300 has minor difference. Hence, reuse the SA8775P videocc bindings
for QCS8300 platform.
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Imran Shaik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring (Arm) <[email protected]>
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| 0e193cc5 | 09-Jan-2025 |
Imran Shaik <[email protected]> |
dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300
The QCS8300 camera clock controller is a derivative of SA8775P, but has
an additional clock and minor differences. Hence, reuse the SA8775P
cam
dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300
The QCS8300 camera clock controller is a derivative of SA8775P, but has
an additional clock and minor differences. Hence, reuse the SA8775P
camera bindings and add additional clock required for QCS8300.
Reviewed-by: Vladimir Zapolskiy <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Imran Shaik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring (Arm) <[email protected]>
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| f0ada00a | 09-Jan-2025 |
Imran Shaik <[email protected]> |
dt-bindings: clock: qcom: Add GPU clocks for QCS8300
The QCS8300 GPU clock controller is a derivative of SA8775P, but has few
additional clocks and minor differences. Hence, reuse gpucc bindings of
dt-bindings: clock: qcom: Add GPU clocks for QCS8300
The QCS8300 GPU clock controller is a derivative of SA8775P, but has few
additional clocks and minor differences. Hence, reuse gpucc bindings of
SA8775P and add additional clocks required for QCS8300.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Imran Shaik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring (Arm) <[email protected]>
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