sys: Remove $FreeBSD$: one-line .c pattern

Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/

spdx: The BSD-2-Clause-FreeBSD identifier is obsolete, drop -FreeBSD

The SPDX folks have obsoleted the BSD-2-Clause-FreeBSD identifier. Catch
up to that fact and revert to their recommended match of

spdx: The BSD-2-Clause-FreeBSD identifier is obsolete, drop -FreeBSD

The SPDX folks have obsoleted the BSD-2-Clause-FreeBSD identifier. Catch
up to that fact and revert to their recommended match of BSD-2-Clause.

Discussed with: pfg
MFC After: 3 days
Sponsored by: Netflix

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Add support for the new Arm Generic UART _HID

Historically the ACPI _HID for both the Arm PL011 and Generic UARTs
was ARMH0011. In the Arm Base Boot Requirements 2.0 the Generic UART
_HID is changed

Add support for the new Arm Generic UART _HID

Historically the ACPI _HID for both the Arm PL011 and Generic UARTs
was ARMH0011. In the Arm Base Boot Requirements 2.0 the Generic UART
_HID is changed to ARMHB000. Use this new value in the PL011 driver
where we support both UART types.

This has been observed in some recent EDK2 builds.

Sponsored by: Arm Ltd

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uart: clean up empty lines in .c and .h files

Add quirk for ignoring SPCR AccessWidth values on the PL011 UART

The SPCR table on the Lenovo HR330A Ampere eMAG server indicates 8-bit
access, but 32-bit access is required for the PL011 to work.

Add quirk for ignoring SPCR AccessWidth values on the PL011 UART

The SPCR table on the Lenovo HR330A Ampere eMAG server indicates 8-bit
access, but 32-bit access is required for the PL011 to work.

PL011 on SBSA platforms always supports 32-bit access (and that was
hardcoded here before my EC2 fix), let's use 32-bit access for PL011
and 32BIT interface types.

Tested by emaste on Ampere eMAG and Cavium/Marvell ThunderX2.

Submitted by: Greg V <[email protected]>
Reviewed by: andrew, imp (earlier)
Differential Revision: https://reviews.freebsd.org/D19507

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add snps IP uart support / genaralize UART

This is an amalgam of a patch by Doug Ambrisko to
generalize uart_acpi_find_device, imp moving the
ACPI table to uart_dev_ns8250.c and advice by jhb
to wor

add snps IP uart support / genaralize UART

This is an amalgam of a patch by Doug Ambrisko to
generalize uart_acpi_find_device, imp moving the
ACPI table to uart_dev_ns8250.c and advice by jhb
to work around a bug in the EPYC 3151 BIOS
(the BIOS incorrectly marks the serial ports as
disabled)

Reviewed by: imp
MFC after: 8 weeks
Differential Revision: https://reviews.freebsd.org/D16432

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The Arm pl011 driver assumes it's running a devicetree based system.
It calls OF_* functions to check if it needs to implement workarounds.
This may not be the case on arm64 where we support both FDT

The Arm pl011 driver assumes it's running a devicetree based system.
It calls OF_* functions to check if it needs to implement workarounds.
This may not be the case on arm64 where we support both FDT and ACPI.
Fix this by checking if we are booting on FDT before calling these checks.

Reviewed by: ian
Sponsored by: DARPA, AFRL
Sponsored by: Cavium (Hardware)
Differential Revision: https://reviews.freebsd.org/D14515

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Teach the Arm pl011 driver to attach to a SBSA uart. This is defined in
the Server Base System Architecture to be a subset of the pl011 r1p5. As
we don't use the removed features it is safe to just a

Teach the Arm pl011 driver to attach to a SBSA uart. This is defined in
the Server Base System Architecture to be a subset of the pl011 r1p5. As
we don't use the removed features it is safe to just attach to the existing
driver as is.

Sponsored by: DARPA, AFRL

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Rename the FDT compat_data array to a bus-specific name.

Sponsored by: DARPA, AFRL

Do pass removing some write-only variables from the kernel.

This reduces noise when kernel is compiled by newer GCC versions,
such as one used by external toolchain ports.

Reviewed by: kib, andrew(

Do pass removing some write-only variables from the kernel.

This reduces noise when kernel is compiled by newer GCC versions,
such as one used by external toolchain ports.

Reviewed by: kib, andrew(sys/arm and sys/arm64), emaste(partial), erj(partial)
Reviewed by: jhb (sys/dev/pci/* sys/kern/vfs_aio.c and sys/kern/kern_synch.c)
Differential Revision: https://reviews.freebsd.org/D10385

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sys/dev: further adoption of SPDX licensing ID tags.

Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error

sys/dev: further adoption of SPDX licensing ID tags.

Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error
prone - task.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.

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Extend the pl011 small-fifos fix to other SoCs that indicate rev 5
hardware but lack the larger fifos rev 5 hardware should have.

The linux world (where our FDT data comes from) solved this by addin

Extend the pl011 small-fifos fix to other SoCs that indicate rev 5
hardware but lack the larger fifos rev 5 hardware should have.

The linux world (where our FDT data comes from) solved this by adding
a new property to pl011 nodes, "arm,primecell-periphid". When this
property is present, its values override the values in the hardware
periphid registers. For pl011 rev 5 hardware with small fifos, they
override the id so that it appears to be rev 4 hardware.

The driver now uses the new property when present. It also continues
to check the device compat string, to handle older fdt data that may
still be in use on existing systems (on RPi systems it is common to
update system software without updating fdt data which is part of the
boot firmware).

Reviewed by: imp

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Handle fifo size differences between older and newer revs of pl011 hardware.

Starting with rev 5 (which is inexplicably indicated by a version number
of '3' in the Peripheral ID register), the pl011

Handle fifo size differences between older and newer revs of pl011 hardware.

Starting with rev 5 (which is inexplicably indicated by a version number
of '3' in the Peripheral ID register), the pl011 doubled the size of the
rx and tx fifos, to 32 bytes, so read the ID register and set the size
variables in the softc accordingly.

An interesting wrinkle in this otherwise-simple concept is that the
bcm2835 SoC, used in Raspberry Pi systems among others, has the rev 5
pl011 hardware, but somehow also has the older 16-byte fifos. We check
the FDT data to see if the hardware is part of a bcm283x system and use
the smaller size if so.

Thanks to jchandra@ for pointing out that newer hardware has bigger fifos.

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Reconfigure the fifo watermark levels on the pl011 uart to interrupt when
the fifos are 3/4 full (rc) or empty (tx).

Fix bugs exposed by the recent enabling of FIFOs in the pl011 uart. These
have been in the code all along, but were masked by having a fifo depth of
one byte at the hardware level, so everything kin

Fix bugs exposed by the recent enabling of FIFOs in the pl011 uart. These
have been in the code all along, but were masked by having a fifo depth of
one byte at the hardware level, so everything kinda worked by accident.

The hardware interrupts when the TX fifo is half empty, so set
sc->sc_txfifosz to 8 bytes (half the hardware fifo size) to match. This
eliminates dropped characters on output.

Restructure the read loop to consume all the bytes in the fifo by using
the "rx fifo empty" bit of the flags register rather than the "rx ready"
bit of the interrupt status register. The rx-ready interrupt is cleared
when the number of bytes in the fifo fall below the interrupt trigger
level, leaving the fifo half full every time receive routine was called.
Now it loops until the fifo is completely empty every time (including
when the function is called due to a receive timeout as well as for
fifo-full).

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Enable pl011 UART FIFOs

The pl011 UART has a 16 entry Tx FIFO and a 16 entry Rx FIFO that
have not been used so far. Update the driver to enable the FIFOs
and use them in transmit and receive.

Revi

Enable pl011 UART FIFOs

The pl011 UART has a 16 entry Tx FIFO and a 16 entry Rx FIFO that
have not been used so far. Update the driver to enable the FIFOs
and use them in transmit and receive.

Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D8819

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Fix whitespace issues in pl011 uart driver

Fix up trailing whitespace introduced by r310190. While there,
fix a couple of earlier whitespace errors as well.

Simplify interrupt mask programming in pl011 uart

Remove unused fields from uart_pl011_softc. Add an interrupt mask
field to the softc and use it to set the interrupt mask register.

There should be

Simplify interrupt mask programming in pl011 uart

Remove unused fields from uart_pl011_softc. Add an interrupt mask
field to the softc and use it to set the interrupt mask register.

There should be no functional change introduced here except in the
grab and ungrab functions. In these functions, we now disable and
enable all interrupts rather than just the receive interrupt.

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Fix interrupt clear in pl011 uart receive function

Clear the interrupt state before reading the input char from the
input FIFO. In the current code there is a window between the read
to the data reg

Fix interrupt clear in pl011 uart receive function

Clear the interrupt state before reading the input char from the
input FIFO. In the current code there is a window between the read
to the data register and the write to the the ICR, during which an
input char will not cause an interrupt.

This fixes the issue by which the serial port input on QEMU freezes
when using the emulated pl011 serial port.

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Include the missing accommon.h from the ACPI uart code.

Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation

Add support to find the arm64 serial using the ACPI tables. This uses the
Serial Port Console Redirection Table to find the device to use.

Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Fo

Add support to find the arm64 serial using the ACPI tables. This uses the
Serial Port Console Redirection Table to find the device to use.

Obtained from: ABT Systems Ltd
Sponsored by: The FreeBSD Foundation

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Add support for arm64 to uart_dev_acpi by using the _HID property to find
the uart class to use in a similar way as the fdt driver.

Obtained from: ABT Systems Ltd
MFC after: 1 month
Sponsored by: Th

Add support for arm64 to uart_dev_acpi by using the _HID property to find
the uart class to use in a similar way as the fdt driver.

Obtained from: ABT Systems Ltd
MFC after: 1 month
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D7248

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Add support for the uart classes to set their default register shift value.
This is needed with the pl011 driver. Before this change it would default
to a shift of 0, however the hardware places the

Add support for the uart classes to set their default register shift value.
This is needed with the pl011 driver. Before this change it would default
to a shift of 0, however the hardware places the registers at 4-byte
addresses meaning the value should be 2.

This patch fixes this for the pl011 when configured using the fdt. The
other drivers have a default value of 0 to keep this a no-op.

MFC after: 1 week

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Move the uart_class definitions and fdt compat data into the individual
uart implementations, and export them using the new linker-set mechanism.

Differential Revision: https://reviews.freebsd.org/D

Move the uart_class definitions and fdt compat data into the individual
uart implementations, and export them using the new linker-set mechanism.

Differential Revision: https://reviews.freebsd.org/D1993
Submitted by: Michal Meloun

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Fix the pl011 driver to work when the uart will write in zero cycles. This
is the case, depending on the options, in some of the ARM hardware
simulators. In these cases we don't get an interrupt so w

Fix the pl011 driver to work when the uart will write in zero cycles. This
is the case, depending on the options, in some of the ARM hardware
simulators. In these cases we don't get an interrupt so will need to
schedule the task to write more data to the uart.

MFC after: 1 week
Sponsored by: The FreeBSD Foundation

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