sys: Remove $FreeBSD$: one-line .c patternRemove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/
sys: Remove $FreeBSD$: two-line .h patternRemove /^\s*\*\n \*\s+\$FreeBSD\$$\n/
arm64: Hyper-V: enablement for ARM64 in Hyper-V (Part 3, final)This is the last part for ARM64 Hyper-V enablement. This includescommone files and make file changes to enable the ARM64 FreeBSDgues
arm64: Hyper-V: enablement for ARM64 in Hyper-V (Part 3, final)This is the last part for ARM64 Hyper-V enablement. This includescommone files and make file changes to enable the ARM64 FreeBSDguest on Hyper-V. With this patch, it should be able to buildthe ARM64 image and install it on Hyper-V.Reviewed by: emaste, andrew, whuTested by: Souradeep Chakrabarti <[email protected]>Sponsored by: MicrosoftDifferential Revision: https://reviews.freebsd.org/D36744
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Change "compiled" to "assembled"Assembly files are assembled, not compiled.Submitted by: github user gAlfonso-bitPull Request: https://github.com/freebsd/freebsd-src/pull/474Sponsored by: Net
Change "compiled" to "assembled"Assembly files are assembled, not compiled.Submitted by: github user gAlfonso-bitPull Request: https://github.com/freebsd/freebsd-src/pull/474Sponsored by: Netflix
hyperv: Fix vmbus after the i386 4/4 splitThe vmbus ISR needs to live in a trampoline. Dynamically allocating atrampoline at driver initialization time poses some difficulties due tothe fact tha
hyperv: Fix vmbus after the i386 4/4 splitThe vmbus ISR needs to live in a trampoline. Dynamically allocating atrampoline at driver initialization time poses some difficulties due tothe fact that the KENTER macro assumes that the offset relative totramp_idleptd is fixed at static link time. Another problem is thatnative_lapic_ipi_alloc() uses setidt(), which assumes a fixed trampolineoffset.Rather than fight this, move the Hyper-V ISR to i386/exception.s. Add anew HYPERV kernel option to make this optional, and configure it bydefault on i386. This is sufficient to make use of vmbus(4) after the4/4 split. Note that vmbus cannot be loaded dynamically and both theHYPERV option and device must be configured together. I think this isnot too onerous a requirement, since vmbus(4) was previouslynon-functional.Reported by: Harry Schmalzbauer <[email protected]>Tested by: Harry Schmalzbauer <[email protected]>Reviewed by: whu, kibMFC after: 2 weeksSponsored by: The FreeBSD FoundationDifferential Revision: https://reviews.freebsd.org/D30577
x86: remove gcov kernel supportReviewed by: jhbSponsored by: The FreeBSD FoundationDifferential revision: https://reviews.freebsd.org/D29529
i386 4/4G split.The change makes the user and kernel address spaces on i386independent, giving each almost the full 4G of usable virtual addressesexcept for one PDE at top used for trampoline and
i386 4/4G split.The change makes the user and kernel address spaces on i386independent, giving each almost the full 4G of usable virtual addressesexcept for one PDE at top used for trampoline and per-CPU trampolinestacks, and system structures that must be always mapped, namely IDT,GDT, common TSS and LDT, and process-private TSS and LDT if allocated.By using 1:1 mapping for the kernel text and data, it appearedpossible to eliminate assembler part of the locore.S which bootstrapsinitial page table and KPTmap. The code is rewritten in C and movedinto the pmap_cold(). The comment in vmparam.h explains the KVAlayout.There is no PCID mechanism available in protected mode, so eachkernel/user switch forth and back completely flushes the TLB, exceptfor the trampoline PTD region. The TLB invalidations for userspacebecomes trivial, because IPI handlers switch page tables. On the otherhand, context switches no longer need to reload %cr3.copyout(9) was rewritten to use vm_fault_quick_hold(). An issue fornew copyout(9) is compatibility with wiring user buffers around sysctlhandlers. This explains two kind of locks for copyout ptes andaccounting of the vslock() calls. The vm_fault_quick_hold() AKA slowpath, is only tried after the 'fast path' failed, which temporarychanges mapping to the userspace and copies the data to/from smallper-cpu buffer in the trampoline. If a page fault occurs during thecopy, it is short-circuit by exception.s to not even reach C code.The change was motivated by the need to implement the Meltdownmitigation, but instead of KPTI the full split is done. The i386architecture already shows the sizing problems, in particular, it isimpossible to link clang and lld with debugging. I expect that theissues due to the virtual address space limits would only exaggerateand the split gives more liveness to the platform.Tested by: phoDiscussed with: bdeSponsored by: The FreeBSD FoundationMFC after: 1 monthDifferential revision: https://reviews.freebsd.org/D14633
Rename assym.s to assym.incassym is only to be included by other .s files, and should neveractually be assembled by itself.Reviewed by: imp, bdrewery (earlier)Sponsored by: The FreeBSD Foundati
Rename assym.s to assym.incassym is only to be included by other .s files, and should neveractually be assembled by itself.Reviewed by: imp, bdrewery (earlier)Sponsored by: The FreeBSD FoundationDifferential Revision: https://reviews.freebsd.org/D14180
PTI for amd64.The implementation of the Kernel Page Table Isolation (KPTI) foramd64, first version. It provides a workaround for the 'meltdown'vulnerability. PTI is turned off by default for now
PTI for amd64.The implementation of the Kernel Page Table Isolation (KPTI) foramd64, first version. It provides a workaround for the 'meltdown'vulnerability. PTI is turned off by default for now, enable with theloader tunable vm.pmap.pti=1.The pmap page table is split into kernel-mode table and user-modetable. Kernel-mode table is identical to the non-PTI table, whileusermode table is obtained from kernel table by leaving userspacemappings intact, but only leaving the following parts of the kernelmapped: kernel text (but not modules text) PCPU GDT/IDT/user LDT/task structures IST stacks for NMI and doublefault handlers.Kernel switches to user page table before returning to usermode, andrestores full kernel page table on the entry. Initial kernel-modestack for PTI trampoline is allocated in PCPU, it is only 16qwords. Kernel entry trampoline switches page tables. then thehardware trap frame is copied to the normal kstack, and executioncontinues.IST stacks are kept mapped and no trampoline is needed forNMI/doublefault, but of course page table switch is performed.On return to usermode, the trampoline is used again, iret frame iscopied to the trampoline stack, page tables are switched and iretq isexecuted. The case of iretq faulting due to the invalid usermodecontext is tricky, since the frame for fault is appended to thetrampoline frame. Besides copying the fault frame and original(corrupted) frame to kstack, the fault frame must be patched to makeit look as if the fault occured on the kstack, see the comment indoret_iret detection code in trap().Currently kernel pages which are mapped during trampoline operationare identical for all pmaps. They are registered usingpmap_pti_add_kva(). Besides initial registrations done during boot,LDT and non-common TSS segments are registered if user requested theiruse. In principle, they can be installed into kernel page table perpmap with some work. Similarly, PCPU can be hidden from userspacemapping using trampoline PCPU page, but again I do not see muchbenefits besides complexity.PDPE pages for the kernel half of the user page tables arepre-allocated during boot because we need to know pml4 entries whichare copied to the top-level paging structure page, in advance on a newpmap creation. I enforce this to avoid iterating over the allexisting pmaps if a new PDPE page is needed for PTI kernel mappings.The iteration is a known problematic operation on i386.The need to flush hidden kernel translations on the switch to usermode make global tables (PG_G) meaningless and even harming, so PG_Guse is disabled for PTI case. Our existing use of PCID isincompatible with PTI and is automatically disabled if PTI isenabled. PCID can be forced on only for developer's benefit.MCE is known to be broken, it requires IST stack to operate completelycorrectly even for non-PTI case, and absolutely needs dedicated ISTstack because MCE delivery while trampoline did not switched from PTIstack is fatal. The fix is pending.Reviewed by: markj (partially)Tested by: pho (previous version)Discussed with: jeff, jhbSponsored by: The FreeBSD FoundationMFC after: 2 weeks
hyperv: Move machine dependent bits into machine dependent files.MFC after: 1 weekSponsored by: Microsoft OSTCDifferential Revision: https://reviews.freebsd.org/D6701
hyperv: Rename some cleaned up/almost cleaned up filesMFC after: 1 weekSponsored by: Microsoft OSTC
hyperv/vmbus: Indentation cleanupNo functional changes.MFC after: 1 weekSponsored by: Microsoft OSTCDifferential Revision: https://reviews.freebsd.org/D6602
hyperv/vmbus: Rename ISR functionsMFC after: 1 weekSponsored by: Microsoft OSTCDifferential Revision: https://reviews.freebsd.org/D6601
hyperv: Deprecate HYPERV option by moving Hyper-V IDT vector into vmbusSubmitted by: Jun Su <junsu microsoft com>Reviewed by: jhb, kib, sepheSponsored by: Microsoft OSTCDifferential Revision: ht
hyperv: Deprecate HYPERV option by moving Hyper-V IDT vector into vmbusSubmitted by: Jun Su <junsu microsoft com>Reviewed by: jhb, kib, sepheSponsored by: Microsoft OSTCDifferential Revision: https://reviews.freebsd.org/D5910