uart_dev_ns8250: Switch ACPI UART subtype for Marvell SoCs

DBG2 ACPI table description [1] specifies three subtypes
related to 16550 UART:
0x0 - 16550 compatible
0x1 - 16550 subset
0x12 - 16550 comp

uart_dev_ns8250: Switch ACPI UART subtype for Marvell SoCs

DBG2 ACPI table description [1] specifies three subtypes
related to 16550 UART:
0x0 - 16550 compatible
0x1 - 16550 subset
0x12 - 16550 compatible with parameters defined in Generic Address Structure (GAS)

It turned out however, that the Windows OS treats 0x0 subtype as
legacy x86 UART with 8-bit access. ARM SoCs can use types 0x1 (16550 with
fixed mmio32 access) or 0x12 (16550 with fully respected GAS contents).

Switch Marvell SoCs ACPI UART subtype to 0x1 - thanks to that the same firmware
can run properly with UART output in FreeBSD, Windows 10, Linux and ESXI
hypervisor. Tests showed the older firmware versions that use 0x0
UART subtype in SPCR table continue to display output properly.

[1] https://docs.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table

Obtained from: Semihalf
Sponsored by: ARM
Differential revision: https://reviews.freebsd.org/D30386
MFC after: 2 weeks

(cherry picked from commit 9cf66a0458f4913d34cb3c5f6b653c78f70de8a8)

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uart: Fix an out-of-bounds read in ns8250_bus_probe()

The problem is that ns8250_bus_probe() accesses a field from the
ns8250_softc, which embeds the generic UART softc, but the ns8250_softc
hasn't

uart: Fix an out-of-bounds read in ns8250_bus_probe()

The problem is that ns8250_bus_probe() accesses a field from the
ns8250_softc, which embeds the generic UART softc, but the ns8250_softc
hasn't yet been allocated because we're still probing.

This is a regression from commit 0aefb0a63c50. This fixed a problem
where one of the upper four IER bits, which are usually reserved, needs
to be set in order to get RX interrupts before the RX FIFO is full. At
the same time, we avoid clearing those reserved bits (see commit
58957d87173, though other UART drivers I looked at do not bother with
this).

So, copy what ns8250_init() does to disable interrupts, since we don't
know what the "right" mask is at this point.

Reported by: [email protected]
Reviewed by: imp
Sponsored by: The FreeBSD Foundation

(cherry picked from commit 4a9a41650c909706bc0b9a3f29817c11b262b0a0)

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ns8250: don't drop IER_TXRDY on bus_grab/ungrab

It has been observed that some systems are often unable to resume from
ddb after entering with debug.kdb.enter=1. Checking the status further
shows th

ns8250: don't drop IER_TXRDY on bus_grab/ungrab

It has been observed that some systems are often unable to resume from
ddb after entering with debug.kdb.enter=1. Checking the status further
shows the terminal is blocked waiting in tty_drain(), but it never makes
progress in clearing the output queue, because sc->sc_txbusy is high.

I noticed that when entering polling mode for the debugger, IER_TXRDY is
set in the failure case. Since this bit is never tracked by the softc,
it will not be restored by ns8250_bus_ungrab(). This creates a race in
which a TX interrupt can be lost, creating the hang described above.
Ensuring that this bit is restored is enough to prevent this, and resume
from ddb as expected.

The solution is to track this bit in the sc->ier field, for the same
lifetime that TX interrupts are enabled.

PR: 223917, 240122
Sponsored by: The FreeBSD Foundation

(cherry picked from commit 7e7f7beee732810d3afcc83828341ac3e139b5bd)

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uart: clean up empty lines in .c and .h files

Correct baud rate error calculation.

Shifting right by 1 is not the same as dividing by 2 for signed
values. In particular, dividing a signed value by 2 gives the integer
ceiling of the (e.g. -5 /

Correct baud rate error calculation.

Shifting right by 1 is not the same as dividing by 2 for signed
values. In particular, dividing a signed value by 2 gives the integer
ceiling of the (e.g. -5 / 2 == -2) whereas shifting right by 1 always
gives the floor (-5 >> 1 == -3).

An embedded board with a 25 Mhz base clock results in an error of
-30.5% when used with a baud rate of 115200. Using division, this
truncates to -30% and is permitted. Using the shift, this fails and
is rejected causing TIOCSETA requests to fail with EINVAL and breaking
getty(8).

Using division gives the same error range for both over and under baud
rates and also makes the code match the behavior documented in the
existing comment about supporting boards with 25 Mhz clocks.

Reported by: imp
MFC after: 2 weeks
Sponsored by: DARPA
Differential Revision: https://reviews.freebsd.org/D24367

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Relax TX draining in ns8250_bus_transmit().

Since TX interrupt is generated when THRE is set, wait for TEMT set means
wait for full character transmission time. At low speeds that may take
awhile,

Relax TX draining in ns8250_bus_transmit().

Since TX interrupt is generated when THRE is set, wait for TEMT set means
wait for full character transmission time. At low speeds that may take
awhile, burning CPU time while holding sc_hwmtx lock, also congested.

This is partial revert of r317659.

PR: 240121
MFC after: 2 weeks

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Add ACPI entries for Synopsys Designware UARTs used on ARM platforms

This fixes (userspace) console on the Marvell MACCHIATObin in ACPI mode with
latest TianoCore EDK2 firmware.

Submitted by: Greg

Add ACPI entries for Synopsys Designware UARTs used on ARM platforms

This fixes (userspace) console on the Marvell MACCHIATObin in ACPI mode with
latest TianoCore EDK2 firmware.

Submitted by: Greg V <[email protected]>
Reviewed by: mw, bcran
Differential Revision: https://reviews.freebsd.org/D20765

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add snps IP uart support / genaralize UART

This is an amalgam of a patch by Doug Ambrisko to
generalize uart_acpi_find_device, imp moving the
ACPI table to uart_dev_ns8250.c and advice by jhb
to wor

add snps IP uart support / genaralize UART

This is an amalgam of a patch by Doug Ambrisko to
generalize uart_acpi_find_device, imp moving the
ACPI table to uart_dev_ns8250.c and advice by jhb
to work around a bug in the EPYC 3151 BIOS
(the BIOS incorrectly marks the serial ports as
disabled)

Reviewed by: imp
MFC after: 8 weeks
Differential Revision: https://reviews.freebsd.org/D16432

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Add busy detect quirk to list of console options

This change allows one to set the busy_detect flag
required by the synopsys UART at the loader prompt.
This is needed by the EPYC 3000 SoC.

This wil

Add busy detect quirk to list of console options

This change allows one to set the busy_detect flag
required by the synopsys UART at the loader prompt.
This is needed by the EPYC 3000 SoC.

This will give users a working console up to the point where getty is required:
hw.uart.console="mm:0xfedc9000,rs:2,bd:1"

Reviewed by: imp
MFC after: 4 weeks
Differential Revision: https://reviews.freebsd.org/D16399

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sys/dev: further adoption of SPDX licensing ID tags.

Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error

sys/dev: further adoption of SPDX licensing ID tags.

Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error
prone - task.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.

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uart: detect 256-byte FIFOs

Submitted by: Zakary Nafziger <[email protected]>
Sponsored by: The FreeBSD Foundation

Make some UART consoles to not spin wait for data to be sent.

At least with Tx FIFO enabled it shows me ~10% reduction of verbose boot
time with serial console at 115200 baud.

Reviewed by: marcel
M

Make some UART consoles to not spin wait for data to be sent.

At least with Tx FIFO enabled it shows me ~10% reduction of verbose boot
time with serial console at 115200 baud.

Reviewed by: marcel
MFC after: 2 weeks

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Add support for UART found in the Ingenic XBurst system on chips.

These CPUs has non-standard UART enable bit hidden in the UART FIFO
Control Register.

Sponsored by: DARPA, AFRL

sys/dev: minor spelling fixes.

Most affect comments, very few have user-visible effects.

Move support for Synopsys Designware APB UART out of ns8250 and into a
separate driver. Add support for activating clock and hwreset resources
for these devices when the EXT_RESOURCES option is prese

Move support for Synopsys Designware APB UART out of ns8250 and into a
separate driver. Add support for activating clock and hwreset resources
for these devices when the EXT_RESOURCES option is present.

Reviewed by: andrew, mmel, Emmanuel Vadot <[email protected]>
Approved by: adrian (mentor)
Differential Revision: https://reviews.freebsd.org/D5749

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Add ns16550a compatible string in UART 8250 driver

Obtained from: Semihalf
Submitted by: Michal Stanek <[email protected]>
Sponsored by: Annapurna Labs
Approved by:

Add ns16550a compatible string in UART 8250 driver

Obtained from: Semihalf
Submitted by: Michal Stanek <[email protected]>
Sponsored by: Annapurna Labs
Approved by: cognet (mentor)
Reviewed by: imp, wma
Differential revision: https://reviews.freebsd.org/D5404

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UART: Fix spurious interrupts generated by ns8250 and lpc drivers:
- don't enable transmitter empty interrupt before filling TX FIFO.
- add missing uart_barrier() call in interrupt service routine

Fix busy-detect when using DesignWare UART

uart_dev_ns8250 now relies on compatible property instead of additional
'busy-detect' cell. All drivers with compatible = "snps,dw-apb-uart" have
busy dete

Fix busy-detect when using DesignWare UART

uart_dev_ns8250 now relies on compatible property instead of additional
'busy-detect' cell. All drivers with compatible = "snps,dw-apb-uart" have
busy detection turned on. DTS files of devices affected by the change
were modified and 'busy-detect' property was removed.

Reviewed by: andrew, ian, imp
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <[email protected]>
Differential revision: https://reviews.freebsd.org/D4218

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Add compatibility string for dw-apb-uart in ns8250 driver

This compatibility string is used in .dts file of Armada38x
and isrequired for driver attachment.

Reviewed by: andrew, ian, imp
Obtained

Add compatibility string for dw-apb-uart in ns8250 driver

This compatibility string is used in .dts file of Armada38x
and isrequired for driver attachment.

Reviewed by: andrew, ian, imp
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Michal Stanek <[email protected]>
Differential revision: https://reviews.freebsd.org/D4216

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Restore uart PPS signal capture polarity to its historical norm, and add an
option to invert the polarity in software. Also add an option to capture
very narrow pulses by using the hardware's MSR del

Restore uart PPS signal capture polarity to its historical norm, and add an
option to invert the polarity in software. Also add an option to capture
very narrow pulses by using the hardware's MSR delta-bit capability of
latching line state changes.

This effectively reverts the mistake I made in r286595 which was based on
empirical measurements made on hardware using TTL-level signaling, in which
the logic levels are inverted from RS-232. Thus, this re-syncs the polarity
with the requirements of RFC 2783, which is writen in terms of RS-232
signaling.

Narrow-pulse mode uses the ability of most ns8250 and similar chips to
provide a delta indication in the modem status register. The hardware is
able to notice and latch the change when the pulse width is shorter than
interrupt latency, which results in the signal no longer being asserted by
time the interrupt service code runs. When running in this mode we get
notified only that "a pulse happened" so the driver synthesizes both an
ASSERT and a CLEAR event (with the same timestamp for each). When the pulse
width is about equal to the interrupt latency the driver may intermittantly
see both edges of the pulse. To prevent generating spurious events, the
driver implements a half-second lockout period after generating an event
before it will generate another.

Differential Revision: https://reviews.freebsd.org/D4477

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uart(4) - make the 8250 uart baudrate tolerance build time tweakable.

It turns out on a 16550 w/ a 25MHz SoC reference clock you get a little
over 3% error at 115200 baud, which causes this to fail.

uart(4) - make the 8250 uart baudrate tolerance build time tweakable.

It turns out on a 16550 w/ a 25MHz SoC reference clock you get a little
over 3% error at 115200 baud, which causes this to fail.

Just .. cope. Things cope these days.

Default to 30 (3.0%) as before, but allow UART_DEV_TOLERANCE_PCT to be
set at build time to change that.

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Actually check the DTS node value to enable the uart quirks.

Without this fix, you cannot disable the quirks by setting it to 0, just
the presence of the FDT node was enough to enable it.

Add support for the uart classes to set their default register shift value.
This is needed with the pl011 driver. Before this change it would default
to a shift of 0, however the hardware places the

Add support for the uart classes to set their default register shift value.
This is needed with the pl011 driver. Before this change it would default
to a shift of 0, however the hardware places the registers at 4-byte
addresses meaning the value should be 2.

This patch fixes this for the pl011 when configured using the fdt. The
other drivers have a default value of 0 to keep this a no-op.

MFC after: 1 week

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Move the uart_class definitions and fdt compat data into the individual
uart implementations, and export them using the new linker-set mechanism.

Differential Revision: https://reviews.freebsd.org/D

Move the uart_class definitions and fdt compat data into the individual
uart implementations, and export them using the new linker-set mechanism.

Differential Revision: https://reviews.freebsd.org/D1993
Submitted by: Michal Meloun

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Pull in r267961 and r267973 again. Fix for issues reported will follow.