| a58ed3b4 | 10-Aug-2021 |
Alexander Motin <[email protected]> |
ntb_hw_intel(4): Remove CTLFLAG_NEEDGIANT flags.
Most of the sysctls just read hardware registers. They don't need
any locking.
MFC after: 2 weeks
(cherry picked from commit 50f16247a110d2ace56f1
ntb_hw_intel(4): Remove CTLFLAG_NEEDGIANT flags.
Most of the sysctls just read hardware registers. They don't need
any locking.
MFC after: 2 weeks
(cherry picked from commit 50f16247a110d2ace56f1120304616f3e6ad9763)
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| 6660ef6e | 23-Oct-2020 |
Mark Johnston <[email protected]> |
ntb: Add Intel Xeon Gen3 support
The NTB hardware starting with Skylake has some changes to the register
map and the doorbell interface. Add a new NTB_XEON_GEN3 device type and
use it to conditiona
ntb: Add Intel Xeon Gen3 support
The NTB hardware starting with Skylake has some changes to the register
map and the doorbell interface. Add a new NTB_XEON_GEN3 device type and
use it to conditionalize driver logic that differs from the existing
Xeon code.
Reviewed by: vangyzen
Discussed with: cem, Bret Ketchum <[email protected]>
MFC after: 1 month
Sponsored by: NetApp, Inc.
Sponsored by: Klara, Inc.
Differential Revision: https://reviews.freebsd.org/D26683
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| 95ba48d9 | 28-Nov-2019 |
Alexander Motin <[email protected]> |
Make DMAR allow Intel NTB device to access its own BAR0.
I have no good explanation why it happens, but I found that in B2B mode
at least Xeon v4 NTB leaks accesses to its configuration memory at BA
Make DMAR allow Intel NTB device to access its own BAR0.
I have no good explanation why it happens, but I found that in B2B mode
at least Xeon v4 NTB leaks accesses to its configuration memory at BAR0
originated from the link side to its host side. DMAR predictably blocks
those, making access to remote scratchpad registers in B2B mode impossible.
This change creates identity mapping in DMAR covering the BAR0 addresses,
making the NTB work fine with DMAR enabled. It seems like allowing single
4KB range at 32KB offset may be enough, but I don't see a reason to be so
specific.
MFC after: 1 week
Sponsored by: iXsystems, Inc.
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| 028d9689 | 10-Nov-2019 |
Alexander Motin <[email protected]> |
Add compact scraptchpad protocol for ntb_transport(4).
Previously ntb_transport(4) required at least 6 scratchpad registers,
plus 2 more for each additional memory window. That is too much for some
Add compact scraptchpad protocol for ntb_transport(4).
Previously ntb_transport(4) required at least 6 scratchpad registers,
plus 2 more for each additional memory window. That is too much for some
configurations, where several drivers have to share resources of the same
NTB hardware. This patch introduces new compact version of the protocol,
requiring only 3 scratchpad registers, plus one more for each additional
memory window. The optimization is based on fact that neither of version,
number of windows or number of queue pairs really need more then one byte
each, and window sizes of 4GB are not very useful now. The new protocol
is activated automatically when the configuration is low on scratchpad
registers, or it can be activated explicitly with loader tunable.
MFC after: 2 weeks
Sponsored by: iXsystems, Inc.
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