Fix Machine Check Exception on Page Size Change.Approved by: soSecurity: FreeBSD-SA-19:25.mcepscSecurity: CVE-2018-12207
MFC 348210: Add a constant for the LS config MSR on AMD CPUs.
MFC r347216:amd64: fix BUS_SPACE_MAXSIZE to 64bit max value.
MFC r347566:Mitigations for Microarchitectural Data Sampling.Reference: https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00233.htmlSecurity: CVE-2018-12126, CVE-2018-1212
MFC r347566:Mitigations for Microarchitectural Data Sampling.Reference: https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00233.htmlSecurity: CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091Security: FreeBSD-SA-19:07.mdsReviewed by: jhbTested by: emaste, lwhsuApproved by: so (gtetlow)
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MFC r346062:pci_cfgreg.c: Use io port config access for early boot time.PR: 236838
MFC r345228:amd64 KPTI: add control from procctl(2).
MFC r345189:Add symbolic name for TSC_AUX MSR address.
MFC r345075:Add register number, CPUID bits, and print identification for TSXforce abort errata.
MFC r344354:Add usermode helpers for the Intel userspace protection keys feature.
MFC r344353:Add kernel support for Intel userspace protection keys feature onSkylake Xeons.
MFC r344293:Add definition for %cr4 PKRU enable bit.
MFC r343757:Update CPUID bits definitions and CPU identification based on changesin SDM rev. 069.
MFC r343146:x86 busdma: fix mis-use of bus_addr_t where vm_paddr_t is assumed.
MFC 340460: Convert the number of MSI IRQs on x86 from a constant to a tunable.The number of MSI IRQs still defaults to 512, but it can now bechanged at boot time via the machdep.num_msi_irqs tuna
MFC 340460: Convert the number of MSI IRQs on x86 from a constant to a tunable.The number of MSI IRQs still defaults to 512, but it can now bechanged at boot time via the machdep.num_msi_irqs tunable.Relnotes: yes
MFC r340487:Align IA32_ARCH_CAP MSR definitions and use with SDM rev. 068.
MFC r340384:Apply fix to un-cripple max cpu id on BSP earlier.
Update x86/ifunc.h.Remove ifunc emulation.Add helper for usermode ifunc resolver definition.Update copyright years.Sponsored by: The FreeBSD FoundationApproved by: re (rgrimes)MFC after: 1 we
Update x86/ifunc.h.Remove ifunc emulation.Add helper for usermode ifunc resolver definition.Update copyright years.Sponsored by: The FreeBSD FoundationApproved by: re (rgrimes)MFC after: 1 week
Log a message after a successful boot-time microcode update.Reviewed by: kibApproved by: re (delphij)Sponsored by: The FreeBSD FoundationDifferential Revision: https://reviews.freebsd.org/D17135
Dynamically allocate IRQ ranges on x86.Previously, x86 used static ranges of IRQ values for different typesof I/O interrupts. Interrupt pins on I/O APICs and 8259A PICs usedIRQ values from 0 to
Dynamically allocate IRQ ranges on x86.Previously, x86 used static ranges of IRQ values for different typesof I/O interrupts. Interrupt pins on I/O APICs and 8259A PICs usedIRQ values from 0 to 254. MSI interrupts used a compile-time-definedrange starting at 256, and Xen event channels used acompile-time-defined range after MSI. Some recent systems have morethan 255 I/O APIC interrupt pins which resulted in those IRQ valuesoverflowing into the MSI range triggering an assertion failure.Replace statically assigned ranges with dynamic ranges. Do a singlepass computing the sizes of the IRQ ranges (PICs, MSI, Xen) todetermine the total number of IRQs required. Allocate the interruptsource and interrupt count arrays dynamically once this pass hascompleted. To minimize runtime complexity these arrays are only sizedonce during bootup. The PIC range is determined by the PICs presentin the system. The MSI and Xen ranges continue to use a fixed size,though this does make it possible to turn the MSI range size into atunable in the future.As a result, various places are updated to use dynamic limits insteadof constants. In addition, the vmstat(8) utility has been taught tounderstand that some kernels may treat 'intrcnt' and 'intrnames' aspointers rather than arrays when extracting interrupt stats from acrashdump. This is determined by the presence (vs absence) of aglobal 'nintrcnt' symbol.This change reverts r189404 which worked around a buggy BIOS whichenumerated an I/O APIC twice (using the same memory mapped address forboth entries but using an IRQ base of 256 for one entry and a validIRQ base for the second entry). Making the "base" of MSI IRQ valuesdynamic avoids the panic that r189404 worked around, and there may nowbe valid I/O APICs with an IRQ base above 256 which this workaroundwould incorrectly skip.If in the future the issue reported in PR 130483 reoccurs, we willhave to add a pass over the I/O APIC entries in the MADT to detectduplicates using the memory mapped address and use some strategy tochoose the "correct" one.While here, reserve room in intrcnts for the Hyper-V counters.PR: 229429, 130483Reviewed by: kib, royger, cemTested by: royger (Xen), kib (DMAR)Approved by: re (gjb)MFC after: 2 weeksDifferential Revision: https://reviews.freebsd.org/D16861
Merge amd64 and i386 <machine/intr_machdep.h> headers.Reviewed by: kibMFC after: 2 weeksDifferential Revision: https://reviews.freebsd.org/D16803
Remove some vestiges of IPI_LAZYPMAP on i386.The support for lazy pmap invalidations on i386 was removed in r281707.This removes the constant for the IPI and stops accounting for it whensizing th
Remove some vestiges of IPI_LAZYPMAP on i386.The support for lazy pmap invalidations on i386 was removed in r281707.This removes the constant for the IPI and stops accounting for it whensizing the interrupt count arrays.Reviewed by: kibMFC after: 2 weeksDifferential Revision: https://reviews.freebsd.org/D16801
Add definitions related to the L1D flush operation capability and MSR.Sponsored by: The FreeBSD Foundation
Implement kernel support for early loading of Intel microcode updates.Updates in the format described in section 9.11 of the Intel SDM cannow be applied as one of the first steps in booting the ke
Implement kernel support for early loading of Intel microcode updates.Updates in the format described in section 9.11 of the Intel SDM cannow be applied as one of the first steps in booting the kernel. Updatesthat are loaded this way are automatically re-applied upon exit fromACPI sleep states, in contrast with the existing cpucontrol(8)-basedmethod. For the time being only Intel updates are supported.Microcode update files are passed to the kernel via loader(8). Thefile type must be "cpu_microcode" in order for the file to be recognizedas a candidate microcode update. Updates for multiple CPU types may beconcatenated together into a single file, in which case the kernelwill select and apply a matching update. Memory used to store theupdate file will be freed back to the system once the update is applied,so this approach will not consume more memory than required.Reviewed by: kibMFC after: 6 weeksSponsored by: The FreeBSD FoundationDifferential Revision: https://reviews.freebsd.org/D16370
Use the existing MSR_BIOS_SIGN on AMD.Reported by: kibSponsored by: The FreeBSD Foundation
Define the MSR used to fetch the current microcode patch level on AMD.It is defined in the AMD family 17h register reference.MFC after: 3 daysSponsored by: The FreeBSD Foundation
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