MFC r353675 from stable-12 (r353651-r353652 from head)...r353651:Relax the sdhci(4) check that filters out the 1.8v voltage option unlessthe slot is flagged as 'embedded'.The features related t
MFC r353675 from stable-12 (r353651-r353652 from head)...r353651:Relax the sdhci(4) check that filters out the 1.8v voltage option unlessthe slot is flagged as 'embedded'.The features related to embedded and shared slots were added in v3.0 ofthe sdhci spec. Hardware prior to v3 sometimes supported 1.8v on non-removable devices in embedded systems, but had no way to indicate thatvia the standard sdhci registers (instead they use out of band metadatasuch as FDT data).This change adds the controller specification version to the check forwhether to filter out the 1.8v selection. On older hardware, the 1.8voption is allowed to remain. On 3.0 or later it still requires theembedded-slot flag to remain.This is part of the fix for PR 241301 (eMMC not detected on Beaglebone).Changes to the sdhci_ti driver are also needed for a full fix.PR: 241301r353652:Revert r351218 (by manu). While the changes in r351218 appear to be (andshould be) correct, they lead to the eMMC on a Beaglebone failing to workin some situations.The TI sdhci hardware is kind of strange. The first device inherentlysupports 1.8v and 3.3v and the abililty to switch between them, and theother two devices must be set to 1.8v in the sdhci power control register tooperate correctly, but doing so actually makes them run at 3.3v (unless anexternal level-shifter is present in the signal path). Even the 1.8v on thefirst device may actually be 3.3v (or any other value), depending on whatvoltage is fed to the VDDS1-VDDS7 power supply pins on the am335x chip.Another strange quirk is that the convention for am335x sdhci drivers inlinux and uboot and the am335x boot ROM seems to be to set the voltage inthe sdhci capabilities register to 3.0v even though the actual voltage is3.3v. Why this is done is a complete mystery to me, but it seems to berequired for correct operation.If we had complete modern support for the am335x chip we could get theactual voltages from the FDT data and the regulator framework. But ouram335x code currently doesn't have any regulator framework support.Reverting to the prior code will get the popular Beaglebone boards workingagain.This is part of the fix for PR 241301, but also requires r353651 for acomplete fix.PR: 241301Discussed with: manuApproved by: re(kib)
show more ...
MFC r350847:Allow the sdhci timeout sysctl var to be set as a tunable. Also, add amissing newline in a warning printf.
MFC r348880, r348882r348880 by loos:Add the GPIO driver for the North/South bridge in Marvell Armada 37x0.The A3700 has a different GPIO controller and thus, do not use the old (andshared) code
MFC r348880, r348882r348880 by loos:Add the GPIO driver for the North/South bridge in Marvell Armada 37x0.The A3700 has a different GPIO controller and thus, do not use the old (andshared) code for Marvell.The pinctrl driver, also part of the controller, is not supported yet (butthe implementation should be straightforward).Sponsored by: Rubicon Communications, LLC (Netgate)r348882 by loos:Add support for the GPIO SD Card VCC regulator/switch and the GPIO SD Carddetection pins to the Marvell Xenon SDHCI controller.These features are enable by 'vqmmc-supply' and 'cd-gpios' properties in theDTS.This fixes the SD Card detection on espressobin.Sponsored by: Rubicon Communications, LLC (Netgate)
MFC r342008, r342010-r342020r342008:fdt: Add support for simple-mfd busQuoting the binding Documentation :"These devices comprise a nexus for heterogeneous hardware blocks containingmore than
MFC r342008, r342010-r342020r342008:fdt: Add support for simple-mfd busQuoting the binding Documentation :"These devices comprise a nexus for heterogeneous hardware blocks containingmore than one non-unique yet varying hardware functionality."Reviewed by: loosSponsored by: Rubicon Communications, LLC ("Netgate")Differential Revision: https://reviews.freebsd.org/D17751r342010:arm64: Add new SoC type MARVELL_8KSponsored by: Rubicon Communications, LLC ("Netgate")r342011:arm64: mvebu_pinctrl: Add driver for Marvell Pinmux ControllerAdd a driver compatible with Marvell mvebu-pinctrl and add ap806-pinctrlsupport.Sponsored by: Rubicon Communications, LCC ("Netgate")r342012:arm64: marvell: Add driver for Marvell Ap806 System ControllerThe first two clocks are for the clusters and their frequencies can befound reading a register. Then a fixed 1200Mhz clock is present and twofixed clocks, 'mss' which is 1200 / 6 and 'sdio' which is 1200 / 3.Sponsored by: Rubicon Communications, LLC ("Netgate")r342013:arm64: mv_gpio: Add Marvell 8K supportWhile here put the interrupts setup in it's own functionSponsored by: Rubicon Communications, LCC ("Netgate")r342014:arm64: marvell: Add cp110 clock controller supportThe cp110 clock controller controls the clocks and gate of the CP110hardware block.Every clock/gate are implemented except the NAND clock.Sponsored by: Rubicon Communications, LLC ("Netgate")r342015:twsi: Clean up marvell part and add support for Marvell 7k/8kSponsored by: Rubicon Communications, LLC ("Netgate")r342016:arm64: Add mv_cp110_icu and mv_cp110_gicpicu is a interrupt concentrator in the CP110 block and gicpis a gic extension to allow interrupts in the CP block to be turnedinto GIC SPI interruptsSponsored by: Rubicon Communications, LLC ("Netgate")r342017:sdhci_xenon: Add Marvell 8k compatible stringSponsored by: Rubicon Communications, LLC ("Netgate")r342018:mv_gpio: Since it's also an interrupt controller, attach soonerSponsored by: Rubicon Communications, LLC ("Netgate")r342019:arm64: mv_cp110_icu: Fix buildr342020:mv_thermal: Add thermal driver for AP806 and CP110 thermal sensorSponsored by: Rubicon Communications, LLC ("Netgate")
MFC r345372: Whitespace cleanup in sdhci.c No functional changes. Replace whitespace by tabs, indent with 4 spaces, coalesce multi-line shorter than 80 characters,
MFC r345370: Align struct sdhci_slot MMCCAM members. Whitespace only, no functional change.
MFC: r342634o Don't allocate resources for SDMA in sdhci(4) if the controller or the front-end doesn't support SDMA or the latter implements a platform- specific transfer method instead. While
MFC: r342634o Don't allocate resources for SDMA in sdhci(4) if the controller or the front-end doesn't support SDMA or the latter implements a platform- specific transfer method instead. While at it, factor out allocation and freeing of SDMA resources to sdhci_dma_{alloc,free}() in order to keep the code more readable when adding support for ADMA variants.o Base the size of the SDMA bounce buffer on MAXPHYS up to the maximum of 512 KiB instead of using a fixed 4-KiB-buffer. With the default MAXPHYS of 128 KiB and depending on the controller and medium, this reduces the number of SDHCI interrupts by a factor of ~16 to ~32 on sequential reads while an increase of throughput of up to ~84 % was seen. Front-ends for broken controllers that only support an SDMA buffer boundary of a specific size may set SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY and supply a size via struct sdhci_slot. According to Linux, only Qualcomm MSM-type SDHCI controllers are affected by this, though. Requested by: Shreyank Amartya (unconditional bump to 512 KiB)o Introduce a SDHCI_DEPEND macro for specifying the dependency of the front-end modules on the sdhci(4) one and bump the module version of sdhci(4) to 2 via an also newly introduced SDHCI_VERSION in order to ensure that all components are in sync WRT struct sdhci_slot.o In sdhci(4): - Make pointers const were applicable, - replace a few device_printf(9) calls with slot_printf() for consistency, and - sync some local functions with their prototypes WRT static.
MFC: r340543, r340654Add a quirk handling for AMDI0040 controllers allowing them to do HS400.Submitted by: Shreyank Amartya (original version)
[sdhci] Add ACPI identifier for AMD eMMC 5.0 controllerSubmitted by: Rajesh Kumar <[email protected]>Approved by: re (rgrimes)Differential Revision: https://reviews.freebsd.org/D17189
- Explicitly compare a pointer to NULL. The __builtin_expect() of clang 3.4.1 otherwise isn't able to cope with the expression.- Fix a nearby whitespace bug.Approved by: re (gjb, kib)
arm64: GENERIC-MMCCAM: Fix build and module dependFix the build of the GENERIC-MMCCAM kernel config after the sdhci_xenondriver was commited.While here correct sdhci_fdt and tegra_sdhci, even wit
arm64: GENERIC-MMCCAM: Fix build and module dependFix the build of the GENERIC-MMCCAM kernel config after the sdhci_xenondriver was commited.While here correct sdhci_fdt and tegra_sdhci, even with MMCCAM they doneed to depend on sdhci(4)Reported by: Reshetnikov Dmitriy <[email protected]>Approved by: re (kib)Sponsored by: Rubicon Communications, LLC ("NetGate")
- According to section 2.2.5 of the SDHCI specification version 4.20, SDHCI_TRNS_ACMD12 is to be set only for multiple-block read/write commands without data length information, so don't uncondit
- According to section 2.2.5 of the SDHCI specification version 4.20, SDHCI_TRNS_ACMD12 is to be set only for multiple-block read/write commands without data length information, so don't unconditionally set this bit. The result matches what e. g. Linux does.- Section 2.2.19 of the SDHCI specification version 4.20 states that SDHCI_ACMD12_ERR should be only valid if SDHCI_INT_ACMD12ERR is set and hardware may clear SDHCI_ACMD12_ERR when SDHCI_INT_ACMD12ERR is cleared (differing silicon behavior is specifically allowed, though). Thus, read SDHCI_ACMD12_ERR before clearing SDHCI_INT_ACMD12ERR. While at it, use the 16-bit accessor rather than the 32-bit one for reading the 16-bit SDHCI_ACMD12_ERR.- SDHCI_INT_TUNEERR isn't one of the ROC bits in SDHCI_INT_STATUS so clear it explicitly.- Add missing prototypes and sort them.
Add support to the Marvell Xenon SDHCI controller.Tested on Espresso.bin (37x0) and Macchiato.bin (8k) with SD cards andeMMCs.Obtained from: pfSenseSponsored by: Rubicon Communications, LLC (Ne
Add support to the Marvell Xenon SDHCI controller.Tested on Espresso.bin (37x0) and Macchiato.bin (8k) with SD cards andeMMCs.Obtained from: pfSenseSponsored by: Rubicon Communications, LLC (Netgate)
The broken DDR52 support of Intel Bay Trail eMMC controllers rumoredin the commit log of r321385 has been confirmed via the public VLI54erratum. Thus, stop advertising DDR52 for these controllers.
The broken DDR52 support of Intel Bay Trail eMMC controllers rumoredin the commit log of r321385 has been confirmed via the public VLI54erratum. Thus, stop advertising DDR52 for these controllers.Note that this change should hardly make a difference in practice aseMMC chips from the same era as these SoCs most likely support HS200at least, probably even up to HS400ES.
Fix build when option MMCCAM is defined.
Don't call sdhci_cleanup_slot() if sdhci_init_slot() never got called.Also, do callout_init() very early in attach, so that callout_drain()can be called in detach without worrying about whether it
Don't call sdhci_cleanup_slot() if sdhci_init_slot() never got called.Also, do callout_init() very early in attach, so that callout_drain()can be called in detach without worrying about whether it ever got init'd.
Add support for SDHCI controller found in Qualcomm Snapdragon 410e.Tested on DragonBoard 410c.Sponsored by: DARPA, AFRL
Fix a bug introduced in r327339; at the point in time re-tuning isexecuted, the interrupt aggregation code might have disabled theSDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE bits in slot->intmaska
Fix a bug introduced in r327339; at the point in time re-tuning isexecuted, the interrupt aggregation code might have disabled theSDHCI_INT_DMA_END and/or SDHCI_INT_RESPONSE bits in slot->intmaskand the SDHCI_SIGNAL_ENABLE register respectively. So when restoringthe interrupt masks based on the previous contents of slot->intmaskin sdhci_exec_tuning(), ensure that the SDHCI_INT_ENABLE registerdoesn't lose these two bits.While at it and in the spirit of r327339, let sdhci_tuning_intmask()set the tuning error and re-tuning interrupt bits based on theSDHCI_TUNING_ENABLED rather than the SDHCI_TUNING_SUPPORTED flagbeing set, i. e. only when (re-)tuning is actually used. Currently,this changes makes no net difference, though.
- There is no need to keep the tuning error and re-tuning interrupts enabled (though, no interrupt generation enabled for them) all the time as soon as (re-)tuning is supported; only enable them
- There is no need to keep the tuning error and re-tuning interrupts enabled (though, no interrupt generation enabled for them) all the time as soon as (re-)tuning is supported; only enable them and let them generate interrupts when actually using (re-)tuning.- Also disable all interrupts except SDHCI_INT_DATA_AVAIL ones while executing tuning and not just their signaling.
Probe Intel Denverton eMMC 5.0 controllers.
sys/dev: further adoption of SPDX licensing ID tags.Mainly focus on files that use BSD 2-Clause license, however the tool Iwas using misidentified many licenses so this was mostly a manual - error
sys/dev: further adoption of SPDX licensing ID tags.Mainly focus on files that use BSD 2-Clause license, however the tool Iwas using misidentified many licenses so this was mostly a manual - errorprone - task.The Software Package Data Exchange (SPDX) group provides a specificationto make it easier for automated tools to detect and summarize well knownopensource licenses. We are gradually adopting the specification, notingthat the tags are considered only advisory and do not, in any way,superceed or replace the license texts.
Actually release resources in detach() rather than just returning EBUSY.This will enable use of 'devctl disable', allow creation of a module, etc.
Rename sdhci_cam_start_slot() into sdhci_start_slot()This change allows to just call sdhci_start_slot() in SDHCI driversand not to think about which stack handles the operation.As a side effect,
Rename sdhci_cam_start_slot() into sdhci_start_slot()This change allows to just call sdhci_start_slot() in SDHCI driversand not to think about which stack handles the operation.As a side effect, this will also fix MMCCAM with sdhci_acpi driver.Approved by: imp (mentor)Differential Revision: https://reviews.freebsd.org/D12471
- Check the slot type capability, set SDHCI_SLOT_{EMBEDDED,NON_REMOVABLE} for embedded slots. Fail in the sdhci(4) initialization for slot type shared, which is completely unsupported by this dri
- Check the slot type capability, set SDHCI_SLOT_{EMBEDDED,NON_REMOVABLE} for embedded slots. Fail in the sdhci(4) initialization for slot type shared, which is completely unsupported by this driver at the moment. [1] For Intel eMMC controllers, taking the embedded slot type into account obsoltes setting SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE so remove these quirk entries.- Hide the 1.8 V VDD capability when the slot is detected as non-embedded, as the SDHCI specification explicitly states that 1.8 V VDD is applicable to embedded slots only. [2]- Define some easy bits of the SDHCI specification v4.20. [3]- Don't leak bus_dma(9) resources in failure paths of sdhci_init_slot().Obtained from: DragonFlyBSD 65704a46 [1], 7ba10b88 [2], 0df14648 [3]
o Add support for eMMC HS200 and HS400 bus speed modes at 200 MHz to sdhci(4), mmc(4) and mmcsd(4). For the most part, this consists of: - Correcting and extending the infrastructure for negotiat
o Add support for eMMC HS200 and HS400 bus speed modes at 200 MHz to sdhci(4), mmc(4) and mmcsd(4). For the most part, this consists of: - Correcting and extending the infrastructure for negotiating and enabling post-DDR52 modes already added as part of r315598. In fact, HS400ES now should work as well but hasn't been activated due to lack of corresponding hardware. - Adding support executing standard SDHCI initial tuning as well as re-tuning as required for eMMC HS200/HS400 and the fast UHS-I SD card modes. Currently, corresponding methods are only hooked up to the ACPI and PCI front-ends of sdhci(4), though. Moreover, sdhci(4) won't offer any modes requiring (re-)tuning to the MMC/SD layer in order to not break operations with other sdhci(4) front- ends. Likewise, sdhci(4) now no longer offers modes requiring the set_uhs_timing method introduced in r315598 to be implemented/ hooked up (previously, this method was used with DDR52 only, which in turn is only available with Intel controllers so far, i. e. no such limitation was necessary before). Similarly for 1.2/1.8 V VCCQ support and the switch_vccq method. - Addition of locking to the IOCTL half of mmcsd(4) to prevent races with detachment and suspension, especially since it's required to immediately switch away from RPMB partitions again after an access to these (so re-tuning can take place anew, given that the current eMMC specification v5.1 doesn't allow tuning commands to be issued with a RPMB partition selected). Therefore, the existing part_mtx lock in the mmcsd(4) softc is additionally renamed to disk_mtx in order to denote that it only refers to the disk(9) half, likewise for corresponding macros. On the system where the addition of DDR52 support increased the read throughput to ~80 MB/s (from ~45 MB/s at high speed), HS200 yields ~154 MB/s and HS400 ~187 MB/s, i. e. performance now has more than quadrupled compared to pre-r315598. Also, with the advent of (re-)tuning support, most infrastructure necessary for SD card UHS-I modes up to SDR104 now is also in place. Note, though, that the standard SDHCI way of (re-)tuning is special in several ways, which also is why sending the actual tuning requests to the device is part of sdhci(4). SDHCI implementations not following the specification, MMC and non-SDHCI SD card controllers likely will use a generic implementation in the MMC/SD layer for executing tuning, which hasn't been written so far, though. However, in fact this isn't a feature-only change; there are boards based on Intel Bay Trail where DDR52 is problematic and the suggested workaround is to use HS200 mode instead. So far exact details are unknown, however, i. e. whether that's due to a defect in these SoCs or on the boards. Moreover, due to the above changes requiring to be aware of possible MMC siblings in the fast path of mmc(4), corresponding information now is cached in mmc_softc. As a side-effect, mmc_calculate_clock(), mmc_delete_cards(), mmc_discover_cards() and mmc_rescan_cards() now all are guaranteed to operate on the same set of devices as there no longer is any use of device_get_children(9), which can fail in low memory situations. Likewise, mmc_calculate_clock() now longer will trigger a panic due to the latter.o Fix a bug in the failure reporting of mmcsd_delete(); in case of an error when the starting block of a previously stored erase request is used (in order to be able to erase a full erase sector worth of data), the starting block of the newly supplied bio_pblkno has to be returned for indicating no progress. Otherwise, upper layers might be told that a negative number of BIOs have been completed, leading to a panic.o Fix 2 bugs on resume: - Things done in fork1(9) like the acquisition of an SX lock or the sleepable memory allocation are incompatible with a MTX_DEF taken. Thus, mmcsd_resume() must not call kproc_create(9), which in turn uses fork1(9), with the disk_mtx (formerly part_mtx) held. - In mmc_suspend(), the bus is powered down, which in the typical case of a device being selected at the time of suspension, causes the device deselection as part of the bus acquisition by mmc(4) in mmc_scan() to fail as the bus isn't powered up again before later in mmc_go_discovery(). Thus, power down with the bus acquired in mmc_suspend(), which will trigger the deselection up-front.o Fix a memory leak in mmcsd_ioctl() in case copyin(9) fails. [1]o Fix missing variable initialization in mmc_switch_status(). [2]o Fix R1_SWITCH_ERROR detection in mmc_switch_status(). [3]o Handle the case of device_add_child(9) failing, for example due to a memory shortage, gracefully in mmc(4) and sdhci(4), including not leaking memory for the instance variables in case of mmc(4) (which might or might not fix [4] as the latter problem has been discovered independently).o Handle the case of an unknown SD CSD version in mmc_decode_csd_sd() gracefully instead of calling panic(9).o Again, check and handle the return values of some additional function calls in mmc(4) instead of assuming that everything went right or mark non-fatal errors by casting the return value to void.o Correct a typo in the Linux IOCTL compatibility; it should have been MMC_IOC_MULTI_CMD rather than MMC_IOC_CMD_MULTI.o Now that we are reaching ever faster speeds (more improvement in this regard is to be expected when adding ADMA support to sdhci(4)), apply a few micro-optimizations like predicting mmc(4) and sdhci(4) debugging to be off or caching erase sector and maximum data sizes as well support of block addressing in mmsd(4) (instead of doing 2 indirections on every read/write request for determining the maximum data size for example).Reported by: CoverityCID: 1372612 [1], 1372624 [2], 1372594 [3], 1007069 [4]
12345