MFC r350231: Correct spelling, partion -> partition.

MFC r341381-r341383, r341385, r343950, r344527, r344576-r344580, r344585, r344589-r344590, r344623, r344626-r344627

r341381:
arm64: rockchip: Add RK3399_CLK_PLL

PLLs on the RK3399 are different tha

MFC r341381-r341383, r341385, r343950, r344527, r344576-r344580, r344585, r344589-r344590, r344623, r344626-r344627

r341381:
arm64: rockchip: Add RK3399_CLK_PLL

PLLs on the RK3399 are different than the ones on the RK3328.
Add a new type and some dedicated recalc and set_freq functions.
Rename the RK3328 dedicated rk_clk_pll function with rk3328_ prefix.

r341382:
arm64/rockchip: add RK3399 support

Add CRU (Clock and Reset Unit) driver for RK3399.
Add support in rk_pinctrl driver.

Submitted by: Greg V <[email protected]> (Original version)
Differential Revision: https://reviews.freebsd.org/D16732

r341383:
arm64: rockchip: rk_i2c: Use correct clock

While here add RK3399 support and call clk_set_assigned to set the correct
clock set in the DTS.

r341385:
arm64: rockchip: rk805: Add basic support for RK808 PMIC

RK808 PMIC is the companion chip for RK3399 SoC.
Add basic regulator support in RK805 since they are similar.

r343950:
arm64: Fix compile when removing SOC_ROCKCHIP_* options

Make every rockchip file depend on the multiple soc_rockchip options
While here make rk_i2c and rk_gpio depend on their device options.

Reported by: sbruno

r344527:
arm64: rockchip: clk: Set the write mask when setting the clock mux

RockChip clocks have a write mask in the upper 16bits of the mux register
which wasn't set in the set_mux function.
Also the wrong parent was tested instead of the real current one, when
switch parent, test with the current one before.

Pointy Hat: manu

r344576:
arm64: rockchip: clk: rk_clk_composite: Properly use the mask bits

RockChip clocks register have a write mask in the upper 16 bits, if a 1
is present the corresponding bit in the lower 16 ones is set.
Use this instead of always setting the mask to 0xFFFF0000.
This avoids a read of the register.
While here add some debug printf useful for debuging clock problems

r344577:
arm64: rockchip: clk: ARM CLK improvement

RockChip clocks register have a write mask in the upper 16 bits, if a 1
is present the corresponding bit in the lower 16 ones is set.
Use this instead of always setting the mask to 0xFFFF0000.
This avoids a read of the register.
While here set the parent after changing its freqeuncy, this reduce the time
between changing the parent and changing the divider for the arm clock.

r344578:
arm64: rockchip: rk3328_pll: Multiple improvement

RockChip clocks register have a write mask in the upper 16 bits, if a 1
is present the corresponding bit in the lower 16 ones is set.
Use this instead of always setting the mask to 0xFFFF0000.
This avoids a read of the register.
While here, when switching PLL frequency, first switch it to slow mode.
When set to slow mode the PLL clock will be the external oscillator.
Changing the PLL parameters while its output is used can cause hang (sometimes).

r344579:
arm64: rockchip: rk805: Add LDO regulators

Add the 3 LDO regulator found in the RK805 Power Management IC.

r344580:
arm64: rockchip: rk805: Map the regulator

No map function was provided before so every regulator lookup resolved
the regulator with id 1, as it uses the default mapper, which is wrong.
Correctly map the regulators.
While here remove some debug printfs and make them disable by default.

r344585:
arm64: rockchip: rk_pinctrl: Fix two banks in RK3328

The last two banks don't have 3 bits for the pin function but only 2.
This fixes eMMC on the Rock64.

r344589:
arm64: rockchip: rk3399_pll: Switch to slow mode when changing the freq

Like r344578 but for RK3399.
This solve some hangs when switching between frequency.

r344590:
arm64: rockchip: rk3399_pll: Fix copy paste

RK3399 PLLs don't have mode_reg, use the correct register.

r344623:
arm64: rockchip: clk_pll: Multiple improvement

Remove the mode_val from the clock definition as it's a bit unreadable.
Use mode_shift to represent which bit control the mode in the register.
Simplify some case where we can avoid a register read before changing it.
Set the PLL back to normal mode after the PLL have stabilized.

Discussed with: mmel

r344626:
arm64: rockchip: rk3399_clk: Add sd clock definitions

r344627:
mmc: dwmmc: Match on "rockchip,rk3288-dw-mshc" compatible

This is the common denominator for rockchip compatible from RK3288 to RK3399.
The other compatible are generally present in the DTS but the controllers
are the same.

show more ...