| d84612e9 | 02-Mar-2020 |
Alex Marginean <[email protected]> |
net/enetc: init SI transactions attribute register
This was left to its default value. With the patch transactions are: - coherent, - do not allocate in downstream cache (there is none on LS1028a),
net/enetc: init SI transactions attribute register
This was left to its default value. With the patch transactions are: - coherent, - do not allocate in downstream cache (there is none on LS1028a), - merge surrounding data for BD writes, - overwrite surrounding data for frame data writes.
Signed-off-by: Alex Marginean <[email protected]> Acked-by: Gagandeep Singh <[email protected]>
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