| 8bdbae66 | 13-Dec-2021 |
Pavan Nikhilesh <[email protected]> |
event/cnxk: add external clock support for timer
Add external clock support for cnxk timer adapter.
External clock mapping is as follows:
RTE_EVENT_TIMER_ADAPTER_EXT_CLK0 = TIM_CLK_SRC_10NS,
RTE_EV
event/cnxk: add external clock support for timer
Add external clock support for cnxk timer adapter.
External clock mapping is as follows:
RTE_EVENT_TIMER_ADAPTER_EXT_CLK0 = TIM_CLK_SRC_10NS,
RTE_EVENT_TIMER_ADAPTER_EXT_CLK1 = TIM_CLK_SRC_GPIO,
RTE_EVENT_TIMER_ADAPTER_EXT_CLK2 = TIM_CLK_SRC_PTP,
RTE_EVENT_TIMER_ADAPTER_EXT_CLK3 = TIM_CLK_SRC_SYNCE,
TIM supports clock input from external GPIO, PTP, SYNCE clocks.
Input resolution is adjusted based on CNTVCT frequency for better
estimation.
Since TIM is unaware of input clock frequency, application is
expected to pass the frequency.
Example:
-a 0002:0e:00.0,tim_eclk_freq=122880000-0-0
The order of frequencies above is GPIO-PTP-SYNCE.
Signed-off-by: Shijith Thotton <[email protected]>
Signed-off-by: Pavan Nikhilesh <[email protected]>
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| fcc5489c | 21-May-2021 |
Timothy McDaniel <[email protected]> |
event/dlb2: select scalar dequeue by default
Optimized dequeue using x86 vector instructions was added
in 21.05, but due to limited testing the default has been
changed back to the scalar mode imple
event/dlb2: select scalar dequeue by default
Optimized dequeue using x86 vector instructions was added
in 21.05, but due to limited testing the default has been
changed back to the scalar mode implementation. The vector mode
implementation can be enabled via the devargs option
"vector_opts_enabled=<y/Y>".
Fixes: 000a7b8e7582 ("event/dlb2: optimize dequeue operation")
Signed-off-by: Timothy McDaniel <[email protected]>
Signed-off-by: David Marchand <[email protected]>
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| 9e35ae07 | 21-May-2021 |
Timothy McDaniel <[email protected]> |
doc: fix runtime options in DLB2 guide
Convert to PCI "--allow" devarg format.
The documentation was previously using the "--vdev" form, which cannot
be used with the DLB2 PF PMD.
Fixes: f3cad285bb
doc: fix runtime options in DLB2 guide
Convert to PCI "--allow" devarg format.
The documentation was previously using the "--vdev" form, which cannot
be used with the DLB2 PF PMD.
Fixes: f3cad285bb88 ("event/dlb2: add infos get and configure")
Fixes: f7cc194b0f7e ("event/dlb2: add enqueue and its burst variants")
Fixes: a2e4f1f5e79f ("event/dlb2: add dequeue and its burst variants")
Fixes: 95aa7101cd3c ("doc: add some features to DLB2 guide")
Cc: [email protected]
Signed-off-by: Timothy McDaniel <[email protected]>
Signed-off-by: David Marchand <[email protected]>
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| 8a3d58c1 | 04-May-2021 |
Shijith Thotton <[email protected]> |
event/cnxk: add option to control timer adapters
Add devargs to control each event timer adapter i.e. TIM rings internal
parameters uniquely. The following dict format is expected
[ring-chnk_slots-d
event/cnxk: add option to control timer adapters
Add devargs to control each event timer adapter i.e. TIM rings internal
parameters uniquely. The following dict format is expected
[ring-chnk_slots-disable_npa-stats_ena]. 0 represents default values.
Example:
--dev "0002:1e:00.0,tim_ring_ctl=[2-1023-1-0]"
Signed-off-by: Pavan Nikhilesh <[email protected]>
Signed-off-by: Shijith Thotton <[email protected]>
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| 7ffa7379 | 04-May-2021 |
Pavan Nikhilesh <[email protected]> |
event/cnxk: add option to configure getwork mode
Add devargs to configure the platform specific getwork mode.
CN9K getwork mode by default is set to use dual workslot mode.
Add option to force sing
event/cnxk: add option to configure getwork mode
Add devargs to configure the platform specific getwork mode.
CN9K getwork mode by default is set to use dual workslot mode.
Add option to force single workslot mode.
Example:
--dev "0002:0e:00.0,single_ws=1"
CN10K supports multiple getwork prefetch modes, by default the
prefetch mode is set to none.
Add option to select getwork prefetch mode
Example:
--dev "0002:1e:00.0,gw_mode=1"
Signed-off-by: Pavan Nikhilesh <[email protected]>
Signed-off-by: Shijith Thotton <[email protected]>
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| 38c2e324 | 04-May-2021 |
Shijith Thotton <[email protected]> |
event/cnxk: add option to control SSO HWGRP QoS
SSO HWGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight
events. By default the buffers are assigned to the SSO HWGRPs to
satisfy minimum HW r
event/cnxk: add option to control SSO HWGRP QoS
SSO HWGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight
events. By default the buffers are assigned to the SSO HWGRPs to
satisfy minimum HW requirements. SSO is free to assign the remaining
buffers to HWGRPs based on a preconfigured threshold.
We can control the QoS of SSO HWGRP by modifying the above mentioned
thresholds. HWGRPs that have higher importance can be assigned higher
thresholds than the rest.
Example:
--dev "0002:0e:00.0,qos=[1-50-50-50]" // [Qx-XAQ-TAQ-IAQ]
Qx -> Event queue Aka SSO GGRP.
XAQ -> DRAM In-flights.
TAQ & IAQ -> SRAM In-flights.
The values need to be expressed in terms of percentages, 0 represents
default.
Signed-off-by: Pavan Nikhilesh <[email protected]>
Signed-off-by: Shijith Thotton <[email protected]>
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| e656d40f | 04-May-2021 |
Shijith Thotton <[email protected]> |
event/cnxk: add option for in-flight buffer count
The number of events for a *open system* event device is specified
as -1 as per the eventdev specification.
Since, SSO inflight events are only limi
event/cnxk: add option for in-flight buffer count
The number of events for a *open system* event device is specified
as -1 as per the eventdev specification.
Since, SSO inflight events are only limited by DRAM size, the
xae_cnt devargs parameter is introduced to provide upper limit for
in-flight events.
Example:
--dev "0002:0e:00.0,xae_cnt=8192"
Signed-off-by: Shijith Thotton <[email protected]>
Signed-off-by: Pavan Nikhilesh <[email protected]>
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