1 // A WORD OF CAUTION 2 // 3 // This entire file basically needs to be kept in sync with itself. It's not 4 // really possible to modify just one bit of this file without understanding 5 // all the other bits. Documentation tries to reference various bits here and 6 // there but try to make sure to read over everything before tweaking things! 7 8 use core::arch::naked_asm; 9 10 #[unsafe(naked)] 11 pub(crate) unsafe extern "C" fn wasmtime_fiber_switch(top_of_stack: *mut u8 /* a0 */) { 12 naked_asm!( 13 " 14 // See https://github.com/rust-lang/rust/issues/80608. 15 .attribute arch, \"rv64gc\" 16 17 // We're switching to arbitrary code somewhere else, so pessimistically 18 // assume that all callee-save register are clobbered. This means we need 19 // to save/restore all of them. 20 // 21 // Note that this order for saving is important since we use CFI directives 22 // below to point to where all the saved registers are. 23 sd ra,-0x8(sp) 24 sd fp,-0x10(sp) 25 sd s1,-0x18(sp) 26 sd s2,-0x20(sp) 27 sd s3,-0x28(sp) 28 sd s4,-0x30(sp) 29 sd s5,-0x38(sp) 30 sd s6,-0x40(sp) 31 sd s7,-0x48(sp) 32 sd s8,-0x50(sp) 33 sd s9,-0x58(sp) 34 sd s10,-0x60(sp) 35 sd s11,-0x68(sp) 36 fsd fs0,-0x70(sp) 37 fsd fs1,-0x78(sp) 38 fsd fs2,-0x80(sp) 39 fsd fs3,-0x88(sp) 40 fsd fs4,-0x90(sp) 41 fsd fs5,-0x98(sp) 42 fsd fs6,-0xa0(sp) 43 fsd fs7,-0xa8(sp) 44 fsd fs8,-0xb0(sp) 45 fsd fs9,-0xb8(sp) 46 fsd fs10,-0xc0(sp) 47 fsd fs11,-0xc8(sp) 48 addi sp , sp , -0xd0 49 50 ld t0 ,-0x10(a0) 51 sd sp ,-0x10(a0) 52 53 // Swap stacks and restore all our callee-saved registers 54 mv sp,t0 55 56 fld fs11,0x8(sp) 57 fld fs10,0x10(sp) 58 fld fs9,0x18(sp) 59 fld fs8,0x20(sp) 60 fld fs7,0x28(sp) 61 fld fs6,0x30(sp) 62 fld fs5,0x38(sp) 63 fld fs4,0x40(sp) 64 fld fs3,0x48(sp) 65 fld fs2,0x50(sp) 66 fld fs1,0x58(sp) 67 fld fs0,0x60(sp) 68 ld s11,0x68(sp) 69 ld s10,0x70(sp) 70 ld s9,0x78(sp) 71 ld s8,0x80(sp) 72 ld s7,0x88(sp) 73 ld s6,0x90(sp) 74 ld s5,0x98(sp) 75 ld s4,0xa0(sp) 76 ld s3,0xa8(sp) 77 ld s2,0xb0(sp) 78 ld s1,0xb8(sp) 79 ld fp,0xc0(sp) 80 ld ra,0xc8(sp) 81 addi sp , sp , 0xd0 82 jr ra 83 ", 84 ); 85 } 86 87 #[unsafe(naked)] 88 pub(crate) unsafe extern "C" fn wasmtime_fiber_init( 89 top_of_stack: *mut u8, // a0 90 entry_point: extern "C" fn(*mut u8, *mut u8), // a1 91 entry_arg0: *mut u8, // a2 92 ) { 93 naked_asm!( 94 " 95 lla t0,{} 96 sd t0,-0x18(a0) // ra,first should be wasmtime_fiber_start. 97 sd a0,-0x20(a0) // fp pointer. 98 sd a1,-0x28(a0) // entry_point will load to s1. 99 sd a2,-0x30(a0) // entry_arg0 will load to s2. 100 101 // 102 addi t0,a0,-0xe0 103 sd t0,-0x10(a0) 104 ret 105 ", 106 sym wasmtime_fiber_start, 107 ); 108 } 109 110 #[unsafe(naked)] 111 unsafe extern "C" fn wasmtime_fiber_start() -> ! { 112 naked_asm!( 113 " 114 .cfi_startproc simple 115 .cfi_def_cfa_offset 0 116 117 118 .cfi_escape 0x0f, /* DW_CFA_def_cfa_expression */ \ 119 5, /* the byte length of this expression */ \ 120 0x52, /* DW_OP_reg2 (sp) */ \ 121 0x06, /* DW_OP_deref */ \ 122 0x08, 0xd0 , /* DW_OP_const1u 0xc8 */ \ 123 0x22 /* DW_OP_plus */ 124 125 126 .cfi_rel_offset ra,-0x8 127 .cfi_rel_offset fp,-0x10 128 .cfi_rel_offset s1,-0x18 129 .cfi_rel_offset s2,-0x20 130 .cfi_rel_offset s3,-0x28 131 .cfi_rel_offset s4,-0x30 132 .cfi_rel_offset s5,-0x38 133 .cfi_rel_offset s6,-0x40 134 .cfi_rel_offset s7,-0x48 135 .cfi_rel_offset s8,-0x50 136 .cfi_rel_offset s9,-0x58 137 .cfi_rel_offset s10,-0x60 138 .cfi_rel_offset s11,-0x68 139 .cfi_rel_offset fs0,-0x70 140 .cfi_rel_offset fs1,-0x78 141 .cfi_rel_offset fs2,-0x80 142 .cfi_rel_offset fs3,-0x88 143 .cfi_rel_offset fs4,-0x90 144 .cfi_rel_offset fs5,-0x98 145 .cfi_rel_offset fs6,-0xa0 146 .cfi_rel_offset fs7,-0xa8 147 .cfi_rel_offset fs8,-0xb0 148 .cfi_rel_offset fs9,-0xb8 149 .cfi_rel_offset fs10,-0xc0 150 .cfi_rel_offset fs11,-0xc8 151 152 mv a0,s2 153 mv a1,fp 154 jalr s1 155 // .4byte 0 will cause panic. 156 // for safety just like x86_64.rs. 157 .4byte 0 158 .cfi_endproc 159 ", 160 ); 161 } 162