1 // GENERATED BY ISLE. DO NOT EDIT!
2 //
3 // Generated automatically from the instruction-selection DSL code in:
4 // - src/clif.isle
5 // - src/prelude.isle
6 // - src/isa/aarch64/inst.isle
7 // - src/isa/aarch64/lower.isle
8 
9 #![allow(dead_code, unreachable_code, unreachable_patterns)]
10 #![allow(unused_imports, unused_variables, non_snake_case, unused_mut)]
11 #![allow(irrefutable_let_patterns)]
12 
13 use super::*; // Pulls in all external types.
14 
15 /// Context during lowering: an implementation of this trait
16 /// must be provided with all external constructors and extractors.
17 /// A mutable borrow is passed along through all lowering logic.
18 pub trait Context {
19     fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
20     fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
21     fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
22     fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
23     fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
24     fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
25     fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
26     fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
27     fn value_regs_invalid(&mut self) -> ValueRegs;
28     fn output_none(&mut self) -> InstOutput;
29     fn output(&mut self, arg0: ValueRegs) -> InstOutput;
30     fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput;
31     fn output_builder_new(&mut self) -> InstOutputBuilder;
32     fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit;
33     fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput;
34     fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
35     fn invalid_reg(&mut self) -> Reg;
36     fn put_in_reg(&mut self, arg0: Value) -> Reg;
37     fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
38     fn ensure_in_vreg(&mut self, arg0: Reg, arg1: Type) -> Reg;
39     fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
40     fn u8_as_u64(&mut self, arg0: u8) -> u64;
41     fn u16_as_u64(&mut self, arg0: u16) -> u64;
42     fn u32_as_u64(&mut self, arg0: u32) -> u64;
43     fn i64_as_u64(&mut self, arg0: i64) -> u64;
44     fn u64_add(&mut self, arg0: u64, arg1: u64) -> u64;
45     fn u64_sub(&mut self, arg0: u64, arg1: u64) -> u64;
46     fn u64_and(&mut self, arg0: u64, arg1: u64) -> u64;
47     fn ty_bits(&mut self, arg0: Type) -> u8;
48     fn ty_bits_u16(&mut self, arg0: Type) -> u16;
49     fn ty_bits_u64(&mut self, arg0: Type) -> u64;
50     fn ty_mask(&mut self, arg0: Type) -> u64;
51     fn ty_bytes(&mut self, arg0: Type) -> u16;
52     fn lane_type(&mut self, arg0: Type) -> Type;
53     fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
54     fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
55     fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
56     fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
57     fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
58     fn ty_int_bool_64(&mut self, arg0: Type) -> Option<Type>;
59     fn ty_int_bool_ref_64(&mut self, arg0: Type) -> Option<Type>;
60     fn ty_int_bool_128(&mut self, arg0: Type) -> Option<Type>;
61     fn ty_scalar_float(&mut self, arg0: Type) -> Option<Type>;
62     fn ty_vec128(&mut self, arg0: Type) -> Option<Type>;
63     fn ty_vec128_int(&mut self, arg0: Type) -> Option<Type>;
64     fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
65     fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
66     fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>;
67     fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>;
68     fn value_slice_len(&mut self, arg0: ValueSlice) -> usize;
69     fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value;
70     fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
71     fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
72     fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
73     fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
74     fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
75     fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
76     fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
77     fn first_result(&mut self, arg0: Inst) -> Option<Value>;
78     fn inst_data(&mut self, arg0: Inst) -> InstructionData;
79     fn value_type(&mut self, arg0: Value) -> Type;
80     fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
81     fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
82     fn offset32_to_u32(&mut self, arg0: Offset32) -> u32;
83     fn emit(&mut self, arg0: &MInst) -> Unit;
84     fn trap_code_division_by_zero(&mut self) -> TrapCode;
85     fn trap_code_integer_overflow(&mut self) -> TrapCode;
86     fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
87     fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
88     fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
89     fn symbol_value_data(
90         &mut self,
91         arg0: GlobalValue,
92     ) -> Option<(ExternalName, RelocDistance, i64)>;
93     fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
94     fn use_lse(&mut self, arg0: Inst) -> Option<()>;
95     fn move_wide_const_from_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
96     fn move_wide_const_from_negated_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
97     fn imm_logic_from_u64(&mut self, arg0: u64, arg1: Type) -> Option<ImmLogic>;
98     fn imm_logic_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmLogic>;
99     fn imm_shift_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmShift>;
100     fn imm_shift_from_u8(&mut self, arg0: u8) -> ImmShift;
101     fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12>;
102     fn u8_into_uimm5(&mut self, arg0: u8) -> UImm5;
103     fn u8_into_imm12(&mut self, arg0: u8) -> Imm12;
104     fn u64_into_imm_logic(&mut self, arg0: Type, arg1: u64) -> ImmLogic;
105     fn imm12_from_negated_u64(&mut self, arg0: u64) -> Option<Imm12>;
106     fn lshl_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ShiftOpAndAmt>;
107     fn integral_ty(&mut self, arg0: Type) -> Option<Type>;
108     fn valid_atomic_transaction(&mut self, arg0: Type) -> Option<Type>;
109     fn extended_value_from_value(&mut self, arg0: Value) -> Option<ExtendedValue>;
110     fn put_extended_in_reg(&mut self, arg0: &ExtendedValue) -> Reg;
111     fn get_extended_op(&mut self, arg0: &ExtendedValue) -> ExtendOp;
112     fn nzcv(&mut self, arg0: bool, arg1: bool, arg2: bool, arg3: bool) -> NZCV;
113     fn cond_br_zero(&mut self, arg0: Reg) -> CondBrKind;
114     fn cond_br_cond(&mut self, arg0: &Cond) -> CondBrKind;
115     fn zero_reg(&mut self) -> Reg;
116     fn writable_zero_reg(&mut self) -> WritableReg;
117     fn xreg(&mut self, arg0: u8) -> Reg;
118     fn writable_xreg(&mut self, arg0: u8) -> WritableReg;
119     fn load_constant64_full(&mut self, arg0: u64) -> Reg;
120     fn sinkable_atomic_load(&mut self, arg0: Value) -> Option<SinkableAtomicLoad>;
121     fn sink_atomic_load(&mut self, arg0: &SinkableAtomicLoad) -> Reg;
122     fn zero_value_f32(&mut self, arg0: Ieee32) -> Option<Ieee32>;
123     fn zero_value_f64(&mut self, arg0: Ieee64) -> Option<Ieee64>;
124     fn float_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &FloatCC) -> VecMisc2;
125     fn float_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &FloatCC) -> VecMisc2;
126     fn fcmp_zero_cond(&mut self, arg0: &FloatCC) -> Option<FloatCC>;
127     fn fcmp_zero_cond_not_eq(&mut self, arg0: &FloatCC) -> Option<FloatCC>;
128     fn zero_value(&mut self, arg0: Imm64) -> Option<Imm64>;
129     fn int_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &IntCC) -> VecMisc2;
130     fn int_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &IntCC) -> VecMisc2;
131     fn icmp_zero_cond(&mut self, arg0: &IntCC) -> Option<IntCC>;
132     fn icmp_zero_cond_not_eq(&mut self, arg0: &IntCC) -> Option<IntCC>;
133     fn safe_divisor_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
134     fn shift_mask(&mut self, arg0: Type) -> ImmLogic;
135     fn negate_imm_shift(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
136     fn rotr_mask(&mut self, arg0: Type) -> ImmLogic;
137     fn rotr_opposite_amount(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
138 }
139 
140 /// Internal type SideEffectNoResult: defined at src/prelude.isle line 412.
141 #[derive(Clone, Debug)]
142 pub enum SideEffectNoResult {
143     Inst { inst: MInst },
144     Inst2 { inst1: MInst, inst2: MInst },
145 }
146 
147 /// Internal type ProducesFlags: defined at src/prelude.isle line 439.
148 #[derive(Clone, Debug)]
149 pub enum ProducesFlags {
150     ProducesFlagsSideEffect { inst: MInst },
151     ProducesFlagsReturnsReg { inst: MInst, result: Reg },
152     ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg },
153 }
154 
155 /// Internal type ConsumesFlags: defined at src/prelude.isle line 450.
156 #[derive(Clone, Debug)]
157 pub enum ConsumesFlags {
158     ConsumesFlagsReturnsResultWithProducer {
159         inst: MInst,
160         result: Reg,
161     },
162     ConsumesFlagsReturnsReg {
163         inst: MInst,
164         result: Reg,
165     },
166     ConsumesFlagsTwiceReturnsValueRegs {
167         inst1: MInst,
168         inst2: MInst,
169         result: ValueRegs,
170     },
171     ConsumesFlagsFourTimesReturnsValueRegs {
172         inst1: MInst,
173         inst2: MInst,
174         inst3: MInst,
175         inst4: MInst,
176         result: ValueRegs,
177     },
178 }
179 
180 /// Internal type MInst: defined at src/isa/aarch64/inst.isle line 2.
181 #[derive(Clone, Debug)]
182 pub enum MInst {
183     Nop0,
184     Nop4,
185     AluRRR {
186         alu_op: ALUOp,
187         size: OperandSize,
188         rd: WritableReg,
189         rn: Reg,
190         rm: Reg,
191     },
192     AluRRRR {
193         alu_op: ALUOp3,
194         size: OperandSize,
195         rd: WritableReg,
196         rn: Reg,
197         rm: Reg,
198         ra: Reg,
199     },
200     AluRRImm12 {
201         alu_op: ALUOp,
202         size: OperandSize,
203         rd: WritableReg,
204         rn: Reg,
205         imm12: Imm12,
206     },
207     AluRRImmLogic {
208         alu_op: ALUOp,
209         size: OperandSize,
210         rd: WritableReg,
211         rn: Reg,
212         imml: ImmLogic,
213     },
214     AluRRImmShift {
215         alu_op: ALUOp,
216         size: OperandSize,
217         rd: WritableReg,
218         rn: Reg,
219         immshift: ImmShift,
220     },
221     AluRRRShift {
222         alu_op: ALUOp,
223         size: OperandSize,
224         rd: WritableReg,
225         rn: Reg,
226         rm: Reg,
227         shiftop: ShiftOpAndAmt,
228     },
229     AluRRRExtend {
230         alu_op: ALUOp,
231         size: OperandSize,
232         rd: WritableReg,
233         rn: Reg,
234         rm: Reg,
235         extendop: ExtendOp,
236     },
237     BitRR {
238         op: BitOp,
239         size: OperandSize,
240         rd: WritableReg,
241         rn: Reg,
242     },
243     ULoad8 {
244         rd: WritableReg,
245         mem: AMode,
246         flags: MemFlags,
247     },
248     SLoad8 {
249         rd: WritableReg,
250         mem: AMode,
251         flags: MemFlags,
252     },
253     ULoad16 {
254         rd: WritableReg,
255         mem: AMode,
256         flags: MemFlags,
257     },
258     SLoad16 {
259         rd: WritableReg,
260         mem: AMode,
261         flags: MemFlags,
262     },
263     ULoad32 {
264         rd: WritableReg,
265         mem: AMode,
266         flags: MemFlags,
267     },
268     SLoad32 {
269         rd: WritableReg,
270         mem: AMode,
271         flags: MemFlags,
272     },
273     ULoad64 {
274         rd: WritableReg,
275         mem: AMode,
276         flags: MemFlags,
277     },
278     Store8 {
279         rd: Reg,
280         mem: AMode,
281         flags: MemFlags,
282     },
283     Store16 {
284         rd: Reg,
285         mem: AMode,
286         flags: MemFlags,
287     },
288     Store32 {
289         rd: Reg,
290         mem: AMode,
291         flags: MemFlags,
292     },
293     Store64 {
294         rd: Reg,
295         mem: AMode,
296         flags: MemFlags,
297     },
298     StoreP64 {
299         rt: Reg,
300         rt2: Reg,
301         mem: PairAMode,
302         flags: MemFlags,
303     },
304     LoadP64 {
305         rt: WritableReg,
306         rt2: WritableReg,
307         mem: PairAMode,
308         flags: MemFlags,
309     },
310     Mov {
311         size: OperandSize,
312         rd: WritableReg,
313         rm: Reg,
314     },
315     MovWide {
316         op: MoveWideOp,
317         rd: WritableReg,
318         imm: MoveWideConst,
319         size: OperandSize,
320     },
321     Extend {
322         rd: WritableReg,
323         rn: Reg,
324         signed: bool,
325         from_bits: u8,
326         to_bits: u8,
327     },
328     CSel {
329         rd: WritableReg,
330         cond: Cond,
331         rn: Reg,
332         rm: Reg,
333     },
334     CSet {
335         rd: WritableReg,
336         cond: Cond,
337     },
338     CSetm {
339         rd: WritableReg,
340         cond: Cond,
341     },
342     CCmpImm {
343         size: OperandSize,
344         rn: Reg,
345         imm: UImm5,
346         nzcv: NZCV,
347         cond: Cond,
348     },
349     AtomicRMWLoop {
350         ty: Type,
351         op: AtomicRMWLoopOp,
352     },
353     AtomicCASLoop {
354         ty: Type,
355     },
356     AtomicRMW {
357         op: AtomicRMWOp,
358         rs: Reg,
359         rt: WritableReg,
360         rn: Reg,
361         ty: Type,
362     },
363     AtomicCAS {
364         rs: WritableReg,
365         rt: Reg,
366         rn: Reg,
367         ty: Type,
368     },
369     LoadAcquire {
370         access_ty: Type,
371         rt: WritableReg,
372         rn: Reg,
373     },
374     StoreRelease {
375         access_ty: Type,
376         rt: Reg,
377         rn: Reg,
378     },
379     Fence,
380     FpuMove64 {
381         rd: WritableReg,
382         rn: Reg,
383     },
384     FpuMove128 {
385         rd: WritableReg,
386         rn: Reg,
387     },
388     FpuMoveFromVec {
389         rd: WritableReg,
390         rn: Reg,
391         idx: u8,
392         size: VectorSize,
393     },
394     FpuExtend {
395         rd: WritableReg,
396         rn: Reg,
397         size: ScalarSize,
398     },
399     FpuRR {
400         fpu_op: FPUOp1,
401         size: ScalarSize,
402         rd: WritableReg,
403         rn: Reg,
404     },
405     FpuRRR {
406         fpu_op: FPUOp2,
407         size: ScalarSize,
408         rd: WritableReg,
409         rn: Reg,
410         rm: Reg,
411     },
412     FpuRRI {
413         fpu_op: FPUOpRI,
414         rd: WritableReg,
415         rn: Reg,
416     },
417     FpuRRRR {
418         fpu_op: FPUOp3,
419         rd: WritableReg,
420         rn: Reg,
421         rm: Reg,
422         ra: Reg,
423     },
424     FpuCmp {
425         size: ScalarSize,
426         rn: Reg,
427         rm: Reg,
428     },
429     FpuLoad32 {
430         rd: WritableReg,
431         mem: AMode,
432         flags: MemFlags,
433     },
434     FpuStore32 {
435         rd: Reg,
436         mem: AMode,
437         flags: MemFlags,
438     },
439     FpuLoad64 {
440         rd: WritableReg,
441         mem: AMode,
442         flags: MemFlags,
443     },
444     FpuStore64 {
445         rd: Reg,
446         mem: AMode,
447         flags: MemFlags,
448     },
449     FpuLoad128 {
450         rd: WritableReg,
451         mem: AMode,
452         flags: MemFlags,
453     },
454     FpuStore128 {
455         rd: Reg,
456         mem: AMode,
457         flags: MemFlags,
458     },
459     FpuLoadP64 {
460         rt: WritableReg,
461         rt2: WritableReg,
462         mem: PairAMode,
463         flags: MemFlags,
464     },
465     FpuStoreP64 {
466         rt: Reg,
467         rt2: Reg,
468         mem: PairAMode,
469         flags: MemFlags,
470     },
471     FpuLoadP128 {
472         rt: WritableReg,
473         rt2: WritableReg,
474         mem: PairAMode,
475         flags: MemFlags,
476     },
477     FpuStoreP128 {
478         rt: Reg,
479         rt2: Reg,
480         mem: PairAMode,
481         flags: MemFlags,
482     },
483     LoadFpuConst64 {
484         rd: WritableReg,
485         const_data: u64,
486     },
487     LoadFpuConst128 {
488         rd: WritableReg,
489         const_data: u128,
490     },
491     FpuToInt {
492         op: FpuToIntOp,
493         rd: WritableReg,
494         rn: Reg,
495     },
496     IntToFpu {
497         op: IntToFpuOp,
498         rd: WritableReg,
499         rn: Reg,
500     },
501     FpuCSel32 {
502         rd: WritableReg,
503         rn: Reg,
504         rm: Reg,
505         cond: Cond,
506     },
507     FpuCSel64 {
508         rd: WritableReg,
509         rn: Reg,
510         rm: Reg,
511         cond: Cond,
512     },
513     FpuRound {
514         op: FpuRoundMode,
515         rd: WritableReg,
516         rn: Reg,
517     },
518     MovToFpu {
519         rd: WritableReg,
520         rn: Reg,
521         size: ScalarSize,
522     },
523     FpuMoveFPImm {
524         rd: WritableReg,
525         imm: ASIMDFPModImm,
526         size: ScalarSize,
527     },
528     MovToVec {
529         rd: WritableReg,
530         rn: Reg,
531         idx: u8,
532         size: VectorSize,
533     },
534     MovFromVec {
535         rd: WritableReg,
536         rn: Reg,
537         idx: u8,
538         size: VectorSize,
539     },
540     MovFromVecSigned {
541         rd: WritableReg,
542         rn: Reg,
543         idx: u8,
544         size: VectorSize,
545         scalar_size: OperandSize,
546     },
547     VecDup {
548         rd: WritableReg,
549         rn: Reg,
550         size: VectorSize,
551     },
552     VecDupFromFpu {
553         rd: WritableReg,
554         rn: Reg,
555         size: VectorSize,
556     },
557     VecDupFPImm {
558         rd: WritableReg,
559         imm: ASIMDFPModImm,
560         size: VectorSize,
561     },
562     VecDupImm {
563         rd: WritableReg,
564         imm: ASIMDMovModImm,
565         invert: bool,
566         size: VectorSize,
567     },
568     VecExtend {
569         t: VecExtendOp,
570         rd: WritableReg,
571         rn: Reg,
572         high_half: bool,
573     },
574     VecMovElement {
575         rd: WritableReg,
576         rn: Reg,
577         dest_idx: u8,
578         src_idx: u8,
579         size: VectorSize,
580     },
581     VecRRLong {
582         op: VecRRLongOp,
583         rd: WritableReg,
584         rn: Reg,
585         high_half: bool,
586     },
587     VecRRNarrow {
588         op: VecRRNarrowOp,
589         rd: WritableReg,
590         rn: Reg,
591         high_half: bool,
592     },
593     VecRRPair {
594         op: VecPairOp,
595         rd: WritableReg,
596         rn: Reg,
597     },
598     VecRRRLong {
599         alu_op: VecRRRLongOp,
600         rd: WritableReg,
601         rn: Reg,
602         rm: Reg,
603         high_half: bool,
604     },
605     VecRRPairLong {
606         op: VecRRPairLongOp,
607         rd: WritableReg,
608         rn: Reg,
609     },
610     VecRRR {
611         alu_op: VecALUOp,
612         rd: WritableReg,
613         rn: Reg,
614         rm: Reg,
615         size: VectorSize,
616     },
617     VecMisc {
618         op: VecMisc2,
619         rd: WritableReg,
620         rn: Reg,
621         size: VectorSize,
622     },
623     VecLanes {
624         op: VecLanesOp,
625         rd: WritableReg,
626         rn: Reg,
627         size: VectorSize,
628     },
629     VecShiftImm {
630         op: VecShiftImmOp,
631         rd: WritableReg,
632         rn: Reg,
633         size: VectorSize,
634         imm: u8,
635     },
636     VecExtract {
637         rd: WritableReg,
638         rn: Reg,
639         rm: Reg,
640         imm4: u8,
641     },
642     VecTbl {
643         rd: WritableReg,
644         rn: Reg,
645         rm: Reg,
646         is_extension: bool,
647     },
648     VecTbl2 {
649         rd: WritableReg,
650         rn: Reg,
651         rn2: Reg,
652         rm: Reg,
653         is_extension: bool,
654     },
655     VecLoadReplicate {
656         rd: WritableReg,
657         rn: Reg,
658         size: VectorSize,
659     },
660     VecCSel {
661         rd: WritableReg,
662         rn: Reg,
663         rm: Reg,
664         cond: Cond,
665     },
666     MovToNZCV {
667         rn: Reg,
668     },
669     MovFromNZCV {
670         rd: WritableReg,
671     },
672     Call {
673         info: BoxCallInfo,
674     },
675     CallInd {
676         info: BoxCallIndInfo,
677     },
678     Ret {
679         rets: VecReg,
680     },
681     EpiloguePlaceholder,
682     Jump {
683         dest: BranchTarget,
684     },
685     CondBr {
686         taken: BranchTarget,
687         not_taken: BranchTarget,
688         kind: CondBrKind,
689     },
690     TrapIf {
691         kind: CondBrKind,
692         trap_code: TrapCode,
693     },
694     IndirectBr {
695         rn: Reg,
696         targets: VecMachLabel,
697     },
698     Brk,
699     Udf {
700         trap_code: TrapCode,
701     },
702     Adr {
703         rd: WritableReg,
704         off: i32,
705     },
706     Word4 {
707         data: u32,
708     },
709     Word8 {
710         data: u64,
711     },
712     JTSequence {
713         info: BoxJTSequenceInfo,
714         ridx: Reg,
715         rtmp1: WritableReg,
716         rtmp2: WritableReg,
717     },
718     LoadExtName {
719         rd: WritableReg,
720         name: BoxExternalName,
721         offset: i64,
722     },
723     LoadAddr {
724         rd: WritableReg,
725         mem: AMode,
726     },
727     VirtualSPOffsetAdj {
728         offset: i64,
729     },
730     EmitIsland {
731         needed_space: CodeOffset,
732     },
733     ElfTlsGetAddr {
734         symbol: ExternalName,
735     },
736     Unwind {
737         inst: UnwindInst,
738     },
739     DummyUse {
740         reg: Reg,
741     },
742 }
743 
744 /// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 776.
745 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
746 pub enum ALUOp {
747     Add,
748     Sub,
749     Orr,
750     OrrNot,
751     And,
752     AndS,
753     AndNot,
754     Eor,
755     EorNot,
756     AddS,
757     SubS,
758     SMulH,
759     UMulH,
760     SDiv,
761     UDiv,
762     RotR,
763     Lsr,
764     Asr,
765     Lsl,
766     Adc,
767     AdcS,
768     Sbc,
769     SbcS,
770 }
771 
772 /// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 814.
773 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
774 pub enum ALUOp3 {
775     MAdd,
776     MSub,
777 }
778 
779 /// Internal type MoveWideOp: defined at src/isa/aarch64/inst.isle line 822.
780 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
781 pub enum MoveWideOp {
782     MovZ,
783     MovN,
784     MovK,
785 }
786 
787 /// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 860.
788 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
789 pub enum BitOp {
790     RBit,
791     Clz,
792     Cls,
793 }
794 
795 /// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 927.
796 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
797 pub enum FPUOp1 {
798     Abs,
799     Neg,
800     Sqrt,
801     Cvt32To64,
802     Cvt64To32,
803 }
804 
805 /// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 937.
806 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
807 pub enum FPUOp2 {
808     Add,
809     Sub,
810     Mul,
811     Div,
812     Max,
813     Min,
814 }
815 
816 /// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 948.
817 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
818 pub enum FPUOp3 {
819     MAdd32,
820     MAdd64,
821 }
822 
823 /// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 955.
824 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
825 pub enum FpuToIntOp {
826     F32ToU32,
827     F32ToI32,
828     F32ToU64,
829     F32ToI64,
830     F64ToU32,
831     F64ToI32,
832     F64ToU64,
833     F64ToI64,
834 }
835 
836 /// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 968.
837 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
838 pub enum IntToFpuOp {
839     U32ToF32,
840     I32ToF32,
841     U32ToF64,
842     I32ToF64,
843     U64ToF32,
844     I64ToF32,
845     U64ToF64,
846     I64ToF64,
847 }
848 
849 /// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 982.
850 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
851 pub enum FpuRoundMode {
852     Minus32,
853     Minus64,
854     Plus32,
855     Plus64,
856     Zero32,
857     Zero64,
858     Nearest32,
859     Nearest64,
860 }
861 
862 /// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 995.
863 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
864 pub enum VecExtendOp {
865     Sxtl8,
866     Sxtl16,
867     Sxtl32,
868     Uxtl8,
869     Uxtl16,
870     Uxtl32,
871 }
872 
873 /// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1012.
874 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
875 pub enum VecALUOp {
876     Sqadd,
877     Uqadd,
878     Sqsub,
879     Uqsub,
880     Cmeq,
881     Cmge,
882     Cmgt,
883     Cmhs,
884     Cmhi,
885     Fcmeq,
886     Fcmgt,
887     Fcmge,
888     And,
889     Bic,
890     Orr,
891     Eor,
892     Bsl,
893     Umaxp,
894     Add,
895     Sub,
896     Mul,
897     Sshl,
898     Ushl,
899     Umin,
900     Smin,
901     Umax,
902     Smax,
903     Urhadd,
904     Fadd,
905     Fsub,
906     Fdiv,
907     Fmax,
908     Fmin,
909     Fmul,
910     Addp,
911     Zip1,
912     Sqrdmulh,
913 }
914 
915 /// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1091.
916 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
917 pub enum VecMisc2 {
918     Not,
919     Neg,
920     Abs,
921     Fabs,
922     Fneg,
923     Fsqrt,
924     Rev64,
925     Fcvtzs,
926     Fcvtzu,
927     Scvtf,
928     Ucvtf,
929     Frintn,
930     Frintz,
931     Frintm,
932     Frintp,
933     Cnt,
934     Cmeq0,
935     Cmge0,
936     Cmgt0,
937     Cmle0,
938     Cmlt0,
939     Fcmeq0,
940     Fcmge0,
941     Fcmgt0,
942     Fcmle0,
943     Fcmlt0,
944 }
945 
946 /// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1148.
947 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
948 pub enum VecRRLongOp {
949     Fcvtl16,
950     Fcvtl32,
951     Shll8,
952     Shll16,
953     Shll32,
954 }
955 
956 /// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1163.
957 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
958 pub enum VecRRNarrowOp {
959     Xtn16,
960     Xtn32,
961     Xtn64,
962     Sqxtn16,
963     Sqxtn32,
964     Sqxtn64,
965     Sqxtun16,
966     Sqxtun32,
967     Sqxtun64,
968     Uqxtn16,
969     Uqxtn32,
970     Uqxtn64,
971     Fcvtn32,
972     Fcvtn64,
973 }
974 
975 /// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1195.
976 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
977 pub enum VecRRRLongOp {
978     Smull8,
979     Smull16,
980     Smull32,
981     Umull8,
982     Umull16,
983     Umull32,
984     Umlal8,
985     Umlal16,
986     Umlal32,
987 }
988 
989 /// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1212.
990 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
991 pub enum VecPairOp {
992     Addp,
993 }
994 
995 /// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1220.
996 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
997 pub enum VecRRPairLongOp {
998     Saddlp8,
999     Saddlp16,
1000     Uaddlp8,
1001     Uaddlp16,
1002 }
1003 
1004 /// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1231.
1005 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1006 pub enum VecLanesOp {
1007     Addv,
1008     Uminv,
1009 }
1010 
1011 /// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1240.
1012 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1013 pub enum VecShiftImmOp {
1014     Shl,
1015     Ushr,
1016     Sshr,
1017 }
1018 
1019 /// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1251.
1020 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1021 pub enum AtomicRMWOp {
1022     Add,
1023     Clr,
1024     Eor,
1025     Set,
1026     Smax,
1027     Smin,
1028     Umax,
1029     Umin,
1030     Swp,
1031 }
1032 
1033 /// Internal type AtomicRMWLoopOp: defined at src/isa/aarch64/inst.isle line 1266.
1034 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1035 pub enum AtomicRMWLoopOp {
1036     Add,
1037     Sub,
1038     And,
1039     Nand,
1040     Eor,
1041     Orr,
1042     Smax,
1043     Smin,
1044     Umax,
1045     Umin,
1046     Xchg,
1047 }
1048 
1049 // Generated as internal constructor for term output_reg.
1050 pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
1051     let pattern0_0 = arg0;
1052     // Rule at src/prelude.isle line 86.
1053     let expr0_0 = C::value_reg(ctx, pattern0_0);
1054     let expr1_0 = C::output(ctx, expr0_0);
1055     return Some(expr1_0);
1056 }
1057 
1058 // Generated as internal constructor for term output_value.
1059 pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> {
1060     let pattern0_0 = arg0;
1061     // Rule at src/prelude.isle line 90.
1062     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1063     let expr1_0 = C::output(ctx, expr0_0);
1064     return Some(expr1_0);
1065 }
1066 
1067 // Generated as internal constructor for term temp_reg.
1068 pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
1069     let pattern0_0 = arg0;
1070     // Rule at src/prelude.isle line 110.
1071     let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
1072     let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
1073     return Some(expr1_0);
1074 }
1075 
1076 // Generated as internal constructor for term lo_reg.
1077 pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
1078     let pattern0_0 = arg0;
1079     // Rule at src/prelude.isle line 150.
1080     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1081     let expr1_0: usize = 0;
1082     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1083     return Some(expr2_0);
1084 }
1085 
1086 // Generated as internal constructor for term side_effect.
1087 pub fn constructor_side_effect<C: Context>(
1088     ctx: &mut C,
1089     arg0: &SideEffectNoResult,
1090 ) -> Option<InstOutput> {
1091     let pattern0_0 = arg0;
1092     match pattern0_0 {
1093         &SideEffectNoResult::Inst {
1094             inst: ref pattern1_0,
1095         } => {
1096             // Rule at src/prelude.isle line 420.
1097             let expr0_0 = C::emit(ctx, pattern1_0);
1098             let expr1_0 = C::output_none(ctx);
1099             return Some(expr1_0);
1100         }
1101         &SideEffectNoResult::Inst2 {
1102             inst1: ref pattern1_0,
1103             inst2: ref pattern1_1,
1104         } => {
1105             // Rule at src/prelude.isle line 423.
1106             let expr0_0 = C::emit(ctx, pattern1_0);
1107             let expr1_0 = C::emit(ctx, pattern1_1);
1108             let expr2_0 = C::output_none(ctx);
1109             return Some(expr2_0);
1110         }
1111         _ => {}
1112     }
1113     return None;
1114 }
1115 
1116 // Generated as internal constructor for term side_effect_concat.
1117 pub fn constructor_side_effect_concat<C: Context>(
1118     ctx: &mut C,
1119     arg0: &SideEffectNoResult,
1120     arg1: &SideEffectNoResult,
1121 ) -> Option<SideEffectNoResult> {
1122     let pattern0_0 = arg0;
1123     if let &SideEffectNoResult::Inst {
1124         inst: ref pattern1_0,
1125     } = pattern0_0
1126     {
1127         let pattern2_0 = arg1;
1128         if let &SideEffectNoResult::Inst {
1129             inst: ref pattern3_0,
1130         } = pattern2_0
1131         {
1132             // Rule at src/prelude.isle line 429.
1133             let expr0_0 = SideEffectNoResult::Inst2 {
1134                 inst1: pattern1_0.clone(),
1135                 inst2: pattern3_0.clone(),
1136             };
1137             return Some(expr0_0);
1138         }
1139     }
1140     return None;
1141 }
1142 
1143 // Generated as internal constructor for term produces_flags_get_reg.
1144 pub fn constructor_produces_flags_get_reg<C: Context>(
1145     ctx: &mut C,
1146     arg0: &ProducesFlags,
1147 ) -> Option<Reg> {
1148     let pattern0_0 = arg0;
1149     if let &ProducesFlags::ProducesFlagsReturnsReg {
1150         inst: ref pattern1_0,
1151         result: pattern1_1,
1152     } = pattern0_0
1153     {
1154         // Rule at src/prelude.isle line 466.
1155         return Some(pattern1_1);
1156     }
1157     return None;
1158 }
1159 
1160 // Generated as internal constructor for term produces_flags_ignore.
1161 pub fn constructor_produces_flags_ignore<C: Context>(
1162     ctx: &mut C,
1163     arg0: &ProducesFlags,
1164 ) -> Option<ProducesFlags> {
1165     let pattern0_0 = arg0;
1166     match pattern0_0 {
1167         &ProducesFlags::ProducesFlagsReturnsReg {
1168             inst: ref pattern1_0,
1169             result: pattern1_1,
1170         } => {
1171             // Rule at src/prelude.isle line 471.
1172             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1173                 inst: pattern1_0.clone(),
1174             };
1175             return Some(expr0_0);
1176         }
1177         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1178             inst: ref pattern1_0,
1179             result: pattern1_1,
1180         } => {
1181             // Rule at src/prelude.isle line 473.
1182             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1183                 inst: pattern1_0.clone(),
1184             };
1185             return Some(expr0_0);
1186         }
1187         _ => {}
1188     }
1189     return None;
1190 }
1191 
1192 // Generated as internal constructor for term consumes_flags_concat.
1193 pub fn constructor_consumes_flags_concat<C: Context>(
1194     ctx: &mut C,
1195     arg0: &ConsumesFlags,
1196     arg1: &ConsumesFlags,
1197 ) -> Option<ConsumesFlags> {
1198     let pattern0_0 = arg0;
1199     if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1200         inst: ref pattern1_0,
1201         result: pattern1_1,
1202     } = pattern0_0
1203     {
1204         let pattern2_0 = arg1;
1205         if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1206             inst: ref pattern3_0,
1207             result: pattern3_1,
1208         } = pattern2_0
1209         {
1210             // Rule at src/prelude.isle line 480.
1211             let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1212             let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1213                 inst1: pattern1_0.clone(),
1214                 inst2: pattern3_0.clone(),
1215                 result: expr0_0,
1216             };
1217             return Some(expr1_0);
1218         }
1219     }
1220     return None;
1221 }
1222 
1223 // Generated as internal constructor for term with_flags.
1224 pub fn constructor_with_flags<C: Context>(
1225     ctx: &mut C,
1226     arg0: &ProducesFlags,
1227     arg1: &ConsumesFlags,
1228 ) -> Option<ValueRegs> {
1229     let pattern0_0 = arg0;
1230     match pattern0_0 {
1231         &ProducesFlags::ProducesFlagsSideEffect {
1232             inst: ref pattern1_0,
1233         } => {
1234             let pattern2_0 = arg1;
1235             match pattern2_0 {
1236                 &ConsumesFlags::ConsumesFlagsReturnsReg {
1237                     inst: ref pattern3_0,
1238                     result: pattern3_1,
1239                 } => {
1240                     // Rule at src/prelude.isle line 505.
1241                     let expr0_0 = C::emit(ctx, pattern1_0);
1242                     let expr1_0 = C::emit(ctx, pattern3_0);
1243                     let expr2_0 = C::value_reg(ctx, pattern3_1);
1244                     return Some(expr2_0);
1245                 }
1246                 &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1247                     inst1: ref pattern3_0,
1248                     inst2: ref pattern3_1,
1249                     result: pattern3_2,
1250                 } => {
1251                     // Rule at src/prelude.isle line 511.
1252                     let expr0_0 = C::emit(ctx, pattern1_0);
1253                     let expr1_0 = C::emit(ctx, pattern3_0);
1254                     let expr2_0 = C::emit(ctx, pattern3_1);
1255                     return Some(pattern3_2);
1256                 }
1257                 &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs {
1258                     inst1: ref pattern3_0,
1259                     inst2: ref pattern3_1,
1260                     inst3: ref pattern3_2,
1261                     inst4: ref pattern3_3,
1262                     result: pattern3_4,
1263                 } => {
1264                     // Rule at src/prelude.isle line 523.
1265                     let expr0_0 = C::emit(ctx, pattern1_0);
1266                     let expr1_0 = C::emit(ctx, pattern3_0);
1267                     let expr2_0 = C::emit(ctx, pattern3_1);
1268                     let expr3_0 = C::emit(ctx, pattern3_2);
1269                     let expr4_0 = C::emit(ctx, pattern3_3);
1270                     return Some(pattern3_4);
1271                 }
1272                 _ => {}
1273             }
1274         }
1275         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1276             inst: ref pattern1_0,
1277             result: pattern1_1,
1278         } => {
1279             let pattern2_0 = arg1;
1280             if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1281                 inst: ref pattern3_0,
1282                 result: pattern3_1,
1283             } = pattern2_0
1284             {
1285                 // Rule at src/prelude.isle line 499.
1286                 let expr0_0 = C::emit(ctx, pattern1_0);
1287                 let expr1_0 = C::emit(ctx, pattern3_0);
1288                 let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1289                 return Some(expr2_0);
1290             }
1291         }
1292         _ => {}
1293     }
1294     return None;
1295 }
1296 
1297 // Generated as internal constructor for term with_flags_reg.
1298 pub fn constructor_with_flags_reg<C: Context>(
1299     ctx: &mut C,
1300     arg0: &ProducesFlags,
1301     arg1: &ConsumesFlags,
1302 ) -> Option<Reg> {
1303     let pattern0_0 = arg0;
1304     let pattern1_0 = arg1;
1305     // Rule at src/prelude.isle line 540.
1306     let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?;
1307     let expr1_0: usize = 0;
1308     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1309     return Some(expr2_0);
1310 }
1311 
1312 // Generated as internal constructor for term operand_size.
1313 pub fn constructor_operand_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
1314     let pattern0_0 = arg0;
1315     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
1316         // Rule at src/isa/aarch64/inst.isle line 878.
1317         let expr0_0 = OperandSize::Size32;
1318         return Some(expr0_0);
1319     }
1320     if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
1321         // Rule at src/isa/aarch64/inst.isle line 879.
1322         let expr0_0 = OperandSize::Size64;
1323         return Some(expr0_0);
1324     }
1325     return None;
1326 }
1327 
1328 // Generated as internal constructor for term vector_size.
1329 pub fn constructor_vector_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<VectorSize> {
1330     let pattern0_0 = arg0;
1331     if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
1332         if pattern1_0 == 8 {
1333             if pattern1_1 == 16 {
1334                 // Rule at src/isa/aarch64/inst.isle line 921.
1335                 let expr0_0 = VectorSize::Size8x16;
1336                 return Some(expr0_0);
1337             }
1338         }
1339         if pattern1_0 == 16 {
1340             if pattern1_1 == 8 {
1341                 // Rule at src/isa/aarch64/inst.isle line 922.
1342                 let expr0_0 = VectorSize::Size16x8;
1343                 return Some(expr0_0);
1344             }
1345         }
1346         if pattern1_0 == 32 {
1347             if pattern1_1 == 4 {
1348                 // Rule at src/isa/aarch64/inst.isle line 923.
1349                 let expr0_0 = VectorSize::Size32x4;
1350                 return Some(expr0_0);
1351             }
1352         }
1353         if pattern1_0 == 64 {
1354             if pattern1_1 == 2 {
1355                 // Rule at src/isa/aarch64/inst.isle line 924.
1356                 let expr0_0 = VectorSize::Size64x2;
1357                 return Some(expr0_0);
1358             }
1359         }
1360     }
1361     return None;
1362 }
1363 
1364 // Generated as internal constructor for term mov64_to_real.
1365 pub fn constructor_mov64_to_real<C: Context>(ctx: &mut C, arg0: u8, arg1: Reg) -> Option<Reg> {
1366     let pattern0_0 = arg0;
1367     let pattern1_0 = arg1;
1368     // Rule at src/isa/aarch64/inst.isle line 1379.
1369     let expr0_0 = C::writable_xreg(ctx, pattern0_0);
1370     let expr1_0: Type = I64;
1371     let expr2_0 = constructor_operand_size(ctx, expr1_0)?;
1372     let expr3_0 = MInst::Mov {
1373         size: expr2_0,
1374         rd: expr0_0,
1375         rm: pattern1_0,
1376     };
1377     let expr4_0 = C::emit(ctx, &expr3_0);
1378     let expr5_0 = C::writable_reg_to_reg(ctx, expr0_0);
1379     return Some(expr5_0);
1380 }
1381 
1382 // Generated as internal constructor for term mov64_from_real.
1383 pub fn constructor_mov64_from_real<C: Context>(ctx: &mut C, arg0: u8) -> Option<Reg> {
1384     let pattern0_0 = arg0;
1385     // Rule at src/isa/aarch64/inst.isle line 1385.
1386     let expr0_0: Type = I64;
1387     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1388     let expr2_0: Type = I64;
1389     let expr3_0 = constructor_operand_size(ctx, expr2_0)?;
1390     let expr4_0 = C::xreg(ctx, pattern0_0);
1391     let expr5_0 = MInst::Mov {
1392         size: expr3_0,
1393         rd: expr1_0,
1394         rm: expr4_0,
1395     };
1396     let expr6_0 = C::emit(ctx, &expr5_0);
1397     let expr7_0 = C::writable_reg_to_reg(ctx, expr1_0);
1398     return Some(expr7_0);
1399 }
1400 
1401 // Generated as internal constructor for term movz.
1402 pub fn constructor_movz<C: Context>(
1403     ctx: &mut C,
1404     arg0: MoveWideConst,
1405     arg1: &OperandSize,
1406 ) -> Option<Reg> {
1407     let pattern0_0 = arg0;
1408     let pattern1_0 = arg1;
1409     // Rule at src/isa/aarch64/inst.isle line 1392.
1410     let expr0_0: Type = I64;
1411     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1412     let expr2_0 = MoveWideOp::MovZ;
1413     let expr3_0 = MInst::MovWide {
1414         op: expr2_0,
1415         rd: expr1_0,
1416         imm: pattern0_0,
1417         size: pattern1_0.clone(),
1418     };
1419     let expr4_0 = C::emit(ctx, &expr3_0);
1420     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1421     return Some(expr5_0);
1422 }
1423 
1424 // Generated as internal constructor for term movn.
1425 pub fn constructor_movn<C: Context>(
1426     ctx: &mut C,
1427     arg0: MoveWideConst,
1428     arg1: &OperandSize,
1429 ) -> Option<Reg> {
1430     let pattern0_0 = arg0;
1431     let pattern1_0 = arg1;
1432     // Rule at src/isa/aarch64/inst.isle line 1399.
1433     let expr0_0: Type = I64;
1434     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1435     let expr2_0 = MoveWideOp::MovN;
1436     let expr3_0 = MInst::MovWide {
1437         op: expr2_0,
1438         rd: expr1_0,
1439         imm: pattern0_0,
1440         size: pattern1_0.clone(),
1441     };
1442     let expr4_0 = C::emit(ctx, &expr3_0);
1443     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1444     return Some(expr5_0);
1445 }
1446 
1447 // Generated as internal constructor for term alu_rr_imm_logic.
1448 pub fn constructor_alu_rr_imm_logic<C: Context>(
1449     ctx: &mut C,
1450     arg0: &ALUOp,
1451     arg1: Type,
1452     arg2: Reg,
1453     arg3: ImmLogic,
1454 ) -> Option<Reg> {
1455     let pattern0_0 = arg0;
1456     let pattern1_0 = arg1;
1457     let pattern2_0 = arg2;
1458     let pattern3_0 = arg3;
1459     // Rule at src/isa/aarch64/inst.isle line 1406.
1460     let expr0_0: Type = I64;
1461     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1462     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1463     let expr3_0 = MInst::AluRRImmLogic {
1464         alu_op: pattern0_0.clone(),
1465         size: expr2_0,
1466         rd: expr1_0,
1467         rn: pattern2_0,
1468         imml: pattern3_0,
1469     };
1470     let expr4_0 = C::emit(ctx, &expr3_0);
1471     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1472     return Some(expr5_0);
1473 }
1474 
1475 // Generated as internal constructor for term alu_rr_imm_shift.
1476 pub fn constructor_alu_rr_imm_shift<C: Context>(
1477     ctx: &mut C,
1478     arg0: &ALUOp,
1479     arg1: Type,
1480     arg2: Reg,
1481     arg3: ImmShift,
1482 ) -> Option<Reg> {
1483     let pattern0_0 = arg0;
1484     let pattern1_0 = arg1;
1485     let pattern2_0 = arg2;
1486     let pattern3_0 = arg3;
1487     // Rule at src/isa/aarch64/inst.isle line 1413.
1488     let expr0_0: Type = I64;
1489     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1490     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1491     let expr3_0 = MInst::AluRRImmShift {
1492         alu_op: pattern0_0.clone(),
1493         size: expr2_0,
1494         rd: expr1_0,
1495         rn: pattern2_0,
1496         immshift: pattern3_0,
1497     };
1498     let expr4_0 = C::emit(ctx, &expr3_0);
1499     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1500     return Some(expr5_0);
1501 }
1502 
1503 // Generated as internal constructor for term alu_rrr.
1504 pub fn constructor_alu_rrr<C: Context>(
1505     ctx: &mut C,
1506     arg0: &ALUOp,
1507     arg1: Type,
1508     arg2: Reg,
1509     arg3: Reg,
1510 ) -> Option<Reg> {
1511     let pattern0_0 = arg0;
1512     let pattern1_0 = arg1;
1513     let pattern2_0 = arg2;
1514     let pattern3_0 = arg3;
1515     // Rule at src/isa/aarch64/inst.isle line 1420.
1516     let expr0_0: Type = I64;
1517     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1518     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1519     let expr3_0 = MInst::AluRRR {
1520         alu_op: pattern0_0.clone(),
1521         size: expr2_0,
1522         rd: expr1_0,
1523         rn: pattern2_0,
1524         rm: pattern3_0,
1525     };
1526     let expr4_0 = C::emit(ctx, &expr3_0);
1527     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1528     return Some(expr5_0);
1529 }
1530 
1531 // Generated as internal constructor for term vec_rrr.
1532 pub fn constructor_vec_rrr<C: Context>(
1533     ctx: &mut C,
1534     arg0: &VecALUOp,
1535     arg1: Reg,
1536     arg2: Reg,
1537     arg3: &VectorSize,
1538 ) -> Option<Reg> {
1539     let pattern0_0 = arg0;
1540     let pattern1_0 = arg1;
1541     let pattern2_0 = arg2;
1542     let pattern3_0 = arg3;
1543     // Rule at src/isa/aarch64/inst.isle line 1427.
1544     let expr0_0: Type = I8X16;
1545     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1546     let expr2_0 = MInst::VecRRR {
1547         alu_op: pattern0_0.clone(),
1548         rd: expr1_0,
1549         rn: pattern1_0,
1550         rm: pattern2_0,
1551         size: pattern3_0.clone(),
1552     };
1553     let expr3_0 = C::emit(ctx, &expr2_0);
1554     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1555     return Some(expr4_0);
1556 }
1557 
1558 // Generated as internal constructor for term vec_lanes.
1559 pub fn constructor_vec_lanes<C: Context>(
1560     ctx: &mut C,
1561     arg0: &VecLanesOp,
1562     arg1: Reg,
1563     arg2: &VectorSize,
1564 ) -> Option<Reg> {
1565     let pattern0_0 = arg0;
1566     let pattern1_0 = arg1;
1567     let pattern2_0 = arg2;
1568     // Rule at src/isa/aarch64/inst.isle line 1434.
1569     let expr0_0: Type = I8X16;
1570     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1571     let expr2_0 = MInst::VecLanes {
1572         op: pattern0_0.clone(),
1573         rd: expr1_0,
1574         rn: pattern1_0,
1575         size: pattern2_0.clone(),
1576     };
1577     let expr3_0 = C::emit(ctx, &expr2_0);
1578     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1579     return Some(expr4_0);
1580 }
1581 
1582 // Generated as internal constructor for term vec_dup.
1583 pub fn constructor_vec_dup<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
1584     let pattern0_0 = arg0;
1585     let pattern1_0 = arg1;
1586     // Rule at src/isa/aarch64/inst.isle line 1441.
1587     let expr0_0: Type = I8X16;
1588     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1589     let expr2_0 = MInst::VecDup {
1590         rd: expr1_0,
1591         rn: pattern0_0,
1592         size: pattern1_0.clone(),
1593     };
1594     let expr3_0 = C::emit(ctx, &expr2_0);
1595     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1596     return Some(expr4_0);
1597 }
1598 
1599 // Generated as internal constructor for term alu_rr_imm12.
1600 pub fn constructor_alu_rr_imm12<C: Context>(
1601     ctx: &mut C,
1602     arg0: &ALUOp,
1603     arg1: Type,
1604     arg2: Reg,
1605     arg3: Imm12,
1606 ) -> Option<Reg> {
1607     let pattern0_0 = arg0;
1608     let pattern1_0 = arg1;
1609     let pattern2_0 = arg2;
1610     let pattern3_0 = arg3;
1611     // Rule at src/isa/aarch64/inst.isle line 1448.
1612     let expr0_0: Type = I64;
1613     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1614     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1615     let expr3_0 = MInst::AluRRImm12 {
1616         alu_op: pattern0_0.clone(),
1617         size: expr2_0,
1618         rd: expr1_0,
1619         rn: pattern2_0,
1620         imm12: pattern3_0,
1621     };
1622     let expr4_0 = C::emit(ctx, &expr3_0);
1623     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1624     return Some(expr5_0);
1625 }
1626 
1627 // Generated as internal constructor for term alu_rrr_shift.
1628 pub fn constructor_alu_rrr_shift<C: Context>(
1629     ctx: &mut C,
1630     arg0: &ALUOp,
1631     arg1: Type,
1632     arg2: Reg,
1633     arg3: Reg,
1634     arg4: ShiftOpAndAmt,
1635 ) -> Option<Reg> {
1636     let pattern0_0 = arg0;
1637     let pattern1_0 = arg1;
1638     let pattern2_0 = arg2;
1639     let pattern3_0 = arg3;
1640     let pattern4_0 = arg4;
1641     // Rule at src/isa/aarch64/inst.isle line 1455.
1642     let expr0_0: Type = I64;
1643     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1644     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1645     let expr3_0 = MInst::AluRRRShift {
1646         alu_op: pattern0_0.clone(),
1647         size: expr2_0,
1648         rd: expr1_0,
1649         rn: pattern2_0,
1650         rm: pattern3_0,
1651         shiftop: pattern4_0,
1652     };
1653     let expr4_0 = C::emit(ctx, &expr3_0);
1654     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1655     return Some(expr5_0);
1656 }
1657 
1658 // Generated as internal constructor for term alu_rrr_extend.
1659 pub fn constructor_alu_rrr_extend<C: Context>(
1660     ctx: &mut C,
1661     arg0: &ALUOp,
1662     arg1: Type,
1663     arg2: Reg,
1664     arg3: Reg,
1665     arg4: &ExtendOp,
1666 ) -> Option<Reg> {
1667     let pattern0_0 = arg0;
1668     let pattern1_0 = arg1;
1669     let pattern2_0 = arg2;
1670     let pattern3_0 = arg3;
1671     let pattern4_0 = arg4;
1672     // Rule at src/isa/aarch64/inst.isle line 1462.
1673     let expr0_0: Type = I64;
1674     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1675     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1676     let expr3_0 = MInst::AluRRRExtend {
1677         alu_op: pattern0_0.clone(),
1678         size: expr2_0,
1679         rd: expr1_0,
1680         rn: pattern2_0,
1681         rm: pattern3_0,
1682         extendop: pattern4_0.clone(),
1683     };
1684     let expr4_0 = C::emit(ctx, &expr3_0);
1685     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1686     return Some(expr5_0);
1687 }
1688 
1689 // Generated as internal constructor for term alu_rr_extend_reg.
1690 pub fn constructor_alu_rr_extend_reg<C: Context>(
1691     ctx: &mut C,
1692     arg0: &ALUOp,
1693     arg1: Type,
1694     arg2: Reg,
1695     arg3: &ExtendedValue,
1696 ) -> Option<Reg> {
1697     let pattern0_0 = arg0;
1698     let pattern1_0 = arg1;
1699     let pattern2_0 = arg2;
1700     let pattern3_0 = arg3;
1701     // Rule at src/isa/aarch64/inst.isle line 1470.
1702     let expr0_0 = C::put_extended_in_reg(ctx, pattern3_0);
1703     let expr1_0 = C::get_extended_op(ctx, pattern3_0);
1704     let expr2_0 =
1705         constructor_alu_rrr_extend(ctx, pattern0_0, pattern1_0, pattern2_0, expr0_0, &expr1_0)?;
1706     return Some(expr2_0);
1707 }
1708 
1709 // Generated as internal constructor for term alu_rrrr.
1710 pub fn constructor_alu_rrrr<C: Context>(
1711     ctx: &mut C,
1712     arg0: &ALUOp3,
1713     arg1: Type,
1714     arg2: Reg,
1715     arg3: Reg,
1716     arg4: Reg,
1717 ) -> Option<Reg> {
1718     let pattern0_0 = arg0;
1719     let pattern1_0 = arg1;
1720     let pattern2_0 = arg2;
1721     let pattern3_0 = arg3;
1722     let pattern4_0 = arg4;
1723     // Rule at src/isa/aarch64/inst.isle line 1477.
1724     let expr0_0: Type = I64;
1725     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1726     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1727     let expr3_0 = MInst::AluRRRR {
1728         alu_op: pattern0_0.clone(),
1729         size: expr2_0,
1730         rd: expr1_0,
1731         rn: pattern2_0,
1732         rm: pattern3_0,
1733         ra: pattern4_0,
1734     };
1735     let expr4_0 = C::emit(ctx, &expr3_0);
1736     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1737     return Some(expr5_0);
1738 }
1739 
1740 // Generated as internal constructor for term bit_rr.
1741 pub fn constructor_bit_rr<C: Context>(
1742     ctx: &mut C,
1743     arg0: &BitOp,
1744     arg1: Type,
1745     arg2: Reg,
1746 ) -> Option<Reg> {
1747     let pattern0_0 = arg0;
1748     let pattern1_0 = arg1;
1749     let pattern2_0 = arg2;
1750     // Rule at src/isa/aarch64/inst.isle line 1484.
1751     let expr0_0: Type = I64;
1752     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1753     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1754     let expr3_0 = MInst::BitRR {
1755         op: pattern0_0.clone(),
1756         size: expr2_0,
1757         rd: expr1_0,
1758         rn: pattern2_0,
1759     };
1760     let expr4_0 = C::emit(ctx, &expr3_0);
1761     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1762     return Some(expr5_0);
1763 }
1764 
1765 // Generated as internal constructor for term add_with_flags_paired.
1766 pub fn constructor_add_with_flags_paired<C: Context>(
1767     ctx: &mut C,
1768     arg0: Type,
1769     arg1: Reg,
1770     arg2: Reg,
1771 ) -> Option<ProducesFlags> {
1772     let pattern0_0 = arg0;
1773     let pattern1_0 = arg1;
1774     let pattern2_0 = arg2;
1775     // Rule at src/isa/aarch64/inst.isle line 1491.
1776     let expr0_0: Type = I64;
1777     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1778     let expr2_0 = ALUOp::AddS;
1779     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1780     let expr4_0 = MInst::AluRRR {
1781         alu_op: expr2_0,
1782         size: expr3_0,
1783         rd: expr1_0,
1784         rn: pattern1_0,
1785         rm: pattern2_0,
1786     };
1787     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1788     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1789         inst: expr4_0,
1790         result: expr5_0,
1791     };
1792     return Some(expr6_0);
1793 }
1794 
1795 // Generated as internal constructor for term adc_paired.
1796 pub fn constructor_adc_paired<C: Context>(
1797     ctx: &mut C,
1798     arg0: Type,
1799     arg1: Reg,
1800     arg2: Reg,
1801 ) -> Option<ConsumesFlags> {
1802     let pattern0_0 = arg0;
1803     let pattern1_0 = arg1;
1804     let pattern2_0 = arg2;
1805     // Rule at src/isa/aarch64/inst.isle line 1499.
1806     let expr0_0: Type = I64;
1807     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1808     let expr2_0 = ALUOp::Adc;
1809     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1810     let expr4_0 = MInst::AluRRR {
1811         alu_op: expr2_0,
1812         size: expr3_0,
1813         rd: expr1_0,
1814         rn: pattern1_0,
1815         rm: pattern2_0,
1816     };
1817     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1818     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1819         inst: expr4_0,
1820         result: expr5_0,
1821     };
1822     return Some(expr6_0);
1823 }
1824 
1825 // Generated as internal constructor for term sub_with_flags_paired.
1826 pub fn constructor_sub_with_flags_paired<C: Context>(
1827     ctx: &mut C,
1828     arg0: Type,
1829     arg1: Reg,
1830     arg2: Reg,
1831 ) -> Option<ProducesFlags> {
1832     let pattern0_0 = arg0;
1833     let pattern1_0 = arg1;
1834     let pattern2_0 = arg2;
1835     // Rule at src/isa/aarch64/inst.isle line 1507.
1836     let expr0_0: Type = I64;
1837     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1838     let expr2_0 = ALUOp::SubS;
1839     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1840     let expr4_0 = MInst::AluRRR {
1841         alu_op: expr2_0,
1842         size: expr3_0,
1843         rd: expr1_0,
1844         rn: pattern1_0,
1845         rm: pattern2_0,
1846     };
1847     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1848     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1849         inst: expr4_0,
1850         result: expr5_0,
1851     };
1852     return Some(expr6_0);
1853 }
1854 
1855 // Generated as internal constructor for term cmp64_imm.
1856 pub fn constructor_cmp64_imm<C: Context>(
1857     ctx: &mut C,
1858     arg0: Reg,
1859     arg1: Imm12,
1860 ) -> Option<ProducesFlags> {
1861     let pattern0_0 = arg0;
1862     let pattern1_0 = arg1;
1863     // Rule at src/isa/aarch64/inst.isle line 1514.
1864     let expr0_0 = ALUOp::SubS;
1865     let expr1_0 = OperandSize::Size64;
1866     let expr2_0 = C::writable_zero_reg(ctx);
1867     let expr3_0 = MInst::AluRRImm12 {
1868         alu_op: expr0_0,
1869         size: expr1_0,
1870         rd: expr2_0,
1871         rn: pattern0_0,
1872         imm12: pattern1_0,
1873     };
1874     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
1875     return Some(expr4_0);
1876 }
1877 
1878 // Generated as internal constructor for term sbc_paired.
1879 pub fn constructor_sbc_paired<C: Context>(
1880     ctx: &mut C,
1881     arg0: Type,
1882     arg1: Reg,
1883     arg2: Reg,
1884 ) -> Option<ConsumesFlags> {
1885     let pattern0_0 = arg0;
1886     let pattern1_0 = arg1;
1887     let pattern2_0 = arg2;
1888     // Rule at src/isa/aarch64/inst.isle line 1521.
1889     let expr0_0: Type = I64;
1890     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1891     let expr2_0 = ALUOp::Sbc;
1892     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1893     let expr4_0 = MInst::AluRRR {
1894         alu_op: expr2_0,
1895         size: expr3_0,
1896         rd: expr1_0,
1897         rn: pattern1_0,
1898         rm: pattern2_0,
1899     };
1900     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1901     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1902         inst: expr4_0,
1903         result: expr5_0,
1904     };
1905     return Some(expr6_0);
1906 }
1907 
1908 // Generated as internal constructor for term vec_misc.
1909 pub fn constructor_vec_misc<C: Context>(
1910     ctx: &mut C,
1911     arg0: &VecMisc2,
1912     arg1: Reg,
1913     arg2: &VectorSize,
1914 ) -> Option<Reg> {
1915     let pattern0_0 = arg0;
1916     let pattern1_0 = arg1;
1917     let pattern2_0 = arg2;
1918     // Rule at src/isa/aarch64/inst.isle line 1529.
1919     let expr0_0: Type = I8X16;
1920     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1921     let expr2_0 = MInst::VecMisc {
1922         op: pattern0_0.clone(),
1923         rd: expr1_0,
1924         rn: pattern1_0,
1925         size: pattern2_0.clone(),
1926     };
1927     let expr3_0 = C::emit(ctx, &expr2_0);
1928     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1929     return Some(expr4_0);
1930 }
1931 
1932 // Generated as internal constructor for term vec_rrr_long.
1933 pub fn constructor_vec_rrr_long<C: Context>(
1934     ctx: &mut C,
1935     arg0: &VecRRRLongOp,
1936     arg1: Reg,
1937     arg2: Reg,
1938     arg3: bool,
1939 ) -> Option<Reg> {
1940     let pattern0_0 = arg0;
1941     let pattern1_0 = arg1;
1942     let pattern2_0 = arg2;
1943     let pattern3_0 = arg3;
1944     // Rule at src/isa/aarch64/inst.isle line 1536.
1945     let expr0_0: Type = I8X16;
1946     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1947     let expr2_0 = MInst::VecRRRLong {
1948         alu_op: pattern0_0.clone(),
1949         rd: expr1_0,
1950         rn: pattern1_0,
1951         rm: pattern2_0,
1952         high_half: pattern3_0,
1953     };
1954     let expr3_0 = C::emit(ctx, &expr2_0);
1955     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1956     return Some(expr4_0);
1957 }
1958 
1959 // Generated as internal constructor for term vec_rrrr_long.
1960 pub fn constructor_vec_rrrr_long<C: Context>(
1961     ctx: &mut C,
1962     arg0: &VecRRRLongOp,
1963     arg1: Reg,
1964     arg2: Reg,
1965     arg3: Reg,
1966     arg4: bool,
1967 ) -> Option<Reg> {
1968     let pattern0_0 = arg0;
1969     let pattern1_0 = arg1;
1970     let pattern2_0 = arg2;
1971     let pattern3_0 = arg3;
1972     let pattern4_0 = arg4;
1973     // Rule at src/isa/aarch64/inst.isle line 1546.
1974     let expr0_0: Type = I8X16;
1975     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1976     let expr2_0 = MInst::FpuMove128 {
1977         rd: expr1_0,
1978         rn: pattern1_0,
1979     };
1980     let expr3_0 = C::emit(ctx, &expr2_0);
1981     let expr4_0 = MInst::VecRRRLong {
1982         alu_op: pattern0_0.clone(),
1983         rd: expr1_0,
1984         rn: pattern2_0,
1985         rm: pattern3_0,
1986         high_half: pattern4_0,
1987     };
1988     let expr5_0 = C::emit(ctx, &expr4_0);
1989     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1990     return Some(expr6_0);
1991 }
1992 
1993 // Generated as internal constructor for term vec_rr_narrow.
1994 pub fn constructor_vec_rr_narrow<C: Context>(
1995     ctx: &mut C,
1996     arg0: &VecRRNarrowOp,
1997     arg1: Reg,
1998     arg2: bool,
1999 ) -> Option<Reg> {
2000     let pattern0_0 = arg0;
2001     let pattern1_0 = arg1;
2002     let pattern2_0 = arg2;
2003     // Rule at src/isa/aarch64/inst.isle line 1554.
2004     let expr0_0: Type = I8X16;
2005     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2006     let expr2_0 = MInst::VecRRNarrow {
2007         op: pattern0_0.clone(),
2008         rd: expr1_0,
2009         rn: pattern1_0,
2010         high_half: pattern2_0,
2011     };
2012     let expr3_0 = C::emit(ctx, &expr2_0);
2013     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2014     return Some(expr4_0);
2015 }
2016 
2017 // Generated as internal constructor for term vec_rr_long.
2018 pub fn constructor_vec_rr_long<C: Context>(
2019     ctx: &mut C,
2020     arg0: &VecRRLongOp,
2021     arg1: Reg,
2022     arg2: bool,
2023 ) -> Option<Reg> {
2024     let pattern0_0 = arg0;
2025     let pattern1_0 = arg1;
2026     let pattern2_0 = arg2;
2027     // Rule at src/isa/aarch64/inst.isle line 1561.
2028     let expr0_0: Type = I8X16;
2029     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2030     let expr2_0 = MInst::VecRRLong {
2031         op: pattern0_0.clone(),
2032         rd: expr1_0,
2033         rn: pattern1_0,
2034         high_half: pattern2_0,
2035     };
2036     let expr3_0 = C::emit(ctx, &expr2_0);
2037     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2038     return Some(expr4_0);
2039 }
2040 
2041 // Generated as internal constructor for term mov_to_fpu.
2042 pub fn constructor_mov_to_fpu<C: Context>(
2043     ctx: &mut C,
2044     arg0: Reg,
2045     arg1: &ScalarSize,
2046 ) -> Option<Reg> {
2047     let pattern0_0 = arg0;
2048     let pattern1_0 = arg1;
2049     // Rule at src/isa/aarch64/inst.isle line 1568.
2050     let expr0_0: Type = I8X16;
2051     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2052     let expr2_0 = MInst::MovToFpu {
2053         rd: expr1_0,
2054         rn: pattern0_0,
2055         size: pattern1_0.clone(),
2056     };
2057     let expr3_0 = C::emit(ctx, &expr2_0);
2058     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2059     return Some(expr4_0);
2060 }
2061 
2062 // Generated as internal constructor for term mov_to_vec.
2063 pub fn constructor_mov_to_vec<C: Context>(
2064     ctx: &mut C,
2065     arg0: Reg,
2066     arg1: Reg,
2067     arg2: u8,
2068     arg3: &VectorSize,
2069 ) -> Option<Reg> {
2070     let pattern0_0 = arg0;
2071     let pattern1_0 = arg1;
2072     let pattern2_0 = arg2;
2073     let pattern3_0 = arg3;
2074     // Rule at src/isa/aarch64/inst.isle line 1575.
2075     let expr0_0: Type = I8X16;
2076     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2077     let expr2_0 = MInst::FpuMove128 {
2078         rd: expr1_0,
2079         rn: pattern0_0,
2080     };
2081     let expr3_0 = C::emit(ctx, &expr2_0);
2082     let expr4_0 = MInst::MovToVec {
2083         rd: expr1_0,
2084         rn: pattern1_0,
2085         idx: pattern2_0,
2086         size: pattern3_0.clone(),
2087     };
2088     let expr5_0 = C::emit(ctx, &expr4_0);
2089     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
2090     return Some(expr6_0);
2091 }
2092 
2093 // Generated as internal constructor for term mov_from_vec.
2094 pub fn constructor_mov_from_vec<C: Context>(
2095     ctx: &mut C,
2096     arg0: Reg,
2097     arg1: u8,
2098     arg2: &VectorSize,
2099 ) -> Option<Reg> {
2100     let pattern0_0 = arg0;
2101     let pattern1_0 = arg1;
2102     let pattern2_0 = arg2;
2103     // Rule at src/isa/aarch64/inst.isle line 1583.
2104     let expr0_0: Type = I64;
2105     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2106     let expr2_0 = MInst::MovFromVec {
2107         rd: expr1_0,
2108         rn: pattern0_0,
2109         idx: pattern1_0,
2110         size: pattern2_0.clone(),
2111     };
2112     let expr3_0 = C::emit(ctx, &expr2_0);
2113     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2114     return Some(expr4_0);
2115 }
2116 
2117 // Generated as internal constructor for term mov_from_vec_signed.
2118 pub fn constructor_mov_from_vec_signed<C: Context>(
2119     ctx: &mut C,
2120     arg0: Reg,
2121     arg1: u8,
2122     arg2: &VectorSize,
2123     arg3: &OperandSize,
2124 ) -> Option<Reg> {
2125     let pattern0_0 = arg0;
2126     let pattern1_0 = arg1;
2127     let pattern2_0 = arg2;
2128     let pattern3_0 = arg3;
2129     // Rule at src/isa/aarch64/inst.isle line 1590.
2130     let expr0_0: Type = I64;
2131     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2132     let expr2_0 = MInst::MovFromVecSigned {
2133         rd: expr1_0,
2134         rn: pattern0_0,
2135         idx: pattern1_0,
2136         size: pattern2_0.clone(),
2137         scalar_size: pattern3_0.clone(),
2138     };
2139     let expr3_0 = C::emit(ctx, &expr2_0);
2140     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2141     return Some(expr4_0);
2142 }
2143 
2144 // Generated as internal constructor for term extend.
2145 pub fn constructor_extend<C: Context>(
2146     ctx: &mut C,
2147     arg0: Reg,
2148     arg1: bool,
2149     arg2: u8,
2150     arg3: u8,
2151 ) -> Option<Reg> {
2152     let pattern0_0 = arg0;
2153     let pattern1_0 = arg1;
2154     let pattern2_0 = arg2;
2155     let pattern3_0 = arg3;
2156     // Rule at src/isa/aarch64/inst.isle line 1597.
2157     let expr0_0: Type = I64;
2158     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2159     let expr2_0 = MInst::Extend {
2160         rd: expr1_0,
2161         rn: pattern0_0,
2162         signed: pattern1_0,
2163         from_bits: pattern2_0,
2164         to_bits: pattern3_0,
2165     };
2166     let expr3_0 = C::emit(ctx, &expr2_0);
2167     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2168     return Some(expr4_0);
2169 }
2170 
2171 // Generated as internal constructor for term load_acquire.
2172 pub fn constructor_load_acquire<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2173     let pattern0_0 = arg0;
2174     let pattern1_0 = arg1;
2175     // Rule at src/isa/aarch64/inst.isle line 1604.
2176     let expr0_0: Type = I64;
2177     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2178     let expr2_0 = MInst::LoadAcquire {
2179         access_ty: pattern0_0,
2180         rt: expr1_0,
2181         rn: pattern1_0,
2182     };
2183     let expr3_0 = C::emit(ctx, &expr2_0);
2184     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2185     return Some(expr4_0);
2186 }
2187 
2188 // Generated as internal constructor for term tst_imm.
2189 pub fn constructor_tst_imm<C: Context>(
2190     ctx: &mut C,
2191     arg0: Type,
2192     arg1: Reg,
2193     arg2: ImmLogic,
2194 ) -> Option<ProducesFlags> {
2195     let pattern0_0 = arg0;
2196     let pattern1_0 = arg1;
2197     let pattern2_0 = arg2;
2198     // Rule at src/isa/aarch64/inst.isle line 1614.
2199     let expr0_0 = ALUOp::AndS;
2200     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
2201     let expr2_0 = C::writable_zero_reg(ctx);
2202     let expr3_0 = MInst::AluRRImmLogic {
2203         alu_op: expr0_0,
2204         size: expr1_0,
2205         rd: expr2_0,
2206         rn: pattern1_0,
2207         imml: pattern2_0,
2208     };
2209     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
2210     return Some(expr4_0);
2211 }
2212 
2213 // Generated as internal constructor for term csel.
2214 pub fn constructor_csel<C: Context>(
2215     ctx: &mut C,
2216     arg0: &Cond,
2217     arg1: Reg,
2218     arg2: Reg,
2219 ) -> Option<ConsumesFlags> {
2220     let pattern0_0 = arg0;
2221     let pattern1_0 = arg1;
2222     let pattern2_0 = arg2;
2223     // Rule at src/isa/aarch64/inst.isle line 1628.
2224     let expr0_0: Type = I64;
2225     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2226     let expr2_0 = MInst::CSel {
2227         rd: expr1_0,
2228         cond: pattern0_0.clone(),
2229         rn: pattern1_0,
2230         rm: pattern2_0,
2231     };
2232     let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
2233     let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
2234         inst: expr2_0,
2235         result: expr3_0,
2236     };
2237     return Some(expr4_0);
2238 }
2239 
2240 // Generated as internal constructor for term add.
2241 pub fn constructor_add<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2242     let pattern0_0 = arg0;
2243     let pattern1_0 = arg1;
2244     let pattern2_0 = arg2;
2245     // Rule at src/isa/aarch64/inst.isle line 1637.
2246     let expr0_0 = ALUOp::Add;
2247     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2248     return Some(expr1_0);
2249 }
2250 
2251 // Generated as internal constructor for term add_imm.
2252 pub fn constructor_add_imm<C: Context>(
2253     ctx: &mut C,
2254     arg0: Type,
2255     arg1: Reg,
2256     arg2: Imm12,
2257 ) -> Option<Reg> {
2258     let pattern0_0 = arg0;
2259     let pattern1_0 = arg1;
2260     let pattern2_0 = arg2;
2261     // Rule at src/isa/aarch64/inst.isle line 1640.
2262     let expr0_0 = ALUOp::Add;
2263     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2264     return Some(expr1_0);
2265 }
2266 
2267 // Generated as internal constructor for term add_extend.
2268 pub fn constructor_add_extend<C: Context>(
2269     ctx: &mut C,
2270     arg0: Type,
2271     arg1: Reg,
2272     arg2: &ExtendedValue,
2273 ) -> Option<Reg> {
2274     let pattern0_0 = arg0;
2275     let pattern1_0 = arg1;
2276     let pattern2_0 = arg2;
2277     // Rule at src/isa/aarch64/inst.isle line 1643.
2278     let expr0_0 = ALUOp::Add;
2279     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2280     return Some(expr1_0);
2281 }
2282 
2283 // Generated as internal constructor for term add_shift.
2284 pub fn constructor_add_shift<C: Context>(
2285     ctx: &mut C,
2286     arg0: Type,
2287     arg1: Reg,
2288     arg2: Reg,
2289     arg3: ShiftOpAndAmt,
2290 ) -> Option<Reg> {
2291     let pattern0_0 = arg0;
2292     let pattern1_0 = arg1;
2293     let pattern2_0 = arg2;
2294     let pattern3_0 = arg3;
2295     // Rule at src/isa/aarch64/inst.isle line 1646.
2296     let expr0_0 = ALUOp::Add;
2297     let expr1_0 = constructor_alu_rrr_shift(
2298         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2299     )?;
2300     return Some(expr1_0);
2301 }
2302 
2303 // Generated as internal constructor for term add_vec.
2304 pub fn constructor_add_vec<C: Context>(
2305     ctx: &mut C,
2306     arg0: Reg,
2307     arg1: Reg,
2308     arg2: &VectorSize,
2309 ) -> Option<Reg> {
2310     let pattern0_0 = arg0;
2311     let pattern1_0 = arg1;
2312     let pattern2_0 = arg2;
2313     // Rule at src/isa/aarch64/inst.isle line 1649.
2314     let expr0_0 = VecALUOp::Add;
2315     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2316     return Some(expr1_0);
2317 }
2318 
2319 // Generated as internal constructor for term sub.
2320 pub fn constructor_sub<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2321     let pattern0_0 = arg0;
2322     let pattern1_0 = arg1;
2323     let pattern2_0 = arg2;
2324     // Rule at src/isa/aarch64/inst.isle line 1654.
2325     let expr0_0 = ALUOp::Sub;
2326     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2327     return Some(expr1_0);
2328 }
2329 
2330 // Generated as internal constructor for term sub_imm.
2331 pub fn constructor_sub_imm<C: Context>(
2332     ctx: &mut C,
2333     arg0: Type,
2334     arg1: Reg,
2335     arg2: Imm12,
2336 ) -> Option<Reg> {
2337     let pattern0_0 = arg0;
2338     let pattern1_0 = arg1;
2339     let pattern2_0 = arg2;
2340     // Rule at src/isa/aarch64/inst.isle line 1657.
2341     let expr0_0 = ALUOp::Sub;
2342     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2343     return Some(expr1_0);
2344 }
2345 
2346 // Generated as internal constructor for term sub_extend.
2347 pub fn constructor_sub_extend<C: Context>(
2348     ctx: &mut C,
2349     arg0: Type,
2350     arg1: Reg,
2351     arg2: &ExtendedValue,
2352 ) -> Option<Reg> {
2353     let pattern0_0 = arg0;
2354     let pattern1_0 = arg1;
2355     let pattern2_0 = arg2;
2356     // Rule at src/isa/aarch64/inst.isle line 1660.
2357     let expr0_0 = ALUOp::Sub;
2358     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2359     return Some(expr1_0);
2360 }
2361 
2362 // Generated as internal constructor for term sub_shift.
2363 pub fn constructor_sub_shift<C: Context>(
2364     ctx: &mut C,
2365     arg0: Type,
2366     arg1: Reg,
2367     arg2: Reg,
2368     arg3: ShiftOpAndAmt,
2369 ) -> Option<Reg> {
2370     let pattern0_0 = arg0;
2371     let pattern1_0 = arg1;
2372     let pattern2_0 = arg2;
2373     let pattern3_0 = arg3;
2374     // Rule at src/isa/aarch64/inst.isle line 1663.
2375     let expr0_0 = ALUOp::Sub;
2376     let expr1_0 = constructor_alu_rrr_shift(
2377         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2378     )?;
2379     return Some(expr1_0);
2380 }
2381 
2382 // Generated as internal constructor for term sub_vec.
2383 pub fn constructor_sub_vec<C: Context>(
2384     ctx: &mut C,
2385     arg0: Reg,
2386     arg1: Reg,
2387     arg2: &VectorSize,
2388 ) -> Option<Reg> {
2389     let pattern0_0 = arg0;
2390     let pattern1_0 = arg1;
2391     let pattern2_0 = arg2;
2392     // Rule at src/isa/aarch64/inst.isle line 1666.
2393     let expr0_0 = VecALUOp::Sub;
2394     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2395     return Some(expr1_0);
2396 }
2397 
2398 // Generated as internal constructor for term madd.
2399 pub fn constructor_madd<C: Context>(
2400     ctx: &mut C,
2401     arg0: Type,
2402     arg1: Reg,
2403     arg2: Reg,
2404     arg3: Reg,
2405 ) -> Option<Reg> {
2406     let pattern0_0 = arg0;
2407     let pattern1_0 = arg1;
2408     let pattern2_0 = arg2;
2409     let pattern3_0 = arg3;
2410     // Rule at src/isa/aarch64/inst.isle line 1671.
2411     let expr0_0 = ALUOp3::MAdd;
2412     let expr1_0 = constructor_alu_rrrr(
2413         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2414     )?;
2415     return Some(expr1_0);
2416 }
2417 
2418 // Generated as internal constructor for term msub.
2419 pub fn constructor_msub<C: Context>(
2420     ctx: &mut C,
2421     arg0: Type,
2422     arg1: Reg,
2423     arg2: Reg,
2424     arg3: Reg,
2425 ) -> Option<Reg> {
2426     let pattern0_0 = arg0;
2427     let pattern1_0 = arg1;
2428     let pattern2_0 = arg2;
2429     let pattern3_0 = arg3;
2430     // Rule at src/isa/aarch64/inst.isle line 1676.
2431     let expr0_0 = ALUOp3::MSub;
2432     let expr1_0 = constructor_alu_rrrr(
2433         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2434     )?;
2435     return Some(expr1_0);
2436 }
2437 
2438 // Generated as internal constructor for term uqadd.
2439 pub fn constructor_uqadd<C: Context>(
2440     ctx: &mut C,
2441     arg0: Reg,
2442     arg1: Reg,
2443     arg2: &VectorSize,
2444 ) -> Option<Reg> {
2445     let pattern0_0 = arg0;
2446     let pattern1_0 = arg1;
2447     let pattern2_0 = arg2;
2448     // Rule at src/isa/aarch64/inst.isle line 1680.
2449     let expr0_0 = VecALUOp::Uqadd;
2450     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2451     return Some(expr1_0);
2452 }
2453 
2454 // Generated as internal constructor for term sqadd.
2455 pub fn constructor_sqadd<C: Context>(
2456     ctx: &mut C,
2457     arg0: Reg,
2458     arg1: Reg,
2459     arg2: &VectorSize,
2460 ) -> Option<Reg> {
2461     let pattern0_0 = arg0;
2462     let pattern1_0 = arg1;
2463     let pattern2_0 = arg2;
2464     // Rule at src/isa/aarch64/inst.isle line 1684.
2465     let expr0_0 = VecALUOp::Sqadd;
2466     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2467     return Some(expr1_0);
2468 }
2469 
2470 // Generated as internal constructor for term uqsub.
2471 pub fn constructor_uqsub<C: Context>(
2472     ctx: &mut C,
2473     arg0: Reg,
2474     arg1: Reg,
2475     arg2: &VectorSize,
2476 ) -> Option<Reg> {
2477     let pattern0_0 = arg0;
2478     let pattern1_0 = arg1;
2479     let pattern2_0 = arg2;
2480     // Rule at src/isa/aarch64/inst.isle line 1688.
2481     let expr0_0 = VecALUOp::Uqsub;
2482     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2483     return Some(expr1_0);
2484 }
2485 
2486 // Generated as internal constructor for term sqsub.
2487 pub fn constructor_sqsub<C: Context>(
2488     ctx: &mut C,
2489     arg0: Reg,
2490     arg1: Reg,
2491     arg2: &VectorSize,
2492 ) -> Option<Reg> {
2493     let pattern0_0 = arg0;
2494     let pattern1_0 = arg1;
2495     let pattern2_0 = arg2;
2496     // Rule at src/isa/aarch64/inst.isle line 1692.
2497     let expr0_0 = VecALUOp::Sqsub;
2498     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2499     return Some(expr1_0);
2500 }
2501 
2502 // Generated as internal constructor for term umulh.
2503 pub fn constructor_umulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2504     let pattern0_0 = arg0;
2505     let pattern1_0 = arg1;
2506     let pattern2_0 = arg2;
2507     // Rule at src/isa/aarch64/inst.isle line 1696.
2508     let expr0_0 = ALUOp::UMulH;
2509     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2510     return Some(expr1_0);
2511 }
2512 
2513 // Generated as internal constructor for term smulh.
2514 pub fn constructor_smulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2515     let pattern0_0 = arg0;
2516     let pattern1_0 = arg1;
2517     let pattern2_0 = arg2;
2518     // Rule at src/isa/aarch64/inst.isle line 1700.
2519     let expr0_0 = ALUOp::SMulH;
2520     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2521     return Some(expr1_0);
2522 }
2523 
2524 // Generated as internal constructor for term mul.
2525 pub fn constructor_mul<C: Context>(
2526     ctx: &mut C,
2527     arg0: Reg,
2528     arg1: Reg,
2529     arg2: &VectorSize,
2530 ) -> Option<Reg> {
2531     let pattern0_0 = arg0;
2532     let pattern1_0 = arg1;
2533     let pattern2_0 = arg2;
2534     // Rule at src/isa/aarch64/inst.isle line 1704.
2535     let expr0_0 = VecALUOp::Mul;
2536     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2537     return Some(expr1_0);
2538 }
2539 
2540 // Generated as internal constructor for term neg.
2541 pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2542     let pattern0_0 = arg0;
2543     let pattern1_0 = arg1;
2544     // Rule at src/isa/aarch64/inst.isle line 1708.
2545     let expr0_0 = VecMisc2::Neg;
2546     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2547     return Some(expr1_0);
2548 }
2549 
2550 // Generated as internal constructor for term rev64.
2551 pub fn constructor_rev64<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2552     let pattern0_0 = arg0;
2553     let pattern1_0 = arg1;
2554     // Rule at src/isa/aarch64/inst.isle line 1712.
2555     let expr0_0 = VecMisc2::Rev64;
2556     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2557     return Some(expr1_0);
2558 }
2559 
2560 // Generated as internal constructor for term xtn64.
2561 pub fn constructor_xtn64<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2562     let pattern0_0 = arg0;
2563     let pattern1_0 = arg1;
2564     // Rule at src/isa/aarch64/inst.isle line 1716.
2565     let expr0_0 = VecRRNarrowOp::Xtn64;
2566     let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2567     return Some(expr1_0);
2568 }
2569 
2570 // Generated as internal constructor for term addp.
2571 pub fn constructor_addp<C: Context>(
2572     ctx: &mut C,
2573     arg0: Reg,
2574     arg1: Reg,
2575     arg2: &VectorSize,
2576 ) -> Option<Reg> {
2577     let pattern0_0 = arg0;
2578     let pattern1_0 = arg1;
2579     let pattern2_0 = arg2;
2580     // Rule at src/isa/aarch64/inst.isle line 1720.
2581     let expr0_0 = VecALUOp::Addp;
2582     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2583     return Some(expr1_0);
2584 }
2585 
2586 // Generated as internal constructor for term addv.
2587 pub fn constructor_addv<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2588     let pattern0_0 = arg0;
2589     let pattern1_0 = arg1;
2590     // Rule at src/isa/aarch64/inst.isle line 1724.
2591     let expr0_0 = VecLanesOp::Addv;
2592     let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2593     return Some(expr1_0);
2594 }
2595 
2596 // Generated as internal constructor for term shll32.
2597 pub fn constructor_shll32<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2598     let pattern0_0 = arg0;
2599     let pattern1_0 = arg1;
2600     // Rule at src/isa/aarch64/inst.isle line 1728.
2601     let expr0_0 = VecRRLongOp::Shll32;
2602     let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2603     return Some(expr1_0);
2604 }
2605 
2606 // Generated as internal constructor for term umlal32.
2607 pub fn constructor_umlal32<C: Context>(
2608     ctx: &mut C,
2609     arg0: Reg,
2610     arg1: Reg,
2611     arg2: Reg,
2612     arg3: bool,
2613 ) -> Option<Reg> {
2614     let pattern0_0 = arg0;
2615     let pattern1_0 = arg1;
2616     let pattern2_0 = arg2;
2617     let pattern3_0 = arg3;
2618     // Rule at src/isa/aarch64/inst.isle line 1732.
2619     let expr0_0 = VecRRRLongOp::Umlal32;
2620     let expr1_0 = constructor_vec_rrrr_long(
2621         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2622     )?;
2623     return Some(expr1_0);
2624 }
2625 
2626 // Generated as internal constructor for term smull8.
2627 pub fn constructor_smull8<C: Context>(
2628     ctx: &mut C,
2629     arg0: Reg,
2630     arg1: Reg,
2631     arg2: bool,
2632 ) -> Option<Reg> {
2633     let pattern0_0 = arg0;
2634     let pattern1_0 = arg1;
2635     let pattern2_0 = arg2;
2636     // Rule at src/isa/aarch64/inst.isle line 1736.
2637     let expr0_0 = VecRRRLongOp::Smull8;
2638     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2639     return Some(expr1_0);
2640 }
2641 
2642 // Generated as internal constructor for term umull8.
2643 pub fn constructor_umull8<C: Context>(
2644     ctx: &mut C,
2645     arg0: Reg,
2646     arg1: Reg,
2647     arg2: bool,
2648 ) -> Option<Reg> {
2649     let pattern0_0 = arg0;
2650     let pattern1_0 = arg1;
2651     let pattern2_0 = arg2;
2652     // Rule at src/isa/aarch64/inst.isle line 1740.
2653     let expr0_0 = VecRRRLongOp::Umull8;
2654     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2655     return Some(expr1_0);
2656 }
2657 
2658 // Generated as internal constructor for term smull16.
2659 pub fn constructor_smull16<C: Context>(
2660     ctx: &mut C,
2661     arg0: Reg,
2662     arg1: Reg,
2663     arg2: bool,
2664 ) -> Option<Reg> {
2665     let pattern0_0 = arg0;
2666     let pattern1_0 = arg1;
2667     let pattern2_0 = arg2;
2668     // Rule at src/isa/aarch64/inst.isle line 1744.
2669     let expr0_0 = VecRRRLongOp::Smull16;
2670     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2671     return Some(expr1_0);
2672 }
2673 
2674 // Generated as internal constructor for term umull16.
2675 pub fn constructor_umull16<C: Context>(
2676     ctx: &mut C,
2677     arg0: Reg,
2678     arg1: Reg,
2679     arg2: bool,
2680 ) -> Option<Reg> {
2681     let pattern0_0 = arg0;
2682     let pattern1_0 = arg1;
2683     let pattern2_0 = arg2;
2684     // Rule at src/isa/aarch64/inst.isle line 1748.
2685     let expr0_0 = VecRRRLongOp::Umull16;
2686     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2687     return Some(expr1_0);
2688 }
2689 
2690 // Generated as internal constructor for term smull32.
2691 pub fn constructor_smull32<C: Context>(
2692     ctx: &mut C,
2693     arg0: Reg,
2694     arg1: Reg,
2695     arg2: bool,
2696 ) -> Option<Reg> {
2697     let pattern0_0 = arg0;
2698     let pattern1_0 = arg1;
2699     let pattern2_0 = arg2;
2700     // Rule at src/isa/aarch64/inst.isle line 1752.
2701     let expr0_0 = VecRRRLongOp::Smull32;
2702     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2703     return Some(expr1_0);
2704 }
2705 
2706 // Generated as internal constructor for term umull32.
2707 pub fn constructor_umull32<C: Context>(
2708     ctx: &mut C,
2709     arg0: Reg,
2710     arg1: Reg,
2711     arg2: bool,
2712 ) -> Option<Reg> {
2713     let pattern0_0 = arg0;
2714     let pattern1_0 = arg1;
2715     let pattern2_0 = arg2;
2716     // Rule at src/isa/aarch64/inst.isle line 1756.
2717     let expr0_0 = VecRRRLongOp::Umull32;
2718     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2719     return Some(expr1_0);
2720 }
2721 
2722 // Generated as internal constructor for term asr.
2723 pub fn constructor_asr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2724     let pattern0_0 = arg0;
2725     let pattern1_0 = arg1;
2726     let pattern2_0 = arg2;
2727     // Rule at src/isa/aarch64/inst.isle line 1760.
2728     let expr0_0 = ALUOp::Asr;
2729     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2730     return Some(expr1_0);
2731 }
2732 
2733 // Generated as internal constructor for term asr_imm.
2734 pub fn constructor_asr_imm<C: Context>(
2735     ctx: &mut C,
2736     arg0: Type,
2737     arg1: Reg,
2738     arg2: ImmShift,
2739 ) -> Option<Reg> {
2740     let pattern0_0 = arg0;
2741     let pattern1_0 = arg1;
2742     let pattern2_0 = arg2;
2743     // Rule at src/isa/aarch64/inst.isle line 1763.
2744     let expr0_0 = ALUOp::Asr;
2745     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2746     return Some(expr1_0);
2747 }
2748 
2749 // Generated as internal constructor for term lsr.
2750 pub fn constructor_lsr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2751     let pattern0_0 = arg0;
2752     let pattern1_0 = arg1;
2753     let pattern2_0 = arg2;
2754     // Rule at src/isa/aarch64/inst.isle line 1767.
2755     let expr0_0 = ALUOp::Lsr;
2756     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2757     return Some(expr1_0);
2758 }
2759 
2760 // Generated as internal constructor for term lsr_imm.
2761 pub fn constructor_lsr_imm<C: Context>(
2762     ctx: &mut C,
2763     arg0: Type,
2764     arg1: Reg,
2765     arg2: ImmShift,
2766 ) -> Option<Reg> {
2767     let pattern0_0 = arg0;
2768     let pattern1_0 = arg1;
2769     let pattern2_0 = arg2;
2770     // Rule at src/isa/aarch64/inst.isle line 1770.
2771     let expr0_0 = ALUOp::Lsr;
2772     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2773     return Some(expr1_0);
2774 }
2775 
2776 // Generated as internal constructor for term lsl.
2777 pub fn constructor_lsl<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2778     let pattern0_0 = arg0;
2779     let pattern1_0 = arg1;
2780     let pattern2_0 = arg2;
2781     // Rule at src/isa/aarch64/inst.isle line 1774.
2782     let expr0_0 = ALUOp::Lsl;
2783     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2784     return Some(expr1_0);
2785 }
2786 
2787 // Generated as internal constructor for term lsl_imm.
2788 pub fn constructor_lsl_imm<C: Context>(
2789     ctx: &mut C,
2790     arg0: Type,
2791     arg1: Reg,
2792     arg2: ImmShift,
2793 ) -> Option<Reg> {
2794     let pattern0_0 = arg0;
2795     let pattern1_0 = arg1;
2796     let pattern2_0 = arg2;
2797     // Rule at src/isa/aarch64/inst.isle line 1777.
2798     let expr0_0 = ALUOp::Lsl;
2799     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2800     return Some(expr1_0);
2801 }
2802 
2803 // Generated as internal constructor for term a64_udiv.
2804 pub fn constructor_a64_udiv<C: Context>(
2805     ctx: &mut C,
2806     arg0: Type,
2807     arg1: Reg,
2808     arg2: Reg,
2809 ) -> Option<Reg> {
2810     let pattern0_0 = arg0;
2811     let pattern1_0 = arg1;
2812     let pattern2_0 = arg2;
2813     // Rule at src/isa/aarch64/inst.isle line 1781.
2814     let expr0_0 = ALUOp::UDiv;
2815     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2816     return Some(expr1_0);
2817 }
2818 
2819 // Generated as internal constructor for term a64_sdiv.
2820 pub fn constructor_a64_sdiv<C: Context>(
2821     ctx: &mut C,
2822     arg0: Type,
2823     arg1: Reg,
2824     arg2: Reg,
2825 ) -> Option<Reg> {
2826     let pattern0_0 = arg0;
2827     let pattern1_0 = arg1;
2828     let pattern2_0 = arg2;
2829     // Rule at src/isa/aarch64/inst.isle line 1785.
2830     let expr0_0 = ALUOp::SDiv;
2831     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2832     return Some(expr1_0);
2833 }
2834 
2835 // Generated as internal constructor for term not.
2836 pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2837     let pattern0_0 = arg0;
2838     let pattern1_0 = arg1;
2839     // Rule at src/isa/aarch64/inst.isle line 1789.
2840     let expr0_0 = VecMisc2::Not;
2841     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2842     return Some(expr1_0);
2843 }
2844 
2845 // Generated as internal constructor for term orr_not.
2846 pub fn constructor_orr_not<C: Context>(
2847     ctx: &mut C,
2848     arg0: Type,
2849     arg1: Reg,
2850     arg2: Reg,
2851 ) -> Option<Reg> {
2852     let pattern0_0 = arg0;
2853     let pattern1_0 = arg1;
2854     let pattern2_0 = arg2;
2855     // Rule at src/isa/aarch64/inst.isle line 1794.
2856     let expr0_0 = ALUOp::OrrNot;
2857     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2858     return Some(expr1_0);
2859 }
2860 
2861 // Generated as internal constructor for term orr_not_shift.
2862 pub fn constructor_orr_not_shift<C: Context>(
2863     ctx: &mut C,
2864     arg0: Type,
2865     arg1: Reg,
2866     arg2: Reg,
2867     arg3: ShiftOpAndAmt,
2868 ) -> Option<Reg> {
2869     let pattern0_0 = arg0;
2870     let pattern1_0 = arg1;
2871     let pattern2_0 = arg2;
2872     let pattern3_0 = arg3;
2873     // Rule at src/isa/aarch64/inst.isle line 1797.
2874     let expr0_0 = ALUOp::OrrNot;
2875     let expr1_0 = constructor_alu_rrr_shift(
2876         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2877     )?;
2878     return Some(expr1_0);
2879 }
2880 
2881 // Generated as internal constructor for term orr.
2882 pub fn constructor_orr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2883     let pattern0_0 = arg0;
2884     let pattern1_0 = arg1;
2885     let pattern2_0 = arg2;
2886     // Rule at src/isa/aarch64/inst.isle line 1802.
2887     let expr0_0 = ALUOp::Orr;
2888     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2889     return Some(expr1_0);
2890 }
2891 
2892 // Generated as internal constructor for term orr_imm.
2893 pub fn constructor_orr_imm<C: Context>(
2894     ctx: &mut C,
2895     arg0: Type,
2896     arg1: Reg,
2897     arg2: ImmLogic,
2898 ) -> Option<Reg> {
2899     let pattern0_0 = arg0;
2900     let pattern1_0 = arg1;
2901     let pattern2_0 = arg2;
2902     // Rule at src/isa/aarch64/inst.isle line 1805.
2903     let expr0_0 = ALUOp::Orr;
2904     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2905     return Some(expr1_0);
2906 }
2907 
2908 // Generated as internal constructor for term orr_vec.
2909 pub fn constructor_orr_vec<C: Context>(
2910     ctx: &mut C,
2911     arg0: Reg,
2912     arg1: Reg,
2913     arg2: &VectorSize,
2914 ) -> Option<Reg> {
2915     let pattern0_0 = arg0;
2916     let pattern1_0 = arg1;
2917     let pattern2_0 = arg2;
2918     // Rule at src/isa/aarch64/inst.isle line 1808.
2919     let expr0_0 = VecALUOp::Orr;
2920     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2921     return Some(expr1_0);
2922 }
2923 
2924 // Generated as internal constructor for term and_imm.
2925 pub fn constructor_and_imm<C: Context>(
2926     ctx: &mut C,
2927     arg0: Type,
2928     arg1: Reg,
2929     arg2: ImmLogic,
2930 ) -> Option<Reg> {
2931     let pattern0_0 = arg0;
2932     let pattern1_0 = arg1;
2933     let pattern2_0 = arg2;
2934     // Rule at src/isa/aarch64/inst.isle line 1813.
2935     let expr0_0 = ALUOp::And;
2936     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2937     return Some(expr1_0);
2938 }
2939 
2940 // Generated as internal constructor for term and_vec.
2941 pub fn constructor_and_vec<C: Context>(
2942     ctx: &mut C,
2943     arg0: Reg,
2944     arg1: Reg,
2945     arg2: &VectorSize,
2946 ) -> Option<Reg> {
2947     let pattern0_0 = arg0;
2948     let pattern1_0 = arg1;
2949     let pattern2_0 = arg2;
2950     // Rule at src/isa/aarch64/inst.isle line 1816.
2951     let expr0_0 = VecALUOp::And;
2952     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2953     return Some(expr1_0);
2954 }
2955 
2956 // Generated as internal constructor for term eor_vec.
2957 pub fn constructor_eor_vec<C: Context>(
2958     ctx: &mut C,
2959     arg0: Reg,
2960     arg1: Reg,
2961     arg2: &VectorSize,
2962 ) -> Option<Reg> {
2963     let pattern0_0 = arg0;
2964     let pattern1_0 = arg1;
2965     let pattern2_0 = arg2;
2966     // Rule at src/isa/aarch64/inst.isle line 1820.
2967     let expr0_0 = VecALUOp::Eor;
2968     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2969     return Some(expr1_0);
2970 }
2971 
2972 // Generated as internal constructor for term bic_vec.
2973 pub fn constructor_bic_vec<C: Context>(
2974     ctx: &mut C,
2975     arg0: Reg,
2976     arg1: Reg,
2977     arg2: &VectorSize,
2978 ) -> Option<Reg> {
2979     let pattern0_0 = arg0;
2980     let pattern1_0 = arg1;
2981     let pattern2_0 = arg2;
2982     // Rule at src/isa/aarch64/inst.isle line 1824.
2983     let expr0_0 = VecALUOp::Bic;
2984     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2985     return Some(expr1_0);
2986 }
2987 
2988 // Generated as internal constructor for term sshl.
2989 pub fn constructor_sshl<C: Context>(
2990     ctx: &mut C,
2991     arg0: Reg,
2992     arg1: Reg,
2993     arg2: &VectorSize,
2994 ) -> Option<Reg> {
2995     let pattern0_0 = arg0;
2996     let pattern1_0 = arg1;
2997     let pattern2_0 = arg2;
2998     // Rule at src/isa/aarch64/inst.isle line 1828.
2999     let expr0_0 = VecALUOp::Sshl;
3000     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3001     return Some(expr1_0);
3002 }
3003 
3004 // Generated as internal constructor for term ushl.
3005 pub fn constructor_ushl<C: Context>(
3006     ctx: &mut C,
3007     arg0: Reg,
3008     arg1: Reg,
3009     arg2: &VectorSize,
3010 ) -> Option<Reg> {
3011     let pattern0_0 = arg0;
3012     let pattern1_0 = arg1;
3013     let pattern2_0 = arg2;
3014     // Rule at src/isa/aarch64/inst.isle line 1832.
3015     let expr0_0 = VecALUOp::Ushl;
3016     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3017     return Some(expr1_0);
3018 }
3019 
3020 // Generated as internal constructor for term a64_rotr.
3021 pub fn constructor_a64_rotr<C: Context>(
3022     ctx: &mut C,
3023     arg0: Type,
3024     arg1: Reg,
3025     arg2: Reg,
3026 ) -> Option<Reg> {
3027     let pattern0_0 = arg0;
3028     let pattern1_0 = arg1;
3029     let pattern2_0 = arg2;
3030     // Rule at src/isa/aarch64/inst.isle line 1837.
3031     let expr0_0 = ALUOp::RotR;
3032     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3033     return Some(expr1_0);
3034 }
3035 
3036 // Generated as internal constructor for term a64_rotr_imm.
3037 pub fn constructor_a64_rotr_imm<C: Context>(
3038     ctx: &mut C,
3039     arg0: Type,
3040     arg1: Reg,
3041     arg2: ImmShift,
3042 ) -> Option<Reg> {
3043     let pattern0_0 = arg0;
3044     let pattern1_0 = arg1;
3045     let pattern2_0 = arg2;
3046     // Rule at src/isa/aarch64/inst.isle line 1840.
3047     let expr0_0 = ALUOp::RotR;
3048     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3049     return Some(expr1_0);
3050 }
3051 
3052 // Generated as internal constructor for term rbit.
3053 pub fn constructor_rbit<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
3054     let pattern0_0 = arg0;
3055     let pattern1_0 = arg1;
3056     // Rule at src/isa/aarch64/inst.isle line 1845.
3057     let expr0_0 = BitOp::RBit;
3058     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3059     return Some(expr1_0);
3060 }
3061 
3062 // Generated as internal constructor for term a64_clz.
3063 pub fn constructor_a64_clz<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
3064     let pattern0_0 = arg0;
3065     let pattern1_0 = arg1;
3066     // Rule at src/isa/aarch64/inst.isle line 1850.
3067     let expr0_0 = BitOp::Clz;
3068     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3069     return Some(expr1_0);
3070 }
3071 
3072 // Generated as internal constructor for term a64_cls.
3073 pub fn constructor_a64_cls<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
3074     let pattern0_0 = arg0;
3075     let pattern1_0 = arg1;
3076     // Rule at src/isa/aarch64/inst.isle line 1855.
3077     let expr0_0 = BitOp::Cls;
3078     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3079     return Some(expr1_0);
3080 }
3081 
3082 // Generated as internal constructor for term eon.
3083 pub fn constructor_eon<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
3084     let pattern0_0 = arg0;
3085     let pattern1_0 = arg1;
3086     let pattern2_0 = arg2;
3087     // Rule at src/isa/aarch64/inst.isle line 1860.
3088     let expr0_0 = ALUOp::EorNot;
3089     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3090     return Some(expr1_0);
3091 }
3092 
3093 // Generated as internal constructor for term vec_cnt.
3094 pub fn constructor_vec_cnt<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3095     let pattern0_0 = arg0;
3096     let pattern1_0 = arg1;
3097     // Rule at src/isa/aarch64/inst.isle line 1865.
3098     let expr0_0 = VecMisc2::Cnt;
3099     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3100     return Some(expr1_0);
3101 }
3102 
3103 // Generated as internal constructor for term imm.
3104 pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
3105     let pattern0_0 = arg0;
3106     if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) {
3107         let pattern2_0 = arg1;
3108         let mut closure3 = || {
3109             let expr0_0: Type = I64;
3110             return Some(expr0_0);
3111         };
3112         if let Some(pattern3_0) = closure3() {
3113             if let Some(pattern4_0) = C::imm_logic_from_u64(ctx, pattern2_0, pattern3_0) {
3114                 // Rule at src/isa/aarch64/inst.isle line 1880.
3115                 let expr0_0: Type = I64;
3116                 let expr1_0 = C::zero_reg(ctx);
3117                 let expr2_0 = constructor_orr_imm(ctx, expr0_0, expr1_0, pattern4_0)?;
3118                 return Some(expr2_0);
3119             }
3120         }
3121         if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) {
3122             // Rule at src/isa/aarch64/inst.isle line 1872.
3123             let expr0_0 = OperandSize::Size64;
3124             let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?;
3125             return Some(expr1_0);
3126         }
3127         if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) {
3128             // Rule at src/isa/aarch64/inst.isle line 1876.
3129             let expr0_0 = OperandSize::Size64;
3130             let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?;
3131             return Some(expr1_0);
3132         }
3133         // Rule at src/isa/aarch64/inst.isle line 1887.
3134         let expr0_0 = C::load_constant64_full(ctx, pattern2_0);
3135         return Some(expr0_0);
3136     }
3137     return None;
3138 }
3139 
3140 // Generated as internal constructor for term put_in_reg_sext32.
3141 pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3142     let pattern0_0 = arg0;
3143     let pattern1_0 = C::value_type(ctx, pattern0_0);
3144     if pattern1_0 == I32 {
3145         // Rule at src/isa/aarch64/inst.isle line 1898.
3146         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3147         return Some(expr0_0);
3148     }
3149     if pattern1_0 == I64 {
3150         // Rule at src/isa/aarch64/inst.isle line 1899.
3151         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3152         return Some(expr0_0);
3153     }
3154     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3155         // Rule at src/isa/aarch64/inst.isle line 1894.
3156         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3157         let expr1_0: bool = true;
3158         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3159         let expr3_0: u8 = 32;
3160         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3161         return Some(expr4_0);
3162     }
3163     return None;
3164 }
3165 
3166 // Generated as internal constructor for term put_in_reg_zext32.
3167 pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3168     let pattern0_0 = arg0;
3169     let pattern1_0 = C::value_type(ctx, pattern0_0);
3170     if pattern1_0 == I32 {
3171         // Rule at src/isa/aarch64/inst.isle line 1907.
3172         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3173         return Some(expr0_0);
3174     }
3175     if pattern1_0 == I64 {
3176         // Rule at src/isa/aarch64/inst.isle line 1908.
3177         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3178         return Some(expr0_0);
3179     }
3180     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3181         // Rule at src/isa/aarch64/inst.isle line 1903.
3182         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3183         let expr1_0: bool = false;
3184         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3185         let expr3_0: u8 = 32;
3186         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3187         return Some(expr4_0);
3188     }
3189     return None;
3190 }
3191 
3192 // Generated as internal constructor for term put_in_reg_sext64.
3193 pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3194     let pattern0_0 = arg0;
3195     let pattern1_0 = C::value_type(ctx, pattern0_0);
3196     if pattern1_0 == I64 {
3197         // Rule at src/isa/aarch64/inst.isle line 1916.
3198         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3199         return Some(expr0_0);
3200     }
3201     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3202         // Rule at src/isa/aarch64/inst.isle line 1912.
3203         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3204         let expr1_0: bool = true;
3205         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3206         let expr3_0: u8 = 64;
3207         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3208         return Some(expr4_0);
3209     }
3210     return None;
3211 }
3212 
3213 // Generated as internal constructor for term put_in_reg_zext64.
3214 pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3215     let pattern0_0 = arg0;
3216     let pattern1_0 = C::value_type(ctx, pattern0_0);
3217     if pattern1_0 == I64 {
3218         // Rule at src/isa/aarch64/inst.isle line 1924.
3219         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3220         return Some(expr0_0);
3221     }
3222     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3223         // Rule at src/isa/aarch64/inst.isle line 1920.
3224         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3225         let expr1_0: bool = false;
3226         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3227         let expr3_0: u8 = 64;
3228         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3229         return Some(expr4_0);
3230     }
3231     return None;
3232 }
3233 
3234 // Generated as internal constructor for term trap_if_zero_divisor.
3235 pub fn constructor_trap_if_zero_divisor<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3236     let pattern0_0 = arg0;
3237     // Rule at src/isa/aarch64/inst.isle line 1929.
3238     let expr0_0 = C::cond_br_zero(ctx, pattern0_0);
3239     let expr1_0 = C::trap_code_division_by_zero(ctx);
3240     let expr2_0 = MInst::TrapIf {
3241         kind: expr0_0,
3242         trap_code: expr1_0,
3243     };
3244     let expr3_0 = C::emit(ctx, &expr2_0);
3245     return Some(pattern0_0);
3246 }
3247 
3248 // Generated as internal constructor for term size_from_ty.
3249 pub fn constructor_size_from_ty<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
3250     let pattern0_0 = arg0;
3251     if pattern0_0 == I64 {
3252         // Rule at src/isa/aarch64/inst.isle line 1935.
3253         let expr0_0 = OperandSize::Size64;
3254         return Some(expr0_0);
3255     }
3256     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
3257         // Rule at src/isa/aarch64/inst.isle line 1934.
3258         let expr0_0 = OperandSize::Size32;
3259         return Some(expr0_0);
3260     }
3261     return None;
3262 }
3263 
3264 // Generated as internal constructor for term trap_if_div_overflow.
3265 pub fn constructor_trap_if_div_overflow<C: Context>(
3266     ctx: &mut C,
3267     arg0: Type,
3268     arg1: Reg,
3269     arg2: Reg,
3270 ) -> Option<Reg> {
3271     let pattern0_0 = arg0;
3272     let pattern1_0 = arg1;
3273     let pattern2_0 = arg2;
3274     // Rule at src/isa/aarch64/inst.isle line 1941.
3275     let expr0_0 = ALUOp::AddS;
3276     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
3277     let expr2_0 = C::writable_zero_reg(ctx);
3278     let expr3_0: u8 = 1;
3279     let expr4_0 = C::u8_into_imm12(ctx, expr3_0);
3280     let expr5_0 = MInst::AluRRImm12 {
3281         alu_op: expr0_0,
3282         size: expr1_0,
3283         rd: expr2_0,
3284         rn: pattern2_0,
3285         imm12: expr4_0,
3286     };
3287     let expr6_0 = C::emit(ctx, &expr5_0);
3288     let expr7_0 = constructor_size_from_ty(ctx, pattern0_0)?;
3289     let expr8_0: u8 = 1;
3290     let expr9_0 = C::u8_into_uimm5(ctx, expr8_0);
3291     let expr10_0: bool = false;
3292     let expr11_0: bool = false;
3293     let expr12_0: bool = false;
3294     let expr13_0: bool = false;
3295     let expr14_0 = C::nzcv(ctx, expr10_0, expr11_0, expr12_0, expr13_0);
3296     let expr15_0 = Cond::Eq;
3297     let expr16_0 = MInst::CCmpImm {
3298         size: expr7_0,
3299         rn: pattern1_0,
3300         imm: expr9_0,
3301         nzcv: expr14_0,
3302         cond: expr15_0,
3303     };
3304     let expr17_0 = C::emit(ctx, &expr16_0);
3305     let expr18_0 = Cond::Vs;
3306     let expr19_0 = C::cond_br_cond(ctx, &expr18_0);
3307     let expr20_0 = C::trap_code_integer_overflow(ctx);
3308     let expr21_0 = MInst::TrapIf {
3309         kind: expr19_0,
3310         trap_code: expr20_0,
3311     };
3312     let expr22_0 = C::emit(ctx, &expr21_0);
3313     return Some(pattern1_0);
3314 }
3315 
3316 // Generated as internal constructor for term alu_rs_imm_logic_commutative.
3317 pub fn constructor_alu_rs_imm_logic_commutative<C: Context>(
3318     ctx: &mut C,
3319     arg0: &ALUOp,
3320     arg1: Type,
3321     arg2: Value,
3322     arg3: Value,
3323 ) -> Option<Reg> {
3324     let pattern0_0 = arg0;
3325     let pattern1_0 = arg1;
3326     let pattern2_0 = arg2;
3327     if let Some(pattern3_0) = C::def_inst(ctx, pattern2_0) {
3328         let pattern4_0 = C::inst_data(ctx, pattern3_0);
3329         match &pattern4_0 {
3330             &InstructionData::UnaryImm {
3331                 opcode: ref pattern5_0,
3332                 imm: pattern5_1,
3333             } => {
3334                 if let &Opcode::Iconst = pattern5_0 {
3335                     let mut closure7 = || {
3336                         return Some(pattern1_0);
3337                     };
3338                     if let Some(pattern7_0) = closure7() {
3339                         if let Some(pattern8_0) =
3340                             C::imm_logic_from_imm64(ctx, pattern5_1, pattern7_0)
3341                         {
3342                             let pattern9_0 = arg3;
3343                             // Rule at src/isa/aarch64/inst.isle line 1986.
3344                             let expr0_0 = C::put_in_reg(ctx, pattern9_0);
3345                             let expr1_0 = constructor_alu_rr_imm_logic(
3346                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0,
3347                             )?;
3348                             return Some(expr1_0);
3349                         }
3350                     }
3351                 }
3352             }
3353             &InstructionData::Binary {
3354                 opcode: ref pattern5_0,
3355                 args: ref pattern5_1,
3356             } => {
3357                 if let &Opcode::Ishl = pattern5_0 {
3358                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3359                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3360                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
3361                         if let &InstructionData::UnaryImm {
3362                             opcode: ref pattern10_0,
3363                             imm: pattern10_1,
3364                         } = &pattern9_0
3365                         {
3366                             if let &Opcode::Iconst = pattern10_0 {
3367                                 let mut closure12 = || {
3368                                     return Some(pattern1_0);
3369                                 };
3370                                 if let Some(pattern12_0) = closure12() {
3371                                     if let Some(pattern13_0) =
3372                                         C::lshl_from_imm64(ctx, pattern10_1, pattern12_0)
3373                                     {
3374                                         let pattern14_0 = arg3;
3375                                         // Rule at src/isa/aarch64/inst.isle line 1992.
3376                                         let expr0_0 = C::put_in_reg(ctx, pattern14_0);
3377                                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3378                                         let expr2_0 = constructor_alu_rrr_shift(
3379                                             ctx,
3380                                             pattern0_0,
3381                                             pattern1_0,
3382                                             expr0_0,
3383                                             expr1_0,
3384                                             pattern13_0,
3385                                         )?;
3386                                         return Some(expr2_0);
3387                                     }
3388                                 }
3389                             }
3390                         }
3391                     }
3392                 }
3393             }
3394             _ => {}
3395         }
3396     }
3397     let pattern3_0 = arg3;
3398     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3399         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3400         match &pattern5_0 {
3401             &InstructionData::UnaryImm {
3402                 opcode: ref pattern6_0,
3403                 imm: pattern6_1,
3404             } => {
3405                 if let &Opcode::Iconst = pattern6_0 {
3406                     let mut closure8 = || {
3407                         return Some(pattern1_0);
3408                     };
3409                     if let Some(pattern8_0) = closure8() {
3410                         if let Some(pattern9_0) =
3411                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3412                         {
3413                             // Rule at src/isa/aarch64/inst.isle line 1984.
3414                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3415                             let expr1_0 = constructor_alu_rr_imm_logic(
3416                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3417                             )?;
3418                             return Some(expr1_0);
3419                         }
3420                     }
3421                 }
3422             }
3423             &InstructionData::Binary {
3424                 opcode: ref pattern6_0,
3425                 args: ref pattern6_1,
3426             } => {
3427                 if let &Opcode::Ishl = pattern6_0 {
3428                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3429                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3430                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3431                         if let &InstructionData::UnaryImm {
3432                             opcode: ref pattern11_0,
3433                             imm: pattern11_1,
3434                         } = &pattern10_0
3435                         {
3436                             if let &Opcode::Iconst = pattern11_0 {
3437                                 let mut closure13 = || {
3438                                     return Some(pattern1_0);
3439                                 };
3440                                 if let Some(pattern13_0) = closure13() {
3441                                     if let Some(pattern14_0) =
3442                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3443                                     {
3444                                         // Rule at src/isa/aarch64/inst.isle line 1990.
3445                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3446                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3447                                         let expr2_0 = constructor_alu_rrr_shift(
3448                                             ctx,
3449                                             pattern0_0,
3450                                             pattern1_0,
3451                                             expr0_0,
3452                                             expr1_0,
3453                                             pattern14_0,
3454                                         )?;
3455                                         return Some(expr2_0);
3456                                     }
3457                                 }
3458                             }
3459                         }
3460                     }
3461                 }
3462             }
3463             _ => {}
3464         }
3465     }
3466     // Rule at src/isa/aarch64/inst.isle line 1980.
3467     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3468     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3469     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3470     return Some(expr2_0);
3471 }
3472 
3473 // Generated as internal constructor for term alu_rs_imm_logic.
3474 pub fn constructor_alu_rs_imm_logic<C: Context>(
3475     ctx: &mut C,
3476     arg0: &ALUOp,
3477     arg1: Type,
3478     arg2: Value,
3479     arg3: Value,
3480 ) -> Option<Reg> {
3481     let pattern0_0 = arg0;
3482     let pattern1_0 = arg1;
3483     let pattern2_0 = arg2;
3484     let pattern3_0 = arg3;
3485     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3486         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3487         match &pattern5_0 {
3488             &InstructionData::UnaryImm {
3489                 opcode: ref pattern6_0,
3490                 imm: pattern6_1,
3491             } => {
3492                 if let &Opcode::Iconst = pattern6_0 {
3493                     let mut closure8 = || {
3494                         return Some(pattern1_0);
3495                     };
3496                     if let Some(pattern8_0) = closure8() {
3497                         if let Some(pattern9_0) =
3498                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3499                         {
3500                             // Rule at src/isa/aarch64/inst.isle line 2000.
3501                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3502                             let expr1_0 = constructor_alu_rr_imm_logic(
3503                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3504                             )?;
3505                             return Some(expr1_0);
3506                         }
3507                     }
3508                 }
3509             }
3510             &InstructionData::Binary {
3511                 opcode: ref pattern6_0,
3512                 args: ref pattern6_1,
3513             } => {
3514                 if let &Opcode::Ishl = pattern6_0 {
3515                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3516                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3517                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3518                         if let &InstructionData::UnaryImm {
3519                             opcode: ref pattern11_0,
3520                             imm: pattern11_1,
3521                         } = &pattern10_0
3522                         {
3523                             if let &Opcode::Iconst = pattern11_0 {
3524                                 let mut closure13 = || {
3525                                     return Some(pattern1_0);
3526                                 };
3527                                 if let Some(pattern13_0) = closure13() {
3528                                     if let Some(pattern14_0) =
3529                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3530                                     {
3531                                         // Rule at src/isa/aarch64/inst.isle line 2002.
3532                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3533                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3534                                         let expr2_0 = constructor_alu_rrr_shift(
3535                                             ctx,
3536                                             pattern0_0,
3537                                             pattern1_0,
3538                                             expr0_0,
3539                                             expr1_0,
3540                                             pattern14_0,
3541                                         )?;
3542                                         return Some(expr2_0);
3543                                     }
3544                                 }
3545                             }
3546                         }
3547                     }
3548                 }
3549             }
3550             _ => {}
3551         }
3552     }
3553     // Rule at src/isa/aarch64/inst.isle line 1998.
3554     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3555     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3556     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3557     return Some(expr2_0);
3558 }
3559 
3560 // Generated as internal constructor for term i128_alu_bitop.
3561 pub fn constructor_i128_alu_bitop<C: Context>(
3562     ctx: &mut C,
3563     arg0: &ALUOp,
3564     arg1: Type,
3565     arg2: Value,
3566     arg3: Value,
3567 ) -> Option<ValueRegs> {
3568     let pattern0_0 = arg0;
3569     let pattern1_0 = arg1;
3570     let pattern2_0 = arg2;
3571     let pattern3_0 = arg3;
3572     // Rule at src/isa/aarch64/inst.isle line 2010.
3573     let expr0_0 = C::put_in_regs(ctx, pattern2_0);
3574     let expr1_0: usize = 0;
3575     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3576     let expr3_0: usize = 1;
3577     let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
3578     let expr5_0 = C::put_in_regs(ctx, pattern3_0);
3579     let expr6_0: usize = 0;
3580     let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
3581     let expr8_0: usize = 1;
3582     let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
3583     let expr10_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr2_0, expr7_0)?;
3584     let expr11_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr4_0, expr9_0)?;
3585     let expr12_0 = C::value_regs(ctx, expr10_0, expr11_0);
3586     return Some(expr12_0);
3587 }
3588 
3589 // Generated as internal constructor for term float_cmp_zero.
3590 pub fn constructor_float_cmp_zero<C: Context>(
3591     ctx: &mut C,
3592     arg0: &FloatCC,
3593     arg1: Reg,
3594     arg2: &VectorSize,
3595 ) -> Option<Reg> {
3596     let pattern0_0 = arg0;
3597     let pattern1_0 = arg1;
3598     let pattern2_0 = arg2;
3599     // Rule at src/isa/aarch64/inst.isle line 2050.
3600     let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0);
3601     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3602     return Some(expr1_0);
3603 }
3604 
3605 // Generated as internal constructor for term float_cmp_zero_swap.
3606 pub fn constructor_float_cmp_zero_swap<C: Context>(
3607     ctx: &mut C,
3608     arg0: &FloatCC,
3609     arg1: Reg,
3610     arg2: &VectorSize,
3611 ) -> Option<Reg> {
3612     let pattern0_0 = arg0;
3613     let pattern1_0 = arg1;
3614     let pattern2_0 = arg2;
3615     // Rule at src/isa/aarch64/inst.isle line 2055.
3616     let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0);
3617     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3618     return Some(expr1_0);
3619 }
3620 
3621 // Generated as internal constructor for term fcmeq0.
3622 pub fn constructor_fcmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3623     let pattern0_0 = arg0;
3624     let pattern1_0 = arg1;
3625     // Rule at src/isa/aarch64/inst.isle line 2060.
3626     let expr0_0 = VecMisc2::Fcmeq0;
3627     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3628     return Some(expr1_0);
3629 }
3630 
3631 // Generated as internal constructor for term int_cmp_zero.
3632 pub fn constructor_int_cmp_zero<C: Context>(
3633     ctx: &mut C,
3634     arg0: &IntCC,
3635     arg1: Reg,
3636     arg2: &VectorSize,
3637 ) -> Option<Reg> {
3638     let pattern0_0 = arg0;
3639     let pattern1_0 = arg1;
3640     let pattern2_0 = arg2;
3641     // Rule at src/isa/aarch64/inst.isle line 2086.
3642     let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0);
3643     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3644     return Some(expr1_0);
3645 }
3646 
3647 // Generated as internal constructor for term int_cmp_zero_swap.
3648 pub fn constructor_int_cmp_zero_swap<C: Context>(
3649     ctx: &mut C,
3650     arg0: &IntCC,
3651     arg1: Reg,
3652     arg2: &VectorSize,
3653 ) -> Option<Reg> {
3654     let pattern0_0 = arg0;
3655     let pattern1_0 = arg1;
3656     let pattern2_0 = arg2;
3657     // Rule at src/isa/aarch64/inst.isle line 2091.
3658     let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0);
3659     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3660     return Some(expr1_0);
3661 }
3662 
3663 // Generated as internal constructor for term cmeq0.
3664 pub fn constructor_cmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3665     let pattern0_0 = arg0;
3666     let pattern1_0 = arg1;
3667     // Rule at src/isa/aarch64/inst.isle line 2096.
3668     let expr0_0 = VecMisc2::Cmeq0;
3669     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3670     return Some(expr1_0);
3671 }
3672 
3673 // Generated as internal constructor for term lse_atomic_rmw.
3674 pub fn constructor_lse_atomic_rmw<C: Context>(
3675     ctx: &mut C,
3676     arg0: &AtomicRMWOp,
3677     arg1: Value,
3678     arg2: Reg,
3679     arg3: Type,
3680 ) -> Option<Reg> {
3681     let pattern0_0 = arg0;
3682     let pattern1_0 = arg1;
3683     let pattern2_0 = arg2;
3684     let pattern3_0 = arg3;
3685     // Rule at src/isa/aarch64/inst.isle line 2101.
3686     let expr0_0 = C::put_in_reg(ctx, pattern1_0);
3687     let expr1_0 = C::temp_writable_reg(ctx, pattern3_0);
3688     let expr2_0 = MInst::AtomicRMW {
3689         op: pattern0_0.clone(),
3690         rs: pattern2_0,
3691         rt: expr1_0,
3692         rn: expr0_0,
3693         ty: pattern3_0,
3694     };
3695     let expr3_0 = C::emit(ctx, &expr2_0);
3696     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
3697     return Some(expr4_0);
3698 }
3699 
3700 // Generated as internal constructor for term atomic_rmw_loop.
3701 pub fn constructor_atomic_rmw_loop<C: Context>(
3702     ctx: &mut C,
3703     arg0: &AtomicRMWLoopOp,
3704     arg1: Value,
3705     arg2: Value,
3706     arg3: Type,
3707 ) -> Option<Reg> {
3708     let pattern0_0 = arg0;
3709     let pattern1_0 = arg1;
3710     let pattern2_0 = arg2;
3711     let pattern3_0 = arg3;
3712     // Rule at src/isa/aarch64/inst.isle line 2116.
3713     let expr0_0 = C::put_in_reg(ctx, pattern1_0);
3714     let expr1_0: Type = I64;
3715     let expr2_0 = C::ensure_in_vreg(ctx, expr0_0, expr1_0);
3716     let expr3_0 = C::put_in_reg(ctx, pattern2_0);
3717     let expr4_0: Type = I64;
3718     let expr5_0 = C::ensure_in_vreg(ctx, expr3_0, expr4_0);
3719     let expr6_0: u8 = 25;
3720     let expr7_0 = constructor_mov64_to_real(ctx, expr6_0, expr2_0)?;
3721     let expr8_0: u8 = 26;
3722     let expr9_0 = constructor_mov64_to_real(ctx, expr8_0, expr5_0)?;
3723     let expr10_0 = MInst::AtomicRMWLoop {
3724         ty: pattern3_0,
3725         op: pattern0_0.clone(),
3726     };
3727     let expr11_0 = C::emit(ctx, &expr10_0);
3728     let expr12_0: u8 = 27;
3729     let expr13_0 = constructor_mov64_from_real(ctx, expr12_0)?;
3730     return Some(expr13_0);
3731 }
3732 
3733 // Generated as internal constructor for term lower.
3734 pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> {
3735     let pattern0_0 = arg0;
3736     if let Some(()) = C::use_lse(ctx, pattern0_0) {
3737         if let Some(pattern2_0) = C::first_result(ctx, pattern0_0) {
3738             let pattern3_0 = C::value_type(ctx, pattern2_0);
3739             if let Some(pattern4_0) = C::valid_atomic_transaction(ctx, pattern3_0) {
3740                 let pattern5_0 = C::inst_data(ctx, pattern0_0);
3741                 if let &InstructionData::AtomicRmw {
3742                     opcode: ref pattern6_0,
3743                     args: ref pattern6_1,
3744                     flags: pattern6_2,
3745                     op: ref pattern6_3,
3746                 } = &pattern5_0
3747                 {
3748                     if let &Opcode::AtomicRmw = pattern6_0 {
3749                         let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3750                         match pattern6_3 {
3751                             &AtomicRmwOp::Add => {
3752                                 // Rule at src/isa/aarch64/lower.isle line 1202.
3753                                 let expr0_0 = AtomicRMWOp::Add;
3754                                 let expr1_0 = C::put_in_reg(ctx, pattern8_1);
3755                                 let expr2_0 = constructor_lse_atomic_rmw(
3756                                     ctx, &expr0_0, pattern8_0, expr1_0, pattern4_0,
3757                                 )?;
3758                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3759                                 return Some(expr3_0);
3760                             }
3761                             &AtomicRmwOp::And => {
3762                                 // Rule at src/isa/aarch64/lower.isle line 1234.
3763                                 let expr0_0 = AtomicRMWOp::Clr;
3764                                 let expr1_0 = C::put_in_reg(ctx, pattern8_1);
3765                                 let expr2_0 = C::zero_reg(ctx);
3766                                 let expr3_0 = constructor_eon(ctx, pattern4_0, expr1_0, expr2_0)?;
3767                                 let expr4_0 = constructor_lse_atomic_rmw(
3768                                     ctx, &expr0_0, pattern8_0, expr3_0, pattern4_0,
3769                                 )?;
3770                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3771                                 return Some(expr5_0);
3772                             }
3773                             &AtomicRmwOp::Or => {
3774                                 // Rule at src/isa/aarch64/lower.isle line 1210.
3775                                 let expr0_0 = AtomicRMWOp::Set;
3776                                 let expr1_0 = C::put_in_reg(ctx, pattern8_1);
3777                                 let expr2_0 = constructor_lse_atomic_rmw(
3778                                     ctx, &expr0_0, pattern8_0, expr1_0, pattern4_0,
3779                                 )?;
3780                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3781                                 return Some(expr3_0);
3782                             }
3783                             &AtomicRmwOp::Smax => {
3784                                 // Rule at src/isa/aarch64/lower.isle line 1214.
3785                                 let expr0_0 = AtomicRMWOp::Smax;
3786                                 let expr1_0 = C::put_in_reg(ctx, pattern8_1);
3787                                 let expr2_0 = constructor_lse_atomic_rmw(
3788                                     ctx, &expr0_0, pattern8_0, expr1_0, pattern4_0,
3789                                 )?;
3790                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3791                                 return Some(expr3_0);
3792                             }
3793                             &AtomicRmwOp::Smin => {
3794                                 // Rule at src/isa/aarch64/lower.isle line 1218.
3795                                 let expr0_0 = AtomicRMWOp::Smin;
3796                                 let expr1_0 = C::put_in_reg(ctx, pattern8_1);
3797                                 let expr2_0 = constructor_lse_atomic_rmw(
3798                                     ctx, &expr0_0, pattern8_0, expr1_0, pattern4_0,
3799                                 )?;
3800                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3801                                 return Some(expr3_0);
3802                             }
3803                             &AtomicRmwOp::Sub => {
3804                                 // Rule at src/isa/aarch64/lower.isle line 1230.
3805                                 let expr0_0 = AtomicRMWOp::Add;
3806                                 let expr1_0 = C::zero_reg(ctx);
3807                                 let expr2_0 = C::put_in_reg(ctx, pattern8_1);
3808                                 let expr3_0 = constructor_sub(ctx, pattern4_0, expr1_0, expr2_0)?;
3809                                 let expr4_0 = constructor_lse_atomic_rmw(
3810                                     ctx, &expr0_0, pattern8_0, expr3_0, pattern4_0,
3811                                 )?;
3812                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3813                                 return Some(expr5_0);
3814                             }
3815                             &AtomicRmwOp::Umax => {
3816                                 // Rule at src/isa/aarch64/lower.isle line 1222.
3817                                 let expr0_0 = AtomicRMWOp::Umax;
3818                                 let expr1_0 = C::put_in_reg(ctx, pattern8_1);
3819                                 let expr2_0 = constructor_lse_atomic_rmw(
3820                                     ctx, &expr0_0, pattern8_0, expr1_0, pattern4_0,
3821                                 )?;
3822                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3823                                 return Some(expr3_0);
3824                             }
3825                             &AtomicRmwOp::Umin => {
3826                                 // Rule at src/isa/aarch64/lower.isle line 1226.
3827                                 let expr0_0 = AtomicRMWOp::Umin;
3828                                 let expr1_0 = C::put_in_reg(ctx, pattern8_1);
3829                                 let expr2_0 = constructor_lse_atomic_rmw(
3830                                     ctx, &expr0_0, pattern8_0, expr1_0, pattern4_0,
3831                                 )?;
3832                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3833                                 return Some(expr3_0);
3834                             }
3835                             &AtomicRmwOp::Xor => {
3836                                 // Rule at src/isa/aarch64/lower.isle line 1206.
3837                                 let expr0_0 = AtomicRMWOp::Eor;
3838                                 let expr1_0 = C::put_in_reg(ctx, pattern8_1);
3839                                 let expr2_0 = constructor_lse_atomic_rmw(
3840                                     ctx, &expr0_0, pattern8_0, expr1_0, pattern4_0,
3841                                 )?;
3842                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3843                                 return Some(expr3_0);
3844                             }
3845                             _ => {}
3846                         }
3847                     }
3848                 }
3849             }
3850         }
3851     }
3852     if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
3853         let pattern2_0 = C::value_type(ctx, pattern1_0);
3854         if pattern2_0 == I8 {
3855             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3856             if let &InstructionData::Unary {
3857                 opcode: ref pattern5_0,
3858                 arg: pattern5_1,
3859             } = &pattern4_0
3860             {
3861                 match pattern5_0 {
3862                     &Opcode::Bitrev => {
3863                         // Rule at src/isa/aarch64/lower.isle line 980.
3864                         let expr0_0: Type = I32;
3865                         let expr1_0: Type = I32;
3866                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3867                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3868                         let expr4_0: u8 = 24;
3869                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3870                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3871                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3872                         return Some(expr7_0);
3873                     }
3874                     &Opcode::Clz => {
3875                         // Rule at src/isa/aarch64/lower.isle line 1001.
3876                         let expr0_0: Type = I32;
3877                         let expr1_0: Type = I32;
3878                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3879                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3880                         let expr4_0: u8 = 24;
3881                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3882                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3883                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3884                         return Some(expr7_0);
3885                     }
3886                     &Opcode::Cls => {
3887                         // Rule at src/isa/aarch64/lower.isle line 1048.
3888                         let expr0_0: Type = I32;
3889                         let expr1_0: Type = I32;
3890                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3891                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3892                         let expr4_0: u8 = 24;
3893                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3894                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3895                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3896                         return Some(expr7_0);
3897                     }
3898                     &Opcode::Ctz => {
3899                         // Rule at src/isa/aarch64/lower.isle line 1031.
3900                         let expr0_0: Type = I32;
3901                         let expr1_0: Type = I32;
3902                         let expr2_0: Type = I32;
3903                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3904                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3905                         let expr5_0: Type = I32;
3906                         let expr6_0: u64 = 8388608;
3907                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3908                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3909                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3910                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3911                         return Some(expr10_0);
3912                     }
3913                     &Opcode::Popcnt => {
3914                         // Rule at src/isa/aarch64/lower.isle line 1099.
3915                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3916                         let expr1_0 = ScalarSize::Size32;
3917                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3918                         let expr3_0 = VectorSize::Size8x8;
3919                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3920                         let expr5_0: u8 = 0;
3921                         let expr6_0 = VectorSize::Size8x16;
3922                         let expr7_0 = constructor_mov_from_vec(ctx, expr4_0, expr5_0, &expr6_0)?;
3923                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
3924                         return Some(expr8_0);
3925                     }
3926                     _ => {}
3927                 }
3928             }
3929         }
3930         if pattern2_0 == I16 {
3931             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3932             if let &InstructionData::Unary {
3933                 opcode: ref pattern5_0,
3934                 arg: pattern5_1,
3935             } = &pattern4_0
3936             {
3937                 match pattern5_0 {
3938                     &Opcode::Bitrev => {
3939                         // Rule at src/isa/aarch64/lower.isle line 986.
3940                         let expr0_0: Type = I32;
3941                         let expr1_0: Type = I32;
3942                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3943                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3944                         let expr4_0: u8 = 16;
3945                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3946                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3947                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3948                         return Some(expr7_0);
3949                     }
3950                     &Opcode::Clz => {
3951                         // Rule at src/isa/aarch64/lower.isle line 1004.
3952                         let expr0_0: Type = I32;
3953                         let expr1_0: Type = I32;
3954                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3955                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3956                         let expr4_0: u8 = 16;
3957                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3958                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3959                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3960                         return Some(expr7_0);
3961                     }
3962                     &Opcode::Cls => {
3963                         // Rule at src/isa/aarch64/lower.isle line 1051.
3964                         let expr0_0: Type = I32;
3965                         let expr1_0: Type = I32;
3966                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3967                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3968                         let expr4_0: u8 = 16;
3969                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3970                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3971                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3972                         return Some(expr7_0);
3973                     }
3974                     &Opcode::Ctz => {
3975                         // Rule at src/isa/aarch64/lower.isle line 1034.
3976                         let expr0_0: Type = I32;
3977                         let expr1_0: Type = I32;
3978                         let expr2_0: Type = I32;
3979                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3980                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3981                         let expr5_0: Type = I32;
3982                         let expr6_0: u64 = 32768;
3983                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3984                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3985                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3986                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3987                         return Some(expr10_0);
3988                     }
3989                     &Opcode::Popcnt => {
3990                         // Rule at src/isa/aarch64/lower.isle line 1105.
3991                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3992                         let expr1_0 = ScalarSize::Size32;
3993                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3994                         let expr3_0 = VectorSize::Size8x8;
3995                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3996                         let expr5_0 = VectorSize::Size8x8;
3997                         let expr6_0 = constructor_addp(ctx, expr4_0, expr4_0, &expr5_0)?;
3998                         let expr7_0: u8 = 0;
3999                         let expr8_0 = VectorSize::Size8x16;
4000                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
4001                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
4002                         return Some(expr10_0);
4003                     }
4004                     _ => {}
4005                 }
4006             }
4007         }
4008         if pattern2_0 == I32 {
4009             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4010             match &pattern4_0 {
4011                 &InstructionData::Binary {
4012                     opcode: ref pattern5_0,
4013                     args: ref pattern5_1,
4014                 } => {
4015                     match pattern5_0 {
4016                         &Opcode::Rotl => {
4017                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4018                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
4019                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
4020                                 if let &InstructionData::UnaryImm {
4021                                     opcode: ref pattern10_0,
4022                                     imm: pattern10_1,
4023                                 } = &pattern9_0
4024                                 {
4025                                     if let &Opcode::Iconst = pattern10_0 {
4026                                         let mut closure12 = || {
4027                                             let expr0_0: Type = I32;
4028                                             return Some(expr0_0);
4029                                         };
4030                                         if let Some(pattern12_0) = closure12() {
4031                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4032                                                 ctx,
4033                                                 pattern10_1,
4034                                                 pattern12_0,
4035                                             ) {
4036                                                 // Rule at src/isa/aarch64/lower.isle line 871.
4037                                                 let expr0_0: Type = I32;
4038                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4039                                                 let expr2_0: Type = I32;
4040                                                 let expr3_0 =
4041                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
4042                                                 let expr4_0 = constructor_a64_rotr_imm(
4043                                                     ctx, expr0_0, expr1_0, expr3_0,
4044                                                 )?;
4045                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
4046                                                 return Some(expr5_0);
4047                                             }
4048                                         }
4049                                     }
4050                                 }
4051                             }
4052                             // Rule at src/isa/aarch64/lower.isle line 861.
4053                             let expr0_0: Type = I32;
4054                             let expr1_0 = C::zero_reg(ctx);
4055                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4056                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
4057                             let expr4_0: Type = I32;
4058                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
4059                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
4060                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
4061                             return Some(expr7_0);
4062                         }
4063                         &Opcode::Rotr => {
4064                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4065                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
4066                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
4067                                 if let &InstructionData::UnaryImm {
4068                                     opcode: ref pattern10_0,
4069                                     imm: pattern10_1,
4070                                 } = &pattern9_0
4071                                 {
4072                                     if let &Opcode::Iconst = pattern10_0 {
4073                                         let mut closure12 = || {
4074                                             let expr0_0: Type = I32;
4075                                             return Some(expr0_0);
4076                                         };
4077                                         if let Some(pattern12_0) = closure12() {
4078                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4079                                                 ctx,
4080                                                 pattern10_1,
4081                                                 pattern12_0,
4082                                             ) {
4083                                                 // Rule at src/isa/aarch64/lower.isle line 913.
4084                                                 let expr0_0: Type = I32;
4085                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4086                                                 let expr2_0 = constructor_a64_rotr_imm(
4087                                                     ctx,
4088                                                     expr0_0,
4089                                                     expr1_0,
4090                                                     pattern13_0,
4091                                                 )?;
4092                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4093                                                 return Some(expr3_0);
4094                                             }
4095                                         }
4096                                     }
4097                                 }
4098                             }
4099                             // Rule at src/isa/aarch64/lower.isle line 901.
4100                             let expr0_0: Type = I32;
4101                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4102                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4103                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
4104                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4105                             return Some(expr4_0);
4106                         }
4107                         _ => {}
4108                     }
4109                 }
4110                 &InstructionData::Unary {
4111                     opcode: ref pattern5_0,
4112                     arg: pattern5_1,
4113                 } => {
4114                     if let &Opcode::Popcnt = pattern5_0 {
4115                         // Rule at src/isa/aarch64/lower.isle line 1111.
4116                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4117                         let expr1_0 = ScalarSize::Size32;
4118                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
4119                         let expr3_0 = VectorSize::Size8x8;
4120                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
4121                         let expr5_0 = VectorSize::Size8x8;
4122                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
4123                         let expr7_0: u8 = 0;
4124                         let expr8_0 = VectorSize::Size8x16;
4125                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
4126                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
4127                         return Some(expr10_0);
4128                     }
4129                 }
4130                 _ => {}
4131             }
4132         }
4133         if pattern2_0 == I64 {
4134             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4135             match &pattern4_0 {
4136                 &InstructionData::Binary {
4137                     opcode: ref pattern5_0,
4138                     args: ref pattern5_1,
4139                 } => {
4140                     match pattern5_0 {
4141                         &Opcode::Umulhi => {
4142                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4143                             // Rule at src/isa/aarch64/lower.isle line 371.
4144                             let expr0_0: Type = I64;
4145                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4146                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4147                             let expr3_0 = constructor_umulh(ctx, expr0_0, expr1_0, expr2_0)?;
4148                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4149                             return Some(expr4_0);
4150                         }
4151                         &Opcode::Smulhi => {
4152                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4153                             // Rule at src/isa/aarch64/lower.isle line 359.
4154                             let expr0_0: Type = I64;
4155                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4156                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4157                             let expr3_0 = constructor_smulh(ctx, expr0_0, expr1_0, expr2_0)?;
4158                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4159                             return Some(expr4_0);
4160                         }
4161                         &Opcode::Band => {
4162                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4163                             // Rule at src/isa/aarch64/lower.isle line 592.
4164                             let expr0_0 = ALUOp::And;
4165                             let expr1_0: Type = I64;
4166                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
4167                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4168                             )?;
4169                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4170                             return Some(expr3_0);
4171                         }
4172                         &Opcode::Bor => {
4173                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4174                             // Rule at src/isa/aarch64/lower.isle line 605.
4175                             let expr0_0 = ALUOp::Orr;
4176                             let expr1_0: Type = I64;
4177                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
4178                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4179                             )?;
4180                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4181                             return Some(expr3_0);
4182                         }
4183                         &Opcode::Bxor => {
4184                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4185                             // Rule at src/isa/aarch64/lower.isle line 618.
4186                             let expr0_0 = ALUOp::Eor;
4187                             let expr1_0: Type = I64;
4188                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
4189                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4190                             )?;
4191                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4192                             return Some(expr3_0);
4193                         }
4194                         &Opcode::BandNot => {
4195                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4196                             // Rule at src/isa/aarch64/lower.isle line 631.
4197                             let expr0_0 = ALUOp::AndNot;
4198                             let expr1_0: Type = I64;
4199                             let expr2_0 = constructor_alu_rs_imm_logic(
4200                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4201                             )?;
4202                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4203                             return Some(expr3_0);
4204                         }
4205                         &Opcode::BorNot => {
4206                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4207                             // Rule at src/isa/aarch64/lower.isle line 644.
4208                             let expr0_0 = ALUOp::OrrNot;
4209                             let expr1_0: Type = I64;
4210                             let expr2_0 = constructor_alu_rs_imm_logic(
4211                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4212                             )?;
4213                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4214                             return Some(expr3_0);
4215                         }
4216                         &Opcode::BxorNot => {
4217                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4218                             // Rule at src/isa/aarch64/lower.isle line 654.
4219                             let expr0_0 = ALUOp::EorNot;
4220                             let expr1_0: Type = I64;
4221                             let expr2_0 = constructor_alu_rs_imm_logic(
4222                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4223                             )?;
4224                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4225                             return Some(expr3_0);
4226                         }
4227                         &Opcode::Rotl => {
4228                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4229                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
4230                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
4231                                 if let &InstructionData::UnaryImm {
4232                                     opcode: ref pattern10_0,
4233                                     imm: pattern10_1,
4234                                 } = &pattern9_0
4235                                 {
4236                                     if let &Opcode::Iconst = pattern10_0 {
4237                                         let mut closure12 = || {
4238                                             let expr0_0: Type = I64;
4239                                             return Some(expr0_0);
4240                                         };
4241                                         if let Some(pattern12_0) = closure12() {
4242                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4243                                                 ctx,
4244                                                 pattern10_1,
4245                                                 pattern12_0,
4246                                             ) {
4247                                                 // Rule at src/isa/aarch64/lower.isle line 875.
4248                                                 let expr0_0: Type = I64;
4249                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4250                                                 let expr2_0: Type = I64;
4251                                                 let expr3_0 =
4252                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
4253                                                 let expr4_0 = constructor_a64_rotr_imm(
4254                                                     ctx, expr0_0, expr1_0, expr3_0,
4255                                                 )?;
4256                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
4257                                                 return Some(expr5_0);
4258                                             }
4259                                         }
4260                                     }
4261                                 }
4262                             }
4263                             // Rule at src/isa/aarch64/lower.isle line 866.
4264                             let expr0_0: Type = I64;
4265                             let expr1_0 = C::zero_reg(ctx);
4266                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4267                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
4268                             let expr4_0: Type = I64;
4269                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
4270                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
4271                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
4272                             return Some(expr7_0);
4273                         }
4274                         &Opcode::Rotr => {
4275                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4276                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
4277                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
4278                                 if let &InstructionData::UnaryImm {
4279                                     opcode: ref pattern10_0,
4280                                     imm: pattern10_1,
4281                                 } = &pattern9_0
4282                                 {
4283                                     if let &Opcode::Iconst = pattern10_0 {
4284                                         let mut closure12 = || {
4285                                             let expr0_0: Type = I64;
4286                                             return Some(expr0_0);
4287                                         };
4288                                         if let Some(pattern12_0) = closure12() {
4289                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4290                                                 ctx,
4291                                                 pattern10_1,
4292                                                 pattern12_0,
4293                                             ) {
4294                                                 // Rule at src/isa/aarch64/lower.isle line 917.
4295                                                 let expr0_0: Type = I64;
4296                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4297                                                 let expr2_0 = constructor_a64_rotr_imm(
4298                                                     ctx,
4299                                                     expr0_0,
4300                                                     expr1_0,
4301                                                     pattern13_0,
4302                                                 )?;
4303                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4304                                                 return Some(expr3_0);
4305                                             }
4306                                         }
4307                                     }
4308                                 }
4309                             }
4310                             // Rule at src/isa/aarch64/lower.isle line 905.
4311                             let expr0_0: Type = I64;
4312                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4313                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4314                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
4315                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4316                             return Some(expr4_0);
4317                         }
4318                         &Opcode::Ishl => {
4319                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4320                             // Rule at src/isa/aarch64/lower.isle line 666.
4321                             let expr0_0 = ALUOp::Lsl;
4322                             let expr1_0: Type = I64;
4323                             let expr2_0 = C::put_in_reg(ctx, pattern7_0);
4324                             let expr3_0 =
4325                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4326                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4327                             return Some(expr4_0);
4328                         }
4329                         &Opcode::Ushr => {
4330                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4331                             // Rule at src/isa/aarch64/lower.isle line 750.
4332                             let expr0_0 = ALUOp::Lsr;
4333                             let expr1_0: Type = I64;
4334                             let expr2_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
4335                             let expr3_0 =
4336                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4337                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4338                             return Some(expr4_0);
4339                         }
4340                         &Opcode::Sshr => {
4341                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4342                             // Rule at src/isa/aarch64/lower.isle line 797.
4343                             let expr0_0 = ALUOp::Asr;
4344                             let expr1_0: Type = I64;
4345                             let expr2_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
4346                             let expr3_0 =
4347                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4348                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4349                             return Some(expr4_0);
4350                         }
4351                         _ => {}
4352                     }
4353                 }
4354                 &InstructionData::Unary {
4355                     opcode: ref pattern5_0,
4356                     arg: pattern5_1,
4357                 } => {
4358                     if let &Opcode::Popcnt = pattern5_0 {
4359                         // Rule at src/isa/aarch64/lower.isle line 1117.
4360                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4361                         let expr1_0 = ScalarSize::Size64;
4362                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
4363                         let expr3_0 = VectorSize::Size8x8;
4364                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
4365                         let expr5_0 = VectorSize::Size8x8;
4366                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
4367                         let expr7_0: u8 = 0;
4368                         let expr8_0 = VectorSize::Size8x16;
4369                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
4370                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
4371                         return Some(expr10_0);
4372                     }
4373                 }
4374                 _ => {}
4375             }
4376         }
4377         if pattern2_0 == I128 {
4378             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4379             match &pattern4_0 {
4380                 &InstructionData::Binary {
4381                     opcode: ref pattern5_0,
4382                     args: ref pattern5_1,
4383                 } => {
4384                     match pattern5_0 {
4385                         &Opcode::Iadd => {
4386                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4387                             // Rule at src/isa/aarch64/lower.isle line 83.
4388                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4389                             let expr1_0: usize = 0;
4390                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4391                             let expr3_0: usize = 1;
4392                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4393                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4394                             let expr6_0: usize = 0;
4395                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4396                             let expr8_0: usize = 1;
4397                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4398                             let expr10_0: Type = I64;
4399                             let expr11_0 =
4400                                 constructor_add_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4401                             let expr12_0: Type = I64;
4402                             let expr13_0 = constructor_adc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4403                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4404                             let expr15_0 = C::output(ctx, expr14_0);
4405                             return Some(expr15_0);
4406                         }
4407                         &Opcode::Isub => {
4408                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4409                             // Rule at src/isa/aarch64/lower.isle line 133.
4410                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4411                             let expr1_0: usize = 0;
4412                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4413                             let expr3_0: usize = 1;
4414                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4415                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4416                             let expr6_0: usize = 0;
4417                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4418                             let expr8_0: usize = 1;
4419                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4420                             let expr10_0: Type = I64;
4421                             let expr11_0 =
4422                                 constructor_sub_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4423                             let expr12_0: Type = I64;
4424                             let expr13_0 = constructor_sbc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4425                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4426                             let expr15_0 = C::output(ctx, expr14_0);
4427                             return Some(expr15_0);
4428                         }
4429                         &Opcode::Imul => {
4430                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4431                             // Rule at src/isa/aarch64/lower.isle line 187.
4432                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4433                             let expr1_0: usize = 0;
4434                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4435                             let expr3_0: usize = 1;
4436                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4437                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4438                             let expr6_0: usize = 0;
4439                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4440                             let expr8_0: usize = 1;
4441                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4442                             let expr10_0: Type = I64;
4443                             let expr11_0 = constructor_umulh(ctx, expr10_0, expr2_0, expr7_0)?;
4444                             let expr12_0: Type = I64;
4445                             let expr13_0 =
4446                                 constructor_madd(ctx, expr12_0, expr2_0, expr9_0, expr11_0)?;
4447                             let expr14_0: Type = I64;
4448                             let expr15_0 =
4449                                 constructor_madd(ctx, expr14_0, expr4_0, expr7_0, expr13_0)?;
4450                             let expr16_0: Type = I64;
4451                             let expr17_0 = C::zero_reg(ctx);
4452                             let expr18_0 =
4453                                 constructor_madd(ctx, expr16_0, expr2_0, expr7_0, expr17_0)?;
4454                             let expr19_0 = C::value_regs(ctx, expr18_0, expr15_0);
4455                             let expr20_0 = C::output(ctx, expr19_0);
4456                             return Some(expr20_0);
4457                         }
4458                         &Opcode::Band => {
4459                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4460                             // Rule at src/isa/aarch64/lower.isle line 595.
4461                             let expr0_0 = ALUOp::And;
4462                             let expr1_0: Type = I64;
4463                             let expr2_0 = constructor_i128_alu_bitop(
4464                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4465                             )?;
4466                             let expr3_0 = C::output(ctx, expr2_0);
4467                             return Some(expr3_0);
4468                         }
4469                         &Opcode::Bor => {
4470                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4471                             // Rule at src/isa/aarch64/lower.isle line 608.
4472                             let expr0_0 = ALUOp::Orr;
4473                             let expr1_0: Type = I64;
4474                             let expr2_0 = constructor_i128_alu_bitop(
4475                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4476                             )?;
4477                             let expr3_0 = C::output(ctx, expr2_0);
4478                             return Some(expr3_0);
4479                         }
4480                         &Opcode::Bxor => {
4481                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4482                             // Rule at src/isa/aarch64/lower.isle line 621.
4483                             let expr0_0 = ALUOp::Eor;
4484                             let expr1_0: Type = I64;
4485                             let expr2_0 = constructor_i128_alu_bitop(
4486                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4487                             )?;
4488                             let expr3_0 = C::output(ctx, expr2_0);
4489                             return Some(expr3_0);
4490                         }
4491                         &Opcode::BandNot => {
4492                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4493                             // Rule at src/isa/aarch64/lower.isle line 634.
4494                             let expr0_0 = ALUOp::AndNot;
4495                             let expr1_0: Type = I64;
4496                             let expr2_0 = constructor_i128_alu_bitop(
4497                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4498                             )?;
4499                             let expr3_0 = C::output(ctx, expr2_0);
4500                             return Some(expr3_0);
4501                         }
4502                         &Opcode::BorNot => {
4503                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4504                             // Rule at src/isa/aarch64/lower.isle line 647.
4505                             let expr0_0 = ALUOp::OrrNot;
4506                             let expr1_0: Type = I64;
4507                             let expr2_0 = constructor_i128_alu_bitop(
4508                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4509                             )?;
4510                             let expr3_0 = C::output(ctx, expr2_0);
4511                             return Some(expr3_0);
4512                         }
4513                         &Opcode::BxorNot => {
4514                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4515                             // Rule at src/isa/aarch64/lower.isle line 657.
4516                             let expr0_0 = ALUOp::EorNot;
4517                             let expr1_0: Type = I64;
4518                             let expr2_0 = constructor_i128_alu_bitop(
4519                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4520                             )?;
4521                             let expr3_0 = C::output(ctx, expr2_0);
4522                             return Some(expr3_0);
4523                         }
4524                         &Opcode::Rotl => {
4525                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4526                             // Rule at src/isa/aarch64/lower.isle line 884.
4527                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4528                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4529                             let expr2_0: usize = 0;
4530                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4531                             let expr4_0: Type = I64;
4532                             let expr5_0: Type = I64;
4533                             let expr6_0: u64 = 128;
4534                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4535                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4536                             let expr9_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4537                             let expr10_0 = constructor_lower_ushr128(ctx, expr0_0, expr8_0)?;
4538                             let expr11_0: Type = I64;
4539                             let expr12_0: usize = 0;
4540                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4541                             let expr14_0: usize = 0;
4542                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4543                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4544                             let expr17_0: Type = I64;
4545                             let expr18_0: usize = 1;
4546                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4547                             let expr20_0: usize = 1;
4548                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4549                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4550                             let expr23_0 = C::value_regs(ctx, expr16_0, expr22_0);
4551                             let expr24_0 = C::output(ctx, expr23_0);
4552                             return Some(expr24_0);
4553                         }
4554                         &Opcode::Rotr => {
4555                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4556                             // Rule at src/isa/aarch64/lower.isle line 965.
4557                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4558                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4559                             let expr2_0: usize = 0;
4560                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4561                             let expr4_0: Type = I64;
4562                             let expr5_0: Type = I64;
4563                             let expr6_0: u64 = 128;
4564                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4565                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4566                             let expr9_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4567                             let expr10_0 = constructor_lower_shl128(ctx, expr0_0, expr8_0)?;
4568                             let expr11_0: Type = I64;
4569                             let expr12_0: usize = 1;
4570                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4571                             let expr14_0: usize = 1;
4572                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4573                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4574                             let expr17_0: Type = I64;
4575                             let expr18_0: usize = 0;
4576                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4577                             let expr20_0: usize = 0;
4578                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4579                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4580                             let expr23_0 = C::value_regs(ctx, expr22_0, expr16_0);
4581                             let expr24_0 = C::output(ctx, expr23_0);
4582                             return Some(expr24_0);
4583                         }
4584                         &Opcode::Ishl => {
4585                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4586                             // Rule at src/isa/aarch64/lower.isle line 670.
4587                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4588                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4589                             let expr2_0: usize = 0;
4590                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4591                             let expr4_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4592                             let expr5_0 = C::output(ctx, expr4_0);
4593                             return Some(expr5_0);
4594                         }
4595                         &Opcode::Ushr => {
4596                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4597                             // Rule at src/isa/aarch64/lower.isle line 754.
4598                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4599                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4600                             let expr2_0: usize = 0;
4601                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4602                             let expr4_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4603                             let expr5_0 = C::output(ctx, expr4_0);
4604                             return Some(expr5_0);
4605                         }
4606                         &Opcode::Sshr => {
4607                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4608                             // Rule at src/isa/aarch64/lower.isle line 801.
4609                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4610                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4611                             let expr2_0: usize = 0;
4612                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4613                             let expr4_0 = constructor_lower_sshr128(ctx, expr0_0, expr3_0)?;
4614                             let expr5_0 = C::output(ctx, expr4_0);
4615                             return Some(expr5_0);
4616                         }
4617                         _ => {}
4618                     }
4619                 }
4620                 &InstructionData::Unary {
4621                     opcode: ref pattern5_0,
4622                     arg: pattern5_1,
4623                 } => {
4624                     match pattern5_0 {
4625                         &Opcode::Bnot => {
4626                             // Rule at src/isa/aarch64/lower.isle line 575.
4627                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4628                             let expr1_0: usize = 0;
4629                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4630                             let expr3_0: usize = 1;
4631                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4632                             let expr5_0: Type = I64;
4633                             let expr6_0 = C::zero_reg(ctx);
4634                             let expr7_0 = constructor_orr_not(ctx, expr5_0, expr6_0, expr2_0)?;
4635                             let expr8_0: Type = I64;
4636                             let expr9_0 = C::zero_reg(ctx);
4637                             let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, expr4_0)?;
4638                             let expr11_0 = C::value_regs(ctx, expr7_0, expr10_0);
4639                             let expr12_0 = C::output(ctx, expr11_0);
4640                             return Some(expr12_0);
4641                         }
4642                         &Opcode::Bitrev => {
4643                             // Rule at src/isa/aarch64/lower.isle line 989.
4644                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4645                             let expr1_0: Type = I64;
4646                             let expr2_0: usize = 0;
4647                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4648                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4649                             let expr5_0: Type = I64;
4650                             let expr6_0: usize = 1;
4651                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4652                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4653                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4654                             let expr10_0 = C::output(ctx, expr9_0);
4655                             return Some(expr10_0);
4656                         }
4657                         &Opcode::Clz => {
4658                             // Rule at src/isa/aarch64/lower.isle line 1007.
4659                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4660                             let expr1_0 = constructor_lower_clz128(ctx, expr0_0)?;
4661                             let expr2_0 = C::output(ctx, expr1_0);
4662                             return Some(expr2_0);
4663                         }
4664                         &Opcode::Cls => {
4665                             // Rule at src/isa/aarch64/lower.isle line 1063.
4666                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4667                             let expr1_0: usize = 0;
4668                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4669                             let expr3_0: usize = 1;
4670                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4671                             let expr5_0: Type = I64;
4672                             let expr6_0 = constructor_a64_cls(ctx, expr5_0, expr2_0)?;
4673                             let expr7_0: Type = I64;
4674                             let expr8_0 = constructor_a64_cls(ctx, expr7_0, expr4_0)?;
4675                             let expr9_0: Type = I64;
4676                             let expr10_0 = constructor_eon(ctx, expr9_0, expr4_0, expr2_0)?;
4677                             let expr11_0: Type = I64;
4678                             let expr12_0: u8 = 63;
4679                             let expr13_0 = C::imm_shift_from_u8(ctx, expr12_0);
4680                             let expr14_0 = constructor_lsr_imm(ctx, expr11_0, expr10_0, expr13_0)?;
4681                             let expr15_0: Type = I64;
4682                             let expr16_0 =
4683                                 constructor_madd(ctx, expr15_0, expr6_0, expr14_0, expr14_0)?;
4684                             let expr17_0: u8 = 63;
4685                             let expr18_0 = C::u8_into_imm12(ctx, expr17_0);
4686                             let expr19_0 = constructor_cmp64_imm(ctx, expr8_0, expr18_0)?;
4687                             let expr20_0 = Cond::Eq;
4688                             let expr21_0 = C::zero_reg(ctx);
4689                             let expr22_0 = constructor_csel(ctx, &expr20_0, expr16_0, expr21_0)?;
4690                             let expr23_0 = constructor_with_flags_reg(ctx, &expr19_0, &expr22_0)?;
4691                             let expr24_0: Type = I64;
4692                             let expr25_0 = constructor_add(ctx, expr24_0, expr23_0, expr8_0)?;
4693                             let expr26_0: Type = I64;
4694                             let expr27_0: u64 = 0;
4695                             let expr28_0 = constructor_imm(ctx, expr26_0, expr27_0)?;
4696                             let expr29_0 = C::value_regs(ctx, expr25_0, expr28_0);
4697                             let expr30_0 = C::output(ctx, expr29_0);
4698                             return Some(expr30_0);
4699                         }
4700                         &Opcode::Ctz => {
4701                             // Rule at src/isa/aarch64/lower.isle line 1037.
4702                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4703                             let expr1_0: Type = I64;
4704                             let expr2_0: usize = 0;
4705                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4706                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4707                             let expr5_0: Type = I64;
4708                             let expr6_0: usize = 1;
4709                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4710                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4711                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4712                             let expr10_0 = constructor_lower_clz128(ctx, expr9_0)?;
4713                             let expr11_0 = C::output(ctx, expr10_0);
4714                             return Some(expr11_0);
4715                         }
4716                         &Opcode::Popcnt => {
4717                             // Rule at src/isa/aarch64/lower.isle line 1123.
4718                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4719                             let expr1_0: usize = 0;
4720                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4721                             let expr3_0 = ScalarSize::Size64;
4722                             let expr4_0 = constructor_mov_to_fpu(ctx, expr2_0, &expr3_0)?;
4723                             let expr5_0: usize = 1;
4724                             let expr6_0 = C::value_regs_get(ctx, expr0_0, expr5_0);
4725                             let expr7_0: u8 = 1;
4726                             let expr8_0 = VectorSize::Size64x2;
4727                             let expr9_0 =
4728                                 constructor_mov_to_vec(ctx, expr4_0, expr6_0, expr7_0, &expr8_0)?;
4729                             let expr10_0 = VectorSize::Size8x16;
4730                             let expr11_0 = constructor_vec_cnt(ctx, expr9_0, &expr10_0)?;
4731                             let expr12_0 = VectorSize::Size8x16;
4732                             let expr13_0 = constructor_addv(ctx, expr11_0, &expr12_0)?;
4733                             let expr14_0: u8 = 0;
4734                             let expr15_0 = VectorSize::Size8x16;
4735                             let expr16_0 =
4736                                 constructor_mov_from_vec(ctx, expr13_0, expr14_0, &expr15_0)?;
4737                             let expr17_0: Type = I64;
4738                             let expr18_0: u64 = 0;
4739                             let expr19_0 = constructor_imm(ctx, expr17_0, expr18_0)?;
4740                             let expr20_0 = C::value_regs(ctx, expr16_0, expr19_0);
4741                             let expr21_0 = C::output(ctx, expr20_0);
4742                             return Some(expr21_0);
4743                         }
4744                         &Opcode::Uextend => {
4745                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4746                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4747                                 if let &InstructionData::BinaryImm8 {
4748                                     opcode: ref pattern9_0,
4749                                     arg: pattern9_1,
4750                                     imm: pattern9_2,
4751                                 } = &pattern8_0
4752                                 {
4753                                     if let &Opcode::Extractlane = pattern9_0 {
4754                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4755                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
4756                                         // Rule at src/isa/aarch64/lower.isle line 505.
4757                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4758                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
4759                                         let expr2_0 = constructor_mov_from_vec(
4760                                             ctx,
4761                                             expr0_0,
4762                                             pattern12_0,
4763                                             &expr1_0,
4764                                         )?;
4765                                         let expr3_0: Type = I64;
4766                                         let expr4_0: u64 = 0;
4767                                         let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
4768                                         let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
4769                                         let expr7_0 = C::output(ctx, expr6_0);
4770                                         return Some(expr7_0);
4771                                     }
4772                                 }
4773                             }
4774                             // Rule at src/isa/aarch64/lower.isle line 500.
4775                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
4776                             let expr1_0: Type = I64;
4777                             let expr2_0: u64 = 0;
4778                             let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
4779                             let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
4780                             let expr5_0 = C::output(ctx, expr4_0);
4781                             return Some(expr5_0);
4782                         }
4783                         &Opcode::Sextend => {
4784                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4785                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4786                                 if let &InstructionData::BinaryImm8 {
4787                                     opcode: ref pattern9_0,
4788                                     arg: pattern9_1,
4789                                     imm: pattern9_2,
4790                                 } = &pattern8_0
4791                                 {
4792                                     if let &Opcode::Extractlane = pattern9_0 {
4793                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4794                                         if pattern11_0 == I64X2 {
4795                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4796                                             // Rule at src/isa/aarch64/lower.isle line 549.
4797                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4798                                             let expr1_0 = VectorSize::Size64x2;
4799                                             let expr2_0 = constructor_mov_from_vec(
4800                                                 ctx,
4801                                                 expr0_0,
4802                                                 pattern13_0,
4803                                                 &expr1_0,
4804                                             )?;
4805                                             let expr3_0: Type = I64;
4806                                             let expr4_0: u8 = 63;
4807                                             let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
4808                                             let expr6_0 = constructor_asr_imm(
4809                                                 ctx, expr3_0, expr2_0, expr5_0,
4810                                             )?;
4811                                             let expr7_0 = C::value_regs(ctx, expr2_0, expr6_0);
4812                                             let expr8_0 = C::output(ctx, expr7_0);
4813                                             return Some(expr8_0);
4814                                         }
4815                                         if let Some(()) = C::not_i64x2(ctx, pattern11_0) {
4816                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4817                                             // Rule at src/isa/aarch64/lower.isle line 538.
4818                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4819                                             let expr1_0 =
4820                                                 constructor_vector_size(ctx, pattern11_0)?;
4821                                             let expr2_0: Type = I64;
4822                                             let expr3_0 = constructor_size_from_ty(ctx, expr2_0)?;
4823                                             let expr4_0 = constructor_mov_from_vec_signed(
4824                                                 ctx,
4825                                                 expr0_0,
4826                                                 pattern13_0,
4827                                                 &expr1_0,
4828                                                 &expr3_0,
4829                                             )?;
4830                                             let expr5_0: Type = I64;
4831                                             let expr6_0: u8 = 63;
4832                                             let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
4833                                             let expr8_0 = constructor_asr_imm(
4834                                                 ctx, expr5_0, expr4_0, expr7_0,
4835                                             )?;
4836                                             let expr9_0 = C::value_regs(ctx, expr4_0, expr8_0);
4837                                             let expr10_0 = C::output(ctx, expr9_0);
4838                                             return Some(expr10_0);
4839                                         }
4840                                     }
4841                                 }
4842                             }
4843                             // Rule at src/isa/aarch64/lower.isle line 528.
4844                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
4845                             let expr1_0: Type = I64;
4846                             let expr2_0: u8 = 63;
4847                             let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0);
4848                             let expr4_0 = constructor_asr_imm(ctx, expr1_0, expr0_0, expr3_0)?;
4849                             let expr5_0 = C::value_regs(ctx, expr0_0, expr4_0);
4850                             let expr6_0 = C::output(ctx, expr5_0);
4851                             return Some(expr6_0);
4852                         }
4853                         _ => {}
4854                     }
4855                 }
4856                 _ => {}
4857             }
4858         }
4859         if pattern2_0 == I8X16 {
4860             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4861             if let &InstructionData::Unary {
4862                 opcode: ref pattern5_0,
4863                 arg: pattern5_1,
4864             } = &pattern4_0
4865             {
4866                 if let &Opcode::Popcnt = pattern5_0 {
4867                     // Rule at src/isa/aarch64/lower.isle line 1131.
4868                     let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4869                     let expr1_0 = VectorSize::Size8x16;
4870                     let expr2_0 = constructor_vec_cnt(ctx, expr0_0, &expr1_0)?;
4871                     let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4872                     return Some(expr3_0);
4873                 }
4874             }
4875         }
4876         if pattern2_0 == I16X8 {
4877             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4878             if let &InstructionData::Binary {
4879                 opcode: ref pattern5_0,
4880                 args: ref pattern5_1,
4881             } = &pattern4_0
4882             {
4883                 if let &Opcode::Imul = pattern5_0 {
4884                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4885                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4886                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4887                         if let &InstructionData::Unary {
4888                             opcode: ref pattern10_0,
4889                             arg: pattern10_1,
4890                         } = &pattern9_0
4891                         {
4892                             match pattern10_0 {
4893                                 &Opcode::SwidenLow => {
4894                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4895                                     if pattern12_0 == I8X16 {
4896                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4897                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4898                                             if let &InstructionData::Unary {
4899                                                 opcode: ref pattern16_0,
4900                                                 arg: pattern16_1,
4901                                             } = &pattern15_0
4902                                             {
4903                                                 if let &Opcode::SwidenLow = pattern16_0 {
4904                                                     let pattern18_0 =
4905                                                         C::value_type(ctx, pattern16_1);
4906                                                     if pattern18_0 == I8X16 {
4907                                                         // Rule at src/isa/aarch64/lower.isle line 286.
4908                                                         let expr0_0 =
4909                                                             C::put_in_reg(ctx, pattern10_1);
4910                                                         let expr1_0 =
4911                                                             C::put_in_reg(ctx, pattern16_1);
4912                                                         let expr2_0: bool = false;
4913                                                         let expr3_0 = constructor_smull8(
4914                                                             ctx, expr0_0, expr1_0, expr2_0,
4915                                                         )?;
4916                                                         let expr4_0 =
4917                                                             constructor_output_reg(ctx, expr3_0)?;
4918                                                         return Some(expr4_0);
4919                                                     }
4920                                                 }
4921                                             }
4922                                         }
4923                                     }
4924                                 }
4925                                 &Opcode::SwidenHigh => {
4926                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4927                                     if pattern12_0 == I8X16 {
4928                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4929                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4930                                             if let &InstructionData::Unary {
4931                                                 opcode: ref pattern16_0,
4932                                                 arg: pattern16_1,
4933                                             } = &pattern15_0
4934                                             {
4935                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4936                                                     let pattern18_0 =
4937                                                         C::value_type(ctx, pattern16_1);
4938                                                     if pattern18_0 == I8X16 {
4939                                                         // Rule at src/isa/aarch64/lower.isle line 292.
4940                                                         let expr0_0 =
4941                                                             C::put_in_reg(ctx, pattern10_1);
4942                                                         let expr1_0 =
4943                                                             C::put_in_reg(ctx, pattern16_1);
4944                                                         let expr2_0: bool = true;
4945                                                         let expr3_0 = constructor_smull8(
4946                                                             ctx, expr0_0, expr1_0, expr2_0,
4947                                                         )?;
4948                                                         let expr4_0 =
4949                                                             constructor_output_reg(ctx, expr3_0)?;
4950                                                         return Some(expr4_0);
4951                                                     }
4952                                                 }
4953                                             }
4954                                         }
4955                                     }
4956                                 }
4957                                 &Opcode::UwidenLow => {
4958                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4959                                     if pattern12_0 == I8X16 {
4960                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4961                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4962                                             if let &InstructionData::Unary {
4963                                                 opcode: ref pattern16_0,
4964                                                 arg: pattern16_1,
4965                                             } = &pattern15_0
4966                                             {
4967                                                 if let &Opcode::UwidenLow = pattern16_0 {
4968                                                     let pattern18_0 =
4969                                                         C::value_type(ctx, pattern16_1);
4970                                                     if pattern18_0 == I8X16 {
4971                                                         // Rule at src/isa/aarch64/lower.isle line 298.
4972                                                         let expr0_0 =
4973                                                             C::put_in_reg(ctx, pattern10_1);
4974                                                         let expr1_0 =
4975                                                             C::put_in_reg(ctx, pattern16_1);
4976                                                         let expr2_0: bool = false;
4977                                                         let expr3_0 = constructor_umull8(
4978                                                             ctx, expr0_0, expr1_0, expr2_0,
4979                                                         )?;
4980                                                         let expr4_0 =
4981                                                             constructor_output_reg(ctx, expr3_0)?;
4982                                                         return Some(expr4_0);
4983                                                     }
4984                                                 }
4985                                             }
4986                                         }
4987                                     }
4988                                 }
4989                                 &Opcode::UwidenHigh => {
4990                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4991                                     if pattern12_0 == I8X16 {
4992                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4993                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4994                                             if let &InstructionData::Unary {
4995                                                 opcode: ref pattern16_0,
4996                                                 arg: pattern16_1,
4997                                             } = &pattern15_0
4998                                             {
4999                                                 if let &Opcode::UwidenHigh = pattern16_0 {
5000                                                     let pattern18_0 =
5001                                                         C::value_type(ctx, pattern16_1);
5002                                                     if pattern18_0 == I8X16 {
5003                                                         // Rule at src/isa/aarch64/lower.isle line 304.
5004                                                         let expr0_0 =
5005                                                             C::put_in_reg(ctx, pattern10_1);
5006                                                         let expr1_0 =
5007                                                             C::put_in_reg(ctx, pattern16_1);
5008                                                         let expr2_0: bool = true;
5009                                                         let expr3_0 = constructor_umull8(
5010                                                             ctx, expr0_0, expr1_0, expr2_0,
5011                                                         )?;
5012                                                         let expr4_0 =
5013                                                             constructor_output_reg(ctx, expr3_0)?;
5014                                                         return Some(expr4_0);
5015                                                     }
5016                                                 }
5017                                             }
5018                                         }
5019                                     }
5020                                 }
5021                                 _ => {}
5022                             }
5023                         }
5024                     }
5025                 }
5026             }
5027         }
5028         if pattern2_0 == I32X4 {
5029             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5030             if let &InstructionData::Binary {
5031                 opcode: ref pattern5_0,
5032                 args: ref pattern5_1,
5033             } = &pattern4_0
5034             {
5035                 if let &Opcode::Imul = pattern5_0 {
5036                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5037                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5038                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
5039                         if let &InstructionData::Unary {
5040                             opcode: ref pattern10_0,
5041                             arg: pattern10_1,
5042                         } = &pattern9_0
5043                         {
5044                             match pattern10_0 {
5045                                 &Opcode::SwidenLow => {
5046                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5047                                     if pattern12_0 == I16X8 {
5048                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5049                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5050                                             if let &InstructionData::Unary {
5051                                                 opcode: ref pattern16_0,
5052                                                 arg: pattern16_1,
5053                                             } = &pattern15_0
5054                                             {
5055                                                 if let &Opcode::SwidenLow = pattern16_0 {
5056                                                     let pattern18_0 =
5057                                                         C::value_type(ctx, pattern16_1);
5058                                                     if pattern18_0 == I16X8 {
5059                                                         // Rule at src/isa/aarch64/lower.isle line 310.
5060                                                         let expr0_0 =
5061                                                             C::put_in_reg(ctx, pattern10_1);
5062                                                         let expr1_0 =
5063                                                             C::put_in_reg(ctx, pattern16_1);
5064                                                         let expr2_0: bool = false;
5065                                                         let expr3_0 = constructor_smull16(
5066                                                             ctx, expr0_0, expr1_0, expr2_0,
5067                                                         )?;
5068                                                         let expr4_0 =
5069                                                             constructor_output_reg(ctx, expr3_0)?;
5070                                                         return Some(expr4_0);
5071                                                     }
5072                                                 }
5073                                             }
5074                                         }
5075                                     }
5076                                 }
5077                                 &Opcode::SwidenHigh => {
5078                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5079                                     if pattern12_0 == I16X8 {
5080                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5081                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5082                                             if let &InstructionData::Unary {
5083                                                 opcode: ref pattern16_0,
5084                                                 arg: pattern16_1,
5085                                             } = &pattern15_0
5086                                             {
5087                                                 if let &Opcode::SwidenHigh = pattern16_0 {
5088                                                     let pattern18_0 =
5089                                                         C::value_type(ctx, pattern16_1);
5090                                                     if pattern18_0 == I16X8 {
5091                                                         // Rule at src/isa/aarch64/lower.isle line 316.
5092                                                         let expr0_0 =
5093                                                             C::put_in_reg(ctx, pattern10_1);
5094                                                         let expr1_0 =
5095                                                             C::put_in_reg(ctx, pattern16_1);
5096                                                         let expr2_0: bool = true;
5097                                                         let expr3_0 = constructor_smull16(
5098                                                             ctx, expr0_0, expr1_0, expr2_0,
5099                                                         )?;
5100                                                         let expr4_0 =
5101                                                             constructor_output_reg(ctx, expr3_0)?;
5102                                                         return Some(expr4_0);
5103                                                     }
5104                                                 }
5105                                             }
5106                                         }
5107                                     }
5108                                 }
5109                                 &Opcode::UwidenLow => {
5110                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5111                                     if pattern12_0 == I16X8 {
5112                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5113                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5114                                             if let &InstructionData::Unary {
5115                                                 opcode: ref pattern16_0,
5116                                                 arg: pattern16_1,
5117                                             } = &pattern15_0
5118                                             {
5119                                                 if let &Opcode::UwidenLow = pattern16_0 {
5120                                                     let pattern18_0 =
5121                                                         C::value_type(ctx, pattern16_1);
5122                                                     if pattern18_0 == I16X8 {
5123                                                         // Rule at src/isa/aarch64/lower.isle line 322.
5124                                                         let expr0_0 =
5125                                                             C::put_in_reg(ctx, pattern10_1);
5126                                                         let expr1_0 =
5127                                                             C::put_in_reg(ctx, pattern16_1);
5128                                                         let expr2_0: bool = false;
5129                                                         let expr3_0 = constructor_umull16(
5130                                                             ctx, expr0_0, expr1_0, expr2_0,
5131                                                         )?;
5132                                                         let expr4_0 =
5133                                                             constructor_output_reg(ctx, expr3_0)?;
5134                                                         return Some(expr4_0);
5135                                                     }
5136                                                 }
5137                                             }
5138                                         }
5139                                     }
5140                                 }
5141                                 &Opcode::UwidenHigh => {
5142                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5143                                     if pattern12_0 == I16X8 {
5144                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5145                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5146                                             if let &InstructionData::Unary {
5147                                                 opcode: ref pattern16_0,
5148                                                 arg: pattern16_1,
5149                                             } = &pattern15_0
5150                                             {
5151                                                 if let &Opcode::UwidenHigh = pattern16_0 {
5152                                                     let pattern18_0 =
5153                                                         C::value_type(ctx, pattern16_1);
5154                                                     if pattern18_0 == I16X8 {
5155                                                         // Rule at src/isa/aarch64/lower.isle line 328.
5156                                                         let expr0_0 =
5157                                                             C::put_in_reg(ctx, pattern10_1);
5158                                                         let expr1_0 =
5159                                                             C::put_in_reg(ctx, pattern16_1);
5160                                                         let expr2_0: bool = true;
5161                                                         let expr3_0 = constructor_umull16(
5162                                                             ctx, expr0_0, expr1_0, expr2_0,
5163                                                         )?;
5164                                                         let expr4_0 =
5165                                                             constructor_output_reg(ctx, expr3_0)?;
5166                                                         return Some(expr4_0);
5167                                                     }
5168                                                 }
5169                                             }
5170                                         }
5171                                     }
5172                                 }
5173                                 _ => {}
5174                             }
5175                         }
5176                     }
5177                 }
5178             }
5179         }
5180         if pattern2_0 == I64X2 {
5181             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5182             if let &InstructionData::Binary {
5183                 opcode: ref pattern5_0,
5184                 args: ref pattern5_1,
5185             } = &pattern4_0
5186             {
5187                 if let &Opcode::Imul = pattern5_0 {
5188                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5189                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5190                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
5191                         if let &InstructionData::Unary {
5192                             opcode: ref pattern10_0,
5193                             arg: pattern10_1,
5194                         } = &pattern9_0
5195                         {
5196                             match pattern10_0 {
5197                                 &Opcode::SwidenLow => {
5198                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5199                                     if pattern12_0 == I32X4 {
5200                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5201                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5202                                             if let &InstructionData::Unary {
5203                                                 opcode: ref pattern16_0,
5204                                                 arg: pattern16_1,
5205                                             } = &pattern15_0
5206                                             {
5207                                                 if let &Opcode::SwidenLow = pattern16_0 {
5208                                                     let pattern18_0 =
5209                                                         C::value_type(ctx, pattern16_1);
5210                                                     if pattern18_0 == I32X4 {
5211                                                         // Rule at src/isa/aarch64/lower.isle line 334.
5212                                                         let expr0_0 =
5213                                                             C::put_in_reg(ctx, pattern10_1);
5214                                                         let expr1_0 =
5215                                                             C::put_in_reg(ctx, pattern16_1);
5216                                                         let expr2_0: bool = false;
5217                                                         let expr3_0 = constructor_smull32(
5218                                                             ctx, expr0_0, expr1_0, expr2_0,
5219                                                         )?;
5220                                                         let expr4_0 =
5221                                                             constructor_output_reg(ctx, expr3_0)?;
5222                                                         return Some(expr4_0);
5223                                                     }
5224                                                 }
5225                                             }
5226                                         }
5227                                     }
5228                                 }
5229                                 &Opcode::SwidenHigh => {
5230                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5231                                     if pattern12_0 == I32X4 {
5232                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5233                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5234                                             if let &InstructionData::Unary {
5235                                                 opcode: ref pattern16_0,
5236                                                 arg: pattern16_1,
5237                                             } = &pattern15_0
5238                                             {
5239                                                 if let &Opcode::SwidenHigh = pattern16_0 {
5240                                                     let pattern18_0 =
5241                                                         C::value_type(ctx, pattern16_1);
5242                                                     if pattern18_0 == I32X4 {
5243                                                         // Rule at src/isa/aarch64/lower.isle line 340.
5244                                                         let expr0_0 =
5245                                                             C::put_in_reg(ctx, pattern10_1);
5246                                                         let expr1_0 =
5247                                                             C::put_in_reg(ctx, pattern16_1);
5248                                                         let expr2_0: bool = true;
5249                                                         let expr3_0 = constructor_smull32(
5250                                                             ctx, expr0_0, expr1_0, expr2_0,
5251                                                         )?;
5252                                                         let expr4_0 =
5253                                                             constructor_output_reg(ctx, expr3_0)?;
5254                                                         return Some(expr4_0);
5255                                                     }
5256                                                 }
5257                                             }
5258                                         }
5259                                     }
5260                                 }
5261                                 &Opcode::UwidenLow => {
5262                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5263                                     if pattern12_0 == I32X4 {
5264                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5265                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5266                                             if let &InstructionData::Unary {
5267                                                 opcode: ref pattern16_0,
5268                                                 arg: pattern16_1,
5269                                             } = &pattern15_0
5270                                             {
5271                                                 if let &Opcode::UwidenLow = pattern16_0 {
5272                                                     let pattern18_0 =
5273                                                         C::value_type(ctx, pattern16_1);
5274                                                     if pattern18_0 == I32X4 {
5275                                                         // Rule at src/isa/aarch64/lower.isle line 346.
5276                                                         let expr0_0 =
5277                                                             C::put_in_reg(ctx, pattern10_1);
5278                                                         let expr1_0 =
5279                                                             C::put_in_reg(ctx, pattern16_1);
5280                                                         let expr2_0: bool = false;
5281                                                         let expr3_0 = constructor_umull32(
5282                                                             ctx, expr0_0, expr1_0, expr2_0,
5283                                                         )?;
5284                                                         let expr4_0 =
5285                                                             constructor_output_reg(ctx, expr3_0)?;
5286                                                         return Some(expr4_0);
5287                                                     }
5288                                                 }
5289                                             }
5290                                         }
5291                                     }
5292                                 }
5293                                 &Opcode::UwidenHigh => {
5294                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5295                                     if pattern12_0 == I32X4 {
5296                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5297                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5298                                             if let &InstructionData::Unary {
5299                                                 opcode: ref pattern16_0,
5300                                                 arg: pattern16_1,
5301                                             } = &pattern15_0
5302                                             {
5303                                                 if let &Opcode::UwidenHigh = pattern16_0 {
5304                                                     let pattern18_0 =
5305                                                         C::value_type(ctx, pattern16_1);
5306                                                     if pattern18_0 == I32X4 {
5307                                                         // Rule at src/isa/aarch64/lower.isle line 352.
5308                                                         let expr0_0 =
5309                                                             C::put_in_reg(ctx, pattern10_1);
5310                                                         let expr1_0 =
5311                                                             C::put_in_reg(ctx, pattern16_1);
5312                                                         let expr2_0: bool = true;
5313                                                         let expr3_0 = constructor_umull32(
5314                                                             ctx, expr0_0, expr1_0, expr2_0,
5315                                                         )?;
5316                                                         let expr4_0 =
5317                                                             constructor_output_reg(ctx, expr3_0)?;
5318                                                         return Some(expr4_0);
5319                                                     }
5320                                                 }
5321                                             }
5322                                         }
5323                                     }
5324                                 }
5325                                 _ => {}
5326                             }
5327                         }
5328                     }
5329                     // Rule at src/isa/aarch64/lower.isle line 247.
5330                     let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5331                     let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5332                     let expr2_0 = VectorSize::Size32x4;
5333                     let expr3_0 = constructor_rev64(ctx, expr1_0, &expr2_0)?;
5334                     let expr4_0 = VectorSize::Size32x4;
5335                     let expr5_0 = constructor_mul(ctx, expr3_0, expr0_0, &expr4_0)?;
5336                     let expr6_0: bool = false;
5337                     let expr7_0 = constructor_xtn64(ctx, expr0_0, expr6_0)?;
5338                     let expr8_0 = VectorSize::Size32x4;
5339                     let expr9_0 = constructor_addp(ctx, expr5_0, expr5_0, &expr8_0)?;
5340                     let expr10_0: bool = false;
5341                     let expr11_0 = constructor_xtn64(ctx, expr1_0, expr10_0)?;
5342                     let expr12_0: bool = false;
5343                     let expr13_0 = constructor_shll32(ctx, expr9_0, expr12_0)?;
5344                     let expr14_0: bool = false;
5345                     let expr15_0 = constructor_umlal32(ctx, expr13_0, expr11_0, expr7_0, expr14_0)?;
5346                     let expr16_0 = constructor_output_reg(ctx, expr15_0)?;
5347                     return Some(expr16_0);
5348                 }
5349             }
5350         }
5351         let pattern3_0 = C::inst_data(ctx, pattern0_0);
5352         match &pattern3_0 {
5353             &InstructionData::NullAry {
5354                 opcode: ref pattern4_0,
5355             } => {
5356                 if let &Opcode::Null = pattern4_0 {
5357                     // Rule at src/isa/aarch64/lower.isle line 22.
5358                     let expr0_0: u64 = 0;
5359                     let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5360                     let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5361                     return Some(expr2_0);
5362                 }
5363             }
5364             &InstructionData::UnaryImm {
5365                 opcode: ref pattern4_0,
5366                 imm: pattern4_1,
5367             } => {
5368                 if let &Opcode::Iconst = pattern4_0 {
5369                     let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1);
5370                     // Rule at src/isa/aarch64/lower.isle line 9.
5371                     let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?;
5372                     let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
5373                     return Some(expr1_0);
5374                 }
5375             }
5376             &InstructionData::UnaryBool {
5377                 opcode: ref pattern4_0,
5378                 imm: pattern4_1,
5379             } => {
5380                 if let &Opcode::Bconst = pattern4_0 {
5381                     if pattern4_1 == true {
5382                         // Rule at src/isa/aarch64/lower.isle line 17.
5383                         let expr0_0: u64 = 1;
5384                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5385                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5386                         return Some(expr2_0);
5387                     }
5388                     if pattern4_1 == false {
5389                         // Rule at src/isa/aarch64/lower.isle line 14.
5390                         let expr0_0: u64 = 0;
5391                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5392                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5393                         return Some(expr2_0);
5394                     }
5395                 }
5396             }
5397             &InstructionData::Unary {
5398                 opcode: ref pattern4_0,
5399                 arg: pattern4_1,
5400             } => {
5401                 match pattern4_0 {
5402                     &Opcode::Bitrev => {
5403                         // Rule at src/isa/aarch64/lower.isle line 995.
5404                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5405                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5406                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5407                         return Some(expr2_0);
5408                     }
5409                     &Opcode::Clz => {
5410                         // Rule at src/isa/aarch64/lower.isle line 1010.
5411                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5412                         let expr1_0 = constructor_a64_clz(ctx, pattern2_0, expr0_0)?;
5413                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5414                         return Some(expr2_0);
5415                     }
5416                     &Opcode::Cls => {
5417                         // Rule at src/isa/aarch64/lower.isle line 1077.
5418                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5419                         let expr1_0 = constructor_a64_cls(ctx, pattern2_0, expr0_0)?;
5420                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5421                         return Some(expr2_0);
5422                     }
5423                     &Opcode::Ctz => {
5424                         // Rule at src/isa/aarch64/lower.isle line 1043.
5425                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5426                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5427                         let expr2_0 = constructor_a64_clz(ctx, pattern2_0, expr1_0)?;
5428                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5429                         return Some(expr3_0);
5430                     }
5431                     _ => {}
5432                 }
5433             }
5434             _ => {}
5435         }
5436         if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) {
5437             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5438             match &pattern4_0 {
5439                 &InstructionData::Binary {
5440                     opcode: ref pattern5_0,
5441                     args: ref pattern5_1,
5442                 } => {
5443                     match pattern5_0 {
5444                         &Opcode::Iadd => {
5445                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5446                             // Rule at src/isa/aarch64/lower.isle line 79.
5447                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5448                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5449                             let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5450                             let expr3_0 = constructor_add_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5451                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5452                             return Some(expr4_0);
5453                         }
5454                         &Opcode::Isub => {
5455                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5456                             // Rule at src/isa/aarch64/lower.isle line 129.
5457                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5458                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5459                             let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5460                             let expr3_0 = constructor_sub_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5461                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5462                             return Some(expr4_0);
5463                         }
5464                         _ => {}
5465                     }
5466                 }
5467                 &InstructionData::FloatCompare {
5468                     opcode: ref pattern5_0,
5469                     args: ref pattern5_1,
5470                     cond: ref pattern5_2,
5471                 } => {
5472                     if let &Opcode::Fcmp = pattern5_0 {
5473                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5474                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5475                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5476                             if let &InstructionData::Unary {
5477                                 opcode: ref pattern10_0,
5478                                 arg: pattern10_1,
5479                             } = &pattern9_0
5480                             {
5481                                 if let &Opcode::Splat = pattern10_0 {
5482                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5483                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5484                                         match &pattern13_0 {
5485                                             &InstructionData::UnaryIeee32 {
5486                                                 opcode: ref pattern14_0,
5487                                                 imm: pattern14_1,
5488                                             } => {
5489                                                 if let &Opcode::F32const = pattern14_0 {
5490                                                     if let Some(pattern16_0) =
5491                                                         C::zero_value_f32(ctx, pattern14_1)
5492                                                     {
5493                                                         if let Some(pattern17_0) =
5494                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5495                                                         {
5496                                                             // Rule at src/isa/aarch64/lower.isle line 1151.
5497                                                             let expr0_0 =
5498                                                                 C::put_in_reg(ctx, pattern7_1);
5499                                                             let expr1_0 = constructor_vector_size(
5500                                                                 ctx, pattern2_0,
5501                                                             )?;
5502                                                             let expr2_0 =
5503                                                                 constructor_float_cmp_zero_swap(
5504                                                                     ctx,
5505                                                                     &pattern17_0,
5506                                                                     expr0_0,
5507                                                                     &expr1_0,
5508                                                                 )?;
5509                                                             let expr3_0 =
5510                                                                 C::value_reg(ctx, expr2_0);
5511                                                             let expr4_0 = C::output(ctx, expr3_0);
5512                                                             return Some(expr4_0);
5513                                                         }
5514                                                         if let Some(pattern17_0) =
5515                                                             C::fcmp_zero_cond_not_eq(
5516                                                                 ctx, pattern5_2,
5517                                                             )
5518                                                         {
5519                                                             // Rule at src/isa/aarch64/lower.isle line 1146.
5520                                                             let expr0_0 =
5521                                                                 C::put_in_reg(ctx, pattern7_1);
5522                                                             let expr1_0 = constructor_vector_size(
5523                                                                 ctx, pattern2_0,
5524                                                             )?;
5525                                                             let expr2_0 = constructor_fcmeq0(
5526                                                                 ctx, expr0_0, &expr1_0,
5527                                                             )?;
5528                                                             let expr3_0 = constructor_not(
5529                                                                 ctx, expr2_0, &expr1_0,
5530                                                             )?;
5531                                                             let expr4_0 =
5532                                                                 C::value_reg(ctx, expr3_0);
5533                                                             let expr5_0 = C::output(ctx, expr4_0);
5534                                                             return Some(expr5_0);
5535                                                         }
5536                                                     }
5537                                                 }
5538                                             }
5539                                             &InstructionData::UnaryIeee64 {
5540                                                 opcode: ref pattern14_0,
5541                                                 imm: pattern14_1,
5542                                             } => {
5543                                                 if let &Opcode::F64const = pattern14_0 {
5544                                                     if let Some(pattern16_0) =
5545                                                         C::zero_value_f64(ctx, pattern14_1)
5546                                                     {
5547                                                         if let Some(pattern17_0) =
5548                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5549                                                         {
5550                                                             // Rule at src/isa/aarch64/lower.isle line 1173.
5551                                                             let expr0_0 =
5552                                                                 C::put_in_reg(ctx, pattern7_1);
5553                                                             let expr1_0 = constructor_vector_size(
5554                                                                 ctx, pattern2_0,
5555                                                             )?;
5556                                                             let expr2_0 =
5557                                                                 constructor_float_cmp_zero_swap(
5558                                                                     ctx,
5559                                                                     &pattern17_0,
5560                                                                     expr0_0,
5561                                                                     &expr1_0,
5562                                                                 )?;
5563                                                             let expr3_0 =
5564                                                                 C::value_reg(ctx, expr2_0);
5565                                                             let expr4_0 = C::output(ctx, expr3_0);
5566                                                             return Some(expr4_0);
5567                                                         }
5568                                                         if let Some(pattern17_0) =
5569                                                             C::fcmp_zero_cond_not_eq(
5570                                                                 ctx, pattern5_2,
5571                                                             )
5572                                                         {
5573                                                             // Rule at src/isa/aarch64/lower.isle line 1168.
5574                                                             let expr0_0 =
5575                                                                 C::put_in_reg(ctx, pattern7_1);
5576                                                             let expr1_0 = constructor_vector_size(
5577                                                                 ctx, pattern2_0,
5578                                                             )?;
5579                                                             let expr2_0 = constructor_fcmeq0(
5580                                                                 ctx, expr0_0, &expr1_0,
5581                                                             )?;
5582                                                             let expr3_0 = constructor_not(
5583                                                                 ctx, expr2_0, &expr1_0,
5584                                                             )?;
5585                                                             let expr4_0 =
5586                                                                 C::value_reg(ctx, expr3_0);
5587                                                             let expr5_0 = C::output(ctx, expr4_0);
5588                                                             return Some(expr5_0);
5589                                                         }
5590                                                     }
5591                                                 }
5592                                             }
5593                                             _ => {}
5594                                         }
5595                                     }
5596                                 }
5597                             }
5598                         }
5599                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5600                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5601                             if let &InstructionData::Unary {
5602                                 opcode: ref pattern10_0,
5603                                 arg: pattern10_1,
5604                             } = &pattern9_0
5605                             {
5606                                 if let &Opcode::Splat = pattern10_0 {
5607                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5608                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5609                                         match &pattern13_0 {
5610                                             &InstructionData::UnaryIeee32 {
5611                                                 opcode: ref pattern14_0,
5612                                                 imm: pattern14_1,
5613                                             } => {
5614                                                 if let &Opcode::F32const = pattern14_0 {
5615                                                     if let Some(pattern16_0) =
5616                                                         C::zero_value_f32(ctx, pattern14_1)
5617                                                     {
5618                                                         if let Some(pattern17_0) =
5619                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5620                                                         {
5621                                                             // Rule at src/isa/aarch64/lower.isle line 1141.
5622                                                             let expr0_0 =
5623                                                                 C::put_in_reg(ctx, pattern7_0);
5624                                                             let expr1_0 = constructor_vector_size(
5625                                                                 ctx, pattern2_0,
5626                                                             )?;
5627                                                             let expr2_0 =
5628                                                                 constructor_float_cmp_zero(
5629                                                                     ctx,
5630                                                                     &pattern17_0,
5631                                                                     expr0_0,
5632                                                                     &expr1_0,
5633                                                                 )?;
5634                                                             let expr3_0 =
5635                                                                 C::value_reg(ctx, expr2_0);
5636                                                             let expr4_0 = C::output(ctx, expr3_0);
5637                                                             return Some(expr4_0);
5638                                                         }
5639                                                         if let Some(pattern17_0) =
5640                                                             C::fcmp_zero_cond_not_eq(
5641                                                                 ctx, pattern5_2,
5642                                                             )
5643                                                         {
5644                                                             // Rule at src/isa/aarch64/lower.isle line 1136.
5645                                                             let expr0_0 =
5646                                                                 C::put_in_reg(ctx, pattern7_0);
5647                                                             let expr1_0 = constructor_vector_size(
5648                                                                 ctx, pattern2_0,
5649                                                             )?;
5650                                                             let expr2_0 = constructor_fcmeq0(
5651                                                                 ctx, expr0_0, &expr1_0,
5652                                                             )?;
5653                                                             let expr3_0 = constructor_not(
5654                                                                 ctx, expr2_0, &expr1_0,
5655                                                             )?;
5656                                                             let expr4_0 =
5657                                                                 C::value_reg(ctx, expr3_0);
5658                                                             let expr5_0 = C::output(ctx, expr4_0);
5659                                                             return Some(expr5_0);
5660                                                         }
5661                                                     }
5662                                                 }
5663                                             }
5664                                             &InstructionData::UnaryIeee64 {
5665                                                 opcode: ref pattern14_0,
5666                                                 imm: pattern14_1,
5667                                             } => {
5668                                                 if let &Opcode::F64const = pattern14_0 {
5669                                                     if let Some(pattern16_0) =
5670                                                         C::zero_value_f64(ctx, pattern14_1)
5671                                                     {
5672                                                         if let Some(pattern17_0) =
5673                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5674                                                         {
5675                                                             // Rule at src/isa/aarch64/lower.isle line 1163.
5676                                                             let expr0_0 =
5677                                                                 C::put_in_reg(ctx, pattern7_0);
5678                                                             let expr1_0 = constructor_vector_size(
5679                                                                 ctx, pattern2_0,
5680                                                             )?;
5681                                                             let expr2_0 =
5682                                                                 constructor_float_cmp_zero(
5683                                                                     ctx,
5684                                                                     &pattern17_0,
5685                                                                     expr0_0,
5686                                                                     &expr1_0,
5687                                                                 )?;
5688                                                             let expr3_0 =
5689                                                                 C::value_reg(ctx, expr2_0);
5690                                                             let expr4_0 = C::output(ctx, expr3_0);
5691                                                             return Some(expr4_0);
5692                                                         }
5693                                                         if let Some(pattern17_0) =
5694                                                             C::fcmp_zero_cond_not_eq(
5695                                                                 ctx, pattern5_2,
5696                                                             )
5697                                                         {
5698                                                             // Rule at src/isa/aarch64/lower.isle line 1158.
5699                                                             let expr0_0 =
5700                                                                 C::put_in_reg(ctx, pattern7_0);
5701                                                             let expr1_0 = constructor_vector_size(
5702                                                                 ctx, pattern2_0,
5703                                                             )?;
5704                                                             let expr2_0 = constructor_fcmeq0(
5705                                                                 ctx, expr0_0, &expr1_0,
5706                                                             )?;
5707                                                             let expr3_0 = constructor_not(
5708                                                                 ctx, expr2_0, &expr1_0,
5709                                                             )?;
5710                                                             let expr4_0 =
5711                                                                 C::value_reg(ctx, expr3_0);
5712                                                             let expr5_0 = C::output(ctx, expr4_0);
5713                                                             return Some(expr5_0);
5714                                                         }
5715                                                     }
5716                                                 }
5717                                             }
5718                                             _ => {}
5719                                         }
5720                                     }
5721                                 }
5722                             }
5723                         }
5724                     }
5725                 }
5726                 &InstructionData::IntCompare {
5727                     opcode: ref pattern5_0,
5728                     args: ref pattern5_1,
5729                     cond: ref pattern5_2,
5730                 } => {
5731                     if let &Opcode::Icmp = pattern5_0 {
5732                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5733                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5734                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5735                             if let &InstructionData::Unary {
5736                                 opcode: ref pattern10_0,
5737                                 arg: pattern10_1,
5738                             } = &pattern9_0
5739                             {
5740                                 if let &Opcode::Splat = pattern10_0 {
5741                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5742                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5743                                         if let &InstructionData::UnaryImm {
5744                                             opcode: ref pattern14_0,
5745                                             imm: pattern14_1,
5746                                         } = &pattern13_0
5747                                         {
5748                                             if let &Opcode::Iconst = pattern14_0 {
5749                                                 if let Some(pattern16_0) =
5750                                                     C::zero_value(ctx, pattern14_1)
5751                                                 {
5752                                                     if let Some(pattern17_0) =
5753                                                         C::icmp_zero_cond(ctx, pattern5_2)
5754                                                     {
5755                                                         // Rule at src/isa/aarch64/lower.isle line 1195.
5756                                                         let expr0_0 =
5757                                                             C::put_in_reg(ctx, pattern7_1);
5758                                                         let expr1_0 = constructor_vector_size(
5759                                                             ctx, pattern2_0,
5760                                                         )?;
5761                                                         let expr2_0 =
5762                                                             constructor_int_cmp_zero_swap(
5763                                                                 ctx,
5764                                                                 &pattern17_0,
5765                                                                 expr0_0,
5766                                                                 &expr1_0,
5767                                                             )?;
5768                                                         let expr3_0 = C::value_reg(ctx, expr2_0);
5769                                                         let expr4_0 = C::output(ctx, expr3_0);
5770                                                         return Some(expr4_0);
5771                                                     }
5772                                                     if let Some(pattern17_0) =
5773                                                         C::icmp_zero_cond_not_eq(ctx, pattern5_2)
5774                                                     {
5775                                                         // Rule at src/isa/aarch64/lower.isle line 1190.
5776                                                         let expr0_0 =
5777                                                             C::put_in_reg(ctx, pattern7_1);
5778                                                         let expr1_0 = constructor_vector_size(
5779                                                             ctx, pattern2_0,
5780                                                         )?;
5781                                                         let expr2_0 = constructor_cmeq0(
5782                                                             ctx, expr0_0, &expr1_0,
5783                                                         )?;
5784                                                         let expr3_0 = constructor_not(
5785                                                             ctx, expr2_0, &expr1_0,
5786                                                         )?;
5787                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5788                                                         let expr5_0 = C::output(ctx, expr4_0);
5789                                                         return Some(expr5_0);
5790                                                     }
5791                                                 }
5792                                             }
5793                                         }
5794                                     }
5795                                 }
5796                             }
5797                         }
5798                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5799                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5800                             if let &InstructionData::Unary {
5801                                 opcode: ref pattern10_0,
5802                                 arg: pattern10_1,
5803                             } = &pattern9_0
5804                             {
5805                                 if let &Opcode::Splat = pattern10_0 {
5806                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5807                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5808                                         if let &InstructionData::UnaryImm {
5809                                             opcode: ref pattern14_0,
5810                                             imm: pattern14_1,
5811                                         } = &pattern13_0
5812                                         {
5813                                             if let &Opcode::Iconst = pattern14_0 {
5814                                                 if let Some(pattern16_0) =
5815                                                     C::zero_value(ctx, pattern14_1)
5816                                                 {
5817                                                     if let Some(pattern17_0) =
5818                                                         C::icmp_zero_cond(ctx, pattern5_2)
5819                                                     {
5820                                                         // Rule at src/isa/aarch64/lower.isle line 1185.
5821                                                         let expr0_0 =
5822                                                             C::put_in_reg(ctx, pattern7_0);
5823                                                         let expr1_0 = constructor_vector_size(
5824                                                             ctx, pattern2_0,
5825                                                         )?;
5826                                                         let expr2_0 = constructor_int_cmp_zero(
5827                                                             ctx,
5828                                                             &pattern17_0,
5829                                                             expr0_0,
5830                                                             &expr1_0,
5831                                                         )?;
5832                                                         let expr3_0 = C::value_reg(ctx, expr2_0);
5833                                                         let expr4_0 = C::output(ctx, expr3_0);
5834                                                         return Some(expr4_0);
5835                                                     }
5836                                                     if let Some(pattern17_0) =
5837                                                         C::icmp_zero_cond_not_eq(ctx, pattern5_2)
5838                                                     {
5839                                                         // Rule at src/isa/aarch64/lower.isle line 1180.
5840                                                         let expr0_0 =
5841                                                             C::put_in_reg(ctx, pattern7_0);
5842                                                         let expr1_0 = constructor_vector_size(
5843                                                             ctx, pattern2_0,
5844                                                         )?;
5845                                                         let expr2_0 = constructor_cmeq0(
5846                                                             ctx, expr0_0, &expr1_0,
5847                                                         )?;
5848                                                         let expr3_0 = constructor_not(
5849                                                             ctx, expr2_0, &expr1_0,
5850                                                         )?;
5851                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5852                                                         let expr5_0 = C::output(ctx, expr4_0);
5853                                                         return Some(expr5_0);
5854                                                     }
5855                                                 }
5856                                             }
5857                                         }
5858                                     }
5859                                 }
5860                             }
5861                         }
5862                     }
5863                 }
5864                 _ => {}
5865             }
5866         }
5867         if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
5868             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5869             if let &InstructionData::Binary {
5870                 opcode: ref pattern5_0,
5871                 args: ref pattern5_1,
5872             } = &pattern4_0
5873             {
5874                 match pattern5_0 {
5875                     &Opcode::Rotl => {
5876                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5877                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5878                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5879                             if let &InstructionData::UnaryImm {
5880                                 opcode: ref pattern10_0,
5881                                 imm: pattern10_1,
5882                             } = &pattern9_0
5883                             {
5884                                 if let &Opcode::Iconst = pattern10_0 {
5885                                     let mut closure12 = || {
5886                                         return Some(pattern3_0);
5887                                     };
5888                                     if let Some(pattern12_0) = closure12() {
5889                                         if let Some(pattern13_0) =
5890                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5891                                         {
5892                                             // Rule at src/isa/aarch64/lower.isle line 849.
5893                                             let expr0_0 =
5894                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5895                                             let expr1_0 =
5896                                                 C::negate_imm_shift(ctx, pattern3_0, pattern13_0);
5897                                             let expr2_0 = constructor_small_rotr_imm(
5898                                                 ctx, pattern3_0, expr0_0, expr1_0,
5899                                             )?;
5900                                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5901                                             return Some(expr3_0);
5902                                         }
5903                                     }
5904                                 }
5905                             }
5906                         }
5907                         // Rule at src/isa/aarch64/lower.isle line 844.
5908                         let expr0_0: Type = I32;
5909                         let expr1_0 = C::zero_reg(ctx);
5910                         let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5911                         let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
5912                         let expr4_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5913                         let expr5_0 = constructor_small_rotr(ctx, pattern3_0, expr4_0, expr3_0)?;
5914                         let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
5915                         return Some(expr6_0);
5916                     }
5917                     &Opcode::Rotr => {
5918                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5919                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5920                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5921                             if let &InstructionData::UnaryImm {
5922                                 opcode: ref pattern10_0,
5923                                 imm: pattern10_1,
5924                             } = &pattern9_0
5925                             {
5926                                 if let &Opcode::Iconst = pattern10_0 {
5927                                     let mut closure12 = || {
5928                                         return Some(pattern3_0);
5929                                     };
5930                                     if let Some(pattern12_0) = closure12() {
5931                                         if let Some(pattern13_0) =
5932                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5933                                         {
5934                                             // Rule at src/isa/aarch64/lower.isle line 909.
5935                                             let expr0_0 =
5936                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5937                                             let expr1_0 = constructor_small_rotr_imm(
5938                                                 ctx,
5939                                                 pattern3_0,
5940                                                 expr0_0,
5941                                                 pattern13_0,
5942                                             )?;
5943                                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5944                                             return Some(expr2_0);
5945                                         }
5946                                     }
5947                                 }
5948                             }
5949                         }
5950                         // Rule at src/isa/aarch64/lower.isle line 897.
5951                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5952                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5953                         let expr2_0 = constructor_small_rotr(ctx, pattern3_0, expr0_0, expr1_0)?;
5954                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5955                         return Some(expr3_0);
5956                     }
5957                     _ => {}
5958                 }
5959             }
5960         }
5961         if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
5962             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5963             if let &InstructionData::Binary {
5964                 opcode: ref pattern5_0,
5965                 args: ref pattern5_1,
5966             } = &pattern4_0
5967             {
5968                 match pattern5_0 {
5969                     &Opcode::Umulhi => {
5970                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5971                         // Rule at src/isa/aarch64/lower.isle line 374.
5972                         let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5973                         let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?;
5974                         let expr2_0: Type = I64;
5975                         let expr3_0 = C::zero_reg(ctx);
5976                         let expr4_0 = constructor_madd(ctx, expr2_0, expr0_0, expr1_0, expr3_0)?;
5977                         let expr5_0: Type = I64;
5978                         let expr6_0 = C::ty_bits(ctx, pattern3_0);
5979                         let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
5980                         let expr8_0 = constructor_lsr_imm(ctx, expr5_0, expr4_0, expr7_0)?;
5981                         let expr9_0 = C::value_reg(ctx, expr8_0);
5982                         let expr10_0 = C::output(ctx, expr9_0);
5983                         return Some(expr10_0);
5984                     }
5985                     &Opcode::Smulhi => {
5986                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5987                         // Rule at src/isa/aarch64/lower.isle line 362.
5988                         let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5989                         let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?;
5990                         let expr2_0: Type = I64;
5991                         let expr3_0 = C::zero_reg(ctx);
5992                         let expr4_0 = constructor_madd(ctx, expr2_0, expr0_0, expr1_0, expr3_0)?;
5993                         let expr5_0: Type = I64;
5994                         let expr6_0 = C::ty_bits(ctx, pattern3_0);
5995                         let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
5996                         let expr8_0 = constructor_asr_imm(ctx, expr5_0, expr4_0, expr7_0)?;
5997                         let expr9_0 = constructor_output_reg(ctx, expr8_0)?;
5998                         return Some(expr9_0);
5999                     }
6000                     &Opcode::Band => {
6001                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6002                         // Rule at src/isa/aarch64/lower.isle line 589.
6003                         let expr0_0 = ALUOp::And;
6004                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
6005                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
6006                         )?;
6007                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6008                         return Some(expr2_0);
6009                     }
6010                     &Opcode::Bor => {
6011                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6012                         // Rule at src/isa/aarch64/lower.isle line 602.
6013                         let expr0_0 = ALUOp::Orr;
6014                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
6015                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
6016                         )?;
6017                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6018                         return Some(expr2_0);
6019                     }
6020                     &Opcode::Bxor => {
6021                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6022                         // Rule at src/isa/aarch64/lower.isle line 615.
6023                         let expr0_0 = ALUOp::Eor;
6024                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
6025                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
6026                         )?;
6027                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6028                         return Some(expr2_0);
6029                     }
6030                     &Opcode::BandNot => {
6031                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6032                         // Rule at src/isa/aarch64/lower.isle line 628.
6033                         let expr0_0 = ALUOp::AndNot;
6034                         let expr1_0 = constructor_alu_rs_imm_logic(
6035                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
6036                         )?;
6037                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6038                         return Some(expr2_0);
6039                     }
6040                     &Opcode::BorNot => {
6041                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6042                         // Rule at src/isa/aarch64/lower.isle line 641.
6043                         let expr0_0 = ALUOp::OrrNot;
6044                         let expr1_0 = constructor_alu_rs_imm_logic(
6045                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
6046                         )?;
6047                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6048                         return Some(expr2_0);
6049                     }
6050                     &Opcode::BxorNot => {
6051                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6052                         // Rule at src/isa/aarch64/lower.isle line 651.
6053                         let expr0_0 = ALUOp::EorNot;
6054                         let expr1_0: Type = I32;
6055                         let expr2_0 = constructor_alu_rs_imm_logic(
6056                             ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
6057                         )?;
6058                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6059                         return Some(expr3_0);
6060                     }
6061                     &Opcode::Ishl => {
6062                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6063                         // Rule at src/isa/aarch64/lower.isle line 662.
6064                         let expr0_0 = ALUOp::Lsl;
6065                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
6066                         let expr2_0 =
6067                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
6068                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6069                         return Some(expr3_0);
6070                     }
6071                     &Opcode::Ushr => {
6072                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6073                         // Rule at src/isa/aarch64/lower.isle line 746.
6074                         let expr0_0 = ALUOp::Lsr;
6075                         let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
6076                         let expr2_0 =
6077                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
6078                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6079                         return Some(expr3_0);
6080                     }
6081                     &Opcode::Sshr => {
6082                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6083                         // Rule at src/isa/aarch64/lower.isle line 793.
6084                         let expr0_0 = ALUOp::Asr;
6085                         let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
6086                         let expr2_0 =
6087                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
6088                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6089                         return Some(expr3_0);
6090                     }
6091                     _ => {}
6092                 }
6093             }
6094         }
6095         if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
6096             let pattern4_0 = C::inst_data(ctx, pattern0_0);
6097             match &pattern4_0 {
6098                 &InstructionData::Binary {
6099                     opcode: ref pattern5_0,
6100                     args: ref pattern5_1,
6101                 } => {
6102                     match pattern5_0 {
6103                         &Opcode::Iadd => {
6104                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6105                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
6106                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6107                                 match &pattern9_0 {
6108                                     &InstructionData::UnaryImm {
6109                                         opcode: ref pattern10_0,
6110                                         imm: pattern10_1,
6111                                     } => {
6112                                         if let &Opcode::Iconst = pattern10_0 {
6113                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
6114                                             if let Some(pattern13_0) =
6115                                                 C::imm12_from_u64(ctx, pattern12_0)
6116                                             {
6117                                                 // Rule at src/isa/aarch64/lower.isle line 37.
6118                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
6119                                                 let expr1_0 = constructor_add_imm(
6120                                                     ctx,
6121                                                     pattern3_0,
6122                                                     expr0_0,
6123                                                     pattern13_0,
6124                                                 )?;
6125                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6126                                                 return Some(expr2_0);
6127                                             }
6128                                             if let Some(pattern13_0) =
6129                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
6130                                             {
6131                                                 // Rule at src/isa/aarch64/lower.isle line 45.
6132                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
6133                                                 let expr1_0 = constructor_sub_imm(
6134                                                     ctx,
6135                                                     pattern3_0,
6136                                                     expr0_0,
6137                                                     pattern13_0,
6138                                                 )?;
6139                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6140                                                 return Some(expr2_0);
6141                                             }
6142                                         }
6143                                     }
6144                                     &InstructionData::Binary {
6145                                         opcode: ref pattern10_0,
6146                                         args: ref pattern10_1,
6147                                     } => {
6148                                         match pattern10_0 {
6149                                             &Opcode::Imul => {
6150                                                 let (pattern12_0, pattern12_1) =
6151                                                     C::unpack_value_array_2(ctx, pattern10_1);
6152                                                 // Rule at src/isa/aarch64/lower.isle line 70.
6153                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
6154                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
6155                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_1);
6156                                                 let expr3_0 = constructor_madd(
6157                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
6158                                                 )?;
6159                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6160                                                 return Some(expr4_0);
6161                                             }
6162                                             &Opcode::Ishl => {
6163                                                 let (pattern12_0, pattern12_1) =
6164                                                     C::unpack_value_array_2(ctx, pattern10_1);
6165                                                 if let Some(pattern13_0) =
6166                                                     C::def_inst(ctx, pattern12_1)
6167                                                 {
6168                                                     let pattern14_0 =
6169                                                         C::inst_data(ctx, pattern13_0);
6170                                                     if let &InstructionData::UnaryImm {
6171                                                         opcode: ref pattern15_0,
6172                                                         imm: pattern15_1,
6173                                                     } = &pattern14_0
6174                                                     {
6175                                                         if let &Opcode::Iconst = pattern15_0 {
6176                                                             let mut closure17 = || {
6177                                                                 return Some(pattern3_0);
6178                                                             };
6179                                                             if let Some(pattern17_0) = closure17() {
6180                                                                 if let Some(pattern18_0) =
6181                                                                     C::lshl_from_imm64(
6182                                                                         ctx,
6183                                                                         pattern15_1,
6184                                                                         pattern17_0,
6185                                                                     )
6186                                                                 {
6187                                                                     // Rule at src/isa/aarch64/lower.isle line 62.
6188                                                                     let expr0_0 = C::put_in_reg(
6189                                                                         ctx, pattern7_1,
6190                                                                     );
6191                                                                     let expr1_0 = C::put_in_reg(
6192                                                                         ctx,
6193                                                                         pattern12_0,
6194                                                                     );
6195                                                                     let expr2_0 =
6196                                                                         constructor_add_shift(
6197                                                                             ctx,
6198                                                                             pattern3_0,
6199                                                                             expr0_0,
6200                                                                             expr1_0,
6201                                                                             pattern18_0,
6202                                                                         )?;
6203                                                                     let expr3_0 =
6204                                                                         constructor_output_reg(
6205                                                                             ctx, expr2_0,
6206                                                                         )?;
6207                                                                     return Some(expr3_0);
6208                                                                 }
6209                                                             }
6210                                                         }
6211                                                     }
6212                                                 }
6213                                             }
6214                                             _ => {}
6215                                         }
6216                                     }
6217                                     _ => {}
6218                                 }
6219                             }
6220                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0)
6221                             {
6222                                 // Rule at src/isa/aarch64/lower.isle line 53.
6223                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
6224                                 let expr1_0 =
6225                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6226                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6227                                 return Some(expr2_0);
6228                             }
6229                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6230                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6231                                 match &pattern9_0 {
6232                                     &InstructionData::UnaryImm {
6233                                         opcode: ref pattern10_0,
6234                                         imm: pattern10_1,
6235                                     } => {
6236                                         if let &Opcode::Iconst = pattern10_0 {
6237                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
6238                                             if let Some(pattern13_0) =
6239                                                 C::imm12_from_u64(ctx, pattern12_0)
6240                                             {
6241                                                 // Rule at src/isa/aarch64/lower.isle line 34.
6242                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6243                                                 let expr1_0 = constructor_add_imm(
6244                                                     ctx,
6245                                                     pattern3_0,
6246                                                     expr0_0,
6247                                                     pattern13_0,
6248                                                 )?;
6249                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6250                                                 return Some(expr2_0);
6251                                             }
6252                                             if let Some(pattern13_0) =
6253                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
6254                                             {
6255                                                 // Rule at src/isa/aarch64/lower.isle line 42.
6256                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6257                                                 let expr1_0 = constructor_sub_imm(
6258                                                     ctx,
6259                                                     pattern3_0,
6260                                                     expr0_0,
6261                                                     pattern13_0,
6262                                                 )?;
6263                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6264                                                 return Some(expr2_0);
6265                                             }
6266                                         }
6267                                     }
6268                                     &InstructionData::Binary {
6269                                         opcode: ref pattern10_0,
6270                                         args: ref pattern10_1,
6271                                     } => {
6272                                         match pattern10_0 {
6273                                             &Opcode::Imul => {
6274                                                 let (pattern12_0, pattern12_1) =
6275                                                     C::unpack_value_array_2(ctx, pattern10_1);
6276                                                 // Rule at src/isa/aarch64/lower.isle line 67.
6277                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
6278                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
6279                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
6280                                                 let expr3_0 = constructor_madd(
6281                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
6282                                                 )?;
6283                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6284                                                 return Some(expr4_0);
6285                                             }
6286                                             &Opcode::Ishl => {
6287                                                 let (pattern12_0, pattern12_1) =
6288                                                     C::unpack_value_array_2(ctx, pattern10_1);
6289                                                 if let Some(pattern13_0) =
6290                                                     C::def_inst(ctx, pattern12_1)
6291                                                 {
6292                                                     let pattern14_0 =
6293                                                         C::inst_data(ctx, pattern13_0);
6294                                                     if let &InstructionData::UnaryImm {
6295                                                         opcode: ref pattern15_0,
6296                                                         imm: pattern15_1,
6297                                                     } = &pattern14_0
6298                                                     {
6299                                                         if let &Opcode::Iconst = pattern15_0 {
6300                                                             let mut closure17 = || {
6301                                                                 return Some(pattern3_0);
6302                                                             };
6303                                                             if let Some(pattern17_0) = closure17() {
6304                                                                 if let Some(pattern18_0) =
6305                                                                     C::lshl_from_imm64(
6306                                                                         ctx,
6307                                                                         pattern15_1,
6308                                                                         pattern17_0,
6309                                                                     )
6310                                                                 {
6311                                                                     // Rule at src/isa/aarch64/lower.isle line 58.
6312                                                                     let expr0_0 = C::put_in_reg(
6313                                                                         ctx, pattern7_0,
6314                                                                     );
6315                                                                     let expr1_0 = C::put_in_reg(
6316                                                                         ctx,
6317                                                                         pattern12_0,
6318                                                                     );
6319                                                                     let expr2_0 =
6320                                                                         constructor_add_shift(
6321                                                                             ctx,
6322                                                                             pattern3_0,
6323                                                                             expr0_0,
6324                                                                             expr1_0,
6325                                                                             pattern18_0,
6326                                                                         )?;
6327                                                                     let expr3_0 =
6328                                                                         constructor_output_reg(
6329                                                                             ctx, expr2_0,
6330                                                                         )?;
6331                                                                     return Some(expr3_0);
6332                                                                 }
6333                                                             }
6334                                                         }
6335                                                     }
6336                                                 }
6337                                             }
6338                                             _ => {}
6339                                         }
6340                                     }
6341                                     _ => {}
6342                                 }
6343                             }
6344                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
6345                             {
6346                                 // Rule at src/isa/aarch64/lower.isle line 50.
6347                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6348                                 let expr1_0 =
6349                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6350                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6351                                 return Some(expr2_0);
6352                             }
6353                             // Rule at src/isa/aarch64/lower.isle line 30.
6354                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6355                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6356                             let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, expr1_0)?;
6357                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6358                             return Some(expr3_0);
6359                         }
6360                         &Opcode::Isub => {
6361                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6362                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6363                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6364                                 match &pattern9_0 {
6365                                     &InstructionData::UnaryImm {
6366                                         opcode: ref pattern10_0,
6367                                         imm: pattern10_1,
6368                                     } => {
6369                                         if let &Opcode::Iconst = pattern10_0 {
6370                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
6371                                             if let Some(pattern13_0) =
6372                                                 C::imm12_from_u64(ctx, pattern12_0)
6373                                             {
6374                                                 // Rule at src/isa/aarch64/lower.isle line 109.
6375                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6376                                                 let expr1_0 = constructor_sub_imm(
6377                                                     ctx,
6378                                                     pattern3_0,
6379                                                     expr0_0,
6380                                                     pattern13_0,
6381                                                 )?;
6382                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6383                                                 return Some(expr2_0);
6384                                             }
6385                                             if let Some(pattern13_0) =
6386                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
6387                                             {
6388                                                 // Rule at src/isa/aarch64/lower.isle line 114.
6389                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6390                                                 let expr1_0 = constructor_add_imm(
6391                                                     ctx,
6392                                                     pattern3_0,
6393                                                     expr0_0,
6394                                                     pattern13_0,
6395                                                 )?;
6396                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6397                                                 return Some(expr2_0);
6398                                             }
6399                                         }
6400                                     }
6401                                     &InstructionData::Binary {
6402                                         opcode: ref pattern10_0,
6403                                         args: ref pattern10_1,
6404                                     } => {
6405                                         match pattern10_0 {
6406                                             &Opcode::Imul => {
6407                                                 let (pattern12_0, pattern12_1) =
6408                                                     C::unpack_value_array_2(ctx, pattern10_1);
6409                                                 // Rule at src/isa/aarch64/lower.isle line 74.
6410                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
6411                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
6412                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
6413                                                 let expr3_0 = constructor_msub(
6414                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
6415                                                 )?;
6416                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6417                                                 return Some(expr4_0);
6418                                             }
6419                                             &Opcode::Ishl => {
6420                                                 let (pattern12_0, pattern12_1) =
6421                                                     C::unpack_value_array_2(ctx, pattern10_1);
6422                                                 if let Some(pattern13_0) =
6423                                                     C::def_inst(ctx, pattern12_1)
6424                                                 {
6425                                                     let pattern14_0 =
6426                                                         C::inst_data(ctx, pattern13_0);
6427                                                     if let &InstructionData::UnaryImm {
6428                                                         opcode: ref pattern15_0,
6429                                                         imm: pattern15_1,
6430                                                     } = &pattern14_0
6431                                                     {
6432                                                         if let &Opcode::Iconst = pattern15_0 {
6433                                                             let mut closure17 = || {
6434                                                                 return Some(pattern3_0);
6435                                                             };
6436                                                             if let Some(pattern17_0) = closure17() {
6437                                                                 if let Some(pattern18_0) =
6438                                                                     C::lshl_from_imm64(
6439                                                                         ctx,
6440                                                                         pattern15_1,
6441                                                                         pattern17_0,
6442                                                                     )
6443                                                                 {
6444                                                                     // Rule at src/isa/aarch64/lower.isle line 124.
6445                                                                     let expr0_0 = C::put_in_reg(
6446                                                                         ctx, pattern7_0,
6447                                                                     );
6448                                                                     let expr1_0 = C::put_in_reg(
6449                                                                         ctx,
6450                                                                         pattern12_0,
6451                                                                     );
6452                                                                     let expr2_0 =
6453                                                                         constructor_sub_shift(
6454                                                                             ctx,
6455                                                                             pattern3_0,
6456                                                                             expr0_0,
6457                                                                             expr1_0,
6458                                                                             pattern18_0,
6459                                                                         )?;
6460                                                                     let expr3_0 =
6461                                                                         constructor_output_reg(
6462                                                                             ctx, expr2_0,
6463                                                                         )?;
6464                                                                     return Some(expr3_0);
6465                                                                 }
6466                                                             }
6467                                                         }
6468                                                     }
6469                                                 }
6470                                             }
6471                                             _ => {}
6472                                         }
6473                                     }
6474                                     _ => {}
6475                                 }
6476                             }
6477                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
6478                             {
6479                                 // Rule at src/isa/aarch64/lower.isle line 119.
6480                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6481                                 let expr1_0 =
6482                                     constructor_sub_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6483                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6484                                 return Some(expr2_0);
6485                             }
6486                             // Rule at src/isa/aarch64/lower.isle line 105.
6487                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6488                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6489                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
6490                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6491                             return Some(expr3_0);
6492                         }
6493                         &Opcode::Imul => {
6494                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6495                             // Rule at src/isa/aarch64/lower.isle line 183.
6496                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6497                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6498                             let expr2_0 = C::zero_reg(ctx);
6499                             let expr3_0 =
6500                                 constructor_madd(ctx, pattern3_0, expr0_0, expr1_0, expr2_0)?;
6501                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6502                             return Some(expr4_0);
6503                         }
6504                         &Opcode::Udiv => {
6505                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6506                             // Rule at src/isa/aarch64/lower.isle line 390.
6507                             let expr0_0: Type = I64;
6508                             let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
6509                             let expr2_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
6510                             let expr3_0 = constructor_a64_udiv(ctx, expr0_0, expr1_0, expr2_0)?;
6511                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6512                             return Some(expr4_0);
6513                         }
6514                         &Opcode::Sdiv => {
6515                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6516                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6517                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6518                                 if let &InstructionData::UnaryImm {
6519                                     opcode: ref pattern10_0,
6520                                     imm: pattern10_1,
6521                                 } = &pattern9_0
6522                                 {
6523                                     if let &Opcode::Iconst = pattern10_0 {
6524                                         if let Some(pattern12_0) =
6525                                             C::safe_divisor_from_imm64(ctx, pattern10_1)
6526                                         {
6527                                             // Rule at src/isa/aarch64/lower.isle line 436.
6528                                             let expr0_0: Type = I64;
6529                                             let expr1_0 =
6530                                                 constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6531                                             let expr2_0 =
6532                                                 constructor_imm(ctx, pattern3_0, pattern12_0)?;
6533                                             let expr3_0 = constructor_a64_sdiv(
6534                                                 ctx, expr0_0, expr1_0, expr2_0,
6535                                             )?;
6536                                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6537                                             return Some(expr4_0);
6538                                         }
6539                                     }
6540                                 }
6541                             }
6542                             // Rule at src/isa/aarch64/lower.isle line 423.
6543                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6544                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
6545                             let expr2_0 = constructor_trap_if_div_overflow(
6546                                 ctx, pattern3_0, expr0_0, expr1_0,
6547                             )?;
6548                             let expr3_0: Type = I64;
6549                             let expr4_0 = constructor_a64_sdiv(ctx, expr3_0, expr2_0, expr1_0)?;
6550                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6551                             return Some(expr5_0);
6552                         }
6553                         &Opcode::Urem => {
6554                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6555                             // Rule at src/isa/aarch64/lower.isle line 464.
6556                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
6557                             let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
6558                             let expr2_0: Type = I64;
6559                             let expr3_0 = constructor_a64_udiv(ctx, expr2_0, expr0_0, expr1_0)?;
6560                             let expr4_0: Type = I64;
6561                             let expr5_0 =
6562                                 constructor_msub(ctx, expr4_0, expr3_0, expr1_0, expr0_0)?;
6563                             let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
6564                             return Some(expr6_0);
6565                         }
6566                         &Opcode::Srem => {
6567                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6568                             // Rule at src/isa/aarch64/lower.isle line 471.
6569                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6570                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
6571                             let expr2_0: Type = I64;
6572                             let expr3_0 = constructor_a64_sdiv(ctx, expr2_0, expr0_0, expr1_0)?;
6573                             let expr4_0: Type = I64;
6574                             let expr5_0 =
6575                                 constructor_msub(ctx, expr4_0, expr3_0, expr1_0, expr0_0)?;
6576                             let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
6577                             return Some(expr6_0);
6578                         }
6579                         _ => {}
6580                     }
6581                 }
6582                 &InstructionData::Unary {
6583                     opcode: ref pattern5_0,
6584                     arg: pattern5_1,
6585                 } => {
6586                     match pattern5_0 {
6587                         &Opcode::Ineg => {
6588                             // Rule at src/isa/aarch64/lower.isle line 173.
6589                             let expr0_0 = C::zero_reg(ctx);
6590                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6591                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
6592                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6593                             return Some(expr3_0);
6594                         }
6595                         &Opcode::Bnot => {
6596                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6597                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6598                                 if let &InstructionData::Binary {
6599                                     opcode: ref pattern9_0,
6600                                     args: ref pattern9_1,
6601                                 } = &pattern8_0
6602                                 {
6603                                     if let &Opcode::Ishl = pattern9_0 {
6604                                         let (pattern11_0, pattern11_1) =
6605                                             C::unpack_value_array_2(ctx, pattern9_1);
6606                                         if let Some(pattern12_0) = C::def_inst(ctx, pattern11_1) {
6607                                             let pattern13_0 = C::inst_data(ctx, pattern12_0);
6608                                             if let &InstructionData::UnaryImm {
6609                                                 opcode: ref pattern14_0,
6610                                                 imm: pattern14_1,
6611                                             } = &pattern13_0
6612                                             {
6613                                                 if let &Opcode::Iconst = pattern14_0 {
6614                                                     let mut closure16 = || {
6615                                                         return Some(pattern3_0);
6616                                                     };
6617                                                     if let Some(pattern16_0) = closure16() {
6618                                                         if let Some(pattern17_0) =
6619                                                             C::lshl_from_imm64(
6620                                                                 ctx,
6621                                                                 pattern14_1,
6622                                                                 pattern16_0,
6623                                                             )
6624                                                         {
6625                                                             // Rule at src/isa/aarch64/lower.isle line 570.
6626                                                             let expr0_0 = C::zero_reg(ctx);
6627                                                             let expr1_0 =
6628                                                                 C::put_in_reg(ctx, pattern11_0);
6629                                                             let expr2_0 =
6630                                                                 constructor_orr_not_shift(
6631                                                                     ctx,
6632                                                                     pattern3_0,
6633                                                                     expr0_0,
6634                                                                     expr1_0,
6635                                                                     pattern17_0,
6636                                                                 )?;
6637                                                             let expr3_0 = constructor_output_reg(
6638                                                                 ctx, expr2_0,
6639                                                             )?;
6640                                                             return Some(expr3_0);
6641                                                         }
6642                                                     }
6643                                                 }
6644                                             }
6645                                         }
6646                                     }
6647                                 }
6648                             }
6649                             // Rule at src/isa/aarch64/lower.isle line 565.
6650                             let expr0_0 = C::zero_reg(ctx);
6651                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6652                             let expr2_0 = constructor_orr_not(ctx, pattern3_0, expr0_0, expr1_0)?;
6653                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6654                             return Some(expr3_0);
6655                         }
6656                         &Opcode::Uextend => {
6657                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6658                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6659                                 if let &InstructionData::BinaryImm8 {
6660                                     opcode: ref pattern9_0,
6661                                     arg: pattern9_1,
6662                                     imm: pattern9_2,
6663                                 } = &pattern8_0
6664                                 {
6665                                     if let &Opcode::Extractlane = pattern9_0 {
6666                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6667                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6668                                         // Rule at src/isa/aarch64/lower.isle line 487.
6669                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6670                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6671                                         let expr2_0 = constructor_mov_from_vec(
6672                                             ctx,
6673                                             expr0_0,
6674                                             pattern12_0,
6675                                             &expr1_0,
6676                                         )?;
6677                                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6678                                         return Some(expr3_0);
6679                                     }
6680                                 }
6681                             }
6682                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6683                             if let Some(pattern8_0) = C::sinkable_atomic_load(ctx, pattern5_1) {
6684                                 // Rule at src/isa/aarch64/lower.isle line 494.
6685                                 let expr0_0 = C::sink_atomic_load(ctx, &pattern8_0);
6686                                 let expr1_0 = constructor_load_acquire(ctx, pattern7_0, expr0_0)?;
6687                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6688                                 return Some(expr2_0);
6689                             }
6690                             // Rule at src/isa/aarch64/lower.isle line 482.
6691                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6692                             let expr1_0: bool = false;
6693                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6694                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6695                             let expr4_0 =
6696                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6697                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6698                             return Some(expr5_0);
6699                         }
6700                         &Opcode::Sextend => {
6701                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6702                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6703                                 if let &InstructionData::BinaryImm8 {
6704                                     opcode: ref pattern9_0,
6705                                     arg: pattern9_1,
6706                                     imm: pattern9_2,
6707                                 } = &pattern8_0
6708                                 {
6709                                     if let &Opcode::Extractlane = pattern9_0 {
6710                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6711                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6712                                         // Rule at src/isa/aarch64/lower.isle line 519.
6713                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6714                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6715                                         let expr2_0 = constructor_size_from_ty(ctx, pattern3_0)?;
6716                                         let expr3_0 = constructor_mov_from_vec_signed(
6717                                             ctx,
6718                                             expr0_0,
6719                                             pattern12_0,
6720                                             &expr1_0,
6721                                             &expr2_0,
6722                                         )?;
6723                                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6724                                         return Some(expr4_0);
6725                                     }
6726                                 }
6727                             }
6728                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6729                             // Rule at src/isa/aarch64/lower.isle line 514.
6730                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6731                             let expr1_0: bool = true;
6732                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6733                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6734                             let expr4_0 =
6735                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6736                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6737                             return Some(expr5_0);
6738                         }
6739                         _ => {}
6740                     }
6741                 }
6742                 _ => {}
6743             }
6744         }
6745         if let Some(pattern3_0) = C::ty_vec128(ctx, pattern2_0) {
6746             let pattern4_0 = C::inst_data(ctx, pattern0_0);
6747             match &pattern4_0 {
6748                 &InstructionData::Binary {
6749                     opcode: ref pattern5_0,
6750                     args: ref pattern5_1,
6751                 } => {
6752                     match pattern5_0 {
6753                         &Opcode::UaddSat => {
6754                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6755                             // Rule at src/isa/aarch64/lower.isle line 152.
6756                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6757                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6758                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6759                             let expr3_0 = constructor_uqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6760                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6761                             return Some(expr4_0);
6762                         }
6763                         &Opcode::SaddSat => {
6764                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6765                             // Rule at src/isa/aarch64/lower.isle line 157.
6766                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6767                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6768                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6769                             let expr3_0 = constructor_sqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6770                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6771                             return Some(expr4_0);
6772                         }
6773                         &Opcode::UsubSat => {
6774                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6775                             // Rule at src/isa/aarch64/lower.isle line 162.
6776                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6777                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6778                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6779                             let expr3_0 = constructor_uqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6780                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6781                             return Some(expr4_0);
6782                         }
6783                         &Opcode::SsubSat => {
6784                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6785                             // Rule at src/isa/aarch64/lower.isle line 167.
6786                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6787                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6788                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6789                             let expr3_0 = constructor_sqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6790                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6791                             return Some(expr4_0);
6792                         }
6793                         &Opcode::Band => {
6794                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6795                             // Rule at src/isa/aarch64/lower.isle line 597.
6796                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6797                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6798                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6799                             let expr3_0 = constructor_and_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6800                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6801                             return Some(expr4_0);
6802                         }
6803                         &Opcode::Bor => {
6804                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6805                             // Rule at src/isa/aarch64/lower.isle line 610.
6806                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6807                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6808                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6809                             let expr3_0 = constructor_orr_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6810                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6811                             return Some(expr4_0);
6812                         }
6813                         &Opcode::Bxor => {
6814                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6815                             // Rule at src/isa/aarch64/lower.isle line 623.
6816                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6817                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6818                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6819                             let expr3_0 = constructor_eor_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6820                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6821                             return Some(expr4_0);
6822                         }
6823                         &Opcode::BandNot => {
6824                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6825                             // Rule at src/isa/aarch64/lower.isle line 636.
6826                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6827                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6828                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6829                             let expr3_0 = constructor_bic_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6830                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6831                             return Some(expr4_0);
6832                         }
6833                         &Opcode::Ishl => {
6834                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6835                             // Rule at src/isa/aarch64/lower.isle line 700.
6836                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6837                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6838                             let expr2_0 = constructor_vec_dup(ctx, expr1_0, &expr0_0)?;
6839                             let expr3_0 = C::put_in_reg(ctx, pattern7_0);
6840                             let expr4_0 = constructor_sshl(ctx, expr3_0, expr2_0, &expr0_0)?;
6841                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6842                             return Some(expr5_0);
6843                         }
6844                         &Opcode::Ushr => {
6845                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6846                             // Rule at src/isa/aarch64/lower.isle line 758.
6847                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6848                             let expr1_0: Type = I32;
6849                             let expr2_0 = C::zero_reg(ctx);
6850                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6851                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6852                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6853                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6854                             let expr7_0 = constructor_ushl(ctx, expr6_0, expr5_0, &expr0_0)?;
6855                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6856                             return Some(expr8_0);
6857                         }
6858                         &Opcode::Sshr => {
6859                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6860                             // Rule at src/isa/aarch64/lower.isle line 807.
6861                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6862                             let expr1_0: Type = I32;
6863                             let expr2_0 = C::zero_reg(ctx);
6864                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6865                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6866                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6867                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6868                             let expr7_0 = constructor_sshl(ctx, expr6_0, expr5_0, &expr0_0)?;
6869                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6870                             return Some(expr8_0);
6871                         }
6872                         _ => {}
6873                     }
6874                 }
6875                 &InstructionData::Unary {
6876                     opcode: ref pattern5_0,
6877                     arg: pattern5_1,
6878                 } => {
6879                     match pattern5_0 {
6880                         &Opcode::Ineg => {
6881                             // Rule at src/isa/aarch64/lower.isle line 177.
6882                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6883                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6884                             let expr2_0 = constructor_neg(ctx, expr0_0, &expr1_0)?;
6885                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6886                             return Some(expr3_0);
6887                         }
6888                         &Opcode::Bnot => {
6889                             // Rule at src/isa/aarch64/lower.isle line 584.
6890                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6891                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6892                             let expr2_0 = constructor_not(ctx, expr0_0, &expr1_0)?;
6893                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6894                             return Some(expr3_0);
6895                         }
6896                         _ => {}
6897                     }
6898                 }
6899                 _ => {}
6900             }
6901             if let Some(()) = C::not_i64x2(ctx, pattern3_0) {
6902                 let pattern5_0 = C::inst_data(ctx, pattern0_0);
6903                 if let &InstructionData::Binary {
6904                     opcode: ref pattern6_0,
6905                     args: ref pattern6_1,
6906                 } = &pattern5_0
6907                 {
6908                     if let &Opcode::Imul = pattern6_0 {
6909                         let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
6910                         // Rule at src/isa/aarch64/lower.isle line 215.
6911                         let expr0_0 = C::put_in_reg(ctx, pattern8_0);
6912                         let expr1_0 = C::put_in_reg(ctx, pattern8_1);
6913                         let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6914                         let expr3_0 = constructor_mul(ctx, expr0_0, expr1_0, &expr2_0)?;
6915                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6916                         return Some(expr4_0);
6917                     }
6918                 }
6919             }
6920         }
6921         if let Some(pattern3_0) = C::valid_atomic_transaction(ctx, pattern2_0) {
6922             let pattern4_0 = C::inst_data(ctx, pattern0_0);
6923             if let &InstructionData::AtomicRmw {
6924                 opcode: ref pattern5_0,
6925                 args: ref pattern5_1,
6926                 flags: pattern5_2,
6927                 op: ref pattern5_3,
6928             } = &pattern4_0
6929             {
6930                 if let &Opcode::AtomicRmw = pattern5_0 {
6931                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6932                     match pattern5_3 {
6933                         &AtomicRmwOp::Add => {
6934                             // Rule at src/isa/aarch64/lower.isle line 1240.
6935                             let expr0_0 = AtomicRMWLoopOp::Add;
6936                             let expr1_0 = constructor_atomic_rmw_loop(
6937                                 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0,
6938                             )?;
6939                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6940                             return Some(expr2_0);
6941                         }
6942                         &AtomicRmwOp::And => {
6943                             // Rule at src/isa/aarch64/lower.isle line 1246.
6944                             let expr0_0 = AtomicRMWLoopOp::And;
6945                             let expr1_0 = constructor_atomic_rmw_loop(
6946                                 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0,
6947                             )?;
6948                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6949                             return Some(expr2_0);
6950                         }
6951                         &AtomicRmwOp::Nand => {
6952                             // Rule at src/isa/aarch64/lower.isle line 1249.
6953                             let expr0_0 = AtomicRMWLoopOp::Nand;
6954                             let expr1_0 = constructor_atomic_rmw_loop(
6955                                 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0,
6956                             )?;
6957                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6958                             return Some(expr2_0);
6959                         }
6960                         &AtomicRmwOp::Or => {
6961                             // Rule at src/isa/aarch64/lower.isle line 1252.
6962                             let expr0_0 = AtomicRMWLoopOp::Orr;
6963                             let expr1_0 = constructor_atomic_rmw_loop(
6964                                 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0,
6965                             )?;
6966                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6967                             return Some(expr2_0);
6968                         }
6969                         &AtomicRmwOp::Smax => {
6970                             // Rule at src/isa/aarch64/lower.isle line 1261.
6971                             let expr0_0 = AtomicRMWLoopOp::Smax;
6972                             let expr1_0 = constructor_atomic_rmw_loop(
6973                                 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0,
6974                             )?;
6975                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6976                             return Some(expr2_0);
6977                         }
6978                         &AtomicRmwOp::Smin => {
6979                             // Rule at src/isa/aarch64/lower.isle line 1258.
6980                             let expr0_0 = AtomicRMWLoopOp::Smin;
6981                             let expr1_0 = constructor_atomic_rmw_loop(
6982                                 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0,
6983                             )?;
6984                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6985                             return Some(expr2_0);
6986                         }
6987                         &AtomicRmwOp::Sub => {
6988                             // Rule at src/isa/aarch64/lower.isle line 1243.
6989                             let expr0_0 = AtomicRMWLoopOp::Sub;
6990                             let expr1_0 = constructor_atomic_rmw_loop(
6991                                 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0,
6992                             )?;
6993                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6994                             return Some(expr2_0);
6995                         }
6996                         &AtomicRmwOp::Umax => {
6997                             // Rule at src/isa/aarch64/lower.isle line 1267.
6998                             let expr0_0 = AtomicRMWLoopOp::Umax;
6999                             let expr1_0 = constructor_atomic_rmw_loop(
7000                                 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0,
7001                             )?;
7002                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
7003                             return Some(expr2_0);
7004                         }
7005                         &AtomicRmwOp::Umin => {
7006                             // Rule at src/isa/aarch64/lower.isle line 1264.
7007                             let expr0_0 = AtomicRMWLoopOp::Umin;
7008                             let expr1_0 = constructor_atomic_rmw_loop(
7009                                 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0,
7010                             )?;
7011                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
7012                             return Some(expr2_0);
7013                         }
7014                         &AtomicRmwOp::Xchg => {
7015                             // Rule at src/isa/aarch64/lower.isle line 1270.
7016                             let expr0_0 = AtomicRMWLoopOp::Xchg;
7017                             let expr1_0 = constructor_atomic_rmw_loop(
7018                                 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0,
7019                             )?;
7020                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
7021                             return Some(expr2_0);
7022                         }
7023                         &AtomicRmwOp::Xor => {
7024                             // Rule at src/isa/aarch64/lower.isle line 1255.
7025                             let expr0_0 = AtomicRMWLoopOp::Eor;
7026                             let expr1_0 = constructor_atomic_rmw_loop(
7027                                 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0,
7028                             )?;
7029                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
7030                             return Some(expr2_0);
7031                         }
7032                         _ => {}
7033                     }
7034                 }
7035             }
7036         }
7037     }
7038     return None;
7039 }
7040 
7041 // Generated as internal constructor for term put_nonzero_in_reg_zext64.
7042 pub fn constructor_put_nonzero_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
7043     let pattern0_0 = arg0;
7044     let pattern1_0 = C::value_type(ctx, pattern0_0);
7045     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
7046         let pattern3_0 = C::inst_data(ctx, pattern2_0);
7047         if let &InstructionData::UnaryImm {
7048             opcode: ref pattern4_0,
7049             imm: pattern4_1,
7050         } = &pattern3_0
7051         {
7052             if let &Opcode::Iconst = pattern4_0 {
7053                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
7054                     // Rule at src/isa/aarch64/lower.isle line 400.
7055                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
7056                     return Some(expr0_0);
7057                 }
7058             }
7059         }
7060     }
7061     // Rule at src/isa/aarch64/lower.isle line 395.
7062     let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern0_0)?;
7063     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
7064     return Some(expr1_0);
7065 }
7066 
7067 // Generated as internal constructor for term put_nonzero_in_reg_sext64.
7068 pub fn constructor_put_nonzero_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
7069     let pattern0_0 = arg0;
7070     let pattern1_0 = C::value_type(ctx, pattern0_0);
7071     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
7072         let pattern3_0 = C::inst_data(ctx, pattern2_0);
7073         if let &InstructionData::UnaryImm {
7074             opcode: ref pattern4_0,
7075             imm: pattern4_1,
7076         } = &pattern3_0
7077         {
7078             if let &Opcode::Iconst = pattern4_0 {
7079                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
7080                     // Rule at src/isa/aarch64/lower.isle line 446.
7081                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
7082                     return Some(expr0_0);
7083                 }
7084             }
7085         }
7086     }
7087     // Rule at src/isa/aarch64/lower.isle line 441.
7088     let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern0_0)?;
7089     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
7090     return Some(expr1_0);
7091 }
7092 
7093 // Generated as internal constructor for term lower_shl128.
7094 pub fn constructor_lower_shl128<C: Context>(
7095     ctx: &mut C,
7096     arg0: ValueRegs,
7097     arg1: Reg,
7098 ) -> Option<ValueRegs> {
7099     let pattern0_0 = arg0;
7100     let pattern1_0 = arg1;
7101     // Rule at src/isa/aarch64/lower.isle line 683.
7102     let expr0_0: usize = 0;
7103     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
7104     let expr2_0: usize = 1;
7105     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
7106     let expr4_0: Type = I64;
7107     let expr5_0 = constructor_lsl(ctx, expr4_0, expr1_0, pattern1_0)?;
7108     let expr6_0: Type = I64;
7109     let expr7_0 = constructor_lsl(ctx, expr6_0, expr3_0, pattern1_0)?;
7110     let expr8_0: Type = I32;
7111     let expr9_0 = C::zero_reg(ctx);
7112     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
7113     let expr11_0: Type = I64;
7114     let expr12_0: Type = I64;
7115     let expr13_0: u8 = 1;
7116     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
7117     let expr15_0 = constructor_lsr_imm(ctx, expr12_0, expr1_0, expr14_0)?;
7118     let expr16_0 = constructor_lsr(ctx, expr11_0, expr15_0, expr10_0)?;
7119     let expr17_0: Type = I64;
7120     let expr18_0 = constructor_orr(ctx, expr17_0, expr7_0, expr16_0)?;
7121     let expr19_0: Type = I64;
7122     let expr20_0: Type = I64;
7123     let expr21_0: u64 = 64;
7124     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
7125     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
7126     let expr24_0 = Cond::Ne;
7127     let expr25_0 = C::zero_reg(ctx);
7128     let expr26_0 = constructor_csel(ctx, &expr24_0, expr25_0, expr5_0)?;
7129     let expr27_0 = Cond::Ne;
7130     let expr28_0 = constructor_csel(ctx, &expr27_0, expr5_0, expr18_0)?;
7131     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr26_0, &expr28_0)?;
7132     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
7133     return Some(expr30_0);
7134 }
7135 
7136 // Generated as internal constructor for term do_shift.
7137 pub fn constructor_do_shift<C: Context>(
7138     ctx: &mut C,
7139     arg0: &ALUOp,
7140     arg1: Type,
7141     arg2: Reg,
7142     arg3: Value,
7143 ) -> Option<Reg> {
7144     let pattern0_0 = arg0;
7145     let pattern1_0 = arg1;
7146     let pattern2_0 = arg2;
7147     let pattern3_0 = arg3;
7148     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
7149         let pattern5_0 = C::inst_data(ctx, pattern4_0);
7150         if let &InstructionData::UnaryImm {
7151             opcode: ref pattern6_0,
7152             imm: pattern6_1,
7153         } = &pattern5_0
7154         {
7155             if let &Opcode::Iconst = pattern6_0 {
7156                 let mut closure8 = || {
7157                     return Some(pattern1_0);
7158                 };
7159                 if let Some(pattern8_0) = closure8() {
7160                     if let Some(pattern9_0) = C::imm_shift_from_imm64(ctx, pattern6_1, pattern8_0) {
7161                         // Rule at src/isa/aarch64/lower.isle line 740.
7162                         let expr0_0 = constructor_alu_rr_imm_shift(
7163                             ctx, pattern0_0, pattern1_0, pattern2_0, pattern9_0,
7164                         )?;
7165                         return Some(expr0_0);
7166                     }
7167                 }
7168             }
7169         }
7170     }
7171     let pattern0_0 = arg0;
7172     let pattern1_0 = arg1;
7173     if pattern1_0 == I32 {
7174         let pattern3_0 = arg2;
7175         let pattern4_0 = arg3;
7176         // Rule at src/isa/aarch64/lower.isle line 731.
7177         let expr0_0: Type = I32;
7178         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
7179         let expr2_0: usize = 0;
7180         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
7181         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
7182         return Some(expr4_0);
7183     }
7184     if pattern1_0 == I64 {
7185         let pattern3_0 = arg2;
7186         let pattern4_0 = arg3;
7187         // Rule at src/isa/aarch64/lower.isle line 732.
7188         let expr0_0: Type = I64;
7189         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
7190         let expr2_0: usize = 0;
7191         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
7192         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
7193         return Some(expr4_0);
7194     }
7195     if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
7196         let pattern3_0 = arg2;
7197         let pattern4_0 = arg3;
7198         // Rule at src/isa/aarch64/lower.isle line 722.
7199         let expr0_0 = C::put_in_regs(ctx, pattern4_0);
7200         let expr1_0: usize = 0;
7201         let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
7202         let expr3_0: Type = I32;
7203         let expr4_0 = C::shift_mask(ctx, pattern2_0);
7204         let expr5_0 = constructor_and_imm(ctx, expr3_0, expr2_0, expr4_0)?;
7205         let expr6_0: Type = I32;
7206         let expr7_0 = constructor_alu_rrr(ctx, pattern0_0, expr6_0, pattern3_0, expr5_0)?;
7207         return Some(expr7_0);
7208     }
7209     return None;
7210 }
7211 
7212 // Generated as internal constructor for term lower_ushr128.
7213 pub fn constructor_lower_ushr128<C: Context>(
7214     ctx: &mut C,
7215     arg0: ValueRegs,
7216     arg1: Reg,
7217 ) -> Option<ValueRegs> {
7218     let pattern0_0 = arg0;
7219     let pattern1_0 = arg1;
7220     // Rule at src/isa/aarch64/lower.isle line 773.
7221     let expr0_0: usize = 0;
7222     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
7223     let expr2_0: usize = 1;
7224     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
7225     let expr4_0: Type = I64;
7226     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
7227     let expr6_0: Type = I64;
7228     let expr7_0 = constructor_lsr(ctx, expr6_0, expr3_0, pattern1_0)?;
7229     let expr8_0: Type = I32;
7230     let expr9_0 = C::zero_reg(ctx);
7231     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
7232     let expr11_0: Type = I64;
7233     let expr12_0: Type = I64;
7234     let expr13_0: u8 = 1;
7235     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
7236     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
7237     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
7238     let expr17_0: Type = I64;
7239     let expr18_0 = constructor_orr(ctx, expr17_0, expr5_0, expr16_0)?;
7240     let expr19_0: Type = I64;
7241     let expr20_0: Type = I64;
7242     let expr21_0: u64 = 64;
7243     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
7244     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
7245     let expr24_0 = Cond::Ne;
7246     let expr25_0 = constructor_csel(ctx, &expr24_0, expr7_0, expr18_0)?;
7247     let expr26_0 = Cond::Ne;
7248     let expr27_0 = C::zero_reg(ctx);
7249     let expr28_0 = constructor_csel(ctx, &expr26_0, expr27_0, expr7_0)?;
7250     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr25_0, &expr28_0)?;
7251     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
7252     return Some(expr30_0);
7253 }
7254 
7255 // Generated as internal constructor for term lower_sshr128.
7256 pub fn constructor_lower_sshr128<C: Context>(
7257     ctx: &mut C,
7258     arg0: ValueRegs,
7259     arg1: Reg,
7260 ) -> Option<ValueRegs> {
7261     let pattern0_0 = arg0;
7262     let pattern1_0 = arg1;
7263     // Rule at src/isa/aarch64/lower.isle line 823.
7264     let expr0_0: usize = 0;
7265     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
7266     let expr2_0: usize = 1;
7267     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
7268     let expr4_0: Type = I64;
7269     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
7270     let expr6_0: Type = I64;
7271     let expr7_0 = constructor_asr(ctx, expr6_0, expr3_0, pattern1_0)?;
7272     let expr8_0: Type = I32;
7273     let expr9_0 = C::zero_reg(ctx);
7274     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
7275     let expr11_0: Type = I64;
7276     let expr12_0: Type = I64;
7277     let expr13_0: u8 = 1;
7278     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
7279     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
7280     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
7281     let expr17_0: Type = I64;
7282     let expr18_0: u8 = 63;
7283     let expr19_0 = C::imm_shift_from_u8(ctx, expr18_0);
7284     let expr20_0 = constructor_asr_imm(ctx, expr17_0, expr3_0, expr19_0)?;
7285     let expr21_0: Type = I64;
7286     let expr22_0 = constructor_orr(ctx, expr21_0, expr5_0, expr16_0)?;
7287     let expr23_0: Type = I64;
7288     let expr24_0: Type = I64;
7289     let expr25_0: u64 = 64;
7290     let expr26_0 = C::u64_into_imm_logic(ctx, expr24_0, expr25_0);
7291     let expr27_0 = constructor_tst_imm(ctx, expr23_0, pattern1_0, expr26_0)?;
7292     let expr28_0 = Cond::Ne;
7293     let expr29_0 = constructor_csel(ctx, &expr28_0, expr7_0, expr22_0)?;
7294     let expr30_0 = Cond::Ne;
7295     let expr31_0 = constructor_csel(ctx, &expr30_0, expr20_0, expr7_0)?;
7296     let expr32_0 = constructor_consumes_flags_concat(ctx, &expr29_0, &expr31_0)?;
7297     let expr33_0 = constructor_with_flags(ctx, &expr27_0, &expr32_0)?;
7298     return Some(expr33_0);
7299 }
7300 
7301 // Generated as internal constructor for term small_rotr.
7302 pub fn constructor_small_rotr<C: Context>(
7303     ctx: &mut C,
7304     arg0: Type,
7305     arg1: Reg,
7306     arg2: Reg,
7307 ) -> Option<Reg> {
7308     let pattern0_0 = arg0;
7309     let pattern1_0 = arg1;
7310     let pattern2_0 = arg2;
7311     // Rule at src/isa/aarch64/lower.isle line 933.
7312     let expr0_0: Type = I32;
7313     let expr1_0 = C::rotr_mask(ctx, pattern0_0);
7314     let expr2_0 = constructor_and_imm(ctx, expr0_0, pattern2_0, expr1_0)?;
7315     let expr3_0: Type = I32;
7316     let expr4_0 = C::ty_bits(ctx, pattern0_0);
7317     let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
7318     let expr6_0 = constructor_sub_imm(ctx, expr3_0, expr2_0, expr5_0)?;
7319     let expr7_0: Type = I32;
7320     let expr8_0 = C::zero_reg(ctx);
7321     let expr9_0 = constructor_sub(ctx, expr7_0, expr8_0, expr6_0)?;
7322     let expr10_0: Type = I32;
7323     let expr11_0 = constructor_lsr(ctx, expr10_0, pattern1_0, expr2_0)?;
7324     let expr12_0: Type = I32;
7325     let expr13_0 = constructor_lsl(ctx, expr12_0, pattern1_0, expr9_0)?;
7326     let expr14_0: Type = I32;
7327     let expr15_0 = constructor_orr(ctx, expr14_0, expr13_0, expr11_0)?;
7328     return Some(expr15_0);
7329 }
7330 
7331 // Generated as internal constructor for term small_rotr_imm.
7332 pub fn constructor_small_rotr_imm<C: Context>(
7333     ctx: &mut C,
7334     arg0: Type,
7335     arg1: Reg,
7336     arg2: ImmShift,
7337 ) -> Option<Reg> {
7338     let pattern0_0 = arg0;
7339     let pattern1_0 = arg1;
7340     let pattern2_0 = arg2;
7341     // Rule at src/isa/aarch64/lower.isle line 954.
7342     let expr0_0: Type = I32;
7343     let expr1_0 = constructor_lsr_imm(ctx, expr0_0, pattern1_0, pattern2_0)?;
7344     let expr2_0: Type = I32;
7345     let expr3_0 = C::rotr_opposite_amount(ctx, pattern0_0, pattern2_0);
7346     let expr4_0 = constructor_lsl_imm(ctx, expr2_0, pattern1_0, expr3_0)?;
7347     let expr5_0: Type = I32;
7348     let expr6_0 = constructor_orr(ctx, expr5_0, expr4_0, expr1_0)?;
7349     return Some(expr6_0);
7350 }
7351 
7352 // Generated as internal constructor for term lower_clz128.
7353 pub fn constructor_lower_clz128<C: Context>(ctx: &mut C, arg0: ValueRegs) -> Option<ValueRegs> {
7354     let pattern0_0 = arg0;
7355     // Rule at src/isa/aarch64/lower.isle line 1019.
7356     let expr0_0: Type = I64;
7357     let expr1_0: usize = 1;
7358     let expr2_0 = C::value_regs_get(ctx, pattern0_0, expr1_0);
7359     let expr3_0 = constructor_a64_clz(ctx, expr0_0, expr2_0)?;
7360     let expr4_0: Type = I64;
7361     let expr5_0: usize = 0;
7362     let expr6_0 = C::value_regs_get(ctx, pattern0_0, expr5_0);
7363     let expr7_0 = constructor_a64_clz(ctx, expr4_0, expr6_0)?;
7364     let expr8_0: Type = I64;
7365     let expr9_0: u8 = 6;
7366     let expr10_0 = C::imm_shift_from_u8(ctx, expr9_0);
7367     let expr11_0 = constructor_lsr_imm(ctx, expr8_0, expr3_0, expr10_0)?;
7368     let expr12_0: Type = I64;
7369     let expr13_0 = constructor_madd(ctx, expr12_0, expr7_0, expr11_0, expr3_0)?;
7370     let expr14_0: Type = I64;
7371     let expr15_0: u64 = 0;
7372     let expr16_0 = constructor_imm(ctx, expr14_0, expr15_0)?;
7373     let expr17_0 = C::value_regs(ctx, expr13_0, expr16_0);
7374     return Some(expr17_0);
7375 }
7376