1 // GENERATED BY ISLE. DO NOT EDIT!
2 //
3 // Generated automatically from the instruction-selection DSL code in:
4 // - src/clif.isle
5 // - src/prelude.isle
6 // - src/isa/aarch64/inst.isle
7 // - src/isa/aarch64/lower.isle
8 
9 #![allow(dead_code, unreachable_code, unreachable_patterns)]
10 #![allow(unused_imports, unused_variables, non_snake_case)]
11 #![allow(irrefutable_let_patterns)]
12 
13 use super::*; // Pulls in all external types.
14 
15 /// Context during lowering: an implementation of this trait
16 /// must be provided with all external constructors and extractors.
17 /// A mutable borrow is passed along through all lowering logic.
18 pub trait Context {
19     fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
20     fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
21     fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
22     fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
23     fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
24     fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
25     fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
26     fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
27     fn value_regs_invalid(&mut self) -> ValueRegs;
28     fn output_none(&mut self) -> InstOutput;
29     fn output(&mut self, arg0: ValueRegs) -> InstOutput;
30     fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput;
31     fn output_builder_new(&mut self) -> InstOutputBuilder;
32     fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit;
33     fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput;
34     fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
35     fn invalid_reg(&mut self) -> Reg;
36     fn put_in_reg(&mut self, arg0: Value) -> Reg;
37     fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
38     fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
39     fn u8_as_u64(&mut self, arg0: u8) -> u64;
40     fn u16_as_u64(&mut self, arg0: u16) -> u64;
41     fn u32_as_u64(&mut self, arg0: u32) -> u64;
42     fn i64_as_u64(&mut self, arg0: i64) -> u64;
43     fn u64_add(&mut self, arg0: u64, arg1: u64) -> u64;
44     fn u64_sub(&mut self, arg0: u64, arg1: u64) -> u64;
45     fn u64_and(&mut self, arg0: u64, arg1: u64) -> u64;
46     fn ty_bits(&mut self, arg0: Type) -> u8;
47     fn ty_bits_u16(&mut self, arg0: Type) -> u16;
48     fn ty_bits_u64(&mut self, arg0: Type) -> u64;
49     fn ty_mask(&mut self, arg0: Type) -> u64;
50     fn ty_bytes(&mut self, arg0: Type) -> u16;
51     fn lane_type(&mut self, arg0: Type) -> Type;
52     fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
53     fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
54     fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
55     fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
56     fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
57     fn ty_int_bool_64(&mut self, arg0: Type) -> Option<Type>;
58     fn ty_int_bool_ref_64(&mut self, arg0: Type) -> Option<Type>;
59     fn ty_int_bool_128(&mut self, arg0: Type) -> Option<Type>;
60     fn ty_scalar_float(&mut self, arg0: Type) -> Option<Type>;
61     fn ty_vec128(&mut self, arg0: Type) -> Option<Type>;
62     fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
63     fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
64     fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>;
65     fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>;
66     fn value_slice_len(&mut self, arg0: ValueSlice) -> usize;
67     fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value;
68     fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
69     fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
70     fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
71     fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
72     fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
73     fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
74     fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
75     fn first_result(&mut self, arg0: Inst) -> Option<Value>;
76     fn inst_data(&mut self, arg0: Inst) -> InstructionData;
77     fn value_type(&mut self, arg0: Value) -> Type;
78     fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
79     fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
80     fn offset32_to_u32(&mut self, arg0: Offset32) -> u32;
81     fn emit(&mut self, arg0: &MInst) -> Unit;
82     fn trap_code_division_by_zero(&mut self) -> TrapCode;
83     fn trap_code_integer_overflow(&mut self) -> TrapCode;
84     fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
85     fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
86     fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
87     fn symbol_value_data(
88         &mut self,
89         arg0: GlobalValue,
90     ) -> Option<(ExternalName, RelocDistance, i64)>;
91     fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
92     fn move_wide_const_from_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
93     fn move_wide_const_from_negated_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
94     fn imm_logic_from_u64(&mut self, arg0: u64, arg1: Type) -> Option<ImmLogic>;
95     fn imm_logic_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmLogic>;
96     fn imm_shift_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmShift>;
97     fn imm_shift_from_u8(&mut self, arg0: u8) -> ImmShift;
98     fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12>;
99     fn u8_into_uimm5(&mut self, arg0: u8) -> UImm5;
100     fn u8_into_imm12(&mut self, arg0: u8) -> Imm12;
101     fn u64_into_imm_logic(&mut self, arg0: Type, arg1: u64) -> ImmLogic;
102     fn imm12_from_negated_u64(&mut self, arg0: u64) -> Option<Imm12>;
103     fn lshl_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ShiftOpAndAmt>;
104     fn integral_ty(&mut self, arg0: Type) -> Option<Type>;
105     fn extended_value_from_value(&mut self, arg0: Value) -> Option<ExtendedValue>;
106     fn put_extended_in_reg(&mut self, arg0: &ExtendedValue) -> Reg;
107     fn get_extended_op(&mut self, arg0: &ExtendedValue) -> ExtendOp;
108     fn nzcv(&mut self, arg0: bool, arg1: bool, arg2: bool, arg3: bool) -> NZCV;
109     fn cond_br_zero(&mut self, arg0: Reg) -> CondBrKind;
110     fn cond_br_cond(&mut self, arg0: &Cond) -> CondBrKind;
111     fn zero_reg(&mut self) -> Reg;
112     fn writable_zero_reg(&mut self) -> WritableReg;
113     fn load_constant64_full(&mut self, arg0: u64) -> Reg;
114     fn sinkable_atomic_load(&mut self, arg0: Value) -> Option<SinkableAtomicLoad>;
115     fn sink_atomic_load(&mut self, arg0: &SinkableAtomicLoad) -> Reg;
116     fn zero_value_f32(&mut self, arg0: Ieee32) -> Option<Ieee32>;
117     fn zero_value_f64(&mut self, arg0: Ieee64) -> Option<Ieee64>;
118     fn float_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &FloatCC) -> VecMisc2;
119     fn float_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &FloatCC) -> VecMisc2;
120     fn fcmp_zero_cond(&mut self, arg0: &FloatCC) -> Option<FloatCC>;
121     fn fcmp_zero_cond_not_eq(&mut self, arg0: &FloatCC) -> Option<FloatCC>;
122     fn zero_value(&mut self, arg0: Imm64) -> Option<Imm64>;
123     fn int_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &IntCC) -> VecMisc2;
124     fn int_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &IntCC) -> VecMisc2;
125     fn icmp_zero_cond(&mut self, arg0: &IntCC) -> Option<IntCC>;
126     fn icmp_zero_cond_not_eq(&mut self, arg0: &IntCC) -> Option<IntCC>;
127     fn safe_divisor_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
128     fn shift_mask(&mut self, arg0: Type) -> ImmLogic;
129     fn negate_imm_shift(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
130     fn rotr_mask(&mut self, arg0: Type) -> ImmLogic;
131     fn rotr_opposite_amount(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
132 }
133 
134 /// Internal type SideEffectNoResult: defined at src/prelude.isle line 402.
135 #[derive(Clone, Debug)]
136 pub enum SideEffectNoResult {
137     Inst { inst: MInst },
138 }
139 
140 /// Internal type ProducesFlags: defined at src/prelude.isle line 418.
141 #[derive(Clone, Debug)]
142 pub enum ProducesFlags {
143     ProducesFlagsSideEffect { inst: MInst },
144     ProducesFlagsReturnsReg { inst: MInst, result: Reg },
145     ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg },
146 }
147 
148 /// Internal type ConsumesFlags: defined at src/prelude.isle line 429.
149 #[derive(Clone, Debug)]
150 pub enum ConsumesFlags {
151     ConsumesFlagsReturnsResultWithProducer {
152         inst: MInst,
153         result: Reg,
154     },
155     ConsumesFlagsReturnsReg {
156         inst: MInst,
157         result: Reg,
158     },
159     ConsumesFlagsTwiceReturnsValueRegs {
160         inst1: MInst,
161         inst2: MInst,
162         result: ValueRegs,
163     },
164     ConsumesFlagsFourTimesReturnsValueRegs {
165         inst1: MInst,
166         inst2: MInst,
167         inst3: MInst,
168         inst4: MInst,
169         result: ValueRegs,
170     },
171 }
172 
173 /// Internal type MInst: defined at src/isa/aarch64/inst.isle line 2.
174 #[derive(Clone, Debug)]
175 pub enum MInst {
176     Nop0,
177     Nop4,
178     AluRRR {
179         alu_op: ALUOp,
180         size: OperandSize,
181         rd: WritableReg,
182         rn: Reg,
183         rm: Reg,
184     },
185     AluRRRR {
186         alu_op: ALUOp3,
187         size: OperandSize,
188         rd: WritableReg,
189         rn: Reg,
190         rm: Reg,
191         ra: Reg,
192     },
193     AluRRImm12 {
194         alu_op: ALUOp,
195         size: OperandSize,
196         rd: WritableReg,
197         rn: Reg,
198         imm12: Imm12,
199     },
200     AluRRImmLogic {
201         alu_op: ALUOp,
202         size: OperandSize,
203         rd: WritableReg,
204         rn: Reg,
205         imml: ImmLogic,
206     },
207     AluRRImmShift {
208         alu_op: ALUOp,
209         size: OperandSize,
210         rd: WritableReg,
211         rn: Reg,
212         immshift: ImmShift,
213     },
214     AluRRRShift {
215         alu_op: ALUOp,
216         size: OperandSize,
217         rd: WritableReg,
218         rn: Reg,
219         rm: Reg,
220         shiftop: ShiftOpAndAmt,
221     },
222     AluRRRExtend {
223         alu_op: ALUOp,
224         size: OperandSize,
225         rd: WritableReg,
226         rn: Reg,
227         rm: Reg,
228         extendop: ExtendOp,
229     },
230     BitRR {
231         op: BitOp,
232         size: OperandSize,
233         rd: WritableReg,
234         rn: Reg,
235     },
236     ULoad8 {
237         rd: WritableReg,
238         mem: AMode,
239         flags: MemFlags,
240     },
241     SLoad8 {
242         rd: WritableReg,
243         mem: AMode,
244         flags: MemFlags,
245     },
246     ULoad16 {
247         rd: WritableReg,
248         mem: AMode,
249         flags: MemFlags,
250     },
251     SLoad16 {
252         rd: WritableReg,
253         mem: AMode,
254         flags: MemFlags,
255     },
256     ULoad32 {
257         rd: WritableReg,
258         mem: AMode,
259         flags: MemFlags,
260     },
261     SLoad32 {
262         rd: WritableReg,
263         mem: AMode,
264         flags: MemFlags,
265     },
266     ULoad64 {
267         rd: WritableReg,
268         mem: AMode,
269         flags: MemFlags,
270     },
271     Store8 {
272         rd: Reg,
273         mem: AMode,
274         flags: MemFlags,
275     },
276     Store16 {
277         rd: Reg,
278         mem: AMode,
279         flags: MemFlags,
280     },
281     Store32 {
282         rd: Reg,
283         mem: AMode,
284         flags: MemFlags,
285     },
286     Store64 {
287         rd: Reg,
288         mem: AMode,
289         flags: MemFlags,
290     },
291     StoreP64 {
292         rt: Reg,
293         rt2: Reg,
294         mem: PairAMode,
295         flags: MemFlags,
296     },
297     LoadP64 {
298         rt: WritableReg,
299         rt2: WritableReg,
300         mem: PairAMode,
301         flags: MemFlags,
302     },
303     Mov64 {
304         rd: WritableReg,
305         rm: Reg,
306     },
307     Mov32 {
308         rd: WritableReg,
309         rm: Reg,
310     },
311     MovZ {
312         rd: WritableReg,
313         imm: MoveWideConst,
314         size: OperandSize,
315     },
316     MovN {
317         rd: WritableReg,
318         imm: MoveWideConst,
319         size: OperandSize,
320     },
321     MovK {
322         rd: WritableReg,
323         imm: MoveWideConst,
324         size: OperandSize,
325     },
326     Extend {
327         rd: WritableReg,
328         rn: Reg,
329         signed: bool,
330         from_bits: u8,
331         to_bits: u8,
332     },
333     CSel {
334         rd: WritableReg,
335         cond: Cond,
336         rn: Reg,
337         rm: Reg,
338     },
339     CSet {
340         rd: WritableReg,
341         cond: Cond,
342     },
343     CSetm {
344         rd: WritableReg,
345         cond: Cond,
346     },
347     CCmpImm {
348         size: OperandSize,
349         rn: Reg,
350         imm: UImm5,
351         nzcv: NZCV,
352         cond: Cond,
353     },
354     AtomicRMWLoop {
355         ty: Type,
356         op: AtomicRmwOp,
357     },
358     AtomicRMW {
359         op: AtomicRMWOp,
360         rs: Reg,
361         rt: WritableReg,
362         rn: Reg,
363         ty: Type,
364     },
365     AtomicCAS {
366         rs: WritableReg,
367         rt: Reg,
368         rn: Reg,
369         ty: Type,
370     },
371     AtomicCASLoop {
372         ty: Type,
373     },
374     LoadAcquire {
375         access_ty: Type,
376         rt: WritableReg,
377         rn: Reg,
378     },
379     StoreRelease {
380         access_ty: Type,
381         rt: Reg,
382         rn: Reg,
383     },
384     Fence,
385     FpuMove64 {
386         rd: WritableReg,
387         rn: Reg,
388     },
389     FpuMove128 {
390         rd: WritableReg,
391         rn: Reg,
392     },
393     FpuMoveFromVec {
394         rd: WritableReg,
395         rn: Reg,
396         idx: u8,
397         size: VectorSize,
398     },
399     FpuExtend {
400         rd: WritableReg,
401         rn: Reg,
402         size: ScalarSize,
403     },
404     FpuRR {
405         fpu_op: FPUOp1,
406         rd: WritableReg,
407         rn: Reg,
408     },
409     FpuRRR {
410         fpu_op: FPUOp2,
411         rd: WritableReg,
412         rn: Reg,
413         rm: Reg,
414     },
415     FpuRRI {
416         fpu_op: FPUOpRI,
417         rd: WritableReg,
418         rn: Reg,
419     },
420     FpuRRRR {
421         fpu_op: FPUOp3,
422         rd: WritableReg,
423         rn: Reg,
424         rm: Reg,
425         ra: Reg,
426     },
427     FpuCmp32 {
428         rn: Reg,
429         rm: Reg,
430     },
431     FpuCmp64 {
432         rn: Reg,
433         rm: Reg,
434     },
435     FpuLoad32 {
436         rd: WritableReg,
437         mem: AMode,
438         flags: MemFlags,
439     },
440     FpuStore32 {
441         rd: Reg,
442         mem: AMode,
443         flags: MemFlags,
444     },
445     FpuLoad64 {
446         rd: WritableReg,
447         mem: AMode,
448         flags: MemFlags,
449     },
450     FpuStore64 {
451         rd: Reg,
452         mem: AMode,
453         flags: MemFlags,
454     },
455     FpuLoad128 {
456         rd: WritableReg,
457         mem: AMode,
458         flags: MemFlags,
459     },
460     FpuStore128 {
461         rd: Reg,
462         mem: AMode,
463         flags: MemFlags,
464     },
465     FpuLoadP64 {
466         rt: WritableReg,
467         rt2: WritableReg,
468         mem: PairAMode,
469         flags: MemFlags,
470     },
471     FpuStoreP64 {
472         rt: Reg,
473         rt2: Reg,
474         mem: PairAMode,
475         flags: MemFlags,
476     },
477     FpuLoadP128 {
478         rt: WritableReg,
479         rt2: WritableReg,
480         mem: PairAMode,
481         flags: MemFlags,
482     },
483     FpuStoreP128 {
484         rt: Reg,
485         rt2: Reg,
486         mem: PairAMode,
487         flags: MemFlags,
488     },
489     LoadFpuConst64 {
490         rd: WritableReg,
491         const_data: u64,
492     },
493     LoadFpuConst128 {
494         rd: WritableReg,
495         const_data: u128,
496     },
497     FpuToInt {
498         op: FpuToIntOp,
499         rd: WritableReg,
500         rn: Reg,
501     },
502     IntToFpu {
503         op: IntToFpuOp,
504         rd: WritableReg,
505         rn: Reg,
506     },
507     FpuCSel32 {
508         rd: WritableReg,
509         rn: Reg,
510         rm: Reg,
511         cond: Cond,
512     },
513     FpuCSel64 {
514         rd: WritableReg,
515         rn: Reg,
516         rm: Reg,
517         cond: Cond,
518     },
519     FpuRound {
520         op: FpuRoundMode,
521         rd: WritableReg,
522         rn: Reg,
523     },
524     MovToFpu {
525         rd: WritableReg,
526         rn: Reg,
527         size: ScalarSize,
528     },
529     FpuMoveFPImm {
530         rd: WritableReg,
531         imm: ASIMDFPModImm,
532         size: ScalarSize,
533     },
534     MovToVec {
535         rd: WritableReg,
536         rn: Reg,
537         idx: u8,
538         size: VectorSize,
539     },
540     MovFromVec {
541         rd: WritableReg,
542         rn: Reg,
543         idx: u8,
544         size: VectorSize,
545     },
546     MovFromVecSigned {
547         rd: WritableReg,
548         rn: Reg,
549         idx: u8,
550         size: VectorSize,
551         scalar_size: OperandSize,
552     },
553     VecDup {
554         rd: WritableReg,
555         rn: Reg,
556         size: VectorSize,
557     },
558     VecDupFromFpu {
559         rd: WritableReg,
560         rn: Reg,
561         size: VectorSize,
562     },
563     VecDupFPImm {
564         rd: WritableReg,
565         imm: ASIMDFPModImm,
566         size: VectorSize,
567     },
568     VecDupImm {
569         rd: WritableReg,
570         imm: ASIMDMovModImm,
571         invert: bool,
572         size: VectorSize,
573     },
574     VecExtend {
575         t: VecExtendOp,
576         rd: WritableReg,
577         rn: Reg,
578         high_half: bool,
579     },
580     VecMovElement {
581         rd: WritableReg,
582         rn: Reg,
583         dest_idx: u8,
584         src_idx: u8,
585         size: VectorSize,
586     },
587     VecRRLong {
588         op: VecRRLongOp,
589         rd: WritableReg,
590         rn: Reg,
591         high_half: bool,
592     },
593     VecRRNarrow {
594         op: VecRRNarrowOp,
595         rd: WritableReg,
596         rn: Reg,
597         high_half: bool,
598     },
599     VecRRPair {
600         op: VecPairOp,
601         rd: WritableReg,
602         rn: Reg,
603     },
604     VecRRRLong {
605         alu_op: VecRRRLongOp,
606         rd: WritableReg,
607         rn: Reg,
608         rm: Reg,
609         high_half: bool,
610     },
611     VecRRPairLong {
612         op: VecRRPairLongOp,
613         rd: WritableReg,
614         rn: Reg,
615     },
616     VecRRR {
617         alu_op: VecALUOp,
618         rd: WritableReg,
619         rn: Reg,
620         rm: Reg,
621         size: VectorSize,
622     },
623     VecMisc {
624         op: VecMisc2,
625         rd: WritableReg,
626         rn: Reg,
627         size: VectorSize,
628     },
629     VecLanes {
630         op: VecLanesOp,
631         rd: WritableReg,
632         rn: Reg,
633         size: VectorSize,
634     },
635     VecShiftImm {
636         op: VecShiftImmOp,
637         rd: WritableReg,
638         rn: Reg,
639         size: VectorSize,
640         imm: u8,
641     },
642     VecExtract {
643         rd: WritableReg,
644         rn: Reg,
645         rm: Reg,
646         imm4: u8,
647     },
648     VecTbl {
649         rd: WritableReg,
650         rn: Reg,
651         rm: Reg,
652         is_extension: bool,
653     },
654     VecTbl2 {
655         rd: WritableReg,
656         rn: Reg,
657         rn2: Reg,
658         rm: Reg,
659         is_extension: bool,
660     },
661     VecLoadReplicate {
662         rd: WritableReg,
663         rn: Reg,
664         size: VectorSize,
665     },
666     VecCSel {
667         rd: WritableReg,
668         rn: Reg,
669         rm: Reg,
670         cond: Cond,
671     },
672     MovToNZCV {
673         rn: Reg,
674     },
675     MovFromNZCV {
676         rd: WritableReg,
677     },
678     Call {
679         info: BoxCallInfo,
680     },
681     CallInd {
682         info: BoxCallIndInfo,
683     },
684     Ret {
685         rets: VecReg,
686     },
687     EpiloguePlaceholder,
688     Jump {
689         dest: BranchTarget,
690     },
691     CondBr {
692         taken: BranchTarget,
693         not_taken: BranchTarget,
694         kind: CondBrKind,
695     },
696     TrapIf {
697         kind: CondBrKind,
698         trap_code: TrapCode,
699     },
700     IndirectBr {
701         rn: Reg,
702         targets: VecMachLabel,
703     },
704     Brk,
705     Udf {
706         trap_code: TrapCode,
707     },
708     Adr {
709         rd: WritableReg,
710         off: i32,
711     },
712     Word4 {
713         data: u32,
714     },
715     Word8 {
716         data: u64,
717     },
718     JTSequence {
719         info: BoxJTSequenceInfo,
720         ridx: Reg,
721         rtmp1: WritableReg,
722         rtmp2: WritableReg,
723     },
724     LoadExtName {
725         rd: WritableReg,
726         name: BoxExternalName,
727         offset: i64,
728     },
729     LoadAddr {
730         rd: WritableReg,
731         mem: AMode,
732     },
733     VirtualSPOffsetAdj {
734         offset: i64,
735     },
736     EmitIsland {
737         needed_space: CodeOffset,
738     },
739     ElfTlsGetAddr {
740         symbol: ExternalName,
741     },
742     Unwind {
743         inst: UnwindInst,
744     },
745     DummyUse {
746         reg: Reg,
747     },
748 }
749 
750 /// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 796.
751 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
752 pub enum ALUOp {
753     Add,
754     Sub,
755     Orr,
756     OrrNot,
757     And,
758     AndS,
759     AndNot,
760     Eor,
761     EorNot,
762     AddS,
763     SubS,
764     SMulH,
765     UMulH,
766     SDiv,
767     UDiv,
768     RotR,
769     Lsr,
770     Asr,
771     Lsl,
772     Adc,
773     AdcS,
774     Sbc,
775     SbcS,
776 }
777 
778 /// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 834.
779 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
780 pub enum ALUOp3 {
781     MAdd,
782     MSub,
783 }
784 
785 /// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 873.
786 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
787 pub enum BitOp {
788     RBit,
789     Clz,
790     Cls,
791 }
792 
793 /// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 940.
794 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
795 pub enum FPUOp1 {
796     Abs32,
797     Abs64,
798     Neg32,
799     Neg64,
800     Sqrt32,
801     Sqrt64,
802     Cvt32To64,
803     Cvt64To32,
804 }
805 
806 /// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 953.
807 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
808 pub enum FPUOp2 {
809     Add32,
810     Add64,
811     Sub32,
812     Sub64,
813     Mul32,
814     Mul64,
815     Div32,
816     Div64,
817     Max32,
818     Max64,
819     Min32,
820     Min64,
821     Sqadd64,
822     Uqadd64,
823     Sqsub64,
824     Uqsub64,
825 }
826 
827 /// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 978.
828 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
829 pub enum FPUOp3 {
830     MAdd32,
831     MAdd64,
832 }
833 
834 /// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 985.
835 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
836 pub enum FpuToIntOp {
837     F32ToU32,
838     F32ToI32,
839     F32ToU64,
840     F32ToI64,
841     F64ToU32,
842     F64ToI32,
843     F64ToU64,
844     F64ToI64,
845 }
846 
847 /// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 998.
848 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
849 pub enum IntToFpuOp {
850     U32ToF32,
851     I32ToF32,
852     U32ToF64,
853     I32ToF64,
854     U64ToF32,
855     I64ToF32,
856     U64ToF64,
857     I64ToF64,
858 }
859 
860 /// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 1012.
861 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
862 pub enum FpuRoundMode {
863     Minus32,
864     Minus64,
865     Plus32,
866     Plus64,
867     Zero32,
868     Zero64,
869     Nearest32,
870     Nearest64,
871 }
872 
873 /// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 1025.
874 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
875 pub enum VecExtendOp {
876     Sxtl8,
877     Sxtl16,
878     Sxtl32,
879     Uxtl8,
880     Uxtl16,
881     Uxtl32,
882 }
883 
884 /// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1042.
885 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
886 pub enum VecALUOp {
887     Sqadd,
888     Uqadd,
889     Sqsub,
890     Uqsub,
891     Cmeq,
892     Cmge,
893     Cmgt,
894     Cmhs,
895     Cmhi,
896     Fcmeq,
897     Fcmgt,
898     Fcmge,
899     And,
900     Bic,
901     Orr,
902     Eor,
903     Bsl,
904     Umaxp,
905     Add,
906     Sub,
907     Mul,
908     Sshl,
909     Ushl,
910     Umin,
911     Smin,
912     Umax,
913     Smax,
914     Urhadd,
915     Fadd,
916     Fsub,
917     Fdiv,
918     Fmax,
919     Fmin,
920     Fmul,
921     Addp,
922     Zip1,
923     Sqrdmulh,
924 }
925 
926 /// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1121.
927 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
928 pub enum VecMisc2 {
929     Not,
930     Neg,
931     Abs,
932     Fabs,
933     Fneg,
934     Fsqrt,
935     Rev64,
936     Fcvtzs,
937     Fcvtzu,
938     Scvtf,
939     Ucvtf,
940     Frintn,
941     Frintz,
942     Frintm,
943     Frintp,
944     Cnt,
945     Cmeq0,
946     Cmge0,
947     Cmgt0,
948     Cmle0,
949     Cmlt0,
950     Fcmeq0,
951     Fcmge0,
952     Fcmgt0,
953     Fcmle0,
954     Fcmlt0,
955 }
956 
957 /// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1178.
958 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
959 pub enum VecRRLongOp {
960     Fcvtl16,
961     Fcvtl32,
962     Shll8,
963     Shll16,
964     Shll32,
965 }
966 
967 /// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1193.
968 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
969 pub enum VecRRNarrowOp {
970     Xtn16,
971     Xtn32,
972     Xtn64,
973     Sqxtn16,
974     Sqxtn32,
975     Sqxtn64,
976     Sqxtun16,
977     Sqxtun32,
978     Sqxtun64,
979     Uqxtn16,
980     Uqxtn32,
981     Uqxtn64,
982     Fcvtn32,
983     Fcvtn64,
984 }
985 
986 /// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1225.
987 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
988 pub enum VecRRRLongOp {
989     Smull8,
990     Smull16,
991     Smull32,
992     Umull8,
993     Umull16,
994     Umull32,
995     Umlal8,
996     Umlal16,
997     Umlal32,
998 }
999 
1000 /// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1242.
1001 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1002 pub enum VecPairOp {
1003     Addp,
1004 }
1005 
1006 /// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1250.
1007 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1008 pub enum VecRRPairLongOp {
1009     Saddlp8,
1010     Saddlp16,
1011     Uaddlp8,
1012     Uaddlp16,
1013 }
1014 
1015 /// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1261.
1016 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1017 pub enum VecLanesOp {
1018     Addv,
1019     Uminv,
1020 }
1021 
1022 /// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1270.
1023 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1024 pub enum VecShiftImmOp {
1025     Shl,
1026     Ushr,
1027     Sshr,
1028 }
1029 
1030 /// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1281.
1031 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1032 pub enum AtomicRMWOp {
1033     Add,
1034     Clr,
1035     Eor,
1036     Set,
1037     Smax,
1038     Smin,
1039     Umax,
1040     Umin,
1041 }
1042 
1043 // Generated as internal constructor for term output_reg.
1044 pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
1045     let pattern0_0 = arg0;
1046     // Rule at src/prelude.isle line 86.
1047     let expr0_0 = C::value_reg(ctx, pattern0_0);
1048     let expr1_0 = C::output(ctx, expr0_0);
1049     return Some(expr1_0);
1050 }
1051 
1052 // Generated as internal constructor for term output_value.
1053 pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> {
1054     let pattern0_0 = arg0;
1055     // Rule at src/prelude.isle line 90.
1056     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1057     let expr1_0 = C::output(ctx, expr0_0);
1058     return Some(expr1_0);
1059 }
1060 
1061 // Generated as internal constructor for term temp_reg.
1062 pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
1063     let pattern0_0 = arg0;
1064     // Rule at src/prelude.isle line 110.
1065     let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
1066     let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
1067     return Some(expr1_0);
1068 }
1069 
1070 // Generated as internal constructor for term lo_reg.
1071 pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
1072     let pattern0_0 = arg0;
1073     // Rule at src/prelude.isle line 145.
1074     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1075     let expr1_0: usize = 0;
1076     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1077     return Some(expr2_0);
1078 }
1079 
1080 // Generated as internal constructor for term side_effect.
1081 pub fn constructor_side_effect<C: Context>(
1082     ctx: &mut C,
1083     arg0: &SideEffectNoResult,
1084 ) -> Option<InstOutput> {
1085     let pattern0_0 = arg0;
1086     if let &SideEffectNoResult::Inst {
1087         inst: ref pattern1_0,
1088     } = pattern0_0
1089     {
1090         // Rule at src/prelude.isle line 407.
1091         let expr0_0 = C::emit(ctx, pattern1_0);
1092         let expr1_0 = C::output_none(ctx);
1093         return Some(expr1_0);
1094     }
1095     return None;
1096 }
1097 
1098 // Generated as internal constructor for term produces_flags_get_reg.
1099 pub fn constructor_produces_flags_get_reg<C: Context>(
1100     ctx: &mut C,
1101     arg0: &ProducesFlags,
1102 ) -> Option<Reg> {
1103     let pattern0_0 = arg0;
1104     if let &ProducesFlags::ProducesFlagsReturnsReg {
1105         inst: ref pattern1_0,
1106         result: pattern1_1,
1107     } = pattern0_0
1108     {
1109         // Rule at src/prelude.isle line 445.
1110         return Some(pattern1_1);
1111     }
1112     return None;
1113 }
1114 
1115 // Generated as internal constructor for term produces_flags_ignore.
1116 pub fn constructor_produces_flags_ignore<C: Context>(
1117     ctx: &mut C,
1118     arg0: &ProducesFlags,
1119 ) -> Option<ProducesFlags> {
1120     let pattern0_0 = arg0;
1121     match pattern0_0 {
1122         &ProducesFlags::ProducesFlagsReturnsReg {
1123             inst: ref pattern1_0,
1124             result: pattern1_1,
1125         } => {
1126             // Rule at src/prelude.isle line 450.
1127             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1128                 inst: pattern1_0.clone(),
1129             };
1130             return Some(expr0_0);
1131         }
1132         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1133             inst: ref pattern1_0,
1134             result: pattern1_1,
1135         } => {
1136             // Rule at src/prelude.isle line 452.
1137             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1138                 inst: pattern1_0.clone(),
1139             };
1140             return Some(expr0_0);
1141         }
1142         _ => {}
1143     }
1144     return None;
1145 }
1146 
1147 // Generated as internal constructor for term consumes_flags_concat.
1148 pub fn constructor_consumes_flags_concat<C: Context>(
1149     ctx: &mut C,
1150     arg0: &ConsumesFlags,
1151     arg1: &ConsumesFlags,
1152 ) -> Option<ConsumesFlags> {
1153     let pattern0_0 = arg0;
1154     if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1155         inst: ref pattern1_0,
1156         result: pattern1_1,
1157     } = pattern0_0
1158     {
1159         let pattern2_0 = arg1;
1160         if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1161             inst: ref pattern3_0,
1162             result: pattern3_1,
1163         } = pattern2_0
1164         {
1165             // Rule at src/prelude.isle line 459.
1166             let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1167             let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1168                 inst1: pattern1_0.clone(),
1169                 inst2: pattern3_0.clone(),
1170                 result: expr0_0,
1171             };
1172             return Some(expr1_0);
1173         }
1174     }
1175     return None;
1176 }
1177 
1178 // Generated as internal constructor for term with_flags.
1179 pub fn constructor_with_flags<C: Context>(
1180     ctx: &mut C,
1181     arg0: &ProducesFlags,
1182     arg1: &ConsumesFlags,
1183 ) -> Option<ValueRegs> {
1184     let pattern0_0 = arg0;
1185     match pattern0_0 {
1186         &ProducesFlags::ProducesFlagsSideEffect {
1187             inst: ref pattern1_0,
1188         } => {
1189             let pattern2_0 = arg1;
1190             match pattern2_0 {
1191                 &ConsumesFlags::ConsumesFlagsReturnsReg {
1192                     inst: ref pattern3_0,
1193                     result: pattern3_1,
1194                 } => {
1195                     // Rule at src/prelude.isle line 484.
1196                     let expr0_0 = C::emit(ctx, pattern1_0);
1197                     let expr1_0 = C::emit(ctx, pattern3_0);
1198                     let expr2_0 = C::value_reg(ctx, pattern3_1);
1199                     return Some(expr2_0);
1200                 }
1201                 &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1202                     inst1: ref pattern3_0,
1203                     inst2: ref pattern3_1,
1204                     result: pattern3_2,
1205                 } => {
1206                     // Rule at src/prelude.isle line 490.
1207                     let expr0_0 = C::emit(ctx, pattern1_0);
1208                     let expr1_0 = C::emit(ctx, pattern3_0);
1209                     let expr2_0 = C::emit(ctx, pattern3_1);
1210                     return Some(pattern3_2);
1211                 }
1212                 &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs {
1213                     inst1: ref pattern3_0,
1214                     inst2: ref pattern3_1,
1215                     inst3: ref pattern3_2,
1216                     inst4: ref pattern3_3,
1217                     result: pattern3_4,
1218                 } => {
1219                     // Rule at src/prelude.isle line 502.
1220                     let expr0_0 = C::emit(ctx, pattern1_0);
1221                     let expr1_0 = C::emit(ctx, pattern3_0);
1222                     let expr2_0 = C::emit(ctx, pattern3_1);
1223                     let expr3_0 = C::emit(ctx, pattern3_2);
1224                     let expr4_0 = C::emit(ctx, pattern3_3);
1225                     return Some(pattern3_4);
1226                 }
1227                 _ => {}
1228             }
1229         }
1230         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1231             inst: ref pattern1_0,
1232             result: pattern1_1,
1233         } => {
1234             let pattern2_0 = arg1;
1235             if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1236                 inst: ref pattern3_0,
1237                 result: pattern3_1,
1238             } = pattern2_0
1239             {
1240                 // Rule at src/prelude.isle line 478.
1241                 let expr0_0 = C::emit(ctx, pattern1_0);
1242                 let expr1_0 = C::emit(ctx, pattern3_0);
1243                 let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1244                 return Some(expr2_0);
1245             }
1246         }
1247         _ => {}
1248     }
1249     return None;
1250 }
1251 
1252 // Generated as internal constructor for term with_flags_reg.
1253 pub fn constructor_with_flags_reg<C: Context>(
1254     ctx: &mut C,
1255     arg0: &ProducesFlags,
1256     arg1: &ConsumesFlags,
1257 ) -> Option<Reg> {
1258     let pattern0_0 = arg0;
1259     let pattern1_0 = arg1;
1260     // Rule at src/prelude.isle line 519.
1261     let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?;
1262     let expr1_0: usize = 0;
1263     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1264     return Some(expr2_0);
1265 }
1266 
1267 // Generated as internal constructor for term operand_size.
1268 pub fn constructor_operand_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
1269     let pattern0_0 = arg0;
1270     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
1271         // Rule at src/isa/aarch64/inst.isle line 891.
1272         let expr0_0 = OperandSize::Size32;
1273         return Some(expr0_0);
1274     }
1275     if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
1276         // Rule at src/isa/aarch64/inst.isle line 892.
1277         let expr0_0 = OperandSize::Size64;
1278         return Some(expr0_0);
1279     }
1280     return None;
1281 }
1282 
1283 // Generated as internal constructor for term vector_size.
1284 pub fn constructor_vector_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<VectorSize> {
1285     let pattern0_0 = arg0;
1286     if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
1287         if pattern1_0 == 8 {
1288             if pattern1_1 == 16 {
1289                 // Rule at src/isa/aarch64/inst.isle line 934.
1290                 let expr0_0 = VectorSize::Size8x16;
1291                 return Some(expr0_0);
1292             }
1293         }
1294         if pattern1_0 == 16 {
1295             if pattern1_1 == 8 {
1296                 // Rule at src/isa/aarch64/inst.isle line 935.
1297                 let expr0_0 = VectorSize::Size16x8;
1298                 return Some(expr0_0);
1299             }
1300         }
1301         if pattern1_0 == 32 {
1302             if pattern1_1 == 4 {
1303                 // Rule at src/isa/aarch64/inst.isle line 936.
1304                 let expr0_0 = VectorSize::Size32x4;
1305                 return Some(expr0_0);
1306             }
1307         }
1308         if pattern1_0 == 64 {
1309             if pattern1_1 == 2 {
1310                 // Rule at src/isa/aarch64/inst.isle line 937.
1311                 let expr0_0 = VectorSize::Size64x2;
1312                 return Some(expr0_0);
1313             }
1314         }
1315     }
1316     return None;
1317 }
1318 
1319 // Generated as internal constructor for term movz.
1320 pub fn constructor_movz<C: Context>(
1321     ctx: &mut C,
1322     arg0: MoveWideConst,
1323     arg1: &OperandSize,
1324 ) -> Option<Reg> {
1325     let pattern0_0 = arg0;
1326     let pattern1_0 = arg1;
1327     // Rule at src/isa/aarch64/inst.isle line 1377.
1328     let expr0_0: Type = I64;
1329     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1330     let expr2_0 = MInst::MovZ {
1331         rd: expr1_0,
1332         imm: pattern0_0,
1333         size: pattern1_0.clone(),
1334     };
1335     let expr3_0 = C::emit(ctx, &expr2_0);
1336     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1337     return Some(expr4_0);
1338 }
1339 
1340 // Generated as internal constructor for term movn.
1341 pub fn constructor_movn<C: Context>(
1342     ctx: &mut C,
1343     arg0: MoveWideConst,
1344     arg1: &OperandSize,
1345 ) -> Option<Reg> {
1346     let pattern0_0 = arg0;
1347     let pattern1_0 = arg1;
1348     // Rule at src/isa/aarch64/inst.isle line 1384.
1349     let expr0_0: Type = I64;
1350     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1351     let expr2_0 = MInst::MovN {
1352         rd: expr1_0,
1353         imm: pattern0_0,
1354         size: pattern1_0.clone(),
1355     };
1356     let expr3_0 = C::emit(ctx, &expr2_0);
1357     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1358     return Some(expr4_0);
1359 }
1360 
1361 // Generated as internal constructor for term alu_rr_imm_logic.
1362 pub fn constructor_alu_rr_imm_logic<C: Context>(
1363     ctx: &mut C,
1364     arg0: &ALUOp,
1365     arg1: Type,
1366     arg2: Reg,
1367     arg3: ImmLogic,
1368 ) -> Option<Reg> {
1369     let pattern0_0 = arg0;
1370     let pattern1_0 = arg1;
1371     let pattern2_0 = arg2;
1372     let pattern3_0 = arg3;
1373     // Rule at src/isa/aarch64/inst.isle line 1391.
1374     let expr0_0: Type = I64;
1375     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1376     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1377     let expr3_0 = MInst::AluRRImmLogic {
1378         alu_op: pattern0_0.clone(),
1379         size: expr2_0,
1380         rd: expr1_0,
1381         rn: pattern2_0,
1382         imml: pattern3_0,
1383     };
1384     let expr4_0 = C::emit(ctx, &expr3_0);
1385     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1386     return Some(expr5_0);
1387 }
1388 
1389 // Generated as internal constructor for term alu_rr_imm_shift.
1390 pub fn constructor_alu_rr_imm_shift<C: Context>(
1391     ctx: &mut C,
1392     arg0: &ALUOp,
1393     arg1: Type,
1394     arg2: Reg,
1395     arg3: ImmShift,
1396 ) -> Option<Reg> {
1397     let pattern0_0 = arg0;
1398     let pattern1_0 = arg1;
1399     let pattern2_0 = arg2;
1400     let pattern3_0 = arg3;
1401     // Rule at src/isa/aarch64/inst.isle line 1398.
1402     let expr0_0: Type = I64;
1403     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1404     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1405     let expr3_0 = MInst::AluRRImmShift {
1406         alu_op: pattern0_0.clone(),
1407         size: expr2_0,
1408         rd: expr1_0,
1409         rn: pattern2_0,
1410         immshift: pattern3_0,
1411     };
1412     let expr4_0 = C::emit(ctx, &expr3_0);
1413     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1414     return Some(expr5_0);
1415 }
1416 
1417 // Generated as internal constructor for term alu_rrr.
1418 pub fn constructor_alu_rrr<C: Context>(
1419     ctx: &mut C,
1420     arg0: &ALUOp,
1421     arg1: Type,
1422     arg2: Reg,
1423     arg3: Reg,
1424 ) -> Option<Reg> {
1425     let pattern0_0 = arg0;
1426     let pattern1_0 = arg1;
1427     let pattern2_0 = arg2;
1428     let pattern3_0 = arg3;
1429     // Rule at src/isa/aarch64/inst.isle line 1405.
1430     let expr0_0: Type = I64;
1431     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1432     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1433     let expr3_0 = MInst::AluRRR {
1434         alu_op: pattern0_0.clone(),
1435         size: expr2_0,
1436         rd: expr1_0,
1437         rn: pattern2_0,
1438         rm: pattern3_0,
1439     };
1440     let expr4_0 = C::emit(ctx, &expr3_0);
1441     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1442     return Some(expr5_0);
1443 }
1444 
1445 // Generated as internal constructor for term vec_rrr.
1446 pub fn constructor_vec_rrr<C: Context>(
1447     ctx: &mut C,
1448     arg0: &VecALUOp,
1449     arg1: Reg,
1450     arg2: Reg,
1451     arg3: &VectorSize,
1452 ) -> Option<Reg> {
1453     let pattern0_0 = arg0;
1454     let pattern1_0 = arg1;
1455     let pattern2_0 = arg2;
1456     let pattern3_0 = arg3;
1457     // Rule at src/isa/aarch64/inst.isle line 1412.
1458     let expr0_0: Type = I8X16;
1459     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1460     let expr2_0 = MInst::VecRRR {
1461         alu_op: pattern0_0.clone(),
1462         rd: expr1_0,
1463         rn: pattern1_0,
1464         rm: pattern2_0,
1465         size: pattern3_0.clone(),
1466     };
1467     let expr3_0 = C::emit(ctx, &expr2_0);
1468     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1469     return Some(expr4_0);
1470 }
1471 
1472 // Generated as internal constructor for term vec_lanes.
1473 pub fn constructor_vec_lanes<C: Context>(
1474     ctx: &mut C,
1475     arg0: &VecLanesOp,
1476     arg1: Reg,
1477     arg2: &VectorSize,
1478 ) -> Option<Reg> {
1479     let pattern0_0 = arg0;
1480     let pattern1_0 = arg1;
1481     let pattern2_0 = arg2;
1482     // Rule at src/isa/aarch64/inst.isle line 1419.
1483     let expr0_0: Type = I8X16;
1484     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1485     let expr2_0 = MInst::VecLanes {
1486         op: pattern0_0.clone(),
1487         rd: expr1_0,
1488         rn: pattern1_0,
1489         size: pattern2_0.clone(),
1490     };
1491     let expr3_0 = C::emit(ctx, &expr2_0);
1492     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1493     return Some(expr4_0);
1494 }
1495 
1496 // Generated as internal constructor for term vec_dup.
1497 pub fn constructor_vec_dup<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
1498     let pattern0_0 = arg0;
1499     let pattern1_0 = arg1;
1500     // Rule at src/isa/aarch64/inst.isle line 1426.
1501     let expr0_0: Type = I8X16;
1502     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1503     let expr2_0 = MInst::VecDup {
1504         rd: expr1_0,
1505         rn: pattern0_0,
1506         size: pattern1_0.clone(),
1507     };
1508     let expr3_0 = C::emit(ctx, &expr2_0);
1509     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1510     return Some(expr4_0);
1511 }
1512 
1513 // Generated as internal constructor for term alu_rr_imm12.
1514 pub fn constructor_alu_rr_imm12<C: Context>(
1515     ctx: &mut C,
1516     arg0: &ALUOp,
1517     arg1: Type,
1518     arg2: Reg,
1519     arg3: Imm12,
1520 ) -> Option<Reg> {
1521     let pattern0_0 = arg0;
1522     let pattern1_0 = arg1;
1523     let pattern2_0 = arg2;
1524     let pattern3_0 = arg3;
1525     // Rule at src/isa/aarch64/inst.isle line 1433.
1526     let expr0_0: Type = I64;
1527     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1528     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1529     let expr3_0 = MInst::AluRRImm12 {
1530         alu_op: pattern0_0.clone(),
1531         size: expr2_0,
1532         rd: expr1_0,
1533         rn: pattern2_0,
1534         imm12: pattern3_0,
1535     };
1536     let expr4_0 = C::emit(ctx, &expr3_0);
1537     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1538     return Some(expr5_0);
1539 }
1540 
1541 // Generated as internal constructor for term alu_rrr_shift.
1542 pub fn constructor_alu_rrr_shift<C: Context>(
1543     ctx: &mut C,
1544     arg0: &ALUOp,
1545     arg1: Type,
1546     arg2: Reg,
1547     arg3: Reg,
1548     arg4: ShiftOpAndAmt,
1549 ) -> Option<Reg> {
1550     let pattern0_0 = arg0;
1551     let pattern1_0 = arg1;
1552     let pattern2_0 = arg2;
1553     let pattern3_0 = arg3;
1554     let pattern4_0 = arg4;
1555     // Rule at src/isa/aarch64/inst.isle line 1440.
1556     let expr0_0: Type = I64;
1557     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1558     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1559     let expr3_0 = MInst::AluRRRShift {
1560         alu_op: pattern0_0.clone(),
1561         size: expr2_0,
1562         rd: expr1_0,
1563         rn: pattern2_0,
1564         rm: pattern3_0,
1565         shiftop: pattern4_0,
1566     };
1567     let expr4_0 = C::emit(ctx, &expr3_0);
1568     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1569     return Some(expr5_0);
1570 }
1571 
1572 // Generated as internal constructor for term alu_rrr_extend.
1573 pub fn constructor_alu_rrr_extend<C: Context>(
1574     ctx: &mut C,
1575     arg0: &ALUOp,
1576     arg1: Type,
1577     arg2: Reg,
1578     arg3: Reg,
1579     arg4: &ExtendOp,
1580 ) -> Option<Reg> {
1581     let pattern0_0 = arg0;
1582     let pattern1_0 = arg1;
1583     let pattern2_0 = arg2;
1584     let pattern3_0 = arg3;
1585     let pattern4_0 = arg4;
1586     // Rule at src/isa/aarch64/inst.isle line 1447.
1587     let expr0_0: Type = I64;
1588     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1589     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1590     let expr3_0 = MInst::AluRRRExtend {
1591         alu_op: pattern0_0.clone(),
1592         size: expr2_0,
1593         rd: expr1_0,
1594         rn: pattern2_0,
1595         rm: pattern3_0,
1596         extendop: pattern4_0.clone(),
1597     };
1598     let expr4_0 = C::emit(ctx, &expr3_0);
1599     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1600     return Some(expr5_0);
1601 }
1602 
1603 // Generated as internal constructor for term alu_rr_extend_reg.
1604 pub fn constructor_alu_rr_extend_reg<C: Context>(
1605     ctx: &mut C,
1606     arg0: &ALUOp,
1607     arg1: Type,
1608     arg2: Reg,
1609     arg3: &ExtendedValue,
1610 ) -> Option<Reg> {
1611     let pattern0_0 = arg0;
1612     let pattern1_0 = arg1;
1613     let pattern2_0 = arg2;
1614     let pattern3_0 = arg3;
1615     // Rule at src/isa/aarch64/inst.isle line 1455.
1616     let expr0_0 = C::put_extended_in_reg(ctx, pattern3_0);
1617     let expr1_0 = C::get_extended_op(ctx, pattern3_0);
1618     let expr2_0 =
1619         constructor_alu_rrr_extend(ctx, pattern0_0, pattern1_0, pattern2_0, expr0_0, &expr1_0)?;
1620     return Some(expr2_0);
1621 }
1622 
1623 // Generated as internal constructor for term alu_rrrr.
1624 pub fn constructor_alu_rrrr<C: Context>(
1625     ctx: &mut C,
1626     arg0: &ALUOp3,
1627     arg1: Type,
1628     arg2: Reg,
1629     arg3: Reg,
1630     arg4: Reg,
1631 ) -> Option<Reg> {
1632     let pattern0_0 = arg0;
1633     let pattern1_0 = arg1;
1634     let pattern2_0 = arg2;
1635     let pattern3_0 = arg3;
1636     let pattern4_0 = arg4;
1637     // Rule at src/isa/aarch64/inst.isle line 1462.
1638     let expr0_0: Type = I64;
1639     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1640     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1641     let expr3_0 = MInst::AluRRRR {
1642         alu_op: pattern0_0.clone(),
1643         size: expr2_0,
1644         rd: expr1_0,
1645         rn: pattern2_0,
1646         rm: pattern3_0,
1647         ra: pattern4_0,
1648     };
1649     let expr4_0 = C::emit(ctx, &expr3_0);
1650     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1651     return Some(expr5_0);
1652 }
1653 
1654 // Generated as internal constructor for term bit_rr.
1655 pub fn constructor_bit_rr<C: Context>(
1656     ctx: &mut C,
1657     arg0: &BitOp,
1658     arg1: Type,
1659     arg2: Reg,
1660 ) -> Option<Reg> {
1661     let pattern0_0 = arg0;
1662     let pattern1_0 = arg1;
1663     let pattern2_0 = arg2;
1664     // Rule at src/isa/aarch64/inst.isle line 1469.
1665     let expr0_0: Type = I64;
1666     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1667     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1668     let expr3_0 = MInst::BitRR {
1669         op: pattern0_0.clone(),
1670         size: expr2_0,
1671         rd: expr1_0,
1672         rn: pattern2_0,
1673     };
1674     let expr4_0 = C::emit(ctx, &expr3_0);
1675     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1676     return Some(expr5_0);
1677 }
1678 
1679 // Generated as internal constructor for term add_with_flags_paired.
1680 pub fn constructor_add_with_flags_paired<C: Context>(
1681     ctx: &mut C,
1682     arg0: Type,
1683     arg1: Reg,
1684     arg2: Reg,
1685 ) -> Option<ProducesFlags> {
1686     let pattern0_0 = arg0;
1687     let pattern1_0 = arg1;
1688     let pattern2_0 = arg2;
1689     // Rule at src/isa/aarch64/inst.isle line 1476.
1690     let expr0_0: Type = I64;
1691     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1692     let expr2_0 = ALUOp::AddS;
1693     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1694     let expr4_0 = MInst::AluRRR {
1695         alu_op: expr2_0,
1696         size: expr3_0,
1697         rd: expr1_0,
1698         rn: pattern1_0,
1699         rm: pattern2_0,
1700     };
1701     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1702     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1703         inst: expr4_0,
1704         result: expr5_0,
1705     };
1706     return Some(expr6_0);
1707 }
1708 
1709 // Generated as internal constructor for term adc_paired.
1710 pub fn constructor_adc_paired<C: Context>(
1711     ctx: &mut C,
1712     arg0: Type,
1713     arg1: Reg,
1714     arg2: Reg,
1715 ) -> Option<ConsumesFlags> {
1716     let pattern0_0 = arg0;
1717     let pattern1_0 = arg1;
1718     let pattern2_0 = arg2;
1719     // Rule at src/isa/aarch64/inst.isle line 1484.
1720     let expr0_0: Type = I64;
1721     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1722     let expr2_0 = ALUOp::Adc;
1723     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1724     let expr4_0 = MInst::AluRRR {
1725         alu_op: expr2_0,
1726         size: expr3_0,
1727         rd: expr1_0,
1728         rn: pattern1_0,
1729         rm: pattern2_0,
1730     };
1731     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1732     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1733         inst: expr4_0,
1734         result: expr5_0,
1735     };
1736     return Some(expr6_0);
1737 }
1738 
1739 // Generated as internal constructor for term sub_with_flags_paired.
1740 pub fn constructor_sub_with_flags_paired<C: Context>(
1741     ctx: &mut C,
1742     arg0: Type,
1743     arg1: Reg,
1744     arg2: Reg,
1745 ) -> Option<ProducesFlags> {
1746     let pattern0_0 = arg0;
1747     let pattern1_0 = arg1;
1748     let pattern2_0 = arg2;
1749     // Rule at src/isa/aarch64/inst.isle line 1492.
1750     let expr0_0: Type = I64;
1751     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1752     let expr2_0 = ALUOp::SubS;
1753     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1754     let expr4_0 = MInst::AluRRR {
1755         alu_op: expr2_0,
1756         size: expr3_0,
1757         rd: expr1_0,
1758         rn: pattern1_0,
1759         rm: pattern2_0,
1760     };
1761     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1762     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1763         inst: expr4_0,
1764         result: expr5_0,
1765     };
1766     return Some(expr6_0);
1767 }
1768 
1769 // Generated as internal constructor for term cmp64_imm.
1770 pub fn constructor_cmp64_imm<C: Context>(
1771     ctx: &mut C,
1772     arg0: Reg,
1773     arg1: Imm12,
1774 ) -> Option<ProducesFlags> {
1775     let pattern0_0 = arg0;
1776     let pattern1_0 = arg1;
1777     // Rule at src/isa/aarch64/inst.isle line 1499.
1778     let expr0_0 = ALUOp::SubS;
1779     let expr1_0 = OperandSize::Size64;
1780     let expr2_0 = C::writable_zero_reg(ctx);
1781     let expr3_0 = MInst::AluRRImm12 {
1782         alu_op: expr0_0,
1783         size: expr1_0,
1784         rd: expr2_0,
1785         rn: pattern0_0,
1786         imm12: pattern1_0,
1787     };
1788     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
1789     return Some(expr4_0);
1790 }
1791 
1792 // Generated as internal constructor for term sbc_paired.
1793 pub fn constructor_sbc_paired<C: Context>(
1794     ctx: &mut C,
1795     arg0: Type,
1796     arg1: Reg,
1797     arg2: Reg,
1798 ) -> Option<ConsumesFlags> {
1799     let pattern0_0 = arg0;
1800     let pattern1_0 = arg1;
1801     let pattern2_0 = arg2;
1802     // Rule at src/isa/aarch64/inst.isle line 1506.
1803     let expr0_0: Type = I64;
1804     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1805     let expr2_0 = ALUOp::Sbc;
1806     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1807     let expr4_0 = MInst::AluRRR {
1808         alu_op: expr2_0,
1809         size: expr3_0,
1810         rd: expr1_0,
1811         rn: pattern1_0,
1812         rm: pattern2_0,
1813     };
1814     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1815     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1816         inst: expr4_0,
1817         result: expr5_0,
1818     };
1819     return Some(expr6_0);
1820 }
1821 
1822 // Generated as internal constructor for term vec_misc.
1823 pub fn constructor_vec_misc<C: Context>(
1824     ctx: &mut C,
1825     arg0: &VecMisc2,
1826     arg1: Reg,
1827     arg2: &VectorSize,
1828 ) -> Option<Reg> {
1829     let pattern0_0 = arg0;
1830     let pattern1_0 = arg1;
1831     let pattern2_0 = arg2;
1832     // Rule at src/isa/aarch64/inst.isle line 1514.
1833     let expr0_0: Type = I8X16;
1834     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1835     let expr2_0 = MInst::VecMisc {
1836         op: pattern0_0.clone(),
1837         rd: expr1_0,
1838         rn: pattern1_0,
1839         size: pattern2_0.clone(),
1840     };
1841     let expr3_0 = C::emit(ctx, &expr2_0);
1842     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1843     return Some(expr4_0);
1844 }
1845 
1846 // Generated as internal constructor for term vec_rrr_long.
1847 pub fn constructor_vec_rrr_long<C: Context>(
1848     ctx: &mut C,
1849     arg0: &VecRRRLongOp,
1850     arg1: Reg,
1851     arg2: Reg,
1852     arg3: bool,
1853 ) -> Option<Reg> {
1854     let pattern0_0 = arg0;
1855     let pattern1_0 = arg1;
1856     let pattern2_0 = arg2;
1857     let pattern3_0 = arg3;
1858     // Rule at src/isa/aarch64/inst.isle line 1521.
1859     let expr0_0: Type = I8X16;
1860     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1861     let expr2_0 = MInst::VecRRRLong {
1862         alu_op: pattern0_0.clone(),
1863         rd: expr1_0,
1864         rn: pattern1_0,
1865         rm: pattern2_0,
1866         high_half: pattern3_0,
1867     };
1868     let expr3_0 = C::emit(ctx, &expr2_0);
1869     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1870     return Some(expr4_0);
1871 }
1872 
1873 // Generated as internal constructor for term vec_rrrr_long.
1874 pub fn constructor_vec_rrrr_long<C: Context>(
1875     ctx: &mut C,
1876     arg0: &VecRRRLongOp,
1877     arg1: Reg,
1878     arg2: Reg,
1879     arg3: Reg,
1880     arg4: bool,
1881 ) -> Option<Reg> {
1882     let pattern0_0 = arg0;
1883     let pattern1_0 = arg1;
1884     let pattern2_0 = arg2;
1885     let pattern3_0 = arg3;
1886     let pattern4_0 = arg4;
1887     // Rule at src/isa/aarch64/inst.isle line 1531.
1888     let expr0_0: Type = I8X16;
1889     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1890     let expr2_0 = MInst::FpuMove128 {
1891         rd: expr1_0,
1892         rn: pattern1_0,
1893     };
1894     let expr3_0 = C::emit(ctx, &expr2_0);
1895     let expr4_0 = MInst::VecRRRLong {
1896         alu_op: pattern0_0.clone(),
1897         rd: expr1_0,
1898         rn: pattern2_0,
1899         rm: pattern3_0,
1900         high_half: pattern4_0,
1901     };
1902     let expr5_0 = C::emit(ctx, &expr4_0);
1903     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1904     return Some(expr6_0);
1905 }
1906 
1907 // Generated as internal constructor for term vec_rr_narrow.
1908 pub fn constructor_vec_rr_narrow<C: Context>(
1909     ctx: &mut C,
1910     arg0: &VecRRNarrowOp,
1911     arg1: Reg,
1912     arg2: bool,
1913 ) -> Option<Reg> {
1914     let pattern0_0 = arg0;
1915     let pattern1_0 = arg1;
1916     let pattern2_0 = arg2;
1917     // Rule at src/isa/aarch64/inst.isle line 1539.
1918     let expr0_0: Type = I8X16;
1919     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1920     let expr2_0 = MInst::VecRRNarrow {
1921         op: pattern0_0.clone(),
1922         rd: expr1_0,
1923         rn: pattern1_0,
1924         high_half: pattern2_0,
1925     };
1926     let expr3_0 = C::emit(ctx, &expr2_0);
1927     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1928     return Some(expr4_0);
1929 }
1930 
1931 // Generated as internal constructor for term vec_rr_long.
1932 pub fn constructor_vec_rr_long<C: Context>(
1933     ctx: &mut C,
1934     arg0: &VecRRLongOp,
1935     arg1: Reg,
1936     arg2: bool,
1937 ) -> Option<Reg> {
1938     let pattern0_0 = arg0;
1939     let pattern1_0 = arg1;
1940     let pattern2_0 = arg2;
1941     // Rule at src/isa/aarch64/inst.isle line 1546.
1942     let expr0_0: Type = I8X16;
1943     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1944     let expr2_0 = MInst::VecRRLong {
1945         op: pattern0_0.clone(),
1946         rd: expr1_0,
1947         rn: pattern1_0,
1948         high_half: pattern2_0,
1949     };
1950     let expr3_0 = C::emit(ctx, &expr2_0);
1951     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1952     return Some(expr4_0);
1953 }
1954 
1955 // Generated as internal constructor for term mov_to_fpu.
1956 pub fn constructor_mov_to_fpu<C: Context>(
1957     ctx: &mut C,
1958     arg0: Reg,
1959     arg1: &ScalarSize,
1960 ) -> Option<Reg> {
1961     let pattern0_0 = arg0;
1962     let pattern1_0 = arg1;
1963     // Rule at src/isa/aarch64/inst.isle line 1553.
1964     let expr0_0: Type = I8X16;
1965     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1966     let expr2_0 = MInst::MovToFpu {
1967         rd: expr1_0,
1968         rn: pattern0_0,
1969         size: pattern1_0.clone(),
1970     };
1971     let expr3_0 = C::emit(ctx, &expr2_0);
1972     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1973     return Some(expr4_0);
1974 }
1975 
1976 // Generated as internal constructor for term mov_to_vec.
1977 pub fn constructor_mov_to_vec<C: Context>(
1978     ctx: &mut C,
1979     arg0: Reg,
1980     arg1: Reg,
1981     arg2: u8,
1982     arg3: &VectorSize,
1983 ) -> Option<Reg> {
1984     let pattern0_0 = arg0;
1985     let pattern1_0 = arg1;
1986     let pattern2_0 = arg2;
1987     let pattern3_0 = arg3;
1988     // Rule at src/isa/aarch64/inst.isle line 1560.
1989     let expr0_0: Type = I8X16;
1990     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1991     let expr2_0 = MInst::FpuMove128 {
1992         rd: expr1_0,
1993         rn: pattern0_0,
1994     };
1995     let expr3_0 = C::emit(ctx, &expr2_0);
1996     let expr4_0 = MInst::MovToVec {
1997         rd: expr1_0,
1998         rn: pattern1_0,
1999         idx: pattern2_0,
2000         size: pattern3_0.clone(),
2001     };
2002     let expr5_0 = C::emit(ctx, &expr4_0);
2003     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
2004     return Some(expr6_0);
2005 }
2006 
2007 // Generated as internal constructor for term mov_from_vec.
2008 pub fn constructor_mov_from_vec<C: Context>(
2009     ctx: &mut C,
2010     arg0: Reg,
2011     arg1: u8,
2012     arg2: &VectorSize,
2013 ) -> Option<Reg> {
2014     let pattern0_0 = arg0;
2015     let pattern1_0 = arg1;
2016     let pattern2_0 = arg2;
2017     // Rule at src/isa/aarch64/inst.isle line 1568.
2018     let expr0_0: Type = I64;
2019     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2020     let expr2_0 = MInst::MovFromVec {
2021         rd: expr1_0,
2022         rn: pattern0_0,
2023         idx: pattern1_0,
2024         size: pattern2_0.clone(),
2025     };
2026     let expr3_0 = C::emit(ctx, &expr2_0);
2027     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2028     return Some(expr4_0);
2029 }
2030 
2031 // Generated as internal constructor for term mov_from_vec_signed.
2032 pub fn constructor_mov_from_vec_signed<C: Context>(
2033     ctx: &mut C,
2034     arg0: Reg,
2035     arg1: u8,
2036     arg2: &VectorSize,
2037     arg3: &OperandSize,
2038 ) -> Option<Reg> {
2039     let pattern0_0 = arg0;
2040     let pattern1_0 = arg1;
2041     let pattern2_0 = arg2;
2042     let pattern3_0 = arg3;
2043     // Rule at src/isa/aarch64/inst.isle line 1575.
2044     let expr0_0: Type = I64;
2045     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2046     let expr2_0 = MInst::MovFromVecSigned {
2047         rd: expr1_0,
2048         rn: pattern0_0,
2049         idx: pattern1_0,
2050         size: pattern2_0.clone(),
2051         scalar_size: pattern3_0.clone(),
2052     };
2053     let expr3_0 = C::emit(ctx, &expr2_0);
2054     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2055     return Some(expr4_0);
2056 }
2057 
2058 // Generated as internal constructor for term extend.
2059 pub fn constructor_extend<C: Context>(
2060     ctx: &mut C,
2061     arg0: Reg,
2062     arg1: bool,
2063     arg2: u8,
2064     arg3: u8,
2065 ) -> Option<Reg> {
2066     let pattern0_0 = arg0;
2067     let pattern1_0 = arg1;
2068     let pattern2_0 = arg2;
2069     let pattern3_0 = arg3;
2070     // Rule at src/isa/aarch64/inst.isle line 1582.
2071     let expr0_0: Type = I64;
2072     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2073     let expr2_0 = MInst::Extend {
2074         rd: expr1_0,
2075         rn: pattern0_0,
2076         signed: pattern1_0,
2077         from_bits: pattern2_0,
2078         to_bits: pattern3_0,
2079     };
2080     let expr3_0 = C::emit(ctx, &expr2_0);
2081     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2082     return Some(expr4_0);
2083 }
2084 
2085 // Generated as internal constructor for term load_acquire.
2086 pub fn constructor_load_acquire<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2087     let pattern0_0 = arg0;
2088     let pattern1_0 = arg1;
2089     // Rule at src/isa/aarch64/inst.isle line 1589.
2090     let expr0_0: Type = I64;
2091     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2092     let expr2_0 = MInst::LoadAcquire {
2093         access_ty: pattern0_0,
2094         rt: expr1_0,
2095         rn: pattern1_0,
2096     };
2097     let expr3_0 = C::emit(ctx, &expr2_0);
2098     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2099     return Some(expr4_0);
2100 }
2101 
2102 // Generated as internal constructor for term tst_imm.
2103 pub fn constructor_tst_imm<C: Context>(
2104     ctx: &mut C,
2105     arg0: Type,
2106     arg1: Reg,
2107     arg2: ImmLogic,
2108 ) -> Option<ProducesFlags> {
2109     let pattern0_0 = arg0;
2110     let pattern1_0 = arg1;
2111     let pattern2_0 = arg2;
2112     // Rule at src/isa/aarch64/inst.isle line 1599.
2113     let expr0_0 = ALUOp::AndS;
2114     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
2115     let expr2_0 = C::writable_zero_reg(ctx);
2116     let expr3_0 = MInst::AluRRImmLogic {
2117         alu_op: expr0_0,
2118         size: expr1_0,
2119         rd: expr2_0,
2120         rn: pattern1_0,
2121         imml: pattern2_0,
2122     };
2123     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
2124     return Some(expr4_0);
2125 }
2126 
2127 // Generated as internal constructor for term csel.
2128 pub fn constructor_csel<C: Context>(
2129     ctx: &mut C,
2130     arg0: &Cond,
2131     arg1: Reg,
2132     arg2: Reg,
2133 ) -> Option<ConsumesFlags> {
2134     let pattern0_0 = arg0;
2135     let pattern1_0 = arg1;
2136     let pattern2_0 = arg2;
2137     // Rule at src/isa/aarch64/inst.isle line 1613.
2138     let expr0_0: Type = I64;
2139     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2140     let expr2_0 = MInst::CSel {
2141         rd: expr1_0,
2142         cond: pattern0_0.clone(),
2143         rn: pattern1_0,
2144         rm: pattern2_0,
2145     };
2146     let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
2147     let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
2148         inst: expr2_0,
2149         result: expr3_0,
2150     };
2151     return Some(expr4_0);
2152 }
2153 
2154 // Generated as internal constructor for term add.
2155 pub fn constructor_add<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2156     let pattern0_0 = arg0;
2157     let pattern1_0 = arg1;
2158     let pattern2_0 = arg2;
2159     // Rule at src/isa/aarch64/inst.isle line 1622.
2160     let expr0_0 = ALUOp::Add;
2161     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2162     return Some(expr1_0);
2163 }
2164 
2165 // Generated as internal constructor for term add_imm.
2166 pub fn constructor_add_imm<C: Context>(
2167     ctx: &mut C,
2168     arg0: Type,
2169     arg1: Reg,
2170     arg2: Imm12,
2171 ) -> Option<Reg> {
2172     let pattern0_0 = arg0;
2173     let pattern1_0 = arg1;
2174     let pattern2_0 = arg2;
2175     // Rule at src/isa/aarch64/inst.isle line 1625.
2176     let expr0_0 = ALUOp::Add;
2177     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2178     return Some(expr1_0);
2179 }
2180 
2181 // Generated as internal constructor for term add_extend.
2182 pub fn constructor_add_extend<C: Context>(
2183     ctx: &mut C,
2184     arg0: Type,
2185     arg1: Reg,
2186     arg2: &ExtendedValue,
2187 ) -> Option<Reg> {
2188     let pattern0_0 = arg0;
2189     let pattern1_0 = arg1;
2190     let pattern2_0 = arg2;
2191     // Rule at src/isa/aarch64/inst.isle line 1628.
2192     let expr0_0 = ALUOp::Add;
2193     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2194     return Some(expr1_0);
2195 }
2196 
2197 // Generated as internal constructor for term add_shift.
2198 pub fn constructor_add_shift<C: Context>(
2199     ctx: &mut C,
2200     arg0: Type,
2201     arg1: Reg,
2202     arg2: Reg,
2203     arg3: ShiftOpAndAmt,
2204 ) -> Option<Reg> {
2205     let pattern0_0 = arg0;
2206     let pattern1_0 = arg1;
2207     let pattern2_0 = arg2;
2208     let pattern3_0 = arg3;
2209     // Rule at src/isa/aarch64/inst.isle line 1631.
2210     let expr0_0 = ALUOp::Add;
2211     let expr1_0 = constructor_alu_rrr_shift(
2212         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2213     )?;
2214     return Some(expr1_0);
2215 }
2216 
2217 // Generated as internal constructor for term add_vec.
2218 pub fn constructor_add_vec<C: Context>(
2219     ctx: &mut C,
2220     arg0: Reg,
2221     arg1: Reg,
2222     arg2: &VectorSize,
2223 ) -> Option<Reg> {
2224     let pattern0_0 = arg0;
2225     let pattern1_0 = arg1;
2226     let pattern2_0 = arg2;
2227     // Rule at src/isa/aarch64/inst.isle line 1634.
2228     let expr0_0 = VecALUOp::Add;
2229     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2230     return Some(expr1_0);
2231 }
2232 
2233 // Generated as internal constructor for term sub.
2234 pub fn constructor_sub<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2235     let pattern0_0 = arg0;
2236     let pattern1_0 = arg1;
2237     let pattern2_0 = arg2;
2238     // Rule at src/isa/aarch64/inst.isle line 1639.
2239     let expr0_0 = ALUOp::Sub;
2240     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2241     return Some(expr1_0);
2242 }
2243 
2244 // Generated as internal constructor for term sub_imm.
2245 pub fn constructor_sub_imm<C: Context>(
2246     ctx: &mut C,
2247     arg0: Type,
2248     arg1: Reg,
2249     arg2: Imm12,
2250 ) -> Option<Reg> {
2251     let pattern0_0 = arg0;
2252     let pattern1_0 = arg1;
2253     let pattern2_0 = arg2;
2254     // Rule at src/isa/aarch64/inst.isle line 1642.
2255     let expr0_0 = ALUOp::Sub;
2256     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2257     return Some(expr1_0);
2258 }
2259 
2260 // Generated as internal constructor for term sub_extend.
2261 pub fn constructor_sub_extend<C: Context>(
2262     ctx: &mut C,
2263     arg0: Type,
2264     arg1: Reg,
2265     arg2: &ExtendedValue,
2266 ) -> Option<Reg> {
2267     let pattern0_0 = arg0;
2268     let pattern1_0 = arg1;
2269     let pattern2_0 = arg2;
2270     // Rule at src/isa/aarch64/inst.isle line 1645.
2271     let expr0_0 = ALUOp::Sub;
2272     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2273     return Some(expr1_0);
2274 }
2275 
2276 // Generated as internal constructor for term sub_shift.
2277 pub fn constructor_sub_shift<C: Context>(
2278     ctx: &mut C,
2279     arg0: Type,
2280     arg1: Reg,
2281     arg2: Reg,
2282     arg3: ShiftOpAndAmt,
2283 ) -> Option<Reg> {
2284     let pattern0_0 = arg0;
2285     let pattern1_0 = arg1;
2286     let pattern2_0 = arg2;
2287     let pattern3_0 = arg3;
2288     // Rule at src/isa/aarch64/inst.isle line 1648.
2289     let expr0_0 = ALUOp::Sub;
2290     let expr1_0 = constructor_alu_rrr_shift(
2291         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2292     )?;
2293     return Some(expr1_0);
2294 }
2295 
2296 // Generated as internal constructor for term sub_vec.
2297 pub fn constructor_sub_vec<C: Context>(
2298     ctx: &mut C,
2299     arg0: Reg,
2300     arg1: Reg,
2301     arg2: &VectorSize,
2302 ) -> Option<Reg> {
2303     let pattern0_0 = arg0;
2304     let pattern1_0 = arg1;
2305     let pattern2_0 = arg2;
2306     // Rule at src/isa/aarch64/inst.isle line 1651.
2307     let expr0_0 = VecALUOp::Sub;
2308     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2309     return Some(expr1_0);
2310 }
2311 
2312 // Generated as internal constructor for term madd.
2313 pub fn constructor_madd<C: Context>(
2314     ctx: &mut C,
2315     arg0: Type,
2316     arg1: Reg,
2317     arg2: Reg,
2318     arg3: Reg,
2319 ) -> Option<Reg> {
2320     let pattern0_0 = arg0;
2321     let pattern1_0 = arg1;
2322     let pattern2_0 = arg2;
2323     let pattern3_0 = arg3;
2324     // Rule at src/isa/aarch64/inst.isle line 1656.
2325     let expr0_0 = ALUOp3::MAdd;
2326     let expr1_0 = constructor_alu_rrrr(
2327         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2328     )?;
2329     return Some(expr1_0);
2330 }
2331 
2332 // Generated as internal constructor for term msub.
2333 pub fn constructor_msub<C: Context>(
2334     ctx: &mut C,
2335     arg0: Type,
2336     arg1: Reg,
2337     arg2: Reg,
2338     arg3: Reg,
2339 ) -> Option<Reg> {
2340     let pattern0_0 = arg0;
2341     let pattern1_0 = arg1;
2342     let pattern2_0 = arg2;
2343     let pattern3_0 = arg3;
2344     // Rule at src/isa/aarch64/inst.isle line 1661.
2345     let expr0_0 = ALUOp3::MSub;
2346     let expr1_0 = constructor_alu_rrrr(
2347         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2348     )?;
2349     return Some(expr1_0);
2350 }
2351 
2352 // Generated as internal constructor for term uqadd.
2353 pub fn constructor_uqadd<C: Context>(
2354     ctx: &mut C,
2355     arg0: Reg,
2356     arg1: Reg,
2357     arg2: &VectorSize,
2358 ) -> Option<Reg> {
2359     let pattern0_0 = arg0;
2360     let pattern1_0 = arg1;
2361     let pattern2_0 = arg2;
2362     // Rule at src/isa/aarch64/inst.isle line 1665.
2363     let expr0_0 = VecALUOp::Uqadd;
2364     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2365     return Some(expr1_0);
2366 }
2367 
2368 // Generated as internal constructor for term sqadd.
2369 pub fn constructor_sqadd<C: Context>(
2370     ctx: &mut C,
2371     arg0: Reg,
2372     arg1: Reg,
2373     arg2: &VectorSize,
2374 ) -> Option<Reg> {
2375     let pattern0_0 = arg0;
2376     let pattern1_0 = arg1;
2377     let pattern2_0 = arg2;
2378     // Rule at src/isa/aarch64/inst.isle line 1669.
2379     let expr0_0 = VecALUOp::Sqadd;
2380     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2381     return Some(expr1_0);
2382 }
2383 
2384 // Generated as internal constructor for term uqsub.
2385 pub fn constructor_uqsub<C: Context>(
2386     ctx: &mut C,
2387     arg0: Reg,
2388     arg1: Reg,
2389     arg2: &VectorSize,
2390 ) -> Option<Reg> {
2391     let pattern0_0 = arg0;
2392     let pattern1_0 = arg1;
2393     let pattern2_0 = arg2;
2394     // Rule at src/isa/aarch64/inst.isle line 1673.
2395     let expr0_0 = VecALUOp::Uqsub;
2396     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2397     return Some(expr1_0);
2398 }
2399 
2400 // Generated as internal constructor for term sqsub.
2401 pub fn constructor_sqsub<C: Context>(
2402     ctx: &mut C,
2403     arg0: Reg,
2404     arg1: Reg,
2405     arg2: &VectorSize,
2406 ) -> Option<Reg> {
2407     let pattern0_0 = arg0;
2408     let pattern1_0 = arg1;
2409     let pattern2_0 = arg2;
2410     // Rule at src/isa/aarch64/inst.isle line 1677.
2411     let expr0_0 = VecALUOp::Sqsub;
2412     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2413     return Some(expr1_0);
2414 }
2415 
2416 // Generated as internal constructor for term umulh.
2417 pub fn constructor_umulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2418     let pattern0_0 = arg0;
2419     let pattern1_0 = arg1;
2420     let pattern2_0 = arg2;
2421     // Rule at src/isa/aarch64/inst.isle line 1681.
2422     let expr0_0 = ALUOp::UMulH;
2423     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2424     return Some(expr1_0);
2425 }
2426 
2427 // Generated as internal constructor for term smulh.
2428 pub fn constructor_smulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2429     let pattern0_0 = arg0;
2430     let pattern1_0 = arg1;
2431     let pattern2_0 = arg2;
2432     // Rule at src/isa/aarch64/inst.isle line 1685.
2433     let expr0_0 = ALUOp::SMulH;
2434     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2435     return Some(expr1_0);
2436 }
2437 
2438 // Generated as internal constructor for term mul.
2439 pub fn constructor_mul<C: Context>(
2440     ctx: &mut C,
2441     arg0: Reg,
2442     arg1: Reg,
2443     arg2: &VectorSize,
2444 ) -> Option<Reg> {
2445     let pattern0_0 = arg0;
2446     let pattern1_0 = arg1;
2447     let pattern2_0 = arg2;
2448     // Rule at src/isa/aarch64/inst.isle line 1689.
2449     let expr0_0 = VecALUOp::Mul;
2450     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2451     return Some(expr1_0);
2452 }
2453 
2454 // Generated as internal constructor for term neg.
2455 pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2456     let pattern0_0 = arg0;
2457     let pattern1_0 = arg1;
2458     // Rule at src/isa/aarch64/inst.isle line 1693.
2459     let expr0_0 = VecMisc2::Neg;
2460     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2461     return Some(expr1_0);
2462 }
2463 
2464 // Generated as internal constructor for term rev64.
2465 pub fn constructor_rev64<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2466     let pattern0_0 = arg0;
2467     let pattern1_0 = arg1;
2468     // Rule at src/isa/aarch64/inst.isle line 1697.
2469     let expr0_0 = VecMisc2::Rev64;
2470     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2471     return Some(expr1_0);
2472 }
2473 
2474 // Generated as internal constructor for term xtn64.
2475 pub fn constructor_xtn64<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2476     let pattern0_0 = arg0;
2477     let pattern1_0 = arg1;
2478     // Rule at src/isa/aarch64/inst.isle line 1701.
2479     let expr0_0 = VecRRNarrowOp::Xtn64;
2480     let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2481     return Some(expr1_0);
2482 }
2483 
2484 // Generated as internal constructor for term addp.
2485 pub fn constructor_addp<C: Context>(
2486     ctx: &mut C,
2487     arg0: Reg,
2488     arg1: Reg,
2489     arg2: &VectorSize,
2490 ) -> Option<Reg> {
2491     let pattern0_0 = arg0;
2492     let pattern1_0 = arg1;
2493     let pattern2_0 = arg2;
2494     // Rule at src/isa/aarch64/inst.isle line 1705.
2495     let expr0_0 = VecALUOp::Addp;
2496     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2497     return Some(expr1_0);
2498 }
2499 
2500 // Generated as internal constructor for term addv.
2501 pub fn constructor_addv<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2502     let pattern0_0 = arg0;
2503     let pattern1_0 = arg1;
2504     // Rule at src/isa/aarch64/inst.isle line 1709.
2505     let expr0_0 = VecLanesOp::Addv;
2506     let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2507     return Some(expr1_0);
2508 }
2509 
2510 // Generated as internal constructor for term shll32.
2511 pub fn constructor_shll32<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2512     let pattern0_0 = arg0;
2513     let pattern1_0 = arg1;
2514     // Rule at src/isa/aarch64/inst.isle line 1713.
2515     let expr0_0 = VecRRLongOp::Shll32;
2516     let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2517     return Some(expr1_0);
2518 }
2519 
2520 // Generated as internal constructor for term umlal32.
2521 pub fn constructor_umlal32<C: Context>(
2522     ctx: &mut C,
2523     arg0: Reg,
2524     arg1: Reg,
2525     arg2: Reg,
2526     arg3: bool,
2527 ) -> Option<Reg> {
2528     let pattern0_0 = arg0;
2529     let pattern1_0 = arg1;
2530     let pattern2_0 = arg2;
2531     let pattern3_0 = arg3;
2532     // Rule at src/isa/aarch64/inst.isle line 1717.
2533     let expr0_0 = VecRRRLongOp::Umlal32;
2534     let expr1_0 = constructor_vec_rrrr_long(
2535         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2536     )?;
2537     return Some(expr1_0);
2538 }
2539 
2540 // Generated as internal constructor for term smull8.
2541 pub fn constructor_smull8<C: Context>(
2542     ctx: &mut C,
2543     arg0: Reg,
2544     arg1: Reg,
2545     arg2: bool,
2546 ) -> Option<Reg> {
2547     let pattern0_0 = arg0;
2548     let pattern1_0 = arg1;
2549     let pattern2_0 = arg2;
2550     // Rule at src/isa/aarch64/inst.isle line 1721.
2551     let expr0_0 = VecRRRLongOp::Smull8;
2552     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2553     return Some(expr1_0);
2554 }
2555 
2556 // Generated as internal constructor for term umull8.
2557 pub fn constructor_umull8<C: Context>(
2558     ctx: &mut C,
2559     arg0: Reg,
2560     arg1: Reg,
2561     arg2: bool,
2562 ) -> Option<Reg> {
2563     let pattern0_0 = arg0;
2564     let pattern1_0 = arg1;
2565     let pattern2_0 = arg2;
2566     // Rule at src/isa/aarch64/inst.isle line 1725.
2567     let expr0_0 = VecRRRLongOp::Umull8;
2568     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2569     return Some(expr1_0);
2570 }
2571 
2572 // Generated as internal constructor for term smull16.
2573 pub fn constructor_smull16<C: Context>(
2574     ctx: &mut C,
2575     arg0: Reg,
2576     arg1: Reg,
2577     arg2: bool,
2578 ) -> Option<Reg> {
2579     let pattern0_0 = arg0;
2580     let pattern1_0 = arg1;
2581     let pattern2_0 = arg2;
2582     // Rule at src/isa/aarch64/inst.isle line 1729.
2583     let expr0_0 = VecRRRLongOp::Smull16;
2584     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2585     return Some(expr1_0);
2586 }
2587 
2588 // Generated as internal constructor for term umull16.
2589 pub fn constructor_umull16<C: Context>(
2590     ctx: &mut C,
2591     arg0: Reg,
2592     arg1: Reg,
2593     arg2: bool,
2594 ) -> Option<Reg> {
2595     let pattern0_0 = arg0;
2596     let pattern1_0 = arg1;
2597     let pattern2_0 = arg2;
2598     // Rule at src/isa/aarch64/inst.isle line 1733.
2599     let expr0_0 = VecRRRLongOp::Umull16;
2600     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2601     return Some(expr1_0);
2602 }
2603 
2604 // Generated as internal constructor for term smull32.
2605 pub fn constructor_smull32<C: Context>(
2606     ctx: &mut C,
2607     arg0: Reg,
2608     arg1: Reg,
2609     arg2: bool,
2610 ) -> Option<Reg> {
2611     let pattern0_0 = arg0;
2612     let pattern1_0 = arg1;
2613     let pattern2_0 = arg2;
2614     // Rule at src/isa/aarch64/inst.isle line 1737.
2615     let expr0_0 = VecRRRLongOp::Smull32;
2616     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2617     return Some(expr1_0);
2618 }
2619 
2620 // Generated as internal constructor for term umull32.
2621 pub fn constructor_umull32<C: Context>(
2622     ctx: &mut C,
2623     arg0: Reg,
2624     arg1: Reg,
2625     arg2: bool,
2626 ) -> Option<Reg> {
2627     let pattern0_0 = arg0;
2628     let pattern1_0 = arg1;
2629     let pattern2_0 = arg2;
2630     // Rule at src/isa/aarch64/inst.isle line 1741.
2631     let expr0_0 = VecRRRLongOp::Umull32;
2632     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2633     return Some(expr1_0);
2634 }
2635 
2636 // Generated as internal constructor for term asr.
2637 pub fn constructor_asr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2638     let pattern0_0 = arg0;
2639     let pattern1_0 = arg1;
2640     let pattern2_0 = arg2;
2641     // Rule at src/isa/aarch64/inst.isle line 1745.
2642     let expr0_0 = ALUOp::Asr;
2643     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2644     return Some(expr1_0);
2645 }
2646 
2647 // Generated as internal constructor for term asr_imm.
2648 pub fn constructor_asr_imm<C: Context>(
2649     ctx: &mut C,
2650     arg0: Type,
2651     arg1: Reg,
2652     arg2: ImmShift,
2653 ) -> Option<Reg> {
2654     let pattern0_0 = arg0;
2655     let pattern1_0 = arg1;
2656     let pattern2_0 = arg2;
2657     // Rule at src/isa/aarch64/inst.isle line 1748.
2658     let expr0_0 = ALUOp::Asr;
2659     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2660     return Some(expr1_0);
2661 }
2662 
2663 // Generated as internal constructor for term lsr.
2664 pub fn constructor_lsr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2665     let pattern0_0 = arg0;
2666     let pattern1_0 = arg1;
2667     let pattern2_0 = arg2;
2668     // Rule at src/isa/aarch64/inst.isle line 1752.
2669     let expr0_0 = ALUOp::Lsr;
2670     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2671     return Some(expr1_0);
2672 }
2673 
2674 // Generated as internal constructor for term lsr_imm.
2675 pub fn constructor_lsr_imm<C: Context>(
2676     ctx: &mut C,
2677     arg0: Type,
2678     arg1: Reg,
2679     arg2: ImmShift,
2680 ) -> Option<Reg> {
2681     let pattern0_0 = arg0;
2682     let pattern1_0 = arg1;
2683     let pattern2_0 = arg2;
2684     // Rule at src/isa/aarch64/inst.isle line 1755.
2685     let expr0_0 = ALUOp::Lsr;
2686     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2687     return Some(expr1_0);
2688 }
2689 
2690 // Generated as internal constructor for term lsl.
2691 pub fn constructor_lsl<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2692     let pattern0_0 = arg0;
2693     let pattern1_0 = arg1;
2694     let pattern2_0 = arg2;
2695     // Rule at src/isa/aarch64/inst.isle line 1759.
2696     let expr0_0 = ALUOp::Lsl;
2697     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2698     return Some(expr1_0);
2699 }
2700 
2701 // Generated as internal constructor for term lsl_imm.
2702 pub fn constructor_lsl_imm<C: Context>(
2703     ctx: &mut C,
2704     arg0: Type,
2705     arg1: Reg,
2706     arg2: ImmShift,
2707 ) -> Option<Reg> {
2708     let pattern0_0 = arg0;
2709     let pattern1_0 = arg1;
2710     let pattern2_0 = arg2;
2711     // Rule at src/isa/aarch64/inst.isle line 1762.
2712     let expr0_0 = ALUOp::Lsl;
2713     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2714     return Some(expr1_0);
2715 }
2716 
2717 // Generated as internal constructor for term a64_udiv.
2718 pub fn constructor_a64_udiv<C: Context>(
2719     ctx: &mut C,
2720     arg0: Type,
2721     arg1: Reg,
2722     arg2: Reg,
2723 ) -> Option<Reg> {
2724     let pattern0_0 = arg0;
2725     let pattern1_0 = arg1;
2726     let pattern2_0 = arg2;
2727     // Rule at src/isa/aarch64/inst.isle line 1766.
2728     let expr0_0 = ALUOp::UDiv;
2729     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2730     return Some(expr1_0);
2731 }
2732 
2733 // Generated as internal constructor for term a64_sdiv.
2734 pub fn constructor_a64_sdiv<C: Context>(
2735     ctx: &mut C,
2736     arg0: Type,
2737     arg1: Reg,
2738     arg2: Reg,
2739 ) -> Option<Reg> {
2740     let pattern0_0 = arg0;
2741     let pattern1_0 = arg1;
2742     let pattern2_0 = arg2;
2743     // Rule at src/isa/aarch64/inst.isle line 1770.
2744     let expr0_0 = ALUOp::SDiv;
2745     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2746     return Some(expr1_0);
2747 }
2748 
2749 // Generated as internal constructor for term not.
2750 pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2751     let pattern0_0 = arg0;
2752     let pattern1_0 = arg1;
2753     // Rule at src/isa/aarch64/inst.isle line 1774.
2754     let expr0_0 = VecMisc2::Not;
2755     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2756     return Some(expr1_0);
2757 }
2758 
2759 // Generated as internal constructor for term orr_not.
2760 pub fn constructor_orr_not<C: Context>(
2761     ctx: &mut C,
2762     arg0: Type,
2763     arg1: Reg,
2764     arg2: Reg,
2765 ) -> Option<Reg> {
2766     let pattern0_0 = arg0;
2767     let pattern1_0 = arg1;
2768     let pattern2_0 = arg2;
2769     // Rule at src/isa/aarch64/inst.isle line 1779.
2770     let expr0_0 = ALUOp::OrrNot;
2771     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2772     return Some(expr1_0);
2773 }
2774 
2775 // Generated as internal constructor for term orr_not_shift.
2776 pub fn constructor_orr_not_shift<C: Context>(
2777     ctx: &mut C,
2778     arg0: Type,
2779     arg1: Reg,
2780     arg2: Reg,
2781     arg3: ShiftOpAndAmt,
2782 ) -> Option<Reg> {
2783     let pattern0_0 = arg0;
2784     let pattern1_0 = arg1;
2785     let pattern2_0 = arg2;
2786     let pattern3_0 = arg3;
2787     // Rule at src/isa/aarch64/inst.isle line 1782.
2788     let expr0_0 = ALUOp::OrrNot;
2789     let expr1_0 = constructor_alu_rrr_shift(
2790         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2791     )?;
2792     return Some(expr1_0);
2793 }
2794 
2795 // Generated as internal constructor for term orr.
2796 pub fn constructor_orr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2797     let pattern0_0 = arg0;
2798     let pattern1_0 = arg1;
2799     let pattern2_0 = arg2;
2800     // Rule at src/isa/aarch64/inst.isle line 1787.
2801     let expr0_0 = ALUOp::Orr;
2802     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2803     return Some(expr1_0);
2804 }
2805 
2806 // Generated as internal constructor for term orr_imm.
2807 pub fn constructor_orr_imm<C: Context>(
2808     ctx: &mut C,
2809     arg0: Type,
2810     arg1: Reg,
2811     arg2: ImmLogic,
2812 ) -> Option<Reg> {
2813     let pattern0_0 = arg0;
2814     let pattern1_0 = arg1;
2815     let pattern2_0 = arg2;
2816     // Rule at src/isa/aarch64/inst.isle line 1790.
2817     let expr0_0 = ALUOp::Orr;
2818     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2819     return Some(expr1_0);
2820 }
2821 
2822 // Generated as internal constructor for term orr_vec.
2823 pub fn constructor_orr_vec<C: Context>(
2824     ctx: &mut C,
2825     arg0: Reg,
2826     arg1: Reg,
2827     arg2: &VectorSize,
2828 ) -> Option<Reg> {
2829     let pattern0_0 = arg0;
2830     let pattern1_0 = arg1;
2831     let pattern2_0 = arg2;
2832     // Rule at src/isa/aarch64/inst.isle line 1793.
2833     let expr0_0 = VecALUOp::Orr;
2834     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2835     return Some(expr1_0);
2836 }
2837 
2838 // Generated as internal constructor for term and_imm.
2839 pub fn constructor_and_imm<C: Context>(
2840     ctx: &mut C,
2841     arg0: Type,
2842     arg1: Reg,
2843     arg2: ImmLogic,
2844 ) -> Option<Reg> {
2845     let pattern0_0 = arg0;
2846     let pattern1_0 = arg1;
2847     let pattern2_0 = arg2;
2848     // Rule at src/isa/aarch64/inst.isle line 1798.
2849     let expr0_0 = ALUOp::And;
2850     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2851     return Some(expr1_0);
2852 }
2853 
2854 // Generated as internal constructor for term and_vec.
2855 pub fn constructor_and_vec<C: Context>(
2856     ctx: &mut C,
2857     arg0: Reg,
2858     arg1: Reg,
2859     arg2: &VectorSize,
2860 ) -> Option<Reg> {
2861     let pattern0_0 = arg0;
2862     let pattern1_0 = arg1;
2863     let pattern2_0 = arg2;
2864     // Rule at src/isa/aarch64/inst.isle line 1801.
2865     let expr0_0 = VecALUOp::And;
2866     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2867     return Some(expr1_0);
2868 }
2869 
2870 // Generated as internal constructor for term eor_vec.
2871 pub fn constructor_eor_vec<C: Context>(
2872     ctx: &mut C,
2873     arg0: Reg,
2874     arg1: Reg,
2875     arg2: &VectorSize,
2876 ) -> Option<Reg> {
2877     let pattern0_0 = arg0;
2878     let pattern1_0 = arg1;
2879     let pattern2_0 = arg2;
2880     // Rule at src/isa/aarch64/inst.isle line 1805.
2881     let expr0_0 = VecALUOp::Eor;
2882     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2883     return Some(expr1_0);
2884 }
2885 
2886 // Generated as internal constructor for term bic_vec.
2887 pub fn constructor_bic_vec<C: Context>(
2888     ctx: &mut C,
2889     arg0: Reg,
2890     arg1: Reg,
2891     arg2: &VectorSize,
2892 ) -> Option<Reg> {
2893     let pattern0_0 = arg0;
2894     let pattern1_0 = arg1;
2895     let pattern2_0 = arg2;
2896     // Rule at src/isa/aarch64/inst.isle line 1809.
2897     let expr0_0 = VecALUOp::Bic;
2898     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2899     return Some(expr1_0);
2900 }
2901 
2902 // Generated as internal constructor for term sshl.
2903 pub fn constructor_sshl<C: Context>(
2904     ctx: &mut C,
2905     arg0: Reg,
2906     arg1: Reg,
2907     arg2: &VectorSize,
2908 ) -> Option<Reg> {
2909     let pattern0_0 = arg0;
2910     let pattern1_0 = arg1;
2911     let pattern2_0 = arg2;
2912     // Rule at src/isa/aarch64/inst.isle line 1813.
2913     let expr0_0 = VecALUOp::Sshl;
2914     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2915     return Some(expr1_0);
2916 }
2917 
2918 // Generated as internal constructor for term ushl.
2919 pub fn constructor_ushl<C: Context>(
2920     ctx: &mut C,
2921     arg0: Reg,
2922     arg1: Reg,
2923     arg2: &VectorSize,
2924 ) -> Option<Reg> {
2925     let pattern0_0 = arg0;
2926     let pattern1_0 = arg1;
2927     let pattern2_0 = arg2;
2928     // Rule at src/isa/aarch64/inst.isle line 1817.
2929     let expr0_0 = VecALUOp::Ushl;
2930     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2931     return Some(expr1_0);
2932 }
2933 
2934 // Generated as internal constructor for term a64_rotr.
2935 pub fn constructor_a64_rotr<C: Context>(
2936     ctx: &mut C,
2937     arg0: Type,
2938     arg1: Reg,
2939     arg2: Reg,
2940 ) -> Option<Reg> {
2941     let pattern0_0 = arg0;
2942     let pattern1_0 = arg1;
2943     let pattern2_0 = arg2;
2944     // Rule at src/isa/aarch64/inst.isle line 1822.
2945     let expr0_0 = ALUOp::RotR;
2946     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2947     return Some(expr1_0);
2948 }
2949 
2950 // Generated as internal constructor for term a64_rotr_imm.
2951 pub fn constructor_a64_rotr_imm<C: Context>(
2952     ctx: &mut C,
2953     arg0: Type,
2954     arg1: Reg,
2955     arg2: ImmShift,
2956 ) -> Option<Reg> {
2957     let pattern0_0 = arg0;
2958     let pattern1_0 = arg1;
2959     let pattern2_0 = arg2;
2960     // Rule at src/isa/aarch64/inst.isle line 1825.
2961     let expr0_0 = ALUOp::RotR;
2962     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2963     return Some(expr1_0);
2964 }
2965 
2966 // Generated as internal constructor for term rbit.
2967 pub fn constructor_rbit<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2968     let pattern0_0 = arg0;
2969     let pattern1_0 = arg1;
2970     // Rule at src/isa/aarch64/inst.isle line 1830.
2971     let expr0_0 = BitOp::RBit;
2972     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2973     return Some(expr1_0);
2974 }
2975 
2976 // Generated as internal constructor for term a64_clz.
2977 pub fn constructor_a64_clz<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2978     let pattern0_0 = arg0;
2979     let pattern1_0 = arg1;
2980     // Rule at src/isa/aarch64/inst.isle line 1835.
2981     let expr0_0 = BitOp::Clz;
2982     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2983     return Some(expr1_0);
2984 }
2985 
2986 // Generated as internal constructor for term a64_cls.
2987 pub fn constructor_a64_cls<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2988     let pattern0_0 = arg0;
2989     let pattern1_0 = arg1;
2990     // Rule at src/isa/aarch64/inst.isle line 1840.
2991     let expr0_0 = BitOp::Cls;
2992     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2993     return Some(expr1_0);
2994 }
2995 
2996 // Generated as internal constructor for term eon.
2997 pub fn constructor_eon<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2998     let pattern0_0 = arg0;
2999     let pattern1_0 = arg1;
3000     let pattern2_0 = arg2;
3001     // Rule at src/isa/aarch64/inst.isle line 1845.
3002     let expr0_0 = ALUOp::EorNot;
3003     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3004     return Some(expr1_0);
3005 }
3006 
3007 // Generated as internal constructor for term vec_cnt.
3008 pub fn constructor_vec_cnt<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3009     let pattern0_0 = arg0;
3010     let pattern1_0 = arg1;
3011     // Rule at src/isa/aarch64/inst.isle line 1850.
3012     let expr0_0 = VecMisc2::Cnt;
3013     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3014     return Some(expr1_0);
3015 }
3016 
3017 // Generated as internal constructor for term imm.
3018 pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
3019     let pattern0_0 = arg0;
3020     if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) {
3021         let pattern2_0 = arg1;
3022         let closure3 = || {
3023             let expr0_0: Type = I64;
3024             return Some(expr0_0);
3025         };
3026         if let Some(pattern3_0) = closure3() {
3027             if let Some(pattern4_0) = C::imm_logic_from_u64(ctx, pattern2_0, pattern3_0) {
3028                 // Rule at src/isa/aarch64/inst.isle line 1865.
3029                 let expr0_0: Type = I64;
3030                 let expr1_0 = C::zero_reg(ctx);
3031                 let expr2_0 = constructor_orr_imm(ctx, expr0_0, expr1_0, pattern4_0)?;
3032                 return Some(expr2_0);
3033             }
3034         }
3035         if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) {
3036             // Rule at src/isa/aarch64/inst.isle line 1857.
3037             let expr0_0 = OperandSize::Size64;
3038             let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?;
3039             return Some(expr1_0);
3040         }
3041         if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) {
3042             // Rule at src/isa/aarch64/inst.isle line 1861.
3043             let expr0_0 = OperandSize::Size64;
3044             let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?;
3045             return Some(expr1_0);
3046         }
3047         // Rule at src/isa/aarch64/inst.isle line 1872.
3048         let expr0_0 = C::load_constant64_full(ctx, pattern2_0);
3049         return Some(expr0_0);
3050     }
3051     return None;
3052 }
3053 
3054 // Generated as internal constructor for term put_in_reg_sext32.
3055 pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3056     let pattern0_0 = arg0;
3057     let pattern1_0 = C::value_type(ctx, pattern0_0);
3058     if pattern1_0 == I32 {
3059         // Rule at src/isa/aarch64/inst.isle line 1883.
3060         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3061         return Some(expr0_0);
3062     }
3063     if pattern1_0 == I64 {
3064         // Rule at src/isa/aarch64/inst.isle line 1884.
3065         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3066         return Some(expr0_0);
3067     }
3068     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3069         // Rule at src/isa/aarch64/inst.isle line 1879.
3070         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3071         let expr1_0: bool = true;
3072         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3073         let expr3_0: u8 = 32;
3074         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3075         return Some(expr4_0);
3076     }
3077     return None;
3078 }
3079 
3080 // Generated as internal constructor for term put_in_reg_zext32.
3081 pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3082     let pattern0_0 = arg0;
3083     let pattern1_0 = C::value_type(ctx, pattern0_0);
3084     if pattern1_0 == I32 {
3085         // Rule at src/isa/aarch64/inst.isle line 1892.
3086         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3087         return Some(expr0_0);
3088     }
3089     if pattern1_0 == I64 {
3090         // Rule at src/isa/aarch64/inst.isle line 1893.
3091         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3092         return Some(expr0_0);
3093     }
3094     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3095         // Rule at src/isa/aarch64/inst.isle line 1888.
3096         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3097         let expr1_0: bool = false;
3098         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3099         let expr3_0: u8 = 32;
3100         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3101         return Some(expr4_0);
3102     }
3103     return None;
3104 }
3105 
3106 // Generated as internal constructor for term put_in_reg_sext64.
3107 pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3108     let pattern0_0 = arg0;
3109     let pattern1_0 = C::value_type(ctx, pattern0_0);
3110     if pattern1_0 == I64 {
3111         // Rule at src/isa/aarch64/inst.isle line 1901.
3112         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3113         return Some(expr0_0);
3114     }
3115     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3116         // Rule at src/isa/aarch64/inst.isle line 1897.
3117         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3118         let expr1_0: bool = true;
3119         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3120         let expr3_0: u8 = 64;
3121         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3122         return Some(expr4_0);
3123     }
3124     return None;
3125 }
3126 
3127 // Generated as internal constructor for term put_in_reg_zext64.
3128 pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3129     let pattern0_0 = arg0;
3130     let pattern1_0 = C::value_type(ctx, pattern0_0);
3131     if pattern1_0 == I64 {
3132         // Rule at src/isa/aarch64/inst.isle line 1909.
3133         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3134         return Some(expr0_0);
3135     }
3136     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3137         // Rule at src/isa/aarch64/inst.isle line 1905.
3138         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3139         let expr1_0: bool = false;
3140         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3141         let expr3_0: u8 = 64;
3142         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3143         return Some(expr4_0);
3144     }
3145     return None;
3146 }
3147 
3148 // Generated as internal constructor for term trap_if_zero_divisor.
3149 pub fn constructor_trap_if_zero_divisor<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3150     let pattern0_0 = arg0;
3151     // Rule at src/isa/aarch64/inst.isle line 1914.
3152     let expr0_0 = C::cond_br_zero(ctx, pattern0_0);
3153     let expr1_0 = C::trap_code_division_by_zero(ctx);
3154     let expr2_0 = MInst::TrapIf {
3155         kind: expr0_0,
3156         trap_code: expr1_0,
3157     };
3158     let expr3_0 = C::emit(ctx, &expr2_0);
3159     return Some(pattern0_0);
3160 }
3161 
3162 // Generated as internal constructor for term size_from_ty.
3163 pub fn constructor_size_from_ty<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
3164     let pattern0_0 = arg0;
3165     if pattern0_0 == I64 {
3166         // Rule at src/isa/aarch64/inst.isle line 1920.
3167         let expr0_0 = OperandSize::Size64;
3168         return Some(expr0_0);
3169     }
3170     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
3171         // Rule at src/isa/aarch64/inst.isle line 1919.
3172         let expr0_0 = OperandSize::Size32;
3173         return Some(expr0_0);
3174     }
3175     return None;
3176 }
3177 
3178 // Generated as internal constructor for term trap_if_div_overflow.
3179 pub fn constructor_trap_if_div_overflow<C: Context>(
3180     ctx: &mut C,
3181     arg0: Type,
3182     arg1: Reg,
3183     arg2: Reg,
3184 ) -> Option<Reg> {
3185     let pattern0_0 = arg0;
3186     let pattern1_0 = arg1;
3187     let pattern2_0 = arg2;
3188     // Rule at src/isa/aarch64/inst.isle line 1926.
3189     let expr0_0 = ALUOp::AddS;
3190     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
3191     let expr2_0 = C::writable_zero_reg(ctx);
3192     let expr3_0: u8 = 1;
3193     let expr4_0 = C::u8_into_imm12(ctx, expr3_0);
3194     let expr5_0 = MInst::AluRRImm12 {
3195         alu_op: expr0_0,
3196         size: expr1_0,
3197         rd: expr2_0,
3198         rn: pattern2_0,
3199         imm12: expr4_0,
3200     };
3201     let expr6_0 = C::emit(ctx, &expr5_0);
3202     let expr7_0 = constructor_size_from_ty(ctx, pattern0_0)?;
3203     let expr8_0: u8 = 1;
3204     let expr9_0 = C::u8_into_uimm5(ctx, expr8_0);
3205     let expr10_0: bool = false;
3206     let expr11_0: bool = false;
3207     let expr12_0: bool = false;
3208     let expr13_0: bool = false;
3209     let expr14_0 = C::nzcv(ctx, expr10_0, expr11_0, expr12_0, expr13_0);
3210     let expr15_0 = Cond::Eq;
3211     let expr16_0 = MInst::CCmpImm {
3212         size: expr7_0,
3213         rn: pattern1_0,
3214         imm: expr9_0,
3215         nzcv: expr14_0,
3216         cond: expr15_0,
3217     };
3218     let expr17_0 = C::emit(ctx, &expr16_0);
3219     let expr18_0 = Cond::Vs;
3220     let expr19_0 = C::cond_br_cond(ctx, &expr18_0);
3221     let expr20_0 = C::trap_code_integer_overflow(ctx);
3222     let expr21_0 = MInst::TrapIf {
3223         kind: expr19_0,
3224         trap_code: expr20_0,
3225     };
3226     let expr22_0 = C::emit(ctx, &expr21_0);
3227     return Some(pattern1_0);
3228 }
3229 
3230 // Generated as internal constructor for term alu_rs_imm_logic_commutative.
3231 pub fn constructor_alu_rs_imm_logic_commutative<C: Context>(
3232     ctx: &mut C,
3233     arg0: &ALUOp,
3234     arg1: Type,
3235     arg2: Value,
3236     arg3: Value,
3237 ) -> Option<Reg> {
3238     let pattern0_0 = arg0;
3239     let pattern1_0 = arg1;
3240     let pattern2_0 = arg2;
3241     if let Some(pattern3_0) = C::def_inst(ctx, pattern2_0) {
3242         let pattern4_0 = C::inst_data(ctx, pattern3_0);
3243         match &pattern4_0 {
3244             &InstructionData::UnaryImm {
3245                 opcode: ref pattern5_0,
3246                 imm: pattern5_1,
3247             } => {
3248                 if let &Opcode::Iconst = pattern5_0 {
3249                     let closure7 = || {
3250                         return Some(pattern1_0);
3251                     };
3252                     if let Some(pattern7_0) = closure7() {
3253                         if let Some(pattern8_0) =
3254                             C::imm_logic_from_imm64(ctx, pattern5_1, pattern7_0)
3255                         {
3256                             let pattern9_0 = arg3;
3257                             // Rule at src/isa/aarch64/inst.isle line 1971.
3258                             let expr0_0 = C::put_in_reg(ctx, pattern9_0);
3259                             let expr1_0 = constructor_alu_rr_imm_logic(
3260                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0,
3261                             )?;
3262                             return Some(expr1_0);
3263                         }
3264                     }
3265                 }
3266             }
3267             &InstructionData::Binary {
3268                 opcode: ref pattern5_0,
3269                 args: ref pattern5_1,
3270             } => {
3271                 if let &Opcode::Ishl = pattern5_0 {
3272                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3273                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3274                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
3275                         if let &InstructionData::UnaryImm {
3276                             opcode: ref pattern10_0,
3277                             imm: pattern10_1,
3278                         } = &pattern9_0
3279                         {
3280                             if let &Opcode::Iconst = pattern10_0 {
3281                                 let closure12 = || {
3282                                     return Some(pattern1_0);
3283                                 };
3284                                 if let Some(pattern12_0) = closure12() {
3285                                     if let Some(pattern13_0) =
3286                                         C::lshl_from_imm64(ctx, pattern10_1, pattern12_0)
3287                                     {
3288                                         let pattern14_0 = arg3;
3289                                         // Rule at src/isa/aarch64/inst.isle line 1977.
3290                                         let expr0_0 = C::put_in_reg(ctx, pattern14_0);
3291                                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3292                                         let expr2_0 = constructor_alu_rrr_shift(
3293                                             ctx,
3294                                             pattern0_0,
3295                                             pattern1_0,
3296                                             expr0_0,
3297                                             expr1_0,
3298                                             pattern13_0,
3299                                         )?;
3300                                         return Some(expr2_0);
3301                                     }
3302                                 }
3303                             }
3304                         }
3305                     }
3306                 }
3307             }
3308             _ => {}
3309         }
3310     }
3311     let pattern3_0 = arg3;
3312     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3313         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3314         match &pattern5_0 {
3315             &InstructionData::UnaryImm {
3316                 opcode: ref pattern6_0,
3317                 imm: pattern6_1,
3318             } => {
3319                 if let &Opcode::Iconst = pattern6_0 {
3320                     let closure8 = || {
3321                         return Some(pattern1_0);
3322                     };
3323                     if let Some(pattern8_0) = closure8() {
3324                         if let Some(pattern9_0) =
3325                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3326                         {
3327                             // Rule at src/isa/aarch64/inst.isle line 1969.
3328                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3329                             let expr1_0 = constructor_alu_rr_imm_logic(
3330                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3331                             )?;
3332                             return Some(expr1_0);
3333                         }
3334                     }
3335                 }
3336             }
3337             &InstructionData::Binary {
3338                 opcode: ref pattern6_0,
3339                 args: ref pattern6_1,
3340             } => {
3341                 if let &Opcode::Ishl = pattern6_0 {
3342                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3343                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3344                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3345                         if let &InstructionData::UnaryImm {
3346                             opcode: ref pattern11_0,
3347                             imm: pattern11_1,
3348                         } = &pattern10_0
3349                         {
3350                             if let &Opcode::Iconst = pattern11_0 {
3351                                 let closure13 = || {
3352                                     return Some(pattern1_0);
3353                                 };
3354                                 if let Some(pattern13_0) = closure13() {
3355                                     if let Some(pattern14_0) =
3356                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3357                                     {
3358                                         // Rule at src/isa/aarch64/inst.isle line 1975.
3359                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3360                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3361                                         let expr2_0 = constructor_alu_rrr_shift(
3362                                             ctx,
3363                                             pattern0_0,
3364                                             pattern1_0,
3365                                             expr0_0,
3366                                             expr1_0,
3367                                             pattern14_0,
3368                                         )?;
3369                                         return Some(expr2_0);
3370                                     }
3371                                 }
3372                             }
3373                         }
3374                     }
3375                 }
3376             }
3377             _ => {}
3378         }
3379     }
3380     // Rule at src/isa/aarch64/inst.isle line 1965.
3381     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3382     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3383     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3384     return Some(expr2_0);
3385 }
3386 
3387 // Generated as internal constructor for term alu_rs_imm_logic.
3388 pub fn constructor_alu_rs_imm_logic<C: Context>(
3389     ctx: &mut C,
3390     arg0: &ALUOp,
3391     arg1: Type,
3392     arg2: Value,
3393     arg3: Value,
3394 ) -> Option<Reg> {
3395     let pattern0_0 = arg0;
3396     let pattern1_0 = arg1;
3397     let pattern2_0 = arg2;
3398     let pattern3_0 = arg3;
3399     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3400         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3401         match &pattern5_0 {
3402             &InstructionData::UnaryImm {
3403                 opcode: ref pattern6_0,
3404                 imm: pattern6_1,
3405             } => {
3406                 if let &Opcode::Iconst = pattern6_0 {
3407                     let closure8 = || {
3408                         return Some(pattern1_0);
3409                     };
3410                     if let Some(pattern8_0) = closure8() {
3411                         if let Some(pattern9_0) =
3412                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3413                         {
3414                             // Rule at src/isa/aarch64/inst.isle line 1985.
3415                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3416                             let expr1_0 = constructor_alu_rr_imm_logic(
3417                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3418                             )?;
3419                             return Some(expr1_0);
3420                         }
3421                     }
3422                 }
3423             }
3424             &InstructionData::Binary {
3425                 opcode: ref pattern6_0,
3426                 args: ref pattern6_1,
3427             } => {
3428                 if let &Opcode::Ishl = pattern6_0 {
3429                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3430                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3431                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3432                         if let &InstructionData::UnaryImm {
3433                             opcode: ref pattern11_0,
3434                             imm: pattern11_1,
3435                         } = &pattern10_0
3436                         {
3437                             if let &Opcode::Iconst = pattern11_0 {
3438                                 let closure13 = || {
3439                                     return Some(pattern1_0);
3440                                 };
3441                                 if let Some(pattern13_0) = closure13() {
3442                                     if let Some(pattern14_0) =
3443                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3444                                     {
3445                                         // Rule at src/isa/aarch64/inst.isle line 1987.
3446                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3447                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3448                                         let expr2_0 = constructor_alu_rrr_shift(
3449                                             ctx,
3450                                             pattern0_0,
3451                                             pattern1_0,
3452                                             expr0_0,
3453                                             expr1_0,
3454                                             pattern14_0,
3455                                         )?;
3456                                         return Some(expr2_0);
3457                                     }
3458                                 }
3459                             }
3460                         }
3461                     }
3462                 }
3463             }
3464             _ => {}
3465         }
3466     }
3467     // Rule at src/isa/aarch64/inst.isle line 1983.
3468     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3469     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3470     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3471     return Some(expr2_0);
3472 }
3473 
3474 // Generated as internal constructor for term i128_alu_bitop.
3475 pub fn constructor_i128_alu_bitop<C: Context>(
3476     ctx: &mut C,
3477     arg0: &ALUOp,
3478     arg1: Type,
3479     arg2: Value,
3480     arg3: Value,
3481 ) -> Option<ValueRegs> {
3482     let pattern0_0 = arg0;
3483     let pattern1_0 = arg1;
3484     let pattern2_0 = arg2;
3485     let pattern3_0 = arg3;
3486     // Rule at src/isa/aarch64/inst.isle line 1995.
3487     let expr0_0 = C::put_in_regs(ctx, pattern2_0);
3488     let expr1_0: usize = 0;
3489     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3490     let expr3_0: usize = 1;
3491     let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
3492     let expr5_0 = C::put_in_regs(ctx, pattern3_0);
3493     let expr6_0: usize = 0;
3494     let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
3495     let expr8_0: usize = 1;
3496     let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
3497     let expr10_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr2_0, expr7_0)?;
3498     let expr11_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr4_0, expr9_0)?;
3499     let expr12_0 = C::value_regs(ctx, expr10_0, expr11_0);
3500     return Some(expr12_0);
3501 }
3502 
3503 // Generated as internal constructor for term float_cmp_zero.
3504 pub fn constructor_float_cmp_zero<C: Context>(
3505     ctx: &mut C,
3506     arg0: &FloatCC,
3507     arg1: Reg,
3508     arg2: &VectorSize,
3509 ) -> Option<Reg> {
3510     let pattern0_0 = arg0;
3511     let pattern1_0 = arg1;
3512     let pattern2_0 = arg2;
3513     // Rule at src/isa/aarch64/inst.isle line 2035.
3514     let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0);
3515     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3516     return Some(expr1_0);
3517 }
3518 
3519 // Generated as internal constructor for term float_cmp_zero_swap.
3520 pub fn constructor_float_cmp_zero_swap<C: Context>(
3521     ctx: &mut C,
3522     arg0: &FloatCC,
3523     arg1: Reg,
3524     arg2: &VectorSize,
3525 ) -> Option<Reg> {
3526     let pattern0_0 = arg0;
3527     let pattern1_0 = arg1;
3528     let pattern2_0 = arg2;
3529     // Rule at src/isa/aarch64/inst.isle line 2040.
3530     let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0);
3531     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3532     return Some(expr1_0);
3533 }
3534 
3535 // Generated as internal constructor for term fcmeq0.
3536 pub fn constructor_fcmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3537     let pattern0_0 = arg0;
3538     let pattern1_0 = arg1;
3539     // Rule at src/isa/aarch64/inst.isle line 2045.
3540     let expr0_0 = VecMisc2::Fcmeq0;
3541     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3542     return Some(expr1_0);
3543 }
3544 
3545 // Generated as internal constructor for term int_cmp_zero.
3546 pub fn constructor_int_cmp_zero<C: Context>(
3547     ctx: &mut C,
3548     arg0: &IntCC,
3549     arg1: Reg,
3550     arg2: &VectorSize,
3551 ) -> Option<Reg> {
3552     let pattern0_0 = arg0;
3553     let pattern1_0 = arg1;
3554     let pattern2_0 = arg2;
3555     // Rule at src/isa/aarch64/inst.isle line 2071.
3556     let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0);
3557     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3558     return Some(expr1_0);
3559 }
3560 
3561 // Generated as internal constructor for term int_cmp_zero_swap.
3562 pub fn constructor_int_cmp_zero_swap<C: Context>(
3563     ctx: &mut C,
3564     arg0: &IntCC,
3565     arg1: Reg,
3566     arg2: &VectorSize,
3567 ) -> Option<Reg> {
3568     let pattern0_0 = arg0;
3569     let pattern1_0 = arg1;
3570     let pattern2_0 = arg2;
3571     // Rule at src/isa/aarch64/inst.isle line 2076.
3572     let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0);
3573     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3574     return Some(expr1_0);
3575 }
3576 
3577 // Generated as internal constructor for term cmeq0.
3578 pub fn constructor_cmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3579     let pattern0_0 = arg0;
3580     let pattern1_0 = arg1;
3581     // Rule at src/isa/aarch64/inst.isle line 2081.
3582     let expr0_0 = VecMisc2::Cmeq0;
3583     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3584     return Some(expr1_0);
3585 }
3586 
3587 // Generated as internal constructor for term lower.
3588 pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> {
3589     let pattern0_0 = arg0;
3590     if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
3591         let pattern2_0 = C::value_type(ctx, pattern1_0);
3592         if pattern2_0 == I8 {
3593             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3594             if let &InstructionData::Unary {
3595                 opcode: ref pattern5_0,
3596                 arg: pattern5_1,
3597             } = &pattern4_0
3598             {
3599                 match pattern5_0 {
3600                     &Opcode::Bitrev => {
3601                         // Rule at src/isa/aarch64/lower.isle line 980.
3602                         let expr0_0: Type = I32;
3603                         let expr1_0: Type = I32;
3604                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3605                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3606                         let expr4_0: u8 = 24;
3607                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3608                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3609                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3610                         return Some(expr7_0);
3611                     }
3612                     &Opcode::Clz => {
3613                         // Rule at src/isa/aarch64/lower.isle line 1001.
3614                         let expr0_0: Type = I32;
3615                         let expr1_0: Type = I32;
3616                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3617                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3618                         let expr4_0: u8 = 24;
3619                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3620                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3621                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3622                         return Some(expr7_0);
3623                     }
3624                     &Opcode::Cls => {
3625                         // Rule at src/isa/aarch64/lower.isle line 1048.
3626                         let expr0_0: Type = I32;
3627                         let expr1_0: Type = I32;
3628                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3629                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3630                         let expr4_0: u8 = 24;
3631                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3632                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3633                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3634                         return Some(expr7_0);
3635                     }
3636                     &Opcode::Ctz => {
3637                         // Rule at src/isa/aarch64/lower.isle line 1031.
3638                         let expr0_0: Type = I32;
3639                         let expr1_0: Type = I32;
3640                         let expr2_0: Type = I32;
3641                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3642                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3643                         let expr5_0: Type = I32;
3644                         let expr6_0: u64 = 8388608;
3645                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3646                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3647                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3648                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3649                         return Some(expr10_0);
3650                     }
3651                     &Opcode::Popcnt => {
3652                         // Rule at src/isa/aarch64/lower.isle line 1099.
3653                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3654                         let expr1_0 = ScalarSize::Size32;
3655                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3656                         let expr3_0 = VectorSize::Size8x8;
3657                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3658                         let expr5_0: u8 = 0;
3659                         let expr6_0 = VectorSize::Size8x16;
3660                         let expr7_0 = constructor_mov_from_vec(ctx, expr4_0, expr5_0, &expr6_0)?;
3661                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
3662                         return Some(expr8_0);
3663                     }
3664                     _ => {}
3665                 }
3666             }
3667         }
3668         if pattern2_0 == I16 {
3669             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3670             if let &InstructionData::Unary {
3671                 opcode: ref pattern5_0,
3672                 arg: pattern5_1,
3673             } = &pattern4_0
3674             {
3675                 match pattern5_0 {
3676                     &Opcode::Bitrev => {
3677                         // Rule at src/isa/aarch64/lower.isle line 986.
3678                         let expr0_0: Type = I32;
3679                         let expr1_0: Type = I32;
3680                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3681                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3682                         let expr4_0: u8 = 16;
3683                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3684                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3685                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3686                         return Some(expr7_0);
3687                     }
3688                     &Opcode::Clz => {
3689                         // Rule at src/isa/aarch64/lower.isle line 1004.
3690                         let expr0_0: Type = I32;
3691                         let expr1_0: Type = I32;
3692                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3693                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3694                         let expr4_0: u8 = 16;
3695                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3696                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3697                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3698                         return Some(expr7_0);
3699                     }
3700                     &Opcode::Cls => {
3701                         // Rule at src/isa/aarch64/lower.isle line 1051.
3702                         let expr0_0: Type = I32;
3703                         let expr1_0: Type = I32;
3704                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3705                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3706                         let expr4_0: u8 = 16;
3707                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3708                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3709                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3710                         return Some(expr7_0);
3711                     }
3712                     &Opcode::Ctz => {
3713                         // Rule at src/isa/aarch64/lower.isle line 1034.
3714                         let expr0_0: Type = I32;
3715                         let expr1_0: Type = I32;
3716                         let expr2_0: Type = I32;
3717                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3718                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3719                         let expr5_0: Type = I32;
3720                         let expr6_0: u64 = 32768;
3721                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3722                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3723                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3724                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3725                         return Some(expr10_0);
3726                     }
3727                     &Opcode::Popcnt => {
3728                         // Rule at src/isa/aarch64/lower.isle line 1105.
3729                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3730                         let expr1_0 = ScalarSize::Size32;
3731                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3732                         let expr3_0 = VectorSize::Size8x8;
3733                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3734                         let expr5_0 = VectorSize::Size8x8;
3735                         let expr6_0 = constructor_addp(ctx, expr4_0, expr4_0, &expr5_0)?;
3736                         let expr7_0: u8 = 0;
3737                         let expr8_0 = VectorSize::Size8x16;
3738                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3739                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3740                         return Some(expr10_0);
3741                     }
3742                     _ => {}
3743                 }
3744             }
3745         }
3746         if pattern2_0 == I32 {
3747             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3748             match &pattern4_0 {
3749                 &InstructionData::Binary {
3750                     opcode: ref pattern5_0,
3751                     args: ref pattern5_1,
3752                 } => {
3753                     match pattern5_0 {
3754                         &Opcode::Rotl => {
3755                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3756                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3757                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3758                                 if let &InstructionData::UnaryImm {
3759                                     opcode: ref pattern10_0,
3760                                     imm: pattern10_1,
3761                                 } = &pattern9_0
3762                                 {
3763                                     if let &Opcode::Iconst = pattern10_0 {
3764                                         let closure12 = || {
3765                                             let expr0_0: Type = I32;
3766                                             return Some(expr0_0);
3767                                         };
3768                                         if let Some(pattern12_0) = closure12() {
3769                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3770                                                 ctx,
3771                                                 pattern10_1,
3772                                                 pattern12_0,
3773                                             ) {
3774                                                 // Rule at src/isa/aarch64/lower.isle line 871.
3775                                                 let expr0_0: Type = I32;
3776                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3777                                                 let expr2_0: Type = I32;
3778                                                 let expr3_0 =
3779                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3780                                                 let expr4_0 = constructor_a64_rotr_imm(
3781                                                     ctx, expr0_0, expr1_0, expr3_0,
3782                                                 )?;
3783                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3784                                                 return Some(expr5_0);
3785                                             }
3786                                         }
3787                                     }
3788                                 }
3789                             }
3790                             // Rule at src/isa/aarch64/lower.isle line 861.
3791                             let expr0_0: Type = I32;
3792                             let expr1_0 = C::zero_reg(ctx);
3793                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3794                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3795                             let expr4_0: Type = I32;
3796                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3797                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3798                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3799                             return Some(expr7_0);
3800                         }
3801                         &Opcode::Rotr => {
3802                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3803                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3804                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3805                                 if let &InstructionData::UnaryImm {
3806                                     opcode: ref pattern10_0,
3807                                     imm: pattern10_1,
3808                                 } = &pattern9_0
3809                                 {
3810                                     if let &Opcode::Iconst = pattern10_0 {
3811                                         let closure12 = || {
3812                                             let expr0_0: Type = I32;
3813                                             return Some(expr0_0);
3814                                         };
3815                                         if let Some(pattern12_0) = closure12() {
3816                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3817                                                 ctx,
3818                                                 pattern10_1,
3819                                                 pattern12_0,
3820                                             ) {
3821                                                 // Rule at src/isa/aarch64/lower.isle line 913.
3822                                                 let expr0_0: Type = I32;
3823                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3824                                                 let expr2_0 = constructor_a64_rotr_imm(
3825                                                     ctx,
3826                                                     expr0_0,
3827                                                     expr1_0,
3828                                                     pattern13_0,
3829                                                 )?;
3830                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3831                                                 return Some(expr3_0);
3832                                             }
3833                                         }
3834                                     }
3835                                 }
3836                             }
3837                             // Rule at src/isa/aarch64/lower.isle line 901.
3838                             let expr0_0: Type = I32;
3839                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3840                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3841                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
3842                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3843                             return Some(expr4_0);
3844                         }
3845                         _ => {}
3846                     }
3847                 }
3848                 &InstructionData::Unary {
3849                     opcode: ref pattern5_0,
3850                     arg: pattern5_1,
3851                 } => {
3852                     if let &Opcode::Popcnt = pattern5_0 {
3853                         // Rule at src/isa/aarch64/lower.isle line 1111.
3854                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3855                         let expr1_0 = ScalarSize::Size32;
3856                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3857                         let expr3_0 = VectorSize::Size8x8;
3858                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3859                         let expr5_0 = VectorSize::Size8x8;
3860                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
3861                         let expr7_0: u8 = 0;
3862                         let expr8_0 = VectorSize::Size8x16;
3863                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3864                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3865                         return Some(expr10_0);
3866                     }
3867                 }
3868                 _ => {}
3869             }
3870         }
3871         if pattern2_0 == I64 {
3872             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3873             match &pattern4_0 {
3874                 &InstructionData::Binary {
3875                     opcode: ref pattern5_0,
3876                     args: ref pattern5_1,
3877                 } => {
3878                     match pattern5_0 {
3879                         &Opcode::Umulhi => {
3880                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3881                             // Rule at src/isa/aarch64/lower.isle line 371.
3882                             let expr0_0: Type = I64;
3883                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3884                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3885                             let expr3_0 = constructor_umulh(ctx, expr0_0, expr1_0, expr2_0)?;
3886                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3887                             return Some(expr4_0);
3888                         }
3889                         &Opcode::Smulhi => {
3890                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3891                             // Rule at src/isa/aarch64/lower.isle line 359.
3892                             let expr0_0: Type = I64;
3893                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3894                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3895                             let expr3_0 = constructor_smulh(ctx, expr0_0, expr1_0, expr2_0)?;
3896                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3897                             return Some(expr4_0);
3898                         }
3899                         &Opcode::Band => {
3900                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3901                             // Rule at src/isa/aarch64/lower.isle line 592.
3902                             let expr0_0 = ALUOp::And;
3903                             let expr1_0: Type = I64;
3904                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3905                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3906                             )?;
3907                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3908                             return Some(expr3_0);
3909                         }
3910                         &Opcode::Bor => {
3911                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3912                             // Rule at src/isa/aarch64/lower.isle line 605.
3913                             let expr0_0 = ALUOp::Orr;
3914                             let expr1_0: Type = I64;
3915                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3916                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3917                             )?;
3918                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3919                             return Some(expr3_0);
3920                         }
3921                         &Opcode::Bxor => {
3922                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3923                             // Rule at src/isa/aarch64/lower.isle line 618.
3924                             let expr0_0 = ALUOp::Eor;
3925                             let expr1_0: Type = I64;
3926                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3927                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3928                             )?;
3929                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3930                             return Some(expr3_0);
3931                         }
3932                         &Opcode::BandNot => {
3933                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3934                             // Rule at src/isa/aarch64/lower.isle line 631.
3935                             let expr0_0 = ALUOp::AndNot;
3936                             let expr1_0: Type = I64;
3937                             let expr2_0 = constructor_alu_rs_imm_logic(
3938                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3939                             )?;
3940                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3941                             return Some(expr3_0);
3942                         }
3943                         &Opcode::BorNot => {
3944                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3945                             // Rule at src/isa/aarch64/lower.isle line 644.
3946                             let expr0_0 = ALUOp::OrrNot;
3947                             let expr1_0: Type = I64;
3948                             let expr2_0 = constructor_alu_rs_imm_logic(
3949                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3950                             )?;
3951                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3952                             return Some(expr3_0);
3953                         }
3954                         &Opcode::BxorNot => {
3955                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3956                             // Rule at src/isa/aarch64/lower.isle line 654.
3957                             let expr0_0 = ALUOp::EorNot;
3958                             let expr1_0: Type = I64;
3959                             let expr2_0 = constructor_alu_rs_imm_logic(
3960                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3961                             )?;
3962                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3963                             return Some(expr3_0);
3964                         }
3965                         &Opcode::Rotl => {
3966                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3967                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3968                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3969                                 if let &InstructionData::UnaryImm {
3970                                     opcode: ref pattern10_0,
3971                                     imm: pattern10_1,
3972                                 } = &pattern9_0
3973                                 {
3974                                     if let &Opcode::Iconst = pattern10_0 {
3975                                         let closure12 = || {
3976                                             let expr0_0: Type = I64;
3977                                             return Some(expr0_0);
3978                                         };
3979                                         if let Some(pattern12_0) = closure12() {
3980                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3981                                                 ctx,
3982                                                 pattern10_1,
3983                                                 pattern12_0,
3984                                             ) {
3985                                                 // Rule at src/isa/aarch64/lower.isle line 875.
3986                                                 let expr0_0: Type = I64;
3987                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3988                                                 let expr2_0: Type = I64;
3989                                                 let expr3_0 =
3990                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3991                                                 let expr4_0 = constructor_a64_rotr_imm(
3992                                                     ctx, expr0_0, expr1_0, expr3_0,
3993                                                 )?;
3994                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3995                                                 return Some(expr5_0);
3996                                             }
3997                                         }
3998                                     }
3999                                 }
4000                             }
4001                             // Rule at src/isa/aarch64/lower.isle line 866.
4002                             let expr0_0: Type = I64;
4003                             let expr1_0 = C::zero_reg(ctx);
4004                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4005                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
4006                             let expr4_0: Type = I64;
4007                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
4008                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
4009                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
4010                             return Some(expr7_0);
4011                         }
4012                         &Opcode::Rotr => {
4013                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4014                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
4015                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
4016                                 if let &InstructionData::UnaryImm {
4017                                     opcode: ref pattern10_0,
4018                                     imm: pattern10_1,
4019                                 } = &pattern9_0
4020                                 {
4021                                     if let &Opcode::Iconst = pattern10_0 {
4022                                         let closure12 = || {
4023                                             let expr0_0: Type = I64;
4024                                             return Some(expr0_0);
4025                                         };
4026                                         if let Some(pattern12_0) = closure12() {
4027                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4028                                                 ctx,
4029                                                 pattern10_1,
4030                                                 pattern12_0,
4031                                             ) {
4032                                                 // Rule at src/isa/aarch64/lower.isle line 917.
4033                                                 let expr0_0: Type = I64;
4034                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4035                                                 let expr2_0 = constructor_a64_rotr_imm(
4036                                                     ctx,
4037                                                     expr0_0,
4038                                                     expr1_0,
4039                                                     pattern13_0,
4040                                                 )?;
4041                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4042                                                 return Some(expr3_0);
4043                                             }
4044                                         }
4045                                     }
4046                                 }
4047                             }
4048                             // Rule at src/isa/aarch64/lower.isle line 905.
4049                             let expr0_0: Type = I64;
4050                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4051                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4052                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
4053                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4054                             return Some(expr4_0);
4055                         }
4056                         &Opcode::Ishl => {
4057                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4058                             // Rule at src/isa/aarch64/lower.isle line 666.
4059                             let expr0_0 = ALUOp::Lsl;
4060                             let expr1_0: Type = I64;
4061                             let expr2_0 = C::put_in_reg(ctx, pattern7_0);
4062                             let expr3_0 =
4063                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4064                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4065                             return Some(expr4_0);
4066                         }
4067                         &Opcode::Ushr => {
4068                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4069                             // Rule at src/isa/aarch64/lower.isle line 750.
4070                             let expr0_0 = ALUOp::Lsr;
4071                             let expr1_0: Type = I64;
4072                             let expr2_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
4073                             let expr3_0 =
4074                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4075                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4076                             return Some(expr4_0);
4077                         }
4078                         &Opcode::Sshr => {
4079                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4080                             // Rule at src/isa/aarch64/lower.isle line 797.
4081                             let expr0_0 = ALUOp::Asr;
4082                             let expr1_0: Type = I64;
4083                             let expr2_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
4084                             let expr3_0 =
4085                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4086                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4087                             return Some(expr4_0);
4088                         }
4089                         _ => {}
4090                     }
4091                 }
4092                 &InstructionData::Unary {
4093                     opcode: ref pattern5_0,
4094                     arg: pattern5_1,
4095                 } => {
4096                     if let &Opcode::Popcnt = pattern5_0 {
4097                         // Rule at src/isa/aarch64/lower.isle line 1117.
4098                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4099                         let expr1_0 = ScalarSize::Size64;
4100                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
4101                         let expr3_0 = VectorSize::Size8x8;
4102                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
4103                         let expr5_0 = VectorSize::Size8x8;
4104                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
4105                         let expr7_0: u8 = 0;
4106                         let expr8_0 = VectorSize::Size8x16;
4107                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
4108                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
4109                         return Some(expr10_0);
4110                     }
4111                 }
4112                 _ => {}
4113             }
4114         }
4115         if pattern2_0 == I128 {
4116             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4117             match &pattern4_0 {
4118                 &InstructionData::Binary {
4119                     opcode: ref pattern5_0,
4120                     args: ref pattern5_1,
4121                 } => {
4122                     match pattern5_0 {
4123                         &Opcode::Iadd => {
4124                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4125                             // Rule at src/isa/aarch64/lower.isle line 83.
4126                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4127                             let expr1_0: usize = 0;
4128                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4129                             let expr3_0: usize = 1;
4130                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4131                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4132                             let expr6_0: usize = 0;
4133                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4134                             let expr8_0: usize = 1;
4135                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4136                             let expr10_0: Type = I64;
4137                             let expr11_0 =
4138                                 constructor_add_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4139                             let expr12_0: Type = I64;
4140                             let expr13_0 = constructor_adc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4141                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4142                             let expr15_0 = C::output(ctx, expr14_0);
4143                             return Some(expr15_0);
4144                         }
4145                         &Opcode::Isub => {
4146                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4147                             // Rule at src/isa/aarch64/lower.isle line 133.
4148                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4149                             let expr1_0: usize = 0;
4150                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4151                             let expr3_0: usize = 1;
4152                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4153                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4154                             let expr6_0: usize = 0;
4155                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4156                             let expr8_0: usize = 1;
4157                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4158                             let expr10_0: Type = I64;
4159                             let expr11_0 =
4160                                 constructor_sub_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4161                             let expr12_0: Type = I64;
4162                             let expr13_0 = constructor_sbc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4163                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4164                             let expr15_0 = C::output(ctx, expr14_0);
4165                             return Some(expr15_0);
4166                         }
4167                         &Opcode::Imul => {
4168                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4169                             // Rule at src/isa/aarch64/lower.isle line 187.
4170                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4171                             let expr1_0: usize = 0;
4172                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4173                             let expr3_0: usize = 1;
4174                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4175                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4176                             let expr6_0: usize = 0;
4177                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4178                             let expr8_0: usize = 1;
4179                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4180                             let expr10_0: Type = I64;
4181                             let expr11_0 = constructor_umulh(ctx, expr10_0, expr2_0, expr7_0)?;
4182                             let expr12_0: Type = I64;
4183                             let expr13_0 =
4184                                 constructor_madd(ctx, expr12_0, expr2_0, expr9_0, expr11_0)?;
4185                             let expr14_0: Type = I64;
4186                             let expr15_0 =
4187                                 constructor_madd(ctx, expr14_0, expr4_0, expr7_0, expr13_0)?;
4188                             let expr16_0: Type = I64;
4189                             let expr17_0 = C::zero_reg(ctx);
4190                             let expr18_0 =
4191                                 constructor_madd(ctx, expr16_0, expr2_0, expr7_0, expr17_0)?;
4192                             let expr19_0 = C::value_regs(ctx, expr18_0, expr15_0);
4193                             let expr20_0 = C::output(ctx, expr19_0);
4194                             return Some(expr20_0);
4195                         }
4196                         &Opcode::Band => {
4197                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4198                             // Rule at src/isa/aarch64/lower.isle line 595.
4199                             let expr0_0 = ALUOp::And;
4200                             let expr1_0: Type = I64;
4201                             let expr2_0 = constructor_i128_alu_bitop(
4202                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4203                             )?;
4204                             let expr3_0 = C::output(ctx, expr2_0);
4205                             return Some(expr3_0);
4206                         }
4207                         &Opcode::Bor => {
4208                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4209                             // Rule at src/isa/aarch64/lower.isle line 608.
4210                             let expr0_0 = ALUOp::Orr;
4211                             let expr1_0: Type = I64;
4212                             let expr2_0 = constructor_i128_alu_bitop(
4213                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4214                             )?;
4215                             let expr3_0 = C::output(ctx, expr2_0);
4216                             return Some(expr3_0);
4217                         }
4218                         &Opcode::Bxor => {
4219                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4220                             // Rule at src/isa/aarch64/lower.isle line 621.
4221                             let expr0_0 = ALUOp::Eor;
4222                             let expr1_0: Type = I64;
4223                             let expr2_0 = constructor_i128_alu_bitop(
4224                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4225                             )?;
4226                             let expr3_0 = C::output(ctx, expr2_0);
4227                             return Some(expr3_0);
4228                         }
4229                         &Opcode::BandNot => {
4230                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4231                             // Rule at src/isa/aarch64/lower.isle line 634.
4232                             let expr0_0 = ALUOp::AndNot;
4233                             let expr1_0: Type = I64;
4234                             let expr2_0 = constructor_i128_alu_bitop(
4235                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4236                             )?;
4237                             let expr3_0 = C::output(ctx, expr2_0);
4238                             return Some(expr3_0);
4239                         }
4240                         &Opcode::BorNot => {
4241                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4242                             // Rule at src/isa/aarch64/lower.isle line 647.
4243                             let expr0_0 = ALUOp::OrrNot;
4244                             let expr1_0: Type = I64;
4245                             let expr2_0 = constructor_i128_alu_bitop(
4246                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4247                             )?;
4248                             let expr3_0 = C::output(ctx, expr2_0);
4249                             return Some(expr3_0);
4250                         }
4251                         &Opcode::BxorNot => {
4252                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4253                             // Rule at src/isa/aarch64/lower.isle line 657.
4254                             let expr0_0 = ALUOp::EorNot;
4255                             let expr1_0: Type = I64;
4256                             let expr2_0 = constructor_i128_alu_bitop(
4257                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4258                             )?;
4259                             let expr3_0 = C::output(ctx, expr2_0);
4260                             return Some(expr3_0);
4261                         }
4262                         &Opcode::Rotl => {
4263                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4264                             // Rule at src/isa/aarch64/lower.isle line 884.
4265                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4266                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4267                             let expr2_0: usize = 0;
4268                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4269                             let expr4_0: Type = I64;
4270                             let expr5_0: Type = I64;
4271                             let expr6_0: u64 = 128;
4272                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4273                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4274                             let expr9_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4275                             let expr10_0 = constructor_lower_ushr128(ctx, expr0_0, expr8_0)?;
4276                             let expr11_0: Type = I64;
4277                             let expr12_0: usize = 0;
4278                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4279                             let expr14_0: usize = 0;
4280                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4281                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4282                             let expr17_0: Type = I64;
4283                             let expr18_0: usize = 1;
4284                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4285                             let expr20_0: usize = 1;
4286                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4287                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4288                             let expr23_0 = C::value_regs(ctx, expr16_0, expr22_0);
4289                             let expr24_0 = C::output(ctx, expr23_0);
4290                             return Some(expr24_0);
4291                         }
4292                         &Opcode::Rotr => {
4293                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4294                             // Rule at src/isa/aarch64/lower.isle line 965.
4295                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4296                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4297                             let expr2_0: usize = 0;
4298                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4299                             let expr4_0: Type = I64;
4300                             let expr5_0: Type = I64;
4301                             let expr6_0: u64 = 128;
4302                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4303                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4304                             let expr9_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4305                             let expr10_0 = constructor_lower_shl128(ctx, expr0_0, expr8_0)?;
4306                             let expr11_0: Type = I64;
4307                             let expr12_0: usize = 1;
4308                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4309                             let expr14_0: usize = 1;
4310                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4311                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4312                             let expr17_0: Type = I64;
4313                             let expr18_0: usize = 0;
4314                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4315                             let expr20_0: usize = 0;
4316                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4317                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4318                             let expr23_0 = C::value_regs(ctx, expr22_0, expr16_0);
4319                             let expr24_0 = C::output(ctx, expr23_0);
4320                             return Some(expr24_0);
4321                         }
4322                         &Opcode::Ishl => {
4323                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4324                             // Rule at src/isa/aarch64/lower.isle line 670.
4325                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4326                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4327                             let expr2_0: usize = 0;
4328                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4329                             let expr4_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4330                             let expr5_0 = C::output(ctx, expr4_0);
4331                             return Some(expr5_0);
4332                         }
4333                         &Opcode::Ushr => {
4334                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4335                             // Rule at src/isa/aarch64/lower.isle line 754.
4336                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4337                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4338                             let expr2_0: usize = 0;
4339                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4340                             let expr4_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4341                             let expr5_0 = C::output(ctx, expr4_0);
4342                             return Some(expr5_0);
4343                         }
4344                         &Opcode::Sshr => {
4345                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4346                             // Rule at src/isa/aarch64/lower.isle line 801.
4347                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4348                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4349                             let expr2_0: usize = 0;
4350                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4351                             let expr4_0 = constructor_lower_sshr128(ctx, expr0_0, expr3_0)?;
4352                             let expr5_0 = C::output(ctx, expr4_0);
4353                             return Some(expr5_0);
4354                         }
4355                         _ => {}
4356                     }
4357                 }
4358                 &InstructionData::Unary {
4359                     opcode: ref pattern5_0,
4360                     arg: pattern5_1,
4361                 } => {
4362                     match pattern5_0 {
4363                         &Opcode::Bnot => {
4364                             // Rule at src/isa/aarch64/lower.isle line 575.
4365                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4366                             let expr1_0: usize = 0;
4367                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4368                             let expr3_0: usize = 1;
4369                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4370                             let expr5_0: Type = I64;
4371                             let expr6_0 = C::zero_reg(ctx);
4372                             let expr7_0 = constructor_orr_not(ctx, expr5_0, expr6_0, expr2_0)?;
4373                             let expr8_0: Type = I64;
4374                             let expr9_0 = C::zero_reg(ctx);
4375                             let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, expr4_0)?;
4376                             let expr11_0 = C::value_regs(ctx, expr7_0, expr10_0);
4377                             let expr12_0 = C::output(ctx, expr11_0);
4378                             return Some(expr12_0);
4379                         }
4380                         &Opcode::Bitrev => {
4381                             // Rule at src/isa/aarch64/lower.isle line 989.
4382                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4383                             let expr1_0: Type = I64;
4384                             let expr2_0: usize = 0;
4385                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4386                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4387                             let expr5_0: Type = I64;
4388                             let expr6_0: usize = 1;
4389                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4390                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4391                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4392                             let expr10_0 = C::output(ctx, expr9_0);
4393                             return Some(expr10_0);
4394                         }
4395                         &Opcode::Clz => {
4396                             // Rule at src/isa/aarch64/lower.isle line 1007.
4397                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4398                             let expr1_0 = constructor_lower_clz128(ctx, expr0_0)?;
4399                             let expr2_0 = C::output(ctx, expr1_0);
4400                             return Some(expr2_0);
4401                         }
4402                         &Opcode::Cls => {
4403                             // Rule at src/isa/aarch64/lower.isle line 1063.
4404                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4405                             let expr1_0: usize = 0;
4406                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4407                             let expr3_0: usize = 1;
4408                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4409                             let expr5_0: Type = I64;
4410                             let expr6_0 = constructor_a64_cls(ctx, expr5_0, expr2_0)?;
4411                             let expr7_0: Type = I64;
4412                             let expr8_0 = constructor_a64_cls(ctx, expr7_0, expr4_0)?;
4413                             let expr9_0: Type = I64;
4414                             let expr10_0 = constructor_eon(ctx, expr9_0, expr4_0, expr2_0)?;
4415                             let expr11_0: Type = I64;
4416                             let expr12_0: u8 = 63;
4417                             let expr13_0 = C::imm_shift_from_u8(ctx, expr12_0);
4418                             let expr14_0 = constructor_lsr_imm(ctx, expr11_0, expr10_0, expr13_0)?;
4419                             let expr15_0: Type = I64;
4420                             let expr16_0 =
4421                                 constructor_madd(ctx, expr15_0, expr6_0, expr14_0, expr14_0)?;
4422                             let expr17_0: u8 = 63;
4423                             let expr18_0 = C::u8_into_imm12(ctx, expr17_0);
4424                             let expr19_0 = constructor_cmp64_imm(ctx, expr8_0, expr18_0)?;
4425                             let expr20_0 = Cond::Eq;
4426                             let expr21_0 = C::zero_reg(ctx);
4427                             let expr22_0 = constructor_csel(ctx, &expr20_0, expr16_0, expr21_0)?;
4428                             let expr23_0 = constructor_with_flags_reg(ctx, &expr19_0, &expr22_0)?;
4429                             let expr24_0: Type = I64;
4430                             let expr25_0 = constructor_add(ctx, expr24_0, expr23_0, expr8_0)?;
4431                             let expr26_0: Type = I64;
4432                             let expr27_0: u64 = 0;
4433                             let expr28_0 = constructor_imm(ctx, expr26_0, expr27_0)?;
4434                             let expr29_0 = C::value_regs(ctx, expr25_0, expr28_0);
4435                             let expr30_0 = C::output(ctx, expr29_0);
4436                             return Some(expr30_0);
4437                         }
4438                         &Opcode::Ctz => {
4439                             // Rule at src/isa/aarch64/lower.isle line 1037.
4440                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4441                             let expr1_0: Type = I64;
4442                             let expr2_0: usize = 0;
4443                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4444                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4445                             let expr5_0: Type = I64;
4446                             let expr6_0: usize = 1;
4447                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4448                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4449                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4450                             let expr10_0 = constructor_lower_clz128(ctx, expr9_0)?;
4451                             let expr11_0 = C::output(ctx, expr10_0);
4452                             return Some(expr11_0);
4453                         }
4454                         &Opcode::Popcnt => {
4455                             // Rule at src/isa/aarch64/lower.isle line 1123.
4456                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4457                             let expr1_0: usize = 0;
4458                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4459                             let expr3_0 = ScalarSize::Size64;
4460                             let expr4_0 = constructor_mov_to_fpu(ctx, expr2_0, &expr3_0)?;
4461                             let expr5_0: usize = 1;
4462                             let expr6_0 = C::value_regs_get(ctx, expr0_0, expr5_0);
4463                             let expr7_0: u8 = 1;
4464                             let expr8_0 = VectorSize::Size64x2;
4465                             let expr9_0 =
4466                                 constructor_mov_to_vec(ctx, expr4_0, expr6_0, expr7_0, &expr8_0)?;
4467                             let expr10_0 = VectorSize::Size8x16;
4468                             let expr11_0 = constructor_vec_cnt(ctx, expr9_0, &expr10_0)?;
4469                             let expr12_0 = VectorSize::Size8x16;
4470                             let expr13_0 = constructor_addv(ctx, expr11_0, &expr12_0)?;
4471                             let expr14_0: u8 = 0;
4472                             let expr15_0 = VectorSize::Size8x16;
4473                             let expr16_0 =
4474                                 constructor_mov_from_vec(ctx, expr13_0, expr14_0, &expr15_0)?;
4475                             let expr17_0: Type = I64;
4476                             let expr18_0: u64 = 0;
4477                             let expr19_0 = constructor_imm(ctx, expr17_0, expr18_0)?;
4478                             let expr20_0 = C::value_regs(ctx, expr16_0, expr19_0);
4479                             let expr21_0 = C::output(ctx, expr20_0);
4480                             return Some(expr21_0);
4481                         }
4482                         &Opcode::Uextend => {
4483                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4484                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4485                                 if let &InstructionData::BinaryImm8 {
4486                                     opcode: ref pattern9_0,
4487                                     arg: pattern9_1,
4488                                     imm: pattern9_2,
4489                                 } = &pattern8_0
4490                                 {
4491                                     if let &Opcode::Extractlane = pattern9_0 {
4492                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4493                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
4494                                         // Rule at src/isa/aarch64/lower.isle line 505.
4495                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4496                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
4497                                         let expr2_0 = constructor_mov_from_vec(
4498                                             ctx,
4499                                             expr0_0,
4500                                             pattern12_0,
4501                                             &expr1_0,
4502                                         )?;
4503                                         let expr3_0: Type = I64;
4504                                         let expr4_0: u64 = 0;
4505                                         let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
4506                                         let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
4507                                         let expr7_0 = C::output(ctx, expr6_0);
4508                                         return Some(expr7_0);
4509                                     }
4510                                 }
4511                             }
4512                             // Rule at src/isa/aarch64/lower.isle line 500.
4513                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
4514                             let expr1_0: Type = I64;
4515                             let expr2_0: u64 = 0;
4516                             let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
4517                             let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
4518                             let expr5_0 = C::output(ctx, expr4_0);
4519                             return Some(expr5_0);
4520                         }
4521                         &Opcode::Sextend => {
4522                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4523                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4524                                 if let &InstructionData::BinaryImm8 {
4525                                     opcode: ref pattern9_0,
4526                                     arg: pattern9_1,
4527                                     imm: pattern9_2,
4528                                 } = &pattern8_0
4529                                 {
4530                                     if let &Opcode::Extractlane = pattern9_0 {
4531                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4532                                         if pattern11_0 == I64X2 {
4533                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4534                                             // Rule at src/isa/aarch64/lower.isle line 549.
4535                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4536                                             let expr1_0 = VectorSize::Size64x2;
4537                                             let expr2_0 = constructor_mov_from_vec(
4538                                                 ctx,
4539                                                 expr0_0,
4540                                                 pattern13_0,
4541                                                 &expr1_0,
4542                                             )?;
4543                                             let expr3_0: Type = I64;
4544                                             let expr4_0: u8 = 63;
4545                                             let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
4546                                             let expr6_0 = constructor_asr_imm(
4547                                                 ctx, expr3_0, expr2_0, expr5_0,
4548                                             )?;
4549                                             let expr7_0 = C::value_regs(ctx, expr2_0, expr6_0);
4550                                             let expr8_0 = C::output(ctx, expr7_0);
4551                                             return Some(expr8_0);
4552                                         }
4553                                         if let Some(()) = C::not_i64x2(ctx, pattern11_0) {
4554                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4555                                             // Rule at src/isa/aarch64/lower.isle line 538.
4556                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4557                                             let expr1_0 =
4558                                                 constructor_vector_size(ctx, pattern11_0)?;
4559                                             let expr2_0: Type = I64;
4560                                             let expr3_0 = constructor_size_from_ty(ctx, expr2_0)?;
4561                                             let expr4_0 = constructor_mov_from_vec_signed(
4562                                                 ctx,
4563                                                 expr0_0,
4564                                                 pattern13_0,
4565                                                 &expr1_0,
4566                                                 &expr3_0,
4567                                             )?;
4568                                             let expr5_0: Type = I64;
4569                                             let expr6_0: u8 = 63;
4570                                             let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
4571                                             let expr8_0 = constructor_asr_imm(
4572                                                 ctx, expr5_0, expr4_0, expr7_0,
4573                                             )?;
4574                                             let expr9_0 = C::value_regs(ctx, expr4_0, expr8_0);
4575                                             let expr10_0 = C::output(ctx, expr9_0);
4576                                             return Some(expr10_0);
4577                                         }
4578                                     }
4579                                 }
4580                             }
4581                             // Rule at src/isa/aarch64/lower.isle line 528.
4582                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
4583                             let expr1_0: Type = I64;
4584                             let expr2_0: u8 = 63;
4585                             let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0);
4586                             let expr4_0 = constructor_asr_imm(ctx, expr1_0, expr0_0, expr3_0)?;
4587                             let expr5_0 = C::value_regs(ctx, expr0_0, expr4_0);
4588                             let expr6_0 = C::output(ctx, expr5_0);
4589                             return Some(expr6_0);
4590                         }
4591                         _ => {}
4592                     }
4593                 }
4594                 _ => {}
4595             }
4596         }
4597         if pattern2_0 == I8X16 {
4598             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4599             if let &InstructionData::Unary {
4600                 opcode: ref pattern5_0,
4601                 arg: pattern5_1,
4602             } = &pattern4_0
4603             {
4604                 if let &Opcode::Popcnt = pattern5_0 {
4605                     // Rule at src/isa/aarch64/lower.isle line 1131.
4606                     let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4607                     let expr1_0 = VectorSize::Size8x16;
4608                     let expr2_0 = constructor_vec_cnt(ctx, expr0_0, &expr1_0)?;
4609                     let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4610                     return Some(expr3_0);
4611                 }
4612             }
4613         }
4614         if pattern2_0 == I16X8 {
4615             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4616             if let &InstructionData::Binary {
4617                 opcode: ref pattern5_0,
4618                 args: ref pattern5_1,
4619             } = &pattern4_0
4620             {
4621                 if let &Opcode::Imul = pattern5_0 {
4622                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4623                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4624                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4625                         if let &InstructionData::Unary {
4626                             opcode: ref pattern10_0,
4627                             arg: pattern10_1,
4628                         } = &pattern9_0
4629                         {
4630                             match pattern10_0 {
4631                                 &Opcode::SwidenLow => {
4632                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4633                                     if pattern12_0 == I8X16 {
4634                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4635                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4636                                             if let &InstructionData::Unary {
4637                                                 opcode: ref pattern16_0,
4638                                                 arg: pattern16_1,
4639                                             } = &pattern15_0
4640                                             {
4641                                                 if let &Opcode::SwidenLow = pattern16_0 {
4642                                                     let pattern18_0 =
4643                                                         C::value_type(ctx, pattern16_1);
4644                                                     if pattern18_0 == I8X16 {
4645                                                         // Rule at src/isa/aarch64/lower.isle line 286.
4646                                                         let expr0_0 =
4647                                                             C::put_in_reg(ctx, pattern10_1);
4648                                                         let expr1_0 =
4649                                                             C::put_in_reg(ctx, pattern16_1);
4650                                                         let expr2_0: bool = false;
4651                                                         let expr3_0 = constructor_smull8(
4652                                                             ctx, expr0_0, expr1_0, expr2_0,
4653                                                         )?;
4654                                                         let expr4_0 =
4655                                                             constructor_output_reg(ctx, expr3_0)?;
4656                                                         return Some(expr4_0);
4657                                                     }
4658                                                 }
4659                                             }
4660                                         }
4661                                     }
4662                                 }
4663                                 &Opcode::SwidenHigh => {
4664                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4665                                     if pattern12_0 == I8X16 {
4666                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4667                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4668                                             if let &InstructionData::Unary {
4669                                                 opcode: ref pattern16_0,
4670                                                 arg: pattern16_1,
4671                                             } = &pattern15_0
4672                                             {
4673                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4674                                                     let pattern18_0 =
4675                                                         C::value_type(ctx, pattern16_1);
4676                                                     if pattern18_0 == I8X16 {
4677                                                         // Rule at src/isa/aarch64/lower.isle line 292.
4678                                                         let expr0_0 =
4679                                                             C::put_in_reg(ctx, pattern10_1);
4680                                                         let expr1_0 =
4681                                                             C::put_in_reg(ctx, pattern16_1);
4682                                                         let expr2_0: bool = true;
4683                                                         let expr3_0 = constructor_smull8(
4684                                                             ctx, expr0_0, expr1_0, expr2_0,
4685                                                         )?;
4686                                                         let expr4_0 =
4687                                                             constructor_output_reg(ctx, expr3_0)?;
4688                                                         return Some(expr4_0);
4689                                                     }
4690                                                 }
4691                                             }
4692                                         }
4693                                     }
4694                                 }
4695                                 &Opcode::UwidenLow => {
4696                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4697                                     if pattern12_0 == I8X16 {
4698                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4699                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4700                                             if let &InstructionData::Unary {
4701                                                 opcode: ref pattern16_0,
4702                                                 arg: pattern16_1,
4703                                             } = &pattern15_0
4704                                             {
4705                                                 if let &Opcode::UwidenLow = pattern16_0 {
4706                                                     let pattern18_0 =
4707                                                         C::value_type(ctx, pattern16_1);
4708                                                     if pattern18_0 == I8X16 {
4709                                                         // Rule at src/isa/aarch64/lower.isle line 298.
4710                                                         let expr0_0 =
4711                                                             C::put_in_reg(ctx, pattern10_1);
4712                                                         let expr1_0 =
4713                                                             C::put_in_reg(ctx, pattern16_1);
4714                                                         let expr2_0: bool = false;
4715                                                         let expr3_0 = constructor_umull8(
4716                                                             ctx, expr0_0, expr1_0, expr2_0,
4717                                                         )?;
4718                                                         let expr4_0 =
4719                                                             constructor_output_reg(ctx, expr3_0)?;
4720                                                         return Some(expr4_0);
4721                                                     }
4722                                                 }
4723                                             }
4724                                         }
4725                                     }
4726                                 }
4727                                 &Opcode::UwidenHigh => {
4728                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4729                                     if pattern12_0 == I8X16 {
4730                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4731                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4732                                             if let &InstructionData::Unary {
4733                                                 opcode: ref pattern16_0,
4734                                                 arg: pattern16_1,
4735                                             } = &pattern15_0
4736                                             {
4737                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4738                                                     let pattern18_0 =
4739                                                         C::value_type(ctx, pattern16_1);
4740                                                     if pattern18_0 == I8X16 {
4741                                                         // Rule at src/isa/aarch64/lower.isle line 304.
4742                                                         let expr0_0 =
4743                                                             C::put_in_reg(ctx, pattern10_1);
4744                                                         let expr1_0 =
4745                                                             C::put_in_reg(ctx, pattern16_1);
4746                                                         let expr2_0: bool = true;
4747                                                         let expr3_0 = constructor_umull8(
4748                                                             ctx, expr0_0, expr1_0, expr2_0,
4749                                                         )?;
4750                                                         let expr4_0 =
4751                                                             constructor_output_reg(ctx, expr3_0)?;
4752                                                         return Some(expr4_0);
4753                                                     }
4754                                                 }
4755                                             }
4756                                         }
4757                                     }
4758                                 }
4759                                 _ => {}
4760                             }
4761                         }
4762                     }
4763                 }
4764             }
4765         }
4766         if pattern2_0 == I32X4 {
4767             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4768             if let &InstructionData::Binary {
4769                 opcode: ref pattern5_0,
4770                 args: ref pattern5_1,
4771             } = &pattern4_0
4772             {
4773                 if let &Opcode::Imul = pattern5_0 {
4774                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4775                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4776                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4777                         if let &InstructionData::Unary {
4778                             opcode: ref pattern10_0,
4779                             arg: pattern10_1,
4780                         } = &pattern9_0
4781                         {
4782                             match pattern10_0 {
4783                                 &Opcode::SwidenLow => {
4784                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4785                                     if pattern12_0 == I16X8 {
4786                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4787                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4788                                             if let &InstructionData::Unary {
4789                                                 opcode: ref pattern16_0,
4790                                                 arg: pattern16_1,
4791                                             } = &pattern15_0
4792                                             {
4793                                                 if let &Opcode::SwidenLow = pattern16_0 {
4794                                                     let pattern18_0 =
4795                                                         C::value_type(ctx, pattern16_1);
4796                                                     if pattern18_0 == I16X8 {
4797                                                         // Rule at src/isa/aarch64/lower.isle line 310.
4798                                                         let expr0_0 =
4799                                                             C::put_in_reg(ctx, pattern10_1);
4800                                                         let expr1_0 =
4801                                                             C::put_in_reg(ctx, pattern16_1);
4802                                                         let expr2_0: bool = false;
4803                                                         let expr3_0 = constructor_smull16(
4804                                                             ctx, expr0_0, expr1_0, expr2_0,
4805                                                         )?;
4806                                                         let expr4_0 =
4807                                                             constructor_output_reg(ctx, expr3_0)?;
4808                                                         return Some(expr4_0);
4809                                                     }
4810                                                 }
4811                                             }
4812                                         }
4813                                     }
4814                                 }
4815                                 &Opcode::SwidenHigh => {
4816                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4817                                     if pattern12_0 == I16X8 {
4818                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4819                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4820                                             if let &InstructionData::Unary {
4821                                                 opcode: ref pattern16_0,
4822                                                 arg: pattern16_1,
4823                                             } = &pattern15_0
4824                                             {
4825                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4826                                                     let pattern18_0 =
4827                                                         C::value_type(ctx, pattern16_1);
4828                                                     if pattern18_0 == I16X8 {
4829                                                         // Rule at src/isa/aarch64/lower.isle line 316.
4830                                                         let expr0_0 =
4831                                                             C::put_in_reg(ctx, pattern10_1);
4832                                                         let expr1_0 =
4833                                                             C::put_in_reg(ctx, pattern16_1);
4834                                                         let expr2_0: bool = true;
4835                                                         let expr3_0 = constructor_smull16(
4836                                                             ctx, expr0_0, expr1_0, expr2_0,
4837                                                         )?;
4838                                                         let expr4_0 =
4839                                                             constructor_output_reg(ctx, expr3_0)?;
4840                                                         return Some(expr4_0);
4841                                                     }
4842                                                 }
4843                                             }
4844                                         }
4845                                     }
4846                                 }
4847                                 &Opcode::UwidenLow => {
4848                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4849                                     if pattern12_0 == I16X8 {
4850                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4851                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4852                                             if let &InstructionData::Unary {
4853                                                 opcode: ref pattern16_0,
4854                                                 arg: pattern16_1,
4855                                             } = &pattern15_0
4856                                             {
4857                                                 if let &Opcode::UwidenLow = pattern16_0 {
4858                                                     let pattern18_0 =
4859                                                         C::value_type(ctx, pattern16_1);
4860                                                     if pattern18_0 == I16X8 {
4861                                                         // Rule at src/isa/aarch64/lower.isle line 322.
4862                                                         let expr0_0 =
4863                                                             C::put_in_reg(ctx, pattern10_1);
4864                                                         let expr1_0 =
4865                                                             C::put_in_reg(ctx, pattern16_1);
4866                                                         let expr2_0: bool = false;
4867                                                         let expr3_0 = constructor_umull16(
4868                                                             ctx, expr0_0, expr1_0, expr2_0,
4869                                                         )?;
4870                                                         let expr4_0 =
4871                                                             constructor_output_reg(ctx, expr3_0)?;
4872                                                         return Some(expr4_0);
4873                                                     }
4874                                                 }
4875                                             }
4876                                         }
4877                                     }
4878                                 }
4879                                 &Opcode::UwidenHigh => {
4880                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4881                                     if pattern12_0 == I16X8 {
4882                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4883                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4884                                             if let &InstructionData::Unary {
4885                                                 opcode: ref pattern16_0,
4886                                                 arg: pattern16_1,
4887                                             } = &pattern15_0
4888                                             {
4889                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4890                                                     let pattern18_0 =
4891                                                         C::value_type(ctx, pattern16_1);
4892                                                     if pattern18_0 == I16X8 {
4893                                                         // Rule at src/isa/aarch64/lower.isle line 328.
4894                                                         let expr0_0 =
4895                                                             C::put_in_reg(ctx, pattern10_1);
4896                                                         let expr1_0 =
4897                                                             C::put_in_reg(ctx, pattern16_1);
4898                                                         let expr2_0: bool = true;
4899                                                         let expr3_0 = constructor_umull16(
4900                                                             ctx, expr0_0, expr1_0, expr2_0,
4901                                                         )?;
4902                                                         let expr4_0 =
4903                                                             constructor_output_reg(ctx, expr3_0)?;
4904                                                         return Some(expr4_0);
4905                                                     }
4906                                                 }
4907                                             }
4908                                         }
4909                                     }
4910                                 }
4911                                 _ => {}
4912                             }
4913                         }
4914                     }
4915                 }
4916             }
4917         }
4918         if pattern2_0 == I64X2 {
4919             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4920             if let &InstructionData::Binary {
4921                 opcode: ref pattern5_0,
4922                 args: ref pattern5_1,
4923             } = &pattern4_0
4924             {
4925                 if let &Opcode::Imul = pattern5_0 {
4926                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4927                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4928                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4929                         if let &InstructionData::Unary {
4930                             opcode: ref pattern10_0,
4931                             arg: pattern10_1,
4932                         } = &pattern9_0
4933                         {
4934                             match pattern10_0 {
4935                                 &Opcode::SwidenLow => {
4936                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4937                                     if pattern12_0 == I32X4 {
4938                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4939                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4940                                             if let &InstructionData::Unary {
4941                                                 opcode: ref pattern16_0,
4942                                                 arg: pattern16_1,
4943                                             } = &pattern15_0
4944                                             {
4945                                                 if let &Opcode::SwidenLow = pattern16_0 {
4946                                                     let pattern18_0 =
4947                                                         C::value_type(ctx, pattern16_1);
4948                                                     if pattern18_0 == I32X4 {
4949                                                         // Rule at src/isa/aarch64/lower.isle line 334.
4950                                                         let expr0_0 =
4951                                                             C::put_in_reg(ctx, pattern10_1);
4952                                                         let expr1_0 =
4953                                                             C::put_in_reg(ctx, pattern16_1);
4954                                                         let expr2_0: bool = false;
4955                                                         let expr3_0 = constructor_smull32(
4956                                                             ctx, expr0_0, expr1_0, expr2_0,
4957                                                         )?;
4958                                                         let expr4_0 =
4959                                                             constructor_output_reg(ctx, expr3_0)?;
4960                                                         return Some(expr4_0);
4961                                                     }
4962                                                 }
4963                                             }
4964                                         }
4965                                     }
4966                                 }
4967                                 &Opcode::SwidenHigh => {
4968                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4969                                     if pattern12_0 == I32X4 {
4970                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4971                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4972                                             if let &InstructionData::Unary {
4973                                                 opcode: ref pattern16_0,
4974                                                 arg: pattern16_1,
4975                                             } = &pattern15_0
4976                                             {
4977                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4978                                                     let pattern18_0 =
4979                                                         C::value_type(ctx, pattern16_1);
4980                                                     if pattern18_0 == I32X4 {
4981                                                         // Rule at src/isa/aarch64/lower.isle line 340.
4982                                                         let expr0_0 =
4983                                                             C::put_in_reg(ctx, pattern10_1);
4984                                                         let expr1_0 =
4985                                                             C::put_in_reg(ctx, pattern16_1);
4986                                                         let expr2_0: bool = true;
4987                                                         let expr3_0 = constructor_smull32(
4988                                                             ctx, expr0_0, expr1_0, expr2_0,
4989                                                         )?;
4990                                                         let expr4_0 =
4991                                                             constructor_output_reg(ctx, expr3_0)?;
4992                                                         return Some(expr4_0);
4993                                                     }
4994                                                 }
4995                                             }
4996                                         }
4997                                     }
4998                                 }
4999                                 &Opcode::UwidenLow => {
5000                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5001                                     if pattern12_0 == I32X4 {
5002                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5003                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5004                                             if let &InstructionData::Unary {
5005                                                 opcode: ref pattern16_0,
5006                                                 arg: pattern16_1,
5007                                             } = &pattern15_0
5008                                             {
5009                                                 if let &Opcode::UwidenLow = pattern16_0 {
5010                                                     let pattern18_0 =
5011                                                         C::value_type(ctx, pattern16_1);
5012                                                     if pattern18_0 == I32X4 {
5013                                                         // Rule at src/isa/aarch64/lower.isle line 346.
5014                                                         let expr0_0 =
5015                                                             C::put_in_reg(ctx, pattern10_1);
5016                                                         let expr1_0 =
5017                                                             C::put_in_reg(ctx, pattern16_1);
5018                                                         let expr2_0: bool = false;
5019                                                         let expr3_0 = constructor_umull32(
5020                                                             ctx, expr0_0, expr1_0, expr2_0,
5021                                                         )?;
5022                                                         let expr4_0 =
5023                                                             constructor_output_reg(ctx, expr3_0)?;
5024                                                         return Some(expr4_0);
5025                                                     }
5026                                                 }
5027                                             }
5028                                         }
5029                                     }
5030                                 }
5031                                 &Opcode::UwidenHigh => {
5032                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5033                                     if pattern12_0 == I32X4 {
5034                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5035                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5036                                             if let &InstructionData::Unary {
5037                                                 opcode: ref pattern16_0,
5038                                                 arg: pattern16_1,
5039                                             } = &pattern15_0
5040                                             {
5041                                                 if let &Opcode::UwidenHigh = pattern16_0 {
5042                                                     let pattern18_0 =
5043                                                         C::value_type(ctx, pattern16_1);
5044                                                     if pattern18_0 == I32X4 {
5045                                                         // Rule at src/isa/aarch64/lower.isle line 352.
5046                                                         let expr0_0 =
5047                                                             C::put_in_reg(ctx, pattern10_1);
5048                                                         let expr1_0 =
5049                                                             C::put_in_reg(ctx, pattern16_1);
5050                                                         let expr2_0: bool = true;
5051                                                         let expr3_0 = constructor_umull32(
5052                                                             ctx, expr0_0, expr1_0, expr2_0,
5053                                                         )?;
5054                                                         let expr4_0 =
5055                                                             constructor_output_reg(ctx, expr3_0)?;
5056                                                         return Some(expr4_0);
5057                                                     }
5058                                                 }
5059                                             }
5060                                         }
5061                                     }
5062                                 }
5063                                 _ => {}
5064                             }
5065                         }
5066                     }
5067                     // Rule at src/isa/aarch64/lower.isle line 247.
5068                     let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5069                     let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5070                     let expr2_0 = VectorSize::Size32x4;
5071                     let expr3_0 = constructor_rev64(ctx, expr1_0, &expr2_0)?;
5072                     let expr4_0 = VectorSize::Size32x4;
5073                     let expr5_0 = constructor_mul(ctx, expr3_0, expr0_0, &expr4_0)?;
5074                     let expr6_0: bool = false;
5075                     let expr7_0 = constructor_xtn64(ctx, expr0_0, expr6_0)?;
5076                     let expr8_0 = VectorSize::Size32x4;
5077                     let expr9_0 = constructor_addp(ctx, expr5_0, expr5_0, &expr8_0)?;
5078                     let expr10_0: bool = false;
5079                     let expr11_0 = constructor_xtn64(ctx, expr1_0, expr10_0)?;
5080                     let expr12_0: bool = false;
5081                     let expr13_0 = constructor_shll32(ctx, expr9_0, expr12_0)?;
5082                     let expr14_0: bool = false;
5083                     let expr15_0 = constructor_umlal32(ctx, expr13_0, expr11_0, expr7_0, expr14_0)?;
5084                     let expr16_0 = constructor_output_reg(ctx, expr15_0)?;
5085                     return Some(expr16_0);
5086                 }
5087             }
5088         }
5089         let pattern3_0 = C::inst_data(ctx, pattern0_0);
5090         match &pattern3_0 {
5091             &InstructionData::NullAry {
5092                 opcode: ref pattern4_0,
5093             } => {
5094                 if let &Opcode::Null = pattern4_0 {
5095                     // Rule at src/isa/aarch64/lower.isle line 22.
5096                     let expr0_0: u64 = 0;
5097                     let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5098                     let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5099                     return Some(expr2_0);
5100                 }
5101             }
5102             &InstructionData::UnaryImm {
5103                 opcode: ref pattern4_0,
5104                 imm: pattern4_1,
5105             } => {
5106                 if let &Opcode::Iconst = pattern4_0 {
5107                     let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1);
5108                     // Rule at src/isa/aarch64/lower.isle line 9.
5109                     let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?;
5110                     let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
5111                     return Some(expr1_0);
5112                 }
5113             }
5114             &InstructionData::UnaryBool {
5115                 opcode: ref pattern4_0,
5116                 imm: pattern4_1,
5117             } => {
5118                 if let &Opcode::Bconst = pattern4_0 {
5119                     if pattern4_1 == true {
5120                         // Rule at src/isa/aarch64/lower.isle line 17.
5121                         let expr0_0: u64 = 1;
5122                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5123                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5124                         return Some(expr2_0);
5125                     }
5126                     if pattern4_1 == false {
5127                         // Rule at src/isa/aarch64/lower.isle line 14.
5128                         let expr0_0: u64 = 0;
5129                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5130                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5131                         return Some(expr2_0);
5132                     }
5133                 }
5134             }
5135             &InstructionData::Unary {
5136                 opcode: ref pattern4_0,
5137                 arg: pattern4_1,
5138             } => {
5139                 match pattern4_0 {
5140                     &Opcode::Bitrev => {
5141                         // Rule at src/isa/aarch64/lower.isle line 995.
5142                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5143                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5144                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5145                         return Some(expr2_0);
5146                     }
5147                     &Opcode::Clz => {
5148                         // Rule at src/isa/aarch64/lower.isle line 1010.
5149                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5150                         let expr1_0 = constructor_a64_clz(ctx, pattern2_0, expr0_0)?;
5151                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5152                         return Some(expr2_0);
5153                     }
5154                     &Opcode::Cls => {
5155                         // Rule at src/isa/aarch64/lower.isle line 1077.
5156                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5157                         let expr1_0 = constructor_a64_cls(ctx, pattern2_0, expr0_0)?;
5158                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5159                         return Some(expr2_0);
5160                     }
5161                     &Opcode::Ctz => {
5162                         // Rule at src/isa/aarch64/lower.isle line 1043.
5163                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5164                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5165                         let expr2_0 = constructor_a64_clz(ctx, pattern2_0, expr1_0)?;
5166                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5167                         return Some(expr3_0);
5168                     }
5169                     _ => {}
5170                 }
5171             }
5172             _ => {}
5173         }
5174         if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) {
5175             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5176             match &pattern4_0 {
5177                 &InstructionData::Binary {
5178                     opcode: ref pattern5_0,
5179                     args: ref pattern5_1,
5180                 } => {
5181                     match pattern5_0 {
5182                         &Opcode::Iadd => {
5183                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5184                             // Rule at src/isa/aarch64/lower.isle line 79.
5185                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5186                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5187                             let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5188                             let expr3_0 = constructor_add_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5189                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5190                             return Some(expr4_0);
5191                         }
5192                         &Opcode::Isub => {
5193                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5194                             // Rule at src/isa/aarch64/lower.isle line 129.
5195                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5196                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5197                             let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5198                             let expr3_0 = constructor_sub_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5199                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5200                             return Some(expr4_0);
5201                         }
5202                         _ => {}
5203                     }
5204                 }
5205                 &InstructionData::FloatCompare {
5206                     opcode: ref pattern5_0,
5207                     args: ref pattern5_1,
5208                     cond: ref pattern5_2,
5209                 } => {
5210                     if let &Opcode::Fcmp = pattern5_0 {
5211                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5212                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5213                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5214                             if let &InstructionData::Unary {
5215                                 opcode: ref pattern10_0,
5216                                 arg: pattern10_1,
5217                             } = &pattern9_0
5218                             {
5219                                 if let &Opcode::Splat = pattern10_0 {
5220                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5221                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5222                                         match &pattern13_0 {
5223                                             &InstructionData::UnaryIeee32 {
5224                                                 opcode: ref pattern14_0,
5225                                                 imm: pattern14_1,
5226                                             } => {
5227                                                 if let &Opcode::F32const = pattern14_0 {
5228                                                     if let Some(pattern16_0) =
5229                                                         C::zero_value_f32(ctx, pattern14_1)
5230                                                     {
5231                                                         if let Some(pattern17_0) =
5232                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5233                                                         {
5234                                                             // Rule at src/isa/aarch64/lower.isle line 1151.
5235                                                             let expr0_0 =
5236                                                                 C::put_in_reg(ctx, pattern7_1);
5237                                                             let expr1_0 = constructor_vector_size(
5238                                                                 ctx, pattern2_0,
5239                                                             )?;
5240                                                             let expr2_0 =
5241                                                                 constructor_float_cmp_zero_swap(
5242                                                                     ctx,
5243                                                                     &pattern17_0,
5244                                                                     expr0_0,
5245                                                                     &expr1_0,
5246                                                                 )?;
5247                                                             let expr3_0 =
5248                                                                 C::value_reg(ctx, expr2_0);
5249                                                             let expr4_0 = C::output(ctx, expr3_0);
5250                                                             return Some(expr4_0);
5251                                                         }
5252                                                         if let Some(pattern17_0) =
5253                                                             C::fcmp_zero_cond_not_eq(
5254                                                                 ctx, pattern5_2,
5255                                                             )
5256                                                         {
5257                                                             // Rule at src/isa/aarch64/lower.isle line 1146.
5258                                                             let expr0_0 =
5259                                                                 C::put_in_reg(ctx, pattern7_1);
5260                                                             let expr1_0 = constructor_vector_size(
5261                                                                 ctx, pattern2_0,
5262                                                             )?;
5263                                                             let expr2_0 = constructor_fcmeq0(
5264                                                                 ctx, expr0_0, &expr1_0,
5265                                                             )?;
5266                                                             let expr3_0 = constructor_not(
5267                                                                 ctx, expr2_0, &expr1_0,
5268                                                             )?;
5269                                                             let expr4_0 =
5270                                                                 C::value_reg(ctx, expr3_0);
5271                                                             let expr5_0 = C::output(ctx, expr4_0);
5272                                                             return Some(expr5_0);
5273                                                         }
5274                                                     }
5275                                                 }
5276                                             }
5277                                             &InstructionData::UnaryIeee64 {
5278                                                 opcode: ref pattern14_0,
5279                                                 imm: pattern14_1,
5280                                             } => {
5281                                                 if let &Opcode::F64const = pattern14_0 {
5282                                                     if let Some(pattern16_0) =
5283                                                         C::zero_value_f64(ctx, pattern14_1)
5284                                                     {
5285                                                         if let Some(pattern17_0) =
5286                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5287                                                         {
5288                                                             // Rule at src/isa/aarch64/lower.isle line 1173.
5289                                                             let expr0_0 =
5290                                                                 C::put_in_reg(ctx, pattern7_1);
5291                                                             let expr1_0 = constructor_vector_size(
5292                                                                 ctx, pattern2_0,
5293                                                             )?;
5294                                                             let expr2_0 =
5295                                                                 constructor_float_cmp_zero_swap(
5296                                                                     ctx,
5297                                                                     &pattern17_0,
5298                                                                     expr0_0,
5299                                                                     &expr1_0,
5300                                                                 )?;
5301                                                             let expr3_0 =
5302                                                                 C::value_reg(ctx, expr2_0);
5303                                                             let expr4_0 = C::output(ctx, expr3_0);
5304                                                             return Some(expr4_0);
5305                                                         }
5306                                                         if let Some(pattern17_0) =
5307                                                             C::fcmp_zero_cond_not_eq(
5308                                                                 ctx, pattern5_2,
5309                                                             )
5310                                                         {
5311                                                             // Rule at src/isa/aarch64/lower.isle line 1168.
5312                                                             let expr0_0 =
5313                                                                 C::put_in_reg(ctx, pattern7_1);
5314                                                             let expr1_0 = constructor_vector_size(
5315                                                                 ctx, pattern2_0,
5316                                                             )?;
5317                                                             let expr2_0 = constructor_fcmeq0(
5318                                                                 ctx, expr0_0, &expr1_0,
5319                                                             )?;
5320                                                             let expr3_0 = constructor_not(
5321                                                                 ctx, expr2_0, &expr1_0,
5322                                                             )?;
5323                                                             let expr4_0 =
5324                                                                 C::value_reg(ctx, expr3_0);
5325                                                             let expr5_0 = C::output(ctx, expr4_0);
5326                                                             return Some(expr5_0);
5327                                                         }
5328                                                     }
5329                                                 }
5330                                             }
5331                                             _ => {}
5332                                         }
5333                                     }
5334                                 }
5335                             }
5336                         }
5337                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5338                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5339                             if let &InstructionData::Unary {
5340                                 opcode: ref pattern10_0,
5341                                 arg: pattern10_1,
5342                             } = &pattern9_0
5343                             {
5344                                 if let &Opcode::Splat = pattern10_0 {
5345                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5346                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5347                                         match &pattern13_0 {
5348                                             &InstructionData::UnaryIeee32 {
5349                                                 opcode: ref pattern14_0,
5350                                                 imm: pattern14_1,
5351                                             } => {
5352                                                 if let &Opcode::F32const = pattern14_0 {
5353                                                     if let Some(pattern16_0) =
5354                                                         C::zero_value_f32(ctx, pattern14_1)
5355                                                     {
5356                                                         if let Some(pattern17_0) =
5357                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5358                                                         {
5359                                                             // Rule at src/isa/aarch64/lower.isle line 1141.
5360                                                             let expr0_0 =
5361                                                                 C::put_in_reg(ctx, pattern7_0);
5362                                                             let expr1_0 = constructor_vector_size(
5363                                                                 ctx, pattern2_0,
5364                                                             )?;
5365                                                             let expr2_0 =
5366                                                                 constructor_float_cmp_zero(
5367                                                                     ctx,
5368                                                                     &pattern17_0,
5369                                                                     expr0_0,
5370                                                                     &expr1_0,
5371                                                                 )?;
5372                                                             let expr3_0 =
5373                                                                 C::value_reg(ctx, expr2_0);
5374                                                             let expr4_0 = C::output(ctx, expr3_0);
5375                                                             return Some(expr4_0);
5376                                                         }
5377                                                         if let Some(pattern17_0) =
5378                                                             C::fcmp_zero_cond_not_eq(
5379                                                                 ctx, pattern5_2,
5380                                                             )
5381                                                         {
5382                                                             // Rule at src/isa/aarch64/lower.isle line 1136.
5383                                                             let expr0_0 =
5384                                                                 C::put_in_reg(ctx, pattern7_0);
5385                                                             let expr1_0 = constructor_vector_size(
5386                                                                 ctx, pattern2_0,
5387                                                             )?;
5388                                                             let expr2_0 = constructor_fcmeq0(
5389                                                                 ctx, expr0_0, &expr1_0,
5390                                                             )?;
5391                                                             let expr3_0 = constructor_not(
5392                                                                 ctx, expr2_0, &expr1_0,
5393                                                             )?;
5394                                                             let expr4_0 =
5395                                                                 C::value_reg(ctx, expr3_0);
5396                                                             let expr5_0 = C::output(ctx, expr4_0);
5397                                                             return Some(expr5_0);
5398                                                         }
5399                                                     }
5400                                                 }
5401                                             }
5402                                             &InstructionData::UnaryIeee64 {
5403                                                 opcode: ref pattern14_0,
5404                                                 imm: pattern14_1,
5405                                             } => {
5406                                                 if let &Opcode::F64const = pattern14_0 {
5407                                                     if let Some(pattern16_0) =
5408                                                         C::zero_value_f64(ctx, pattern14_1)
5409                                                     {
5410                                                         if let Some(pattern17_0) =
5411                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5412                                                         {
5413                                                             // Rule at src/isa/aarch64/lower.isle line 1163.
5414                                                             let expr0_0 =
5415                                                                 C::put_in_reg(ctx, pattern7_0);
5416                                                             let expr1_0 = constructor_vector_size(
5417                                                                 ctx, pattern2_0,
5418                                                             )?;
5419                                                             let expr2_0 =
5420                                                                 constructor_float_cmp_zero(
5421                                                                     ctx,
5422                                                                     &pattern17_0,
5423                                                                     expr0_0,
5424                                                                     &expr1_0,
5425                                                                 )?;
5426                                                             let expr3_0 =
5427                                                                 C::value_reg(ctx, expr2_0);
5428                                                             let expr4_0 = C::output(ctx, expr3_0);
5429                                                             return Some(expr4_0);
5430                                                         }
5431                                                         if let Some(pattern17_0) =
5432                                                             C::fcmp_zero_cond_not_eq(
5433                                                                 ctx, pattern5_2,
5434                                                             )
5435                                                         {
5436                                                             // Rule at src/isa/aarch64/lower.isle line 1158.
5437                                                             let expr0_0 =
5438                                                                 C::put_in_reg(ctx, pattern7_0);
5439                                                             let expr1_0 = constructor_vector_size(
5440                                                                 ctx, pattern2_0,
5441                                                             )?;
5442                                                             let expr2_0 = constructor_fcmeq0(
5443                                                                 ctx, expr0_0, &expr1_0,
5444                                                             )?;
5445                                                             let expr3_0 = constructor_not(
5446                                                                 ctx, expr2_0, &expr1_0,
5447                                                             )?;
5448                                                             let expr4_0 =
5449                                                                 C::value_reg(ctx, expr3_0);
5450                                                             let expr5_0 = C::output(ctx, expr4_0);
5451                                                             return Some(expr5_0);
5452                                                         }
5453                                                     }
5454                                                 }
5455                                             }
5456                                             _ => {}
5457                                         }
5458                                     }
5459                                 }
5460                             }
5461                         }
5462                     }
5463                 }
5464                 &InstructionData::IntCompare {
5465                     opcode: ref pattern5_0,
5466                     args: ref pattern5_1,
5467                     cond: ref pattern5_2,
5468                 } => {
5469                     if let &Opcode::Icmp = pattern5_0 {
5470                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5471                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5472                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5473                             if let &InstructionData::Unary {
5474                                 opcode: ref pattern10_0,
5475                                 arg: pattern10_1,
5476                             } = &pattern9_0
5477                             {
5478                                 if let &Opcode::Splat = pattern10_0 {
5479                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5480                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5481                                         if let &InstructionData::UnaryImm {
5482                                             opcode: ref pattern14_0,
5483                                             imm: pattern14_1,
5484                                         } = &pattern13_0
5485                                         {
5486                                             if let &Opcode::Iconst = pattern14_0 {
5487                                                 if let Some(pattern16_0) =
5488                                                     C::zero_value(ctx, pattern14_1)
5489                                                 {
5490                                                     if let Some(pattern17_0) =
5491                                                         C::icmp_zero_cond(ctx, pattern5_2)
5492                                                     {
5493                                                         // Rule at src/isa/aarch64/lower.isle line 1195.
5494                                                         let expr0_0 =
5495                                                             C::put_in_reg(ctx, pattern7_1);
5496                                                         let expr1_0 = constructor_vector_size(
5497                                                             ctx, pattern2_0,
5498                                                         )?;
5499                                                         let expr2_0 =
5500                                                             constructor_int_cmp_zero_swap(
5501                                                                 ctx,
5502                                                                 &pattern17_0,
5503                                                                 expr0_0,
5504                                                                 &expr1_0,
5505                                                             )?;
5506                                                         let expr3_0 = C::value_reg(ctx, expr2_0);
5507                                                         let expr4_0 = C::output(ctx, expr3_0);
5508                                                         return Some(expr4_0);
5509                                                     }
5510                                                     if let Some(pattern17_0) =
5511                                                         C::icmp_zero_cond_not_eq(ctx, pattern5_2)
5512                                                     {
5513                                                         // Rule at src/isa/aarch64/lower.isle line 1190.
5514                                                         let expr0_0 =
5515                                                             C::put_in_reg(ctx, pattern7_1);
5516                                                         let expr1_0 = constructor_vector_size(
5517                                                             ctx, pattern2_0,
5518                                                         )?;
5519                                                         let expr2_0 = constructor_cmeq0(
5520                                                             ctx, expr0_0, &expr1_0,
5521                                                         )?;
5522                                                         let expr3_0 = constructor_not(
5523                                                             ctx, expr2_0, &expr1_0,
5524                                                         )?;
5525                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5526                                                         let expr5_0 = C::output(ctx, expr4_0);
5527                                                         return Some(expr5_0);
5528                                                     }
5529                                                 }
5530                                             }
5531                                         }
5532                                     }
5533                                 }
5534                             }
5535                         }
5536                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5537                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5538                             if let &InstructionData::Unary {
5539                                 opcode: ref pattern10_0,
5540                                 arg: pattern10_1,
5541                             } = &pattern9_0
5542                             {
5543                                 if let &Opcode::Splat = pattern10_0 {
5544                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5545                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5546                                         if let &InstructionData::UnaryImm {
5547                                             opcode: ref pattern14_0,
5548                                             imm: pattern14_1,
5549                                         } = &pattern13_0
5550                                         {
5551                                             if let &Opcode::Iconst = pattern14_0 {
5552                                                 if let Some(pattern16_0) =
5553                                                     C::zero_value(ctx, pattern14_1)
5554                                                 {
5555                                                     if let Some(pattern17_0) =
5556                                                         C::icmp_zero_cond(ctx, pattern5_2)
5557                                                     {
5558                                                         // Rule at src/isa/aarch64/lower.isle line 1185.
5559                                                         let expr0_0 =
5560                                                             C::put_in_reg(ctx, pattern7_0);
5561                                                         let expr1_0 = constructor_vector_size(
5562                                                             ctx, pattern2_0,
5563                                                         )?;
5564                                                         let expr2_0 = constructor_int_cmp_zero(
5565                                                             ctx,
5566                                                             &pattern17_0,
5567                                                             expr0_0,
5568                                                             &expr1_0,
5569                                                         )?;
5570                                                         let expr3_0 = C::value_reg(ctx, expr2_0);
5571                                                         let expr4_0 = C::output(ctx, expr3_0);
5572                                                         return Some(expr4_0);
5573                                                     }
5574                                                     if let Some(pattern17_0) =
5575                                                         C::icmp_zero_cond_not_eq(ctx, pattern5_2)
5576                                                     {
5577                                                         // Rule at src/isa/aarch64/lower.isle line 1180.
5578                                                         let expr0_0 =
5579                                                             C::put_in_reg(ctx, pattern7_0);
5580                                                         let expr1_0 = constructor_vector_size(
5581                                                             ctx, pattern2_0,
5582                                                         )?;
5583                                                         let expr2_0 = constructor_cmeq0(
5584                                                             ctx, expr0_0, &expr1_0,
5585                                                         )?;
5586                                                         let expr3_0 = constructor_not(
5587                                                             ctx, expr2_0, &expr1_0,
5588                                                         )?;
5589                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5590                                                         let expr5_0 = C::output(ctx, expr4_0);
5591                                                         return Some(expr5_0);
5592                                                     }
5593                                                 }
5594                                             }
5595                                         }
5596                                     }
5597                                 }
5598                             }
5599                         }
5600                     }
5601                 }
5602                 _ => {}
5603             }
5604         }
5605         if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
5606             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5607             if let &InstructionData::Binary {
5608                 opcode: ref pattern5_0,
5609                 args: ref pattern5_1,
5610             } = &pattern4_0
5611             {
5612                 match pattern5_0 {
5613                     &Opcode::Rotl => {
5614                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5615                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5616                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5617                             if let &InstructionData::UnaryImm {
5618                                 opcode: ref pattern10_0,
5619                                 imm: pattern10_1,
5620                             } = &pattern9_0
5621                             {
5622                                 if let &Opcode::Iconst = pattern10_0 {
5623                                     let closure12 = || {
5624                                         return Some(pattern3_0);
5625                                     };
5626                                     if let Some(pattern12_0) = closure12() {
5627                                         if let Some(pattern13_0) =
5628                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5629                                         {
5630                                             // Rule at src/isa/aarch64/lower.isle line 849.
5631                                             let expr0_0 =
5632                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5633                                             let expr1_0 =
5634                                                 C::negate_imm_shift(ctx, pattern3_0, pattern13_0);
5635                                             let expr2_0 = constructor_small_rotr_imm(
5636                                                 ctx, pattern3_0, expr0_0, expr1_0,
5637                                             )?;
5638                                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5639                                             return Some(expr3_0);
5640                                         }
5641                                     }
5642                                 }
5643                             }
5644                         }
5645                         // Rule at src/isa/aarch64/lower.isle line 844.
5646                         let expr0_0: Type = I32;
5647                         let expr1_0 = C::zero_reg(ctx);
5648                         let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5649                         let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
5650                         let expr4_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5651                         let expr5_0 = constructor_small_rotr(ctx, pattern3_0, expr4_0, expr3_0)?;
5652                         let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
5653                         return Some(expr6_0);
5654                     }
5655                     &Opcode::Rotr => {
5656                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5657                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5658                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5659                             if let &InstructionData::UnaryImm {
5660                                 opcode: ref pattern10_0,
5661                                 imm: pattern10_1,
5662                             } = &pattern9_0
5663                             {
5664                                 if let &Opcode::Iconst = pattern10_0 {
5665                                     let closure12 = || {
5666                                         return Some(pattern3_0);
5667                                     };
5668                                     if let Some(pattern12_0) = closure12() {
5669                                         if let Some(pattern13_0) =
5670                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5671                                         {
5672                                             // Rule at src/isa/aarch64/lower.isle line 909.
5673                                             let expr0_0 =
5674                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5675                                             let expr1_0 = constructor_small_rotr_imm(
5676                                                 ctx,
5677                                                 pattern3_0,
5678                                                 expr0_0,
5679                                                 pattern13_0,
5680                                             )?;
5681                                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5682                                             return Some(expr2_0);
5683                                         }
5684                                     }
5685                                 }
5686                             }
5687                         }
5688                         // Rule at src/isa/aarch64/lower.isle line 897.
5689                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5690                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5691                         let expr2_0 = constructor_small_rotr(ctx, pattern3_0, expr0_0, expr1_0)?;
5692                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5693                         return Some(expr3_0);
5694                     }
5695                     _ => {}
5696                 }
5697             }
5698         }
5699         if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
5700             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5701             if let &InstructionData::Binary {
5702                 opcode: ref pattern5_0,
5703                 args: ref pattern5_1,
5704             } = &pattern4_0
5705             {
5706                 match pattern5_0 {
5707                     &Opcode::Umulhi => {
5708                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5709                         // Rule at src/isa/aarch64/lower.isle line 374.
5710                         let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5711                         let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?;
5712                         let expr2_0: Type = I64;
5713                         let expr3_0 = C::zero_reg(ctx);
5714                         let expr4_0 = constructor_madd(ctx, expr2_0, expr0_0, expr1_0, expr3_0)?;
5715                         let expr5_0: Type = I64;
5716                         let expr6_0 = C::ty_bits(ctx, pattern3_0);
5717                         let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
5718                         let expr8_0 = constructor_lsr_imm(ctx, expr5_0, expr4_0, expr7_0)?;
5719                         let expr9_0 = C::value_reg(ctx, expr8_0);
5720                         let expr10_0 = C::output(ctx, expr9_0);
5721                         return Some(expr10_0);
5722                     }
5723                     &Opcode::Smulhi => {
5724                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5725                         // Rule at src/isa/aarch64/lower.isle line 362.
5726                         let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5727                         let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?;
5728                         let expr2_0: Type = I64;
5729                         let expr3_0 = C::zero_reg(ctx);
5730                         let expr4_0 = constructor_madd(ctx, expr2_0, expr0_0, expr1_0, expr3_0)?;
5731                         let expr5_0: Type = I64;
5732                         let expr6_0 = C::ty_bits(ctx, pattern3_0);
5733                         let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
5734                         let expr8_0 = constructor_asr_imm(ctx, expr5_0, expr4_0, expr7_0)?;
5735                         let expr9_0 = constructor_output_reg(ctx, expr8_0)?;
5736                         return Some(expr9_0);
5737                     }
5738                     &Opcode::Band => {
5739                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5740                         // Rule at src/isa/aarch64/lower.isle line 589.
5741                         let expr0_0 = ALUOp::And;
5742                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5743                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5744                         )?;
5745                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5746                         return Some(expr2_0);
5747                     }
5748                     &Opcode::Bor => {
5749                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5750                         // Rule at src/isa/aarch64/lower.isle line 602.
5751                         let expr0_0 = ALUOp::Orr;
5752                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5753                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5754                         )?;
5755                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5756                         return Some(expr2_0);
5757                     }
5758                     &Opcode::Bxor => {
5759                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5760                         // Rule at src/isa/aarch64/lower.isle line 615.
5761                         let expr0_0 = ALUOp::Eor;
5762                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5763                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5764                         )?;
5765                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5766                         return Some(expr2_0);
5767                     }
5768                     &Opcode::BandNot => {
5769                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5770                         // Rule at src/isa/aarch64/lower.isle line 628.
5771                         let expr0_0 = ALUOp::AndNot;
5772                         let expr1_0 = constructor_alu_rs_imm_logic(
5773                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5774                         )?;
5775                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5776                         return Some(expr2_0);
5777                     }
5778                     &Opcode::BorNot => {
5779                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5780                         // Rule at src/isa/aarch64/lower.isle line 641.
5781                         let expr0_0 = ALUOp::OrrNot;
5782                         let expr1_0 = constructor_alu_rs_imm_logic(
5783                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5784                         )?;
5785                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5786                         return Some(expr2_0);
5787                     }
5788                     &Opcode::BxorNot => {
5789                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5790                         // Rule at src/isa/aarch64/lower.isle line 651.
5791                         let expr0_0 = ALUOp::EorNot;
5792                         let expr1_0: Type = I32;
5793                         let expr2_0 = constructor_alu_rs_imm_logic(
5794                             ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
5795                         )?;
5796                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5797                         return Some(expr3_0);
5798                     }
5799                     &Opcode::Ishl => {
5800                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5801                         // Rule at src/isa/aarch64/lower.isle line 662.
5802                         let expr0_0 = ALUOp::Lsl;
5803                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
5804                         let expr2_0 =
5805                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5806                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5807                         return Some(expr3_0);
5808                     }
5809                     &Opcode::Ushr => {
5810                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5811                         // Rule at src/isa/aarch64/lower.isle line 746.
5812                         let expr0_0 = ALUOp::Lsr;
5813                         let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5814                         let expr2_0 =
5815                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5816                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5817                         return Some(expr3_0);
5818                     }
5819                     &Opcode::Sshr => {
5820                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5821                         // Rule at src/isa/aarch64/lower.isle line 793.
5822                         let expr0_0 = ALUOp::Asr;
5823                         let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
5824                         let expr2_0 =
5825                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5826                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5827                         return Some(expr3_0);
5828                     }
5829                     _ => {}
5830                 }
5831             }
5832         }
5833         if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
5834             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5835             match &pattern4_0 {
5836                 &InstructionData::Binary {
5837                     opcode: ref pattern5_0,
5838                     args: ref pattern5_1,
5839                 } => {
5840                     match pattern5_0 {
5841                         &Opcode::Iadd => {
5842                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5843                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5844                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5845                                 match &pattern9_0 {
5846                                     &InstructionData::UnaryImm {
5847                                         opcode: ref pattern10_0,
5848                                         imm: pattern10_1,
5849                                     } => {
5850                                         if let &Opcode::Iconst = pattern10_0 {
5851                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5852                                             if let Some(pattern13_0) =
5853                                                 C::imm12_from_u64(ctx, pattern12_0)
5854                                             {
5855                                                 // Rule at src/isa/aarch64/lower.isle line 37.
5856                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5857                                                 let expr1_0 = constructor_add_imm(
5858                                                     ctx,
5859                                                     pattern3_0,
5860                                                     expr0_0,
5861                                                     pattern13_0,
5862                                                 )?;
5863                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5864                                                 return Some(expr2_0);
5865                                             }
5866                                             if let Some(pattern13_0) =
5867                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5868                                             {
5869                                                 // Rule at src/isa/aarch64/lower.isle line 45.
5870                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5871                                                 let expr1_0 = constructor_sub_imm(
5872                                                     ctx,
5873                                                     pattern3_0,
5874                                                     expr0_0,
5875                                                     pattern13_0,
5876                                                 )?;
5877                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5878                                                 return Some(expr2_0);
5879                                             }
5880                                         }
5881                                     }
5882                                     &InstructionData::Binary {
5883                                         opcode: ref pattern10_0,
5884                                         args: ref pattern10_1,
5885                                     } => {
5886                                         match pattern10_0 {
5887                                             &Opcode::Imul => {
5888                                                 let (pattern12_0, pattern12_1) =
5889                                                     C::unpack_value_array_2(ctx, pattern10_1);
5890                                                 // Rule at src/isa/aarch64/lower.isle line 70.
5891                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5892                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5893                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5894                                                 let expr3_0 = constructor_madd(
5895                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5896                                                 )?;
5897                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5898                                                 return Some(expr4_0);
5899                                             }
5900                                             &Opcode::Ishl => {
5901                                                 let (pattern12_0, pattern12_1) =
5902                                                     C::unpack_value_array_2(ctx, pattern10_1);
5903                                                 if let Some(pattern13_0) =
5904                                                     C::def_inst(ctx, pattern12_1)
5905                                                 {
5906                                                     let pattern14_0 =
5907                                                         C::inst_data(ctx, pattern13_0);
5908                                                     if let &InstructionData::UnaryImm {
5909                                                         opcode: ref pattern15_0,
5910                                                         imm: pattern15_1,
5911                                                     } = &pattern14_0
5912                                                     {
5913                                                         if let &Opcode::Iconst = pattern15_0 {
5914                                                             let closure17 = || {
5915                                                                 return Some(pattern3_0);
5916                                                             };
5917                                                             if let Some(pattern17_0) = closure17() {
5918                                                                 if let Some(pattern18_0) =
5919                                                                     C::lshl_from_imm64(
5920                                                                         ctx,
5921                                                                         pattern15_1,
5922                                                                         pattern17_0,
5923                                                                     )
5924                                                                 {
5925                                                                     // Rule at src/isa/aarch64/lower.isle line 62.
5926                                                                     let expr0_0 = C::put_in_reg(
5927                                                                         ctx, pattern7_1,
5928                                                                     );
5929                                                                     let expr1_0 = C::put_in_reg(
5930                                                                         ctx,
5931                                                                         pattern12_0,
5932                                                                     );
5933                                                                     let expr2_0 =
5934                                                                         constructor_add_shift(
5935                                                                             ctx,
5936                                                                             pattern3_0,
5937                                                                             expr0_0,
5938                                                                             expr1_0,
5939                                                                             pattern18_0,
5940                                                                         )?;
5941                                                                     let expr3_0 =
5942                                                                         constructor_output_reg(
5943                                                                             ctx, expr2_0,
5944                                                                         )?;
5945                                                                     return Some(expr3_0);
5946                                                                 }
5947                                                             }
5948                                                         }
5949                                                     }
5950                                                 }
5951                                             }
5952                                             _ => {}
5953                                         }
5954                                     }
5955                                     _ => {}
5956                                 }
5957                             }
5958                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0)
5959                             {
5960                                 // Rule at src/isa/aarch64/lower.isle line 53.
5961                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5962                                 let expr1_0 =
5963                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5964                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5965                                 return Some(expr2_0);
5966                             }
5967                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5968                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5969                                 match &pattern9_0 {
5970                                     &InstructionData::UnaryImm {
5971                                         opcode: ref pattern10_0,
5972                                         imm: pattern10_1,
5973                                     } => {
5974                                         if let &Opcode::Iconst = pattern10_0 {
5975                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5976                                             if let Some(pattern13_0) =
5977                                                 C::imm12_from_u64(ctx, pattern12_0)
5978                                             {
5979                                                 // Rule at src/isa/aarch64/lower.isle line 34.
5980                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5981                                                 let expr1_0 = constructor_add_imm(
5982                                                     ctx,
5983                                                     pattern3_0,
5984                                                     expr0_0,
5985                                                     pattern13_0,
5986                                                 )?;
5987                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5988                                                 return Some(expr2_0);
5989                                             }
5990                                             if let Some(pattern13_0) =
5991                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5992                                             {
5993                                                 // Rule at src/isa/aarch64/lower.isle line 42.
5994                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5995                                                 let expr1_0 = constructor_sub_imm(
5996                                                     ctx,
5997                                                     pattern3_0,
5998                                                     expr0_0,
5999                                                     pattern13_0,
6000                                                 )?;
6001                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6002                                                 return Some(expr2_0);
6003                                             }
6004                                         }
6005                                     }
6006                                     &InstructionData::Binary {
6007                                         opcode: ref pattern10_0,
6008                                         args: ref pattern10_1,
6009                                     } => {
6010                                         match pattern10_0 {
6011                                             &Opcode::Imul => {
6012                                                 let (pattern12_0, pattern12_1) =
6013                                                     C::unpack_value_array_2(ctx, pattern10_1);
6014                                                 // Rule at src/isa/aarch64/lower.isle line 67.
6015                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
6016                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
6017                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
6018                                                 let expr3_0 = constructor_madd(
6019                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
6020                                                 )?;
6021                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6022                                                 return Some(expr4_0);
6023                                             }
6024                                             &Opcode::Ishl => {
6025                                                 let (pattern12_0, pattern12_1) =
6026                                                     C::unpack_value_array_2(ctx, pattern10_1);
6027                                                 if let Some(pattern13_0) =
6028                                                     C::def_inst(ctx, pattern12_1)
6029                                                 {
6030                                                     let pattern14_0 =
6031                                                         C::inst_data(ctx, pattern13_0);
6032                                                     if let &InstructionData::UnaryImm {
6033                                                         opcode: ref pattern15_0,
6034                                                         imm: pattern15_1,
6035                                                     } = &pattern14_0
6036                                                     {
6037                                                         if let &Opcode::Iconst = pattern15_0 {
6038                                                             let closure17 = || {
6039                                                                 return Some(pattern3_0);
6040                                                             };
6041                                                             if let Some(pattern17_0) = closure17() {
6042                                                                 if let Some(pattern18_0) =
6043                                                                     C::lshl_from_imm64(
6044                                                                         ctx,
6045                                                                         pattern15_1,
6046                                                                         pattern17_0,
6047                                                                     )
6048                                                                 {
6049                                                                     // Rule at src/isa/aarch64/lower.isle line 58.
6050                                                                     let expr0_0 = C::put_in_reg(
6051                                                                         ctx, pattern7_0,
6052                                                                     );
6053                                                                     let expr1_0 = C::put_in_reg(
6054                                                                         ctx,
6055                                                                         pattern12_0,
6056                                                                     );
6057                                                                     let expr2_0 =
6058                                                                         constructor_add_shift(
6059                                                                             ctx,
6060                                                                             pattern3_0,
6061                                                                             expr0_0,
6062                                                                             expr1_0,
6063                                                                             pattern18_0,
6064                                                                         )?;
6065                                                                     let expr3_0 =
6066                                                                         constructor_output_reg(
6067                                                                             ctx, expr2_0,
6068                                                                         )?;
6069                                                                     return Some(expr3_0);
6070                                                                 }
6071                                                             }
6072                                                         }
6073                                                     }
6074                                                 }
6075                                             }
6076                                             _ => {}
6077                                         }
6078                                     }
6079                                     _ => {}
6080                                 }
6081                             }
6082                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
6083                             {
6084                                 // Rule at src/isa/aarch64/lower.isle line 50.
6085                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6086                                 let expr1_0 =
6087                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6088                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6089                                 return Some(expr2_0);
6090                             }
6091                             // Rule at src/isa/aarch64/lower.isle line 30.
6092                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6093                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6094                             let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, expr1_0)?;
6095                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6096                             return Some(expr3_0);
6097                         }
6098                         &Opcode::Isub => {
6099                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6100                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6101                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6102                                 match &pattern9_0 {
6103                                     &InstructionData::UnaryImm {
6104                                         opcode: ref pattern10_0,
6105                                         imm: pattern10_1,
6106                                     } => {
6107                                         if let &Opcode::Iconst = pattern10_0 {
6108                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
6109                                             if let Some(pattern13_0) =
6110                                                 C::imm12_from_u64(ctx, pattern12_0)
6111                                             {
6112                                                 // Rule at src/isa/aarch64/lower.isle line 109.
6113                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6114                                                 let expr1_0 = constructor_sub_imm(
6115                                                     ctx,
6116                                                     pattern3_0,
6117                                                     expr0_0,
6118                                                     pattern13_0,
6119                                                 )?;
6120                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6121                                                 return Some(expr2_0);
6122                                             }
6123                                             if let Some(pattern13_0) =
6124                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
6125                                             {
6126                                                 // Rule at src/isa/aarch64/lower.isle line 114.
6127                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6128                                                 let expr1_0 = constructor_add_imm(
6129                                                     ctx,
6130                                                     pattern3_0,
6131                                                     expr0_0,
6132                                                     pattern13_0,
6133                                                 )?;
6134                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6135                                                 return Some(expr2_0);
6136                                             }
6137                                         }
6138                                     }
6139                                     &InstructionData::Binary {
6140                                         opcode: ref pattern10_0,
6141                                         args: ref pattern10_1,
6142                                     } => {
6143                                         match pattern10_0 {
6144                                             &Opcode::Imul => {
6145                                                 let (pattern12_0, pattern12_1) =
6146                                                     C::unpack_value_array_2(ctx, pattern10_1);
6147                                                 // Rule at src/isa/aarch64/lower.isle line 74.
6148                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
6149                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
6150                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
6151                                                 let expr3_0 = constructor_msub(
6152                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
6153                                                 )?;
6154                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6155                                                 return Some(expr4_0);
6156                                             }
6157                                             &Opcode::Ishl => {
6158                                                 let (pattern12_0, pattern12_1) =
6159                                                     C::unpack_value_array_2(ctx, pattern10_1);
6160                                                 if let Some(pattern13_0) =
6161                                                     C::def_inst(ctx, pattern12_1)
6162                                                 {
6163                                                     let pattern14_0 =
6164                                                         C::inst_data(ctx, pattern13_0);
6165                                                     if let &InstructionData::UnaryImm {
6166                                                         opcode: ref pattern15_0,
6167                                                         imm: pattern15_1,
6168                                                     } = &pattern14_0
6169                                                     {
6170                                                         if let &Opcode::Iconst = pattern15_0 {
6171                                                             let closure17 = || {
6172                                                                 return Some(pattern3_0);
6173                                                             };
6174                                                             if let Some(pattern17_0) = closure17() {
6175                                                                 if let Some(pattern18_0) =
6176                                                                     C::lshl_from_imm64(
6177                                                                         ctx,
6178                                                                         pattern15_1,
6179                                                                         pattern17_0,
6180                                                                     )
6181                                                                 {
6182                                                                     // Rule at src/isa/aarch64/lower.isle line 124.
6183                                                                     let expr0_0 = C::put_in_reg(
6184                                                                         ctx, pattern7_0,
6185                                                                     );
6186                                                                     let expr1_0 = C::put_in_reg(
6187                                                                         ctx,
6188                                                                         pattern12_0,
6189                                                                     );
6190                                                                     let expr2_0 =
6191                                                                         constructor_sub_shift(
6192                                                                             ctx,
6193                                                                             pattern3_0,
6194                                                                             expr0_0,
6195                                                                             expr1_0,
6196                                                                             pattern18_0,
6197                                                                         )?;
6198                                                                     let expr3_0 =
6199                                                                         constructor_output_reg(
6200                                                                             ctx, expr2_0,
6201                                                                         )?;
6202                                                                     return Some(expr3_0);
6203                                                                 }
6204                                                             }
6205                                                         }
6206                                                     }
6207                                                 }
6208                                             }
6209                                             _ => {}
6210                                         }
6211                                     }
6212                                     _ => {}
6213                                 }
6214                             }
6215                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
6216                             {
6217                                 // Rule at src/isa/aarch64/lower.isle line 119.
6218                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6219                                 let expr1_0 =
6220                                     constructor_sub_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6221                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6222                                 return Some(expr2_0);
6223                             }
6224                             // Rule at src/isa/aarch64/lower.isle line 105.
6225                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6226                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6227                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
6228                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6229                             return Some(expr3_0);
6230                         }
6231                         &Opcode::Imul => {
6232                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6233                             // Rule at src/isa/aarch64/lower.isle line 183.
6234                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6235                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6236                             let expr2_0 = C::zero_reg(ctx);
6237                             let expr3_0 =
6238                                 constructor_madd(ctx, pattern3_0, expr0_0, expr1_0, expr2_0)?;
6239                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6240                             return Some(expr4_0);
6241                         }
6242                         &Opcode::Udiv => {
6243                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6244                             // Rule at src/isa/aarch64/lower.isle line 390.
6245                             let expr0_0: Type = I64;
6246                             let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
6247                             let expr2_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
6248                             let expr3_0 = constructor_a64_udiv(ctx, expr0_0, expr1_0, expr2_0)?;
6249                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6250                             return Some(expr4_0);
6251                         }
6252                         &Opcode::Sdiv => {
6253                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6254                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6255                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6256                                 if let &InstructionData::UnaryImm {
6257                                     opcode: ref pattern10_0,
6258                                     imm: pattern10_1,
6259                                 } = &pattern9_0
6260                                 {
6261                                     if let &Opcode::Iconst = pattern10_0 {
6262                                         if let Some(pattern12_0) =
6263                                             C::safe_divisor_from_imm64(ctx, pattern10_1)
6264                                         {
6265                                             // Rule at src/isa/aarch64/lower.isle line 436.
6266                                             let expr0_0: Type = I64;
6267                                             let expr1_0 =
6268                                                 constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6269                                             let expr2_0 =
6270                                                 constructor_imm(ctx, pattern3_0, pattern12_0)?;
6271                                             let expr3_0 = constructor_a64_sdiv(
6272                                                 ctx, expr0_0, expr1_0, expr2_0,
6273                                             )?;
6274                                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6275                                             return Some(expr4_0);
6276                                         }
6277                                     }
6278                                 }
6279                             }
6280                             // Rule at src/isa/aarch64/lower.isle line 423.
6281                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6282                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
6283                             let expr2_0 = constructor_trap_if_div_overflow(
6284                                 ctx, pattern3_0, expr0_0, expr1_0,
6285                             )?;
6286                             let expr3_0: Type = I64;
6287                             let expr4_0 = constructor_a64_sdiv(ctx, expr3_0, expr2_0, expr1_0)?;
6288                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6289                             return Some(expr5_0);
6290                         }
6291                         &Opcode::Urem => {
6292                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6293                             // Rule at src/isa/aarch64/lower.isle line 464.
6294                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
6295                             let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
6296                             let expr2_0: Type = I64;
6297                             let expr3_0 = constructor_a64_udiv(ctx, expr2_0, expr0_0, expr1_0)?;
6298                             let expr4_0: Type = I64;
6299                             let expr5_0 =
6300                                 constructor_msub(ctx, expr4_0, expr3_0, expr1_0, expr0_0)?;
6301                             let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
6302                             return Some(expr6_0);
6303                         }
6304                         &Opcode::Srem => {
6305                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6306                             // Rule at src/isa/aarch64/lower.isle line 471.
6307                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6308                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
6309                             let expr2_0: Type = I64;
6310                             let expr3_0 = constructor_a64_sdiv(ctx, expr2_0, expr0_0, expr1_0)?;
6311                             let expr4_0: Type = I64;
6312                             let expr5_0 =
6313                                 constructor_msub(ctx, expr4_0, expr3_0, expr1_0, expr0_0)?;
6314                             let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
6315                             return Some(expr6_0);
6316                         }
6317                         _ => {}
6318                     }
6319                 }
6320                 &InstructionData::Unary {
6321                     opcode: ref pattern5_0,
6322                     arg: pattern5_1,
6323                 } => {
6324                     match pattern5_0 {
6325                         &Opcode::Ineg => {
6326                             // Rule at src/isa/aarch64/lower.isle line 173.
6327                             let expr0_0 = C::zero_reg(ctx);
6328                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6329                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
6330                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6331                             return Some(expr3_0);
6332                         }
6333                         &Opcode::Bnot => {
6334                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6335                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6336                                 if let &InstructionData::Binary {
6337                                     opcode: ref pattern9_0,
6338                                     args: ref pattern9_1,
6339                                 } = &pattern8_0
6340                                 {
6341                                     if let &Opcode::Ishl = pattern9_0 {
6342                                         let (pattern11_0, pattern11_1) =
6343                                             C::unpack_value_array_2(ctx, pattern9_1);
6344                                         if let Some(pattern12_0) = C::def_inst(ctx, pattern11_1) {
6345                                             let pattern13_0 = C::inst_data(ctx, pattern12_0);
6346                                             if let &InstructionData::UnaryImm {
6347                                                 opcode: ref pattern14_0,
6348                                                 imm: pattern14_1,
6349                                             } = &pattern13_0
6350                                             {
6351                                                 if let &Opcode::Iconst = pattern14_0 {
6352                                                     let closure16 = || {
6353                                                         return Some(pattern3_0);
6354                                                     };
6355                                                     if let Some(pattern16_0) = closure16() {
6356                                                         if let Some(pattern17_0) =
6357                                                             C::lshl_from_imm64(
6358                                                                 ctx,
6359                                                                 pattern14_1,
6360                                                                 pattern16_0,
6361                                                             )
6362                                                         {
6363                                                             // Rule at src/isa/aarch64/lower.isle line 570.
6364                                                             let expr0_0 = C::zero_reg(ctx);
6365                                                             let expr1_0 =
6366                                                                 C::put_in_reg(ctx, pattern11_0);
6367                                                             let expr2_0 =
6368                                                                 constructor_orr_not_shift(
6369                                                                     ctx,
6370                                                                     pattern3_0,
6371                                                                     expr0_0,
6372                                                                     expr1_0,
6373                                                                     pattern17_0,
6374                                                                 )?;
6375                                                             let expr3_0 = constructor_output_reg(
6376                                                                 ctx, expr2_0,
6377                                                             )?;
6378                                                             return Some(expr3_0);
6379                                                         }
6380                                                     }
6381                                                 }
6382                                             }
6383                                         }
6384                                     }
6385                                 }
6386                             }
6387                             // Rule at src/isa/aarch64/lower.isle line 565.
6388                             let expr0_0 = C::zero_reg(ctx);
6389                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6390                             let expr2_0 = constructor_orr_not(ctx, pattern3_0, expr0_0, expr1_0)?;
6391                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6392                             return Some(expr3_0);
6393                         }
6394                         &Opcode::Uextend => {
6395                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6396                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6397                                 if let &InstructionData::BinaryImm8 {
6398                                     opcode: ref pattern9_0,
6399                                     arg: pattern9_1,
6400                                     imm: pattern9_2,
6401                                 } = &pattern8_0
6402                                 {
6403                                     if let &Opcode::Extractlane = pattern9_0 {
6404                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6405                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6406                                         // Rule at src/isa/aarch64/lower.isle line 487.
6407                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6408                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6409                                         let expr2_0 = constructor_mov_from_vec(
6410                                             ctx,
6411                                             expr0_0,
6412                                             pattern12_0,
6413                                             &expr1_0,
6414                                         )?;
6415                                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6416                                         return Some(expr3_0);
6417                                     }
6418                                 }
6419                             }
6420                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6421                             if let Some(pattern8_0) = C::sinkable_atomic_load(ctx, pattern5_1) {
6422                                 // Rule at src/isa/aarch64/lower.isle line 494.
6423                                 let expr0_0 = C::sink_atomic_load(ctx, &pattern8_0);
6424                                 let expr1_0 = constructor_load_acquire(ctx, pattern7_0, expr0_0)?;
6425                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6426                                 return Some(expr2_0);
6427                             }
6428                             // Rule at src/isa/aarch64/lower.isle line 482.
6429                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6430                             let expr1_0: bool = false;
6431                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6432                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6433                             let expr4_0 =
6434                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6435                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6436                             return Some(expr5_0);
6437                         }
6438                         &Opcode::Sextend => {
6439                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6440                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6441                                 if let &InstructionData::BinaryImm8 {
6442                                     opcode: ref pattern9_0,
6443                                     arg: pattern9_1,
6444                                     imm: pattern9_2,
6445                                 } = &pattern8_0
6446                                 {
6447                                     if let &Opcode::Extractlane = pattern9_0 {
6448                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6449                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6450                                         // Rule at src/isa/aarch64/lower.isle line 519.
6451                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6452                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6453                                         let expr2_0 = constructor_size_from_ty(ctx, pattern3_0)?;
6454                                         let expr3_0 = constructor_mov_from_vec_signed(
6455                                             ctx,
6456                                             expr0_0,
6457                                             pattern12_0,
6458                                             &expr1_0,
6459                                             &expr2_0,
6460                                         )?;
6461                                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6462                                         return Some(expr4_0);
6463                                     }
6464                                 }
6465                             }
6466                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6467                             // Rule at src/isa/aarch64/lower.isle line 514.
6468                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6469                             let expr1_0: bool = true;
6470                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6471                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6472                             let expr4_0 =
6473                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6474                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6475                             return Some(expr5_0);
6476                         }
6477                         _ => {}
6478                     }
6479                 }
6480                 _ => {}
6481             }
6482         }
6483         if let Some(pattern3_0) = C::ty_vec128(ctx, pattern2_0) {
6484             let pattern4_0 = C::inst_data(ctx, pattern0_0);
6485             match &pattern4_0 {
6486                 &InstructionData::Binary {
6487                     opcode: ref pattern5_0,
6488                     args: ref pattern5_1,
6489                 } => {
6490                     match pattern5_0 {
6491                         &Opcode::UaddSat => {
6492                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6493                             // Rule at src/isa/aarch64/lower.isle line 152.
6494                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6495                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6496                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6497                             let expr3_0 = constructor_uqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6498                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6499                             return Some(expr4_0);
6500                         }
6501                         &Opcode::SaddSat => {
6502                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6503                             // Rule at src/isa/aarch64/lower.isle line 157.
6504                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6505                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6506                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6507                             let expr3_0 = constructor_sqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6508                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6509                             return Some(expr4_0);
6510                         }
6511                         &Opcode::UsubSat => {
6512                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6513                             // Rule at src/isa/aarch64/lower.isle line 162.
6514                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6515                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6516                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6517                             let expr3_0 = constructor_uqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6518                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6519                             return Some(expr4_0);
6520                         }
6521                         &Opcode::SsubSat => {
6522                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6523                             // Rule at src/isa/aarch64/lower.isle line 167.
6524                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6525                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6526                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6527                             let expr3_0 = constructor_sqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6528                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6529                             return Some(expr4_0);
6530                         }
6531                         &Opcode::Band => {
6532                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6533                             // Rule at src/isa/aarch64/lower.isle line 597.
6534                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6535                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6536                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6537                             let expr3_0 = constructor_and_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6538                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6539                             return Some(expr4_0);
6540                         }
6541                         &Opcode::Bor => {
6542                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6543                             // Rule at src/isa/aarch64/lower.isle line 610.
6544                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6545                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6546                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6547                             let expr3_0 = constructor_orr_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6548                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6549                             return Some(expr4_0);
6550                         }
6551                         &Opcode::Bxor => {
6552                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6553                             // Rule at src/isa/aarch64/lower.isle line 623.
6554                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6555                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6556                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6557                             let expr3_0 = constructor_eor_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6558                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6559                             return Some(expr4_0);
6560                         }
6561                         &Opcode::BandNot => {
6562                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6563                             // Rule at src/isa/aarch64/lower.isle line 636.
6564                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6565                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6566                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6567                             let expr3_0 = constructor_bic_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6568                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6569                             return Some(expr4_0);
6570                         }
6571                         &Opcode::Ishl => {
6572                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6573                             // Rule at src/isa/aarch64/lower.isle line 700.
6574                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6575                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6576                             let expr2_0 = constructor_vec_dup(ctx, expr1_0, &expr0_0)?;
6577                             let expr3_0 = C::put_in_reg(ctx, pattern7_0);
6578                             let expr4_0 = constructor_sshl(ctx, expr3_0, expr2_0, &expr0_0)?;
6579                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6580                             return Some(expr5_0);
6581                         }
6582                         &Opcode::Ushr => {
6583                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6584                             // Rule at src/isa/aarch64/lower.isle line 758.
6585                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6586                             let expr1_0: Type = I32;
6587                             let expr2_0 = C::zero_reg(ctx);
6588                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6589                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6590                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6591                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6592                             let expr7_0 = constructor_ushl(ctx, expr6_0, expr5_0, &expr0_0)?;
6593                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6594                             return Some(expr8_0);
6595                         }
6596                         &Opcode::Sshr => {
6597                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6598                             // Rule at src/isa/aarch64/lower.isle line 807.
6599                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6600                             let expr1_0: Type = I32;
6601                             let expr2_0 = C::zero_reg(ctx);
6602                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6603                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6604                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6605                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6606                             let expr7_0 = constructor_sshl(ctx, expr6_0, expr5_0, &expr0_0)?;
6607                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6608                             return Some(expr8_0);
6609                         }
6610                         _ => {}
6611                     }
6612                 }
6613                 &InstructionData::Unary {
6614                     opcode: ref pattern5_0,
6615                     arg: pattern5_1,
6616                 } => {
6617                     match pattern5_0 {
6618                         &Opcode::Ineg => {
6619                             // Rule at src/isa/aarch64/lower.isle line 177.
6620                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6621                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6622                             let expr2_0 = constructor_neg(ctx, expr0_0, &expr1_0)?;
6623                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6624                             return Some(expr3_0);
6625                         }
6626                         &Opcode::Bnot => {
6627                             // Rule at src/isa/aarch64/lower.isle line 584.
6628                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6629                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6630                             let expr2_0 = constructor_not(ctx, expr0_0, &expr1_0)?;
6631                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6632                             return Some(expr3_0);
6633                         }
6634                         _ => {}
6635                     }
6636                 }
6637                 _ => {}
6638             }
6639             if let Some(()) = C::not_i64x2(ctx, pattern3_0) {
6640                 let pattern5_0 = C::inst_data(ctx, pattern0_0);
6641                 if let &InstructionData::Binary {
6642                     opcode: ref pattern6_0,
6643                     args: ref pattern6_1,
6644                 } = &pattern5_0
6645                 {
6646                     if let &Opcode::Imul = pattern6_0 {
6647                         let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
6648                         // Rule at src/isa/aarch64/lower.isle line 215.
6649                         let expr0_0 = C::put_in_reg(ctx, pattern8_0);
6650                         let expr1_0 = C::put_in_reg(ctx, pattern8_1);
6651                         let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6652                         let expr3_0 = constructor_mul(ctx, expr0_0, expr1_0, &expr2_0)?;
6653                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6654                         return Some(expr4_0);
6655                     }
6656                 }
6657             }
6658         }
6659     }
6660     return None;
6661 }
6662 
6663 // Generated as internal constructor for term put_nonzero_in_reg_zext64.
6664 pub fn constructor_put_nonzero_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6665     let pattern0_0 = arg0;
6666     let pattern1_0 = C::value_type(ctx, pattern0_0);
6667     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6668         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6669         if let &InstructionData::UnaryImm {
6670             opcode: ref pattern4_0,
6671             imm: pattern4_1,
6672         } = &pattern3_0
6673         {
6674             if let &Opcode::Iconst = pattern4_0 {
6675                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6676                     // Rule at src/isa/aarch64/lower.isle line 400.
6677                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6678                     return Some(expr0_0);
6679                 }
6680             }
6681         }
6682     }
6683     // Rule at src/isa/aarch64/lower.isle line 395.
6684     let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern0_0)?;
6685     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6686     return Some(expr1_0);
6687 }
6688 
6689 // Generated as internal constructor for term put_nonzero_in_reg_sext64.
6690 pub fn constructor_put_nonzero_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6691     let pattern0_0 = arg0;
6692     let pattern1_0 = C::value_type(ctx, pattern0_0);
6693     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6694         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6695         if let &InstructionData::UnaryImm {
6696             opcode: ref pattern4_0,
6697             imm: pattern4_1,
6698         } = &pattern3_0
6699         {
6700             if let &Opcode::Iconst = pattern4_0 {
6701                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6702                     // Rule at src/isa/aarch64/lower.isle line 446.
6703                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6704                     return Some(expr0_0);
6705                 }
6706             }
6707         }
6708     }
6709     // Rule at src/isa/aarch64/lower.isle line 441.
6710     let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern0_0)?;
6711     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6712     return Some(expr1_0);
6713 }
6714 
6715 // Generated as internal constructor for term lower_shl128.
6716 pub fn constructor_lower_shl128<C: Context>(
6717     ctx: &mut C,
6718     arg0: ValueRegs,
6719     arg1: Reg,
6720 ) -> Option<ValueRegs> {
6721     let pattern0_0 = arg0;
6722     let pattern1_0 = arg1;
6723     // Rule at src/isa/aarch64/lower.isle line 683.
6724     let expr0_0: usize = 0;
6725     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6726     let expr2_0: usize = 1;
6727     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6728     let expr4_0: Type = I64;
6729     let expr5_0 = constructor_lsl(ctx, expr4_0, expr1_0, pattern1_0)?;
6730     let expr6_0: Type = I64;
6731     let expr7_0 = constructor_lsl(ctx, expr6_0, expr3_0, pattern1_0)?;
6732     let expr8_0: Type = I32;
6733     let expr9_0 = C::zero_reg(ctx);
6734     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6735     let expr11_0: Type = I64;
6736     let expr12_0: Type = I64;
6737     let expr13_0: u8 = 1;
6738     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6739     let expr15_0 = constructor_lsr_imm(ctx, expr12_0, expr1_0, expr14_0)?;
6740     let expr16_0 = constructor_lsr(ctx, expr11_0, expr15_0, expr10_0)?;
6741     let expr17_0: Type = I64;
6742     let expr18_0 = constructor_orr(ctx, expr17_0, expr7_0, expr16_0)?;
6743     let expr19_0: Type = I64;
6744     let expr20_0: Type = I64;
6745     let expr21_0: u64 = 64;
6746     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6747     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6748     let expr24_0 = Cond::Ne;
6749     let expr25_0 = C::zero_reg(ctx);
6750     let expr26_0 = constructor_csel(ctx, &expr24_0, expr25_0, expr5_0)?;
6751     let expr27_0 = Cond::Ne;
6752     let expr28_0 = constructor_csel(ctx, &expr27_0, expr5_0, expr18_0)?;
6753     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr26_0, &expr28_0)?;
6754     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6755     return Some(expr30_0);
6756 }
6757 
6758 // Generated as internal constructor for term do_shift.
6759 pub fn constructor_do_shift<C: Context>(
6760     ctx: &mut C,
6761     arg0: &ALUOp,
6762     arg1: Type,
6763     arg2: Reg,
6764     arg3: Value,
6765 ) -> Option<Reg> {
6766     let pattern0_0 = arg0;
6767     let pattern1_0 = arg1;
6768     let pattern2_0 = arg2;
6769     let pattern3_0 = arg3;
6770     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
6771         let pattern5_0 = C::inst_data(ctx, pattern4_0);
6772         if let &InstructionData::UnaryImm {
6773             opcode: ref pattern6_0,
6774             imm: pattern6_1,
6775         } = &pattern5_0
6776         {
6777             if let &Opcode::Iconst = pattern6_0 {
6778                 let closure8 = || {
6779                     return Some(pattern1_0);
6780                 };
6781                 if let Some(pattern8_0) = closure8() {
6782                     if let Some(pattern9_0) = C::imm_shift_from_imm64(ctx, pattern6_1, pattern8_0) {
6783                         // Rule at src/isa/aarch64/lower.isle line 740.
6784                         let expr0_0 = constructor_alu_rr_imm_shift(
6785                             ctx, pattern0_0, pattern1_0, pattern2_0, pattern9_0,
6786                         )?;
6787                         return Some(expr0_0);
6788                     }
6789                 }
6790             }
6791         }
6792     }
6793     let pattern0_0 = arg0;
6794     let pattern1_0 = arg1;
6795     if pattern1_0 == I32 {
6796         let pattern3_0 = arg2;
6797         let pattern4_0 = arg3;
6798         // Rule at src/isa/aarch64/lower.isle line 731.
6799         let expr0_0: Type = I32;
6800         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6801         let expr2_0: usize = 0;
6802         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6803         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6804         return Some(expr4_0);
6805     }
6806     if pattern1_0 == I64 {
6807         let pattern3_0 = arg2;
6808         let pattern4_0 = arg3;
6809         // Rule at src/isa/aarch64/lower.isle line 732.
6810         let expr0_0: Type = I64;
6811         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6812         let expr2_0: usize = 0;
6813         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6814         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6815         return Some(expr4_0);
6816     }
6817     if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
6818         let pattern3_0 = arg2;
6819         let pattern4_0 = arg3;
6820         // Rule at src/isa/aarch64/lower.isle line 722.
6821         let expr0_0 = C::put_in_regs(ctx, pattern4_0);
6822         let expr1_0: usize = 0;
6823         let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
6824         let expr3_0: Type = I32;
6825         let expr4_0 = C::shift_mask(ctx, pattern2_0);
6826         let expr5_0 = constructor_and_imm(ctx, expr3_0, expr2_0, expr4_0)?;
6827         let expr6_0: Type = I32;
6828         let expr7_0 = constructor_alu_rrr(ctx, pattern0_0, expr6_0, pattern3_0, expr5_0)?;
6829         return Some(expr7_0);
6830     }
6831     return None;
6832 }
6833 
6834 // Generated as internal constructor for term lower_ushr128.
6835 pub fn constructor_lower_ushr128<C: Context>(
6836     ctx: &mut C,
6837     arg0: ValueRegs,
6838     arg1: Reg,
6839 ) -> Option<ValueRegs> {
6840     let pattern0_0 = arg0;
6841     let pattern1_0 = arg1;
6842     // Rule at src/isa/aarch64/lower.isle line 773.
6843     let expr0_0: usize = 0;
6844     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6845     let expr2_0: usize = 1;
6846     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6847     let expr4_0: Type = I64;
6848     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6849     let expr6_0: Type = I64;
6850     let expr7_0 = constructor_lsr(ctx, expr6_0, expr3_0, pattern1_0)?;
6851     let expr8_0: Type = I32;
6852     let expr9_0 = C::zero_reg(ctx);
6853     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6854     let expr11_0: Type = I64;
6855     let expr12_0: Type = I64;
6856     let expr13_0: u8 = 1;
6857     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6858     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6859     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6860     let expr17_0: Type = I64;
6861     let expr18_0 = constructor_orr(ctx, expr17_0, expr5_0, expr16_0)?;
6862     let expr19_0: Type = I64;
6863     let expr20_0: Type = I64;
6864     let expr21_0: u64 = 64;
6865     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6866     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6867     let expr24_0 = Cond::Ne;
6868     let expr25_0 = constructor_csel(ctx, &expr24_0, expr7_0, expr18_0)?;
6869     let expr26_0 = Cond::Ne;
6870     let expr27_0 = C::zero_reg(ctx);
6871     let expr28_0 = constructor_csel(ctx, &expr26_0, expr27_0, expr7_0)?;
6872     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr25_0, &expr28_0)?;
6873     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6874     return Some(expr30_0);
6875 }
6876 
6877 // Generated as internal constructor for term lower_sshr128.
6878 pub fn constructor_lower_sshr128<C: Context>(
6879     ctx: &mut C,
6880     arg0: ValueRegs,
6881     arg1: Reg,
6882 ) -> Option<ValueRegs> {
6883     let pattern0_0 = arg0;
6884     let pattern1_0 = arg1;
6885     // Rule at src/isa/aarch64/lower.isle line 823.
6886     let expr0_0: usize = 0;
6887     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6888     let expr2_0: usize = 1;
6889     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6890     let expr4_0: Type = I64;
6891     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6892     let expr6_0: Type = I64;
6893     let expr7_0 = constructor_asr(ctx, expr6_0, expr3_0, pattern1_0)?;
6894     let expr8_0: Type = I32;
6895     let expr9_0 = C::zero_reg(ctx);
6896     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6897     let expr11_0: Type = I64;
6898     let expr12_0: Type = I64;
6899     let expr13_0: u8 = 1;
6900     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6901     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6902     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6903     let expr17_0: Type = I64;
6904     let expr18_0: u8 = 63;
6905     let expr19_0 = C::imm_shift_from_u8(ctx, expr18_0);
6906     let expr20_0 = constructor_asr_imm(ctx, expr17_0, expr3_0, expr19_0)?;
6907     let expr21_0: Type = I64;
6908     let expr22_0 = constructor_orr(ctx, expr21_0, expr5_0, expr16_0)?;
6909     let expr23_0: Type = I64;
6910     let expr24_0: Type = I64;
6911     let expr25_0: u64 = 64;
6912     let expr26_0 = C::u64_into_imm_logic(ctx, expr24_0, expr25_0);
6913     let expr27_0 = constructor_tst_imm(ctx, expr23_0, pattern1_0, expr26_0)?;
6914     let expr28_0 = Cond::Ne;
6915     let expr29_0 = constructor_csel(ctx, &expr28_0, expr7_0, expr22_0)?;
6916     let expr30_0 = Cond::Ne;
6917     let expr31_0 = constructor_csel(ctx, &expr30_0, expr20_0, expr7_0)?;
6918     let expr32_0 = constructor_consumes_flags_concat(ctx, &expr29_0, &expr31_0)?;
6919     let expr33_0 = constructor_with_flags(ctx, &expr27_0, &expr32_0)?;
6920     return Some(expr33_0);
6921 }
6922 
6923 // Generated as internal constructor for term small_rotr.
6924 pub fn constructor_small_rotr<C: Context>(
6925     ctx: &mut C,
6926     arg0: Type,
6927     arg1: Reg,
6928     arg2: Reg,
6929 ) -> Option<Reg> {
6930     let pattern0_0 = arg0;
6931     let pattern1_0 = arg1;
6932     let pattern2_0 = arg2;
6933     // Rule at src/isa/aarch64/lower.isle line 933.
6934     let expr0_0: Type = I32;
6935     let expr1_0 = C::rotr_mask(ctx, pattern0_0);
6936     let expr2_0 = constructor_and_imm(ctx, expr0_0, pattern2_0, expr1_0)?;
6937     let expr3_0: Type = I32;
6938     let expr4_0 = C::ty_bits(ctx, pattern0_0);
6939     let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
6940     let expr6_0 = constructor_sub_imm(ctx, expr3_0, expr2_0, expr5_0)?;
6941     let expr7_0: Type = I32;
6942     let expr8_0 = C::zero_reg(ctx);
6943     let expr9_0 = constructor_sub(ctx, expr7_0, expr8_0, expr6_0)?;
6944     let expr10_0: Type = I32;
6945     let expr11_0 = constructor_lsr(ctx, expr10_0, pattern1_0, expr2_0)?;
6946     let expr12_0: Type = I32;
6947     let expr13_0 = constructor_lsl(ctx, expr12_0, pattern1_0, expr9_0)?;
6948     let expr14_0: Type = I32;
6949     let expr15_0 = constructor_orr(ctx, expr14_0, expr13_0, expr11_0)?;
6950     return Some(expr15_0);
6951 }
6952 
6953 // Generated as internal constructor for term small_rotr_imm.
6954 pub fn constructor_small_rotr_imm<C: Context>(
6955     ctx: &mut C,
6956     arg0: Type,
6957     arg1: Reg,
6958     arg2: ImmShift,
6959 ) -> Option<Reg> {
6960     let pattern0_0 = arg0;
6961     let pattern1_0 = arg1;
6962     let pattern2_0 = arg2;
6963     // Rule at src/isa/aarch64/lower.isle line 954.
6964     let expr0_0: Type = I32;
6965     let expr1_0 = constructor_lsr_imm(ctx, expr0_0, pattern1_0, pattern2_0)?;
6966     let expr2_0: Type = I32;
6967     let expr3_0 = C::rotr_opposite_amount(ctx, pattern0_0, pattern2_0);
6968     let expr4_0 = constructor_lsl_imm(ctx, expr2_0, pattern1_0, expr3_0)?;
6969     let expr5_0: Type = I32;
6970     let expr6_0 = constructor_orr(ctx, expr5_0, expr4_0, expr1_0)?;
6971     return Some(expr6_0);
6972 }
6973 
6974 // Generated as internal constructor for term lower_clz128.
6975 pub fn constructor_lower_clz128<C: Context>(ctx: &mut C, arg0: ValueRegs) -> Option<ValueRegs> {
6976     let pattern0_0 = arg0;
6977     // Rule at src/isa/aarch64/lower.isle line 1019.
6978     let expr0_0: Type = I64;
6979     let expr1_0: usize = 1;
6980     let expr2_0 = C::value_regs_get(ctx, pattern0_0, expr1_0);
6981     let expr3_0 = constructor_a64_clz(ctx, expr0_0, expr2_0)?;
6982     let expr4_0: Type = I64;
6983     let expr5_0: usize = 0;
6984     let expr6_0 = C::value_regs_get(ctx, pattern0_0, expr5_0);
6985     let expr7_0 = constructor_a64_clz(ctx, expr4_0, expr6_0)?;
6986     let expr8_0: Type = I64;
6987     let expr9_0: u8 = 6;
6988     let expr10_0 = C::imm_shift_from_u8(ctx, expr9_0);
6989     let expr11_0 = constructor_lsr_imm(ctx, expr8_0, expr3_0, expr10_0)?;
6990     let expr12_0: Type = I64;
6991     let expr13_0 = constructor_madd(ctx, expr12_0, expr7_0, expr11_0, expr3_0)?;
6992     let expr14_0: Type = I64;
6993     let expr15_0: u64 = 0;
6994     let expr16_0 = constructor_imm(ctx, expr14_0, expr15_0)?;
6995     let expr17_0 = C::value_regs(ctx, expr13_0, expr16_0);
6996     return Some(expr17_0);
6997 }
6998