1 // GENERATED BY ISLE. DO NOT EDIT! 2 // 3 // Generated automatically from the instruction-selection DSL code in: 4 // - src/clif.isle 5 // - src/prelude.isle 6 // - src/isa/aarch64/inst.isle 7 // - src/isa/aarch64/lower.isle 8 9 #![allow(dead_code, unreachable_code, unreachable_patterns)] 10 #![allow(unused_imports, unused_variables, non_snake_case, unused_mut)] 11 #![allow(irrefutable_let_patterns)] 12 13 use super::*; // Pulls in all external types. 14 15 /// Context during lowering: an implementation of this trait 16 /// must be provided with all external constructors and extractors. 17 /// A mutable borrow is passed along through all lowering logic. 18 pub trait Context { 19 fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value); 20 fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2; 21 fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value); 22 fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3; 23 fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32; 24 fn s32_add_fallible(&mut self, arg0: u32, arg1: u32) -> Option<u32>; 25 fn u32_nonnegative(&mut self, arg0: u32) -> Option<u32>; 26 fn offset32(&mut self, arg0: Offset32) -> Option<u32>; 27 fn u32_lteq(&mut self, arg0: u32, arg1: u32) -> Option<Unit>; 28 fn simm32(&mut self, arg0: Imm64) -> Option<u32>; 29 fn uimm8(&mut self, arg0: Imm64) -> Option<u8>; 30 fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8; 31 fn value_reg(&mut self, arg0: Reg) -> ValueRegs; 32 fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs; 33 fn value_regs_invalid(&mut self) -> ValueRegs; 34 fn output_none(&mut self) -> InstOutput; 35 fn output(&mut self, arg0: ValueRegs) -> InstOutput; 36 fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput; 37 fn output_builder_new(&mut self) -> InstOutputBuilder; 38 fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit; 39 fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput; 40 fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg; 41 fn invalid_reg_etor(&mut self, arg0: Reg) -> Option<()>; 42 fn invalid_reg(&mut self) -> Reg; 43 fn valid_reg(&mut self, arg0: Reg) -> Option<()>; 44 fn put_in_reg(&mut self, arg0: Value) -> Reg; 45 fn put_in_regs(&mut self, arg0: Value) -> ValueRegs; 46 fn ensure_in_vreg(&mut self, arg0: Reg, arg1: Type) -> Reg; 47 fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg; 48 fn u8_as_u32(&mut self, arg0: u8) -> Option<u32>; 49 fn u8_as_u64(&mut self, arg0: u8) -> Option<u64>; 50 fn u16_as_u64(&mut self, arg0: u16) -> Option<u64>; 51 fn u32_as_u64(&mut self, arg0: u32) -> Option<u64>; 52 fn i64_as_u64(&mut self, arg0: i64) -> Option<u64>; 53 fn u64_add(&mut self, arg0: u64, arg1: u64) -> Option<u64>; 54 fn u64_sub(&mut self, arg0: u64, arg1: u64) -> Option<u64>; 55 fn u64_and(&mut self, arg0: u64, arg1: u64) -> Option<u64>; 56 fn ty_bits(&mut self, arg0: Type) -> Option<u8>; 57 fn ty_bits_u16(&mut self, arg0: Type) -> u16; 58 fn ty_bits_u64(&mut self, arg0: Type) -> u64; 59 fn ty_mask(&mut self, arg0: Type) -> u64; 60 fn ty_bytes(&mut self, arg0: Type) -> u16; 61 fn lane_type(&mut self, arg0: Type) -> Type; 62 fn fits_in_16(&mut self, arg0: Type) -> Option<Type>; 63 fn fits_in_32(&mut self, arg0: Type) -> Option<Type>; 64 fn fits_in_64(&mut self, arg0: Type) -> Option<Type>; 65 fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>; 66 fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>; 67 fn ty_int_bool_64(&mut self, arg0: Type) -> Option<Type>; 68 fn ty_int_bool_ref_64(&mut self, arg0: Type) -> Option<Type>; 69 fn ty_int_bool_128(&mut self, arg0: Type) -> Option<Type>; 70 fn ty_scalar_float(&mut self, arg0: Type) -> Option<Type>; 71 fn ty_vec128(&mut self, arg0: Type) -> Option<Type>; 72 fn ty_vec128_int(&mut self, arg0: Type) -> Option<Type>; 73 fn not_i64x2(&mut self, arg0: Type) -> Option<()>; 74 fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice; 75 fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>; 76 fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>; 77 fn value_slice_len(&mut self, arg0: ValueSlice) -> usize; 78 fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value; 79 fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg; 80 fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8; 81 fn u64_from_imm64(&mut self, arg0: Imm64) -> u64; 82 fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>; 83 fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64; 84 fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64; 85 fn inst_results(&mut self, arg0: Inst) -> ValueSlice; 86 fn first_result(&mut self, arg0: Inst) -> Option<Value>; 87 fn inst_data(&mut self, arg0: Inst) -> InstructionData; 88 fn value_type(&mut self, arg0: Value) -> Type; 89 fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>; 90 fn def_inst(&mut self, arg0: Value) -> Option<Inst>; 91 fn offset32_to_u32(&mut self, arg0: Offset32) -> u32; 92 fn emit(&mut self, arg0: &MInst) -> Unit; 93 fn trap_code_division_by_zero(&mut self) -> TrapCode; 94 fn trap_code_integer_overflow(&mut self) -> TrapCode; 95 fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode; 96 fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>; 97 fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance); 98 fn symbol_value_data( 99 &mut self, 100 arg0: GlobalValue, 101 ) -> Option<(ExternalName, RelocDistance, i64)>; 102 fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>; 103 fn use_lse(&mut self, arg0: Inst) -> Option<()>; 104 fn move_wide_const_from_u64(&mut self, arg0: u64) -> Option<MoveWideConst>; 105 fn move_wide_const_from_negated_u64(&mut self, arg0: u64) -> Option<MoveWideConst>; 106 fn imm_logic_from_u64(&mut self, arg0: Type, arg1: u64) -> Option<ImmLogic>; 107 fn imm_logic_from_imm64(&mut self, arg0: Type, arg1: Imm64) -> Option<ImmLogic>; 108 fn imm_shift_from_imm64(&mut self, arg0: Type, arg1: Imm64) -> Option<ImmShift>; 109 fn imm_shift_from_u8(&mut self, arg0: u8) -> ImmShift; 110 fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12>; 111 fn u8_into_uimm5(&mut self, arg0: u8) -> UImm5; 112 fn u8_into_imm12(&mut self, arg0: u8) -> Imm12; 113 fn u64_into_imm_logic(&mut self, arg0: Type, arg1: u64) -> ImmLogic; 114 fn imm12_from_negated_u64(&mut self, arg0: u64) -> Option<Imm12>; 115 fn lshl_from_imm64(&mut self, arg0: Type, arg1: Imm64) -> Option<ShiftOpAndAmt>; 116 fn integral_ty(&mut self, arg0: Type) -> Option<Type>; 117 fn valid_atomic_transaction(&mut self, arg0: Type) -> Option<Type>; 118 fn extended_value_from_value(&mut self, arg0: Value) -> Option<ExtendedValue>; 119 fn put_extended_in_reg(&mut self, arg0: &ExtendedValue) -> Reg; 120 fn get_extended_op(&mut self, arg0: &ExtendedValue) -> ExtendOp; 121 fn nzcv(&mut self, arg0: bool, arg1: bool, arg2: bool, arg3: bool) -> NZCV; 122 fn cond_br_zero(&mut self, arg0: Reg) -> CondBrKind; 123 fn cond_br_cond(&mut self, arg0: &Cond) -> CondBrKind; 124 fn zero_reg(&mut self) -> Reg; 125 fn writable_zero_reg(&mut self) -> WritableReg; 126 fn xreg(&mut self, arg0: u8) -> Reg; 127 fn writable_xreg(&mut self, arg0: u8) -> WritableReg; 128 fn load_constant64_full(&mut self, arg0: u64) -> Reg; 129 fn sinkable_atomic_load(&mut self, arg0: Value) -> Option<SinkableAtomicLoad>; 130 fn sink_atomic_load(&mut self, arg0: &SinkableAtomicLoad) -> Reg; 131 fn zero_value_f32(&mut self, arg0: Ieee32) -> Option<Ieee32>; 132 fn zero_value_f64(&mut self, arg0: Ieee64) -> Option<Ieee64>; 133 fn float_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &FloatCC) -> VecMisc2; 134 fn float_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &FloatCC) -> VecMisc2; 135 fn fcmp_zero_cond(&mut self, arg0: &FloatCC) -> Option<FloatCC>; 136 fn fcmp_zero_cond_not_eq(&mut self, arg0: &FloatCC) -> Option<FloatCC>; 137 fn zero_value(&mut self, arg0: Imm64) -> Option<Imm64>; 138 fn int_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &IntCC) -> VecMisc2; 139 fn int_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &IntCC) -> VecMisc2; 140 fn icmp_zero_cond(&mut self, arg0: &IntCC) -> Option<IntCC>; 141 fn icmp_zero_cond_not_eq(&mut self, arg0: &IntCC) -> Option<IntCC>; 142 fn safe_divisor_from_imm64(&mut self, arg0: Imm64) -> Option<u64>; 143 fn shift_mask(&mut self, arg0: Type) -> ImmLogic; 144 fn negate_imm_shift(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift; 145 fn rotr_mask(&mut self, arg0: Type) -> ImmLogic; 146 fn rotr_opposite_amount(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift; 147 } 148 149 /// Internal type SideEffectNoResult: defined at src/prelude.isle line 447. 150 #[derive(Clone, Debug)] 151 pub enum SideEffectNoResult { 152 Inst { inst: MInst }, 153 Inst2 { inst1: MInst, inst2: MInst }, 154 } 155 156 /// Internal type ProducesFlags: defined at src/prelude.isle line 474. 157 #[derive(Clone, Debug)] 158 pub enum ProducesFlags { 159 ProducesFlagsSideEffect { inst: MInst }, 160 ProducesFlagsReturnsReg { inst: MInst, result: Reg }, 161 ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg }, 162 } 163 164 /// Internal type ConsumesFlags: defined at src/prelude.isle line 485. 165 #[derive(Clone, Debug)] 166 pub enum ConsumesFlags { 167 ConsumesFlagsReturnsResultWithProducer { 168 inst: MInst, 169 result: Reg, 170 }, 171 ConsumesFlagsReturnsReg { 172 inst: MInst, 173 result: Reg, 174 }, 175 ConsumesFlagsTwiceReturnsValueRegs { 176 inst1: MInst, 177 inst2: MInst, 178 result: ValueRegs, 179 }, 180 ConsumesFlagsFourTimesReturnsValueRegs { 181 inst1: MInst, 182 inst2: MInst, 183 inst3: MInst, 184 inst4: MInst, 185 result: ValueRegs, 186 }, 187 } 188 189 /// Internal type MInst: defined at src/isa/aarch64/inst.isle line 2. 190 #[derive(Clone, Debug)] 191 pub enum MInst { 192 Nop0, 193 Nop4, 194 AluRRR { 195 alu_op: ALUOp, 196 size: OperandSize, 197 rd: WritableReg, 198 rn: Reg, 199 rm: Reg, 200 }, 201 AluRRRR { 202 alu_op: ALUOp3, 203 size: OperandSize, 204 rd: WritableReg, 205 rn: Reg, 206 rm: Reg, 207 ra: Reg, 208 }, 209 AluRRImm12 { 210 alu_op: ALUOp, 211 size: OperandSize, 212 rd: WritableReg, 213 rn: Reg, 214 imm12: Imm12, 215 }, 216 AluRRImmLogic { 217 alu_op: ALUOp, 218 size: OperandSize, 219 rd: WritableReg, 220 rn: Reg, 221 imml: ImmLogic, 222 }, 223 AluRRImmShift { 224 alu_op: ALUOp, 225 size: OperandSize, 226 rd: WritableReg, 227 rn: Reg, 228 immshift: ImmShift, 229 }, 230 AluRRRShift { 231 alu_op: ALUOp, 232 size: OperandSize, 233 rd: WritableReg, 234 rn: Reg, 235 rm: Reg, 236 shiftop: ShiftOpAndAmt, 237 }, 238 AluRRRExtend { 239 alu_op: ALUOp, 240 size: OperandSize, 241 rd: WritableReg, 242 rn: Reg, 243 rm: Reg, 244 extendop: ExtendOp, 245 }, 246 BitRR { 247 op: BitOp, 248 size: OperandSize, 249 rd: WritableReg, 250 rn: Reg, 251 }, 252 ULoad8 { 253 rd: WritableReg, 254 mem: AMode, 255 flags: MemFlags, 256 }, 257 SLoad8 { 258 rd: WritableReg, 259 mem: AMode, 260 flags: MemFlags, 261 }, 262 ULoad16 { 263 rd: WritableReg, 264 mem: AMode, 265 flags: MemFlags, 266 }, 267 SLoad16 { 268 rd: WritableReg, 269 mem: AMode, 270 flags: MemFlags, 271 }, 272 ULoad32 { 273 rd: WritableReg, 274 mem: AMode, 275 flags: MemFlags, 276 }, 277 SLoad32 { 278 rd: WritableReg, 279 mem: AMode, 280 flags: MemFlags, 281 }, 282 ULoad64 { 283 rd: WritableReg, 284 mem: AMode, 285 flags: MemFlags, 286 }, 287 Store8 { 288 rd: Reg, 289 mem: AMode, 290 flags: MemFlags, 291 }, 292 Store16 { 293 rd: Reg, 294 mem: AMode, 295 flags: MemFlags, 296 }, 297 Store32 { 298 rd: Reg, 299 mem: AMode, 300 flags: MemFlags, 301 }, 302 Store64 { 303 rd: Reg, 304 mem: AMode, 305 flags: MemFlags, 306 }, 307 StoreP64 { 308 rt: Reg, 309 rt2: Reg, 310 mem: PairAMode, 311 flags: MemFlags, 312 }, 313 LoadP64 { 314 rt: WritableReg, 315 rt2: WritableReg, 316 mem: PairAMode, 317 flags: MemFlags, 318 }, 319 Mov { 320 size: OperandSize, 321 rd: WritableReg, 322 rm: Reg, 323 }, 324 MovWide { 325 op: MoveWideOp, 326 rd: WritableReg, 327 imm: MoveWideConst, 328 size: OperandSize, 329 }, 330 Extend { 331 rd: WritableReg, 332 rn: Reg, 333 signed: bool, 334 from_bits: u8, 335 to_bits: u8, 336 }, 337 CSel { 338 rd: WritableReg, 339 cond: Cond, 340 rn: Reg, 341 rm: Reg, 342 }, 343 CSet { 344 rd: WritableReg, 345 cond: Cond, 346 }, 347 CSetm { 348 rd: WritableReg, 349 cond: Cond, 350 }, 351 CCmpImm { 352 size: OperandSize, 353 rn: Reg, 354 imm: UImm5, 355 nzcv: NZCV, 356 cond: Cond, 357 }, 358 AtomicRMWLoop { 359 ty: Type, 360 op: AtomicRMWLoopOp, 361 }, 362 AtomicCASLoop { 363 ty: Type, 364 }, 365 AtomicRMW { 366 op: AtomicRMWOp, 367 rs: Reg, 368 rt: WritableReg, 369 rn: Reg, 370 ty: Type, 371 }, 372 AtomicCAS { 373 rs: WritableReg, 374 rt: Reg, 375 rn: Reg, 376 ty: Type, 377 }, 378 LoadAcquire { 379 access_ty: Type, 380 rt: WritableReg, 381 rn: Reg, 382 }, 383 StoreRelease { 384 access_ty: Type, 385 rt: Reg, 386 rn: Reg, 387 }, 388 Fence, 389 FpuMove64 { 390 rd: WritableReg, 391 rn: Reg, 392 }, 393 FpuMove128 { 394 rd: WritableReg, 395 rn: Reg, 396 }, 397 FpuMoveFromVec { 398 rd: WritableReg, 399 rn: Reg, 400 idx: u8, 401 size: VectorSize, 402 }, 403 FpuExtend { 404 rd: WritableReg, 405 rn: Reg, 406 size: ScalarSize, 407 }, 408 FpuRR { 409 fpu_op: FPUOp1, 410 size: ScalarSize, 411 rd: WritableReg, 412 rn: Reg, 413 }, 414 FpuRRR { 415 fpu_op: FPUOp2, 416 size: ScalarSize, 417 rd: WritableReg, 418 rn: Reg, 419 rm: Reg, 420 }, 421 FpuRRI { 422 fpu_op: FPUOpRI, 423 rd: WritableReg, 424 rn: Reg, 425 }, 426 FpuRRRR { 427 fpu_op: FPUOp3, 428 rd: WritableReg, 429 rn: Reg, 430 rm: Reg, 431 ra: Reg, 432 }, 433 FpuCmp { 434 size: ScalarSize, 435 rn: Reg, 436 rm: Reg, 437 }, 438 FpuLoad32 { 439 rd: WritableReg, 440 mem: AMode, 441 flags: MemFlags, 442 }, 443 FpuStore32 { 444 rd: Reg, 445 mem: AMode, 446 flags: MemFlags, 447 }, 448 FpuLoad64 { 449 rd: WritableReg, 450 mem: AMode, 451 flags: MemFlags, 452 }, 453 FpuStore64 { 454 rd: Reg, 455 mem: AMode, 456 flags: MemFlags, 457 }, 458 FpuLoad128 { 459 rd: WritableReg, 460 mem: AMode, 461 flags: MemFlags, 462 }, 463 FpuStore128 { 464 rd: Reg, 465 mem: AMode, 466 flags: MemFlags, 467 }, 468 FpuLoadP64 { 469 rt: WritableReg, 470 rt2: WritableReg, 471 mem: PairAMode, 472 flags: MemFlags, 473 }, 474 FpuStoreP64 { 475 rt: Reg, 476 rt2: Reg, 477 mem: PairAMode, 478 flags: MemFlags, 479 }, 480 FpuLoadP128 { 481 rt: WritableReg, 482 rt2: WritableReg, 483 mem: PairAMode, 484 flags: MemFlags, 485 }, 486 FpuStoreP128 { 487 rt: Reg, 488 rt2: Reg, 489 mem: PairAMode, 490 flags: MemFlags, 491 }, 492 LoadFpuConst64 { 493 rd: WritableReg, 494 const_data: u64, 495 }, 496 LoadFpuConst128 { 497 rd: WritableReg, 498 const_data: u128, 499 }, 500 FpuToInt { 501 op: FpuToIntOp, 502 rd: WritableReg, 503 rn: Reg, 504 }, 505 IntToFpu { 506 op: IntToFpuOp, 507 rd: WritableReg, 508 rn: Reg, 509 }, 510 FpuCSel32 { 511 rd: WritableReg, 512 rn: Reg, 513 rm: Reg, 514 cond: Cond, 515 }, 516 FpuCSel64 { 517 rd: WritableReg, 518 rn: Reg, 519 rm: Reg, 520 cond: Cond, 521 }, 522 FpuRound { 523 op: FpuRoundMode, 524 rd: WritableReg, 525 rn: Reg, 526 }, 527 MovToFpu { 528 rd: WritableReg, 529 rn: Reg, 530 size: ScalarSize, 531 }, 532 FpuMoveFPImm { 533 rd: WritableReg, 534 imm: ASIMDFPModImm, 535 size: ScalarSize, 536 }, 537 MovToVec { 538 rd: WritableReg, 539 rn: Reg, 540 idx: u8, 541 size: VectorSize, 542 }, 543 MovFromVec { 544 rd: WritableReg, 545 rn: Reg, 546 idx: u8, 547 size: VectorSize, 548 }, 549 MovFromVecSigned { 550 rd: WritableReg, 551 rn: Reg, 552 idx: u8, 553 size: VectorSize, 554 scalar_size: OperandSize, 555 }, 556 VecDup { 557 rd: WritableReg, 558 rn: Reg, 559 size: VectorSize, 560 }, 561 VecDupFromFpu { 562 rd: WritableReg, 563 rn: Reg, 564 size: VectorSize, 565 }, 566 VecDupFPImm { 567 rd: WritableReg, 568 imm: ASIMDFPModImm, 569 size: VectorSize, 570 }, 571 VecDupImm { 572 rd: WritableReg, 573 imm: ASIMDMovModImm, 574 invert: bool, 575 size: VectorSize, 576 }, 577 VecExtend { 578 t: VecExtendOp, 579 rd: WritableReg, 580 rn: Reg, 581 high_half: bool, 582 }, 583 VecMovElement { 584 rd: WritableReg, 585 rn: Reg, 586 dest_idx: u8, 587 src_idx: u8, 588 size: VectorSize, 589 }, 590 VecRRLong { 591 op: VecRRLongOp, 592 rd: WritableReg, 593 rn: Reg, 594 high_half: bool, 595 }, 596 VecRRNarrow { 597 op: VecRRNarrowOp, 598 rd: WritableReg, 599 rn: Reg, 600 high_half: bool, 601 }, 602 VecRRPair { 603 op: VecPairOp, 604 rd: WritableReg, 605 rn: Reg, 606 }, 607 VecRRRLong { 608 alu_op: VecRRRLongOp, 609 rd: WritableReg, 610 rn: Reg, 611 rm: Reg, 612 high_half: bool, 613 }, 614 VecRRPairLong { 615 op: VecRRPairLongOp, 616 rd: WritableReg, 617 rn: Reg, 618 }, 619 VecRRR { 620 alu_op: VecALUOp, 621 rd: WritableReg, 622 rn: Reg, 623 rm: Reg, 624 size: VectorSize, 625 }, 626 VecMisc { 627 op: VecMisc2, 628 rd: WritableReg, 629 rn: Reg, 630 size: VectorSize, 631 }, 632 VecLanes { 633 op: VecLanesOp, 634 rd: WritableReg, 635 rn: Reg, 636 size: VectorSize, 637 }, 638 VecShiftImm { 639 op: VecShiftImmOp, 640 rd: WritableReg, 641 rn: Reg, 642 size: VectorSize, 643 imm: u8, 644 }, 645 VecExtract { 646 rd: WritableReg, 647 rn: Reg, 648 rm: Reg, 649 imm4: u8, 650 }, 651 VecTbl { 652 rd: WritableReg, 653 rn: Reg, 654 rm: Reg, 655 is_extension: bool, 656 }, 657 VecTbl2 { 658 rd: WritableReg, 659 rn: Reg, 660 rn2: Reg, 661 rm: Reg, 662 is_extension: bool, 663 }, 664 VecLoadReplicate { 665 rd: WritableReg, 666 rn: Reg, 667 size: VectorSize, 668 }, 669 VecCSel { 670 rd: WritableReg, 671 rn: Reg, 672 rm: Reg, 673 cond: Cond, 674 }, 675 MovToNZCV { 676 rn: Reg, 677 }, 678 MovFromNZCV { 679 rd: WritableReg, 680 }, 681 Call { 682 info: BoxCallInfo, 683 }, 684 CallInd { 685 info: BoxCallIndInfo, 686 }, 687 Ret { 688 rets: VecReg, 689 }, 690 EpiloguePlaceholder, 691 Jump { 692 dest: BranchTarget, 693 }, 694 CondBr { 695 taken: BranchTarget, 696 not_taken: BranchTarget, 697 kind: CondBrKind, 698 }, 699 TrapIf { 700 kind: CondBrKind, 701 trap_code: TrapCode, 702 }, 703 IndirectBr { 704 rn: Reg, 705 targets: VecMachLabel, 706 }, 707 Brk, 708 Udf { 709 trap_code: TrapCode, 710 }, 711 Adr { 712 rd: WritableReg, 713 off: i32, 714 }, 715 Word4 { 716 data: u32, 717 }, 718 Word8 { 719 data: u64, 720 }, 721 JTSequence { 722 info: BoxJTSequenceInfo, 723 ridx: Reg, 724 rtmp1: WritableReg, 725 rtmp2: WritableReg, 726 }, 727 LoadExtName { 728 rd: WritableReg, 729 name: BoxExternalName, 730 offset: i64, 731 }, 732 LoadAddr { 733 rd: WritableReg, 734 mem: AMode, 735 }, 736 VirtualSPOffsetAdj { 737 offset: i64, 738 }, 739 EmitIsland { 740 needed_space: CodeOffset, 741 }, 742 ElfTlsGetAddr { 743 symbol: ExternalName, 744 }, 745 Unwind { 746 inst: UnwindInst, 747 }, 748 DummyUse { 749 reg: Reg, 750 }, 751 } 752 753 /// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 776. 754 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 755 pub enum ALUOp { 756 Add, 757 Sub, 758 Orr, 759 OrrNot, 760 And, 761 AndS, 762 AndNot, 763 Eor, 764 EorNot, 765 AddS, 766 SubS, 767 SMulH, 768 UMulH, 769 SDiv, 770 UDiv, 771 RotR, 772 Lsr, 773 Asr, 774 Lsl, 775 Adc, 776 AdcS, 777 Sbc, 778 SbcS, 779 } 780 781 /// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 814. 782 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 783 pub enum ALUOp3 { 784 MAdd, 785 MSub, 786 } 787 788 /// Internal type MoveWideOp: defined at src/isa/aarch64/inst.isle line 822. 789 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 790 pub enum MoveWideOp { 791 MovZ, 792 MovN, 793 MovK, 794 } 795 796 /// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 860. 797 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 798 pub enum BitOp { 799 RBit, 800 Clz, 801 Cls, 802 } 803 804 /// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 927. 805 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 806 pub enum FPUOp1 { 807 Abs, 808 Neg, 809 Sqrt, 810 Cvt32To64, 811 Cvt64To32, 812 } 813 814 /// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 937. 815 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 816 pub enum FPUOp2 { 817 Add, 818 Sub, 819 Mul, 820 Div, 821 Max, 822 Min, 823 } 824 825 /// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 948. 826 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 827 pub enum FPUOp3 { 828 MAdd32, 829 MAdd64, 830 } 831 832 /// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 955. 833 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 834 pub enum FpuToIntOp { 835 F32ToU32, 836 F32ToI32, 837 F32ToU64, 838 F32ToI64, 839 F64ToU32, 840 F64ToI32, 841 F64ToU64, 842 F64ToI64, 843 } 844 845 /// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 968. 846 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 847 pub enum IntToFpuOp { 848 U32ToF32, 849 I32ToF32, 850 U32ToF64, 851 I32ToF64, 852 U64ToF32, 853 I64ToF32, 854 U64ToF64, 855 I64ToF64, 856 } 857 858 /// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 982. 859 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 860 pub enum FpuRoundMode { 861 Minus32, 862 Minus64, 863 Plus32, 864 Plus64, 865 Zero32, 866 Zero64, 867 Nearest32, 868 Nearest64, 869 } 870 871 /// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 995. 872 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 873 pub enum VecExtendOp { 874 Sxtl8, 875 Sxtl16, 876 Sxtl32, 877 Uxtl8, 878 Uxtl16, 879 Uxtl32, 880 } 881 882 /// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1012. 883 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 884 pub enum VecALUOp { 885 Sqadd, 886 Uqadd, 887 Sqsub, 888 Uqsub, 889 Cmeq, 890 Cmge, 891 Cmgt, 892 Cmhs, 893 Cmhi, 894 Fcmeq, 895 Fcmgt, 896 Fcmge, 897 And, 898 Bic, 899 Orr, 900 Eor, 901 Bsl, 902 Umaxp, 903 Add, 904 Sub, 905 Mul, 906 Sshl, 907 Ushl, 908 Umin, 909 Smin, 910 Umax, 911 Smax, 912 Urhadd, 913 Fadd, 914 Fsub, 915 Fdiv, 916 Fmax, 917 Fmin, 918 Fmul, 919 Addp, 920 Zip1, 921 Sqrdmulh, 922 } 923 924 /// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1091. 925 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 926 pub enum VecMisc2 { 927 Not, 928 Neg, 929 Abs, 930 Fabs, 931 Fneg, 932 Fsqrt, 933 Rev64, 934 Fcvtzs, 935 Fcvtzu, 936 Scvtf, 937 Ucvtf, 938 Frintn, 939 Frintz, 940 Frintm, 941 Frintp, 942 Cnt, 943 Cmeq0, 944 Cmge0, 945 Cmgt0, 946 Cmle0, 947 Cmlt0, 948 Fcmeq0, 949 Fcmge0, 950 Fcmgt0, 951 Fcmle0, 952 Fcmlt0, 953 } 954 955 /// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1148. 956 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 957 pub enum VecRRLongOp { 958 Fcvtl16, 959 Fcvtl32, 960 Shll8, 961 Shll16, 962 Shll32, 963 } 964 965 /// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1163. 966 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 967 pub enum VecRRNarrowOp { 968 Xtn16, 969 Xtn32, 970 Xtn64, 971 Sqxtn16, 972 Sqxtn32, 973 Sqxtn64, 974 Sqxtun16, 975 Sqxtun32, 976 Sqxtun64, 977 Uqxtn16, 978 Uqxtn32, 979 Uqxtn64, 980 Fcvtn32, 981 Fcvtn64, 982 } 983 984 /// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1195. 985 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 986 pub enum VecRRRLongOp { 987 Smull8, 988 Smull16, 989 Smull32, 990 Umull8, 991 Umull16, 992 Umull32, 993 Umlal8, 994 Umlal16, 995 Umlal32, 996 } 997 998 /// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1212. 999 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 1000 pub enum VecPairOp { 1001 Addp, 1002 } 1003 1004 /// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1220. 1005 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 1006 pub enum VecRRPairLongOp { 1007 Saddlp8, 1008 Saddlp16, 1009 Uaddlp8, 1010 Uaddlp16, 1011 } 1012 1013 /// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1231. 1014 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 1015 pub enum VecLanesOp { 1016 Addv, 1017 Uminv, 1018 } 1019 1020 /// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1240. 1021 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 1022 pub enum VecShiftImmOp { 1023 Shl, 1024 Ushr, 1025 Sshr, 1026 } 1027 1028 /// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1251. 1029 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 1030 pub enum AtomicRMWOp { 1031 Add, 1032 Clr, 1033 Eor, 1034 Set, 1035 Smax, 1036 Smin, 1037 Umax, 1038 Umin, 1039 Swp, 1040 } 1041 1042 /// Internal type AtomicRMWLoopOp: defined at src/isa/aarch64/inst.isle line 1266. 1043 #[derive(Copy, Clone, PartialEq, Eq, Debug)] 1044 pub enum AtomicRMWLoopOp { 1045 Add, 1046 Sub, 1047 And, 1048 Nand, 1049 Eor, 1050 Orr, 1051 Smax, 1052 Smin, 1053 Umax, 1054 Umin, 1055 Xchg, 1056 } 1057 1058 // Generated as internal constructor for term output_reg. 1059 pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> { 1060 let pattern0_0 = arg0; 1061 // Rule at src/prelude.isle line 113. 1062 let expr0_0 = C::value_reg(ctx, pattern0_0); 1063 let expr1_0 = C::output(ctx, expr0_0); 1064 return Some(expr1_0); 1065 } 1066 1067 // Generated as internal constructor for term output_value. 1068 pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> { 1069 let pattern0_0 = arg0; 1070 // Rule at src/prelude.isle line 117. 1071 let expr0_0 = C::put_in_regs(ctx, pattern0_0); 1072 let expr1_0 = C::output(ctx, expr0_0); 1073 return Some(expr1_0); 1074 } 1075 1076 // Generated as internal constructor for term temp_reg. 1077 pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> { 1078 let pattern0_0 = arg0; 1079 // Rule at src/prelude.isle line 137. 1080 let expr0_0 = C::temp_writable_reg(ctx, pattern0_0); 1081 let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0); 1082 return Some(expr1_0); 1083 } 1084 1085 // Generated as internal constructor for term lo_reg. 1086 pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> { 1087 let pattern0_0 = arg0; 1088 // Rule at src/prelude.isle line 182. 1089 let expr0_0 = C::put_in_regs(ctx, pattern0_0); 1090 let expr1_0: usize = 0; 1091 let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); 1092 return Some(expr2_0); 1093 } 1094 1095 // Generated as internal constructor for term side_effect. 1096 pub fn constructor_side_effect<C: Context>( 1097 ctx: &mut C, 1098 arg0: &SideEffectNoResult, 1099 ) -> Option<InstOutput> { 1100 let pattern0_0 = arg0; 1101 match pattern0_0 { 1102 &SideEffectNoResult::Inst { 1103 inst: ref pattern1_0, 1104 } => { 1105 // Rule at src/prelude.isle line 455. 1106 let expr0_0 = C::emit(ctx, pattern1_0); 1107 let expr1_0 = C::output_none(ctx); 1108 return Some(expr1_0); 1109 } 1110 &SideEffectNoResult::Inst2 { 1111 inst1: ref pattern1_0, 1112 inst2: ref pattern1_1, 1113 } => { 1114 // Rule at src/prelude.isle line 458. 1115 let expr0_0 = C::emit(ctx, pattern1_0); 1116 let expr1_0 = C::emit(ctx, pattern1_1); 1117 let expr2_0 = C::output_none(ctx); 1118 return Some(expr2_0); 1119 } 1120 _ => {} 1121 } 1122 return None; 1123 } 1124 1125 // Generated as internal constructor for term side_effect_concat. 1126 pub fn constructor_side_effect_concat<C: Context>( 1127 ctx: &mut C, 1128 arg0: &SideEffectNoResult, 1129 arg1: &SideEffectNoResult, 1130 ) -> Option<SideEffectNoResult> { 1131 let pattern0_0 = arg0; 1132 if let &SideEffectNoResult::Inst { 1133 inst: ref pattern1_0, 1134 } = pattern0_0 1135 { 1136 let pattern2_0 = arg1; 1137 if let &SideEffectNoResult::Inst { 1138 inst: ref pattern3_0, 1139 } = pattern2_0 1140 { 1141 // Rule at src/prelude.isle line 464. 1142 let expr0_0 = SideEffectNoResult::Inst2 { 1143 inst1: pattern1_0.clone(), 1144 inst2: pattern3_0.clone(), 1145 }; 1146 return Some(expr0_0); 1147 } 1148 } 1149 return None; 1150 } 1151 1152 // Generated as internal constructor for term produces_flags_get_reg. 1153 pub fn constructor_produces_flags_get_reg<C: Context>( 1154 ctx: &mut C, 1155 arg0: &ProducesFlags, 1156 ) -> Option<Reg> { 1157 let pattern0_0 = arg0; 1158 if let &ProducesFlags::ProducesFlagsReturnsReg { 1159 inst: ref pattern1_0, 1160 result: pattern1_1, 1161 } = pattern0_0 1162 { 1163 // Rule at src/prelude.isle line 501. 1164 return Some(pattern1_1); 1165 } 1166 return None; 1167 } 1168 1169 // Generated as internal constructor for term produces_flags_ignore. 1170 pub fn constructor_produces_flags_ignore<C: Context>( 1171 ctx: &mut C, 1172 arg0: &ProducesFlags, 1173 ) -> Option<ProducesFlags> { 1174 let pattern0_0 = arg0; 1175 match pattern0_0 { 1176 &ProducesFlags::ProducesFlagsReturnsReg { 1177 inst: ref pattern1_0, 1178 result: pattern1_1, 1179 } => { 1180 // Rule at src/prelude.isle line 506. 1181 let expr0_0 = ProducesFlags::ProducesFlagsSideEffect { 1182 inst: pattern1_0.clone(), 1183 }; 1184 return Some(expr0_0); 1185 } 1186 &ProducesFlags::ProducesFlagsReturnsResultWithConsumer { 1187 inst: ref pattern1_0, 1188 result: pattern1_1, 1189 } => { 1190 // Rule at src/prelude.isle line 508. 1191 let expr0_0 = ProducesFlags::ProducesFlagsSideEffect { 1192 inst: pattern1_0.clone(), 1193 }; 1194 return Some(expr0_0); 1195 } 1196 _ => {} 1197 } 1198 return None; 1199 } 1200 1201 // Generated as internal constructor for term consumes_flags_concat. 1202 pub fn constructor_consumes_flags_concat<C: Context>( 1203 ctx: &mut C, 1204 arg0: &ConsumesFlags, 1205 arg1: &ConsumesFlags, 1206 ) -> Option<ConsumesFlags> { 1207 let pattern0_0 = arg0; 1208 if let &ConsumesFlags::ConsumesFlagsReturnsReg { 1209 inst: ref pattern1_0, 1210 result: pattern1_1, 1211 } = pattern0_0 1212 { 1213 let pattern2_0 = arg1; 1214 if let &ConsumesFlags::ConsumesFlagsReturnsReg { 1215 inst: ref pattern3_0, 1216 result: pattern3_1, 1217 } = pattern2_0 1218 { 1219 // Rule at src/prelude.isle line 515. 1220 let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1); 1221 let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs { 1222 inst1: pattern1_0.clone(), 1223 inst2: pattern3_0.clone(), 1224 result: expr0_0, 1225 }; 1226 return Some(expr1_0); 1227 } 1228 } 1229 return None; 1230 } 1231 1232 // Generated as internal constructor for term with_flags. 1233 pub fn constructor_with_flags<C: Context>( 1234 ctx: &mut C, 1235 arg0: &ProducesFlags, 1236 arg1: &ConsumesFlags, 1237 ) -> Option<ValueRegs> { 1238 let pattern0_0 = arg0; 1239 match pattern0_0 { 1240 &ProducesFlags::ProducesFlagsSideEffect { 1241 inst: ref pattern1_0, 1242 } => { 1243 let pattern2_0 = arg1; 1244 match pattern2_0 { 1245 &ConsumesFlags::ConsumesFlagsReturnsReg { 1246 inst: ref pattern3_0, 1247 result: pattern3_1, 1248 } => { 1249 // Rule at src/prelude.isle line 540. 1250 let expr0_0 = C::emit(ctx, pattern1_0); 1251 let expr1_0 = C::emit(ctx, pattern3_0); 1252 let expr2_0 = C::value_reg(ctx, pattern3_1); 1253 return Some(expr2_0); 1254 } 1255 &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs { 1256 inst1: ref pattern3_0, 1257 inst2: ref pattern3_1, 1258 result: pattern3_2, 1259 } => { 1260 // Rule at src/prelude.isle line 546. 1261 let expr0_0 = C::emit(ctx, pattern1_0); 1262 let expr1_0 = C::emit(ctx, pattern3_0); 1263 let expr2_0 = C::emit(ctx, pattern3_1); 1264 return Some(pattern3_2); 1265 } 1266 &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs { 1267 inst1: ref pattern3_0, 1268 inst2: ref pattern3_1, 1269 inst3: ref pattern3_2, 1270 inst4: ref pattern3_3, 1271 result: pattern3_4, 1272 } => { 1273 // Rule at src/prelude.isle line 558. 1274 let expr0_0 = C::emit(ctx, pattern1_0); 1275 let expr1_0 = C::emit(ctx, pattern3_0); 1276 let expr2_0 = C::emit(ctx, pattern3_1); 1277 let expr3_0 = C::emit(ctx, pattern3_2); 1278 let expr4_0 = C::emit(ctx, pattern3_3); 1279 return Some(pattern3_4); 1280 } 1281 _ => {} 1282 } 1283 } 1284 &ProducesFlags::ProducesFlagsReturnsResultWithConsumer { 1285 inst: ref pattern1_0, 1286 result: pattern1_1, 1287 } => { 1288 let pattern2_0 = arg1; 1289 if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer { 1290 inst: ref pattern3_0, 1291 result: pattern3_1, 1292 } = pattern2_0 1293 { 1294 // Rule at src/prelude.isle line 534. 1295 let expr0_0 = C::emit(ctx, pattern1_0); 1296 let expr1_0 = C::emit(ctx, pattern3_0); 1297 let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1); 1298 return Some(expr2_0); 1299 } 1300 } 1301 _ => {} 1302 } 1303 return None; 1304 } 1305 1306 // Generated as internal constructor for term with_flags_reg. 1307 pub fn constructor_with_flags_reg<C: Context>( 1308 ctx: &mut C, 1309 arg0: &ProducesFlags, 1310 arg1: &ConsumesFlags, 1311 ) -> Option<Reg> { 1312 let pattern0_0 = arg0; 1313 let pattern1_0 = arg1; 1314 // Rule at src/prelude.isle line 575. 1315 let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?; 1316 let expr1_0: usize = 0; 1317 let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); 1318 return Some(expr2_0); 1319 } 1320 1321 // Generated as internal constructor for term operand_size. 1322 pub fn constructor_operand_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> { 1323 let pattern0_0 = arg0; 1324 if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) { 1325 // Rule at src/isa/aarch64/inst.isle line 878. 1326 let expr0_0 = OperandSize::Size32; 1327 return Some(expr0_0); 1328 } 1329 if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) { 1330 // Rule at src/isa/aarch64/inst.isle line 879. 1331 let expr0_0 = OperandSize::Size64; 1332 return Some(expr0_0); 1333 } 1334 return None; 1335 } 1336 1337 // Generated as internal constructor for term vector_size. 1338 pub fn constructor_vector_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<VectorSize> { 1339 let pattern0_0 = arg0; 1340 if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) { 1341 if pattern1_0 == 8 { 1342 if pattern1_1 == 16 { 1343 // Rule at src/isa/aarch64/inst.isle line 921. 1344 let expr0_0 = VectorSize::Size8x16; 1345 return Some(expr0_0); 1346 } 1347 } 1348 if pattern1_0 == 16 { 1349 if pattern1_1 == 8 { 1350 // Rule at src/isa/aarch64/inst.isle line 922. 1351 let expr0_0 = VectorSize::Size16x8; 1352 return Some(expr0_0); 1353 } 1354 } 1355 if pattern1_0 == 32 { 1356 if pattern1_1 == 4 { 1357 // Rule at src/isa/aarch64/inst.isle line 923. 1358 let expr0_0 = VectorSize::Size32x4; 1359 return Some(expr0_0); 1360 } 1361 } 1362 if pattern1_0 == 64 { 1363 if pattern1_1 == 2 { 1364 // Rule at src/isa/aarch64/inst.isle line 924. 1365 let expr0_0 = VectorSize::Size64x2; 1366 return Some(expr0_0); 1367 } 1368 } 1369 } 1370 return None; 1371 } 1372 1373 // Generated as internal constructor for term mov64_to_real. 1374 pub fn constructor_mov64_to_real<C: Context>(ctx: &mut C, arg0: u8, arg1: Reg) -> Option<Reg> { 1375 let pattern0_0 = arg0; 1376 let pattern1_0 = arg1; 1377 // Rule at src/isa/aarch64/inst.isle line 1379. 1378 let expr0_0 = C::writable_xreg(ctx, pattern0_0); 1379 let expr1_0: Type = I64; 1380 let expr2_0 = constructor_operand_size(ctx, expr1_0)?; 1381 let expr3_0 = MInst::Mov { 1382 size: expr2_0, 1383 rd: expr0_0, 1384 rm: pattern1_0, 1385 }; 1386 let expr4_0 = C::emit(ctx, &expr3_0); 1387 let expr5_0 = C::writable_reg_to_reg(ctx, expr0_0); 1388 return Some(expr5_0); 1389 } 1390 1391 // Generated as internal constructor for term mov64_from_real. 1392 pub fn constructor_mov64_from_real<C: Context>(ctx: &mut C, arg0: u8) -> Option<Reg> { 1393 let pattern0_0 = arg0; 1394 // Rule at src/isa/aarch64/inst.isle line 1385. 1395 let expr0_0: Type = I64; 1396 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1397 let expr2_0: Type = I64; 1398 let expr3_0 = constructor_operand_size(ctx, expr2_0)?; 1399 let expr4_0 = C::xreg(ctx, pattern0_0); 1400 let expr5_0 = MInst::Mov { 1401 size: expr3_0, 1402 rd: expr1_0, 1403 rm: expr4_0, 1404 }; 1405 let expr6_0 = C::emit(ctx, &expr5_0); 1406 let expr7_0 = C::writable_reg_to_reg(ctx, expr1_0); 1407 return Some(expr7_0); 1408 } 1409 1410 // Generated as internal constructor for term movz. 1411 pub fn constructor_movz<C: Context>( 1412 ctx: &mut C, 1413 arg0: MoveWideConst, 1414 arg1: &OperandSize, 1415 ) -> Option<Reg> { 1416 let pattern0_0 = arg0; 1417 let pattern1_0 = arg1; 1418 // Rule at src/isa/aarch64/inst.isle line 1392. 1419 let expr0_0: Type = I64; 1420 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1421 let expr2_0 = MoveWideOp::MovZ; 1422 let expr3_0 = MInst::MovWide { 1423 op: expr2_0, 1424 rd: expr1_0, 1425 imm: pattern0_0, 1426 size: pattern1_0.clone(), 1427 }; 1428 let expr4_0 = C::emit(ctx, &expr3_0); 1429 let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); 1430 return Some(expr5_0); 1431 } 1432 1433 // Generated as internal constructor for term movn. 1434 pub fn constructor_movn<C: Context>( 1435 ctx: &mut C, 1436 arg0: MoveWideConst, 1437 arg1: &OperandSize, 1438 ) -> Option<Reg> { 1439 let pattern0_0 = arg0; 1440 let pattern1_0 = arg1; 1441 // Rule at src/isa/aarch64/inst.isle line 1399. 1442 let expr0_0: Type = I64; 1443 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1444 let expr2_0 = MoveWideOp::MovN; 1445 let expr3_0 = MInst::MovWide { 1446 op: expr2_0, 1447 rd: expr1_0, 1448 imm: pattern0_0, 1449 size: pattern1_0.clone(), 1450 }; 1451 let expr4_0 = C::emit(ctx, &expr3_0); 1452 let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); 1453 return Some(expr5_0); 1454 } 1455 1456 // Generated as internal constructor for term alu_rr_imm_logic. 1457 pub fn constructor_alu_rr_imm_logic<C: Context>( 1458 ctx: &mut C, 1459 arg0: &ALUOp, 1460 arg1: Type, 1461 arg2: Reg, 1462 arg3: ImmLogic, 1463 ) -> Option<Reg> { 1464 let pattern0_0 = arg0; 1465 let pattern1_0 = arg1; 1466 let pattern2_0 = arg2; 1467 let pattern3_0 = arg3; 1468 // Rule at src/isa/aarch64/inst.isle line 1406. 1469 let expr0_0: Type = I64; 1470 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1471 let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; 1472 let expr3_0 = MInst::AluRRImmLogic { 1473 alu_op: pattern0_0.clone(), 1474 size: expr2_0, 1475 rd: expr1_0, 1476 rn: pattern2_0, 1477 imml: pattern3_0, 1478 }; 1479 let expr4_0 = C::emit(ctx, &expr3_0); 1480 let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); 1481 return Some(expr5_0); 1482 } 1483 1484 // Generated as internal constructor for term alu_rr_imm_shift. 1485 pub fn constructor_alu_rr_imm_shift<C: Context>( 1486 ctx: &mut C, 1487 arg0: &ALUOp, 1488 arg1: Type, 1489 arg2: Reg, 1490 arg3: ImmShift, 1491 ) -> Option<Reg> { 1492 let pattern0_0 = arg0; 1493 let pattern1_0 = arg1; 1494 let pattern2_0 = arg2; 1495 let pattern3_0 = arg3; 1496 // Rule at src/isa/aarch64/inst.isle line 1413. 1497 let expr0_0: Type = I64; 1498 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1499 let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; 1500 let expr3_0 = MInst::AluRRImmShift { 1501 alu_op: pattern0_0.clone(), 1502 size: expr2_0, 1503 rd: expr1_0, 1504 rn: pattern2_0, 1505 immshift: pattern3_0, 1506 }; 1507 let expr4_0 = C::emit(ctx, &expr3_0); 1508 let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); 1509 return Some(expr5_0); 1510 } 1511 1512 // Generated as internal constructor for term alu_rrr. 1513 pub fn constructor_alu_rrr<C: Context>( 1514 ctx: &mut C, 1515 arg0: &ALUOp, 1516 arg1: Type, 1517 arg2: Reg, 1518 arg3: Reg, 1519 ) -> Option<Reg> { 1520 let pattern0_0 = arg0; 1521 let pattern1_0 = arg1; 1522 let pattern2_0 = arg2; 1523 let pattern3_0 = arg3; 1524 // Rule at src/isa/aarch64/inst.isle line 1420. 1525 let expr0_0: Type = I64; 1526 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1527 let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; 1528 let expr3_0 = MInst::AluRRR { 1529 alu_op: pattern0_0.clone(), 1530 size: expr2_0, 1531 rd: expr1_0, 1532 rn: pattern2_0, 1533 rm: pattern3_0, 1534 }; 1535 let expr4_0 = C::emit(ctx, &expr3_0); 1536 let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); 1537 return Some(expr5_0); 1538 } 1539 1540 // Generated as internal constructor for term vec_rrr. 1541 pub fn constructor_vec_rrr<C: Context>( 1542 ctx: &mut C, 1543 arg0: &VecALUOp, 1544 arg1: Reg, 1545 arg2: Reg, 1546 arg3: &VectorSize, 1547 ) -> Option<Reg> { 1548 let pattern0_0 = arg0; 1549 let pattern1_0 = arg1; 1550 let pattern2_0 = arg2; 1551 let pattern3_0 = arg3; 1552 // Rule at src/isa/aarch64/inst.isle line 1427. 1553 let expr0_0: Type = I8X16; 1554 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1555 let expr2_0 = MInst::VecRRR { 1556 alu_op: pattern0_0.clone(), 1557 rd: expr1_0, 1558 rn: pattern1_0, 1559 rm: pattern2_0, 1560 size: pattern3_0.clone(), 1561 }; 1562 let expr3_0 = C::emit(ctx, &expr2_0); 1563 let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); 1564 return Some(expr4_0); 1565 } 1566 1567 // Generated as internal constructor for term vec_lanes. 1568 pub fn constructor_vec_lanes<C: Context>( 1569 ctx: &mut C, 1570 arg0: &VecLanesOp, 1571 arg1: Reg, 1572 arg2: &VectorSize, 1573 ) -> Option<Reg> { 1574 let pattern0_0 = arg0; 1575 let pattern1_0 = arg1; 1576 let pattern2_0 = arg2; 1577 // Rule at src/isa/aarch64/inst.isle line 1434. 1578 let expr0_0: Type = I8X16; 1579 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1580 let expr2_0 = MInst::VecLanes { 1581 op: pattern0_0.clone(), 1582 rd: expr1_0, 1583 rn: pattern1_0, 1584 size: pattern2_0.clone(), 1585 }; 1586 let expr3_0 = C::emit(ctx, &expr2_0); 1587 let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); 1588 return Some(expr4_0); 1589 } 1590 1591 // Generated as internal constructor for term vec_dup. 1592 pub fn constructor_vec_dup<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> { 1593 let pattern0_0 = arg0; 1594 let pattern1_0 = arg1; 1595 // Rule at src/isa/aarch64/inst.isle line 1441. 1596 let expr0_0: Type = I8X16; 1597 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1598 let expr2_0 = MInst::VecDup { 1599 rd: expr1_0, 1600 rn: pattern0_0, 1601 size: pattern1_0.clone(), 1602 }; 1603 let expr3_0 = C::emit(ctx, &expr2_0); 1604 let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); 1605 return Some(expr4_0); 1606 } 1607 1608 // Generated as internal constructor for term alu_rr_imm12. 1609 pub fn constructor_alu_rr_imm12<C: Context>( 1610 ctx: &mut C, 1611 arg0: &ALUOp, 1612 arg1: Type, 1613 arg2: Reg, 1614 arg3: Imm12, 1615 ) -> Option<Reg> { 1616 let pattern0_0 = arg0; 1617 let pattern1_0 = arg1; 1618 let pattern2_0 = arg2; 1619 let pattern3_0 = arg3; 1620 // Rule at src/isa/aarch64/inst.isle line 1448. 1621 let expr0_0: Type = I64; 1622 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1623 let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; 1624 let expr3_0 = MInst::AluRRImm12 { 1625 alu_op: pattern0_0.clone(), 1626 size: expr2_0, 1627 rd: expr1_0, 1628 rn: pattern2_0, 1629 imm12: pattern3_0, 1630 }; 1631 let expr4_0 = C::emit(ctx, &expr3_0); 1632 let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); 1633 return Some(expr5_0); 1634 } 1635 1636 // Generated as internal constructor for term alu_rrr_shift. 1637 pub fn constructor_alu_rrr_shift<C: Context>( 1638 ctx: &mut C, 1639 arg0: &ALUOp, 1640 arg1: Type, 1641 arg2: Reg, 1642 arg3: Reg, 1643 arg4: ShiftOpAndAmt, 1644 ) -> Option<Reg> { 1645 let pattern0_0 = arg0; 1646 let pattern1_0 = arg1; 1647 let pattern2_0 = arg2; 1648 let pattern3_0 = arg3; 1649 let pattern4_0 = arg4; 1650 // Rule at src/isa/aarch64/inst.isle line 1455. 1651 let expr0_0: Type = I64; 1652 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1653 let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; 1654 let expr3_0 = MInst::AluRRRShift { 1655 alu_op: pattern0_0.clone(), 1656 size: expr2_0, 1657 rd: expr1_0, 1658 rn: pattern2_0, 1659 rm: pattern3_0, 1660 shiftop: pattern4_0, 1661 }; 1662 let expr4_0 = C::emit(ctx, &expr3_0); 1663 let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); 1664 return Some(expr5_0); 1665 } 1666 1667 // Generated as internal constructor for term alu_rrr_extend. 1668 pub fn constructor_alu_rrr_extend<C: Context>( 1669 ctx: &mut C, 1670 arg0: &ALUOp, 1671 arg1: Type, 1672 arg2: Reg, 1673 arg3: Reg, 1674 arg4: &ExtendOp, 1675 ) -> Option<Reg> { 1676 let pattern0_0 = arg0; 1677 let pattern1_0 = arg1; 1678 let pattern2_0 = arg2; 1679 let pattern3_0 = arg3; 1680 let pattern4_0 = arg4; 1681 // Rule at src/isa/aarch64/inst.isle line 1462. 1682 let expr0_0: Type = I64; 1683 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1684 let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; 1685 let expr3_0 = MInst::AluRRRExtend { 1686 alu_op: pattern0_0.clone(), 1687 size: expr2_0, 1688 rd: expr1_0, 1689 rn: pattern2_0, 1690 rm: pattern3_0, 1691 extendop: pattern4_0.clone(), 1692 }; 1693 let expr4_0 = C::emit(ctx, &expr3_0); 1694 let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); 1695 return Some(expr5_0); 1696 } 1697 1698 // Generated as internal constructor for term alu_rr_extend_reg. 1699 pub fn constructor_alu_rr_extend_reg<C: Context>( 1700 ctx: &mut C, 1701 arg0: &ALUOp, 1702 arg1: Type, 1703 arg2: Reg, 1704 arg3: &ExtendedValue, 1705 ) -> Option<Reg> { 1706 let pattern0_0 = arg0; 1707 let pattern1_0 = arg1; 1708 let pattern2_0 = arg2; 1709 let pattern3_0 = arg3; 1710 // Rule at src/isa/aarch64/inst.isle line 1470. 1711 let expr0_0 = C::put_extended_in_reg(ctx, pattern3_0); 1712 let expr1_0 = C::get_extended_op(ctx, pattern3_0); 1713 let expr2_0 = 1714 constructor_alu_rrr_extend(ctx, pattern0_0, pattern1_0, pattern2_0, expr0_0, &expr1_0)?; 1715 return Some(expr2_0); 1716 } 1717 1718 // Generated as internal constructor for term alu_rrrr. 1719 pub fn constructor_alu_rrrr<C: Context>( 1720 ctx: &mut C, 1721 arg0: &ALUOp3, 1722 arg1: Type, 1723 arg2: Reg, 1724 arg3: Reg, 1725 arg4: Reg, 1726 ) -> Option<Reg> { 1727 let pattern0_0 = arg0; 1728 let pattern1_0 = arg1; 1729 let pattern2_0 = arg2; 1730 let pattern3_0 = arg3; 1731 let pattern4_0 = arg4; 1732 // Rule at src/isa/aarch64/inst.isle line 1477. 1733 let expr0_0: Type = I64; 1734 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1735 let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; 1736 let expr3_0 = MInst::AluRRRR { 1737 alu_op: pattern0_0.clone(), 1738 size: expr2_0, 1739 rd: expr1_0, 1740 rn: pattern2_0, 1741 rm: pattern3_0, 1742 ra: pattern4_0, 1743 }; 1744 let expr4_0 = C::emit(ctx, &expr3_0); 1745 let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); 1746 return Some(expr5_0); 1747 } 1748 1749 // Generated as internal constructor for term bit_rr. 1750 pub fn constructor_bit_rr<C: Context>( 1751 ctx: &mut C, 1752 arg0: &BitOp, 1753 arg1: Type, 1754 arg2: Reg, 1755 ) -> Option<Reg> { 1756 let pattern0_0 = arg0; 1757 let pattern1_0 = arg1; 1758 let pattern2_0 = arg2; 1759 // Rule at src/isa/aarch64/inst.isle line 1484. 1760 let expr0_0: Type = I64; 1761 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1762 let expr2_0 = constructor_operand_size(ctx, pattern1_0)?; 1763 let expr3_0 = MInst::BitRR { 1764 op: pattern0_0.clone(), 1765 size: expr2_0, 1766 rd: expr1_0, 1767 rn: pattern2_0, 1768 }; 1769 let expr4_0 = C::emit(ctx, &expr3_0); 1770 let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); 1771 return Some(expr5_0); 1772 } 1773 1774 // Generated as internal constructor for term add_with_flags_paired. 1775 pub fn constructor_add_with_flags_paired<C: Context>( 1776 ctx: &mut C, 1777 arg0: Type, 1778 arg1: Reg, 1779 arg2: Reg, 1780 ) -> Option<ProducesFlags> { 1781 let pattern0_0 = arg0; 1782 let pattern1_0 = arg1; 1783 let pattern2_0 = arg2; 1784 // Rule at src/isa/aarch64/inst.isle line 1491. 1785 let expr0_0: Type = I64; 1786 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1787 let expr2_0 = ALUOp::AddS; 1788 let expr3_0 = constructor_operand_size(ctx, pattern0_0)?; 1789 let expr4_0 = MInst::AluRRR { 1790 alu_op: expr2_0, 1791 size: expr3_0, 1792 rd: expr1_0, 1793 rn: pattern1_0, 1794 rm: pattern2_0, 1795 }; 1796 let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); 1797 let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer { 1798 inst: expr4_0, 1799 result: expr5_0, 1800 }; 1801 return Some(expr6_0); 1802 } 1803 1804 // Generated as internal constructor for term adc_paired. 1805 pub fn constructor_adc_paired<C: Context>( 1806 ctx: &mut C, 1807 arg0: Type, 1808 arg1: Reg, 1809 arg2: Reg, 1810 ) -> Option<ConsumesFlags> { 1811 let pattern0_0 = arg0; 1812 let pattern1_0 = arg1; 1813 let pattern2_0 = arg2; 1814 // Rule at src/isa/aarch64/inst.isle line 1499. 1815 let expr0_0: Type = I64; 1816 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1817 let expr2_0 = ALUOp::Adc; 1818 let expr3_0 = constructor_operand_size(ctx, pattern0_0)?; 1819 let expr4_0 = MInst::AluRRR { 1820 alu_op: expr2_0, 1821 size: expr3_0, 1822 rd: expr1_0, 1823 rn: pattern1_0, 1824 rm: pattern2_0, 1825 }; 1826 let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); 1827 let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer { 1828 inst: expr4_0, 1829 result: expr5_0, 1830 }; 1831 return Some(expr6_0); 1832 } 1833 1834 // Generated as internal constructor for term sub_with_flags_paired. 1835 pub fn constructor_sub_with_flags_paired<C: Context>( 1836 ctx: &mut C, 1837 arg0: Type, 1838 arg1: Reg, 1839 arg2: Reg, 1840 ) -> Option<ProducesFlags> { 1841 let pattern0_0 = arg0; 1842 let pattern1_0 = arg1; 1843 let pattern2_0 = arg2; 1844 // Rule at src/isa/aarch64/inst.isle line 1507. 1845 let expr0_0: Type = I64; 1846 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1847 let expr2_0 = ALUOp::SubS; 1848 let expr3_0 = constructor_operand_size(ctx, pattern0_0)?; 1849 let expr4_0 = MInst::AluRRR { 1850 alu_op: expr2_0, 1851 size: expr3_0, 1852 rd: expr1_0, 1853 rn: pattern1_0, 1854 rm: pattern2_0, 1855 }; 1856 let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); 1857 let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer { 1858 inst: expr4_0, 1859 result: expr5_0, 1860 }; 1861 return Some(expr6_0); 1862 } 1863 1864 // Generated as internal constructor for term cmp64_imm. 1865 pub fn constructor_cmp64_imm<C: Context>( 1866 ctx: &mut C, 1867 arg0: Reg, 1868 arg1: Imm12, 1869 ) -> Option<ProducesFlags> { 1870 let pattern0_0 = arg0; 1871 let pattern1_0 = arg1; 1872 // Rule at src/isa/aarch64/inst.isle line 1514. 1873 let expr0_0 = ALUOp::SubS; 1874 let expr1_0 = OperandSize::Size64; 1875 let expr2_0 = C::writable_zero_reg(ctx); 1876 let expr3_0 = MInst::AluRRImm12 { 1877 alu_op: expr0_0, 1878 size: expr1_0, 1879 rd: expr2_0, 1880 rn: pattern0_0, 1881 imm12: pattern1_0, 1882 }; 1883 let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 }; 1884 return Some(expr4_0); 1885 } 1886 1887 // Generated as internal constructor for term sbc_paired. 1888 pub fn constructor_sbc_paired<C: Context>( 1889 ctx: &mut C, 1890 arg0: Type, 1891 arg1: Reg, 1892 arg2: Reg, 1893 ) -> Option<ConsumesFlags> { 1894 let pattern0_0 = arg0; 1895 let pattern1_0 = arg1; 1896 let pattern2_0 = arg2; 1897 // Rule at src/isa/aarch64/inst.isle line 1521. 1898 let expr0_0: Type = I64; 1899 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1900 let expr2_0 = ALUOp::Sbc; 1901 let expr3_0 = constructor_operand_size(ctx, pattern0_0)?; 1902 let expr4_0 = MInst::AluRRR { 1903 alu_op: expr2_0, 1904 size: expr3_0, 1905 rd: expr1_0, 1906 rn: pattern1_0, 1907 rm: pattern2_0, 1908 }; 1909 let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0); 1910 let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer { 1911 inst: expr4_0, 1912 result: expr5_0, 1913 }; 1914 return Some(expr6_0); 1915 } 1916 1917 // Generated as internal constructor for term vec_misc. 1918 pub fn constructor_vec_misc<C: Context>( 1919 ctx: &mut C, 1920 arg0: &VecMisc2, 1921 arg1: Reg, 1922 arg2: &VectorSize, 1923 ) -> Option<Reg> { 1924 let pattern0_0 = arg0; 1925 let pattern1_0 = arg1; 1926 let pattern2_0 = arg2; 1927 // Rule at src/isa/aarch64/inst.isle line 1529. 1928 let expr0_0: Type = I8X16; 1929 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1930 let expr2_0 = MInst::VecMisc { 1931 op: pattern0_0.clone(), 1932 rd: expr1_0, 1933 rn: pattern1_0, 1934 size: pattern2_0.clone(), 1935 }; 1936 let expr3_0 = C::emit(ctx, &expr2_0); 1937 let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); 1938 return Some(expr4_0); 1939 } 1940 1941 // Generated as internal constructor for term vec_rrr_long. 1942 pub fn constructor_vec_rrr_long<C: Context>( 1943 ctx: &mut C, 1944 arg0: &VecRRRLongOp, 1945 arg1: Reg, 1946 arg2: Reg, 1947 arg3: bool, 1948 ) -> Option<Reg> { 1949 let pattern0_0 = arg0; 1950 let pattern1_0 = arg1; 1951 let pattern2_0 = arg2; 1952 let pattern3_0 = arg3; 1953 // Rule at src/isa/aarch64/inst.isle line 1536. 1954 let expr0_0: Type = I8X16; 1955 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1956 let expr2_0 = MInst::VecRRRLong { 1957 alu_op: pattern0_0.clone(), 1958 rd: expr1_0, 1959 rn: pattern1_0, 1960 rm: pattern2_0, 1961 high_half: pattern3_0, 1962 }; 1963 let expr3_0 = C::emit(ctx, &expr2_0); 1964 let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); 1965 return Some(expr4_0); 1966 } 1967 1968 // Generated as internal constructor for term vec_rrrr_long. 1969 pub fn constructor_vec_rrrr_long<C: Context>( 1970 ctx: &mut C, 1971 arg0: &VecRRRLongOp, 1972 arg1: Reg, 1973 arg2: Reg, 1974 arg3: Reg, 1975 arg4: bool, 1976 ) -> Option<Reg> { 1977 let pattern0_0 = arg0; 1978 let pattern1_0 = arg1; 1979 let pattern2_0 = arg2; 1980 let pattern3_0 = arg3; 1981 let pattern4_0 = arg4; 1982 // Rule at src/isa/aarch64/inst.isle line 1546. 1983 let expr0_0: Type = I8X16; 1984 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 1985 let expr2_0 = MInst::FpuMove128 { 1986 rd: expr1_0, 1987 rn: pattern1_0, 1988 }; 1989 let expr3_0 = C::emit(ctx, &expr2_0); 1990 let expr4_0 = MInst::VecRRRLong { 1991 alu_op: pattern0_0.clone(), 1992 rd: expr1_0, 1993 rn: pattern2_0, 1994 rm: pattern3_0, 1995 high_half: pattern4_0, 1996 }; 1997 let expr5_0 = C::emit(ctx, &expr4_0); 1998 let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0); 1999 return Some(expr6_0); 2000 } 2001 2002 // Generated as internal constructor for term vec_rr_narrow. 2003 pub fn constructor_vec_rr_narrow<C: Context>( 2004 ctx: &mut C, 2005 arg0: &VecRRNarrowOp, 2006 arg1: Reg, 2007 arg2: bool, 2008 ) -> Option<Reg> { 2009 let pattern0_0 = arg0; 2010 let pattern1_0 = arg1; 2011 let pattern2_0 = arg2; 2012 // Rule at src/isa/aarch64/inst.isle line 1554. 2013 let expr0_0: Type = I8X16; 2014 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 2015 let expr2_0 = MInst::VecRRNarrow { 2016 op: pattern0_0.clone(), 2017 rd: expr1_0, 2018 rn: pattern1_0, 2019 high_half: pattern2_0, 2020 }; 2021 let expr3_0 = C::emit(ctx, &expr2_0); 2022 let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); 2023 return Some(expr4_0); 2024 } 2025 2026 // Generated as internal constructor for term vec_rr_long. 2027 pub fn constructor_vec_rr_long<C: Context>( 2028 ctx: &mut C, 2029 arg0: &VecRRLongOp, 2030 arg1: Reg, 2031 arg2: bool, 2032 ) -> Option<Reg> { 2033 let pattern0_0 = arg0; 2034 let pattern1_0 = arg1; 2035 let pattern2_0 = arg2; 2036 // Rule at src/isa/aarch64/inst.isle line 1561. 2037 let expr0_0: Type = I8X16; 2038 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 2039 let expr2_0 = MInst::VecRRLong { 2040 op: pattern0_0.clone(), 2041 rd: expr1_0, 2042 rn: pattern1_0, 2043 high_half: pattern2_0, 2044 }; 2045 let expr3_0 = C::emit(ctx, &expr2_0); 2046 let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); 2047 return Some(expr4_0); 2048 } 2049 2050 // Generated as internal constructor for term mov_to_fpu. 2051 pub fn constructor_mov_to_fpu<C: Context>( 2052 ctx: &mut C, 2053 arg0: Reg, 2054 arg1: &ScalarSize, 2055 ) -> Option<Reg> { 2056 let pattern0_0 = arg0; 2057 let pattern1_0 = arg1; 2058 // Rule at src/isa/aarch64/inst.isle line 1568. 2059 let expr0_0: Type = I8X16; 2060 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 2061 let expr2_0 = MInst::MovToFpu { 2062 rd: expr1_0, 2063 rn: pattern0_0, 2064 size: pattern1_0.clone(), 2065 }; 2066 let expr3_0 = C::emit(ctx, &expr2_0); 2067 let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); 2068 return Some(expr4_0); 2069 } 2070 2071 // Generated as internal constructor for term mov_to_vec. 2072 pub fn constructor_mov_to_vec<C: Context>( 2073 ctx: &mut C, 2074 arg0: Reg, 2075 arg1: Reg, 2076 arg2: u8, 2077 arg3: &VectorSize, 2078 ) -> Option<Reg> { 2079 let pattern0_0 = arg0; 2080 let pattern1_0 = arg1; 2081 let pattern2_0 = arg2; 2082 let pattern3_0 = arg3; 2083 // Rule at src/isa/aarch64/inst.isle line 1575. 2084 let expr0_0: Type = I8X16; 2085 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 2086 let expr2_0 = MInst::FpuMove128 { 2087 rd: expr1_0, 2088 rn: pattern0_0, 2089 }; 2090 let expr3_0 = C::emit(ctx, &expr2_0); 2091 let expr4_0 = MInst::MovToVec { 2092 rd: expr1_0, 2093 rn: pattern1_0, 2094 idx: pattern2_0, 2095 size: pattern3_0.clone(), 2096 }; 2097 let expr5_0 = C::emit(ctx, &expr4_0); 2098 let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0); 2099 return Some(expr6_0); 2100 } 2101 2102 // Generated as internal constructor for term mov_from_vec. 2103 pub fn constructor_mov_from_vec<C: Context>( 2104 ctx: &mut C, 2105 arg0: Reg, 2106 arg1: u8, 2107 arg2: &VectorSize, 2108 ) -> Option<Reg> { 2109 let pattern0_0 = arg0; 2110 let pattern1_0 = arg1; 2111 let pattern2_0 = arg2; 2112 // Rule at src/isa/aarch64/inst.isle line 1583. 2113 let expr0_0: Type = I64; 2114 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 2115 let expr2_0 = MInst::MovFromVec { 2116 rd: expr1_0, 2117 rn: pattern0_0, 2118 idx: pattern1_0, 2119 size: pattern2_0.clone(), 2120 }; 2121 let expr3_0 = C::emit(ctx, &expr2_0); 2122 let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); 2123 return Some(expr4_0); 2124 } 2125 2126 // Generated as internal constructor for term mov_from_vec_signed. 2127 pub fn constructor_mov_from_vec_signed<C: Context>( 2128 ctx: &mut C, 2129 arg0: Reg, 2130 arg1: u8, 2131 arg2: &VectorSize, 2132 arg3: &OperandSize, 2133 ) -> Option<Reg> { 2134 let pattern0_0 = arg0; 2135 let pattern1_0 = arg1; 2136 let pattern2_0 = arg2; 2137 let pattern3_0 = arg3; 2138 // Rule at src/isa/aarch64/inst.isle line 1590. 2139 let expr0_0: Type = I64; 2140 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 2141 let expr2_0 = MInst::MovFromVecSigned { 2142 rd: expr1_0, 2143 rn: pattern0_0, 2144 idx: pattern1_0, 2145 size: pattern2_0.clone(), 2146 scalar_size: pattern3_0.clone(), 2147 }; 2148 let expr3_0 = C::emit(ctx, &expr2_0); 2149 let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); 2150 return Some(expr4_0); 2151 } 2152 2153 // Generated as internal constructor for term extend. 2154 pub fn constructor_extend<C: Context>( 2155 ctx: &mut C, 2156 arg0: Reg, 2157 arg1: bool, 2158 arg2: u8, 2159 arg3: u8, 2160 ) -> Option<Reg> { 2161 let pattern0_0 = arg0; 2162 let pattern1_0 = arg1; 2163 let pattern2_0 = arg2; 2164 let pattern3_0 = arg3; 2165 // Rule at src/isa/aarch64/inst.isle line 1597. 2166 let expr0_0: Type = I64; 2167 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 2168 let expr2_0 = MInst::Extend { 2169 rd: expr1_0, 2170 rn: pattern0_0, 2171 signed: pattern1_0, 2172 from_bits: pattern2_0, 2173 to_bits: pattern3_0, 2174 }; 2175 let expr3_0 = C::emit(ctx, &expr2_0); 2176 let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); 2177 return Some(expr4_0); 2178 } 2179 2180 // Generated as internal constructor for term load_acquire. 2181 pub fn constructor_load_acquire<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> { 2182 let pattern0_0 = arg0; 2183 let pattern1_0 = arg1; 2184 // Rule at src/isa/aarch64/inst.isle line 1604. 2185 let expr0_0: Type = I64; 2186 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 2187 let expr2_0 = MInst::LoadAcquire { 2188 access_ty: pattern0_0, 2189 rt: expr1_0, 2190 rn: pattern1_0, 2191 }; 2192 let expr3_0 = C::emit(ctx, &expr2_0); 2193 let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); 2194 return Some(expr4_0); 2195 } 2196 2197 // Generated as internal constructor for term tst_imm. 2198 pub fn constructor_tst_imm<C: Context>( 2199 ctx: &mut C, 2200 arg0: Type, 2201 arg1: Reg, 2202 arg2: ImmLogic, 2203 ) -> Option<ProducesFlags> { 2204 let pattern0_0 = arg0; 2205 let pattern1_0 = arg1; 2206 let pattern2_0 = arg2; 2207 // Rule at src/isa/aarch64/inst.isle line 1614. 2208 let expr0_0 = ALUOp::AndS; 2209 let expr1_0 = constructor_operand_size(ctx, pattern0_0)?; 2210 let expr2_0 = C::writable_zero_reg(ctx); 2211 let expr3_0 = MInst::AluRRImmLogic { 2212 alu_op: expr0_0, 2213 size: expr1_0, 2214 rd: expr2_0, 2215 rn: pattern1_0, 2216 imml: pattern2_0, 2217 }; 2218 let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 }; 2219 return Some(expr4_0); 2220 } 2221 2222 // Generated as internal constructor for term csel. 2223 pub fn constructor_csel<C: Context>( 2224 ctx: &mut C, 2225 arg0: &Cond, 2226 arg1: Reg, 2227 arg2: Reg, 2228 ) -> Option<ConsumesFlags> { 2229 let pattern0_0 = arg0; 2230 let pattern1_0 = arg1; 2231 let pattern2_0 = arg2; 2232 // Rule at src/isa/aarch64/inst.isle line 1628. 2233 let expr0_0: Type = I64; 2234 let expr1_0 = C::temp_writable_reg(ctx, expr0_0); 2235 let expr2_0 = MInst::CSel { 2236 rd: expr1_0, 2237 cond: pattern0_0.clone(), 2238 rn: pattern1_0, 2239 rm: pattern2_0, 2240 }; 2241 let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0); 2242 let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg { 2243 inst: expr2_0, 2244 result: expr3_0, 2245 }; 2246 return Some(expr4_0); 2247 } 2248 2249 // Generated as internal constructor for term add. 2250 pub fn constructor_add<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> { 2251 let pattern0_0 = arg0; 2252 let pattern1_0 = arg1; 2253 let pattern2_0 = arg2; 2254 // Rule at src/isa/aarch64/inst.isle line 1637. 2255 let expr0_0 = ALUOp::Add; 2256 let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2257 return Some(expr1_0); 2258 } 2259 2260 // Generated as internal constructor for term add_imm. 2261 pub fn constructor_add_imm<C: Context>( 2262 ctx: &mut C, 2263 arg0: Type, 2264 arg1: Reg, 2265 arg2: Imm12, 2266 ) -> Option<Reg> { 2267 let pattern0_0 = arg0; 2268 let pattern1_0 = arg1; 2269 let pattern2_0 = arg2; 2270 // Rule at src/isa/aarch64/inst.isle line 1640. 2271 let expr0_0 = ALUOp::Add; 2272 let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2273 return Some(expr1_0); 2274 } 2275 2276 // Generated as internal constructor for term add_extend. 2277 pub fn constructor_add_extend<C: Context>( 2278 ctx: &mut C, 2279 arg0: Type, 2280 arg1: Reg, 2281 arg2: &ExtendedValue, 2282 ) -> Option<Reg> { 2283 let pattern0_0 = arg0; 2284 let pattern1_0 = arg1; 2285 let pattern2_0 = arg2; 2286 // Rule at src/isa/aarch64/inst.isle line 1643. 2287 let expr0_0 = ALUOp::Add; 2288 let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2289 return Some(expr1_0); 2290 } 2291 2292 // Generated as internal constructor for term add_shift. 2293 pub fn constructor_add_shift<C: Context>( 2294 ctx: &mut C, 2295 arg0: Type, 2296 arg1: Reg, 2297 arg2: Reg, 2298 arg3: ShiftOpAndAmt, 2299 ) -> Option<Reg> { 2300 let pattern0_0 = arg0; 2301 let pattern1_0 = arg1; 2302 let pattern2_0 = arg2; 2303 let pattern3_0 = arg3; 2304 // Rule at src/isa/aarch64/inst.isle line 1646. 2305 let expr0_0 = ALUOp::Add; 2306 let expr1_0 = constructor_alu_rrr_shift( 2307 ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0, 2308 )?; 2309 return Some(expr1_0); 2310 } 2311 2312 // Generated as internal constructor for term add_vec. 2313 pub fn constructor_add_vec<C: Context>( 2314 ctx: &mut C, 2315 arg0: Reg, 2316 arg1: Reg, 2317 arg2: &VectorSize, 2318 ) -> Option<Reg> { 2319 let pattern0_0 = arg0; 2320 let pattern1_0 = arg1; 2321 let pattern2_0 = arg2; 2322 // Rule at src/isa/aarch64/inst.isle line 1649. 2323 let expr0_0 = VecALUOp::Add; 2324 let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2325 return Some(expr1_0); 2326 } 2327 2328 // Generated as internal constructor for term sub. 2329 pub fn constructor_sub<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> { 2330 let pattern0_0 = arg0; 2331 let pattern1_0 = arg1; 2332 let pattern2_0 = arg2; 2333 // Rule at src/isa/aarch64/inst.isle line 1654. 2334 let expr0_0 = ALUOp::Sub; 2335 let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2336 return Some(expr1_0); 2337 } 2338 2339 // Generated as internal constructor for term sub_imm. 2340 pub fn constructor_sub_imm<C: Context>( 2341 ctx: &mut C, 2342 arg0: Type, 2343 arg1: Reg, 2344 arg2: Imm12, 2345 ) -> Option<Reg> { 2346 let pattern0_0 = arg0; 2347 let pattern1_0 = arg1; 2348 let pattern2_0 = arg2; 2349 // Rule at src/isa/aarch64/inst.isle line 1657. 2350 let expr0_0 = ALUOp::Sub; 2351 let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2352 return Some(expr1_0); 2353 } 2354 2355 // Generated as internal constructor for term sub_extend. 2356 pub fn constructor_sub_extend<C: Context>( 2357 ctx: &mut C, 2358 arg0: Type, 2359 arg1: Reg, 2360 arg2: &ExtendedValue, 2361 ) -> Option<Reg> { 2362 let pattern0_0 = arg0; 2363 let pattern1_0 = arg1; 2364 let pattern2_0 = arg2; 2365 // Rule at src/isa/aarch64/inst.isle line 1660. 2366 let expr0_0 = ALUOp::Sub; 2367 let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2368 return Some(expr1_0); 2369 } 2370 2371 // Generated as internal constructor for term sub_shift. 2372 pub fn constructor_sub_shift<C: Context>( 2373 ctx: &mut C, 2374 arg0: Type, 2375 arg1: Reg, 2376 arg2: Reg, 2377 arg3: ShiftOpAndAmt, 2378 ) -> Option<Reg> { 2379 let pattern0_0 = arg0; 2380 let pattern1_0 = arg1; 2381 let pattern2_0 = arg2; 2382 let pattern3_0 = arg3; 2383 // Rule at src/isa/aarch64/inst.isle line 1663. 2384 let expr0_0 = ALUOp::Sub; 2385 let expr1_0 = constructor_alu_rrr_shift( 2386 ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0, 2387 )?; 2388 return Some(expr1_0); 2389 } 2390 2391 // Generated as internal constructor for term sub_vec. 2392 pub fn constructor_sub_vec<C: Context>( 2393 ctx: &mut C, 2394 arg0: Reg, 2395 arg1: Reg, 2396 arg2: &VectorSize, 2397 ) -> Option<Reg> { 2398 let pattern0_0 = arg0; 2399 let pattern1_0 = arg1; 2400 let pattern2_0 = arg2; 2401 // Rule at src/isa/aarch64/inst.isle line 1666. 2402 let expr0_0 = VecALUOp::Sub; 2403 let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2404 return Some(expr1_0); 2405 } 2406 2407 // Generated as internal constructor for term madd. 2408 pub fn constructor_madd<C: Context>( 2409 ctx: &mut C, 2410 arg0: Type, 2411 arg1: Reg, 2412 arg2: Reg, 2413 arg3: Reg, 2414 ) -> Option<Reg> { 2415 let pattern0_0 = arg0; 2416 let pattern1_0 = arg1; 2417 let pattern2_0 = arg2; 2418 let pattern3_0 = arg3; 2419 // Rule at src/isa/aarch64/inst.isle line 1671. 2420 let expr0_0 = ALUOp3::MAdd; 2421 let expr1_0 = constructor_alu_rrrr( 2422 ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0, 2423 )?; 2424 return Some(expr1_0); 2425 } 2426 2427 // Generated as internal constructor for term msub. 2428 pub fn constructor_msub<C: Context>( 2429 ctx: &mut C, 2430 arg0: Type, 2431 arg1: Reg, 2432 arg2: Reg, 2433 arg3: Reg, 2434 ) -> Option<Reg> { 2435 let pattern0_0 = arg0; 2436 let pattern1_0 = arg1; 2437 let pattern2_0 = arg2; 2438 let pattern3_0 = arg3; 2439 // Rule at src/isa/aarch64/inst.isle line 1676. 2440 let expr0_0 = ALUOp3::MSub; 2441 let expr1_0 = constructor_alu_rrrr( 2442 ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0, 2443 )?; 2444 return Some(expr1_0); 2445 } 2446 2447 // Generated as internal constructor for term uqadd. 2448 pub fn constructor_uqadd<C: Context>( 2449 ctx: &mut C, 2450 arg0: Reg, 2451 arg1: Reg, 2452 arg2: &VectorSize, 2453 ) -> Option<Reg> { 2454 let pattern0_0 = arg0; 2455 let pattern1_0 = arg1; 2456 let pattern2_0 = arg2; 2457 // Rule at src/isa/aarch64/inst.isle line 1680. 2458 let expr0_0 = VecALUOp::Uqadd; 2459 let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2460 return Some(expr1_0); 2461 } 2462 2463 // Generated as internal constructor for term sqadd. 2464 pub fn constructor_sqadd<C: Context>( 2465 ctx: &mut C, 2466 arg0: Reg, 2467 arg1: Reg, 2468 arg2: &VectorSize, 2469 ) -> Option<Reg> { 2470 let pattern0_0 = arg0; 2471 let pattern1_0 = arg1; 2472 let pattern2_0 = arg2; 2473 // Rule at src/isa/aarch64/inst.isle line 1684. 2474 let expr0_0 = VecALUOp::Sqadd; 2475 let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2476 return Some(expr1_0); 2477 } 2478 2479 // Generated as internal constructor for term uqsub. 2480 pub fn constructor_uqsub<C: Context>( 2481 ctx: &mut C, 2482 arg0: Reg, 2483 arg1: Reg, 2484 arg2: &VectorSize, 2485 ) -> Option<Reg> { 2486 let pattern0_0 = arg0; 2487 let pattern1_0 = arg1; 2488 let pattern2_0 = arg2; 2489 // Rule at src/isa/aarch64/inst.isle line 1688. 2490 let expr0_0 = VecALUOp::Uqsub; 2491 let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2492 return Some(expr1_0); 2493 } 2494 2495 // Generated as internal constructor for term sqsub. 2496 pub fn constructor_sqsub<C: Context>( 2497 ctx: &mut C, 2498 arg0: Reg, 2499 arg1: Reg, 2500 arg2: &VectorSize, 2501 ) -> Option<Reg> { 2502 let pattern0_0 = arg0; 2503 let pattern1_0 = arg1; 2504 let pattern2_0 = arg2; 2505 // Rule at src/isa/aarch64/inst.isle line 1692. 2506 let expr0_0 = VecALUOp::Sqsub; 2507 let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2508 return Some(expr1_0); 2509 } 2510 2511 // Generated as internal constructor for term umulh. 2512 pub fn constructor_umulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> { 2513 let pattern0_0 = arg0; 2514 let pattern1_0 = arg1; 2515 let pattern2_0 = arg2; 2516 // Rule at src/isa/aarch64/inst.isle line 1696. 2517 let expr0_0 = ALUOp::UMulH; 2518 let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2519 return Some(expr1_0); 2520 } 2521 2522 // Generated as internal constructor for term smulh. 2523 pub fn constructor_smulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> { 2524 let pattern0_0 = arg0; 2525 let pattern1_0 = arg1; 2526 let pattern2_0 = arg2; 2527 // Rule at src/isa/aarch64/inst.isle line 1700. 2528 let expr0_0 = ALUOp::SMulH; 2529 let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2530 return Some(expr1_0); 2531 } 2532 2533 // Generated as internal constructor for term mul. 2534 pub fn constructor_mul<C: Context>( 2535 ctx: &mut C, 2536 arg0: Reg, 2537 arg1: Reg, 2538 arg2: &VectorSize, 2539 ) -> Option<Reg> { 2540 let pattern0_0 = arg0; 2541 let pattern1_0 = arg1; 2542 let pattern2_0 = arg2; 2543 // Rule at src/isa/aarch64/inst.isle line 1704. 2544 let expr0_0 = VecALUOp::Mul; 2545 let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2546 return Some(expr1_0); 2547 } 2548 2549 // Generated as internal constructor for term neg. 2550 pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> { 2551 let pattern0_0 = arg0; 2552 let pattern1_0 = arg1; 2553 // Rule at src/isa/aarch64/inst.isle line 1708. 2554 let expr0_0 = VecMisc2::Neg; 2555 let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?; 2556 return Some(expr1_0); 2557 } 2558 2559 // Generated as internal constructor for term rev64. 2560 pub fn constructor_rev64<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> { 2561 let pattern0_0 = arg0; 2562 let pattern1_0 = arg1; 2563 // Rule at src/isa/aarch64/inst.isle line 1712. 2564 let expr0_0 = VecMisc2::Rev64; 2565 let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?; 2566 return Some(expr1_0); 2567 } 2568 2569 // Generated as internal constructor for term xtn64. 2570 pub fn constructor_xtn64<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> { 2571 let pattern0_0 = arg0; 2572 let pattern1_0 = arg1; 2573 // Rule at src/isa/aarch64/inst.isle line 1716. 2574 let expr0_0 = VecRRNarrowOp::Xtn64; 2575 let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?; 2576 return Some(expr1_0); 2577 } 2578 2579 // Generated as internal constructor for term addp. 2580 pub fn constructor_addp<C: Context>( 2581 ctx: &mut C, 2582 arg0: Reg, 2583 arg1: Reg, 2584 arg2: &VectorSize, 2585 ) -> Option<Reg> { 2586 let pattern0_0 = arg0; 2587 let pattern1_0 = arg1; 2588 let pattern2_0 = arg2; 2589 // Rule at src/isa/aarch64/inst.isle line 1720. 2590 let expr0_0 = VecALUOp::Addp; 2591 let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2592 return Some(expr1_0); 2593 } 2594 2595 // Generated as internal constructor for term addv. 2596 pub fn constructor_addv<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> { 2597 let pattern0_0 = arg0; 2598 let pattern1_0 = arg1; 2599 // Rule at src/isa/aarch64/inst.isle line 1724. 2600 let expr0_0 = VecLanesOp::Addv; 2601 let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?; 2602 return Some(expr1_0); 2603 } 2604 2605 // Generated as internal constructor for term shll32. 2606 pub fn constructor_shll32<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> { 2607 let pattern0_0 = arg0; 2608 let pattern1_0 = arg1; 2609 // Rule at src/isa/aarch64/inst.isle line 1728. 2610 let expr0_0 = VecRRLongOp::Shll32; 2611 let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?; 2612 return Some(expr1_0); 2613 } 2614 2615 // Generated as internal constructor for term umlal32. 2616 pub fn constructor_umlal32<C: Context>( 2617 ctx: &mut C, 2618 arg0: Reg, 2619 arg1: Reg, 2620 arg2: Reg, 2621 arg3: bool, 2622 ) -> Option<Reg> { 2623 let pattern0_0 = arg0; 2624 let pattern1_0 = arg1; 2625 let pattern2_0 = arg2; 2626 let pattern3_0 = arg3; 2627 // Rule at src/isa/aarch64/inst.isle line 1732. 2628 let expr0_0 = VecRRRLongOp::Umlal32; 2629 let expr1_0 = constructor_vec_rrrr_long( 2630 ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0, 2631 )?; 2632 return Some(expr1_0); 2633 } 2634 2635 // Generated as internal constructor for term smull8. 2636 pub fn constructor_smull8<C: Context>( 2637 ctx: &mut C, 2638 arg0: Reg, 2639 arg1: Reg, 2640 arg2: bool, 2641 ) -> Option<Reg> { 2642 let pattern0_0 = arg0; 2643 let pattern1_0 = arg1; 2644 let pattern2_0 = arg2; 2645 // Rule at src/isa/aarch64/inst.isle line 1736. 2646 let expr0_0 = VecRRRLongOp::Smull8; 2647 let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2648 return Some(expr1_0); 2649 } 2650 2651 // Generated as internal constructor for term umull8. 2652 pub fn constructor_umull8<C: Context>( 2653 ctx: &mut C, 2654 arg0: Reg, 2655 arg1: Reg, 2656 arg2: bool, 2657 ) -> Option<Reg> { 2658 let pattern0_0 = arg0; 2659 let pattern1_0 = arg1; 2660 let pattern2_0 = arg2; 2661 // Rule at src/isa/aarch64/inst.isle line 1740. 2662 let expr0_0 = VecRRRLongOp::Umull8; 2663 let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2664 return Some(expr1_0); 2665 } 2666 2667 // Generated as internal constructor for term smull16. 2668 pub fn constructor_smull16<C: Context>( 2669 ctx: &mut C, 2670 arg0: Reg, 2671 arg1: Reg, 2672 arg2: bool, 2673 ) -> Option<Reg> { 2674 let pattern0_0 = arg0; 2675 let pattern1_0 = arg1; 2676 let pattern2_0 = arg2; 2677 // Rule at src/isa/aarch64/inst.isle line 1744. 2678 let expr0_0 = VecRRRLongOp::Smull16; 2679 let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2680 return Some(expr1_0); 2681 } 2682 2683 // Generated as internal constructor for term umull16. 2684 pub fn constructor_umull16<C: Context>( 2685 ctx: &mut C, 2686 arg0: Reg, 2687 arg1: Reg, 2688 arg2: bool, 2689 ) -> Option<Reg> { 2690 let pattern0_0 = arg0; 2691 let pattern1_0 = arg1; 2692 let pattern2_0 = arg2; 2693 // Rule at src/isa/aarch64/inst.isle line 1748. 2694 let expr0_0 = VecRRRLongOp::Umull16; 2695 let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2696 return Some(expr1_0); 2697 } 2698 2699 // Generated as internal constructor for term smull32. 2700 pub fn constructor_smull32<C: Context>( 2701 ctx: &mut C, 2702 arg0: Reg, 2703 arg1: Reg, 2704 arg2: bool, 2705 ) -> Option<Reg> { 2706 let pattern0_0 = arg0; 2707 let pattern1_0 = arg1; 2708 let pattern2_0 = arg2; 2709 // Rule at src/isa/aarch64/inst.isle line 1752. 2710 let expr0_0 = VecRRRLongOp::Smull32; 2711 let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2712 return Some(expr1_0); 2713 } 2714 2715 // Generated as internal constructor for term umull32. 2716 pub fn constructor_umull32<C: Context>( 2717 ctx: &mut C, 2718 arg0: Reg, 2719 arg1: Reg, 2720 arg2: bool, 2721 ) -> Option<Reg> { 2722 let pattern0_0 = arg0; 2723 let pattern1_0 = arg1; 2724 let pattern2_0 = arg2; 2725 // Rule at src/isa/aarch64/inst.isle line 1756. 2726 let expr0_0 = VecRRRLongOp::Umull32; 2727 let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2728 return Some(expr1_0); 2729 } 2730 2731 // Generated as internal constructor for term asr. 2732 pub fn constructor_asr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> { 2733 let pattern0_0 = arg0; 2734 let pattern1_0 = arg1; 2735 let pattern2_0 = arg2; 2736 // Rule at src/isa/aarch64/inst.isle line 1760. 2737 let expr0_0 = ALUOp::Asr; 2738 let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2739 return Some(expr1_0); 2740 } 2741 2742 // Generated as internal constructor for term asr_imm. 2743 pub fn constructor_asr_imm<C: Context>( 2744 ctx: &mut C, 2745 arg0: Type, 2746 arg1: Reg, 2747 arg2: ImmShift, 2748 ) -> Option<Reg> { 2749 let pattern0_0 = arg0; 2750 let pattern1_0 = arg1; 2751 let pattern2_0 = arg2; 2752 // Rule at src/isa/aarch64/inst.isle line 1763. 2753 let expr0_0 = ALUOp::Asr; 2754 let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2755 return Some(expr1_0); 2756 } 2757 2758 // Generated as internal constructor for term lsr. 2759 pub fn constructor_lsr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> { 2760 let pattern0_0 = arg0; 2761 let pattern1_0 = arg1; 2762 let pattern2_0 = arg2; 2763 // Rule at src/isa/aarch64/inst.isle line 1767. 2764 let expr0_0 = ALUOp::Lsr; 2765 let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2766 return Some(expr1_0); 2767 } 2768 2769 // Generated as internal constructor for term lsr_imm. 2770 pub fn constructor_lsr_imm<C: Context>( 2771 ctx: &mut C, 2772 arg0: Type, 2773 arg1: Reg, 2774 arg2: ImmShift, 2775 ) -> Option<Reg> { 2776 let pattern0_0 = arg0; 2777 let pattern1_0 = arg1; 2778 let pattern2_0 = arg2; 2779 // Rule at src/isa/aarch64/inst.isle line 1770. 2780 let expr0_0 = ALUOp::Lsr; 2781 let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2782 return Some(expr1_0); 2783 } 2784 2785 // Generated as internal constructor for term lsl. 2786 pub fn constructor_lsl<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> { 2787 let pattern0_0 = arg0; 2788 let pattern1_0 = arg1; 2789 let pattern2_0 = arg2; 2790 // Rule at src/isa/aarch64/inst.isle line 1774. 2791 let expr0_0 = ALUOp::Lsl; 2792 let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2793 return Some(expr1_0); 2794 } 2795 2796 // Generated as internal constructor for term lsl_imm. 2797 pub fn constructor_lsl_imm<C: Context>( 2798 ctx: &mut C, 2799 arg0: Type, 2800 arg1: Reg, 2801 arg2: ImmShift, 2802 ) -> Option<Reg> { 2803 let pattern0_0 = arg0; 2804 let pattern1_0 = arg1; 2805 let pattern2_0 = arg2; 2806 // Rule at src/isa/aarch64/inst.isle line 1777. 2807 let expr0_0 = ALUOp::Lsl; 2808 let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2809 return Some(expr1_0); 2810 } 2811 2812 // Generated as internal constructor for term a64_udiv. 2813 pub fn constructor_a64_udiv<C: Context>( 2814 ctx: &mut C, 2815 arg0: Type, 2816 arg1: Reg, 2817 arg2: Reg, 2818 ) -> Option<Reg> { 2819 let pattern0_0 = arg0; 2820 let pattern1_0 = arg1; 2821 let pattern2_0 = arg2; 2822 // Rule at src/isa/aarch64/inst.isle line 1781. 2823 let expr0_0 = ALUOp::UDiv; 2824 let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2825 return Some(expr1_0); 2826 } 2827 2828 // Generated as internal constructor for term a64_sdiv. 2829 pub fn constructor_a64_sdiv<C: Context>( 2830 ctx: &mut C, 2831 arg0: Type, 2832 arg1: Reg, 2833 arg2: Reg, 2834 ) -> Option<Reg> { 2835 let pattern0_0 = arg0; 2836 let pattern1_0 = arg1; 2837 let pattern2_0 = arg2; 2838 // Rule at src/isa/aarch64/inst.isle line 1785. 2839 let expr0_0 = ALUOp::SDiv; 2840 let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2841 return Some(expr1_0); 2842 } 2843 2844 // Generated as internal constructor for term not. 2845 pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> { 2846 let pattern0_0 = arg0; 2847 let pattern1_0 = arg1; 2848 // Rule at src/isa/aarch64/inst.isle line 1789. 2849 let expr0_0 = VecMisc2::Not; 2850 let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?; 2851 return Some(expr1_0); 2852 } 2853 2854 // Generated as internal constructor for term orr_not. 2855 pub fn constructor_orr_not<C: Context>( 2856 ctx: &mut C, 2857 arg0: Type, 2858 arg1: Reg, 2859 arg2: Reg, 2860 ) -> Option<Reg> { 2861 let pattern0_0 = arg0; 2862 let pattern1_0 = arg1; 2863 let pattern2_0 = arg2; 2864 // Rule at src/isa/aarch64/inst.isle line 1794. 2865 let expr0_0 = ALUOp::OrrNot; 2866 let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2867 return Some(expr1_0); 2868 } 2869 2870 // Generated as internal constructor for term orr_not_shift. 2871 pub fn constructor_orr_not_shift<C: Context>( 2872 ctx: &mut C, 2873 arg0: Type, 2874 arg1: Reg, 2875 arg2: Reg, 2876 arg3: ShiftOpAndAmt, 2877 ) -> Option<Reg> { 2878 let pattern0_0 = arg0; 2879 let pattern1_0 = arg1; 2880 let pattern2_0 = arg2; 2881 let pattern3_0 = arg3; 2882 // Rule at src/isa/aarch64/inst.isle line 1797. 2883 let expr0_0 = ALUOp::OrrNot; 2884 let expr1_0 = constructor_alu_rrr_shift( 2885 ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0, 2886 )?; 2887 return Some(expr1_0); 2888 } 2889 2890 // Generated as internal constructor for term orr. 2891 pub fn constructor_orr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> { 2892 let pattern0_0 = arg0; 2893 let pattern1_0 = arg1; 2894 let pattern2_0 = arg2; 2895 // Rule at src/isa/aarch64/inst.isle line 1802. 2896 let expr0_0 = ALUOp::Orr; 2897 let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2898 return Some(expr1_0); 2899 } 2900 2901 // Generated as internal constructor for term orr_imm. 2902 pub fn constructor_orr_imm<C: Context>( 2903 ctx: &mut C, 2904 arg0: Type, 2905 arg1: Reg, 2906 arg2: ImmLogic, 2907 ) -> Option<Reg> { 2908 let pattern0_0 = arg0; 2909 let pattern1_0 = arg1; 2910 let pattern2_0 = arg2; 2911 // Rule at src/isa/aarch64/inst.isle line 1805. 2912 let expr0_0 = ALUOp::Orr; 2913 let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2914 return Some(expr1_0); 2915 } 2916 2917 // Generated as internal constructor for term orr_vec. 2918 pub fn constructor_orr_vec<C: Context>( 2919 ctx: &mut C, 2920 arg0: Reg, 2921 arg1: Reg, 2922 arg2: &VectorSize, 2923 ) -> Option<Reg> { 2924 let pattern0_0 = arg0; 2925 let pattern1_0 = arg1; 2926 let pattern2_0 = arg2; 2927 // Rule at src/isa/aarch64/inst.isle line 1808. 2928 let expr0_0 = VecALUOp::Orr; 2929 let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2930 return Some(expr1_0); 2931 } 2932 2933 // Generated as internal constructor for term and_imm. 2934 pub fn constructor_and_imm<C: Context>( 2935 ctx: &mut C, 2936 arg0: Type, 2937 arg1: Reg, 2938 arg2: ImmLogic, 2939 ) -> Option<Reg> { 2940 let pattern0_0 = arg0; 2941 let pattern1_0 = arg1; 2942 let pattern2_0 = arg2; 2943 // Rule at src/isa/aarch64/inst.isle line 1813. 2944 let expr0_0 = ALUOp::And; 2945 let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2946 return Some(expr1_0); 2947 } 2948 2949 // Generated as internal constructor for term and_vec. 2950 pub fn constructor_and_vec<C: Context>( 2951 ctx: &mut C, 2952 arg0: Reg, 2953 arg1: Reg, 2954 arg2: &VectorSize, 2955 ) -> Option<Reg> { 2956 let pattern0_0 = arg0; 2957 let pattern1_0 = arg1; 2958 let pattern2_0 = arg2; 2959 // Rule at src/isa/aarch64/inst.isle line 1816. 2960 let expr0_0 = VecALUOp::And; 2961 let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2962 return Some(expr1_0); 2963 } 2964 2965 // Generated as internal constructor for term eor_vec. 2966 pub fn constructor_eor_vec<C: Context>( 2967 ctx: &mut C, 2968 arg0: Reg, 2969 arg1: Reg, 2970 arg2: &VectorSize, 2971 ) -> Option<Reg> { 2972 let pattern0_0 = arg0; 2973 let pattern1_0 = arg1; 2974 let pattern2_0 = arg2; 2975 // Rule at src/isa/aarch64/inst.isle line 1820. 2976 let expr0_0 = VecALUOp::Eor; 2977 let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2978 return Some(expr1_0); 2979 } 2980 2981 // Generated as internal constructor for term bic_vec. 2982 pub fn constructor_bic_vec<C: Context>( 2983 ctx: &mut C, 2984 arg0: Reg, 2985 arg1: Reg, 2986 arg2: &VectorSize, 2987 ) -> Option<Reg> { 2988 let pattern0_0 = arg0; 2989 let pattern1_0 = arg1; 2990 let pattern2_0 = arg2; 2991 // Rule at src/isa/aarch64/inst.isle line 1824. 2992 let expr0_0 = VecALUOp::Bic; 2993 let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 2994 return Some(expr1_0); 2995 } 2996 2997 // Generated as internal constructor for term sshl. 2998 pub fn constructor_sshl<C: Context>( 2999 ctx: &mut C, 3000 arg0: Reg, 3001 arg1: Reg, 3002 arg2: &VectorSize, 3003 ) -> Option<Reg> { 3004 let pattern0_0 = arg0; 3005 let pattern1_0 = arg1; 3006 let pattern2_0 = arg2; 3007 // Rule at src/isa/aarch64/inst.isle line 1828. 3008 let expr0_0 = VecALUOp::Sshl; 3009 let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 3010 return Some(expr1_0); 3011 } 3012 3013 // Generated as internal constructor for term ushl. 3014 pub fn constructor_ushl<C: Context>( 3015 ctx: &mut C, 3016 arg0: Reg, 3017 arg1: Reg, 3018 arg2: &VectorSize, 3019 ) -> Option<Reg> { 3020 let pattern0_0 = arg0; 3021 let pattern1_0 = arg1; 3022 let pattern2_0 = arg2; 3023 // Rule at src/isa/aarch64/inst.isle line 1832. 3024 let expr0_0 = VecALUOp::Ushl; 3025 let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 3026 return Some(expr1_0); 3027 } 3028 3029 // Generated as internal constructor for term a64_rotr. 3030 pub fn constructor_a64_rotr<C: Context>( 3031 ctx: &mut C, 3032 arg0: Type, 3033 arg1: Reg, 3034 arg2: Reg, 3035 ) -> Option<Reg> { 3036 let pattern0_0 = arg0; 3037 let pattern1_0 = arg1; 3038 let pattern2_0 = arg2; 3039 // Rule at src/isa/aarch64/inst.isle line 1837. 3040 let expr0_0 = ALUOp::RotR; 3041 let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 3042 return Some(expr1_0); 3043 } 3044 3045 // Generated as internal constructor for term a64_rotr_imm. 3046 pub fn constructor_a64_rotr_imm<C: Context>( 3047 ctx: &mut C, 3048 arg0: Type, 3049 arg1: Reg, 3050 arg2: ImmShift, 3051 ) -> Option<Reg> { 3052 let pattern0_0 = arg0; 3053 let pattern1_0 = arg1; 3054 let pattern2_0 = arg2; 3055 // Rule at src/isa/aarch64/inst.isle line 1840. 3056 let expr0_0 = ALUOp::RotR; 3057 let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 3058 return Some(expr1_0); 3059 } 3060 3061 // Generated as internal constructor for term rbit. 3062 pub fn constructor_rbit<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> { 3063 let pattern0_0 = arg0; 3064 let pattern1_0 = arg1; 3065 // Rule at src/isa/aarch64/inst.isle line 1845. 3066 let expr0_0 = BitOp::RBit; 3067 let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?; 3068 return Some(expr1_0); 3069 } 3070 3071 // Generated as internal constructor for term a64_clz. 3072 pub fn constructor_a64_clz<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> { 3073 let pattern0_0 = arg0; 3074 let pattern1_0 = arg1; 3075 // Rule at src/isa/aarch64/inst.isle line 1850. 3076 let expr0_0 = BitOp::Clz; 3077 let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?; 3078 return Some(expr1_0); 3079 } 3080 3081 // Generated as internal constructor for term a64_cls. 3082 pub fn constructor_a64_cls<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> { 3083 let pattern0_0 = arg0; 3084 let pattern1_0 = arg1; 3085 // Rule at src/isa/aarch64/inst.isle line 1855. 3086 let expr0_0 = BitOp::Cls; 3087 let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?; 3088 return Some(expr1_0); 3089 } 3090 3091 // Generated as internal constructor for term eon. 3092 pub fn constructor_eon<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> { 3093 let pattern0_0 = arg0; 3094 let pattern1_0 = arg1; 3095 let pattern2_0 = arg2; 3096 // Rule at src/isa/aarch64/inst.isle line 1860. 3097 let expr0_0 = ALUOp::EorNot; 3098 let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?; 3099 return Some(expr1_0); 3100 } 3101 3102 // Generated as internal constructor for term vec_cnt. 3103 pub fn constructor_vec_cnt<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> { 3104 let pattern0_0 = arg0; 3105 let pattern1_0 = arg1; 3106 // Rule at src/isa/aarch64/inst.isle line 1865. 3107 let expr0_0 = VecMisc2::Cnt; 3108 let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?; 3109 return Some(expr1_0); 3110 } 3111 3112 // Generated as internal constructor for term imm. 3113 pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> { 3114 let pattern0_0 = arg0; 3115 if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) { 3116 let pattern2_0 = arg1; 3117 let mut closure3 = || { 3118 let expr0_0: Type = I64; 3119 let expr1_0 = C::imm_logic_from_u64(ctx, expr0_0, pattern2_0)?; 3120 return Some(expr1_0); 3121 }; 3122 if let Some(pattern3_0) = closure3() { 3123 // Rule at src/isa/aarch64/inst.isle line 1880. 3124 let expr0_0: Type = I64; 3125 let expr1_0 = C::zero_reg(ctx); 3126 let expr2_0 = constructor_orr_imm(ctx, expr0_0, expr1_0, pattern3_0)?; 3127 return Some(expr2_0); 3128 } 3129 if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) { 3130 // Rule at src/isa/aarch64/inst.isle line 1872. 3131 let expr0_0 = OperandSize::Size64; 3132 let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?; 3133 return Some(expr1_0); 3134 } 3135 if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) { 3136 // Rule at src/isa/aarch64/inst.isle line 1876. 3137 let expr0_0 = OperandSize::Size64; 3138 let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?; 3139 return Some(expr1_0); 3140 } 3141 // Rule at src/isa/aarch64/inst.isle line 1888. 3142 let expr0_0 = C::load_constant64_full(ctx, pattern2_0); 3143 return Some(expr0_0); 3144 } 3145 return None; 3146 } 3147 3148 // Generated as internal constructor for term put_in_reg_sext32. 3149 pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> { 3150 let pattern0_0 = arg0; 3151 let pattern1_0 = C::value_type(ctx, pattern0_0); 3152 if pattern1_0 == I32 { 3153 // Rule at src/isa/aarch64/inst.isle line 1899. 3154 let expr0_0 = C::put_in_reg(ctx, pattern0_0); 3155 return Some(expr0_0); 3156 } 3157 if pattern1_0 == I64 { 3158 // Rule at src/isa/aarch64/inst.isle line 1900. 3159 let expr0_0 = C::put_in_reg(ctx, pattern0_0); 3160 return Some(expr0_0); 3161 } 3162 if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) { 3163 // Rule at src/isa/aarch64/inst.isle line 1895. 3164 let expr0_0 = C::put_in_reg(ctx, pattern0_0); 3165 let expr1_0: bool = true; 3166 let expr2_0 = C::ty_bits(ctx, pattern2_0)?; 3167 let expr3_0: u8 = 32; 3168 let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?; 3169 return Some(expr4_0); 3170 } 3171 return None; 3172 } 3173 3174 // Generated as internal constructor for term put_in_reg_zext32. 3175 pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> { 3176 let pattern0_0 = arg0; 3177 let pattern1_0 = C::value_type(ctx, pattern0_0); 3178 if pattern1_0 == I32 { 3179 // Rule at src/isa/aarch64/inst.isle line 1908. 3180 let expr0_0 = C::put_in_reg(ctx, pattern0_0); 3181 return Some(expr0_0); 3182 } 3183 if pattern1_0 == I64 { 3184 // Rule at src/isa/aarch64/inst.isle line 1909. 3185 let expr0_0 = C::put_in_reg(ctx, pattern0_0); 3186 return Some(expr0_0); 3187 } 3188 if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) { 3189 // Rule at src/isa/aarch64/inst.isle line 1904. 3190 let expr0_0 = C::put_in_reg(ctx, pattern0_0); 3191 let expr1_0: bool = false; 3192 let expr2_0 = C::ty_bits(ctx, pattern2_0)?; 3193 let expr3_0: u8 = 32; 3194 let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?; 3195 return Some(expr4_0); 3196 } 3197 return None; 3198 } 3199 3200 // Generated as internal constructor for term put_in_reg_sext64. 3201 pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> { 3202 let pattern0_0 = arg0; 3203 let pattern1_0 = C::value_type(ctx, pattern0_0); 3204 if pattern1_0 == I64 { 3205 // Rule at src/isa/aarch64/inst.isle line 1917. 3206 let expr0_0 = C::put_in_reg(ctx, pattern0_0); 3207 return Some(expr0_0); 3208 } 3209 if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) { 3210 // Rule at src/isa/aarch64/inst.isle line 1913. 3211 let expr0_0 = C::put_in_reg(ctx, pattern0_0); 3212 let expr1_0: bool = true; 3213 let expr2_0 = C::ty_bits(ctx, pattern2_0)?; 3214 let expr3_0: u8 = 64; 3215 let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?; 3216 return Some(expr4_0); 3217 } 3218 return None; 3219 } 3220 3221 // Generated as internal constructor for term put_in_reg_zext64. 3222 pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> { 3223 let pattern0_0 = arg0; 3224 let pattern1_0 = C::value_type(ctx, pattern0_0); 3225 if pattern1_0 == I64 { 3226 // Rule at src/isa/aarch64/inst.isle line 1925. 3227 let expr0_0 = C::put_in_reg(ctx, pattern0_0); 3228 return Some(expr0_0); 3229 } 3230 if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) { 3231 // Rule at src/isa/aarch64/inst.isle line 1921. 3232 let expr0_0 = C::put_in_reg(ctx, pattern0_0); 3233 let expr1_0: bool = false; 3234 let expr2_0 = C::ty_bits(ctx, pattern2_0)?; 3235 let expr3_0: u8 = 64; 3236 let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?; 3237 return Some(expr4_0); 3238 } 3239 return None; 3240 } 3241 3242 // Generated as internal constructor for term trap_if_zero_divisor. 3243 pub fn constructor_trap_if_zero_divisor<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> { 3244 let pattern0_0 = arg0; 3245 // Rule at src/isa/aarch64/inst.isle line 1930. 3246 let expr0_0 = C::cond_br_zero(ctx, pattern0_0); 3247 let expr1_0 = C::trap_code_division_by_zero(ctx); 3248 let expr2_0 = MInst::TrapIf { 3249 kind: expr0_0, 3250 trap_code: expr1_0, 3251 }; 3252 let expr3_0 = C::emit(ctx, &expr2_0); 3253 return Some(pattern0_0); 3254 } 3255 3256 // Generated as internal constructor for term size_from_ty. 3257 pub fn constructor_size_from_ty<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> { 3258 let pattern0_0 = arg0; 3259 if pattern0_0 == I64 { 3260 // Rule at src/isa/aarch64/inst.isle line 1936. 3261 let expr0_0 = OperandSize::Size64; 3262 return Some(expr0_0); 3263 } 3264 if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) { 3265 // Rule at src/isa/aarch64/inst.isle line 1935. 3266 let expr0_0 = OperandSize::Size32; 3267 return Some(expr0_0); 3268 } 3269 return None; 3270 } 3271 3272 // Generated as internal constructor for term trap_if_div_overflow. 3273 pub fn constructor_trap_if_div_overflow<C: Context>( 3274 ctx: &mut C, 3275 arg0: Type, 3276 arg1: Reg, 3277 arg2: Reg, 3278 ) -> Option<Reg> { 3279 let pattern0_0 = arg0; 3280 let pattern1_0 = arg1; 3281 let pattern2_0 = arg2; 3282 // Rule at src/isa/aarch64/inst.isle line 1942. 3283 let expr0_0 = ALUOp::AddS; 3284 let expr1_0 = constructor_operand_size(ctx, pattern0_0)?; 3285 let expr2_0 = C::writable_zero_reg(ctx); 3286 let expr3_0: u8 = 1; 3287 let expr4_0 = C::u8_into_imm12(ctx, expr3_0); 3288 let expr5_0 = MInst::AluRRImm12 { 3289 alu_op: expr0_0, 3290 size: expr1_0, 3291 rd: expr2_0, 3292 rn: pattern2_0, 3293 imm12: expr4_0, 3294 }; 3295 let expr6_0 = C::emit(ctx, &expr5_0); 3296 let expr7_0 = constructor_size_from_ty(ctx, pattern0_0)?; 3297 let expr8_0: u8 = 1; 3298 let expr9_0 = C::u8_into_uimm5(ctx, expr8_0); 3299 let expr10_0: bool = false; 3300 let expr11_0: bool = false; 3301 let expr12_0: bool = false; 3302 let expr13_0: bool = false; 3303 let expr14_0 = C::nzcv(ctx, expr10_0, expr11_0, expr12_0, expr13_0); 3304 let expr15_0 = Cond::Eq; 3305 let expr16_0 = MInst::CCmpImm { 3306 size: expr7_0, 3307 rn: pattern1_0, 3308 imm: expr9_0, 3309 nzcv: expr14_0, 3310 cond: expr15_0, 3311 }; 3312 let expr17_0 = C::emit(ctx, &expr16_0); 3313 let expr18_0 = Cond::Vs; 3314 let expr19_0 = C::cond_br_cond(ctx, &expr18_0); 3315 let expr20_0 = C::trap_code_integer_overflow(ctx); 3316 let expr21_0 = MInst::TrapIf { 3317 kind: expr19_0, 3318 trap_code: expr20_0, 3319 }; 3320 let expr22_0 = C::emit(ctx, &expr21_0); 3321 return Some(pattern1_0); 3322 } 3323 3324 // Generated as internal constructor for term alu_rs_imm_logic_commutative. 3325 pub fn constructor_alu_rs_imm_logic_commutative<C: Context>( 3326 ctx: &mut C, 3327 arg0: &ALUOp, 3328 arg1: Type, 3329 arg2: Value, 3330 arg3: Value, 3331 ) -> Option<Reg> { 3332 let pattern0_0 = arg0; 3333 let pattern1_0 = arg1; 3334 let pattern2_0 = arg2; 3335 if let Some(pattern3_0) = C::def_inst(ctx, pattern2_0) { 3336 let pattern4_0 = C::inst_data(ctx, pattern3_0); 3337 match &pattern4_0 { 3338 &InstructionData::UnaryImm { 3339 opcode: ref pattern5_0, 3340 imm: pattern5_1, 3341 } => { 3342 if let &Opcode::Iconst = pattern5_0 { 3343 let pattern7_0 = arg3; 3344 let mut closure8 = || { 3345 let expr0_0 = C::imm_logic_from_imm64(ctx, pattern1_0, pattern5_1)?; 3346 return Some(expr0_0); 3347 }; 3348 if let Some(pattern8_0) = closure8() { 3349 // Rule at src/isa/aarch64/inst.isle line 1988. 3350 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 3351 let expr1_0 = constructor_alu_rr_imm_logic( 3352 ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0, 3353 )?; 3354 return Some(expr1_0); 3355 } 3356 } 3357 } 3358 &InstructionData::Binary { 3359 opcode: ref pattern5_0, 3360 args: ref pattern5_1, 3361 } => { 3362 if let &Opcode::Ishl = pattern5_0 { 3363 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 3364 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { 3365 let pattern9_0 = C::inst_data(ctx, pattern8_0); 3366 if let &InstructionData::UnaryImm { 3367 opcode: ref pattern10_0, 3368 imm: pattern10_1, 3369 } = &pattern9_0 3370 { 3371 if let &Opcode::Iconst = pattern10_0 { 3372 let pattern12_0 = arg3; 3373 let mut closure13 = || { 3374 let expr0_0 = C::lshl_from_imm64(ctx, pattern1_0, pattern10_1)?; 3375 return Some(expr0_0); 3376 }; 3377 if let Some(pattern13_0) = closure13() { 3378 // Rule at src/isa/aarch64/inst.isle line 1996. 3379 let expr0_0 = C::put_in_reg(ctx, pattern12_0); 3380 let expr1_0 = C::put_in_reg(ctx, pattern7_0); 3381 let expr2_0 = constructor_alu_rrr_shift( 3382 ctx, 3383 pattern0_0, 3384 pattern1_0, 3385 expr0_0, 3386 expr1_0, 3387 pattern13_0, 3388 )?; 3389 return Some(expr2_0); 3390 } 3391 } 3392 } 3393 } 3394 } 3395 } 3396 _ => {} 3397 } 3398 } 3399 let pattern3_0 = arg3; 3400 if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) { 3401 let pattern5_0 = C::inst_data(ctx, pattern4_0); 3402 match &pattern5_0 { 3403 &InstructionData::UnaryImm { 3404 opcode: ref pattern6_0, 3405 imm: pattern6_1, 3406 } => { 3407 if let &Opcode::Iconst = pattern6_0 { 3408 let mut closure8 = || { 3409 let expr0_0 = C::imm_logic_from_imm64(ctx, pattern1_0, pattern6_1)?; 3410 return Some(expr0_0); 3411 }; 3412 if let Some(pattern8_0) = closure8() { 3413 // Rule at src/isa/aarch64/inst.isle line 1985. 3414 let expr0_0 = C::put_in_reg(ctx, pattern2_0); 3415 let expr1_0 = constructor_alu_rr_imm_logic( 3416 ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0, 3417 )?; 3418 return Some(expr1_0); 3419 } 3420 } 3421 } 3422 &InstructionData::Binary { 3423 opcode: ref pattern6_0, 3424 args: ref pattern6_1, 3425 } => { 3426 if let &Opcode::Ishl = pattern6_0 { 3427 let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1); 3428 if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) { 3429 let pattern10_0 = C::inst_data(ctx, pattern9_0); 3430 if let &InstructionData::UnaryImm { 3431 opcode: ref pattern11_0, 3432 imm: pattern11_1, 3433 } = &pattern10_0 3434 { 3435 if let &Opcode::Iconst = pattern11_0 { 3436 let mut closure13 = || { 3437 let expr0_0 = C::lshl_from_imm64(ctx, pattern1_0, pattern11_1)?; 3438 return Some(expr0_0); 3439 }; 3440 if let Some(pattern13_0) = closure13() { 3441 // Rule at src/isa/aarch64/inst.isle line 1993. 3442 let expr0_0 = C::put_in_reg(ctx, pattern2_0); 3443 let expr1_0 = C::put_in_reg(ctx, pattern8_0); 3444 let expr2_0 = constructor_alu_rrr_shift( 3445 ctx, 3446 pattern0_0, 3447 pattern1_0, 3448 expr0_0, 3449 expr1_0, 3450 pattern13_0, 3451 )?; 3452 return Some(expr2_0); 3453 } 3454 } 3455 } 3456 } 3457 } 3458 } 3459 _ => {} 3460 } 3461 } 3462 // Rule at src/isa/aarch64/inst.isle line 1981. 3463 let expr0_0 = C::put_in_reg(ctx, pattern2_0); 3464 let expr1_0 = C::put_in_reg(ctx, pattern3_0); 3465 let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?; 3466 return Some(expr2_0); 3467 } 3468 3469 // Generated as internal constructor for term alu_rs_imm_logic. 3470 pub fn constructor_alu_rs_imm_logic<C: Context>( 3471 ctx: &mut C, 3472 arg0: &ALUOp, 3473 arg1: Type, 3474 arg2: Value, 3475 arg3: Value, 3476 ) -> Option<Reg> { 3477 let pattern0_0 = arg0; 3478 let pattern1_0 = arg1; 3479 let pattern2_0 = arg2; 3480 let pattern3_0 = arg3; 3481 if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) { 3482 let pattern5_0 = C::inst_data(ctx, pattern4_0); 3483 match &pattern5_0 { 3484 &InstructionData::UnaryImm { 3485 opcode: ref pattern6_0, 3486 imm: pattern6_1, 3487 } => { 3488 if let &Opcode::Iconst = pattern6_0 { 3489 let mut closure8 = || { 3490 let expr0_0 = C::imm_logic_from_imm64(ctx, pattern1_0, pattern6_1)?; 3491 return Some(expr0_0); 3492 }; 3493 if let Some(pattern8_0) = closure8() { 3494 // Rule at src/isa/aarch64/inst.isle line 2005. 3495 let expr0_0 = C::put_in_reg(ctx, pattern2_0); 3496 let expr1_0 = constructor_alu_rr_imm_logic( 3497 ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0, 3498 )?; 3499 return Some(expr1_0); 3500 } 3501 } 3502 } 3503 &InstructionData::Binary { 3504 opcode: ref pattern6_0, 3505 args: ref pattern6_1, 3506 } => { 3507 if let &Opcode::Ishl = pattern6_0 { 3508 let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1); 3509 if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) { 3510 let pattern10_0 = C::inst_data(ctx, pattern9_0); 3511 if let &InstructionData::UnaryImm { 3512 opcode: ref pattern11_0, 3513 imm: pattern11_1, 3514 } = &pattern10_0 3515 { 3516 if let &Opcode::Iconst = pattern11_0 { 3517 let mut closure13 = || { 3518 let expr0_0 = C::lshl_from_imm64(ctx, pattern1_0, pattern11_1)?; 3519 return Some(expr0_0); 3520 }; 3521 if let Some(pattern13_0) = closure13() { 3522 // Rule at src/isa/aarch64/inst.isle line 2008. 3523 let expr0_0 = C::put_in_reg(ctx, pattern2_0); 3524 let expr1_0 = C::put_in_reg(ctx, pattern8_0); 3525 let expr2_0 = constructor_alu_rrr_shift( 3526 ctx, 3527 pattern0_0, 3528 pattern1_0, 3529 expr0_0, 3530 expr1_0, 3531 pattern13_0, 3532 )?; 3533 return Some(expr2_0); 3534 } 3535 } 3536 } 3537 } 3538 } 3539 } 3540 _ => {} 3541 } 3542 } 3543 // Rule at src/isa/aarch64/inst.isle line 2003. 3544 let expr0_0 = C::put_in_reg(ctx, pattern2_0); 3545 let expr1_0 = C::put_in_reg(ctx, pattern3_0); 3546 let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?; 3547 return Some(expr2_0); 3548 } 3549 3550 // Generated as internal constructor for term i128_alu_bitop. 3551 pub fn constructor_i128_alu_bitop<C: Context>( 3552 ctx: &mut C, 3553 arg0: &ALUOp, 3554 arg1: Type, 3555 arg2: Value, 3556 arg3: Value, 3557 ) -> Option<ValueRegs> { 3558 let pattern0_0 = arg0; 3559 let pattern1_0 = arg1; 3560 let pattern2_0 = arg2; 3561 let pattern3_0 = arg3; 3562 // Rule at src/isa/aarch64/inst.isle line 2017. 3563 let expr0_0 = C::put_in_regs(ctx, pattern2_0); 3564 let expr1_0: usize = 0; 3565 let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); 3566 let expr3_0: usize = 1; 3567 let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0); 3568 let expr5_0 = C::put_in_regs(ctx, pattern3_0); 3569 let expr6_0: usize = 0; 3570 let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0); 3571 let expr8_0: usize = 1; 3572 let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0); 3573 let expr10_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr2_0, expr7_0)?; 3574 let expr11_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr4_0, expr9_0)?; 3575 let expr12_0 = C::value_regs(ctx, expr10_0, expr11_0); 3576 return Some(expr12_0); 3577 } 3578 3579 // Generated as internal constructor for term float_cmp_zero. 3580 pub fn constructor_float_cmp_zero<C: Context>( 3581 ctx: &mut C, 3582 arg0: &FloatCC, 3583 arg1: Reg, 3584 arg2: &VectorSize, 3585 ) -> Option<Reg> { 3586 let pattern0_0 = arg0; 3587 let pattern1_0 = arg1; 3588 let pattern2_0 = arg2; 3589 // Rule at src/isa/aarch64/inst.isle line 2057. 3590 let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0); 3591 let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?; 3592 return Some(expr1_0); 3593 } 3594 3595 // Generated as internal constructor for term float_cmp_zero_swap. 3596 pub fn constructor_float_cmp_zero_swap<C: Context>( 3597 ctx: &mut C, 3598 arg0: &FloatCC, 3599 arg1: Reg, 3600 arg2: &VectorSize, 3601 ) -> Option<Reg> { 3602 let pattern0_0 = arg0; 3603 let pattern1_0 = arg1; 3604 let pattern2_0 = arg2; 3605 // Rule at src/isa/aarch64/inst.isle line 2062. 3606 let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0); 3607 let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?; 3608 return Some(expr1_0); 3609 } 3610 3611 // Generated as internal constructor for term fcmeq0. 3612 pub fn constructor_fcmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> { 3613 let pattern0_0 = arg0; 3614 let pattern1_0 = arg1; 3615 // Rule at src/isa/aarch64/inst.isle line 2067. 3616 let expr0_0 = VecMisc2::Fcmeq0; 3617 let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?; 3618 return Some(expr1_0); 3619 } 3620 3621 // Generated as internal constructor for term int_cmp_zero. 3622 pub fn constructor_int_cmp_zero<C: Context>( 3623 ctx: &mut C, 3624 arg0: &IntCC, 3625 arg1: Reg, 3626 arg2: &VectorSize, 3627 ) -> Option<Reg> { 3628 let pattern0_0 = arg0; 3629 let pattern1_0 = arg1; 3630 let pattern2_0 = arg2; 3631 // Rule at src/isa/aarch64/inst.isle line 2093. 3632 let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0); 3633 let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?; 3634 return Some(expr1_0); 3635 } 3636 3637 // Generated as internal constructor for term int_cmp_zero_swap. 3638 pub fn constructor_int_cmp_zero_swap<C: Context>( 3639 ctx: &mut C, 3640 arg0: &IntCC, 3641 arg1: Reg, 3642 arg2: &VectorSize, 3643 ) -> Option<Reg> { 3644 let pattern0_0 = arg0; 3645 let pattern1_0 = arg1; 3646 let pattern2_0 = arg2; 3647 // Rule at src/isa/aarch64/inst.isle line 2098. 3648 let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0); 3649 let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?; 3650 return Some(expr1_0); 3651 } 3652 3653 // Generated as internal constructor for term cmeq0. 3654 pub fn constructor_cmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> { 3655 let pattern0_0 = arg0; 3656 let pattern1_0 = arg1; 3657 // Rule at src/isa/aarch64/inst.isle line 2103. 3658 let expr0_0 = VecMisc2::Cmeq0; 3659 let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?; 3660 return Some(expr1_0); 3661 } 3662 3663 // Generated as internal constructor for term lse_atomic_rmw. 3664 pub fn constructor_lse_atomic_rmw<C: Context>( 3665 ctx: &mut C, 3666 arg0: &AtomicRMWOp, 3667 arg1: Value, 3668 arg2: Reg, 3669 arg3: Type, 3670 ) -> Option<Reg> { 3671 let pattern0_0 = arg0; 3672 let pattern1_0 = arg1; 3673 let pattern2_0 = arg2; 3674 let pattern3_0 = arg3; 3675 // Rule at src/isa/aarch64/inst.isle line 2108. 3676 let expr0_0 = C::put_in_reg(ctx, pattern1_0); 3677 let expr1_0 = C::temp_writable_reg(ctx, pattern3_0); 3678 let expr2_0 = MInst::AtomicRMW { 3679 op: pattern0_0.clone(), 3680 rs: pattern2_0, 3681 rt: expr1_0, 3682 rn: expr0_0, 3683 ty: pattern3_0, 3684 }; 3685 let expr3_0 = C::emit(ctx, &expr2_0); 3686 let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); 3687 return Some(expr4_0); 3688 } 3689 3690 // Generated as internal constructor for term atomic_rmw_loop. 3691 pub fn constructor_atomic_rmw_loop<C: Context>( 3692 ctx: &mut C, 3693 arg0: &AtomicRMWLoopOp, 3694 arg1: Value, 3695 arg2: Value, 3696 arg3: Type, 3697 ) -> Option<Reg> { 3698 let pattern0_0 = arg0; 3699 let pattern1_0 = arg1; 3700 let pattern2_0 = arg2; 3701 let pattern3_0 = arg3; 3702 // Rule at src/isa/aarch64/inst.isle line 2123. 3703 let expr0_0 = C::put_in_reg(ctx, pattern1_0); 3704 let expr1_0: Type = I64; 3705 let expr2_0 = C::ensure_in_vreg(ctx, expr0_0, expr1_0); 3706 let expr3_0 = C::put_in_reg(ctx, pattern2_0); 3707 let expr4_0: Type = I64; 3708 let expr5_0 = C::ensure_in_vreg(ctx, expr3_0, expr4_0); 3709 let expr6_0: u8 = 25; 3710 let expr7_0 = constructor_mov64_to_real(ctx, expr6_0, expr2_0)?; 3711 let expr8_0: u8 = 26; 3712 let expr9_0 = constructor_mov64_to_real(ctx, expr8_0, expr5_0)?; 3713 let expr10_0 = MInst::AtomicRMWLoop { 3714 ty: pattern3_0, 3715 op: pattern0_0.clone(), 3716 }; 3717 let expr11_0 = C::emit(ctx, &expr10_0); 3718 let expr12_0: u8 = 27; 3719 let expr13_0 = constructor_mov64_from_real(ctx, expr12_0)?; 3720 return Some(expr13_0); 3721 } 3722 3723 // Generated as internal constructor for term lower. 3724 pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> { 3725 let pattern0_0 = arg0; 3726 if let Some(()) = C::use_lse(ctx, pattern0_0) { 3727 if let Some(pattern2_0) = C::first_result(ctx, pattern0_0) { 3728 let pattern3_0 = C::value_type(ctx, pattern2_0); 3729 if let Some(pattern4_0) = C::valid_atomic_transaction(ctx, pattern3_0) { 3730 let pattern5_0 = C::inst_data(ctx, pattern0_0); 3731 if let &InstructionData::AtomicRmw { 3732 opcode: ref pattern6_0, 3733 args: ref pattern6_1, 3734 flags: pattern6_2, 3735 op: ref pattern6_3, 3736 } = &pattern5_0 3737 { 3738 if let &Opcode::AtomicRmw = pattern6_0 { 3739 let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1); 3740 match pattern6_3 { 3741 &AtomicRmwOp::Add => { 3742 // Rule at src/isa/aarch64/lower.isle line 1213. 3743 let expr0_0 = AtomicRMWOp::Add; 3744 let expr1_0 = C::put_in_reg(ctx, pattern8_1); 3745 let expr2_0 = constructor_lse_atomic_rmw( 3746 ctx, &expr0_0, pattern8_0, expr1_0, pattern4_0, 3747 )?; 3748 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 3749 return Some(expr3_0); 3750 } 3751 &AtomicRmwOp::And => { 3752 // Rule at src/isa/aarch64/lower.isle line 1245. 3753 let expr0_0 = AtomicRMWOp::Clr; 3754 let expr1_0 = C::put_in_reg(ctx, pattern8_1); 3755 let expr2_0 = C::zero_reg(ctx); 3756 let expr3_0 = constructor_eon(ctx, pattern4_0, expr1_0, expr2_0)?; 3757 let expr4_0 = constructor_lse_atomic_rmw( 3758 ctx, &expr0_0, pattern8_0, expr3_0, pattern4_0, 3759 )?; 3760 let expr5_0 = constructor_output_reg(ctx, expr4_0)?; 3761 return Some(expr5_0); 3762 } 3763 &AtomicRmwOp::Or => { 3764 // Rule at src/isa/aarch64/lower.isle line 1221. 3765 let expr0_0 = AtomicRMWOp::Set; 3766 let expr1_0 = C::put_in_reg(ctx, pattern8_1); 3767 let expr2_0 = constructor_lse_atomic_rmw( 3768 ctx, &expr0_0, pattern8_0, expr1_0, pattern4_0, 3769 )?; 3770 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 3771 return Some(expr3_0); 3772 } 3773 &AtomicRmwOp::Smax => { 3774 // Rule at src/isa/aarch64/lower.isle line 1225. 3775 let expr0_0 = AtomicRMWOp::Smax; 3776 let expr1_0 = C::put_in_reg(ctx, pattern8_1); 3777 let expr2_0 = constructor_lse_atomic_rmw( 3778 ctx, &expr0_0, pattern8_0, expr1_0, pattern4_0, 3779 )?; 3780 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 3781 return Some(expr3_0); 3782 } 3783 &AtomicRmwOp::Smin => { 3784 // Rule at src/isa/aarch64/lower.isle line 1229. 3785 let expr0_0 = AtomicRMWOp::Smin; 3786 let expr1_0 = C::put_in_reg(ctx, pattern8_1); 3787 let expr2_0 = constructor_lse_atomic_rmw( 3788 ctx, &expr0_0, pattern8_0, expr1_0, pattern4_0, 3789 )?; 3790 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 3791 return Some(expr3_0); 3792 } 3793 &AtomicRmwOp::Sub => { 3794 // Rule at src/isa/aarch64/lower.isle line 1241. 3795 let expr0_0 = AtomicRMWOp::Add; 3796 let expr1_0 = C::zero_reg(ctx); 3797 let expr2_0 = C::put_in_reg(ctx, pattern8_1); 3798 let expr3_0 = constructor_sub(ctx, pattern4_0, expr1_0, expr2_0)?; 3799 let expr4_0 = constructor_lse_atomic_rmw( 3800 ctx, &expr0_0, pattern8_0, expr3_0, pattern4_0, 3801 )?; 3802 let expr5_0 = constructor_output_reg(ctx, expr4_0)?; 3803 return Some(expr5_0); 3804 } 3805 &AtomicRmwOp::Umax => { 3806 // Rule at src/isa/aarch64/lower.isle line 1233. 3807 let expr0_0 = AtomicRMWOp::Umax; 3808 let expr1_0 = C::put_in_reg(ctx, pattern8_1); 3809 let expr2_0 = constructor_lse_atomic_rmw( 3810 ctx, &expr0_0, pattern8_0, expr1_0, pattern4_0, 3811 )?; 3812 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 3813 return Some(expr3_0); 3814 } 3815 &AtomicRmwOp::Umin => { 3816 // Rule at src/isa/aarch64/lower.isle line 1237. 3817 let expr0_0 = AtomicRMWOp::Umin; 3818 let expr1_0 = C::put_in_reg(ctx, pattern8_1); 3819 let expr2_0 = constructor_lse_atomic_rmw( 3820 ctx, &expr0_0, pattern8_0, expr1_0, pattern4_0, 3821 )?; 3822 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 3823 return Some(expr3_0); 3824 } 3825 &AtomicRmwOp::Xor => { 3826 // Rule at src/isa/aarch64/lower.isle line 1217. 3827 let expr0_0 = AtomicRMWOp::Eor; 3828 let expr1_0 = C::put_in_reg(ctx, pattern8_1); 3829 let expr2_0 = constructor_lse_atomic_rmw( 3830 ctx, &expr0_0, pattern8_0, expr1_0, pattern4_0, 3831 )?; 3832 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 3833 return Some(expr3_0); 3834 } 3835 _ => {} 3836 } 3837 } 3838 } 3839 } 3840 } 3841 } 3842 if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) { 3843 let pattern2_0 = C::value_type(ctx, pattern1_0); 3844 if pattern2_0 == I8 { 3845 let pattern4_0 = C::inst_data(ctx, pattern0_0); 3846 if let &InstructionData::Unary { 3847 opcode: ref pattern5_0, 3848 arg: pattern5_1, 3849 } = &pattern4_0 3850 { 3851 match pattern5_0 { 3852 &Opcode::Bitrev => { 3853 // Rule at src/isa/aarch64/lower.isle line 991. 3854 let expr0_0: Type = I32; 3855 let expr1_0: Type = I32; 3856 let expr2_0 = C::put_in_reg(ctx, pattern5_1); 3857 let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?; 3858 let expr4_0: u8 = 24; 3859 let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0); 3860 let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?; 3861 let expr7_0 = constructor_output_reg(ctx, expr6_0)?; 3862 return Some(expr7_0); 3863 } 3864 &Opcode::Clz => { 3865 // Rule at src/isa/aarch64/lower.isle line 1012. 3866 let expr0_0: Type = I32; 3867 let expr1_0: Type = I32; 3868 let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?; 3869 let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?; 3870 let expr4_0: u8 = 24; 3871 let expr5_0 = C::u8_into_imm12(ctx, expr4_0); 3872 let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?; 3873 let expr7_0 = constructor_output_reg(ctx, expr6_0)?; 3874 return Some(expr7_0); 3875 } 3876 &Opcode::Cls => { 3877 // Rule at src/isa/aarch64/lower.isle line 1059. 3878 let expr0_0: Type = I32; 3879 let expr1_0: Type = I32; 3880 let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?; 3881 let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?; 3882 let expr4_0: u8 = 24; 3883 let expr5_0 = C::u8_into_imm12(ctx, expr4_0); 3884 let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?; 3885 let expr7_0 = constructor_output_reg(ctx, expr6_0)?; 3886 return Some(expr7_0); 3887 } 3888 &Opcode::Ctz => { 3889 // Rule at src/isa/aarch64/lower.isle line 1042. 3890 let expr0_0: Type = I32; 3891 let expr1_0: Type = I32; 3892 let expr2_0: Type = I32; 3893 let expr3_0 = C::put_in_reg(ctx, pattern5_1); 3894 let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?; 3895 let expr5_0: Type = I32; 3896 let expr6_0: u64 = 8388608; 3897 let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0); 3898 let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?; 3899 let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?; 3900 let expr10_0 = constructor_output_reg(ctx, expr9_0)?; 3901 return Some(expr10_0); 3902 } 3903 &Opcode::Popcnt => { 3904 // Rule at src/isa/aarch64/lower.isle line 1110. 3905 let expr0_0 = C::put_in_reg(ctx, pattern5_1); 3906 let expr1_0 = ScalarSize::Size32; 3907 let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?; 3908 let expr3_0 = VectorSize::Size8x8; 3909 let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?; 3910 let expr5_0: u8 = 0; 3911 let expr6_0 = VectorSize::Size8x16; 3912 let expr7_0 = constructor_mov_from_vec(ctx, expr4_0, expr5_0, &expr6_0)?; 3913 let expr8_0 = constructor_output_reg(ctx, expr7_0)?; 3914 return Some(expr8_0); 3915 } 3916 _ => {} 3917 } 3918 } 3919 } 3920 if pattern2_0 == I16 { 3921 let pattern4_0 = C::inst_data(ctx, pattern0_0); 3922 if let &InstructionData::Unary { 3923 opcode: ref pattern5_0, 3924 arg: pattern5_1, 3925 } = &pattern4_0 3926 { 3927 match pattern5_0 { 3928 &Opcode::Bitrev => { 3929 // Rule at src/isa/aarch64/lower.isle line 997. 3930 let expr0_0: Type = I32; 3931 let expr1_0: Type = I32; 3932 let expr2_0 = C::put_in_reg(ctx, pattern5_1); 3933 let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?; 3934 let expr4_0: u8 = 16; 3935 let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0); 3936 let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?; 3937 let expr7_0 = constructor_output_reg(ctx, expr6_0)?; 3938 return Some(expr7_0); 3939 } 3940 &Opcode::Clz => { 3941 // Rule at src/isa/aarch64/lower.isle line 1015. 3942 let expr0_0: Type = I32; 3943 let expr1_0: Type = I32; 3944 let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?; 3945 let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?; 3946 let expr4_0: u8 = 16; 3947 let expr5_0 = C::u8_into_imm12(ctx, expr4_0); 3948 let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?; 3949 let expr7_0 = constructor_output_reg(ctx, expr6_0)?; 3950 return Some(expr7_0); 3951 } 3952 &Opcode::Cls => { 3953 // Rule at src/isa/aarch64/lower.isle line 1062. 3954 let expr0_0: Type = I32; 3955 let expr1_0: Type = I32; 3956 let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?; 3957 let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?; 3958 let expr4_0: u8 = 16; 3959 let expr5_0 = C::u8_into_imm12(ctx, expr4_0); 3960 let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?; 3961 let expr7_0 = constructor_output_reg(ctx, expr6_0)?; 3962 return Some(expr7_0); 3963 } 3964 &Opcode::Ctz => { 3965 // Rule at src/isa/aarch64/lower.isle line 1045. 3966 let expr0_0: Type = I32; 3967 let expr1_0: Type = I32; 3968 let expr2_0: Type = I32; 3969 let expr3_0 = C::put_in_reg(ctx, pattern5_1); 3970 let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?; 3971 let expr5_0: Type = I32; 3972 let expr6_0: u64 = 32768; 3973 let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0); 3974 let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?; 3975 let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?; 3976 let expr10_0 = constructor_output_reg(ctx, expr9_0)?; 3977 return Some(expr10_0); 3978 } 3979 &Opcode::Popcnt => { 3980 // Rule at src/isa/aarch64/lower.isle line 1116. 3981 let expr0_0 = C::put_in_reg(ctx, pattern5_1); 3982 let expr1_0 = ScalarSize::Size32; 3983 let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?; 3984 let expr3_0 = VectorSize::Size8x8; 3985 let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?; 3986 let expr5_0 = VectorSize::Size8x8; 3987 let expr6_0 = constructor_addp(ctx, expr4_0, expr4_0, &expr5_0)?; 3988 let expr7_0: u8 = 0; 3989 let expr8_0 = VectorSize::Size8x16; 3990 let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?; 3991 let expr10_0 = constructor_output_reg(ctx, expr9_0)?; 3992 return Some(expr10_0); 3993 } 3994 _ => {} 3995 } 3996 } 3997 } 3998 if pattern2_0 == I32 { 3999 let pattern4_0 = C::inst_data(ctx, pattern0_0); 4000 match &pattern4_0 { 4001 &InstructionData::Binary { 4002 opcode: ref pattern5_0, 4003 args: ref pattern5_1, 4004 } => { 4005 match pattern5_0 { 4006 &Opcode::Rotl => { 4007 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4008 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { 4009 let pattern9_0 = C::inst_data(ctx, pattern8_0); 4010 if let &InstructionData::UnaryImm { 4011 opcode: ref pattern10_0, 4012 imm: pattern10_1, 4013 } = &pattern9_0 4014 { 4015 if let &Opcode::Iconst = pattern10_0 { 4016 let mut closure12 = || { 4017 let expr0_0: Type = I32; 4018 let expr1_0 = 4019 C::imm_shift_from_imm64(ctx, expr0_0, pattern10_1)?; 4020 return Some(expr1_0); 4021 }; 4022 if let Some(pattern12_0) = closure12() { 4023 // Rule at src/isa/aarch64/lower.isle line 877. 4024 let expr0_0: Type = I32; 4025 let expr1_0 = C::put_in_reg(ctx, pattern7_0); 4026 let expr2_0: Type = I32; 4027 let expr3_0 = 4028 C::negate_imm_shift(ctx, expr2_0, pattern12_0); 4029 let expr4_0 = constructor_a64_rotr_imm( 4030 ctx, expr0_0, expr1_0, expr3_0, 4031 )?; 4032 let expr5_0 = constructor_output_reg(ctx, expr4_0)?; 4033 return Some(expr5_0); 4034 } 4035 } 4036 } 4037 } 4038 // Rule at src/isa/aarch64/lower.isle line 867. 4039 let expr0_0: Type = I32; 4040 let expr1_0 = C::zero_reg(ctx); 4041 let expr2_0 = C::put_in_reg(ctx, pattern7_1); 4042 let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?; 4043 let expr4_0: Type = I32; 4044 let expr5_0 = C::put_in_reg(ctx, pattern7_0); 4045 let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?; 4046 let expr7_0 = constructor_output_reg(ctx, expr6_0)?; 4047 return Some(expr7_0); 4048 } 4049 &Opcode::Rotr => { 4050 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4051 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { 4052 let pattern9_0 = C::inst_data(ctx, pattern8_0); 4053 if let &InstructionData::UnaryImm { 4054 opcode: ref pattern10_0, 4055 imm: pattern10_1, 4056 } = &pattern9_0 4057 { 4058 if let &Opcode::Iconst = pattern10_0 { 4059 let mut closure12 = || { 4060 let expr0_0: Type = I32; 4061 let expr1_0 = 4062 C::imm_shift_from_imm64(ctx, expr0_0, pattern10_1)?; 4063 return Some(expr1_0); 4064 }; 4065 if let Some(pattern12_0) = closure12() { 4066 // Rule at src/isa/aarch64/lower.isle line 922. 4067 let expr0_0: Type = I32; 4068 let expr1_0 = C::put_in_reg(ctx, pattern7_0); 4069 let expr2_0 = constructor_a64_rotr_imm( 4070 ctx, 4071 expr0_0, 4072 expr1_0, 4073 pattern12_0, 4074 )?; 4075 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 4076 return Some(expr3_0); 4077 } 4078 } 4079 } 4080 } 4081 // Rule at src/isa/aarch64/lower.isle line 909. 4082 let expr0_0: Type = I32; 4083 let expr1_0 = C::put_in_reg(ctx, pattern7_0); 4084 let expr2_0 = C::put_in_reg(ctx, pattern7_1); 4085 let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?; 4086 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 4087 return Some(expr4_0); 4088 } 4089 _ => {} 4090 } 4091 } 4092 &InstructionData::Unary { 4093 opcode: ref pattern5_0, 4094 arg: pattern5_1, 4095 } => { 4096 if let &Opcode::Popcnt = pattern5_0 { 4097 // Rule at src/isa/aarch64/lower.isle line 1122. 4098 let expr0_0 = C::put_in_reg(ctx, pattern5_1); 4099 let expr1_0 = ScalarSize::Size32; 4100 let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?; 4101 let expr3_0 = VectorSize::Size8x8; 4102 let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?; 4103 let expr5_0 = VectorSize::Size8x8; 4104 let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?; 4105 let expr7_0: u8 = 0; 4106 let expr8_0 = VectorSize::Size8x16; 4107 let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?; 4108 let expr10_0 = constructor_output_reg(ctx, expr9_0)?; 4109 return Some(expr10_0); 4110 } 4111 } 4112 _ => {} 4113 } 4114 } 4115 if pattern2_0 == I64 { 4116 let pattern4_0 = C::inst_data(ctx, pattern0_0); 4117 match &pattern4_0 { 4118 &InstructionData::Binary { 4119 opcode: ref pattern5_0, 4120 args: ref pattern5_1, 4121 } => { 4122 match pattern5_0 { 4123 &Opcode::Umulhi => { 4124 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4125 // Rule at src/isa/aarch64/lower.isle line 374. 4126 let expr0_0: Type = I64; 4127 let expr1_0 = C::put_in_reg(ctx, pattern7_0); 4128 let expr2_0 = C::put_in_reg(ctx, pattern7_1); 4129 let expr3_0 = constructor_umulh(ctx, expr0_0, expr1_0, expr2_0)?; 4130 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 4131 return Some(expr4_0); 4132 } 4133 &Opcode::Smulhi => { 4134 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4135 // Rule at src/isa/aarch64/lower.isle line 362. 4136 let expr0_0: Type = I64; 4137 let expr1_0 = C::put_in_reg(ctx, pattern7_0); 4138 let expr2_0 = C::put_in_reg(ctx, pattern7_1); 4139 let expr3_0 = constructor_smulh(ctx, expr0_0, expr1_0, expr2_0)?; 4140 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 4141 return Some(expr4_0); 4142 } 4143 &Opcode::Band => { 4144 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4145 // Rule at src/isa/aarch64/lower.isle line 596. 4146 let expr0_0 = ALUOp::And; 4147 let expr1_0: Type = I64; 4148 let expr2_0 = constructor_alu_rs_imm_logic_commutative( 4149 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1, 4150 )?; 4151 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 4152 return Some(expr3_0); 4153 } 4154 &Opcode::Bor => { 4155 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4156 // Rule at src/isa/aarch64/lower.isle line 609. 4157 let expr0_0 = ALUOp::Orr; 4158 let expr1_0: Type = I64; 4159 let expr2_0 = constructor_alu_rs_imm_logic_commutative( 4160 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1, 4161 )?; 4162 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 4163 return Some(expr3_0); 4164 } 4165 &Opcode::Bxor => { 4166 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4167 // Rule at src/isa/aarch64/lower.isle line 622. 4168 let expr0_0 = ALUOp::Eor; 4169 let expr1_0: Type = I64; 4170 let expr2_0 = constructor_alu_rs_imm_logic_commutative( 4171 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1, 4172 )?; 4173 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 4174 return Some(expr3_0); 4175 } 4176 &Opcode::BandNot => { 4177 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4178 // Rule at src/isa/aarch64/lower.isle line 635. 4179 let expr0_0 = ALUOp::AndNot; 4180 let expr1_0: Type = I64; 4181 let expr2_0 = constructor_alu_rs_imm_logic( 4182 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1, 4183 )?; 4184 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 4185 return Some(expr3_0); 4186 } 4187 &Opcode::BorNot => { 4188 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4189 // Rule at src/isa/aarch64/lower.isle line 648. 4190 let expr0_0 = ALUOp::OrrNot; 4191 let expr1_0: Type = I64; 4192 let expr2_0 = constructor_alu_rs_imm_logic( 4193 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1, 4194 )?; 4195 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 4196 return Some(expr3_0); 4197 } 4198 &Opcode::BxorNot => { 4199 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4200 // Rule at src/isa/aarch64/lower.isle line 658. 4201 let expr0_0 = ALUOp::EorNot; 4202 let expr1_0: Type = I64; 4203 let expr2_0 = constructor_alu_rs_imm_logic( 4204 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1, 4205 )?; 4206 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 4207 return Some(expr3_0); 4208 } 4209 &Opcode::Rotl => { 4210 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4211 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { 4212 let pattern9_0 = C::inst_data(ctx, pattern8_0); 4213 if let &InstructionData::UnaryImm { 4214 opcode: ref pattern10_0, 4215 imm: pattern10_1, 4216 } = &pattern9_0 4217 { 4218 if let &Opcode::Iconst = pattern10_0 { 4219 let mut closure12 = || { 4220 let expr0_0: Type = I64; 4221 let expr1_0 = 4222 C::imm_shift_from_imm64(ctx, expr0_0, pattern10_1)?; 4223 return Some(expr1_0); 4224 }; 4225 if let Some(pattern12_0) = closure12() { 4226 // Rule at src/isa/aarch64/lower.isle line 882. 4227 let expr0_0: Type = I64; 4228 let expr1_0 = C::put_in_reg(ctx, pattern7_0); 4229 let expr2_0: Type = I64; 4230 let expr3_0 = 4231 C::negate_imm_shift(ctx, expr2_0, pattern12_0); 4232 let expr4_0 = constructor_a64_rotr_imm( 4233 ctx, expr0_0, expr1_0, expr3_0, 4234 )?; 4235 let expr5_0 = constructor_output_reg(ctx, expr4_0)?; 4236 return Some(expr5_0); 4237 } 4238 } 4239 } 4240 } 4241 // Rule at src/isa/aarch64/lower.isle line 872. 4242 let expr0_0: Type = I64; 4243 let expr1_0 = C::zero_reg(ctx); 4244 let expr2_0 = C::put_in_reg(ctx, pattern7_1); 4245 let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?; 4246 let expr4_0: Type = I64; 4247 let expr5_0 = C::put_in_reg(ctx, pattern7_0); 4248 let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?; 4249 let expr7_0 = constructor_output_reg(ctx, expr6_0)?; 4250 return Some(expr7_0); 4251 } 4252 &Opcode::Rotr => { 4253 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4254 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { 4255 let pattern9_0 = C::inst_data(ctx, pattern8_0); 4256 if let &InstructionData::UnaryImm { 4257 opcode: ref pattern10_0, 4258 imm: pattern10_1, 4259 } = &pattern9_0 4260 { 4261 if let &Opcode::Iconst = pattern10_0 { 4262 let mut closure12 = || { 4263 let expr0_0: Type = I64; 4264 let expr1_0 = 4265 C::imm_shift_from_imm64(ctx, expr0_0, pattern10_1)?; 4266 return Some(expr1_0); 4267 }; 4268 if let Some(pattern12_0) = closure12() { 4269 // Rule at src/isa/aarch64/lower.isle line 927. 4270 let expr0_0: Type = I64; 4271 let expr1_0 = C::put_in_reg(ctx, pattern7_0); 4272 let expr2_0 = constructor_a64_rotr_imm( 4273 ctx, 4274 expr0_0, 4275 expr1_0, 4276 pattern12_0, 4277 )?; 4278 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 4279 return Some(expr3_0); 4280 } 4281 } 4282 } 4283 } 4284 // Rule at src/isa/aarch64/lower.isle line 913. 4285 let expr0_0: Type = I64; 4286 let expr1_0 = C::put_in_reg(ctx, pattern7_0); 4287 let expr2_0 = C::put_in_reg(ctx, pattern7_1); 4288 let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?; 4289 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 4290 return Some(expr4_0); 4291 } 4292 &Opcode::Ishl => { 4293 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4294 // Rule at src/isa/aarch64/lower.isle line 670. 4295 let expr0_0 = ALUOp::Lsl; 4296 let expr1_0: Type = I64; 4297 let expr2_0 = C::put_in_reg(ctx, pattern7_0); 4298 let expr3_0 = 4299 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?; 4300 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 4301 return Some(expr4_0); 4302 } 4303 &Opcode::Ushr => { 4304 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4305 // Rule at src/isa/aarch64/lower.isle line 755. 4306 let expr0_0 = ALUOp::Lsr; 4307 let expr1_0: Type = I64; 4308 let expr2_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?; 4309 let expr3_0 = 4310 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?; 4311 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 4312 return Some(expr4_0); 4313 } 4314 &Opcode::Sshr => { 4315 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4316 // Rule at src/isa/aarch64/lower.isle line 802. 4317 let expr0_0 = ALUOp::Asr; 4318 let expr1_0: Type = I64; 4319 let expr2_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?; 4320 let expr3_0 = 4321 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?; 4322 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 4323 return Some(expr4_0); 4324 } 4325 _ => {} 4326 } 4327 } 4328 &InstructionData::Unary { 4329 opcode: ref pattern5_0, 4330 arg: pattern5_1, 4331 } => { 4332 if let &Opcode::Popcnt = pattern5_0 { 4333 // Rule at src/isa/aarch64/lower.isle line 1128. 4334 let expr0_0 = C::put_in_reg(ctx, pattern5_1); 4335 let expr1_0 = ScalarSize::Size64; 4336 let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?; 4337 let expr3_0 = VectorSize::Size8x8; 4338 let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?; 4339 let expr5_0 = VectorSize::Size8x8; 4340 let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?; 4341 let expr7_0: u8 = 0; 4342 let expr8_0 = VectorSize::Size8x16; 4343 let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?; 4344 let expr10_0 = constructor_output_reg(ctx, expr9_0)?; 4345 return Some(expr10_0); 4346 } 4347 } 4348 _ => {} 4349 } 4350 } 4351 if pattern2_0 == I128 { 4352 let pattern4_0 = C::inst_data(ctx, pattern0_0); 4353 match &pattern4_0 { 4354 &InstructionData::Binary { 4355 opcode: ref pattern5_0, 4356 args: ref pattern5_1, 4357 } => { 4358 match pattern5_0 { 4359 &Opcode::Iadd => { 4360 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4361 // Rule at src/isa/aarch64/lower.isle line 85. 4362 let expr0_0 = C::put_in_regs(ctx, pattern7_0); 4363 let expr1_0: usize = 0; 4364 let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); 4365 let expr3_0: usize = 1; 4366 let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0); 4367 let expr5_0 = C::put_in_regs(ctx, pattern7_1); 4368 let expr6_0: usize = 0; 4369 let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0); 4370 let expr8_0: usize = 1; 4371 let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0); 4372 let expr10_0: Type = I64; 4373 let expr11_0 = 4374 constructor_add_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?; 4375 let expr12_0: Type = I64; 4376 let expr13_0 = constructor_adc_paired(ctx, expr12_0, expr4_0, expr9_0)?; 4377 let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?; 4378 let expr15_0 = C::output(ctx, expr14_0); 4379 return Some(expr15_0); 4380 } 4381 &Opcode::Isub => { 4382 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4383 // Rule at src/isa/aarch64/lower.isle line 136. 4384 let expr0_0 = C::put_in_regs(ctx, pattern7_0); 4385 let expr1_0: usize = 0; 4386 let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); 4387 let expr3_0: usize = 1; 4388 let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0); 4389 let expr5_0 = C::put_in_regs(ctx, pattern7_1); 4390 let expr6_0: usize = 0; 4391 let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0); 4392 let expr8_0: usize = 1; 4393 let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0); 4394 let expr10_0: Type = I64; 4395 let expr11_0 = 4396 constructor_sub_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?; 4397 let expr12_0: Type = I64; 4398 let expr13_0 = constructor_sbc_paired(ctx, expr12_0, expr4_0, expr9_0)?; 4399 let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?; 4400 let expr15_0 = C::output(ctx, expr14_0); 4401 return Some(expr15_0); 4402 } 4403 &Opcode::Imul => { 4404 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4405 // Rule at src/isa/aarch64/lower.isle line 190. 4406 let expr0_0 = C::put_in_regs(ctx, pattern7_0); 4407 let expr1_0: usize = 0; 4408 let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); 4409 let expr3_0: usize = 1; 4410 let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0); 4411 let expr5_0 = C::put_in_regs(ctx, pattern7_1); 4412 let expr6_0: usize = 0; 4413 let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0); 4414 let expr8_0: usize = 1; 4415 let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0); 4416 let expr10_0: Type = I64; 4417 let expr11_0 = constructor_umulh(ctx, expr10_0, expr2_0, expr7_0)?; 4418 let expr12_0: Type = I64; 4419 let expr13_0 = 4420 constructor_madd(ctx, expr12_0, expr2_0, expr9_0, expr11_0)?; 4421 let expr14_0: Type = I64; 4422 let expr15_0 = 4423 constructor_madd(ctx, expr14_0, expr4_0, expr7_0, expr13_0)?; 4424 let expr16_0: Type = I64; 4425 let expr17_0 = C::zero_reg(ctx); 4426 let expr18_0 = 4427 constructor_madd(ctx, expr16_0, expr2_0, expr7_0, expr17_0)?; 4428 let expr19_0 = C::value_regs(ctx, expr18_0, expr15_0); 4429 let expr20_0 = C::output(ctx, expr19_0); 4430 return Some(expr20_0); 4431 } 4432 &Opcode::Band => { 4433 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4434 // Rule at src/isa/aarch64/lower.isle line 599. 4435 let expr0_0 = ALUOp::And; 4436 let expr1_0: Type = I64; 4437 let expr2_0 = constructor_i128_alu_bitop( 4438 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1, 4439 )?; 4440 let expr3_0 = C::output(ctx, expr2_0); 4441 return Some(expr3_0); 4442 } 4443 &Opcode::Bor => { 4444 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4445 // Rule at src/isa/aarch64/lower.isle line 612. 4446 let expr0_0 = ALUOp::Orr; 4447 let expr1_0: Type = I64; 4448 let expr2_0 = constructor_i128_alu_bitop( 4449 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1, 4450 )?; 4451 let expr3_0 = C::output(ctx, expr2_0); 4452 return Some(expr3_0); 4453 } 4454 &Opcode::Bxor => { 4455 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4456 // Rule at src/isa/aarch64/lower.isle line 625. 4457 let expr0_0 = ALUOp::Eor; 4458 let expr1_0: Type = I64; 4459 let expr2_0 = constructor_i128_alu_bitop( 4460 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1, 4461 )?; 4462 let expr3_0 = C::output(ctx, expr2_0); 4463 return Some(expr3_0); 4464 } 4465 &Opcode::BandNot => { 4466 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4467 // Rule at src/isa/aarch64/lower.isle line 638. 4468 let expr0_0 = ALUOp::AndNot; 4469 let expr1_0: Type = I64; 4470 let expr2_0 = constructor_i128_alu_bitop( 4471 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1, 4472 )?; 4473 let expr3_0 = C::output(ctx, expr2_0); 4474 return Some(expr3_0); 4475 } 4476 &Opcode::BorNot => { 4477 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4478 // Rule at src/isa/aarch64/lower.isle line 651. 4479 let expr0_0 = ALUOp::OrrNot; 4480 let expr1_0: Type = I64; 4481 let expr2_0 = constructor_i128_alu_bitop( 4482 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1, 4483 )?; 4484 let expr3_0 = C::output(ctx, expr2_0); 4485 return Some(expr3_0); 4486 } 4487 &Opcode::BxorNot => { 4488 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4489 // Rule at src/isa/aarch64/lower.isle line 661. 4490 let expr0_0 = ALUOp::EorNot; 4491 let expr1_0: Type = I64; 4492 let expr2_0 = constructor_i128_alu_bitop( 4493 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1, 4494 )?; 4495 let expr3_0 = C::output(ctx, expr2_0); 4496 return Some(expr3_0); 4497 } 4498 &Opcode::Rotl => { 4499 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4500 // Rule at src/isa/aarch64/lower.isle line 892. 4501 let expr0_0 = C::put_in_regs(ctx, pattern7_0); 4502 let expr1_0 = C::put_in_regs(ctx, pattern7_1); 4503 let expr2_0: usize = 0; 4504 let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0); 4505 let expr4_0: Type = I64; 4506 let expr5_0: Type = I64; 4507 let expr6_0: u64 = 128; 4508 let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?; 4509 let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?; 4510 let expr9_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?; 4511 let expr10_0 = constructor_lower_ushr128(ctx, expr0_0, expr8_0)?; 4512 let expr11_0: Type = I64; 4513 let expr12_0: usize = 0; 4514 let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0); 4515 let expr14_0: usize = 0; 4516 let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0); 4517 let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?; 4518 let expr17_0: Type = I64; 4519 let expr18_0: usize = 1; 4520 let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0); 4521 let expr20_0: usize = 1; 4522 let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0); 4523 let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?; 4524 let expr23_0 = C::value_regs(ctx, expr16_0, expr22_0); 4525 let expr24_0 = C::output(ctx, expr23_0); 4526 return Some(expr24_0); 4527 } 4528 &Opcode::Rotr => { 4529 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4530 // Rule at src/isa/aarch64/lower.isle line 976. 4531 let expr0_0 = C::put_in_regs(ctx, pattern7_0); 4532 let expr1_0 = C::put_in_regs(ctx, pattern7_1); 4533 let expr2_0: usize = 0; 4534 let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0); 4535 let expr4_0: Type = I64; 4536 let expr5_0: Type = I64; 4537 let expr6_0: u64 = 128; 4538 let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?; 4539 let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?; 4540 let expr9_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?; 4541 let expr10_0 = constructor_lower_shl128(ctx, expr0_0, expr8_0)?; 4542 let expr11_0: Type = I64; 4543 let expr12_0: usize = 1; 4544 let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0); 4545 let expr14_0: usize = 1; 4546 let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0); 4547 let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?; 4548 let expr17_0: Type = I64; 4549 let expr18_0: usize = 0; 4550 let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0); 4551 let expr20_0: usize = 0; 4552 let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0); 4553 let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?; 4554 let expr23_0 = C::value_regs(ctx, expr22_0, expr16_0); 4555 let expr24_0 = C::output(ctx, expr23_0); 4556 return Some(expr24_0); 4557 } 4558 &Opcode::Ishl => { 4559 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4560 // Rule at src/isa/aarch64/lower.isle line 674. 4561 let expr0_0 = C::put_in_regs(ctx, pattern7_0); 4562 let expr1_0 = C::put_in_regs(ctx, pattern7_1); 4563 let expr2_0: usize = 0; 4564 let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0); 4565 let expr4_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?; 4566 let expr5_0 = C::output(ctx, expr4_0); 4567 return Some(expr5_0); 4568 } 4569 &Opcode::Ushr => { 4570 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4571 // Rule at src/isa/aarch64/lower.isle line 759. 4572 let expr0_0 = C::put_in_regs(ctx, pattern7_0); 4573 let expr1_0 = C::put_in_regs(ctx, pattern7_1); 4574 let expr2_0: usize = 0; 4575 let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0); 4576 let expr4_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?; 4577 let expr5_0 = C::output(ctx, expr4_0); 4578 return Some(expr5_0); 4579 } 4580 &Opcode::Sshr => { 4581 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4582 // Rule at src/isa/aarch64/lower.isle line 806. 4583 let expr0_0 = C::put_in_regs(ctx, pattern7_0); 4584 let expr1_0 = C::put_in_regs(ctx, pattern7_1); 4585 let expr2_0: usize = 0; 4586 let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0); 4587 let expr4_0 = constructor_lower_sshr128(ctx, expr0_0, expr3_0)?; 4588 let expr5_0 = C::output(ctx, expr4_0); 4589 return Some(expr5_0); 4590 } 4591 _ => {} 4592 } 4593 } 4594 &InstructionData::Unary { 4595 opcode: ref pattern5_0, 4596 arg: pattern5_1, 4597 } => { 4598 match pattern5_0 { 4599 &Opcode::Bnot => { 4600 // Rule at src/isa/aarch64/lower.isle line 579. 4601 let expr0_0 = C::put_in_regs(ctx, pattern5_1); 4602 let expr1_0: usize = 0; 4603 let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); 4604 let expr3_0: usize = 1; 4605 let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0); 4606 let expr5_0: Type = I64; 4607 let expr6_0 = C::zero_reg(ctx); 4608 let expr7_0 = constructor_orr_not(ctx, expr5_0, expr6_0, expr2_0)?; 4609 let expr8_0: Type = I64; 4610 let expr9_0 = C::zero_reg(ctx); 4611 let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, expr4_0)?; 4612 let expr11_0 = C::value_regs(ctx, expr7_0, expr10_0); 4613 let expr12_0 = C::output(ctx, expr11_0); 4614 return Some(expr12_0); 4615 } 4616 &Opcode::Bitrev => { 4617 // Rule at src/isa/aarch64/lower.isle line 1000. 4618 let expr0_0 = C::put_in_regs(ctx, pattern5_1); 4619 let expr1_0: Type = I64; 4620 let expr2_0: usize = 0; 4621 let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0); 4622 let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?; 4623 let expr5_0: Type = I64; 4624 let expr6_0: usize = 1; 4625 let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0); 4626 let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?; 4627 let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0); 4628 let expr10_0 = C::output(ctx, expr9_0); 4629 return Some(expr10_0); 4630 } 4631 &Opcode::Clz => { 4632 // Rule at src/isa/aarch64/lower.isle line 1018. 4633 let expr0_0 = C::put_in_regs(ctx, pattern5_1); 4634 let expr1_0 = constructor_lower_clz128(ctx, expr0_0)?; 4635 let expr2_0 = C::output(ctx, expr1_0); 4636 return Some(expr2_0); 4637 } 4638 &Opcode::Cls => { 4639 // Rule at src/isa/aarch64/lower.isle line 1074. 4640 let expr0_0 = C::put_in_regs(ctx, pattern5_1); 4641 let expr1_0: usize = 0; 4642 let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); 4643 let expr3_0: usize = 1; 4644 let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0); 4645 let expr5_0: Type = I64; 4646 let expr6_0 = constructor_a64_cls(ctx, expr5_0, expr2_0)?; 4647 let expr7_0: Type = I64; 4648 let expr8_0 = constructor_a64_cls(ctx, expr7_0, expr4_0)?; 4649 let expr9_0: Type = I64; 4650 let expr10_0 = constructor_eon(ctx, expr9_0, expr4_0, expr2_0)?; 4651 let expr11_0: Type = I64; 4652 let expr12_0: u8 = 63; 4653 let expr13_0 = C::imm_shift_from_u8(ctx, expr12_0); 4654 let expr14_0 = constructor_lsr_imm(ctx, expr11_0, expr10_0, expr13_0)?; 4655 let expr15_0: Type = I64; 4656 let expr16_0 = 4657 constructor_madd(ctx, expr15_0, expr6_0, expr14_0, expr14_0)?; 4658 let expr17_0: u8 = 63; 4659 let expr18_0 = C::u8_into_imm12(ctx, expr17_0); 4660 let expr19_0 = constructor_cmp64_imm(ctx, expr8_0, expr18_0)?; 4661 let expr20_0 = Cond::Eq; 4662 let expr21_0 = C::zero_reg(ctx); 4663 let expr22_0 = constructor_csel(ctx, &expr20_0, expr16_0, expr21_0)?; 4664 let expr23_0 = constructor_with_flags_reg(ctx, &expr19_0, &expr22_0)?; 4665 let expr24_0: Type = I64; 4666 let expr25_0 = constructor_add(ctx, expr24_0, expr23_0, expr8_0)?; 4667 let expr26_0: Type = I64; 4668 let expr27_0: u64 = 0; 4669 let expr28_0 = constructor_imm(ctx, expr26_0, expr27_0)?; 4670 let expr29_0 = C::value_regs(ctx, expr25_0, expr28_0); 4671 let expr30_0 = C::output(ctx, expr29_0); 4672 return Some(expr30_0); 4673 } 4674 &Opcode::Ctz => { 4675 // Rule at src/isa/aarch64/lower.isle line 1048. 4676 let expr0_0 = C::put_in_regs(ctx, pattern5_1); 4677 let expr1_0: Type = I64; 4678 let expr2_0: usize = 0; 4679 let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0); 4680 let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?; 4681 let expr5_0: Type = I64; 4682 let expr6_0: usize = 1; 4683 let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0); 4684 let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?; 4685 let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0); 4686 let expr10_0 = constructor_lower_clz128(ctx, expr9_0)?; 4687 let expr11_0 = C::output(ctx, expr10_0); 4688 return Some(expr11_0); 4689 } 4690 &Opcode::Popcnt => { 4691 // Rule at src/isa/aarch64/lower.isle line 1134. 4692 let expr0_0 = C::put_in_regs(ctx, pattern5_1); 4693 let expr1_0: usize = 0; 4694 let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); 4695 let expr3_0 = ScalarSize::Size64; 4696 let expr4_0 = constructor_mov_to_fpu(ctx, expr2_0, &expr3_0)?; 4697 let expr5_0: usize = 1; 4698 let expr6_0 = C::value_regs_get(ctx, expr0_0, expr5_0); 4699 let expr7_0: u8 = 1; 4700 let expr8_0 = VectorSize::Size64x2; 4701 let expr9_0 = 4702 constructor_mov_to_vec(ctx, expr4_0, expr6_0, expr7_0, &expr8_0)?; 4703 let expr10_0 = VectorSize::Size8x16; 4704 let expr11_0 = constructor_vec_cnt(ctx, expr9_0, &expr10_0)?; 4705 let expr12_0 = VectorSize::Size8x16; 4706 let expr13_0 = constructor_addv(ctx, expr11_0, &expr12_0)?; 4707 let expr14_0: u8 = 0; 4708 let expr15_0 = VectorSize::Size8x16; 4709 let expr16_0 = 4710 constructor_mov_from_vec(ctx, expr13_0, expr14_0, &expr15_0)?; 4711 let expr17_0: Type = I64; 4712 let expr18_0: u64 = 0; 4713 let expr19_0 = constructor_imm(ctx, expr17_0, expr18_0)?; 4714 let expr20_0 = C::value_regs(ctx, expr16_0, expr19_0); 4715 let expr21_0 = C::output(ctx, expr20_0); 4716 return Some(expr21_0); 4717 } 4718 &Opcode::Uextend => { 4719 if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) { 4720 let pattern8_0 = C::inst_data(ctx, pattern7_0); 4721 if let &InstructionData::BinaryImm8 { 4722 opcode: ref pattern9_0, 4723 arg: pattern9_1, 4724 imm: pattern9_2, 4725 } = &pattern8_0 4726 { 4727 if let &Opcode::Extractlane = pattern9_0 { 4728 let pattern11_0 = C::value_type(ctx, pattern9_1); 4729 let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2); 4730 // Rule at src/isa/aarch64/lower.isle line 508. 4731 let expr0_0 = C::put_in_reg(ctx, pattern9_1); 4732 let expr1_0 = constructor_vector_size(ctx, pattern11_0)?; 4733 let expr2_0 = constructor_mov_from_vec( 4734 ctx, 4735 expr0_0, 4736 pattern12_0, 4737 &expr1_0, 4738 )?; 4739 let expr3_0: Type = I64; 4740 let expr4_0: u64 = 0; 4741 let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?; 4742 let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0); 4743 let expr7_0 = C::output(ctx, expr6_0); 4744 return Some(expr7_0); 4745 } 4746 } 4747 } 4748 // Rule at src/isa/aarch64/lower.isle line 503. 4749 let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?; 4750 let expr1_0: Type = I64; 4751 let expr2_0: u64 = 0; 4752 let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?; 4753 let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0); 4754 let expr5_0 = C::output(ctx, expr4_0); 4755 return Some(expr5_0); 4756 } 4757 &Opcode::Sextend => { 4758 if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) { 4759 let pattern8_0 = C::inst_data(ctx, pattern7_0); 4760 if let &InstructionData::BinaryImm8 { 4761 opcode: ref pattern9_0, 4762 arg: pattern9_1, 4763 imm: pattern9_2, 4764 } = &pattern8_0 4765 { 4766 if let &Opcode::Extractlane = pattern9_0 { 4767 let pattern11_0 = C::value_type(ctx, pattern9_1); 4768 if pattern11_0 == I64X2 { 4769 let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2); 4770 // Rule at src/isa/aarch64/lower.isle line 552. 4771 let expr0_0 = C::put_in_reg(ctx, pattern9_1); 4772 let expr1_0 = VectorSize::Size64x2; 4773 let expr2_0 = constructor_mov_from_vec( 4774 ctx, 4775 expr0_0, 4776 pattern13_0, 4777 &expr1_0, 4778 )?; 4779 let expr3_0: Type = I64; 4780 let expr4_0: u8 = 63; 4781 let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0); 4782 let expr6_0 = constructor_asr_imm( 4783 ctx, expr3_0, expr2_0, expr5_0, 4784 )?; 4785 let expr7_0 = C::value_regs(ctx, expr2_0, expr6_0); 4786 let expr8_0 = C::output(ctx, expr7_0); 4787 return Some(expr8_0); 4788 } 4789 if let Some(()) = C::not_i64x2(ctx, pattern11_0) { 4790 let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2); 4791 // Rule at src/isa/aarch64/lower.isle line 541. 4792 let expr0_0 = C::put_in_reg(ctx, pattern9_1); 4793 let expr1_0 = 4794 constructor_vector_size(ctx, pattern11_0)?; 4795 let expr2_0: Type = I64; 4796 let expr3_0 = constructor_size_from_ty(ctx, expr2_0)?; 4797 let expr4_0 = constructor_mov_from_vec_signed( 4798 ctx, 4799 expr0_0, 4800 pattern13_0, 4801 &expr1_0, 4802 &expr3_0, 4803 )?; 4804 let expr5_0: Type = I64; 4805 let expr6_0: u8 = 63; 4806 let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0); 4807 let expr8_0 = constructor_asr_imm( 4808 ctx, expr5_0, expr4_0, expr7_0, 4809 )?; 4810 let expr9_0 = C::value_regs(ctx, expr4_0, expr8_0); 4811 let expr10_0 = C::output(ctx, expr9_0); 4812 return Some(expr10_0); 4813 } 4814 } 4815 } 4816 } 4817 // Rule at src/isa/aarch64/lower.isle line 531. 4818 let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?; 4819 let expr1_0: Type = I64; 4820 let expr2_0: u8 = 63; 4821 let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0); 4822 let expr4_0 = constructor_asr_imm(ctx, expr1_0, expr0_0, expr3_0)?; 4823 let expr5_0 = C::value_regs(ctx, expr0_0, expr4_0); 4824 let expr6_0 = C::output(ctx, expr5_0); 4825 return Some(expr6_0); 4826 } 4827 _ => {} 4828 } 4829 } 4830 _ => {} 4831 } 4832 } 4833 if pattern2_0 == I8X16 { 4834 let pattern4_0 = C::inst_data(ctx, pattern0_0); 4835 if let &InstructionData::Unary { 4836 opcode: ref pattern5_0, 4837 arg: pattern5_1, 4838 } = &pattern4_0 4839 { 4840 if let &Opcode::Popcnt = pattern5_0 { 4841 // Rule at src/isa/aarch64/lower.isle line 1142. 4842 let expr0_0 = C::put_in_reg(ctx, pattern5_1); 4843 let expr1_0 = VectorSize::Size8x16; 4844 let expr2_0 = constructor_vec_cnt(ctx, expr0_0, &expr1_0)?; 4845 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 4846 return Some(expr3_0); 4847 } 4848 } 4849 } 4850 if pattern2_0 == I16X8 { 4851 let pattern4_0 = C::inst_data(ctx, pattern0_0); 4852 if let &InstructionData::Binary { 4853 opcode: ref pattern5_0, 4854 args: ref pattern5_1, 4855 } = &pattern4_0 4856 { 4857 if let &Opcode::Imul = pattern5_0 { 4858 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 4859 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) { 4860 let pattern9_0 = C::inst_data(ctx, pattern8_0); 4861 if let &InstructionData::Unary { 4862 opcode: ref pattern10_0, 4863 arg: pattern10_1, 4864 } = &pattern9_0 4865 { 4866 match pattern10_0 { 4867 &Opcode::SwidenLow => { 4868 let pattern12_0 = C::value_type(ctx, pattern10_1); 4869 if pattern12_0 == I8X16 { 4870 if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) { 4871 let pattern15_0 = C::inst_data(ctx, pattern14_0); 4872 if let &InstructionData::Unary { 4873 opcode: ref pattern16_0, 4874 arg: pattern16_1, 4875 } = &pattern15_0 4876 { 4877 if let &Opcode::SwidenLow = pattern16_0 { 4878 let pattern18_0 = 4879 C::value_type(ctx, pattern16_1); 4880 if pattern18_0 == I8X16 { 4881 // Rule at src/isa/aarch64/lower.isle line 289. 4882 let expr0_0 = 4883 C::put_in_reg(ctx, pattern10_1); 4884 let expr1_0 = 4885 C::put_in_reg(ctx, pattern16_1); 4886 let expr2_0: bool = false; 4887 let expr3_0 = constructor_smull8( 4888 ctx, expr0_0, expr1_0, expr2_0, 4889 )?; 4890 let expr4_0 = 4891 constructor_output_reg(ctx, expr3_0)?; 4892 return Some(expr4_0); 4893 } 4894 } 4895 } 4896 } 4897 } 4898 } 4899 &Opcode::SwidenHigh => { 4900 let pattern12_0 = C::value_type(ctx, pattern10_1); 4901 if pattern12_0 == I8X16 { 4902 if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) { 4903 let pattern15_0 = C::inst_data(ctx, pattern14_0); 4904 if let &InstructionData::Unary { 4905 opcode: ref pattern16_0, 4906 arg: pattern16_1, 4907 } = &pattern15_0 4908 { 4909 if let &Opcode::SwidenHigh = pattern16_0 { 4910 let pattern18_0 = 4911 C::value_type(ctx, pattern16_1); 4912 if pattern18_0 == I8X16 { 4913 // Rule at src/isa/aarch64/lower.isle line 295. 4914 let expr0_0 = 4915 C::put_in_reg(ctx, pattern10_1); 4916 let expr1_0 = 4917 C::put_in_reg(ctx, pattern16_1); 4918 let expr2_0: bool = true; 4919 let expr3_0 = constructor_smull8( 4920 ctx, expr0_0, expr1_0, expr2_0, 4921 )?; 4922 let expr4_0 = 4923 constructor_output_reg(ctx, expr3_0)?; 4924 return Some(expr4_0); 4925 } 4926 } 4927 } 4928 } 4929 } 4930 } 4931 &Opcode::UwidenLow => { 4932 let pattern12_0 = C::value_type(ctx, pattern10_1); 4933 if pattern12_0 == I8X16 { 4934 if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) { 4935 let pattern15_0 = C::inst_data(ctx, pattern14_0); 4936 if let &InstructionData::Unary { 4937 opcode: ref pattern16_0, 4938 arg: pattern16_1, 4939 } = &pattern15_0 4940 { 4941 if let &Opcode::UwidenLow = pattern16_0 { 4942 let pattern18_0 = 4943 C::value_type(ctx, pattern16_1); 4944 if pattern18_0 == I8X16 { 4945 // Rule at src/isa/aarch64/lower.isle line 301. 4946 let expr0_0 = 4947 C::put_in_reg(ctx, pattern10_1); 4948 let expr1_0 = 4949 C::put_in_reg(ctx, pattern16_1); 4950 let expr2_0: bool = false; 4951 let expr3_0 = constructor_umull8( 4952 ctx, expr0_0, expr1_0, expr2_0, 4953 )?; 4954 let expr4_0 = 4955 constructor_output_reg(ctx, expr3_0)?; 4956 return Some(expr4_0); 4957 } 4958 } 4959 } 4960 } 4961 } 4962 } 4963 &Opcode::UwidenHigh => { 4964 let pattern12_0 = C::value_type(ctx, pattern10_1); 4965 if pattern12_0 == I8X16 { 4966 if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) { 4967 let pattern15_0 = C::inst_data(ctx, pattern14_0); 4968 if let &InstructionData::Unary { 4969 opcode: ref pattern16_0, 4970 arg: pattern16_1, 4971 } = &pattern15_0 4972 { 4973 if let &Opcode::UwidenHigh = pattern16_0 { 4974 let pattern18_0 = 4975 C::value_type(ctx, pattern16_1); 4976 if pattern18_0 == I8X16 { 4977 // Rule at src/isa/aarch64/lower.isle line 307. 4978 let expr0_0 = 4979 C::put_in_reg(ctx, pattern10_1); 4980 let expr1_0 = 4981 C::put_in_reg(ctx, pattern16_1); 4982 let expr2_0: bool = true; 4983 let expr3_0 = constructor_umull8( 4984 ctx, expr0_0, expr1_0, expr2_0, 4985 )?; 4986 let expr4_0 = 4987 constructor_output_reg(ctx, expr3_0)?; 4988 return Some(expr4_0); 4989 } 4990 } 4991 } 4992 } 4993 } 4994 } 4995 _ => {} 4996 } 4997 } 4998 } 4999 } 5000 } 5001 } 5002 if pattern2_0 == I32X4 { 5003 let pattern4_0 = C::inst_data(ctx, pattern0_0); 5004 if let &InstructionData::Binary { 5005 opcode: ref pattern5_0, 5006 args: ref pattern5_1, 5007 } = &pattern4_0 5008 { 5009 if let &Opcode::Imul = pattern5_0 { 5010 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 5011 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) { 5012 let pattern9_0 = C::inst_data(ctx, pattern8_0); 5013 if let &InstructionData::Unary { 5014 opcode: ref pattern10_0, 5015 arg: pattern10_1, 5016 } = &pattern9_0 5017 { 5018 match pattern10_0 { 5019 &Opcode::SwidenLow => { 5020 let pattern12_0 = C::value_type(ctx, pattern10_1); 5021 if pattern12_0 == I16X8 { 5022 if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) { 5023 let pattern15_0 = C::inst_data(ctx, pattern14_0); 5024 if let &InstructionData::Unary { 5025 opcode: ref pattern16_0, 5026 arg: pattern16_1, 5027 } = &pattern15_0 5028 { 5029 if let &Opcode::SwidenLow = pattern16_0 { 5030 let pattern18_0 = 5031 C::value_type(ctx, pattern16_1); 5032 if pattern18_0 == I16X8 { 5033 // Rule at src/isa/aarch64/lower.isle line 313. 5034 let expr0_0 = 5035 C::put_in_reg(ctx, pattern10_1); 5036 let expr1_0 = 5037 C::put_in_reg(ctx, pattern16_1); 5038 let expr2_0: bool = false; 5039 let expr3_0 = constructor_smull16( 5040 ctx, expr0_0, expr1_0, expr2_0, 5041 )?; 5042 let expr4_0 = 5043 constructor_output_reg(ctx, expr3_0)?; 5044 return Some(expr4_0); 5045 } 5046 } 5047 } 5048 } 5049 } 5050 } 5051 &Opcode::SwidenHigh => { 5052 let pattern12_0 = C::value_type(ctx, pattern10_1); 5053 if pattern12_0 == I16X8 { 5054 if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) { 5055 let pattern15_0 = C::inst_data(ctx, pattern14_0); 5056 if let &InstructionData::Unary { 5057 opcode: ref pattern16_0, 5058 arg: pattern16_1, 5059 } = &pattern15_0 5060 { 5061 if let &Opcode::SwidenHigh = pattern16_0 { 5062 let pattern18_0 = 5063 C::value_type(ctx, pattern16_1); 5064 if pattern18_0 == I16X8 { 5065 // Rule at src/isa/aarch64/lower.isle line 319. 5066 let expr0_0 = 5067 C::put_in_reg(ctx, pattern10_1); 5068 let expr1_0 = 5069 C::put_in_reg(ctx, pattern16_1); 5070 let expr2_0: bool = true; 5071 let expr3_0 = constructor_smull16( 5072 ctx, expr0_0, expr1_0, expr2_0, 5073 )?; 5074 let expr4_0 = 5075 constructor_output_reg(ctx, expr3_0)?; 5076 return Some(expr4_0); 5077 } 5078 } 5079 } 5080 } 5081 } 5082 } 5083 &Opcode::UwidenLow => { 5084 let pattern12_0 = C::value_type(ctx, pattern10_1); 5085 if pattern12_0 == I16X8 { 5086 if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) { 5087 let pattern15_0 = C::inst_data(ctx, pattern14_0); 5088 if let &InstructionData::Unary { 5089 opcode: ref pattern16_0, 5090 arg: pattern16_1, 5091 } = &pattern15_0 5092 { 5093 if let &Opcode::UwidenLow = pattern16_0 { 5094 let pattern18_0 = 5095 C::value_type(ctx, pattern16_1); 5096 if pattern18_0 == I16X8 { 5097 // Rule at src/isa/aarch64/lower.isle line 325. 5098 let expr0_0 = 5099 C::put_in_reg(ctx, pattern10_1); 5100 let expr1_0 = 5101 C::put_in_reg(ctx, pattern16_1); 5102 let expr2_0: bool = false; 5103 let expr3_0 = constructor_umull16( 5104 ctx, expr0_0, expr1_0, expr2_0, 5105 )?; 5106 let expr4_0 = 5107 constructor_output_reg(ctx, expr3_0)?; 5108 return Some(expr4_0); 5109 } 5110 } 5111 } 5112 } 5113 } 5114 } 5115 &Opcode::UwidenHigh => { 5116 let pattern12_0 = C::value_type(ctx, pattern10_1); 5117 if pattern12_0 == I16X8 { 5118 if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) { 5119 let pattern15_0 = C::inst_data(ctx, pattern14_0); 5120 if let &InstructionData::Unary { 5121 opcode: ref pattern16_0, 5122 arg: pattern16_1, 5123 } = &pattern15_0 5124 { 5125 if let &Opcode::UwidenHigh = pattern16_0 { 5126 let pattern18_0 = 5127 C::value_type(ctx, pattern16_1); 5128 if pattern18_0 == I16X8 { 5129 // Rule at src/isa/aarch64/lower.isle line 331. 5130 let expr0_0 = 5131 C::put_in_reg(ctx, pattern10_1); 5132 let expr1_0 = 5133 C::put_in_reg(ctx, pattern16_1); 5134 let expr2_0: bool = true; 5135 let expr3_0 = constructor_umull16( 5136 ctx, expr0_0, expr1_0, expr2_0, 5137 )?; 5138 let expr4_0 = 5139 constructor_output_reg(ctx, expr3_0)?; 5140 return Some(expr4_0); 5141 } 5142 } 5143 } 5144 } 5145 } 5146 } 5147 _ => {} 5148 } 5149 } 5150 } 5151 } 5152 } 5153 } 5154 if pattern2_0 == I64X2 { 5155 let pattern4_0 = C::inst_data(ctx, pattern0_0); 5156 if let &InstructionData::Binary { 5157 opcode: ref pattern5_0, 5158 args: ref pattern5_1, 5159 } = &pattern4_0 5160 { 5161 if let &Opcode::Imul = pattern5_0 { 5162 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 5163 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) { 5164 let pattern9_0 = C::inst_data(ctx, pattern8_0); 5165 if let &InstructionData::Unary { 5166 opcode: ref pattern10_0, 5167 arg: pattern10_1, 5168 } = &pattern9_0 5169 { 5170 match pattern10_0 { 5171 &Opcode::SwidenLow => { 5172 let pattern12_0 = C::value_type(ctx, pattern10_1); 5173 if pattern12_0 == I32X4 { 5174 if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) { 5175 let pattern15_0 = C::inst_data(ctx, pattern14_0); 5176 if let &InstructionData::Unary { 5177 opcode: ref pattern16_0, 5178 arg: pattern16_1, 5179 } = &pattern15_0 5180 { 5181 if let &Opcode::SwidenLow = pattern16_0 { 5182 let pattern18_0 = 5183 C::value_type(ctx, pattern16_1); 5184 if pattern18_0 == I32X4 { 5185 // Rule at src/isa/aarch64/lower.isle line 337. 5186 let expr0_0 = 5187 C::put_in_reg(ctx, pattern10_1); 5188 let expr1_0 = 5189 C::put_in_reg(ctx, pattern16_1); 5190 let expr2_0: bool = false; 5191 let expr3_0 = constructor_smull32( 5192 ctx, expr0_0, expr1_0, expr2_0, 5193 )?; 5194 let expr4_0 = 5195 constructor_output_reg(ctx, expr3_0)?; 5196 return Some(expr4_0); 5197 } 5198 } 5199 } 5200 } 5201 } 5202 } 5203 &Opcode::SwidenHigh => { 5204 let pattern12_0 = C::value_type(ctx, pattern10_1); 5205 if pattern12_0 == I32X4 { 5206 if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) { 5207 let pattern15_0 = C::inst_data(ctx, pattern14_0); 5208 if let &InstructionData::Unary { 5209 opcode: ref pattern16_0, 5210 arg: pattern16_1, 5211 } = &pattern15_0 5212 { 5213 if let &Opcode::SwidenHigh = pattern16_0 { 5214 let pattern18_0 = 5215 C::value_type(ctx, pattern16_1); 5216 if pattern18_0 == I32X4 { 5217 // Rule at src/isa/aarch64/lower.isle line 343. 5218 let expr0_0 = 5219 C::put_in_reg(ctx, pattern10_1); 5220 let expr1_0 = 5221 C::put_in_reg(ctx, pattern16_1); 5222 let expr2_0: bool = true; 5223 let expr3_0 = constructor_smull32( 5224 ctx, expr0_0, expr1_0, expr2_0, 5225 )?; 5226 let expr4_0 = 5227 constructor_output_reg(ctx, expr3_0)?; 5228 return Some(expr4_0); 5229 } 5230 } 5231 } 5232 } 5233 } 5234 } 5235 &Opcode::UwidenLow => { 5236 let pattern12_0 = C::value_type(ctx, pattern10_1); 5237 if pattern12_0 == I32X4 { 5238 if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) { 5239 let pattern15_0 = C::inst_data(ctx, pattern14_0); 5240 if let &InstructionData::Unary { 5241 opcode: ref pattern16_0, 5242 arg: pattern16_1, 5243 } = &pattern15_0 5244 { 5245 if let &Opcode::UwidenLow = pattern16_0 { 5246 let pattern18_0 = 5247 C::value_type(ctx, pattern16_1); 5248 if pattern18_0 == I32X4 { 5249 // Rule at src/isa/aarch64/lower.isle line 349. 5250 let expr0_0 = 5251 C::put_in_reg(ctx, pattern10_1); 5252 let expr1_0 = 5253 C::put_in_reg(ctx, pattern16_1); 5254 let expr2_0: bool = false; 5255 let expr3_0 = constructor_umull32( 5256 ctx, expr0_0, expr1_0, expr2_0, 5257 )?; 5258 let expr4_0 = 5259 constructor_output_reg(ctx, expr3_0)?; 5260 return Some(expr4_0); 5261 } 5262 } 5263 } 5264 } 5265 } 5266 } 5267 &Opcode::UwidenHigh => { 5268 let pattern12_0 = C::value_type(ctx, pattern10_1); 5269 if pattern12_0 == I32X4 { 5270 if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) { 5271 let pattern15_0 = C::inst_data(ctx, pattern14_0); 5272 if let &InstructionData::Unary { 5273 opcode: ref pattern16_0, 5274 arg: pattern16_1, 5275 } = &pattern15_0 5276 { 5277 if let &Opcode::UwidenHigh = pattern16_0 { 5278 let pattern18_0 = 5279 C::value_type(ctx, pattern16_1); 5280 if pattern18_0 == I32X4 { 5281 // Rule at src/isa/aarch64/lower.isle line 355. 5282 let expr0_0 = 5283 C::put_in_reg(ctx, pattern10_1); 5284 let expr1_0 = 5285 C::put_in_reg(ctx, pattern16_1); 5286 let expr2_0: bool = true; 5287 let expr3_0 = constructor_umull32( 5288 ctx, expr0_0, expr1_0, expr2_0, 5289 )?; 5290 let expr4_0 = 5291 constructor_output_reg(ctx, expr3_0)?; 5292 return Some(expr4_0); 5293 } 5294 } 5295 } 5296 } 5297 } 5298 } 5299 _ => {} 5300 } 5301 } 5302 } 5303 // Rule at src/isa/aarch64/lower.isle line 250. 5304 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 5305 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 5306 let expr2_0 = VectorSize::Size32x4; 5307 let expr3_0 = constructor_rev64(ctx, expr1_0, &expr2_0)?; 5308 let expr4_0 = VectorSize::Size32x4; 5309 let expr5_0 = constructor_mul(ctx, expr3_0, expr0_0, &expr4_0)?; 5310 let expr6_0: bool = false; 5311 let expr7_0 = constructor_xtn64(ctx, expr0_0, expr6_0)?; 5312 let expr8_0 = VectorSize::Size32x4; 5313 let expr9_0 = constructor_addp(ctx, expr5_0, expr5_0, &expr8_0)?; 5314 let expr10_0: bool = false; 5315 let expr11_0 = constructor_xtn64(ctx, expr1_0, expr10_0)?; 5316 let expr12_0: bool = false; 5317 let expr13_0 = constructor_shll32(ctx, expr9_0, expr12_0)?; 5318 let expr14_0: bool = false; 5319 let expr15_0 = constructor_umlal32(ctx, expr13_0, expr11_0, expr7_0, expr14_0)?; 5320 let expr16_0 = constructor_output_reg(ctx, expr15_0)?; 5321 return Some(expr16_0); 5322 } 5323 } 5324 } 5325 let pattern3_0 = C::inst_data(ctx, pattern0_0); 5326 match &pattern3_0 { 5327 &InstructionData::NullAry { 5328 opcode: ref pattern4_0, 5329 } => { 5330 if let &Opcode::Null = pattern4_0 { 5331 // Rule at src/isa/aarch64/lower.isle line 22. 5332 let expr0_0: u64 = 0; 5333 let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?; 5334 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 5335 return Some(expr2_0); 5336 } 5337 } 5338 &InstructionData::UnaryImm { 5339 opcode: ref pattern4_0, 5340 imm: pattern4_1, 5341 } => { 5342 if let &Opcode::Iconst = pattern4_0 { 5343 let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1); 5344 // Rule at src/isa/aarch64/lower.isle line 9. 5345 let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?; 5346 let expr1_0 = constructor_output_reg(ctx, expr0_0)?; 5347 return Some(expr1_0); 5348 } 5349 } 5350 &InstructionData::UnaryBool { 5351 opcode: ref pattern4_0, 5352 imm: pattern4_1, 5353 } => { 5354 if let &Opcode::Bconst = pattern4_0 { 5355 if pattern4_1 == true { 5356 // Rule at src/isa/aarch64/lower.isle line 17. 5357 let expr0_0: u64 = 1; 5358 let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?; 5359 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 5360 return Some(expr2_0); 5361 } 5362 if pattern4_1 == false { 5363 // Rule at src/isa/aarch64/lower.isle line 14. 5364 let expr0_0: u64 = 0; 5365 let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?; 5366 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 5367 return Some(expr2_0); 5368 } 5369 } 5370 } 5371 &InstructionData::Unary { 5372 opcode: ref pattern4_0, 5373 arg: pattern4_1, 5374 } => { 5375 match pattern4_0 { 5376 &Opcode::Bitrev => { 5377 // Rule at src/isa/aarch64/lower.isle line 1006. 5378 let expr0_0 = C::put_in_reg(ctx, pattern4_1); 5379 let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?; 5380 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 5381 return Some(expr2_0); 5382 } 5383 &Opcode::Clz => { 5384 // Rule at src/isa/aarch64/lower.isle line 1021. 5385 let expr0_0 = C::put_in_reg(ctx, pattern4_1); 5386 let expr1_0 = constructor_a64_clz(ctx, pattern2_0, expr0_0)?; 5387 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 5388 return Some(expr2_0); 5389 } 5390 &Opcode::Cls => { 5391 // Rule at src/isa/aarch64/lower.isle line 1088. 5392 let expr0_0 = C::put_in_reg(ctx, pattern4_1); 5393 let expr1_0 = constructor_a64_cls(ctx, pattern2_0, expr0_0)?; 5394 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 5395 return Some(expr2_0); 5396 } 5397 &Opcode::Ctz => { 5398 // Rule at src/isa/aarch64/lower.isle line 1054. 5399 let expr0_0 = C::put_in_reg(ctx, pattern4_1); 5400 let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?; 5401 let expr2_0 = constructor_a64_clz(ctx, pattern2_0, expr1_0)?; 5402 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 5403 return Some(expr3_0); 5404 } 5405 _ => {} 5406 } 5407 } 5408 _ => {} 5409 } 5410 if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) { 5411 let pattern4_0 = C::inst_data(ctx, pattern0_0); 5412 match &pattern4_0 { 5413 &InstructionData::Binary { 5414 opcode: ref pattern5_0, 5415 args: ref pattern5_1, 5416 } => { 5417 match pattern5_0 { 5418 &Opcode::Iadd => { 5419 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 5420 // Rule at src/isa/aarch64/lower.isle line 81. 5421 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 5422 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 5423 let expr2_0 = constructor_vector_size(ctx, pattern2_0)?; 5424 let expr3_0 = constructor_add_vec(ctx, expr0_0, expr1_0, &expr2_0)?; 5425 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 5426 return Some(expr4_0); 5427 } 5428 &Opcode::Isub => { 5429 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 5430 // Rule at src/isa/aarch64/lower.isle line 132. 5431 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 5432 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 5433 let expr2_0 = constructor_vector_size(ctx, pattern2_0)?; 5434 let expr3_0 = constructor_sub_vec(ctx, expr0_0, expr1_0, &expr2_0)?; 5435 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 5436 return Some(expr4_0); 5437 } 5438 _ => {} 5439 } 5440 } 5441 &InstructionData::FloatCompare { 5442 opcode: ref pattern5_0, 5443 args: ref pattern5_1, 5444 cond: ref pattern5_2, 5445 } => { 5446 if let &Opcode::Fcmp = pattern5_0 { 5447 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 5448 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) { 5449 let pattern9_0 = C::inst_data(ctx, pattern8_0); 5450 if let &InstructionData::Unary { 5451 opcode: ref pattern10_0, 5452 arg: pattern10_1, 5453 } = &pattern9_0 5454 { 5455 if let &Opcode::Splat = pattern10_0 { 5456 if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) { 5457 let pattern13_0 = C::inst_data(ctx, pattern12_0); 5458 match &pattern13_0 { 5459 &InstructionData::UnaryIeee32 { 5460 opcode: ref pattern14_0, 5461 imm: pattern14_1, 5462 } => { 5463 if let &Opcode::F32const = pattern14_0 { 5464 if let Some(pattern16_0) = 5465 C::zero_value_f32(ctx, pattern14_1) 5466 { 5467 if let Some(pattern17_0) = 5468 C::fcmp_zero_cond(ctx, pattern5_2) 5469 { 5470 // Rule at src/isa/aarch64/lower.isle line 1162. 5471 let expr0_0 = 5472 C::put_in_reg(ctx, pattern7_1); 5473 let expr1_0 = constructor_vector_size( 5474 ctx, pattern2_0, 5475 )?; 5476 let expr2_0 = 5477 constructor_float_cmp_zero_swap( 5478 ctx, 5479 &pattern17_0, 5480 expr0_0, 5481 &expr1_0, 5482 )?; 5483 let expr3_0 = 5484 C::value_reg(ctx, expr2_0); 5485 let expr4_0 = C::output(ctx, expr3_0); 5486 return Some(expr4_0); 5487 } 5488 if let Some(pattern17_0) = 5489 C::fcmp_zero_cond_not_eq( 5490 ctx, pattern5_2, 5491 ) 5492 { 5493 // Rule at src/isa/aarch64/lower.isle line 1157. 5494 let expr0_0 = 5495 C::put_in_reg(ctx, pattern7_1); 5496 let expr1_0 = constructor_vector_size( 5497 ctx, pattern2_0, 5498 )?; 5499 let expr2_0 = constructor_fcmeq0( 5500 ctx, expr0_0, &expr1_0, 5501 )?; 5502 let expr3_0 = constructor_not( 5503 ctx, expr2_0, &expr1_0, 5504 )?; 5505 let expr4_0 = 5506 C::value_reg(ctx, expr3_0); 5507 let expr5_0 = C::output(ctx, expr4_0); 5508 return Some(expr5_0); 5509 } 5510 } 5511 } 5512 } 5513 &InstructionData::UnaryIeee64 { 5514 opcode: ref pattern14_0, 5515 imm: pattern14_1, 5516 } => { 5517 if let &Opcode::F64const = pattern14_0 { 5518 if let Some(pattern16_0) = 5519 C::zero_value_f64(ctx, pattern14_1) 5520 { 5521 if let Some(pattern17_0) = 5522 C::fcmp_zero_cond(ctx, pattern5_2) 5523 { 5524 // Rule at src/isa/aarch64/lower.isle line 1184. 5525 let expr0_0 = 5526 C::put_in_reg(ctx, pattern7_1); 5527 let expr1_0 = constructor_vector_size( 5528 ctx, pattern2_0, 5529 )?; 5530 let expr2_0 = 5531 constructor_float_cmp_zero_swap( 5532 ctx, 5533 &pattern17_0, 5534 expr0_0, 5535 &expr1_0, 5536 )?; 5537 let expr3_0 = 5538 C::value_reg(ctx, expr2_0); 5539 let expr4_0 = C::output(ctx, expr3_0); 5540 return Some(expr4_0); 5541 } 5542 if let Some(pattern17_0) = 5543 C::fcmp_zero_cond_not_eq( 5544 ctx, pattern5_2, 5545 ) 5546 { 5547 // Rule at src/isa/aarch64/lower.isle line 1179. 5548 let expr0_0 = 5549 C::put_in_reg(ctx, pattern7_1); 5550 let expr1_0 = constructor_vector_size( 5551 ctx, pattern2_0, 5552 )?; 5553 let expr2_0 = constructor_fcmeq0( 5554 ctx, expr0_0, &expr1_0, 5555 )?; 5556 let expr3_0 = constructor_not( 5557 ctx, expr2_0, &expr1_0, 5558 )?; 5559 let expr4_0 = 5560 C::value_reg(ctx, expr3_0); 5561 let expr5_0 = C::output(ctx, expr4_0); 5562 return Some(expr5_0); 5563 } 5564 } 5565 } 5566 } 5567 _ => {} 5568 } 5569 } 5570 } 5571 } 5572 } 5573 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { 5574 let pattern9_0 = C::inst_data(ctx, pattern8_0); 5575 if let &InstructionData::Unary { 5576 opcode: ref pattern10_0, 5577 arg: pattern10_1, 5578 } = &pattern9_0 5579 { 5580 if let &Opcode::Splat = pattern10_0 { 5581 if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) { 5582 let pattern13_0 = C::inst_data(ctx, pattern12_0); 5583 match &pattern13_0 { 5584 &InstructionData::UnaryIeee32 { 5585 opcode: ref pattern14_0, 5586 imm: pattern14_1, 5587 } => { 5588 if let &Opcode::F32const = pattern14_0 { 5589 if let Some(pattern16_0) = 5590 C::zero_value_f32(ctx, pattern14_1) 5591 { 5592 if let Some(pattern17_0) = 5593 C::fcmp_zero_cond(ctx, pattern5_2) 5594 { 5595 // Rule at src/isa/aarch64/lower.isle line 1152. 5596 let expr0_0 = 5597 C::put_in_reg(ctx, pattern7_0); 5598 let expr1_0 = constructor_vector_size( 5599 ctx, pattern2_0, 5600 )?; 5601 let expr2_0 = 5602 constructor_float_cmp_zero( 5603 ctx, 5604 &pattern17_0, 5605 expr0_0, 5606 &expr1_0, 5607 )?; 5608 let expr3_0 = 5609 C::value_reg(ctx, expr2_0); 5610 let expr4_0 = C::output(ctx, expr3_0); 5611 return Some(expr4_0); 5612 } 5613 if let Some(pattern17_0) = 5614 C::fcmp_zero_cond_not_eq( 5615 ctx, pattern5_2, 5616 ) 5617 { 5618 // Rule at src/isa/aarch64/lower.isle line 1147. 5619 let expr0_0 = 5620 C::put_in_reg(ctx, pattern7_0); 5621 let expr1_0 = constructor_vector_size( 5622 ctx, pattern2_0, 5623 )?; 5624 let expr2_0 = constructor_fcmeq0( 5625 ctx, expr0_0, &expr1_0, 5626 )?; 5627 let expr3_0 = constructor_not( 5628 ctx, expr2_0, &expr1_0, 5629 )?; 5630 let expr4_0 = 5631 C::value_reg(ctx, expr3_0); 5632 let expr5_0 = C::output(ctx, expr4_0); 5633 return Some(expr5_0); 5634 } 5635 } 5636 } 5637 } 5638 &InstructionData::UnaryIeee64 { 5639 opcode: ref pattern14_0, 5640 imm: pattern14_1, 5641 } => { 5642 if let &Opcode::F64const = pattern14_0 { 5643 if let Some(pattern16_0) = 5644 C::zero_value_f64(ctx, pattern14_1) 5645 { 5646 if let Some(pattern17_0) = 5647 C::fcmp_zero_cond(ctx, pattern5_2) 5648 { 5649 // Rule at src/isa/aarch64/lower.isle line 1174. 5650 let expr0_0 = 5651 C::put_in_reg(ctx, pattern7_0); 5652 let expr1_0 = constructor_vector_size( 5653 ctx, pattern2_0, 5654 )?; 5655 let expr2_0 = 5656 constructor_float_cmp_zero( 5657 ctx, 5658 &pattern17_0, 5659 expr0_0, 5660 &expr1_0, 5661 )?; 5662 let expr3_0 = 5663 C::value_reg(ctx, expr2_0); 5664 let expr4_0 = C::output(ctx, expr3_0); 5665 return Some(expr4_0); 5666 } 5667 if let Some(pattern17_0) = 5668 C::fcmp_zero_cond_not_eq( 5669 ctx, pattern5_2, 5670 ) 5671 { 5672 // Rule at src/isa/aarch64/lower.isle line 1169. 5673 let expr0_0 = 5674 C::put_in_reg(ctx, pattern7_0); 5675 let expr1_0 = constructor_vector_size( 5676 ctx, pattern2_0, 5677 )?; 5678 let expr2_0 = constructor_fcmeq0( 5679 ctx, expr0_0, &expr1_0, 5680 )?; 5681 let expr3_0 = constructor_not( 5682 ctx, expr2_0, &expr1_0, 5683 )?; 5684 let expr4_0 = 5685 C::value_reg(ctx, expr3_0); 5686 let expr5_0 = C::output(ctx, expr4_0); 5687 return Some(expr5_0); 5688 } 5689 } 5690 } 5691 } 5692 _ => {} 5693 } 5694 } 5695 } 5696 } 5697 } 5698 } 5699 } 5700 &InstructionData::IntCompare { 5701 opcode: ref pattern5_0, 5702 args: ref pattern5_1, 5703 cond: ref pattern5_2, 5704 } => { 5705 if let &Opcode::Icmp = pattern5_0 { 5706 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 5707 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) { 5708 let pattern9_0 = C::inst_data(ctx, pattern8_0); 5709 if let &InstructionData::Unary { 5710 opcode: ref pattern10_0, 5711 arg: pattern10_1, 5712 } = &pattern9_0 5713 { 5714 if let &Opcode::Splat = pattern10_0 { 5715 if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) { 5716 let pattern13_0 = C::inst_data(ctx, pattern12_0); 5717 if let &InstructionData::UnaryImm { 5718 opcode: ref pattern14_0, 5719 imm: pattern14_1, 5720 } = &pattern13_0 5721 { 5722 if let &Opcode::Iconst = pattern14_0 { 5723 if let Some(pattern16_0) = 5724 C::zero_value(ctx, pattern14_1) 5725 { 5726 if let Some(pattern17_0) = 5727 C::icmp_zero_cond(ctx, pattern5_2) 5728 { 5729 // Rule at src/isa/aarch64/lower.isle line 1206. 5730 let expr0_0 = 5731 C::put_in_reg(ctx, pattern7_1); 5732 let expr1_0 = constructor_vector_size( 5733 ctx, pattern2_0, 5734 )?; 5735 let expr2_0 = 5736 constructor_int_cmp_zero_swap( 5737 ctx, 5738 &pattern17_0, 5739 expr0_0, 5740 &expr1_0, 5741 )?; 5742 let expr3_0 = C::value_reg(ctx, expr2_0); 5743 let expr4_0 = C::output(ctx, expr3_0); 5744 return Some(expr4_0); 5745 } 5746 if let Some(pattern17_0) = 5747 C::icmp_zero_cond_not_eq(ctx, pattern5_2) 5748 { 5749 // Rule at src/isa/aarch64/lower.isle line 1201. 5750 let expr0_0 = 5751 C::put_in_reg(ctx, pattern7_1); 5752 let expr1_0 = constructor_vector_size( 5753 ctx, pattern2_0, 5754 )?; 5755 let expr2_0 = constructor_cmeq0( 5756 ctx, expr0_0, &expr1_0, 5757 )?; 5758 let expr3_0 = constructor_not( 5759 ctx, expr2_0, &expr1_0, 5760 )?; 5761 let expr4_0 = C::value_reg(ctx, expr3_0); 5762 let expr5_0 = C::output(ctx, expr4_0); 5763 return Some(expr5_0); 5764 } 5765 } 5766 } 5767 } 5768 } 5769 } 5770 } 5771 } 5772 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { 5773 let pattern9_0 = C::inst_data(ctx, pattern8_0); 5774 if let &InstructionData::Unary { 5775 opcode: ref pattern10_0, 5776 arg: pattern10_1, 5777 } = &pattern9_0 5778 { 5779 if let &Opcode::Splat = pattern10_0 { 5780 if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) { 5781 let pattern13_0 = C::inst_data(ctx, pattern12_0); 5782 if let &InstructionData::UnaryImm { 5783 opcode: ref pattern14_0, 5784 imm: pattern14_1, 5785 } = &pattern13_0 5786 { 5787 if let &Opcode::Iconst = pattern14_0 { 5788 if let Some(pattern16_0) = 5789 C::zero_value(ctx, pattern14_1) 5790 { 5791 if let Some(pattern17_0) = 5792 C::icmp_zero_cond(ctx, pattern5_2) 5793 { 5794 // Rule at src/isa/aarch64/lower.isle line 1196. 5795 let expr0_0 = 5796 C::put_in_reg(ctx, pattern7_0); 5797 let expr1_0 = constructor_vector_size( 5798 ctx, pattern2_0, 5799 )?; 5800 let expr2_0 = constructor_int_cmp_zero( 5801 ctx, 5802 &pattern17_0, 5803 expr0_0, 5804 &expr1_0, 5805 )?; 5806 let expr3_0 = C::value_reg(ctx, expr2_0); 5807 let expr4_0 = C::output(ctx, expr3_0); 5808 return Some(expr4_0); 5809 } 5810 if let Some(pattern17_0) = 5811 C::icmp_zero_cond_not_eq(ctx, pattern5_2) 5812 { 5813 // Rule at src/isa/aarch64/lower.isle line 1191. 5814 let expr0_0 = 5815 C::put_in_reg(ctx, pattern7_0); 5816 let expr1_0 = constructor_vector_size( 5817 ctx, pattern2_0, 5818 )?; 5819 let expr2_0 = constructor_cmeq0( 5820 ctx, expr0_0, &expr1_0, 5821 )?; 5822 let expr3_0 = constructor_not( 5823 ctx, expr2_0, &expr1_0, 5824 )?; 5825 let expr4_0 = C::value_reg(ctx, expr3_0); 5826 let expr5_0 = C::output(ctx, expr4_0); 5827 return Some(expr5_0); 5828 } 5829 } 5830 } 5831 } 5832 } 5833 } 5834 } 5835 } 5836 } 5837 } 5838 _ => {} 5839 } 5840 } 5841 if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) { 5842 let pattern4_0 = C::inst_data(ctx, pattern0_0); 5843 if let &InstructionData::Binary { 5844 opcode: ref pattern5_0, 5845 args: ref pattern5_1, 5846 } = &pattern4_0 5847 { 5848 match pattern5_0 { 5849 &Opcode::Rotl => { 5850 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 5851 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { 5852 let pattern9_0 = C::inst_data(ctx, pattern8_0); 5853 if let &InstructionData::UnaryImm { 5854 opcode: ref pattern10_0, 5855 imm: pattern10_1, 5856 } = &pattern9_0 5857 { 5858 if let &Opcode::Iconst = pattern10_0 { 5859 let mut closure12 = || { 5860 let expr0_0 = 5861 C::imm_shift_from_imm64(ctx, pattern3_0, pattern10_1)?; 5862 return Some(expr0_0); 5863 }; 5864 if let Some(pattern12_0) = closure12() { 5865 // Rule at src/isa/aarch64/lower.isle line 854. 5866 let expr0_0 = 5867 constructor_put_in_reg_zext32(ctx, pattern7_0)?; 5868 let expr1_0 = 5869 C::negate_imm_shift(ctx, pattern3_0, pattern12_0); 5870 let expr2_0 = constructor_small_rotr_imm( 5871 ctx, pattern3_0, expr0_0, expr1_0, 5872 )?; 5873 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 5874 return Some(expr3_0); 5875 } 5876 } 5877 } 5878 } 5879 // Rule at src/isa/aarch64/lower.isle line 849. 5880 let expr0_0: Type = I32; 5881 let expr1_0 = C::zero_reg(ctx); 5882 let expr2_0 = C::put_in_reg(ctx, pattern7_1); 5883 let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?; 5884 let expr4_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?; 5885 let expr5_0 = constructor_small_rotr(ctx, pattern3_0, expr4_0, expr3_0)?; 5886 let expr6_0 = constructor_output_reg(ctx, expr5_0)?; 5887 return Some(expr6_0); 5888 } 5889 &Opcode::Rotr => { 5890 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 5891 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { 5892 let pattern9_0 = C::inst_data(ctx, pattern8_0); 5893 if let &InstructionData::UnaryImm { 5894 opcode: ref pattern10_0, 5895 imm: pattern10_1, 5896 } = &pattern9_0 5897 { 5898 if let &Opcode::Iconst = pattern10_0 { 5899 let mut closure12 = || { 5900 let expr0_0 = 5901 C::imm_shift_from_imm64(ctx, pattern3_0, pattern10_1)?; 5902 return Some(expr0_0); 5903 }; 5904 if let Some(pattern12_0) = closure12() { 5905 // Rule at src/isa/aarch64/lower.isle line 917. 5906 let expr0_0 = 5907 constructor_put_in_reg_zext32(ctx, pattern7_0)?; 5908 let expr1_0 = constructor_small_rotr_imm( 5909 ctx, 5910 pattern3_0, 5911 expr0_0, 5912 pattern12_0, 5913 )?; 5914 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 5915 return Some(expr2_0); 5916 } 5917 } 5918 } 5919 } 5920 // Rule at src/isa/aarch64/lower.isle line 905. 5921 let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?; 5922 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 5923 let expr2_0 = constructor_small_rotr(ctx, pattern3_0, expr0_0, expr1_0)?; 5924 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 5925 return Some(expr3_0); 5926 } 5927 _ => {} 5928 } 5929 } 5930 } 5931 if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) { 5932 let pattern4_0 = C::inst_data(ctx, pattern0_0); 5933 if let &InstructionData::Binary { 5934 opcode: ref pattern5_0, 5935 args: ref pattern5_1, 5936 } = &pattern4_0 5937 { 5938 match pattern5_0 { 5939 &Opcode::Umulhi => { 5940 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 5941 // Rule at src/isa/aarch64/lower.isle line 377. 5942 let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?; 5943 let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?; 5944 let expr2_0: Type = I64; 5945 let expr3_0 = C::zero_reg(ctx); 5946 let expr4_0 = constructor_madd(ctx, expr2_0, expr0_0, expr1_0, expr3_0)?; 5947 let expr5_0: Type = I64; 5948 let expr6_0 = C::ty_bits(ctx, pattern3_0)?; 5949 let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0); 5950 let expr8_0 = constructor_lsr_imm(ctx, expr5_0, expr4_0, expr7_0)?; 5951 let expr9_0 = C::value_reg(ctx, expr8_0); 5952 let expr10_0 = C::output(ctx, expr9_0); 5953 return Some(expr10_0); 5954 } 5955 &Opcode::Smulhi => { 5956 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 5957 // Rule at src/isa/aarch64/lower.isle line 365. 5958 let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?; 5959 let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?; 5960 let expr2_0: Type = I64; 5961 let expr3_0 = C::zero_reg(ctx); 5962 let expr4_0 = constructor_madd(ctx, expr2_0, expr0_0, expr1_0, expr3_0)?; 5963 let expr5_0: Type = I64; 5964 let expr6_0 = C::ty_bits(ctx, pattern3_0)?; 5965 let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0); 5966 let expr8_0 = constructor_asr_imm(ctx, expr5_0, expr4_0, expr7_0)?; 5967 let expr9_0 = constructor_output_reg(ctx, expr8_0)?; 5968 return Some(expr9_0); 5969 } 5970 &Opcode::Band => { 5971 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 5972 // Rule at src/isa/aarch64/lower.isle line 593. 5973 let expr0_0 = ALUOp::And; 5974 let expr1_0 = constructor_alu_rs_imm_logic_commutative( 5975 ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1, 5976 )?; 5977 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 5978 return Some(expr2_0); 5979 } 5980 &Opcode::Bor => { 5981 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 5982 // Rule at src/isa/aarch64/lower.isle line 606. 5983 let expr0_0 = ALUOp::Orr; 5984 let expr1_0 = constructor_alu_rs_imm_logic_commutative( 5985 ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1, 5986 )?; 5987 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 5988 return Some(expr2_0); 5989 } 5990 &Opcode::Bxor => { 5991 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 5992 // Rule at src/isa/aarch64/lower.isle line 619. 5993 let expr0_0 = ALUOp::Eor; 5994 let expr1_0 = constructor_alu_rs_imm_logic_commutative( 5995 ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1, 5996 )?; 5997 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 5998 return Some(expr2_0); 5999 } 6000 &Opcode::BandNot => { 6001 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6002 // Rule at src/isa/aarch64/lower.isle line 632. 6003 let expr0_0 = ALUOp::AndNot; 6004 let expr1_0 = constructor_alu_rs_imm_logic( 6005 ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1, 6006 )?; 6007 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6008 return Some(expr2_0); 6009 } 6010 &Opcode::BorNot => { 6011 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6012 // Rule at src/isa/aarch64/lower.isle line 645. 6013 let expr0_0 = ALUOp::OrrNot; 6014 let expr1_0 = constructor_alu_rs_imm_logic( 6015 ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1, 6016 )?; 6017 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6018 return Some(expr2_0); 6019 } 6020 &Opcode::BxorNot => { 6021 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6022 // Rule at src/isa/aarch64/lower.isle line 655. 6023 let expr0_0 = ALUOp::EorNot; 6024 let expr1_0: Type = I32; 6025 let expr2_0 = constructor_alu_rs_imm_logic( 6026 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1, 6027 )?; 6028 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 6029 return Some(expr3_0); 6030 } 6031 &Opcode::Ishl => { 6032 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6033 // Rule at src/isa/aarch64/lower.isle line 666. 6034 let expr0_0 = ALUOp::Lsl; 6035 let expr1_0 = C::put_in_reg(ctx, pattern7_0); 6036 let expr2_0 = 6037 constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?; 6038 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 6039 return Some(expr3_0); 6040 } 6041 &Opcode::Ushr => { 6042 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6043 // Rule at src/isa/aarch64/lower.isle line 751. 6044 let expr0_0 = ALUOp::Lsr; 6045 let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?; 6046 let expr2_0 = 6047 constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?; 6048 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 6049 return Some(expr3_0); 6050 } 6051 &Opcode::Sshr => { 6052 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6053 // Rule at src/isa/aarch64/lower.isle line 798. 6054 let expr0_0 = ALUOp::Asr; 6055 let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?; 6056 let expr2_0 = 6057 constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?; 6058 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 6059 return Some(expr3_0); 6060 } 6061 _ => {} 6062 } 6063 } 6064 } 6065 if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) { 6066 let pattern4_0 = C::inst_data(ctx, pattern0_0); 6067 match &pattern4_0 { 6068 &InstructionData::Binary { 6069 opcode: ref pattern5_0, 6070 args: ref pattern5_1, 6071 } => { 6072 match pattern5_0 { 6073 &Opcode::Iadd => { 6074 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6075 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) { 6076 let pattern9_0 = C::inst_data(ctx, pattern8_0); 6077 match &pattern9_0 { 6078 &InstructionData::UnaryImm { 6079 opcode: ref pattern10_0, 6080 imm: pattern10_1, 6081 } => { 6082 if let &Opcode::Iconst = pattern10_0 { 6083 let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1); 6084 if let Some(pattern13_0) = 6085 C::imm12_from_u64(ctx, pattern12_0) 6086 { 6087 // Rule at src/isa/aarch64/lower.isle line 37. 6088 let expr0_0 = C::put_in_reg(ctx, pattern7_1); 6089 let expr1_0 = constructor_add_imm( 6090 ctx, 6091 pattern3_0, 6092 expr0_0, 6093 pattern13_0, 6094 )?; 6095 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6096 return Some(expr2_0); 6097 } 6098 if let Some(pattern13_0) = 6099 C::imm12_from_negated_u64(ctx, pattern12_0) 6100 { 6101 // Rule at src/isa/aarch64/lower.isle line 45. 6102 let expr0_0 = C::put_in_reg(ctx, pattern7_1); 6103 let expr1_0 = constructor_sub_imm( 6104 ctx, 6105 pattern3_0, 6106 expr0_0, 6107 pattern13_0, 6108 )?; 6109 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6110 return Some(expr2_0); 6111 } 6112 } 6113 } 6114 &InstructionData::Binary { 6115 opcode: ref pattern10_0, 6116 args: ref pattern10_1, 6117 } => { 6118 match pattern10_0 { 6119 &Opcode::Imul => { 6120 let (pattern12_0, pattern12_1) = 6121 C::unpack_value_array_2(ctx, pattern10_1); 6122 // Rule at src/isa/aarch64/lower.isle line 72. 6123 let expr0_0 = C::put_in_reg(ctx, pattern12_0); 6124 let expr1_0 = C::put_in_reg(ctx, pattern12_1); 6125 let expr2_0 = C::put_in_reg(ctx, pattern7_1); 6126 let expr3_0 = constructor_madd( 6127 ctx, pattern3_0, expr0_0, expr1_0, expr2_0, 6128 )?; 6129 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6130 return Some(expr4_0); 6131 } 6132 &Opcode::Ishl => { 6133 let (pattern12_0, pattern12_1) = 6134 C::unpack_value_array_2(ctx, pattern10_1); 6135 if let Some(pattern13_0) = 6136 C::def_inst(ctx, pattern12_1) 6137 { 6138 let pattern14_0 = 6139 C::inst_data(ctx, pattern13_0); 6140 if let &InstructionData::UnaryImm { 6141 opcode: ref pattern15_0, 6142 imm: pattern15_1, 6143 } = &pattern14_0 6144 { 6145 if let &Opcode::Iconst = pattern15_0 { 6146 let mut closure17 = || { 6147 let expr0_0 = C::lshl_from_imm64( 6148 ctx, 6149 pattern3_0, 6150 pattern15_1, 6151 )?; 6152 return Some(expr0_0); 6153 }; 6154 if let Some(pattern17_0) = closure17() { 6155 // Rule at src/isa/aarch64/lower.isle line 63. 6156 let expr0_0 = 6157 C::put_in_reg(ctx, pattern7_1); 6158 let expr1_0 = 6159 C::put_in_reg(ctx, pattern12_0); 6160 let expr2_0 = 6161 constructor_add_shift( 6162 ctx, 6163 pattern3_0, 6164 expr0_0, 6165 expr1_0, 6166 pattern17_0, 6167 )?; 6168 let expr3_0 = 6169 constructor_output_reg( 6170 ctx, expr2_0, 6171 )?; 6172 return Some(expr3_0); 6173 } 6174 } 6175 } 6176 } 6177 } 6178 _ => {} 6179 } 6180 } 6181 _ => {} 6182 } 6183 } 6184 if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0) 6185 { 6186 // Rule at src/isa/aarch64/lower.isle line 53. 6187 let expr0_0 = C::put_in_reg(ctx, pattern7_1); 6188 let expr1_0 = 6189 constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?; 6190 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6191 return Some(expr2_0); 6192 } 6193 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { 6194 let pattern9_0 = C::inst_data(ctx, pattern8_0); 6195 match &pattern9_0 { 6196 &InstructionData::UnaryImm { 6197 opcode: ref pattern10_0, 6198 imm: pattern10_1, 6199 } => { 6200 if let &Opcode::Iconst = pattern10_0 { 6201 let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1); 6202 if let Some(pattern13_0) = 6203 C::imm12_from_u64(ctx, pattern12_0) 6204 { 6205 // Rule at src/isa/aarch64/lower.isle line 34. 6206 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6207 let expr1_0 = constructor_add_imm( 6208 ctx, 6209 pattern3_0, 6210 expr0_0, 6211 pattern13_0, 6212 )?; 6213 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6214 return Some(expr2_0); 6215 } 6216 if let Some(pattern13_0) = 6217 C::imm12_from_negated_u64(ctx, pattern12_0) 6218 { 6219 // Rule at src/isa/aarch64/lower.isle line 42. 6220 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6221 let expr1_0 = constructor_sub_imm( 6222 ctx, 6223 pattern3_0, 6224 expr0_0, 6225 pattern13_0, 6226 )?; 6227 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6228 return Some(expr2_0); 6229 } 6230 } 6231 } 6232 &InstructionData::Binary { 6233 opcode: ref pattern10_0, 6234 args: ref pattern10_1, 6235 } => { 6236 match pattern10_0 { 6237 &Opcode::Imul => { 6238 let (pattern12_0, pattern12_1) = 6239 C::unpack_value_array_2(ctx, pattern10_1); 6240 // Rule at src/isa/aarch64/lower.isle line 69. 6241 let expr0_0 = C::put_in_reg(ctx, pattern12_0); 6242 let expr1_0 = C::put_in_reg(ctx, pattern12_1); 6243 let expr2_0 = C::put_in_reg(ctx, pattern7_0); 6244 let expr3_0 = constructor_madd( 6245 ctx, pattern3_0, expr0_0, expr1_0, expr2_0, 6246 )?; 6247 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6248 return Some(expr4_0); 6249 } 6250 &Opcode::Ishl => { 6251 let (pattern12_0, pattern12_1) = 6252 C::unpack_value_array_2(ctx, pattern10_1); 6253 if let Some(pattern13_0) = 6254 C::def_inst(ctx, pattern12_1) 6255 { 6256 let pattern14_0 = 6257 C::inst_data(ctx, pattern13_0); 6258 if let &InstructionData::UnaryImm { 6259 opcode: ref pattern15_0, 6260 imm: pattern15_1, 6261 } = &pattern14_0 6262 { 6263 if let &Opcode::Iconst = pattern15_0 { 6264 let mut closure17 = || { 6265 let expr0_0 = C::lshl_from_imm64( 6266 ctx, 6267 pattern3_0, 6268 pattern15_1, 6269 )?; 6270 return Some(expr0_0); 6271 }; 6272 if let Some(pattern17_0) = closure17() { 6273 // Rule at src/isa/aarch64/lower.isle line 58. 6274 let expr0_0 = 6275 C::put_in_reg(ctx, pattern7_0); 6276 let expr1_0 = 6277 C::put_in_reg(ctx, pattern12_0); 6278 let expr2_0 = 6279 constructor_add_shift( 6280 ctx, 6281 pattern3_0, 6282 expr0_0, 6283 expr1_0, 6284 pattern17_0, 6285 )?; 6286 let expr3_0 = 6287 constructor_output_reg( 6288 ctx, expr2_0, 6289 )?; 6290 return Some(expr3_0); 6291 } 6292 } 6293 } 6294 } 6295 } 6296 _ => {} 6297 } 6298 } 6299 _ => {} 6300 } 6301 } 6302 if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1) 6303 { 6304 // Rule at src/isa/aarch64/lower.isle line 50. 6305 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6306 let expr1_0 = 6307 constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?; 6308 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6309 return Some(expr2_0); 6310 } 6311 // Rule at src/isa/aarch64/lower.isle line 30. 6312 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6313 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 6314 let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, expr1_0)?; 6315 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 6316 return Some(expr3_0); 6317 } 6318 &Opcode::Isub => { 6319 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6320 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { 6321 let pattern9_0 = C::inst_data(ctx, pattern8_0); 6322 match &pattern9_0 { 6323 &InstructionData::UnaryImm { 6324 opcode: ref pattern10_0, 6325 imm: pattern10_1, 6326 } => { 6327 if let &Opcode::Iconst = pattern10_0 { 6328 let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1); 6329 if let Some(pattern13_0) = 6330 C::imm12_from_u64(ctx, pattern12_0) 6331 { 6332 // Rule at src/isa/aarch64/lower.isle line 111. 6333 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6334 let expr1_0 = constructor_sub_imm( 6335 ctx, 6336 pattern3_0, 6337 expr0_0, 6338 pattern13_0, 6339 )?; 6340 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6341 return Some(expr2_0); 6342 } 6343 if let Some(pattern13_0) = 6344 C::imm12_from_negated_u64(ctx, pattern12_0) 6345 { 6346 // Rule at src/isa/aarch64/lower.isle line 116. 6347 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6348 let expr1_0 = constructor_add_imm( 6349 ctx, 6350 pattern3_0, 6351 expr0_0, 6352 pattern13_0, 6353 )?; 6354 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6355 return Some(expr2_0); 6356 } 6357 } 6358 } 6359 &InstructionData::Binary { 6360 opcode: ref pattern10_0, 6361 args: ref pattern10_1, 6362 } => { 6363 match pattern10_0 { 6364 &Opcode::Imul => { 6365 let (pattern12_0, pattern12_1) = 6366 C::unpack_value_array_2(ctx, pattern10_1); 6367 // Rule at src/isa/aarch64/lower.isle line 76. 6368 let expr0_0 = C::put_in_reg(ctx, pattern12_0); 6369 let expr1_0 = C::put_in_reg(ctx, pattern12_1); 6370 let expr2_0 = C::put_in_reg(ctx, pattern7_0); 6371 let expr3_0 = constructor_msub( 6372 ctx, pattern3_0, expr0_0, expr1_0, expr2_0, 6373 )?; 6374 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6375 return Some(expr4_0); 6376 } 6377 &Opcode::Ishl => { 6378 let (pattern12_0, pattern12_1) = 6379 C::unpack_value_array_2(ctx, pattern10_1); 6380 if let Some(pattern13_0) = 6381 C::def_inst(ctx, pattern12_1) 6382 { 6383 let pattern14_0 = 6384 C::inst_data(ctx, pattern13_0); 6385 if let &InstructionData::UnaryImm { 6386 opcode: ref pattern15_0, 6387 imm: pattern15_1, 6388 } = &pattern14_0 6389 { 6390 if let &Opcode::Iconst = pattern15_0 { 6391 let mut closure17 = || { 6392 let expr0_0 = C::lshl_from_imm64( 6393 ctx, 6394 pattern3_0, 6395 pattern15_1, 6396 )?; 6397 return Some(expr0_0); 6398 }; 6399 if let Some(pattern17_0) = closure17() { 6400 // Rule at src/isa/aarch64/lower.isle line 126. 6401 let expr0_0 = 6402 C::put_in_reg(ctx, pattern7_0); 6403 let expr1_0 = 6404 C::put_in_reg(ctx, pattern12_0); 6405 let expr2_0 = 6406 constructor_sub_shift( 6407 ctx, 6408 pattern3_0, 6409 expr0_0, 6410 expr1_0, 6411 pattern17_0, 6412 )?; 6413 let expr3_0 = 6414 constructor_output_reg( 6415 ctx, expr2_0, 6416 )?; 6417 return Some(expr3_0); 6418 } 6419 } 6420 } 6421 } 6422 } 6423 _ => {} 6424 } 6425 } 6426 _ => {} 6427 } 6428 } 6429 if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1) 6430 { 6431 // Rule at src/isa/aarch64/lower.isle line 121. 6432 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6433 let expr1_0 = 6434 constructor_sub_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?; 6435 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6436 return Some(expr2_0); 6437 } 6438 // Rule at src/isa/aarch64/lower.isle line 107. 6439 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6440 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 6441 let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?; 6442 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 6443 return Some(expr3_0); 6444 } 6445 &Opcode::Imul => { 6446 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6447 // Rule at src/isa/aarch64/lower.isle line 186. 6448 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6449 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 6450 let expr2_0 = C::zero_reg(ctx); 6451 let expr3_0 = 6452 constructor_madd(ctx, pattern3_0, expr0_0, expr1_0, expr2_0)?; 6453 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6454 return Some(expr4_0); 6455 } 6456 &Opcode::Udiv => { 6457 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6458 // Rule at src/isa/aarch64/lower.isle line 393. 6459 let expr0_0: Type = I64; 6460 let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?; 6461 let expr2_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?; 6462 let expr3_0 = constructor_a64_udiv(ctx, expr0_0, expr1_0, expr2_0)?; 6463 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6464 return Some(expr4_0); 6465 } 6466 &Opcode::Sdiv => { 6467 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6468 if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { 6469 let pattern9_0 = C::inst_data(ctx, pattern8_0); 6470 if let &InstructionData::UnaryImm { 6471 opcode: ref pattern10_0, 6472 imm: pattern10_1, 6473 } = &pattern9_0 6474 { 6475 if let &Opcode::Iconst = pattern10_0 { 6476 if let Some(pattern12_0) = 6477 C::safe_divisor_from_imm64(ctx, pattern10_1) 6478 { 6479 // Rule at src/isa/aarch64/lower.isle line 439. 6480 let expr0_0: Type = I64; 6481 let expr1_0 = 6482 constructor_put_in_reg_sext64(ctx, pattern7_0)?; 6483 let expr2_0 = 6484 constructor_imm(ctx, pattern3_0, pattern12_0)?; 6485 let expr3_0 = constructor_a64_sdiv( 6486 ctx, expr0_0, expr1_0, expr2_0, 6487 )?; 6488 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6489 return Some(expr4_0); 6490 } 6491 } 6492 } 6493 } 6494 // Rule at src/isa/aarch64/lower.isle line 426. 6495 let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?; 6496 let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?; 6497 let expr2_0 = constructor_trap_if_div_overflow( 6498 ctx, pattern3_0, expr0_0, expr1_0, 6499 )?; 6500 let expr3_0: Type = I64; 6501 let expr4_0 = constructor_a64_sdiv(ctx, expr3_0, expr2_0, expr1_0)?; 6502 let expr5_0 = constructor_output_reg(ctx, expr4_0)?; 6503 return Some(expr5_0); 6504 } 6505 &Opcode::Urem => { 6506 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6507 // Rule at src/isa/aarch64/lower.isle line 467. 6508 let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?; 6509 let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?; 6510 let expr2_0: Type = I64; 6511 let expr3_0 = constructor_a64_udiv(ctx, expr2_0, expr0_0, expr1_0)?; 6512 let expr4_0: Type = I64; 6513 let expr5_0 = 6514 constructor_msub(ctx, expr4_0, expr3_0, expr1_0, expr0_0)?; 6515 let expr6_0 = constructor_output_reg(ctx, expr5_0)?; 6516 return Some(expr6_0); 6517 } 6518 &Opcode::Srem => { 6519 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6520 // Rule at src/isa/aarch64/lower.isle line 474. 6521 let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?; 6522 let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?; 6523 let expr2_0: Type = I64; 6524 let expr3_0 = constructor_a64_sdiv(ctx, expr2_0, expr0_0, expr1_0)?; 6525 let expr4_0: Type = I64; 6526 let expr5_0 = 6527 constructor_msub(ctx, expr4_0, expr3_0, expr1_0, expr0_0)?; 6528 let expr6_0 = constructor_output_reg(ctx, expr5_0)?; 6529 return Some(expr6_0); 6530 } 6531 _ => {} 6532 } 6533 } 6534 &InstructionData::Unary { 6535 opcode: ref pattern5_0, 6536 arg: pattern5_1, 6537 } => { 6538 match pattern5_0 { 6539 &Opcode::Ineg => { 6540 // Rule at src/isa/aarch64/lower.isle line 176. 6541 let expr0_0 = C::zero_reg(ctx); 6542 let expr1_0 = C::put_in_reg(ctx, pattern5_1); 6543 let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?; 6544 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 6545 return Some(expr3_0); 6546 } 6547 &Opcode::Bnot => { 6548 if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) { 6549 let pattern8_0 = C::inst_data(ctx, pattern7_0); 6550 if let &InstructionData::Binary { 6551 opcode: ref pattern9_0, 6552 args: ref pattern9_1, 6553 } = &pattern8_0 6554 { 6555 if let &Opcode::Ishl = pattern9_0 { 6556 let (pattern11_0, pattern11_1) = 6557 C::unpack_value_array_2(ctx, pattern9_1); 6558 if let Some(pattern12_0) = C::def_inst(ctx, pattern11_1) { 6559 let pattern13_0 = C::inst_data(ctx, pattern12_0); 6560 if let &InstructionData::UnaryImm { 6561 opcode: ref pattern14_0, 6562 imm: pattern14_1, 6563 } = &pattern13_0 6564 { 6565 if let &Opcode::Iconst = pattern14_0 { 6566 let mut closure16 = || { 6567 let expr0_0 = C::lshl_from_imm64( 6568 ctx, 6569 pattern3_0, 6570 pattern14_1, 6571 )?; 6572 return Some(expr0_0); 6573 }; 6574 if let Some(pattern16_0) = closure16() { 6575 // Rule at src/isa/aarch64/lower.isle line 573. 6576 let expr0_0 = C::zero_reg(ctx); 6577 let expr1_0 = 6578 C::put_in_reg(ctx, pattern11_0); 6579 let expr2_0 = constructor_orr_not_shift( 6580 ctx, 6581 pattern3_0, 6582 expr0_0, 6583 expr1_0, 6584 pattern16_0, 6585 )?; 6586 let expr3_0 = 6587 constructor_output_reg(ctx, expr2_0)?; 6588 return Some(expr3_0); 6589 } 6590 } 6591 } 6592 } 6593 } 6594 } 6595 } 6596 // Rule at src/isa/aarch64/lower.isle line 568. 6597 let expr0_0 = C::zero_reg(ctx); 6598 let expr1_0 = C::put_in_reg(ctx, pattern5_1); 6599 let expr2_0 = constructor_orr_not(ctx, pattern3_0, expr0_0, expr1_0)?; 6600 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 6601 return Some(expr3_0); 6602 } 6603 &Opcode::Uextend => { 6604 if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) { 6605 let pattern8_0 = C::inst_data(ctx, pattern7_0); 6606 if let &InstructionData::BinaryImm8 { 6607 opcode: ref pattern9_0, 6608 arg: pattern9_1, 6609 imm: pattern9_2, 6610 } = &pattern8_0 6611 { 6612 if let &Opcode::Extractlane = pattern9_0 { 6613 let pattern11_0 = C::value_type(ctx, pattern9_1); 6614 let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2); 6615 // Rule at src/isa/aarch64/lower.isle line 490. 6616 let expr0_0 = C::put_in_reg(ctx, pattern9_1); 6617 let expr1_0 = constructor_vector_size(ctx, pattern11_0)?; 6618 let expr2_0 = constructor_mov_from_vec( 6619 ctx, 6620 expr0_0, 6621 pattern12_0, 6622 &expr1_0, 6623 )?; 6624 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 6625 return Some(expr3_0); 6626 } 6627 } 6628 } 6629 let pattern7_0 = C::value_type(ctx, pattern5_1); 6630 if let Some(pattern8_0) = C::sinkable_atomic_load(ctx, pattern5_1) { 6631 // Rule at src/isa/aarch64/lower.isle line 497. 6632 let expr0_0 = C::sink_atomic_load(ctx, &pattern8_0); 6633 let expr1_0 = constructor_load_acquire(ctx, pattern7_0, expr0_0)?; 6634 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6635 return Some(expr2_0); 6636 } 6637 // Rule at src/isa/aarch64/lower.isle line 485. 6638 let expr0_0 = C::put_in_reg(ctx, pattern5_1); 6639 let expr1_0: bool = false; 6640 let expr2_0 = C::ty_bits(ctx, pattern7_0)?; 6641 let expr3_0 = C::ty_bits(ctx, pattern3_0)?; 6642 let expr4_0 = 6643 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?; 6644 let expr5_0 = constructor_output_reg(ctx, expr4_0)?; 6645 return Some(expr5_0); 6646 } 6647 &Opcode::Sextend => { 6648 if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) { 6649 let pattern8_0 = C::inst_data(ctx, pattern7_0); 6650 if let &InstructionData::BinaryImm8 { 6651 opcode: ref pattern9_0, 6652 arg: pattern9_1, 6653 imm: pattern9_2, 6654 } = &pattern8_0 6655 { 6656 if let &Opcode::Extractlane = pattern9_0 { 6657 let pattern11_0 = C::value_type(ctx, pattern9_1); 6658 let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2); 6659 // Rule at src/isa/aarch64/lower.isle line 522. 6660 let expr0_0 = C::put_in_reg(ctx, pattern9_1); 6661 let expr1_0 = constructor_vector_size(ctx, pattern11_0)?; 6662 let expr2_0 = constructor_size_from_ty(ctx, pattern3_0)?; 6663 let expr3_0 = constructor_mov_from_vec_signed( 6664 ctx, 6665 expr0_0, 6666 pattern12_0, 6667 &expr1_0, 6668 &expr2_0, 6669 )?; 6670 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6671 return Some(expr4_0); 6672 } 6673 } 6674 } 6675 let pattern7_0 = C::value_type(ctx, pattern5_1); 6676 // Rule at src/isa/aarch64/lower.isle line 517. 6677 let expr0_0 = C::put_in_reg(ctx, pattern5_1); 6678 let expr1_0: bool = true; 6679 let expr2_0 = C::ty_bits(ctx, pattern7_0)?; 6680 let expr3_0 = C::ty_bits(ctx, pattern3_0)?; 6681 let expr4_0 = 6682 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?; 6683 let expr5_0 = constructor_output_reg(ctx, expr4_0)?; 6684 return Some(expr5_0); 6685 } 6686 _ => {} 6687 } 6688 } 6689 _ => {} 6690 } 6691 } 6692 if let Some(pattern3_0) = C::ty_vec128(ctx, pattern2_0) { 6693 let pattern4_0 = C::inst_data(ctx, pattern0_0); 6694 match &pattern4_0 { 6695 &InstructionData::Binary { 6696 opcode: ref pattern5_0, 6697 args: ref pattern5_1, 6698 } => { 6699 match pattern5_0 { 6700 &Opcode::UaddSat => { 6701 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6702 // Rule at src/isa/aarch64/lower.isle line 155. 6703 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6704 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 6705 let expr2_0 = constructor_vector_size(ctx, pattern3_0)?; 6706 let expr3_0 = constructor_uqadd(ctx, expr0_0, expr1_0, &expr2_0)?; 6707 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6708 return Some(expr4_0); 6709 } 6710 &Opcode::SaddSat => { 6711 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6712 // Rule at src/isa/aarch64/lower.isle line 160. 6713 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6714 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 6715 let expr2_0 = constructor_vector_size(ctx, pattern3_0)?; 6716 let expr3_0 = constructor_sqadd(ctx, expr0_0, expr1_0, &expr2_0)?; 6717 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6718 return Some(expr4_0); 6719 } 6720 &Opcode::UsubSat => { 6721 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6722 // Rule at src/isa/aarch64/lower.isle line 165. 6723 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6724 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 6725 let expr2_0 = constructor_vector_size(ctx, pattern3_0)?; 6726 let expr3_0 = constructor_uqsub(ctx, expr0_0, expr1_0, &expr2_0)?; 6727 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6728 return Some(expr4_0); 6729 } 6730 &Opcode::SsubSat => { 6731 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6732 // Rule at src/isa/aarch64/lower.isle line 170. 6733 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6734 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 6735 let expr2_0 = constructor_vector_size(ctx, pattern3_0)?; 6736 let expr3_0 = constructor_sqsub(ctx, expr0_0, expr1_0, &expr2_0)?; 6737 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6738 return Some(expr4_0); 6739 } 6740 &Opcode::Band => { 6741 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6742 // Rule at src/isa/aarch64/lower.isle line 601. 6743 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6744 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 6745 let expr2_0 = constructor_vector_size(ctx, pattern3_0)?; 6746 let expr3_0 = constructor_and_vec(ctx, expr0_0, expr1_0, &expr2_0)?; 6747 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6748 return Some(expr4_0); 6749 } 6750 &Opcode::Bor => { 6751 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6752 // Rule at src/isa/aarch64/lower.isle line 614. 6753 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6754 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 6755 let expr2_0 = constructor_vector_size(ctx, pattern3_0)?; 6756 let expr3_0 = constructor_orr_vec(ctx, expr0_0, expr1_0, &expr2_0)?; 6757 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6758 return Some(expr4_0); 6759 } 6760 &Opcode::Bxor => { 6761 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6762 // Rule at src/isa/aarch64/lower.isle line 627. 6763 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6764 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 6765 let expr2_0 = constructor_vector_size(ctx, pattern3_0)?; 6766 let expr3_0 = constructor_eor_vec(ctx, expr0_0, expr1_0, &expr2_0)?; 6767 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6768 return Some(expr4_0); 6769 } 6770 &Opcode::BandNot => { 6771 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6772 // Rule at src/isa/aarch64/lower.isle line 640. 6773 let expr0_0 = C::put_in_reg(ctx, pattern7_0); 6774 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 6775 let expr2_0 = constructor_vector_size(ctx, pattern3_0)?; 6776 let expr3_0 = constructor_bic_vec(ctx, expr0_0, expr1_0, &expr2_0)?; 6777 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6778 return Some(expr4_0); 6779 } 6780 &Opcode::Ishl => { 6781 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6782 // Rule at src/isa/aarch64/lower.isle line 704. 6783 let expr0_0 = constructor_vector_size(ctx, pattern3_0)?; 6784 let expr1_0 = C::put_in_reg(ctx, pattern7_1); 6785 let expr2_0 = constructor_vec_dup(ctx, expr1_0, &expr0_0)?; 6786 let expr3_0 = C::put_in_reg(ctx, pattern7_0); 6787 let expr4_0 = constructor_sshl(ctx, expr3_0, expr2_0, &expr0_0)?; 6788 let expr5_0 = constructor_output_reg(ctx, expr4_0)?; 6789 return Some(expr5_0); 6790 } 6791 &Opcode::Ushr => { 6792 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6793 // Rule at src/isa/aarch64/lower.isle line 763. 6794 let expr0_0 = constructor_vector_size(ctx, pattern3_0)?; 6795 let expr1_0: Type = I32; 6796 let expr2_0 = C::zero_reg(ctx); 6797 let expr3_0 = C::put_in_reg(ctx, pattern7_1); 6798 let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?; 6799 let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?; 6800 let expr6_0 = C::put_in_reg(ctx, pattern7_0); 6801 let expr7_0 = constructor_ushl(ctx, expr6_0, expr5_0, &expr0_0)?; 6802 let expr8_0 = constructor_output_reg(ctx, expr7_0)?; 6803 return Some(expr8_0); 6804 } 6805 &Opcode::Sshr => { 6806 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6807 // Rule at src/isa/aarch64/lower.isle line 812. 6808 let expr0_0 = constructor_vector_size(ctx, pattern3_0)?; 6809 let expr1_0: Type = I32; 6810 let expr2_0 = C::zero_reg(ctx); 6811 let expr3_0 = C::put_in_reg(ctx, pattern7_1); 6812 let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?; 6813 let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?; 6814 let expr6_0 = C::put_in_reg(ctx, pattern7_0); 6815 let expr7_0 = constructor_sshl(ctx, expr6_0, expr5_0, &expr0_0)?; 6816 let expr8_0 = constructor_output_reg(ctx, expr7_0)?; 6817 return Some(expr8_0); 6818 } 6819 _ => {} 6820 } 6821 } 6822 &InstructionData::Unary { 6823 opcode: ref pattern5_0, 6824 arg: pattern5_1, 6825 } => { 6826 match pattern5_0 { 6827 &Opcode::Ineg => { 6828 // Rule at src/isa/aarch64/lower.isle line 180. 6829 let expr0_0 = C::put_in_reg(ctx, pattern5_1); 6830 let expr1_0 = constructor_vector_size(ctx, pattern3_0)?; 6831 let expr2_0 = constructor_neg(ctx, expr0_0, &expr1_0)?; 6832 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 6833 return Some(expr3_0); 6834 } 6835 &Opcode::Bnot => { 6836 // Rule at src/isa/aarch64/lower.isle line 588. 6837 let expr0_0 = C::put_in_reg(ctx, pattern5_1); 6838 let expr1_0 = constructor_vector_size(ctx, pattern3_0)?; 6839 let expr2_0 = constructor_not(ctx, expr0_0, &expr1_0)?; 6840 let expr3_0 = constructor_output_reg(ctx, expr2_0)?; 6841 return Some(expr3_0); 6842 } 6843 _ => {} 6844 } 6845 } 6846 _ => {} 6847 } 6848 if let Some(()) = C::not_i64x2(ctx, pattern3_0) { 6849 let pattern5_0 = C::inst_data(ctx, pattern0_0); 6850 if let &InstructionData::Binary { 6851 opcode: ref pattern6_0, 6852 args: ref pattern6_1, 6853 } = &pattern5_0 6854 { 6855 if let &Opcode::Imul = pattern6_0 { 6856 let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1); 6857 // Rule at src/isa/aarch64/lower.isle line 218. 6858 let expr0_0 = C::put_in_reg(ctx, pattern8_0); 6859 let expr1_0 = C::put_in_reg(ctx, pattern8_1); 6860 let expr2_0 = constructor_vector_size(ctx, pattern3_0)?; 6861 let expr3_0 = constructor_mul(ctx, expr0_0, expr1_0, &expr2_0)?; 6862 let expr4_0 = constructor_output_reg(ctx, expr3_0)?; 6863 return Some(expr4_0); 6864 } 6865 } 6866 } 6867 } 6868 if let Some(pattern3_0) = C::valid_atomic_transaction(ctx, pattern2_0) { 6869 let pattern4_0 = C::inst_data(ctx, pattern0_0); 6870 if let &InstructionData::AtomicRmw { 6871 opcode: ref pattern5_0, 6872 args: ref pattern5_1, 6873 flags: pattern5_2, 6874 op: ref pattern5_3, 6875 } = &pattern4_0 6876 { 6877 if let &Opcode::AtomicRmw = pattern5_0 { 6878 let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1); 6879 match pattern5_3 { 6880 &AtomicRmwOp::Add => { 6881 // Rule at src/isa/aarch64/lower.isle line 1251. 6882 let expr0_0 = AtomicRMWLoopOp::Add; 6883 let expr1_0 = constructor_atomic_rmw_loop( 6884 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0, 6885 )?; 6886 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6887 return Some(expr2_0); 6888 } 6889 &AtomicRmwOp::And => { 6890 // Rule at src/isa/aarch64/lower.isle line 1257. 6891 let expr0_0 = AtomicRMWLoopOp::And; 6892 let expr1_0 = constructor_atomic_rmw_loop( 6893 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0, 6894 )?; 6895 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6896 return Some(expr2_0); 6897 } 6898 &AtomicRmwOp::Nand => { 6899 // Rule at src/isa/aarch64/lower.isle line 1260. 6900 let expr0_0 = AtomicRMWLoopOp::Nand; 6901 let expr1_0 = constructor_atomic_rmw_loop( 6902 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0, 6903 )?; 6904 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6905 return Some(expr2_0); 6906 } 6907 &AtomicRmwOp::Or => { 6908 // Rule at src/isa/aarch64/lower.isle line 1263. 6909 let expr0_0 = AtomicRMWLoopOp::Orr; 6910 let expr1_0 = constructor_atomic_rmw_loop( 6911 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0, 6912 )?; 6913 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6914 return Some(expr2_0); 6915 } 6916 &AtomicRmwOp::Smax => { 6917 // Rule at src/isa/aarch64/lower.isle line 1272. 6918 let expr0_0 = AtomicRMWLoopOp::Smax; 6919 let expr1_0 = constructor_atomic_rmw_loop( 6920 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0, 6921 )?; 6922 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6923 return Some(expr2_0); 6924 } 6925 &AtomicRmwOp::Smin => { 6926 // Rule at src/isa/aarch64/lower.isle line 1269. 6927 let expr0_0 = AtomicRMWLoopOp::Smin; 6928 let expr1_0 = constructor_atomic_rmw_loop( 6929 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0, 6930 )?; 6931 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6932 return Some(expr2_0); 6933 } 6934 &AtomicRmwOp::Sub => { 6935 // Rule at src/isa/aarch64/lower.isle line 1254. 6936 let expr0_0 = AtomicRMWLoopOp::Sub; 6937 let expr1_0 = constructor_atomic_rmw_loop( 6938 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0, 6939 )?; 6940 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6941 return Some(expr2_0); 6942 } 6943 &AtomicRmwOp::Umax => { 6944 // Rule at src/isa/aarch64/lower.isle line 1278. 6945 let expr0_0 = AtomicRMWLoopOp::Umax; 6946 let expr1_0 = constructor_atomic_rmw_loop( 6947 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0, 6948 )?; 6949 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6950 return Some(expr2_0); 6951 } 6952 &AtomicRmwOp::Umin => { 6953 // Rule at src/isa/aarch64/lower.isle line 1275. 6954 let expr0_0 = AtomicRMWLoopOp::Umin; 6955 let expr1_0 = constructor_atomic_rmw_loop( 6956 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0, 6957 )?; 6958 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6959 return Some(expr2_0); 6960 } 6961 &AtomicRmwOp::Xchg => { 6962 // Rule at src/isa/aarch64/lower.isle line 1281. 6963 let expr0_0 = AtomicRMWLoopOp::Xchg; 6964 let expr1_0 = constructor_atomic_rmw_loop( 6965 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0, 6966 )?; 6967 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6968 return Some(expr2_0); 6969 } 6970 &AtomicRmwOp::Xor => { 6971 // Rule at src/isa/aarch64/lower.isle line 1266. 6972 let expr0_0 = AtomicRMWLoopOp::Eor; 6973 let expr1_0 = constructor_atomic_rmw_loop( 6974 ctx, &expr0_0, pattern7_0, pattern7_1, pattern3_0, 6975 )?; 6976 let expr2_0 = constructor_output_reg(ctx, expr1_0)?; 6977 return Some(expr2_0); 6978 } 6979 _ => {} 6980 } 6981 } 6982 } 6983 } 6984 } 6985 return None; 6986 } 6987 6988 // Generated as internal constructor for term put_nonzero_in_reg_zext64. 6989 pub fn constructor_put_nonzero_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> { 6990 let pattern0_0 = arg0; 6991 let pattern1_0 = C::value_type(ctx, pattern0_0); 6992 if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) { 6993 let pattern3_0 = C::inst_data(ctx, pattern2_0); 6994 if let &InstructionData::UnaryImm { 6995 opcode: ref pattern4_0, 6996 imm: pattern4_1, 6997 } = &pattern3_0 6998 { 6999 if let &Opcode::Iconst = pattern4_0 { 7000 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) { 7001 // Rule at src/isa/aarch64/lower.isle line 403. 7002 let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?; 7003 return Some(expr0_0); 7004 } 7005 } 7006 } 7007 } 7008 // Rule at src/isa/aarch64/lower.isle line 398. 7009 let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern0_0)?; 7010 let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?; 7011 return Some(expr1_0); 7012 } 7013 7014 // Generated as internal constructor for term put_nonzero_in_reg_sext64. 7015 pub fn constructor_put_nonzero_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> { 7016 let pattern0_0 = arg0; 7017 let pattern1_0 = C::value_type(ctx, pattern0_0); 7018 if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) { 7019 let pattern3_0 = C::inst_data(ctx, pattern2_0); 7020 if let &InstructionData::UnaryImm { 7021 opcode: ref pattern4_0, 7022 imm: pattern4_1, 7023 } = &pattern3_0 7024 { 7025 if let &Opcode::Iconst = pattern4_0 { 7026 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) { 7027 // Rule at src/isa/aarch64/lower.isle line 449. 7028 let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?; 7029 return Some(expr0_0); 7030 } 7031 } 7032 } 7033 } 7034 // Rule at src/isa/aarch64/lower.isle line 444. 7035 let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern0_0)?; 7036 let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?; 7037 return Some(expr1_0); 7038 } 7039 7040 // Generated as internal constructor for term lower_shl128. 7041 pub fn constructor_lower_shl128<C: Context>( 7042 ctx: &mut C, 7043 arg0: ValueRegs, 7044 arg1: Reg, 7045 ) -> Option<ValueRegs> { 7046 let pattern0_0 = arg0; 7047 let pattern1_0 = arg1; 7048 // Rule at src/isa/aarch64/lower.isle line 687. 7049 let expr0_0: usize = 0; 7050 let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0); 7051 let expr2_0: usize = 1; 7052 let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0); 7053 let expr4_0: Type = I64; 7054 let expr5_0 = constructor_lsl(ctx, expr4_0, expr1_0, pattern1_0)?; 7055 let expr6_0: Type = I64; 7056 let expr7_0 = constructor_lsl(ctx, expr6_0, expr3_0, pattern1_0)?; 7057 let expr8_0: Type = I32; 7058 let expr9_0 = C::zero_reg(ctx); 7059 let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?; 7060 let expr11_0: Type = I64; 7061 let expr12_0: Type = I64; 7062 let expr13_0: u8 = 1; 7063 let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0); 7064 let expr15_0 = constructor_lsr_imm(ctx, expr12_0, expr1_0, expr14_0)?; 7065 let expr16_0 = constructor_lsr(ctx, expr11_0, expr15_0, expr10_0)?; 7066 let expr17_0: Type = I64; 7067 let expr18_0 = constructor_orr(ctx, expr17_0, expr7_0, expr16_0)?; 7068 let expr19_0: Type = I64; 7069 let expr20_0: Type = I64; 7070 let expr21_0: u64 = 64; 7071 let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0); 7072 let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?; 7073 let expr24_0 = Cond::Ne; 7074 let expr25_0 = C::zero_reg(ctx); 7075 let expr26_0 = constructor_csel(ctx, &expr24_0, expr25_0, expr5_0)?; 7076 let expr27_0 = Cond::Ne; 7077 let expr28_0 = constructor_csel(ctx, &expr27_0, expr5_0, expr18_0)?; 7078 let expr29_0 = constructor_consumes_flags_concat(ctx, &expr26_0, &expr28_0)?; 7079 let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?; 7080 return Some(expr30_0); 7081 } 7082 7083 // Generated as internal constructor for term do_shift. 7084 pub fn constructor_do_shift<C: Context>( 7085 ctx: &mut C, 7086 arg0: &ALUOp, 7087 arg1: Type, 7088 arg2: Reg, 7089 arg3: Value, 7090 ) -> Option<Reg> { 7091 let pattern0_0 = arg0; 7092 let pattern1_0 = arg1; 7093 let pattern2_0 = arg2; 7094 let pattern3_0 = arg3; 7095 if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) { 7096 let pattern5_0 = C::inst_data(ctx, pattern4_0); 7097 if let &InstructionData::UnaryImm { 7098 opcode: ref pattern6_0, 7099 imm: pattern6_1, 7100 } = &pattern5_0 7101 { 7102 if let &Opcode::Iconst = pattern6_0 { 7103 let mut closure8 = || { 7104 let expr0_0 = C::imm_shift_from_imm64(ctx, pattern1_0, pattern6_1)?; 7105 return Some(expr0_0); 7106 }; 7107 if let Some(pattern8_0) = closure8() { 7108 // Rule at src/isa/aarch64/lower.isle line 744. 7109 let expr0_0 = constructor_alu_rr_imm_shift( 7110 ctx, pattern0_0, pattern1_0, pattern2_0, pattern8_0, 7111 )?; 7112 return Some(expr0_0); 7113 } 7114 } 7115 } 7116 } 7117 let pattern0_0 = arg0; 7118 let pattern1_0 = arg1; 7119 if pattern1_0 == I32 { 7120 let pattern3_0 = arg2; 7121 let pattern4_0 = arg3; 7122 // Rule at src/isa/aarch64/lower.isle line 735. 7123 let expr0_0: Type = I32; 7124 let expr1_0 = C::put_in_regs(ctx, pattern4_0); 7125 let expr2_0: usize = 0; 7126 let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0); 7127 let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?; 7128 return Some(expr4_0); 7129 } 7130 if pattern1_0 == I64 { 7131 let pattern3_0 = arg2; 7132 let pattern4_0 = arg3; 7133 // Rule at src/isa/aarch64/lower.isle line 736. 7134 let expr0_0: Type = I64; 7135 let expr1_0 = C::put_in_regs(ctx, pattern4_0); 7136 let expr2_0: usize = 0; 7137 let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0); 7138 let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?; 7139 return Some(expr4_0); 7140 } 7141 if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) { 7142 let pattern3_0 = arg2; 7143 let pattern4_0 = arg3; 7144 // Rule at src/isa/aarch64/lower.isle line 726. 7145 let expr0_0 = C::put_in_regs(ctx, pattern4_0); 7146 let expr1_0: usize = 0; 7147 let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0); 7148 let expr3_0: Type = I32; 7149 let expr4_0 = C::shift_mask(ctx, pattern2_0); 7150 let expr5_0 = constructor_and_imm(ctx, expr3_0, expr2_0, expr4_0)?; 7151 let expr6_0: Type = I32; 7152 let expr7_0 = constructor_alu_rrr(ctx, pattern0_0, expr6_0, pattern3_0, expr5_0)?; 7153 return Some(expr7_0); 7154 } 7155 return None; 7156 } 7157 7158 // Generated as internal constructor for term lower_ushr128. 7159 pub fn constructor_lower_ushr128<C: Context>( 7160 ctx: &mut C, 7161 arg0: ValueRegs, 7162 arg1: Reg, 7163 ) -> Option<ValueRegs> { 7164 let pattern0_0 = arg0; 7165 let pattern1_0 = arg1; 7166 // Rule at src/isa/aarch64/lower.isle line 778. 7167 let expr0_0: usize = 0; 7168 let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0); 7169 let expr2_0: usize = 1; 7170 let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0); 7171 let expr4_0: Type = I64; 7172 let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?; 7173 let expr6_0: Type = I64; 7174 let expr7_0 = constructor_lsr(ctx, expr6_0, expr3_0, pattern1_0)?; 7175 let expr8_0: Type = I32; 7176 let expr9_0 = C::zero_reg(ctx); 7177 let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?; 7178 let expr11_0: Type = I64; 7179 let expr12_0: Type = I64; 7180 let expr13_0: u8 = 1; 7181 let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0); 7182 let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?; 7183 let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?; 7184 let expr17_0: Type = I64; 7185 let expr18_0 = constructor_orr(ctx, expr17_0, expr5_0, expr16_0)?; 7186 let expr19_0: Type = I64; 7187 let expr20_0: Type = I64; 7188 let expr21_0: u64 = 64; 7189 let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0); 7190 let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?; 7191 let expr24_0 = Cond::Ne; 7192 let expr25_0 = constructor_csel(ctx, &expr24_0, expr7_0, expr18_0)?; 7193 let expr26_0 = Cond::Ne; 7194 let expr27_0 = C::zero_reg(ctx); 7195 let expr28_0 = constructor_csel(ctx, &expr26_0, expr27_0, expr7_0)?; 7196 let expr29_0 = constructor_consumes_flags_concat(ctx, &expr25_0, &expr28_0)?; 7197 let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?; 7198 return Some(expr30_0); 7199 } 7200 7201 // Generated as internal constructor for term lower_sshr128. 7202 pub fn constructor_lower_sshr128<C: Context>( 7203 ctx: &mut C, 7204 arg0: ValueRegs, 7205 arg1: Reg, 7206 ) -> Option<ValueRegs> { 7207 let pattern0_0 = arg0; 7208 let pattern1_0 = arg1; 7209 // Rule at src/isa/aarch64/lower.isle line 828. 7210 let expr0_0: usize = 0; 7211 let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0); 7212 let expr2_0: usize = 1; 7213 let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0); 7214 let expr4_0: Type = I64; 7215 let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?; 7216 let expr6_0: Type = I64; 7217 let expr7_0 = constructor_asr(ctx, expr6_0, expr3_0, pattern1_0)?; 7218 let expr8_0: Type = I32; 7219 let expr9_0 = C::zero_reg(ctx); 7220 let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?; 7221 let expr11_0: Type = I64; 7222 let expr12_0: Type = I64; 7223 let expr13_0: u8 = 1; 7224 let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0); 7225 let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?; 7226 let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?; 7227 let expr17_0: Type = I64; 7228 let expr18_0: u8 = 63; 7229 let expr19_0 = C::imm_shift_from_u8(ctx, expr18_0); 7230 let expr20_0 = constructor_asr_imm(ctx, expr17_0, expr3_0, expr19_0)?; 7231 let expr21_0: Type = I64; 7232 let expr22_0 = constructor_orr(ctx, expr21_0, expr5_0, expr16_0)?; 7233 let expr23_0: Type = I64; 7234 let expr24_0: Type = I64; 7235 let expr25_0: u64 = 64; 7236 let expr26_0 = C::u64_into_imm_logic(ctx, expr24_0, expr25_0); 7237 let expr27_0 = constructor_tst_imm(ctx, expr23_0, pattern1_0, expr26_0)?; 7238 let expr28_0 = Cond::Ne; 7239 let expr29_0 = constructor_csel(ctx, &expr28_0, expr7_0, expr22_0)?; 7240 let expr30_0 = Cond::Ne; 7241 let expr31_0 = constructor_csel(ctx, &expr30_0, expr20_0, expr7_0)?; 7242 let expr32_0 = constructor_consumes_flags_concat(ctx, &expr29_0, &expr31_0)?; 7243 let expr33_0 = constructor_with_flags(ctx, &expr27_0, &expr32_0)?; 7244 return Some(expr33_0); 7245 } 7246 7247 // Generated as internal constructor for term small_rotr. 7248 pub fn constructor_small_rotr<C: Context>( 7249 ctx: &mut C, 7250 arg0: Type, 7251 arg1: Reg, 7252 arg2: Reg, 7253 ) -> Option<Reg> { 7254 let pattern0_0 = arg0; 7255 let pattern1_0 = arg1; 7256 let pattern2_0 = arg2; 7257 // Rule at src/isa/aarch64/lower.isle line 944. 7258 let expr0_0: Type = I32; 7259 let expr1_0 = C::rotr_mask(ctx, pattern0_0); 7260 let expr2_0 = constructor_and_imm(ctx, expr0_0, pattern2_0, expr1_0)?; 7261 let expr3_0: Type = I32; 7262 let expr4_0 = C::ty_bits(ctx, pattern0_0)?; 7263 let expr5_0 = C::u8_into_imm12(ctx, expr4_0); 7264 let expr6_0 = constructor_sub_imm(ctx, expr3_0, expr2_0, expr5_0)?; 7265 let expr7_0: Type = I32; 7266 let expr8_0 = C::zero_reg(ctx); 7267 let expr9_0 = constructor_sub(ctx, expr7_0, expr8_0, expr6_0)?; 7268 let expr10_0: Type = I32; 7269 let expr11_0 = constructor_lsr(ctx, expr10_0, pattern1_0, expr2_0)?; 7270 let expr12_0: Type = I32; 7271 let expr13_0 = constructor_lsl(ctx, expr12_0, pattern1_0, expr9_0)?; 7272 let expr14_0: Type = I32; 7273 let expr15_0 = constructor_orr(ctx, expr14_0, expr13_0, expr11_0)?; 7274 return Some(expr15_0); 7275 } 7276 7277 // Generated as internal constructor for term small_rotr_imm. 7278 pub fn constructor_small_rotr_imm<C: Context>( 7279 ctx: &mut C, 7280 arg0: Type, 7281 arg1: Reg, 7282 arg2: ImmShift, 7283 ) -> Option<Reg> { 7284 let pattern0_0 = arg0; 7285 let pattern1_0 = arg1; 7286 let pattern2_0 = arg2; 7287 // Rule at src/isa/aarch64/lower.isle line 965. 7288 let expr0_0: Type = I32; 7289 let expr1_0 = constructor_lsr_imm(ctx, expr0_0, pattern1_0, pattern2_0)?; 7290 let expr2_0: Type = I32; 7291 let expr3_0 = C::rotr_opposite_amount(ctx, pattern0_0, pattern2_0); 7292 let expr4_0 = constructor_lsl_imm(ctx, expr2_0, pattern1_0, expr3_0)?; 7293 let expr5_0: Type = I32; 7294 let expr6_0 = constructor_orr(ctx, expr5_0, expr4_0, expr1_0)?; 7295 return Some(expr6_0); 7296 } 7297 7298 // Generated as internal constructor for term lower_clz128. 7299 pub fn constructor_lower_clz128<C: Context>(ctx: &mut C, arg0: ValueRegs) -> Option<ValueRegs> { 7300 let pattern0_0 = arg0; 7301 // Rule at src/isa/aarch64/lower.isle line 1030. 7302 let expr0_0: Type = I64; 7303 let expr1_0: usize = 1; 7304 let expr2_0 = C::value_regs_get(ctx, pattern0_0, expr1_0); 7305 let expr3_0 = constructor_a64_clz(ctx, expr0_0, expr2_0)?; 7306 let expr4_0: Type = I64; 7307 let expr5_0: usize = 0; 7308 let expr6_0 = C::value_regs_get(ctx, pattern0_0, expr5_0); 7309 let expr7_0 = constructor_a64_clz(ctx, expr4_0, expr6_0)?; 7310 let expr8_0: Type = I64; 7311 let expr9_0: u8 = 6; 7312 let expr10_0 = C::imm_shift_from_u8(ctx, expr9_0); 7313 let expr11_0 = constructor_lsr_imm(ctx, expr8_0, expr3_0, expr10_0)?; 7314 let expr12_0: Type = I64; 7315 let expr13_0 = constructor_madd(ctx, expr12_0, expr7_0, expr11_0, expr3_0)?; 7316 let expr14_0: Type = I64; 7317 let expr15_0: u64 = 0; 7318 let expr16_0 = constructor_imm(ctx, expr14_0, expr15_0)?; 7319 let expr17_0 = C::value_regs(ctx, expr13_0, expr16_0); 7320 return Some(expr17_0); 7321 } 7322