1 // GENERATED BY ISLE. DO NOT EDIT!
2 //
3 // Generated automatically from the instruction-selection DSL code in:
4 // - src/clif.isle
5 // - src/prelude.isle
6 // - src/isa/aarch64/inst.isle
7 // - src/isa/aarch64/lower.isle
8 
9 #![allow(dead_code, unreachable_code, unreachable_patterns)]
10 #![allow(unused_imports, unused_variables, non_snake_case)]
11 #![allow(irrefutable_let_patterns)]
12 
13 use super::*; // Pulls in all external types.
14 
15 /// Context during lowering: an implementation of this trait
16 /// must be provided with all external constructors and extractors.
17 /// A mutable borrow is passed along through all lowering logic.
18 pub trait Context {
19     fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
20     fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
21     fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
22     fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
23     fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
24     fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
25     fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
26     fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
27     fn value_regs_invalid(&mut self) -> ValueRegs;
28     fn output_none(&mut self) -> InstOutput;
29     fn output(&mut self, arg0: ValueRegs) -> InstOutput;
30     fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput;
31     fn output_builder_new(&mut self) -> InstOutputBuilder;
32     fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit;
33     fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput;
34     fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
35     fn invalid_reg(&mut self) -> Reg;
36     fn put_in_reg(&mut self, arg0: Value) -> Reg;
37     fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
38     fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
39     fn u8_as_u64(&mut self, arg0: u8) -> u64;
40     fn u16_as_u64(&mut self, arg0: u16) -> u64;
41     fn u32_as_u64(&mut self, arg0: u32) -> u64;
42     fn i64_as_u64(&mut self, arg0: i64) -> u64;
43     fn u64_add(&mut self, arg0: u64, arg1: u64) -> u64;
44     fn u64_sub(&mut self, arg0: u64, arg1: u64) -> u64;
45     fn u64_and(&mut self, arg0: u64, arg1: u64) -> u64;
46     fn ty_bits(&mut self, arg0: Type) -> u8;
47     fn ty_bits_u16(&mut self, arg0: Type) -> u16;
48     fn ty_bits_u64(&mut self, arg0: Type) -> u64;
49     fn ty_mask(&mut self, arg0: Type) -> u64;
50     fn ty_bytes(&mut self, arg0: Type) -> u16;
51     fn lane_type(&mut self, arg0: Type) -> Type;
52     fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
53     fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
54     fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
55     fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
56     fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
57     fn ty_int_bool_64(&mut self, arg0: Type) -> Option<Type>;
58     fn ty_int_bool_ref_64(&mut self, arg0: Type) -> Option<Type>;
59     fn ty_int_bool_128(&mut self, arg0: Type) -> Option<Type>;
60     fn ty_scalar_float(&mut self, arg0: Type) -> Option<Type>;
61     fn ty_vec128(&mut self, arg0: Type) -> Option<Type>;
62     fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
63     fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
64     fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>;
65     fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>;
66     fn value_slice_len(&mut self, arg0: ValueSlice) -> usize;
67     fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value;
68     fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
69     fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
70     fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
71     fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
72     fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
73     fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
74     fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
75     fn first_result(&mut self, arg0: Inst) -> Option<Value>;
76     fn inst_data(&mut self, arg0: Inst) -> InstructionData;
77     fn value_type(&mut self, arg0: Value) -> Type;
78     fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
79     fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
80     fn offset32_to_u32(&mut self, arg0: Offset32) -> u32;
81     fn emit(&mut self, arg0: &MInst) -> Unit;
82     fn trap_code_division_by_zero(&mut self) -> TrapCode;
83     fn trap_code_integer_overflow(&mut self) -> TrapCode;
84     fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
85     fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
86     fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
87     fn symbol_value_data(
88         &mut self,
89         arg0: GlobalValue,
90     ) -> Option<(ExternalName, RelocDistance, i64)>;
91     fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
92     fn move_wide_const_from_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
93     fn move_wide_const_from_negated_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
94     fn imm_logic_from_u64(&mut self, arg0: u64, arg1: Type) -> Option<ImmLogic>;
95     fn imm_logic_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmLogic>;
96     fn imm_shift_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmShift>;
97     fn imm_shift_from_u8(&mut self, arg0: u8) -> ImmShift;
98     fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12>;
99     fn u8_into_uimm5(&mut self, arg0: u8) -> UImm5;
100     fn u8_into_imm12(&mut self, arg0: u8) -> Imm12;
101     fn u64_into_imm_logic(&mut self, arg0: Type, arg1: u64) -> ImmLogic;
102     fn imm12_from_negated_u64(&mut self, arg0: u64) -> Option<Imm12>;
103     fn lshl_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ShiftOpAndAmt>;
104     fn integral_ty(&mut self, arg0: Type) -> Option<Type>;
105     fn extended_value_from_value(&mut self, arg0: Value) -> Option<ExtendedValue>;
106     fn put_extended_in_reg(&mut self, arg0: &ExtendedValue) -> Reg;
107     fn get_extended_op(&mut self, arg0: &ExtendedValue) -> ExtendOp;
108     fn nzcv(&mut self, arg0: bool, arg1: bool, arg2: bool, arg3: bool) -> NZCV;
109     fn cond_br_zero(&mut self, arg0: Reg) -> CondBrKind;
110     fn cond_br_cond(&mut self, arg0: &Cond) -> CondBrKind;
111     fn zero_reg(&mut self) -> Reg;
112     fn writable_zero_reg(&mut self) -> WritableReg;
113     fn load_constant64_full(&mut self, arg0: u64) -> Reg;
114     fn sinkable_atomic_load(&mut self, arg0: Value) -> Option<SinkableAtomicLoad>;
115     fn sink_atomic_load(&mut self, arg0: &SinkableAtomicLoad) -> Reg;
116     fn zero_value_f32(&mut self, arg0: Ieee32) -> Option<Ieee32>;
117     fn zero_value_f64(&mut self, arg0: Ieee64) -> Option<Ieee64>;
118     fn float_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &FloatCC) -> VecMisc2;
119     fn float_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &FloatCC) -> VecMisc2;
120     fn fcmp_zero_cond(&mut self, arg0: &FloatCC) -> Option<FloatCC>;
121     fn fcmp_zero_cond_not_eq(&mut self, arg0: &FloatCC) -> Option<FloatCC>;
122     fn zero_value(&mut self, arg0: Imm64) -> Option<Imm64>;
123     fn int_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &IntCC) -> VecMisc2;
124     fn int_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &IntCC) -> VecMisc2;
125     fn icmp_zero_cond(&mut self, arg0: &IntCC) -> Option<IntCC>;
126     fn icmp_zero_cond_not_eq(&mut self, arg0: &IntCC) -> Option<IntCC>;
127     fn safe_divisor_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
128     fn shift_mask(&mut self, arg0: Type) -> ImmLogic;
129     fn negate_imm_shift(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
130     fn rotr_mask(&mut self, arg0: Type) -> ImmLogic;
131     fn rotr_opposite_amount(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
132 }
133 
134 /// Internal type SideEffectNoResult: defined at src/prelude.isle line 402.
135 #[derive(Clone, Debug)]
136 pub enum SideEffectNoResult {
137     Inst { inst: MInst },
138 }
139 
140 /// Internal type ProducesFlags: defined at src/prelude.isle line 418.
141 #[derive(Clone, Debug)]
142 pub enum ProducesFlags {
143     ProducesFlagsSideEffect { inst: MInst },
144     ProducesFlagsReturnsReg { inst: MInst, result: Reg },
145     ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg },
146 }
147 
148 /// Internal type ConsumesFlags: defined at src/prelude.isle line 429.
149 #[derive(Clone, Debug)]
150 pub enum ConsumesFlags {
151     ConsumesFlagsReturnsResultWithProducer {
152         inst: MInst,
153         result: Reg,
154     },
155     ConsumesFlagsReturnsReg {
156         inst: MInst,
157         result: Reg,
158     },
159     ConsumesFlagsTwiceReturnsValueRegs {
160         inst1: MInst,
161         inst2: MInst,
162         result: ValueRegs,
163     },
164     ConsumesFlagsFourTimesReturnsValueRegs {
165         inst1: MInst,
166         inst2: MInst,
167         inst3: MInst,
168         inst4: MInst,
169         result: ValueRegs,
170     },
171 }
172 
173 /// Internal type MInst: defined at src/isa/aarch64/inst.isle line 2.
174 #[derive(Clone, Debug)]
175 pub enum MInst {
176     Nop0,
177     Nop4,
178     AluRRR {
179         alu_op: ALUOp,
180         size: OperandSize,
181         rd: WritableReg,
182         rn: Reg,
183         rm: Reg,
184     },
185     AluRRRR {
186         alu_op: ALUOp3,
187         size: OperandSize,
188         rd: WritableReg,
189         rn: Reg,
190         rm: Reg,
191         ra: Reg,
192     },
193     AluRRImm12 {
194         alu_op: ALUOp,
195         size: OperandSize,
196         rd: WritableReg,
197         rn: Reg,
198         imm12: Imm12,
199     },
200     AluRRImmLogic {
201         alu_op: ALUOp,
202         size: OperandSize,
203         rd: WritableReg,
204         rn: Reg,
205         imml: ImmLogic,
206     },
207     AluRRImmShift {
208         alu_op: ALUOp,
209         size: OperandSize,
210         rd: WritableReg,
211         rn: Reg,
212         immshift: ImmShift,
213     },
214     AluRRRShift {
215         alu_op: ALUOp,
216         size: OperandSize,
217         rd: WritableReg,
218         rn: Reg,
219         rm: Reg,
220         shiftop: ShiftOpAndAmt,
221     },
222     AluRRRExtend {
223         alu_op: ALUOp,
224         size: OperandSize,
225         rd: WritableReg,
226         rn: Reg,
227         rm: Reg,
228         extendop: ExtendOp,
229     },
230     BitRR {
231         op: BitOp,
232         size: OperandSize,
233         rd: WritableReg,
234         rn: Reg,
235     },
236     ULoad8 {
237         rd: WritableReg,
238         mem: AMode,
239         flags: MemFlags,
240     },
241     SLoad8 {
242         rd: WritableReg,
243         mem: AMode,
244         flags: MemFlags,
245     },
246     ULoad16 {
247         rd: WritableReg,
248         mem: AMode,
249         flags: MemFlags,
250     },
251     SLoad16 {
252         rd: WritableReg,
253         mem: AMode,
254         flags: MemFlags,
255     },
256     ULoad32 {
257         rd: WritableReg,
258         mem: AMode,
259         flags: MemFlags,
260     },
261     SLoad32 {
262         rd: WritableReg,
263         mem: AMode,
264         flags: MemFlags,
265     },
266     ULoad64 {
267         rd: WritableReg,
268         mem: AMode,
269         flags: MemFlags,
270     },
271     Store8 {
272         rd: Reg,
273         mem: AMode,
274         flags: MemFlags,
275     },
276     Store16 {
277         rd: Reg,
278         mem: AMode,
279         flags: MemFlags,
280     },
281     Store32 {
282         rd: Reg,
283         mem: AMode,
284         flags: MemFlags,
285     },
286     Store64 {
287         rd: Reg,
288         mem: AMode,
289         flags: MemFlags,
290     },
291     StoreP64 {
292         rt: Reg,
293         rt2: Reg,
294         mem: PairAMode,
295         flags: MemFlags,
296     },
297     LoadP64 {
298         rt: WritableReg,
299         rt2: WritableReg,
300         mem: PairAMode,
301         flags: MemFlags,
302     },
303     Mov {
304         size: OperandSize,
305         rd: WritableReg,
306         rm: Reg,
307     },
308     MovWide {
309         op: MoveWideOp,
310         rd: WritableReg,
311         imm: MoveWideConst,
312         size: OperandSize,
313     },
314     Extend {
315         rd: WritableReg,
316         rn: Reg,
317         signed: bool,
318         from_bits: u8,
319         to_bits: u8,
320     },
321     CSel {
322         rd: WritableReg,
323         cond: Cond,
324         rn: Reg,
325         rm: Reg,
326     },
327     CSet {
328         rd: WritableReg,
329         cond: Cond,
330     },
331     CSetm {
332         rd: WritableReg,
333         cond: Cond,
334     },
335     CCmpImm {
336         size: OperandSize,
337         rn: Reg,
338         imm: UImm5,
339         nzcv: NZCV,
340         cond: Cond,
341     },
342     AtomicRMWLoop {
343         ty: Type,
344         op: AtomicRmwOp,
345     },
346     AtomicRMW {
347         op: AtomicRMWOp,
348         rs: Reg,
349         rt: WritableReg,
350         rn: Reg,
351         ty: Type,
352     },
353     AtomicCAS {
354         rs: WritableReg,
355         rt: Reg,
356         rn: Reg,
357         ty: Type,
358     },
359     AtomicCASLoop {
360         ty: Type,
361     },
362     LoadAcquire {
363         access_ty: Type,
364         rt: WritableReg,
365         rn: Reg,
366     },
367     StoreRelease {
368         access_ty: Type,
369         rt: Reg,
370         rn: Reg,
371     },
372     Fence,
373     FpuMove64 {
374         rd: WritableReg,
375         rn: Reg,
376     },
377     FpuMove128 {
378         rd: WritableReg,
379         rn: Reg,
380     },
381     FpuMoveFromVec {
382         rd: WritableReg,
383         rn: Reg,
384         idx: u8,
385         size: VectorSize,
386     },
387     FpuExtend {
388         rd: WritableReg,
389         rn: Reg,
390         size: ScalarSize,
391     },
392     FpuRR {
393         fpu_op: FPUOp1,
394         size: ScalarSize,
395         rd: WritableReg,
396         rn: Reg,
397     },
398     FpuRRR {
399         fpu_op: FPUOp2,
400         size: ScalarSize,
401         rd: WritableReg,
402         rn: Reg,
403         rm: Reg,
404     },
405     FpuRRI {
406         fpu_op: FPUOpRI,
407         rd: WritableReg,
408         rn: Reg,
409     },
410     FpuRRRR {
411         fpu_op: FPUOp3,
412         rd: WritableReg,
413         rn: Reg,
414         rm: Reg,
415         ra: Reg,
416     },
417     FpuCmp {
418         size: ScalarSize,
419         rn: Reg,
420         rm: Reg,
421     },
422     FpuLoad32 {
423         rd: WritableReg,
424         mem: AMode,
425         flags: MemFlags,
426     },
427     FpuStore32 {
428         rd: Reg,
429         mem: AMode,
430         flags: MemFlags,
431     },
432     FpuLoad64 {
433         rd: WritableReg,
434         mem: AMode,
435         flags: MemFlags,
436     },
437     FpuStore64 {
438         rd: Reg,
439         mem: AMode,
440         flags: MemFlags,
441     },
442     FpuLoad128 {
443         rd: WritableReg,
444         mem: AMode,
445         flags: MemFlags,
446     },
447     FpuStore128 {
448         rd: Reg,
449         mem: AMode,
450         flags: MemFlags,
451     },
452     FpuLoadP64 {
453         rt: WritableReg,
454         rt2: WritableReg,
455         mem: PairAMode,
456         flags: MemFlags,
457     },
458     FpuStoreP64 {
459         rt: Reg,
460         rt2: Reg,
461         mem: PairAMode,
462         flags: MemFlags,
463     },
464     FpuLoadP128 {
465         rt: WritableReg,
466         rt2: WritableReg,
467         mem: PairAMode,
468         flags: MemFlags,
469     },
470     FpuStoreP128 {
471         rt: Reg,
472         rt2: Reg,
473         mem: PairAMode,
474         flags: MemFlags,
475     },
476     LoadFpuConst64 {
477         rd: WritableReg,
478         const_data: u64,
479     },
480     LoadFpuConst128 {
481         rd: WritableReg,
482         const_data: u128,
483     },
484     FpuToInt {
485         op: FpuToIntOp,
486         rd: WritableReg,
487         rn: Reg,
488     },
489     IntToFpu {
490         op: IntToFpuOp,
491         rd: WritableReg,
492         rn: Reg,
493     },
494     FpuCSel32 {
495         rd: WritableReg,
496         rn: Reg,
497         rm: Reg,
498         cond: Cond,
499     },
500     FpuCSel64 {
501         rd: WritableReg,
502         rn: Reg,
503         rm: Reg,
504         cond: Cond,
505     },
506     FpuRound {
507         op: FpuRoundMode,
508         rd: WritableReg,
509         rn: Reg,
510     },
511     MovToFpu {
512         rd: WritableReg,
513         rn: Reg,
514         size: ScalarSize,
515     },
516     FpuMoveFPImm {
517         rd: WritableReg,
518         imm: ASIMDFPModImm,
519         size: ScalarSize,
520     },
521     MovToVec {
522         rd: WritableReg,
523         rn: Reg,
524         idx: u8,
525         size: VectorSize,
526     },
527     MovFromVec {
528         rd: WritableReg,
529         rn: Reg,
530         idx: u8,
531         size: VectorSize,
532     },
533     MovFromVecSigned {
534         rd: WritableReg,
535         rn: Reg,
536         idx: u8,
537         size: VectorSize,
538         scalar_size: OperandSize,
539     },
540     VecDup {
541         rd: WritableReg,
542         rn: Reg,
543         size: VectorSize,
544     },
545     VecDupFromFpu {
546         rd: WritableReg,
547         rn: Reg,
548         size: VectorSize,
549     },
550     VecDupFPImm {
551         rd: WritableReg,
552         imm: ASIMDFPModImm,
553         size: VectorSize,
554     },
555     VecDupImm {
556         rd: WritableReg,
557         imm: ASIMDMovModImm,
558         invert: bool,
559         size: VectorSize,
560     },
561     VecExtend {
562         t: VecExtendOp,
563         rd: WritableReg,
564         rn: Reg,
565         high_half: bool,
566     },
567     VecMovElement {
568         rd: WritableReg,
569         rn: Reg,
570         dest_idx: u8,
571         src_idx: u8,
572         size: VectorSize,
573     },
574     VecRRLong {
575         op: VecRRLongOp,
576         rd: WritableReg,
577         rn: Reg,
578         high_half: bool,
579     },
580     VecRRNarrow {
581         op: VecRRNarrowOp,
582         rd: WritableReg,
583         rn: Reg,
584         high_half: bool,
585     },
586     VecRRPair {
587         op: VecPairOp,
588         rd: WritableReg,
589         rn: Reg,
590     },
591     VecRRRLong {
592         alu_op: VecRRRLongOp,
593         rd: WritableReg,
594         rn: Reg,
595         rm: Reg,
596         high_half: bool,
597     },
598     VecRRPairLong {
599         op: VecRRPairLongOp,
600         rd: WritableReg,
601         rn: Reg,
602     },
603     VecRRR {
604         alu_op: VecALUOp,
605         rd: WritableReg,
606         rn: Reg,
607         rm: Reg,
608         size: VectorSize,
609     },
610     VecMisc {
611         op: VecMisc2,
612         rd: WritableReg,
613         rn: Reg,
614         size: VectorSize,
615     },
616     VecLanes {
617         op: VecLanesOp,
618         rd: WritableReg,
619         rn: Reg,
620         size: VectorSize,
621     },
622     VecShiftImm {
623         op: VecShiftImmOp,
624         rd: WritableReg,
625         rn: Reg,
626         size: VectorSize,
627         imm: u8,
628     },
629     VecExtract {
630         rd: WritableReg,
631         rn: Reg,
632         rm: Reg,
633         imm4: u8,
634     },
635     VecTbl {
636         rd: WritableReg,
637         rn: Reg,
638         rm: Reg,
639         is_extension: bool,
640     },
641     VecTbl2 {
642         rd: WritableReg,
643         rn: Reg,
644         rn2: Reg,
645         rm: Reg,
646         is_extension: bool,
647     },
648     VecLoadReplicate {
649         rd: WritableReg,
650         rn: Reg,
651         size: VectorSize,
652     },
653     VecCSel {
654         rd: WritableReg,
655         rn: Reg,
656         rm: Reg,
657         cond: Cond,
658     },
659     MovToNZCV {
660         rn: Reg,
661     },
662     MovFromNZCV {
663         rd: WritableReg,
664     },
665     Call {
666         info: BoxCallInfo,
667     },
668     CallInd {
669         info: BoxCallIndInfo,
670     },
671     Ret {
672         rets: VecReg,
673     },
674     EpiloguePlaceholder,
675     Jump {
676         dest: BranchTarget,
677     },
678     CondBr {
679         taken: BranchTarget,
680         not_taken: BranchTarget,
681         kind: CondBrKind,
682     },
683     TrapIf {
684         kind: CondBrKind,
685         trap_code: TrapCode,
686     },
687     IndirectBr {
688         rn: Reg,
689         targets: VecMachLabel,
690     },
691     Brk,
692     Udf {
693         trap_code: TrapCode,
694     },
695     Adr {
696         rd: WritableReg,
697         off: i32,
698     },
699     Word4 {
700         data: u32,
701     },
702     Word8 {
703         data: u64,
704     },
705     JTSequence {
706         info: BoxJTSequenceInfo,
707         ridx: Reg,
708         rtmp1: WritableReg,
709         rtmp2: WritableReg,
710     },
711     LoadExtName {
712         rd: WritableReg,
713         name: BoxExternalName,
714         offset: i64,
715     },
716     LoadAddr {
717         rd: WritableReg,
718         mem: AMode,
719     },
720     VirtualSPOffsetAdj {
721         offset: i64,
722     },
723     EmitIsland {
724         needed_space: CodeOffset,
725     },
726     ElfTlsGetAddr {
727         symbol: ExternalName,
728     },
729     Unwind {
730         inst: UnwindInst,
731     },
732     DummyUse {
733         reg: Reg,
734     },
735 }
736 
737 /// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 779.
738 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
739 pub enum ALUOp {
740     Add,
741     Sub,
742     Orr,
743     OrrNot,
744     And,
745     AndS,
746     AndNot,
747     Eor,
748     EorNot,
749     AddS,
750     SubS,
751     SMulH,
752     UMulH,
753     SDiv,
754     UDiv,
755     RotR,
756     Lsr,
757     Asr,
758     Lsl,
759     Adc,
760     AdcS,
761     Sbc,
762     SbcS,
763 }
764 
765 /// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 817.
766 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
767 pub enum ALUOp3 {
768     MAdd,
769     MSub,
770 }
771 
772 /// Internal type MoveWideOp: defined at src/isa/aarch64/inst.isle line 825.
773 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
774 pub enum MoveWideOp {
775     MovZ,
776     MovN,
777     MovK,
778 }
779 
780 /// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 863.
781 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
782 pub enum BitOp {
783     RBit,
784     Clz,
785     Cls,
786 }
787 
788 /// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 930.
789 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
790 pub enum FPUOp1 {
791     Abs,
792     Neg,
793     Sqrt,
794     Cvt32To64,
795     Cvt64To32,
796 }
797 
798 /// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 940.
799 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
800 pub enum FPUOp2 {
801     Add,
802     Sub,
803     Mul,
804     Div,
805     Max,
806     Min,
807 }
808 
809 /// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 951.
810 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
811 pub enum FPUOp3 {
812     MAdd32,
813     MAdd64,
814 }
815 
816 /// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 958.
817 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
818 pub enum FpuToIntOp {
819     F32ToU32,
820     F32ToI32,
821     F32ToU64,
822     F32ToI64,
823     F64ToU32,
824     F64ToI32,
825     F64ToU64,
826     F64ToI64,
827 }
828 
829 /// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 971.
830 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
831 pub enum IntToFpuOp {
832     U32ToF32,
833     I32ToF32,
834     U32ToF64,
835     I32ToF64,
836     U64ToF32,
837     I64ToF32,
838     U64ToF64,
839     I64ToF64,
840 }
841 
842 /// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 985.
843 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
844 pub enum FpuRoundMode {
845     Minus32,
846     Minus64,
847     Plus32,
848     Plus64,
849     Zero32,
850     Zero64,
851     Nearest32,
852     Nearest64,
853 }
854 
855 /// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 998.
856 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
857 pub enum VecExtendOp {
858     Sxtl8,
859     Sxtl16,
860     Sxtl32,
861     Uxtl8,
862     Uxtl16,
863     Uxtl32,
864 }
865 
866 /// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1015.
867 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
868 pub enum VecALUOp {
869     Sqadd,
870     Uqadd,
871     Sqsub,
872     Uqsub,
873     Cmeq,
874     Cmge,
875     Cmgt,
876     Cmhs,
877     Cmhi,
878     Fcmeq,
879     Fcmgt,
880     Fcmge,
881     And,
882     Bic,
883     Orr,
884     Eor,
885     Bsl,
886     Umaxp,
887     Add,
888     Sub,
889     Mul,
890     Sshl,
891     Ushl,
892     Umin,
893     Smin,
894     Umax,
895     Smax,
896     Urhadd,
897     Fadd,
898     Fsub,
899     Fdiv,
900     Fmax,
901     Fmin,
902     Fmul,
903     Addp,
904     Zip1,
905     Sqrdmulh,
906 }
907 
908 /// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1094.
909 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
910 pub enum VecMisc2 {
911     Not,
912     Neg,
913     Abs,
914     Fabs,
915     Fneg,
916     Fsqrt,
917     Rev64,
918     Fcvtzs,
919     Fcvtzu,
920     Scvtf,
921     Ucvtf,
922     Frintn,
923     Frintz,
924     Frintm,
925     Frintp,
926     Cnt,
927     Cmeq0,
928     Cmge0,
929     Cmgt0,
930     Cmle0,
931     Cmlt0,
932     Fcmeq0,
933     Fcmge0,
934     Fcmgt0,
935     Fcmle0,
936     Fcmlt0,
937 }
938 
939 /// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1151.
940 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
941 pub enum VecRRLongOp {
942     Fcvtl16,
943     Fcvtl32,
944     Shll8,
945     Shll16,
946     Shll32,
947 }
948 
949 /// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1166.
950 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
951 pub enum VecRRNarrowOp {
952     Xtn16,
953     Xtn32,
954     Xtn64,
955     Sqxtn16,
956     Sqxtn32,
957     Sqxtn64,
958     Sqxtun16,
959     Sqxtun32,
960     Sqxtun64,
961     Uqxtn16,
962     Uqxtn32,
963     Uqxtn64,
964     Fcvtn32,
965     Fcvtn64,
966 }
967 
968 /// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1198.
969 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
970 pub enum VecRRRLongOp {
971     Smull8,
972     Smull16,
973     Smull32,
974     Umull8,
975     Umull16,
976     Umull32,
977     Umlal8,
978     Umlal16,
979     Umlal32,
980 }
981 
982 /// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1215.
983 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
984 pub enum VecPairOp {
985     Addp,
986 }
987 
988 /// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1223.
989 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
990 pub enum VecRRPairLongOp {
991     Saddlp8,
992     Saddlp16,
993     Uaddlp8,
994     Uaddlp16,
995 }
996 
997 /// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1234.
998 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
999 pub enum VecLanesOp {
1000     Addv,
1001     Uminv,
1002 }
1003 
1004 /// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1243.
1005 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1006 pub enum VecShiftImmOp {
1007     Shl,
1008     Ushr,
1009     Sshr,
1010 }
1011 
1012 /// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1254.
1013 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1014 pub enum AtomicRMWOp {
1015     Add,
1016     Clr,
1017     Eor,
1018     Set,
1019     Smax,
1020     Smin,
1021     Umax,
1022     Umin,
1023 }
1024 
1025 // Generated as internal constructor for term output_reg.
1026 pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
1027     let pattern0_0 = arg0;
1028     // Rule at src/prelude.isle line 86.
1029     let expr0_0 = C::value_reg(ctx, pattern0_0);
1030     let expr1_0 = C::output(ctx, expr0_0);
1031     return Some(expr1_0);
1032 }
1033 
1034 // Generated as internal constructor for term output_value.
1035 pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> {
1036     let pattern0_0 = arg0;
1037     // Rule at src/prelude.isle line 90.
1038     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1039     let expr1_0 = C::output(ctx, expr0_0);
1040     return Some(expr1_0);
1041 }
1042 
1043 // Generated as internal constructor for term temp_reg.
1044 pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
1045     let pattern0_0 = arg0;
1046     // Rule at src/prelude.isle line 110.
1047     let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
1048     let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
1049     return Some(expr1_0);
1050 }
1051 
1052 // Generated as internal constructor for term lo_reg.
1053 pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
1054     let pattern0_0 = arg0;
1055     // Rule at src/prelude.isle line 145.
1056     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1057     let expr1_0: usize = 0;
1058     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1059     return Some(expr2_0);
1060 }
1061 
1062 // Generated as internal constructor for term side_effect.
1063 pub fn constructor_side_effect<C: Context>(
1064     ctx: &mut C,
1065     arg0: &SideEffectNoResult,
1066 ) -> Option<InstOutput> {
1067     let pattern0_0 = arg0;
1068     if let &SideEffectNoResult::Inst {
1069         inst: ref pattern1_0,
1070     } = pattern0_0
1071     {
1072         // Rule at src/prelude.isle line 407.
1073         let expr0_0 = C::emit(ctx, pattern1_0);
1074         let expr1_0 = C::output_none(ctx);
1075         return Some(expr1_0);
1076     }
1077     return None;
1078 }
1079 
1080 // Generated as internal constructor for term produces_flags_get_reg.
1081 pub fn constructor_produces_flags_get_reg<C: Context>(
1082     ctx: &mut C,
1083     arg0: &ProducesFlags,
1084 ) -> Option<Reg> {
1085     let pattern0_0 = arg0;
1086     if let &ProducesFlags::ProducesFlagsReturnsReg {
1087         inst: ref pattern1_0,
1088         result: pattern1_1,
1089     } = pattern0_0
1090     {
1091         // Rule at src/prelude.isle line 445.
1092         return Some(pattern1_1);
1093     }
1094     return None;
1095 }
1096 
1097 // Generated as internal constructor for term produces_flags_ignore.
1098 pub fn constructor_produces_flags_ignore<C: Context>(
1099     ctx: &mut C,
1100     arg0: &ProducesFlags,
1101 ) -> Option<ProducesFlags> {
1102     let pattern0_0 = arg0;
1103     match pattern0_0 {
1104         &ProducesFlags::ProducesFlagsReturnsReg {
1105             inst: ref pattern1_0,
1106             result: pattern1_1,
1107         } => {
1108             // Rule at src/prelude.isle line 450.
1109             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1110                 inst: pattern1_0.clone(),
1111             };
1112             return Some(expr0_0);
1113         }
1114         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1115             inst: ref pattern1_0,
1116             result: pattern1_1,
1117         } => {
1118             // Rule at src/prelude.isle line 452.
1119             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1120                 inst: pattern1_0.clone(),
1121             };
1122             return Some(expr0_0);
1123         }
1124         _ => {}
1125     }
1126     return None;
1127 }
1128 
1129 // Generated as internal constructor for term consumes_flags_concat.
1130 pub fn constructor_consumes_flags_concat<C: Context>(
1131     ctx: &mut C,
1132     arg0: &ConsumesFlags,
1133     arg1: &ConsumesFlags,
1134 ) -> Option<ConsumesFlags> {
1135     let pattern0_0 = arg0;
1136     if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1137         inst: ref pattern1_0,
1138         result: pattern1_1,
1139     } = pattern0_0
1140     {
1141         let pattern2_0 = arg1;
1142         if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1143             inst: ref pattern3_0,
1144             result: pattern3_1,
1145         } = pattern2_0
1146         {
1147             // Rule at src/prelude.isle line 459.
1148             let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1149             let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1150                 inst1: pattern1_0.clone(),
1151                 inst2: pattern3_0.clone(),
1152                 result: expr0_0,
1153             };
1154             return Some(expr1_0);
1155         }
1156     }
1157     return None;
1158 }
1159 
1160 // Generated as internal constructor for term with_flags.
1161 pub fn constructor_with_flags<C: Context>(
1162     ctx: &mut C,
1163     arg0: &ProducesFlags,
1164     arg1: &ConsumesFlags,
1165 ) -> Option<ValueRegs> {
1166     let pattern0_0 = arg0;
1167     match pattern0_0 {
1168         &ProducesFlags::ProducesFlagsSideEffect {
1169             inst: ref pattern1_0,
1170         } => {
1171             let pattern2_0 = arg1;
1172             match pattern2_0 {
1173                 &ConsumesFlags::ConsumesFlagsReturnsReg {
1174                     inst: ref pattern3_0,
1175                     result: pattern3_1,
1176                 } => {
1177                     // Rule at src/prelude.isle line 484.
1178                     let expr0_0 = C::emit(ctx, pattern1_0);
1179                     let expr1_0 = C::emit(ctx, pattern3_0);
1180                     let expr2_0 = C::value_reg(ctx, pattern3_1);
1181                     return Some(expr2_0);
1182                 }
1183                 &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1184                     inst1: ref pattern3_0,
1185                     inst2: ref pattern3_1,
1186                     result: pattern3_2,
1187                 } => {
1188                     // Rule at src/prelude.isle line 490.
1189                     let expr0_0 = C::emit(ctx, pattern1_0);
1190                     let expr1_0 = C::emit(ctx, pattern3_0);
1191                     let expr2_0 = C::emit(ctx, pattern3_1);
1192                     return Some(pattern3_2);
1193                 }
1194                 &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs {
1195                     inst1: ref pattern3_0,
1196                     inst2: ref pattern3_1,
1197                     inst3: ref pattern3_2,
1198                     inst4: ref pattern3_3,
1199                     result: pattern3_4,
1200                 } => {
1201                     // Rule at src/prelude.isle line 502.
1202                     let expr0_0 = C::emit(ctx, pattern1_0);
1203                     let expr1_0 = C::emit(ctx, pattern3_0);
1204                     let expr2_0 = C::emit(ctx, pattern3_1);
1205                     let expr3_0 = C::emit(ctx, pattern3_2);
1206                     let expr4_0 = C::emit(ctx, pattern3_3);
1207                     return Some(pattern3_4);
1208                 }
1209                 _ => {}
1210             }
1211         }
1212         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1213             inst: ref pattern1_0,
1214             result: pattern1_1,
1215         } => {
1216             let pattern2_0 = arg1;
1217             if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1218                 inst: ref pattern3_0,
1219                 result: pattern3_1,
1220             } = pattern2_0
1221             {
1222                 // Rule at src/prelude.isle line 478.
1223                 let expr0_0 = C::emit(ctx, pattern1_0);
1224                 let expr1_0 = C::emit(ctx, pattern3_0);
1225                 let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1226                 return Some(expr2_0);
1227             }
1228         }
1229         _ => {}
1230     }
1231     return None;
1232 }
1233 
1234 // Generated as internal constructor for term with_flags_reg.
1235 pub fn constructor_with_flags_reg<C: Context>(
1236     ctx: &mut C,
1237     arg0: &ProducesFlags,
1238     arg1: &ConsumesFlags,
1239 ) -> Option<Reg> {
1240     let pattern0_0 = arg0;
1241     let pattern1_0 = arg1;
1242     // Rule at src/prelude.isle line 519.
1243     let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?;
1244     let expr1_0: usize = 0;
1245     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1246     return Some(expr2_0);
1247 }
1248 
1249 // Generated as internal constructor for term operand_size.
1250 pub fn constructor_operand_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
1251     let pattern0_0 = arg0;
1252     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
1253         // Rule at src/isa/aarch64/inst.isle line 881.
1254         let expr0_0 = OperandSize::Size32;
1255         return Some(expr0_0);
1256     }
1257     if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
1258         // Rule at src/isa/aarch64/inst.isle line 882.
1259         let expr0_0 = OperandSize::Size64;
1260         return Some(expr0_0);
1261     }
1262     return None;
1263 }
1264 
1265 // Generated as internal constructor for term vector_size.
1266 pub fn constructor_vector_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<VectorSize> {
1267     let pattern0_0 = arg0;
1268     if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
1269         if pattern1_0 == 8 {
1270             if pattern1_1 == 16 {
1271                 // Rule at src/isa/aarch64/inst.isle line 924.
1272                 let expr0_0 = VectorSize::Size8x16;
1273                 return Some(expr0_0);
1274             }
1275         }
1276         if pattern1_0 == 16 {
1277             if pattern1_1 == 8 {
1278                 // Rule at src/isa/aarch64/inst.isle line 925.
1279                 let expr0_0 = VectorSize::Size16x8;
1280                 return Some(expr0_0);
1281             }
1282         }
1283         if pattern1_0 == 32 {
1284             if pattern1_1 == 4 {
1285                 // Rule at src/isa/aarch64/inst.isle line 926.
1286                 let expr0_0 = VectorSize::Size32x4;
1287                 return Some(expr0_0);
1288             }
1289         }
1290         if pattern1_0 == 64 {
1291             if pattern1_1 == 2 {
1292                 // Rule at src/isa/aarch64/inst.isle line 927.
1293                 let expr0_0 = VectorSize::Size64x2;
1294                 return Some(expr0_0);
1295             }
1296         }
1297     }
1298     return None;
1299 }
1300 
1301 // Generated as internal constructor for term movz.
1302 pub fn constructor_movz<C: Context>(
1303     ctx: &mut C,
1304     arg0: MoveWideConst,
1305     arg1: &OperandSize,
1306 ) -> Option<Reg> {
1307     let pattern0_0 = arg0;
1308     let pattern1_0 = arg1;
1309     // Rule at src/isa/aarch64/inst.isle line 1350.
1310     let expr0_0: Type = I64;
1311     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1312     let expr2_0 = MoveWideOp::MovZ;
1313     let expr3_0 = MInst::MovWide {
1314         op: expr2_0,
1315         rd: expr1_0,
1316         imm: pattern0_0,
1317         size: pattern1_0.clone(),
1318     };
1319     let expr4_0 = C::emit(ctx, &expr3_0);
1320     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1321     return Some(expr5_0);
1322 }
1323 
1324 // Generated as internal constructor for term movn.
1325 pub fn constructor_movn<C: Context>(
1326     ctx: &mut C,
1327     arg0: MoveWideConst,
1328     arg1: &OperandSize,
1329 ) -> Option<Reg> {
1330     let pattern0_0 = arg0;
1331     let pattern1_0 = arg1;
1332     // Rule at src/isa/aarch64/inst.isle line 1357.
1333     let expr0_0: Type = I64;
1334     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1335     let expr2_0 = MoveWideOp::MovN;
1336     let expr3_0 = MInst::MovWide {
1337         op: expr2_0,
1338         rd: expr1_0,
1339         imm: pattern0_0,
1340         size: pattern1_0.clone(),
1341     };
1342     let expr4_0 = C::emit(ctx, &expr3_0);
1343     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1344     return Some(expr5_0);
1345 }
1346 
1347 // Generated as internal constructor for term alu_rr_imm_logic.
1348 pub fn constructor_alu_rr_imm_logic<C: Context>(
1349     ctx: &mut C,
1350     arg0: &ALUOp,
1351     arg1: Type,
1352     arg2: Reg,
1353     arg3: ImmLogic,
1354 ) -> Option<Reg> {
1355     let pattern0_0 = arg0;
1356     let pattern1_0 = arg1;
1357     let pattern2_0 = arg2;
1358     let pattern3_0 = arg3;
1359     // Rule at src/isa/aarch64/inst.isle line 1364.
1360     let expr0_0: Type = I64;
1361     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1362     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1363     let expr3_0 = MInst::AluRRImmLogic {
1364         alu_op: pattern0_0.clone(),
1365         size: expr2_0,
1366         rd: expr1_0,
1367         rn: pattern2_0,
1368         imml: pattern3_0,
1369     };
1370     let expr4_0 = C::emit(ctx, &expr3_0);
1371     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1372     return Some(expr5_0);
1373 }
1374 
1375 // Generated as internal constructor for term alu_rr_imm_shift.
1376 pub fn constructor_alu_rr_imm_shift<C: Context>(
1377     ctx: &mut C,
1378     arg0: &ALUOp,
1379     arg1: Type,
1380     arg2: Reg,
1381     arg3: ImmShift,
1382 ) -> Option<Reg> {
1383     let pattern0_0 = arg0;
1384     let pattern1_0 = arg1;
1385     let pattern2_0 = arg2;
1386     let pattern3_0 = arg3;
1387     // Rule at src/isa/aarch64/inst.isle line 1371.
1388     let expr0_0: Type = I64;
1389     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1390     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1391     let expr3_0 = MInst::AluRRImmShift {
1392         alu_op: pattern0_0.clone(),
1393         size: expr2_0,
1394         rd: expr1_0,
1395         rn: pattern2_0,
1396         immshift: pattern3_0,
1397     };
1398     let expr4_0 = C::emit(ctx, &expr3_0);
1399     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1400     return Some(expr5_0);
1401 }
1402 
1403 // Generated as internal constructor for term alu_rrr.
1404 pub fn constructor_alu_rrr<C: Context>(
1405     ctx: &mut C,
1406     arg0: &ALUOp,
1407     arg1: Type,
1408     arg2: Reg,
1409     arg3: Reg,
1410 ) -> Option<Reg> {
1411     let pattern0_0 = arg0;
1412     let pattern1_0 = arg1;
1413     let pattern2_0 = arg2;
1414     let pattern3_0 = arg3;
1415     // Rule at src/isa/aarch64/inst.isle line 1378.
1416     let expr0_0: Type = I64;
1417     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1418     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1419     let expr3_0 = MInst::AluRRR {
1420         alu_op: pattern0_0.clone(),
1421         size: expr2_0,
1422         rd: expr1_0,
1423         rn: pattern2_0,
1424         rm: pattern3_0,
1425     };
1426     let expr4_0 = C::emit(ctx, &expr3_0);
1427     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1428     return Some(expr5_0);
1429 }
1430 
1431 // Generated as internal constructor for term vec_rrr.
1432 pub fn constructor_vec_rrr<C: Context>(
1433     ctx: &mut C,
1434     arg0: &VecALUOp,
1435     arg1: Reg,
1436     arg2: Reg,
1437     arg3: &VectorSize,
1438 ) -> Option<Reg> {
1439     let pattern0_0 = arg0;
1440     let pattern1_0 = arg1;
1441     let pattern2_0 = arg2;
1442     let pattern3_0 = arg3;
1443     // Rule at src/isa/aarch64/inst.isle line 1385.
1444     let expr0_0: Type = I8X16;
1445     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1446     let expr2_0 = MInst::VecRRR {
1447         alu_op: pattern0_0.clone(),
1448         rd: expr1_0,
1449         rn: pattern1_0,
1450         rm: pattern2_0,
1451         size: pattern3_0.clone(),
1452     };
1453     let expr3_0 = C::emit(ctx, &expr2_0);
1454     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1455     return Some(expr4_0);
1456 }
1457 
1458 // Generated as internal constructor for term vec_lanes.
1459 pub fn constructor_vec_lanes<C: Context>(
1460     ctx: &mut C,
1461     arg0: &VecLanesOp,
1462     arg1: Reg,
1463     arg2: &VectorSize,
1464 ) -> Option<Reg> {
1465     let pattern0_0 = arg0;
1466     let pattern1_0 = arg1;
1467     let pattern2_0 = arg2;
1468     // Rule at src/isa/aarch64/inst.isle line 1392.
1469     let expr0_0: Type = I8X16;
1470     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1471     let expr2_0 = MInst::VecLanes {
1472         op: pattern0_0.clone(),
1473         rd: expr1_0,
1474         rn: pattern1_0,
1475         size: pattern2_0.clone(),
1476     };
1477     let expr3_0 = C::emit(ctx, &expr2_0);
1478     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1479     return Some(expr4_0);
1480 }
1481 
1482 // Generated as internal constructor for term vec_dup.
1483 pub fn constructor_vec_dup<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
1484     let pattern0_0 = arg0;
1485     let pattern1_0 = arg1;
1486     // Rule at src/isa/aarch64/inst.isle line 1399.
1487     let expr0_0: Type = I8X16;
1488     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1489     let expr2_0 = MInst::VecDup {
1490         rd: expr1_0,
1491         rn: pattern0_0,
1492         size: pattern1_0.clone(),
1493     };
1494     let expr3_0 = C::emit(ctx, &expr2_0);
1495     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1496     return Some(expr4_0);
1497 }
1498 
1499 // Generated as internal constructor for term alu_rr_imm12.
1500 pub fn constructor_alu_rr_imm12<C: Context>(
1501     ctx: &mut C,
1502     arg0: &ALUOp,
1503     arg1: Type,
1504     arg2: Reg,
1505     arg3: Imm12,
1506 ) -> Option<Reg> {
1507     let pattern0_0 = arg0;
1508     let pattern1_0 = arg1;
1509     let pattern2_0 = arg2;
1510     let pattern3_0 = arg3;
1511     // Rule at src/isa/aarch64/inst.isle line 1406.
1512     let expr0_0: Type = I64;
1513     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1514     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1515     let expr3_0 = MInst::AluRRImm12 {
1516         alu_op: pattern0_0.clone(),
1517         size: expr2_0,
1518         rd: expr1_0,
1519         rn: pattern2_0,
1520         imm12: pattern3_0,
1521     };
1522     let expr4_0 = C::emit(ctx, &expr3_0);
1523     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1524     return Some(expr5_0);
1525 }
1526 
1527 // Generated as internal constructor for term alu_rrr_shift.
1528 pub fn constructor_alu_rrr_shift<C: Context>(
1529     ctx: &mut C,
1530     arg0: &ALUOp,
1531     arg1: Type,
1532     arg2: Reg,
1533     arg3: Reg,
1534     arg4: ShiftOpAndAmt,
1535 ) -> Option<Reg> {
1536     let pattern0_0 = arg0;
1537     let pattern1_0 = arg1;
1538     let pattern2_0 = arg2;
1539     let pattern3_0 = arg3;
1540     let pattern4_0 = arg4;
1541     // Rule at src/isa/aarch64/inst.isle line 1413.
1542     let expr0_0: Type = I64;
1543     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1544     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1545     let expr3_0 = MInst::AluRRRShift {
1546         alu_op: pattern0_0.clone(),
1547         size: expr2_0,
1548         rd: expr1_0,
1549         rn: pattern2_0,
1550         rm: pattern3_0,
1551         shiftop: pattern4_0,
1552     };
1553     let expr4_0 = C::emit(ctx, &expr3_0);
1554     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1555     return Some(expr5_0);
1556 }
1557 
1558 // Generated as internal constructor for term alu_rrr_extend.
1559 pub fn constructor_alu_rrr_extend<C: Context>(
1560     ctx: &mut C,
1561     arg0: &ALUOp,
1562     arg1: Type,
1563     arg2: Reg,
1564     arg3: Reg,
1565     arg4: &ExtendOp,
1566 ) -> Option<Reg> {
1567     let pattern0_0 = arg0;
1568     let pattern1_0 = arg1;
1569     let pattern2_0 = arg2;
1570     let pattern3_0 = arg3;
1571     let pattern4_0 = arg4;
1572     // Rule at src/isa/aarch64/inst.isle line 1420.
1573     let expr0_0: Type = I64;
1574     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1575     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1576     let expr3_0 = MInst::AluRRRExtend {
1577         alu_op: pattern0_0.clone(),
1578         size: expr2_0,
1579         rd: expr1_0,
1580         rn: pattern2_0,
1581         rm: pattern3_0,
1582         extendop: pattern4_0.clone(),
1583     };
1584     let expr4_0 = C::emit(ctx, &expr3_0);
1585     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1586     return Some(expr5_0);
1587 }
1588 
1589 // Generated as internal constructor for term alu_rr_extend_reg.
1590 pub fn constructor_alu_rr_extend_reg<C: Context>(
1591     ctx: &mut C,
1592     arg0: &ALUOp,
1593     arg1: Type,
1594     arg2: Reg,
1595     arg3: &ExtendedValue,
1596 ) -> Option<Reg> {
1597     let pattern0_0 = arg0;
1598     let pattern1_0 = arg1;
1599     let pattern2_0 = arg2;
1600     let pattern3_0 = arg3;
1601     // Rule at src/isa/aarch64/inst.isle line 1428.
1602     let expr0_0 = C::put_extended_in_reg(ctx, pattern3_0);
1603     let expr1_0 = C::get_extended_op(ctx, pattern3_0);
1604     let expr2_0 =
1605         constructor_alu_rrr_extend(ctx, pattern0_0, pattern1_0, pattern2_0, expr0_0, &expr1_0)?;
1606     return Some(expr2_0);
1607 }
1608 
1609 // Generated as internal constructor for term alu_rrrr.
1610 pub fn constructor_alu_rrrr<C: Context>(
1611     ctx: &mut C,
1612     arg0: &ALUOp3,
1613     arg1: Type,
1614     arg2: Reg,
1615     arg3: Reg,
1616     arg4: Reg,
1617 ) -> Option<Reg> {
1618     let pattern0_0 = arg0;
1619     let pattern1_0 = arg1;
1620     let pattern2_0 = arg2;
1621     let pattern3_0 = arg3;
1622     let pattern4_0 = arg4;
1623     // Rule at src/isa/aarch64/inst.isle line 1435.
1624     let expr0_0: Type = I64;
1625     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1626     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1627     let expr3_0 = MInst::AluRRRR {
1628         alu_op: pattern0_0.clone(),
1629         size: expr2_0,
1630         rd: expr1_0,
1631         rn: pattern2_0,
1632         rm: pattern3_0,
1633         ra: pattern4_0,
1634     };
1635     let expr4_0 = C::emit(ctx, &expr3_0);
1636     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1637     return Some(expr5_0);
1638 }
1639 
1640 // Generated as internal constructor for term bit_rr.
1641 pub fn constructor_bit_rr<C: Context>(
1642     ctx: &mut C,
1643     arg0: &BitOp,
1644     arg1: Type,
1645     arg2: Reg,
1646 ) -> Option<Reg> {
1647     let pattern0_0 = arg0;
1648     let pattern1_0 = arg1;
1649     let pattern2_0 = arg2;
1650     // Rule at src/isa/aarch64/inst.isle line 1442.
1651     let expr0_0: Type = I64;
1652     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1653     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1654     let expr3_0 = MInst::BitRR {
1655         op: pattern0_0.clone(),
1656         size: expr2_0,
1657         rd: expr1_0,
1658         rn: pattern2_0,
1659     };
1660     let expr4_0 = C::emit(ctx, &expr3_0);
1661     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1662     return Some(expr5_0);
1663 }
1664 
1665 // Generated as internal constructor for term add_with_flags_paired.
1666 pub fn constructor_add_with_flags_paired<C: Context>(
1667     ctx: &mut C,
1668     arg0: Type,
1669     arg1: Reg,
1670     arg2: Reg,
1671 ) -> Option<ProducesFlags> {
1672     let pattern0_0 = arg0;
1673     let pattern1_0 = arg1;
1674     let pattern2_0 = arg2;
1675     // Rule at src/isa/aarch64/inst.isle line 1449.
1676     let expr0_0: Type = I64;
1677     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1678     let expr2_0 = ALUOp::AddS;
1679     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1680     let expr4_0 = MInst::AluRRR {
1681         alu_op: expr2_0,
1682         size: expr3_0,
1683         rd: expr1_0,
1684         rn: pattern1_0,
1685         rm: pattern2_0,
1686     };
1687     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1688     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1689         inst: expr4_0,
1690         result: expr5_0,
1691     };
1692     return Some(expr6_0);
1693 }
1694 
1695 // Generated as internal constructor for term adc_paired.
1696 pub fn constructor_adc_paired<C: Context>(
1697     ctx: &mut C,
1698     arg0: Type,
1699     arg1: Reg,
1700     arg2: Reg,
1701 ) -> Option<ConsumesFlags> {
1702     let pattern0_0 = arg0;
1703     let pattern1_0 = arg1;
1704     let pattern2_0 = arg2;
1705     // Rule at src/isa/aarch64/inst.isle line 1457.
1706     let expr0_0: Type = I64;
1707     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1708     let expr2_0 = ALUOp::Adc;
1709     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1710     let expr4_0 = MInst::AluRRR {
1711         alu_op: expr2_0,
1712         size: expr3_0,
1713         rd: expr1_0,
1714         rn: pattern1_0,
1715         rm: pattern2_0,
1716     };
1717     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1718     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1719         inst: expr4_0,
1720         result: expr5_0,
1721     };
1722     return Some(expr6_0);
1723 }
1724 
1725 // Generated as internal constructor for term sub_with_flags_paired.
1726 pub fn constructor_sub_with_flags_paired<C: Context>(
1727     ctx: &mut C,
1728     arg0: Type,
1729     arg1: Reg,
1730     arg2: Reg,
1731 ) -> Option<ProducesFlags> {
1732     let pattern0_0 = arg0;
1733     let pattern1_0 = arg1;
1734     let pattern2_0 = arg2;
1735     // Rule at src/isa/aarch64/inst.isle line 1465.
1736     let expr0_0: Type = I64;
1737     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1738     let expr2_0 = ALUOp::SubS;
1739     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1740     let expr4_0 = MInst::AluRRR {
1741         alu_op: expr2_0,
1742         size: expr3_0,
1743         rd: expr1_0,
1744         rn: pattern1_0,
1745         rm: pattern2_0,
1746     };
1747     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1748     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1749         inst: expr4_0,
1750         result: expr5_0,
1751     };
1752     return Some(expr6_0);
1753 }
1754 
1755 // Generated as internal constructor for term cmp64_imm.
1756 pub fn constructor_cmp64_imm<C: Context>(
1757     ctx: &mut C,
1758     arg0: Reg,
1759     arg1: Imm12,
1760 ) -> Option<ProducesFlags> {
1761     let pattern0_0 = arg0;
1762     let pattern1_0 = arg1;
1763     // Rule at src/isa/aarch64/inst.isle line 1472.
1764     let expr0_0 = ALUOp::SubS;
1765     let expr1_0 = OperandSize::Size64;
1766     let expr2_0 = C::writable_zero_reg(ctx);
1767     let expr3_0 = MInst::AluRRImm12 {
1768         alu_op: expr0_0,
1769         size: expr1_0,
1770         rd: expr2_0,
1771         rn: pattern0_0,
1772         imm12: pattern1_0,
1773     };
1774     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
1775     return Some(expr4_0);
1776 }
1777 
1778 // Generated as internal constructor for term sbc_paired.
1779 pub fn constructor_sbc_paired<C: Context>(
1780     ctx: &mut C,
1781     arg0: Type,
1782     arg1: Reg,
1783     arg2: Reg,
1784 ) -> Option<ConsumesFlags> {
1785     let pattern0_0 = arg0;
1786     let pattern1_0 = arg1;
1787     let pattern2_0 = arg2;
1788     // Rule at src/isa/aarch64/inst.isle line 1479.
1789     let expr0_0: Type = I64;
1790     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1791     let expr2_0 = ALUOp::Sbc;
1792     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1793     let expr4_0 = MInst::AluRRR {
1794         alu_op: expr2_0,
1795         size: expr3_0,
1796         rd: expr1_0,
1797         rn: pattern1_0,
1798         rm: pattern2_0,
1799     };
1800     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1801     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1802         inst: expr4_0,
1803         result: expr5_0,
1804     };
1805     return Some(expr6_0);
1806 }
1807 
1808 // Generated as internal constructor for term vec_misc.
1809 pub fn constructor_vec_misc<C: Context>(
1810     ctx: &mut C,
1811     arg0: &VecMisc2,
1812     arg1: Reg,
1813     arg2: &VectorSize,
1814 ) -> Option<Reg> {
1815     let pattern0_0 = arg0;
1816     let pattern1_0 = arg1;
1817     let pattern2_0 = arg2;
1818     // Rule at src/isa/aarch64/inst.isle line 1487.
1819     let expr0_0: Type = I8X16;
1820     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1821     let expr2_0 = MInst::VecMisc {
1822         op: pattern0_0.clone(),
1823         rd: expr1_0,
1824         rn: pattern1_0,
1825         size: pattern2_0.clone(),
1826     };
1827     let expr3_0 = C::emit(ctx, &expr2_0);
1828     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1829     return Some(expr4_0);
1830 }
1831 
1832 // Generated as internal constructor for term vec_rrr_long.
1833 pub fn constructor_vec_rrr_long<C: Context>(
1834     ctx: &mut C,
1835     arg0: &VecRRRLongOp,
1836     arg1: Reg,
1837     arg2: Reg,
1838     arg3: bool,
1839 ) -> Option<Reg> {
1840     let pattern0_0 = arg0;
1841     let pattern1_0 = arg1;
1842     let pattern2_0 = arg2;
1843     let pattern3_0 = arg3;
1844     // Rule at src/isa/aarch64/inst.isle line 1494.
1845     let expr0_0: Type = I8X16;
1846     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1847     let expr2_0 = MInst::VecRRRLong {
1848         alu_op: pattern0_0.clone(),
1849         rd: expr1_0,
1850         rn: pattern1_0,
1851         rm: pattern2_0,
1852         high_half: pattern3_0,
1853     };
1854     let expr3_0 = C::emit(ctx, &expr2_0);
1855     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1856     return Some(expr4_0);
1857 }
1858 
1859 // Generated as internal constructor for term vec_rrrr_long.
1860 pub fn constructor_vec_rrrr_long<C: Context>(
1861     ctx: &mut C,
1862     arg0: &VecRRRLongOp,
1863     arg1: Reg,
1864     arg2: Reg,
1865     arg3: Reg,
1866     arg4: bool,
1867 ) -> Option<Reg> {
1868     let pattern0_0 = arg0;
1869     let pattern1_0 = arg1;
1870     let pattern2_0 = arg2;
1871     let pattern3_0 = arg3;
1872     let pattern4_0 = arg4;
1873     // Rule at src/isa/aarch64/inst.isle line 1504.
1874     let expr0_0: Type = I8X16;
1875     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1876     let expr2_0 = MInst::FpuMove128 {
1877         rd: expr1_0,
1878         rn: pattern1_0,
1879     };
1880     let expr3_0 = C::emit(ctx, &expr2_0);
1881     let expr4_0 = MInst::VecRRRLong {
1882         alu_op: pattern0_0.clone(),
1883         rd: expr1_0,
1884         rn: pattern2_0,
1885         rm: pattern3_0,
1886         high_half: pattern4_0,
1887     };
1888     let expr5_0 = C::emit(ctx, &expr4_0);
1889     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1890     return Some(expr6_0);
1891 }
1892 
1893 // Generated as internal constructor for term vec_rr_narrow.
1894 pub fn constructor_vec_rr_narrow<C: Context>(
1895     ctx: &mut C,
1896     arg0: &VecRRNarrowOp,
1897     arg1: Reg,
1898     arg2: bool,
1899 ) -> Option<Reg> {
1900     let pattern0_0 = arg0;
1901     let pattern1_0 = arg1;
1902     let pattern2_0 = arg2;
1903     // Rule at src/isa/aarch64/inst.isle line 1512.
1904     let expr0_0: Type = I8X16;
1905     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1906     let expr2_0 = MInst::VecRRNarrow {
1907         op: pattern0_0.clone(),
1908         rd: expr1_0,
1909         rn: pattern1_0,
1910         high_half: pattern2_0,
1911     };
1912     let expr3_0 = C::emit(ctx, &expr2_0);
1913     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1914     return Some(expr4_0);
1915 }
1916 
1917 // Generated as internal constructor for term vec_rr_long.
1918 pub fn constructor_vec_rr_long<C: Context>(
1919     ctx: &mut C,
1920     arg0: &VecRRLongOp,
1921     arg1: Reg,
1922     arg2: bool,
1923 ) -> Option<Reg> {
1924     let pattern0_0 = arg0;
1925     let pattern1_0 = arg1;
1926     let pattern2_0 = arg2;
1927     // Rule at src/isa/aarch64/inst.isle line 1519.
1928     let expr0_0: Type = I8X16;
1929     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1930     let expr2_0 = MInst::VecRRLong {
1931         op: pattern0_0.clone(),
1932         rd: expr1_0,
1933         rn: pattern1_0,
1934         high_half: pattern2_0,
1935     };
1936     let expr3_0 = C::emit(ctx, &expr2_0);
1937     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1938     return Some(expr4_0);
1939 }
1940 
1941 // Generated as internal constructor for term mov_to_fpu.
1942 pub fn constructor_mov_to_fpu<C: Context>(
1943     ctx: &mut C,
1944     arg0: Reg,
1945     arg1: &ScalarSize,
1946 ) -> Option<Reg> {
1947     let pattern0_0 = arg0;
1948     let pattern1_0 = arg1;
1949     // Rule at src/isa/aarch64/inst.isle line 1526.
1950     let expr0_0: Type = I8X16;
1951     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1952     let expr2_0 = MInst::MovToFpu {
1953         rd: expr1_0,
1954         rn: pattern0_0,
1955         size: pattern1_0.clone(),
1956     };
1957     let expr3_0 = C::emit(ctx, &expr2_0);
1958     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1959     return Some(expr4_0);
1960 }
1961 
1962 // Generated as internal constructor for term mov_to_vec.
1963 pub fn constructor_mov_to_vec<C: Context>(
1964     ctx: &mut C,
1965     arg0: Reg,
1966     arg1: Reg,
1967     arg2: u8,
1968     arg3: &VectorSize,
1969 ) -> Option<Reg> {
1970     let pattern0_0 = arg0;
1971     let pattern1_0 = arg1;
1972     let pattern2_0 = arg2;
1973     let pattern3_0 = arg3;
1974     // Rule at src/isa/aarch64/inst.isle line 1533.
1975     let expr0_0: Type = I8X16;
1976     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1977     let expr2_0 = MInst::FpuMove128 {
1978         rd: expr1_0,
1979         rn: pattern0_0,
1980     };
1981     let expr3_0 = C::emit(ctx, &expr2_0);
1982     let expr4_0 = MInst::MovToVec {
1983         rd: expr1_0,
1984         rn: pattern1_0,
1985         idx: pattern2_0,
1986         size: pattern3_0.clone(),
1987     };
1988     let expr5_0 = C::emit(ctx, &expr4_0);
1989     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1990     return Some(expr6_0);
1991 }
1992 
1993 // Generated as internal constructor for term mov_from_vec.
1994 pub fn constructor_mov_from_vec<C: Context>(
1995     ctx: &mut C,
1996     arg0: Reg,
1997     arg1: u8,
1998     arg2: &VectorSize,
1999 ) -> Option<Reg> {
2000     let pattern0_0 = arg0;
2001     let pattern1_0 = arg1;
2002     let pattern2_0 = arg2;
2003     // Rule at src/isa/aarch64/inst.isle line 1541.
2004     let expr0_0: Type = I64;
2005     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2006     let expr2_0 = MInst::MovFromVec {
2007         rd: expr1_0,
2008         rn: pattern0_0,
2009         idx: pattern1_0,
2010         size: pattern2_0.clone(),
2011     };
2012     let expr3_0 = C::emit(ctx, &expr2_0);
2013     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2014     return Some(expr4_0);
2015 }
2016 
2017 // Generated as internal constructor for term mov_from_vec_signed.
2018 pub fn constructor_mov_from_vec_signed<C: Context>(
2019     ctx: &mut C,
2020     arg0: Reg,
2021     arg1: u8,
2022     arg2: &VectorSize,
2023     arg3: &OperandSize,
2024 ) -> Option<Reg> {
2025     let pattern0_0 = arg0;
2026     let pattern1_0 = arg1;
2027     let pattern2_0 = arg2;
2028     let pattern3_0 = arg3;
2029     // Rule at src/isa/aarch64/inst.isle line 1548.
2030     let expr0_0: Type = I64;
2031     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2032     let expr2_0 = MInst::MovFromVecSigned {
2033         rd: expr1_0,
2034         rn: pattern0_0,
2035         idx: pattern1_0,
2036         size: pattern2_0.clone(),
2037         scalar_size: pattern3_0.clone(),
2038     };
2039     let expr3_0 = C::emit(ctx, &expr2_0);
2040     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2041     return Some(expr4_0);
2042 }
2043 
2044 // Generated as internal constructor for term extend.
2045 pub fn constructor_extend<C: Context>(
2046     ctx: &mut C,
2047     arg0: Reg,
2048     arg1: bool,
2049     arg2: u8,
2050     arg3: u8,
2051 ) -> Option<Reg> {
2052     let pattern0_0 = arg0;
2053     let pattern1_0 = arg1;
2054     let pattern2_0 = arg2;
2055     let pattern3_0 = arg3;
2056     // Rule at src/isa/aarch64/inst.isle line 1555.
2057     let expr0_0: Type = I64;
2058     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2059     let expr2_0 = MInst::Extend {
2060         rd: expr1_0,
2061         rn: pattern0_0,
2062         signed: pattern1_0,
2063         from_bits: pattern2_0,
2064         to_bits: pattern3_0,
2065     };
2066     let expr3_0 = C::emit(ctx, &expr2_0);
2067     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2068     return Some(expr4_0);
2069 }
2070 
2071 // Generated as internal constructor for term load_acquire.
2072 pub fn constructor_load_acquire<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2073     let pattern0_0 = arg0;
2074     let pattern1_0 = arg1;
2075     // Rule at src/isa/aarch64/inst.isle line 1562.
2076     let expr0_0: Type = I64;
2077     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2078     let expr2_0 = MInst::LoadAcquire {
2079         access_ty: pattern0_0,
2080         rt: expr1_0,
2081         rn: pattern1_0,
2082     };
2083     let expr3_0 = C::emit(ctx, &expr2_0);
2084     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2085     return Some(expr4_0);
2086 }
2087 
2088 // Generated as internal constructor for term tst_imm.
2089 pub fn constructor_tst_imm<C: Context>(
2090     ctx: &mut C,
2091     arg0: Type,
2092     arg1: Reg,
2093     arg2: ImmLogic,
2094 ) -> Option<ProducesFlags> {
2095     let pattern0_0 = arg0;
2096     let pattern1_0 = arg1;
2097     let pattern2_0 = arg2;
2098     // Rule at src/isa/aarch64/inst.isle line 1572.
2099     let expr0_0 = ALUOp::AndS;
2100     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
2101     let expr2_0 = C::writable_zero_reg(ctx);
2102     let expr3_0 = MInst::AluRRImmLogic {
2103         alu_op: expr0_0,
2104         size: expr1_0,
2105         rd: expr2_0,
2106         rn: pattern1_0,
2107         imml: pattern2_0,
2108     };
2109     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
2110     return Some(expr4_0);
2111 }
2112 
2113 // Generated as internal constructor for term csel.
2114 pub fn constructor_csel<C: Context>(
2115     ctx: &mut C,
2116     arg0: &Cond,
2117     arg1: Reg,
2118     arg2: Reg,
2119 ) -> Option<ConsumesFlags> {
2120     let pattern0_0 = arg0;
2121     let pattern1_0 = arg1;
2122     let pattern2_0 = arg2;
2123     // Rule at src/isa/aarch64/inst.isle line 1586.
2124     let expr0_0: Type = I64;
2125     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2126     let expr2_0 = MInst::CSel {
2127         rd: expr1_0,
2128         cond: pattern0_0.clone(),
2129         rn: pattern1_0,
2130         rm: pattern2_0,
2131     };
2132     let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
2133     let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
2134         inst: expr2_0,
2135         result: expr3_0,
2136     };
2137     return Some(expr4_0);
2138 }
2139 
2140 // Generated as internal constructor for term add.
2141 pub fn constructor_add<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2142     let pattern0_0 = arg0;
2143     let pattern1_0 = arg1;
2144     let pattern2_0 = arg2;
2145     // Rule at src/isa/aarch64/inst.isle line 1595.
2146     let expr0_0 = ALUOp::Add;
2147     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2148     return Some(expr1_0);
2149 }
2150 
2151 // Generated as internal constructor for term add_imm.
2152 pub fn constructor_add_imm<C: Context>(
2153     ctx: &mut C,
2154     arg0: Type,
2155     arg1: Reg,
2156     arg2: Imm12,
2157 ) -> Option<Reg> {
2158     let pattern0_0 = arg0;
2159     let pattern1_0 = arg1;
2160     let pattern2_0 = arg2;
2161     // Rule at src/isa/aarch64/inst.isle line 1598.
2162     let expr0_0 = ALUOp::Add;
2163     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2164     return Some(expr1_0);
2165 }
2166 
2167 // Generated as internal constructor for term add_extend.
2168 pub fn constructor_add_extend<C: Context>(
2169     ctx: &mut C,
2170     arg0: Type,
2171     arg1: Reg,
2172     arg2: &ExtendedValue,
2173 ) -> Option<Reg> {
2174     let pattern0_0 = arg0;
2175     let pattern1_0 = arg1;
2176     let pattern2_0 = arg2;
2177     // Rule at src/isa/aarch64/inst.isle line 1601.
2178     let expr0_0 = ALUOp::Add;
2179     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2180     return Some(expr1_0);
2181 }
2182 
2183 // Generated as internal constructor for term add_shift.
2184 pub fn constructor_add_shift<C: Context>(
2185     ctx: &mut C,
2186     arg0: Type,
2187     arg1: Reg,
2188     arg2: Reg,
2189     arg3: ShiftOpAndAmt,
2190 ) -> Option<Reg> {
2191     let pattern0_0 = arg0;
2192     let pattern1_0 = arg1;
2193     let pattern2_0 = arg2;
2194     let pattern3_0 = arg3;
2195     // Rule at src/isa/aarch64/inst.isle line 1604.
2196     let expr0_0 = ALUOp::Add;
2197     let expr1_0 = constructor_alu_rrr_shift(
2198         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2199     )?;
2200     return Some(expr1_0);
2201 }
2202 
2203 // Generated as internal constructor for term add_vec.
2204 pub fn constructor_add_vec<C: Context>(
2205     ctx: &mut C,
2206     arg0: Reg,
2207     arg1: Reg,
2208     arg2: &VectorSize,
2209 ) -> Option<Reg> {
2210     let pattern0_0 = arg0;
2211     let pattern1_0 = arg1;
2212     let pattern2_0 = arg2;
2213     // Rule at src/isa/aarch64/inst.isle line 1607.
2214     let expr0_0 = VecALUOp::Add;
2215     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2216     return Some(expr1_0);
2217 }
2218 
2219 // Generated as internal constructor for term sub.
2220 pub fn constructor_sub<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2221     let pattern0_0 = arg0;
2222     let pattern1_0 = arg1;
2223     let pattern2_0 = arg2;
2224     // Rule at src/isa/aarch64/inst.isle line 1612.
2225     let expr0_0 = ALUOp::Sub;
2226     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2227     return Some(expr1_0);
2228 }
2229 
2230 // Generated as internal constructor for term sub_imm.
2231 pub fn constructor_sub_imm<C: Context>(
2232     ctx: &mut C,
2233     arg0: Type,
2234     arg1: Reg,
2235     arg2: Imm12,
2236 ) -> Option<Reg> {
2237     let pattern0_0 = arg0;
2238     let pattern1_0 = arg1;
2239     let pattern2_0 = arg2;
2240     // Rule at src/isa/aarch64/inst.isle line 1615.
2241     let expr0_0 = ALUOp::Sub;
2242     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2243     return Some(expr1_0);
2244 }
2245 
2246 // Generated as internal constructor for term sub_extend.
2247 pub fn constructor_sub_extend<C: Context>(
2248     ctx: &mut C,
2249     arg0: Type,
2250     arg1: Reg,
2251     arg2: &ExtendedValue,
2252 ) -> Option<Reg> {
2253     let pattern0_0 = arg0;
2254     let pattern1_0 = arg1;
2255     let pattern2_0 = arg2;
2256     // Rule at src/isa/aarch64/inst.isle line 1618.
2257     let expr0_0 = ALUOp::Sub;
2258     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2259     return Some(expr1_0);
2260 }
2261 
2262 // Generated as internal constructor for term sub_shift.
2263 pub fn constructor_sub_shift<C: Context>(
2264     ctx: &mut C,
2265     arg0: Type,
2266     arg1: Reg,
2267     arg2: Reg,
2268     arg3: ShiftOpAndAmt,
2269 ) -> Option<Reg> {
2270     let pattern0_0 = arg0;
2271     let pattern1_0 = arg1;
2272     let pattern2_0 = arg2;
2273     let pattern3_0 = arg3;
2274     // Rule at src/isa/aarch64/inst.isle line 1621.
2275     let expr0_0 = ALUOp::Sub;
2276     let expr1_0 = constructor_alu_rrr_shift(
2277         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2278     )?;
2279     return Some(expr1_0);
2280 }
2281 
2282 // Generated as internal constructor for term sub_vec.
2283 pub fn constructor_sub_vec<C: Context>(
2284     ctx: &mut C,
2285     arg0: Reg,
2286     arg1: Reg,
2287     arg2: &VectorSize,
2288 ) -> Option<Reg> {
2289     let pattern0_0 = arg0;
2290     let pattern1_0 = arg1;
2291     let pattern2_0 = arg2;
2292     // Rule at src/isa/aarch64/inst.isle line 1624.
2293     let expr0_0 = VecALUOp::Sub;
2294     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2295     return Some(expr1_0);
2296 }
2297 
2298 // Generated as internal constructor for term madd.
2299 pub fn constructor_madd<C: Context>(
2300     ctx: &mut C,
2301     arg0: Type,
2302     arg1: Reg,
2303     arg2: Reg,
2304     arg3: Reg,
2305 ) -> Option<Reg> {
2306     let pattern0_0 = arg0;
2307     let pattern1_0 = arg1;
2308     let pattern2_0 = arg2;
2309     let pattern3_0 = arg3;
2310     // Rule at src/isa/aarch64/inst.isle line 1629.
2311     let expr0_0 = ALUOp3::MAdd;
2312     let expr1_0 = constructor_alu_rrrr(
2313         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2314     )?;
2315     return Some(expr1_0);
2316 }
2317 
2318 // Generated as internal constructor for term msub.
2319 pub fn constructor_msub<C: Context>(
2320     ctx: &mut C,
2321     arg0: Type,
2322     arg1: Reg,
2323     arg2: Reg,
2324     arg3: Reg,
2325 ) -> Option<Reg> {
2326     let pattern0_0 = arg0;
2327     let pattern1_0 = arg1;
2328     let pattern2_0 = arg2;
2329     let pattern3_0 = arg3;
2330     // Rule at src/isa/aarch64/inst.isle line 1634.
2331     let expr0_0 = ALUOp3::MSub;
2332     let expr1_0 = constructor_alu_rrrr(
2333         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2334     )?;
2335     return Some(expr1_0);
2336 }
2337 
2338 // Generated as internal constructor for term uqadd.
2339 pub fn constructor_uqadd<C: Context>(
2340     ctx: &mut C,
2341     arg0: Reg,
2342     arg1: Reg,
2343     arg2: &VectorSize,
2344 ) -> Option<Reg> {
2345     let pattern0_0 = arg0;
2346     let pattern1_0 = arg1;
2347     let pattern2_0 = arg2;
2348     // Rule at src/isa/aarch64/inst.isle line 1638.
2349     let expr0_0 = VecALUOp::Uqadd;
2350     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2351     return Some(expr1_0);
2352 }
2353 
2354 // Generated as internal constructor for term sqadd.
2355 pub fn constructor_sqadd<C: Context>(
2356     ctx: &mut C,
2357     arg0: Reg,
2358     arg1: Reg,
2359     arg2: &VectorSize,
2360 ) -> Option<Reg> {
2361     let pattern0_0 = arg0;
2362     let pattern1_0 = arg1;
2363     let pattern2_0 = arg2;
2364     // Rule at src/isa/aarch64/inst.isle line 1642.
2365     let expr0_0 = VecALUOp::Sqadd;
2366     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2367     return Some(expr1_0);
2368 }
2369 
2370 // Generated as internal constructor for term uqsub.
2371 pub fn constructor_uqsub<C: Context>(
2372     ctx: &mut C,
2373     arg0: Reg,
2374     arg1: Reg,
2375     arg2: &VectorSize,
2376 ) -> Option<Reg> {
2377     let pattern0_0 = arg0;
2378     let pattern1_0 = arg1;
2379     let pattern2_0 = arg2;
2380     // Rule at src/isa/aarch64/inst.isle line 1646.
2381     let expr0_0 = VecALUOp::Uqsub;
2382     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2383     return Some(expr1_0);
2384 }
2385 
2386 // Generated as internal constructor for term sqsub.
2387 pub fn constructor_sqsub<C: Context>(
2388     ctx: &mut C,
2389     arg0: Reg,
2390     arg1: Reg,
2391     arg2: &VectorSize,
2392 ) -> Option<Reg> {
2393     let pattern0_0 = arg0;
2394     let pattern1_0 = arg1;
2395     let pattern2_0 = arg2;
2396     // Rule at src/isa/aarch64/inst.isle line 1650.
2397     let expr0_0 = VecALUOp::Sqsub;
2398     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2399     return Some(expr1_0);
2400 }
2401 
2402 // Generated as internal constructor for term umulh.
2403 pub fn constructor_umulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2404     let pattern0_0 = arg0;
2405     let pattern1_0 = arg1;
2406     let pattern2_0 = arg2;
2407     // Rule at src/isa/aarch64/inst.isle line 1654.
2408     let expr0_0 = ALUOp::UMulH;
2409     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2410     return Some(expr1_0);
2411 }
2412 
2413 // Generated as internal constructor for term smulh.
2414 pub fn constructor_smulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2415     let pattern0_0 = arg0;
2416     let pattern1_0 = arg1;
2417     let pattern2_0 = arg2;
2418     // Rule at src/isa/aarch64/inst.isle line 1658.
2419     let expr0_0 = ALUOp::SMulH;
2420     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2421     return Some(expr1_0);
2422 }
2423 
2424 // Generated as internal constructor for term mul.
2425 pub fn constructor_mul<C: Context>(
2426     ctx: &mut C,
2427     arg0: Reg,
2428     arg1: Reg,
2429     arg2: &VectorSize,
2430 ) -> Option<Reg> {
2431     let pattern0_0 = arg0;
2432     let pattern1_0 = arg1;
2433     let pattern2_0 = arg2;
2434     // Rule at src/isa/aarch64/inst.isle line 1662.
2435     let expr0_0 = VecALUOp::Mul;
2436     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2437     return Some(expr1_0);
2438 }
2439 
2440 // Generated as internal constructor for term neg.
2441 pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2442     let pattern0_0 = arg0;
2443     let pattern1_0 = arg1;
2444     // Rule at src/isa/aarch64/inst.isle line 1666.
2445     let expr0_0 = VecMisc2::Neg;
2446     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2447     return Some(expr1_0);
2448 }
2449 
2450 // Generated as internal constructor for term rev64.
2451 pub fn constructor_rev64<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2452     let pattern0_0 = arg0;
2453     let pattern1_0 = arg1;
2454     // Rule at src/isa/aarch64/inst.isle line 1670.
2455     let expr0_0 = VecMisc2::Rev64;
2456     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2457     return Some(expr1_0);
2458 }
2459 
2460 // Generated as internal constructor for term xtn64.
2461 pub fn constructor_xtn64<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2462     let pattern0_0 = arg0;
2463     let pattern1_0 = arg1;
2464     // Rule at src/isa/aarch64/inst.isle line 1674.
2465     let expr0_0 = VecRRNarrowOp::Xtn64;
2466     let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2467     return Some(expr1_0);
2468 }
2469 
2470 // Generated as internal constructor for term addp.
2471 pub fn constructor_addp<C: Context>(
2472     ctx: &mut C,
2473     arg0: Reg,
2474     arg1: Reg,
2475     arg2: &VectorSize,
2476 ) -> Option<Reg> {
2477     let pattern0_0 = arg0;
2478     let pattern1_0 = arg1;
2479     let pattern2_0 = arg2;
2480     // Rule at src/isa/aarch64/inst.isle line 1678.
2481     let expr0_0 = VecALUOp::Addp;
2482     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2483     return Some(expr1_0);
2484 }
2485 
2486 // Generated as internal constructor for term addv.
2487 pub fn constructor_addv<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2488     let pattern0_0 = arg0;
2489     let pattern1_0 = arg1;
2490     // Rule at src/isa/aarch64/inst.isle line 1682.
2491     let expr0_0 = VecLanesOp::Addv;
2492     let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2493     return Some(expr1_0);
2494 }
2495 
2496 // Generated as internal constructor for term shll32.
2497 pub fn constructor_shll32<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2498     let pattern0_0 = arg0;
2499     let pattern1_0 = arg1;
2500     // Rule at src/isa/aarch64/inst.isle line 1686.
2501     let expr0_0 = VecRRLongOp::Shll32;
2502     let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2503     return Some(expr1_0);
2504 }
2505 
2506 // Generated as internal constructor for term umlal32.
2507 pub fn constructor_umlal32<C: Context>(
2508     ctx: &mut C,
2509     arg0: Reg,
2510     arg1: Reg,
2511     arg2: Reg,
2512     arg3: bool,
2513 ) -> Option<Reg> {
2514     let pattern0_0 = arg0;
2515     let pattern1_0 = arg1;
2516     let pattern2_0 = arg2;
2517     let pattern3_0 = arg3;
2518     // Rule at src/isa/aarch64/inst.isle line 1690.
2519     let expr0_0 = VecRRRLongOp::Umlal32;
2520     let expr1_0 = constructor_vec_rrrr_long(
2521         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2522     )?;
2523     return Some(expr1_0);
2524 }
2525 
2526 // Generated as internal constructor for term smull8.
2527 pub fn constructor_smull8<C: Context>(
2528     ctx: &mut C,
2529     arg0: Reg,
2530     arg1: Reg,
2531     arg2: bool,
2532 ) -> Option<Reg> {
2533     let pattern0_0 = arg0;
2534     let pattern1_0 = arg1;
2535     let pattern2_0 = arg2;
2536     // Rule at src/isa/aarch64/inst.isle line 1694.
2537     let expr0_0 = VecRRRLongOp::Smull8;
2538     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2539     return Some(expr1_0);
2540 }
2541 
2542 // Generated as internal constructor for term umull8.
2543 pub fn constructor_umull8<C: Context>(
2544     ctx: &mut C,
2545     arg0: Reg,
2546     arg1: Reg,
2547     arg2: bool,
2548 ) -> Option<Reg> {
2549     let pattern0_0 = arg0;
2550     let pattern1_0 = arg1;
2551     let pattern2_0 = arg2;
2552     // Rule at src/isa/aarch64/inst.isle line 1698.
2553     let expr0_0 = VecRRRLongOp::Umull8;
2554     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2555     return Some(expr1_0);
2556 }
2557 
2558 // Generated as internal constructor for term smull16.
2559 pub fn constructor_smull16<C: Context>(
2560     ctx: &mut C,
2561     arg0: Reg,
2562     arg1: Reg,
2563     arg2: bool,
2564 ) -> Option<Reg> {
2565     let pattern0_0 = arg0;
2566     let pattern1_0 = arg1;
2567     let pattern2_0 = arg2;
2568     // Rule at src/isa/aarch64/inst.isle line 1702.
2569     let expr0_0 = VecRRRLongOp::Smull16;
2570     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2571     return Some(expr1_0);
2572 }
2573 
2574 // Generated as internal constructor for term umull16.
2575 pub fn constructor_umull16<C: Context>(
2576     ctx: &mut C,
2577     arg0: Reg,
2578     arg1: Reg,
2579     arg2: bool,
2580 ) -> Option<Reg> {
2581     let pattern0_0 = arg0;
2582     let pattern1_0 = arg1;
2583     let pattern2_0 = arg2;
2584     // Rule at src/isa/aarch64/inst.isle line 1706.
2585     let expr0_0 = VecRRRLongOp::Umull16;
2586     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2587     return Some(expr1_0);
2588 }
2589 
2590 // Generated as internal constructor for term smull32.
2591 pub fn constructor_smull32<C: Context>(
2592     ctx: &mut C,
2593     arg0: Reg,
2594     arg1: Reg,
2595     arg2: bool,
2596 ) -> Option<Reg> {
2597     let pattern0_0 = arg0;
2598     let pattern1_0 = arg1;
2599     let pattern2_0 = arg2;
2600     // Rule at src/isa/aarch64/inst.isle line 1710.
2601     let expr0_0 = VecRRRLongOp::Smull32;
2602     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2603     return Some(expr1_0);
2604 }
2605 
2606 // Generated as internal constructor for term umull32.
2607 pub fn constructor_umull32<C: Context>(
2608     ctx: &mut C,
2609     arg0: Reg,
2610     arg1: Reg,
2611     arg2: bool,
2612 ) -> Option<Reg> {
2613     let pattern0_0 = arg0;
2614     let pattern1_0 = arg1;
2615     let pattern2_0 = arg2;
2616     // Rule at src/isa/aarch64/inst.isle line 1714.
2617     let expr0_0 = VecRRRLongOp::Umull32;
2618     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2619     return Some(expr1_0);
2620 }
2621 
2622 // Generated as internal constructor for term asr.
2623 pub fn constructor_asr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2624     let pattern0_0 = arg0;
2625     let pattern1_0 = arg1;
2626     let pattern2_0 = arg2;
2627     // Rule at src/isa/aarch64/inst.isle line 1718.
2628     let expr0_0 = ALUOp::Asr;
2629     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2630     return Some(expr1_0);
2631 }
2632 
2633 // Generated as internal constructor for term asr_imm.
2634 pub fn constructor_asr_imm<C: Context>(
2635     ctx: &mut C,
2636     arg0: Type,
2637     arg1: Reg,
2638     arg2: ImmShift,
2639 ) -> Option<Reg> {
2640     let pattern0_0 = arg0;
2641     let pattern1_0 = arg1;
2642     let pattern2_0 = arg2;
2643     // Rule at src/isa/aarch64/inst.isle line 1721.
2644     let expr0_0 = ALUOp::Asr;
2645     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2646     return Some(expr1_0);
2647 }
2648 
2649 // Generated as internal constructor for term lsr.
2650 pub fn constructor_lsr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2651     let pattern0_0 = arg0;
2652     let pattern1_0 = arg1;
2653     let pattern2_0 = arg2;
2654     // Rule at src/isa/aarch64/inst.isle line 1725.
2655     let expr0_0 = ALUOp::Lsr;
2656     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2657     return Some(expr1_0);
2658 }
2659 
2660 // Generated as internal constructor for term lsr_imm.
2661 pub fn constructor_lsr_imm<C: Context>(
2662     ctx: &mut C,
2663     arg0: Type,
2664     arg1: Reg,
2665     arg2: ImmShift,
2666 ) -> Option<Reg> {
2667     let pattern0_0 = arg0;
2668     let pattern1_0 = arg1;
2669     let pattern2_0 = arg2;
2670     // Rule at src/isa/aarch64/inst.isle line 1728.
2671     let expr0_0 = ALUOp::Lsr;
2672     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2673     return Some(expr1_0);
2674 }
2675 
2676 // Generated as internal constructor for term lsl.
2677 pub fn constructor_lsl<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2678     let pattern0_0 = arg0;
2679     let pattern1_0 = arg1;
2680     let pattern2_0 = arg2;
2681     // Rule at src/isa/aarch64/inst.isle line 1732.
2682     let expr0_0 = ALUOp::Lsl;
2683     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2684     return Some(expr1_0);
2685 }
2686 
2687 // Generated as internal constructor for term lsl_imm.
2688 pub fn constructor_lsl_imm<C: Context>(
2689     ctx: &mut C,
2690     arg0: Type,
2691     arg1: Reg,
2692     arg2: ImmShift,
2693 ) -> Option<Reg> {
2694     let pattern0_0 = arg0;
2695     let pattern1_0 = arg1;
2696     let pattern2_0 = arg2;
2697     // Rule at src/isa/aarch64/inst.isle line 1735.
2698     let expr0_0 = ALUOp::Lsl;
2699     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2700     return Some(expr1_0);
2701 }
2702 
2703 // Generated as internal constructor for term a64_udiv.
2704 pub fn constructor_a64_udiv<C: Context>(
2705     ctx: &mut C,
2706     arg0: Type,
2707     arg1: Reg,
2708     arg2: Reg,
2709 ) -> Option<Reg> {
2710     let pattern0_0 = arg0;
2711     let pattern1_0 = arg1;
2712     let pattern2_0 = arg2;
2713     // Rule at src/isa/aarch64/inst.isle line 1739.
2714     let expr0_0 = ALUOp::UDiv;
2715     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2716     return Some(expr1_0);
2717 }
2718 
2719 // Generated as internal constructor for term a64_sdiv.
2720 pub fn constructor_a64_sdiv<C: Context>(
2721     ctx: &mut C,
2722     arg0: Type,
2723     arg1: Reg,
2724     arg2: Reg,
2725 ) -> Option<Reg> {
2726     let pattern0_0 = arg0;
2727     let pattern1_0 = arg1;
2728     let pattern2_0 = arg2;
2729     // Rule at src/isa/aarch64/inst.isle line 1743.
2730     let expr0_0 = ALUOp::SDiv;
2731     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2732     return Some(expr1_0);
2733 }
2734 
2735 // Generated as internal constructor for term not.
2736 pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2737     let pattern0_0 = arg0;
2738     let pattern1_0 = arg1;
2739     // Rule at src/isa/aarch64/inst.isle line 1747.
2740     let expr0_0 = VecMisc2::Not;
2741     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2742     return Some(expr1_0);
2743 }
2744 
2745 // Generated as internal constructor for term orr_not.
2746 pub fn constructor_orr_not<C: Context>(
2747     ctx: &mut C,
2748     arg0: Type,
2749     arg1: Reg,
2750     arg2: Reg,
2751 ) -> Option<Reg> {
2752     let pattern0_0 = arg0;
2753     let pattern1_0 = arg1;
2754     let pattern2_0 = arg2;
2755     // Rule at src/isa/aarch64/inst.isle line 1752.
2756     let expr0_0 = ALUOp::OrrNot;
2757     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2758     return Some(expr1_0);
2759 }
2760 
2761 // Generated as internal constructor for term orr_not_shift.
2762 pub fn constructor_orr_not_shift<C: Context>(
2763     ctx: &mut C,
2764     arg0: Type,
2765     arg1: Reg,
2766     arg2: Reg,
2767     arg3: ShiftOpAndAmt,
2768 ) -> Option<Reg> {
2769     let pattern0_0 = arg0;
2770     let pattern1_0 = arg1;
2771     let pattern2_0 = arg2;
2772     let pattern3_0 = arg3;
2773     // Rule at src/isa/aarch64/inst.isle line 1755.
2774     let expr0_0 = ALUOp::OrrNot;
2775     let expr1_0 = constructor_alu_rrr_shift(
2776         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2777     )?;
2778     return Some(expr1_0);
2779 }
2780 
2781 // Generated as internal constructor for term orr.
2782 pub fn constructor_orr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2783     let pattern0_0 = arg0;
2784     let pattern1_0 = arg1;
2785     let pattern2_0 = arg2;
2786     // Rule at src/isa/aarch64/inst.isle line 1760.
2787     let expr0_0 = ALUOp::Orr;
2788     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2789     return Some(expr1_0);
2790 }
2791 
2792 // Generated as internal constructor for term orr_imm.
2793 pub fn constructor_orr_imm<C: Context>(
2794     ctx: &mut C,
2795     arg0: Type,
2796     arg1: Reg,
2797     arg2: ImmLogic,
2798 ) -> Option<Reg> {
2799     let pattern0_0 = arg0;
2800     let pattern1_0 = arg1;
2801     let pattern2_0 = arg2;
2802     // Rule at src/isa/aarch64/inst.isle line 1763.
2803     let expr0_0 = ALUOp::Orr;
2804     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2805     return Some(expr1_0);
2806 }
2807 
2808 // Generated as internal constructor for term orr_vec.
2809 pub fn constructor_orr_vec<C: Context>(
2810     ctx: &mut C,
2811     arg0: Reg,
2812     arg1: Reg,
2813     arg2: &VectorSize,
2814 ) -> Option<Reg> {
2815     let pattern0_0 = arg0;
2816     let pattern1_0 = arg1;
2817     let pattern2_0 = arg2;
2818     // Rule at src/isa/aarch64/inst.isle line 1766.
2819     let expr0_0 = VecALUOp::Orr;
2820     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2821     return Some(expr1_0);
2822 }
2823 
2824 // Generated as internal constructor for term and_imm.
2825 pub fn constructor_and_imm<C: Context>(
2826     ctx: &mut C,
2827     arg0: Type,
2828     arg1: Reg,
2829     arg2: ImmLogic,
2830 ) -> Option<Reg> {
2831     let pattern0_0 = arg0;
2832     let pattern1_0 = arg1;
2833     let pattern2_0 = arg2;
2834     // Rule at src/isa/aarch64/inst.isle line 1771.
2835     let expr0_0 = ALUOp::And;
2836     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2837     return Some(expr1_0);
2838 }
2839 
2840 // Generated as internal constructor for term and_vec.
2841 pub fn constructor_and_vec<C: Context>(
2842     ctx: &mut C,
2843     arg0: Reg,
2844     arg1: Reg,
2845     arg2: &VectorSize,
2846 ) -> Option<Reg> {
2847     let pattern0_0 = arg0;
2848     let pattern1_0 = arg1;
2849     let pattern2_0 = arg2;
2850     // Rule at src/isa/aarch64/inst.isle line 1774.
2851     let expr0_0 = VecALUOp::And;
2852     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2853     return Some(expr1_0);
2854 }
2855 
2856 // Generated as internal constructor for term eor_vec.
2857 pub fn constructor_eor_vec<C: Context>(
2858     ctx: &mut C,
2859     arg0: Reg,
2860     arg1: Reg,
2861     arg2: &VectorSize,
2862 ) -> Option<Reg> {
2863     let pattern0_0 = arg0;
2864     let pattern1_0 = arg1;
2865     let pattern2_0 = arg2;
2866     // Rule at src/isa/aarch64/inst.isle line 1778.
2867     let expr0_0 = VecALUOp::Eor;
2868     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2869     return Some(expr1_0);
2870 }
2871 
2872 // Generated as internal constructor for term bic_vec.
2873 pub fn constructor_bic_vec<C: Context>(
2874     ctx: &mut C,
2875     arg0: Reg,
2876     arg1: Reg,
2877     arg2: &VectorSize,
2878 ) -> Option<Reg> {
2879     let pattern0_0 = arg0;
2880     let pattern1_0 = arg1;
2881     let pattern2_0 = arg2;
2882     // Rule at src/isa/aarch64/inst.isle line 1782.
2883     let expr0_0 = VecALUOp::Bic;
2884     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2885     return Some(expr1_0);
2886 }
2887 
2888 // Generated as internal constructor for term sshl.
2889 pub fn constructor_sshl<C: Context>(
2890     ctx: &mut C,
2891     arg0: Reg,
2892     arg1: Reg,
2893     arg2: &VectorSize,
2894 ) -> Option<Reg> {
2895     let pattern0_0 = arg0;
2896     let pattern1_0 = arg1;
2897     let pattern2_0 = arg2;
2898     // Rule at src/isa/aarch64/inst.isle line 1786.
2899     let expr0_0 = VecALUOp::Sshl;
2900     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2901     return Some(expr1_0);
2902 }
2903 
2904 // Generated as internal constructor for term ushl.
2905 pub fn constructor_ushl<C: Context>(
2906     ctx: &mut C,
2907     arg0: Reg,
2908     arg1: Reg,
2909     arg2: &VectorSize,
2910 ) -> Option<Reg> {
2911     let pattern0_0 = arg0;
2912     let pattern1_0 = arg1;
2913     let pattern2_0 = arg2;
2914     // Rule at src/isa/aarch64/inst.isle line 1790.
2915     let expr0_0 = VecALUOp::Ushl;
2916     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2917     return Some(expr1_0);
2918 }
2919 
2920 // Generated as internal constructor for term a64_rotr.
2921 pub fn constructor_a64_rotr<C: Context>(
2922     ctx: &mut C,
2923     arg0: Type,
2924     arg1: Reg,
2925     arg2: Reg,
2926 ) -> Option<Reg> {
2927     let pattern0_0 = arg0;
2928     let pattern1_0 = arg1;
2929     let pattern2_0 = arg2;
2930     // Rule at src/isa/aarch64/inst.isle line 1795.
2931     let expr0_0 = ALUOp::RotR;
2932     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2933     return Some(expr1_0);
2934 }
2935 
2936 // Generated as internal constructor for term a64_rotr_imm.
2937 pub fn constructor_a64_rotr_imm<C: Context>(
2938     ctx: &mut C,
2939     arg0: Type,
2940     arg1: Reg,
2941     arg2: ImmShift,
2942 ) -> Option<Reg> {
2943     let pattern0_0 = arg0;
2944     let pattern1_0 = arg1;
2945     let pattern2_0 = arg2;
2946     // Rule at src/isa/aarch64/inst.isle line 1798.
2947     let expr0_0 = ALUOp::RotR;
2948     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2949     return Some(expr1_0);
2950 }
2951 
2952 // Generated as internal constructor for term rbit.
2953 pub fn constructor_rbit<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2954     let pattern0_0 = arg0;
2955     let pattern1_0 = arg1;
2956     // Rule at src/isa/aarch64/inst.isle line 1803.
2957     let expr0_0 = BitOp::RBit;
2958     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2959     return Some(expr1_0);
2960 }
2961 
2962 // Generated as internal constructor for term a64_clz.
2963 pub fn constructor_a64_clz<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2964     let pattern0_0 = arg0;
2965     let pattern1_0 = arg1;
2966     // Rule at src/isa/aarch64/inst.isle line 1808.
2967     let expr0_0 = BitOp::Clz;
2968     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2969     return Some(expr1_0);
2970 }
2971 
2972 // Generated as internal constructor for term a64_cls.
2973 pub fn constructor_a64_cls<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2974     let pattern0_0 = arg0;
2975     let pattern1_0 = arg1;
2976     // Rule at src/isa/aarch64/inst.isle line 1813.
2977     let expr0_0 = BitOp::Cls;
2978     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2979     return Some(expr1_0);
2980 }
2981 
2982 // Generated as internal constructor for term eon.
2983 pub fn constructor_eon<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2984     let pattern0_0 = arg0;
2985     let pattern1_0 = arg1;
2986     let pattern2_0 = arg2;
2987     // Rule at src/isa/aarch64/inst.isle line 1818.
2988     let expr0_0 = ALUOp::EorNot;
2989     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2990     return Some(expr1_0);
2991 }
2992 
2993 // Generated as internal constructor for term vec_cnt.
2994 pub fn constructor_vec_cnt<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2995     let pattern0_0 = arg0;
2996     let pattern1_0 = arg1;
2997     // Rule at src/isa/aarch64/inst.isle line 1823.
2998     let expr0_0 = VecMisc2::Cnt;
2999     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3000     return Some(expr1_0);
3001 }
3002 
3003 // Generated as internal constructor for term imm.
3004 pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
3005     let pattern0_0 = arg0;
3006     if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) {
3007         let pattern2_0 = arg1;
3008         let closure3 = || {
3009             let expr0_0: Type = I64;
3010             return Some(expr0_0);
3011         };
3012         if let Some(pattern3_0) = closure3() {
3013             if let Some(pattern4_0) = C::imm_logic_from_u64(ctx, pattern2_0, pattern3_0) {
3014                 // Rule at src/isa/aarch64/inst.isle line 1838.
3015                 let expr0_0: Type = I64;
3016                 let expr1_0 = C::zero_reg(ctx);
3017                 let expr2_0 = constructor_orr_imm(ctx, expr0_0, expr1_0, pattern4_0)?;
3018                 return Some(expr2_0);
3019             }
3020         }
3021         if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) {
3022             // Rule at src/isa/aarch64/inst.isle line 1830.
3023             let expr0_0 = OperandSize::Size64;
3024             let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?;
3025             return Some(expr1_0);
3026         }
3027         if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) {
3028             // Rule at src/isa/aarch64/inst.isle line 1834.
3029             let expr0_0 = OperandSize::Size64;
3030             let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?;
3031             return Some(expr1_0);
3032         }
3033         // Rule at src/isa/aarch64/inst.isle line 1845.
3034         let expr0_0 = C::load_constant64_full(ctx, pattern2_0);
3035         return Some(expr0_0);
3036     }
3037     return None;
3038 }
3039 
3040 // Generated as internal constructor for term put_in_reg_sext32.
3041 pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3042     let pattern0_0 = arg0;
3043     let pattern1_0 = C::value_type(ctx, pattern0_0);
3044     if pattern1_0 == I32 {
3045         // Rule at src/isa/aarch64/inst.isle line 1856.
3046         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3047         return Some(expr0_0);
3048     }
3049     if pattern1_0 == I64 {
3050         // Rule at src/isa/aarch64/inst.isle line 1857.
3051         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3052         return Some(expr0_0);
3053     }
3054     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3055         // Rule at src/isa/aarch64/inst.isle line 1852.
3056         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3057         let expr1_0: bool = true;
3058         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3059         let expr3_0: u8 = 32;
3060         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3061         return Some(expr4_0);
3062     }
3063     return None;
3064 }
3065 
3066 // Generated as internal constructor for term put_in_reg_zext32.
3067 pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3068     let pattern0_0 = arg0;
3069     let pattern1_0 = C::value_type(ctx, pattern0_0);
3070     if pattern1_0 == I32 {
3071         // Rule at src/isa/aarch64/inst.isle line 1865.
3072         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3073         return Some(expr0_0);
3074     }
3075     if pattern1_0 == I64 {
3076         // Rule at src/isa/aarch64/inst.isle line 1866.
3077         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3078         return Some(expr0_0);
3079     }
3080     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3081         // Rule at src/isa/aarch64/inst.isle line 1861.
3082         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3083         let expr1_0: bool = false;
3084         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3085         let expr3_0: u8 = 32;
3086         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3087         return Some(expr4_0);
3088     }
3089     return None;
3090 }
3091 
3092 // Generated as internal constructor for term put_in_reg_sext64.
3093 pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3094     let pattern0_0 = arg0;
3095     let pattern1_0 = C::value_type(ctx, pattern0_0);
3096     if pattern1_0 == I64 {
3097         // Rule at src/isa/aarch64/inst.isle line 1874.
3098         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3099         return Some(expr0_0);
3100     }
3101     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3102         // Rule at src/isa/aarch64/inst.isle line 1870.
3103         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3104         let expr1_0: bool = true;
3105         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3106         let expr3_0: u8 = 64;
3107         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3108         return Some(expr4_0);
3109     }
3110     return None;
3111 }
3112 
3113 // Generated as internal constructor for term put_in_reg_zext64.
3114 pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3115     let pattern0_0 = arg0;
3116     let pattern1_0 = C::value_type(ctx, pattern0_0);
3117     if pattern1_0 == I64 {
3118         // Rule at src/isa/aarch64/inst.isle line 1882.
3119         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3120         return Some(expr0_0);
3121     }
3122     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3123         // Rule at src/isa/aarch64/inst.isle line 1878.
3124         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3125         let expr1_0: bool = false;
3126         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3127         let expr3_0: u8 = 64;
3128         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3129         return Some(expr4_0);
3130     }
3131     return None;
3132 }
3133 
3134 // Generated as internal constructor for term trap_if_zero_divisor.
3135 pub fn constructor_trap_if_zero_divisor<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3136     let pattern0_0 = arg0;
3137     // Rule at src/isa/aarch64/inst.isle line 1887.
3138     let expr0_0 = C::cond_br_zero(ctx, pattern0_0);
3139     let expr1_0 = C::trap_code_division_by_zero(ctx);
3140     let expr2_0 = MInst::TrapIf {
3141         kind: expr0_0,
3142         trap_code: expr1_0,
3143     };
3144     let expr3_0 = C::emit(ctx, &expr2_0);
3145     return Some(pattern0_0);
3146 }
3147 
3148 // Generated as internal constructor for term size_from_ty.
3149 pub fn constructor_size_from_ty<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
3150     let pattern0_0 = arg0;
3151     if pattern0_0 == I64 {
3152         // Rule at src/isa/aarch64/inst.isle line 1893.
3153         let expr0_0 = OperandSize::Size64;
3154         return Some(expr0_0);
3155     }
3156     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
3157         // Rule at src/isa/aarch64/inst.isle line 1892.
3158         let expr0_0 = OperandSize::Size32;
3159         return Some(expr0_0);
3160     }
3161     return None;
3162 }
3163 
3164 // Generated as internal constructor for term trap_if_div_overflow.
3165 pub fn constructor_trap_if_div_overflow<C: Context>(
3166     ctx: &mut C,
3167     arg0: Type,
3168     arg1: Reg,
3169     arg2: Reg,
3170 ) -> Option<Reg> {
3171     let pattern0_0 = arg0;
3172     let pattern1_0 = arg1;
3173     let pattern2_0 = arg2;
3174     // Rule at src/isa/aarch64/inst.isle line 1899.
3175     let expr0_0 = ALUOp::AddS;
3176     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
3177     let expr2_0 = C::writable_zero_reg(ctx);
3178     let expr3_0: u8 = 1;
3179     let expr4_0 = C::u8_into_imm12(ctx, expr3_0);
3180     let expr5_0 = MInst::AluRRImm12 {
3181         alu_op: expr0_0,
3182         size: expr1_0,
3183         rd: expr2_0,
3184         rn: pattern2_0,
3185         imm12: expr4_0,
3186     };
3187     let expr6_0 = C::emit(ctx, &expr5_0);
3188     let expr7_0 = constructor_size_from_ty(ctx, pattern0_0)?;
3189     let expr8_0: u8 = 1;
3190     let expr9_0 = C::u8_into_uimm5(ctx, expr8_0);
3191     let expr10_0: bool = false;
3192     let expr11_0: bool = false;
3193     let expr12_0: bool = false;
3194     let expr13_0: bool = false;
3195     let expr14_0 = C::nzcv(ctx, expr10_0, expr11_0, expr12_0, expr13_0);
3196     let expr15_0 = Cond::Eq;
3197     let expr16_0 = MInst::CCmpImm {
3198         size: expr7_0,
3199         rn: pattern1_0,
3200         imm: expr9_0,
3201         nzcv: expr14_0,
3202         cond: expr15_0,
3203     };
3204     let expr17_0 = C::emit(ctx, &expr16_0);
3205     let expr18_0 = Cond::Vs;
3206     let expr19_0 = C::cond_br_cond(ctx, &expr18_0);
3207     let expr20_0 = C::trap_code_integer_overflow(ctx);
3208     let expr21_0 = MInst::TrapIf {
3209         kind: expr19_0,
3210         trap_code: expr20_0,
3211     };
3212     let expr22_0 = C::emit(ctx, &expr21_0);
3213     return Some(pattern1_0);
3214 }
3215 
3216 // Generated as internal constructor for term alu_rs_imm_logic_commutative.
3217 pub fn constructor_alu_rs_imm_logic_commutative<C: Context>(
3218     ctx: &mut C,
3219     arg0: &ALUOp,
3220     arg1: Type,
3221     arg2: Value,
3222     arg3: Value,
3223 ) -> Option<Reg> {
3224     let pattern0_0 = arg0;
3225     let pattern1_0 = arg1;
3226     let pattern2_0 = arg2;
3227     if let Some(pattern3_0) = C::def_inst(ctx, pattern2_0) {
3228         let pattern4_0 = C::inst_data(ctx, pattern3_0);
3229         match &pattern4_0 {
3230             &InstructionData::UnaryImm {
3231                 opcode: ref pattern5_0,
3232                 imm: pattern5_1,
3233             } => {
3234                 if let &Opcode::Iconst = pattern5_0 {
3235                     let closure7 = || {
3236                         return Some(pattern1_0);
3237                     };
3238                     if let Some(pattern7_0) = closure7() {
3239                         if let Some(pattern8_0) =
3240                             C::imm_logic_from_imm64(ctx, pattern5_1, pattern7_0)
3241                         {
3242                             let pattern9_0 = arg3;
3243                             // Rule at src/isa/aarch64/inst.isle line 1944.
3244                             let expr0_0 = C::put_in_reg(ctx, pattern9_0);
3245                             let expr1_0 = constructor_alu_rr_imm_logic(
3246                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0,
3247                             )?;
3248                             return Some(expr1_0);
3249                         }
3250                     }
3251                 }
3252             }
3253             &InstructionData::Binary {
3254                 opcode: ref pattern5_0,
3255                 args: ref pattern5_1,
3256             } => {
3257                 if let &Opcode::Ishl = pattern5_0 {
3258                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3259                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3260                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
3261                         if let &InstructionData::UnaryImm {
3262                             opcode: ref pattern10_0,
3263                             imm: pattern10_1,
3264                         } = &pattern9_0
3265                         {
3266                             if let &Opcode::Iconst = pattern10_0 {
3267                                 let closure12 = || {
3268                                     return Some(pattern1_0);
3269                                 };
3270                                 if let Some(pattern12_0) = closure12() {
3271                                     if let Some(pattern13_0) =
3272                                         C::lshl_from_imm64(ctx, pattern10_1, pattern12_0)
3273                                     {
3274                                         let pattern14_0 = arg3;
3275                                         // Rule at src/isa/aarch64/inst.isle line 1950.
3276                                         let expr0_0 = C::put_in_reg(ctx, pattern14_0);
3277                                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3278                                         let expr2_0 = constructor_alu_rrr_shift(
3279                                             ctx,
3280                                             pattern0_0,
3281                                             pattern1_0,
3282                                             expr0_0,
3283                                             expr1_0,
3284                                             pattern13_0,
3285                                         )?;
3286                                         return Some(expr2_0);
3287                                     }
3288                                 }
3289                             }
3290                         }
3291                     }
3292                 }
3293             }
3294             _ => {}
3295         }
3296     }
3297     let pattern3_0 = arg3;
3298     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3299         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3300         match &pattern5_0 {
3301             &InstructionData::UnaryImm {
3302                 opcode: ref pattern6_0,
3303                 imm: pattern6_1,
3304             } => {
3305                 if let &Opcode::Iconst = pattern6_0 {
3306                     let closure8 = || {
3307                         return Some(pattern1_0);
3308                     };
3309                     if let Some(pattern8_0) = closure8() {
3310                         if let Some(pattern9_0) =
3311                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3312                         {
3313                             // Rule at src/isa/aarch64/inst.isle line 1942.
3314                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3315                             let expr1_0 = constructor_alu_rr_imm_logic(
3316                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3317                             )?;
3318                             return Some(expr1_0);
3319                         }
3320                     }
3321                 }
3322             }
3323             &InstructionData::Binary {
3324                 opcode: ref pattern6_0,
3325                 args: ref pattern6_1,
3326             } => {
3327                 if let &Opcode::Ishl = pattern6_0 {
3328                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3329                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3330                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3331                         if let &InstructionData::UnaryImm {
3332                             opcode: ref pattern11_0,
3333                             imm: pattern11_1,
3334                         } = &pattern10_0
3335                         {
3336                             if let &Opcode::Iconst = pattern11_0 {
3337                                 let closure13 = || {
3338                                     return Some(pattern1_0);
3339                                 };
3340                                 if let Some(pattern13_0) = closure13() {
3341                                     if let Some(pattern14_0) =
3342                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3343                                     {
3344                                         // Rule at src/isa/aarch64/inst.isle line 1948.
3345                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3346                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3347                                         let expr2_0 = constructor_alu_rrr_shift(
3348                                             ctx,
3349                                             pattern0_0,
3350                                             pattern1_0,
3351                                             expr0_0,
3352                                             expr1_0,
3353                                             pattern14_0,
3354                                         )?;
3355                                         return Some(expr2_0);
3356                                     }
3357                                 }
3358                             }
3359                         }
3360                     }
3361                 }
3362             }
3363             _ => {}
3364         }
3365     }
3366     // Rule at src/isa/aarch64/inst.isle line 1938.
3367     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3368     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3369     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3370     return Some(expr2_0);
3371 }
3372 
3373 // Generated as internal constructor for term alu_rs_imm_logic.
3374 pub fn constructor_alu_rs_imm_logic<C: Context>(
3375     ctx: &mut C,
3376     arg0: &ALUOp,
3377     arg1: Type,
3378     arg2: Value,
3379     arg3: Value,
3380 ) -> Option<Reg> {
3381     let pattern0_0 = arg0;
3382     let pattern1_0 = arg1;
3383     let pattern2_0 = arg2;
3384     let pattern3_0 = arg3;
3385     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3386         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3387         match &pattern5_0 {
3388             &InstructionData::UnaryImm {
3389                 opcode: ref pattern6_0,
3390                 imm: pattern6_1,
3391             } => {
3392                 if let &Opcode::Iconst = pattern6_0 {
3393                     let closure8 = || {
3394                         return Some(pattern1_0);
3395                     };
3396                     if let Some(pattern8_0) = closure8() {
3397                         if let Some(pattern9_0) =
3398                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3399                         {
3400                             // Rule at src/isa/aarch64/inst.isle line 1958.
3401                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3402                             let expr1_0 = constructor_alu_rr_imm_logic(
3403                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3404                             )?;
3405                             return Some(expr1_0);
3406                         }
3407                     }
3408                 }
3409             }
3410             &InstructionData::Binary {
3411                 opcode: ref pattern6_0,
3412                 args: ref pattern6_1,
3413             } => {
3414                 if let &Opcode::Ishl = pattern6_0 {
3415                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3416                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3417                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3418                         if let &InstructionData::UnaryImm {
3419                             opcode: ref pattern11_0,
3420                             imm: pattern11_1,
3421                         } = &pattern10_0
3422                         {
3423                             if let &Opcode::Iconst = pattern11_0 {
3424                                 let closure13 = || {
3425                                     return Some(pattern1_0);
3426                                 };
3427                                 if let Some(pattern13_0) = closure13() {
3428                                     if let Some(pattern14_0) =
3429                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3430                                     {
3431                                         // Rule at src/isa/aarch64/inst.isle line 1960.
3432                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3433                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3434                                         let expr2_0 = constructor_alu_rrr_shift(
3435                                             ctx,
3436                                             pattern0_0,
3437                                             pattern1_0,
3438                                             expr0_0,
3439                                             expr1_0,
3440                                             pattern14_0,
3441                                         )?;
3442                                         return Some(expr2_0);
3443                                     }
3444                                 }
3445                             }
3446                         }
3447                     }
3448                 }
3449             }
3450             _ => {}
3451         }
3452     }
3453     // Rule at src/isa/aarch64/inst.isle line 1956.
3454     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3455     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3456     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3457     return Some(expr2_0);
3458 }
3459 
3460 // Generated as internal constructor for term i128_alu_bitop.
3461 pub fn constructor_i128_alu_bitop<C: Context>(
3462     ctx: &mut C,
3463     arg0: &ALUOp,
3464     arg1: Type,
3465     arg2: Value,
3466     arg3: Value,
3467 ) -> Option<ValueRegs> {
3468     let pattern0_0 = arg0;
3469     let pattern1_0 = arg1;
3470     let pattern2_0 = arg2;
3471     let pattern3_0 = arg3;
3472     // Rule at src/isa/aarch64/inst.isle line 1968.
3473     let expr0_0 = C::put_in_regs(ctx, pattern2_0);
3474     let expr1_0: usize = 0;
3475     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3476     let expr3_0: usize = 1;
3477     let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
3478     let expr5_0 = C::put_in_regs(ctx, pattern3_0);
3479     let expr6_0: usize = 0;
3480     let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
3481     let expr8_0: usize = 1;
3482     let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
3483     let expr10_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr2_0, expr7_0)?;
3484     let expr11_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr4_0, expr9_0)?;
3485     let expr12_0 = C::value_regs(ctx, expr10_0, expr11_0);
3486     return Some(expr12_0);
3487 }
3488 
3489 // Generated as internal constructor for term float_cmp_zero.
3490 pub fn constructor_float_cmp_zero<C: Context>(
3491     ctx: &mut C,
3492     arg0: &FloatCC,
3493     arg1: Reg,
3494     arg2: &VectorSize,
3495 ) -> Option<Reg> {
3496     let pattern0_0 = arg0;
3497     let pattern1_0 = arg1;
3498     let pattern2_0 = arg2;
3499     // Rule at src/isa/aarch64/inst.isle line 2008.
3500     let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0);
3501     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3502     return Some(expr1_0);
3503 }
3504 
3505 // Generated as internal constructor for term float_cmp_zero_swap.
3506 pub fn constructor_float_cmp_zero_swap<C: Context>(
3507     ctx: &mut C,
3508     arg0: &FloatCC,
3509     arg1: Reg,
3510     arg2: &VectorSize,
3511 ) -> Option<Reg> {
3512     let pattern0_0 = arg0;
3513     let pattern1_0 = arg1;
3514     let pattern2_0 = arg2;
3515     // Rule at src/isa/aarch64/inst.isle line 2013.
3516     let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0);
3517     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3518     return Some(expr1_0);
3519 }
3520 
3521 // Generated as internal constructor for term fcmeq0.
3522 pub fn constructor_fcmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3523     let pattern0_0 = arg0;
3524     let pattern1_0 = arg1;
3525     // Rule at src/isa/aarch64/inst.isle line 2018.
3526     let expr0_0 = VecMisc2::Fcmeq0;
3527     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3528     return Some(expr1_0);
3529 }
3530 
3531 // Generated as internal constructor for term int_cmp_zero.
3532 pub fn constructor_int_cmp_zero<C: Context>(
3533     ctx: &mut C,
3534     arg0: &IntCC,
3535     arg1: Reg,
3536     arg2: &VectorSize,
3537 ) -> Option<Reg> {
3538     let pattern0_0 = arg0;
3539     let pattern1_0 = arg1;
3540     let pattern2_0 = arg2;
3541     // Rule at src/isa/aarch64/inst.isle line 2044.
3542     let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0);
3543     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3544     return Some(expr1_0);
3545 }
3546 
3547 // Generated as internal constructor for term int_cmp_zero_swap.
3548 pub fn constructor_int_cmp_zero_swap<C: Context>(
3549     ctx: &mut C,
3550     arg0: &IntCC,
3551     arg1: Reg,
3552     arg2: &VectorSize,
3553 ) -> Option<Reg> {
3554     let pattern0_0 = arg0;
3555     let pattern1_0 = arg1;
3556     let pattern2_0 = arg2;
3557     // Rule at src/isa/aarch64/inst.isle line 2049.
3558     let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0);
3559     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3560     return Some(expr1_0);
3561 }
3562 
3563 // Generated as internal constructor for term cmeq0.
3564 pub fn constructor_cmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3565     let pattern0_0 = arg0;
3566     let pattern1_0 = arg1;
3567     // Rule at src/isa/aarch64/inst.isle line 2054.
3568     let expr0_0 = VecMisc2::Cmeq0;
3569     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3570     return Some(expr1_0);
3571 }
3572 
3573 // Generated as internal constructor for term lower.
3574 pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> {
3575     let pattern0_0 = arg0;
3576     if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
3577         let pattern2_0 = C::value_type(ctx, pattern1_0);
3578         if pattern2_0 == I8 {
3579             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3580             if let &InstructionData::Unary {
3581                 opcode: ref pattern5_0,
3582                 arg: pattern5_1,
3583             } = &pattern4_0
3584             {
3585                 match pattern5_0 {
3586                     &Opcode::Bitrev => {
3587                         // Rule at src/isa/aarch64/lower.isle line 980.
3588                         let expr0_0: Type = I32;
3589                         let expr1_0: Type = I32;
3590                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3591                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3592                         let expr4_0: u8 = 24;
3593                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3594                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3595                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3596                         return Some(expr7_0);
3597                     }
3598                     &Opcode::Clz => {
3599                         // Rule at src/isa/aarch64/lower.isle line 1001.
3600                         let expr0_0: Type = I32;
3601                         let expr1_0: Type = I32;
3602                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3603                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3604                         let expr4_0: u8 = 24;
3605                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3606                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3607                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3608                         return Some(expr7_0);
3609                     }
3610                     &Opcode::Cls => {
3611                         // Rule at src/isa/aarch64/lower.isle line 1048.
3612                         let expr0_0: Type = I32;
3613                         let expr1_0: Type = I32;
3614                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3615                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3616                         let expr4_0: u8 = 24;
3617                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3618                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3619                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3620                         return Some(expr7_0);
3621                     }
3622                     &Opcode::Ctz => {
3623                         // Rule at src/isa/aarch64/lower.isle line 1031.
3624                         let expr0_0: Type = I32;
3625                         let expr1_0: Type = I32;
3626                         let expr2_0: Type = I32;
3627                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3628                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3629                         let expr5_0: Type = I32;
3630                         let expr6_0: u64 = 8388608;
3631                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3632                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3633                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3634                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3635                         return Some(expr10_0);
3636                     }
3637                     &Opcode::Popcnt => {
3638                         // Rule at src/isa/aarch64/lower.isle line 1099.
3639                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3640                         let expr1_0 = ScalarSize::Size32;
3641                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3642                         let expr3_0 = VectorSize::Size8x8;
3643                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3644                         let expr5_0: u8 = 0;
3645                         let expr6_0 = VectorSize::Size8x16;
3646                         let expr7_0 = constructor_mov_from_vec(ctx, expr4_0, expr5_0, &expr6_0)?;
3647                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
3648                         return Some(expr8_0);
3649                     }
3650                     _ => {}
3651                 }
3652             }
3653         }
3654         if pattern2_0 == I16 {
3655             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3656             if let &InstructionData::Unary {
3657                 opcode: ref pattern5_0,
3658                 arg: pattern5_1,
3659             } = &pattern4_0
3660             {
3661                 match pattern5_0 {
3662                     &Opcode::Bitrev => {
3663                         // Rule at src/isa/aarch64/lower.isle line 986.
3664                         let expr0_0: Type = I32;
3665                         let expr1_0: Type = I32;
3666                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3667                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3668                         let expr4_0: u8 = 16;
3669                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3670                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3671                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3672                         return Some(expr7_0);
3673                     }
3674                     &Opcode::Clz => {
3675                         // Rule at src/isa/aarch64/lower.isle line 1004.
3676                         let expr0_0: Type = I32;
3677                         let expr1_0: Type = I32;
3678                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3679                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3680                         let expr4_0: u8 = 16;
3681                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3682                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3683                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3684                         return Some(expr7_0);
3685                     }
3686                     &Opcode::Cls => {
3687                         // Rule at src/isa/aarch64/lower.isle line 1051.
3688                         let expr0_0: Type = I32;
3689                         let expr1_0: Type = I32;
3690                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3691                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3692                         let expr4_0: u8 = 16;
3693                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3694                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3695                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3696                         return Some(expr7_0);
3697                     }
3698                     &Opcode::Ctz => {
3699                         // Rule at src/isa/aarch64/lower.isle line 1034.
3700                         let expr0_0: Type = I32;
3701                         let expr1_0: Type = I32;
3702                         let expr2_0: Type = I32;
3703                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3704                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3705                         let expr5_0: Type = I32;
3706                         let expr6_0: u64 = 32768;
3707                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3708                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3709                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3710                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3711                         return Some(expr10_0);
3712                     }
3713                     &Opcode::Popcnt => {
3714                         // Rule at src/isa/aarch64/lower.isle line 1105.
3715                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3716                         let expr1_0 = ScalarSize::Size32;
3717                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3718                         let expr3_0 = VectorSize::Size8x8;
3719                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3720                         let expr5_0 = VectorSize::Size8x8;
3721                         let expr6_0 = constructor_addp(ctx, expr4_0, expr4_0, &expr5_0)?;
3722                         let expr7_0: u8 = 0;
3723                         let expr8_0 = VectorSize::Size8x16;
3724                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3725                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3726                         return Some(expr10_0);
3727                     }
3728                     _ => {}
3729                 }
3730             }
3731         }
3732         if pattern2_0 == I32 {
3733             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3734             match &pattern4_0 {
3735                 &InstructionData::Binary {
3736                     opcode: ref pattern5_0,
3737                     args: ref pattern5_1,
3738                 } => {
3739                     match pattern5_0 {
3740                         &Opcode::Rotl => {
3741                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3742                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3743                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3744                                 if let &InstructionData::UnaryImm {
3745                                     opcode: ref pattern10_0,
3746                                     imm: pattern10_1,
3747                                 } = &pattern9_0
3748                                 {
3749                                     if let &Opcode::Iconst = pattern10_0 {
3750                                         let closure12 = || {
3751                                             let expr0_0: Type = I32;
3752                                             return Some(expr0_0);
3753                                         };
3754                                         if let Some(pattern12_0) = closure12() {
3755                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3756                                                 ctx,
3757                                                 pattern10_1,
3758                                                 pattern12_0,
3759                                             ) {
3760                                                 // Rule at src/isa/aarch64/lower.isle line 871.
3761                                                 let expr0_0: Type = I32;
3762                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3763                                                 let expr2_0: Type = I32;
3764                                                 let expr3_0 =
3765                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3766                                                 let expr4_0 = constructor_a64_rotr_imm(
3767                                                     ctx, expr0_0, expr1_0, expr3_0,
3768                                                 )?;
3769                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3770                                                 return Some(expr5_0);
3771                                             }
3772                                         }
3773                                     }
3774                                 }
3775                             }
3776                             // Rule at src/isa/aarch64/lower.isle line 861.
3777                             let expr0_0: Type = I32;
3778                             let expr1_0 = C::zero_reg(ctx);
3779                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3780                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3781                             let expr4_0: Type = I32;
3782                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3783                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3784                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3785                             return Some(expr7_0);
3786                         }
3787                         &Opcode::Rotr => {
3788                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3789                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3790                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3791                                 if let &InstructionData::UnaryImm {
3792                                     opcode: ref pattern10_0,
3793                                     imm: pattern10_1,
3794                                 } = &pattern9_0
3795                                 {
3796                                     if let &Opcode::Iconst = pattern10_0 {
3797                                         let closure12 = || {
3798                                             let expr0_0: Type = I32;
3799                                             return Some(expr0_0);
3800                                         };
3801                                         if let Some(pattern12_0) = closure12() {
3802                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3803                                                 ctx,
3804                                                 pattern10_1,
3805                                                 pattern12_0,
3806                                             ) {
3807                                                 // Rule at src/isa/aarch64/lower.isle line 913.
3808                                                 let expr0_0: Type = I32;
3809                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3810                                                 let expr2_0 = constructor_a64_rotr_imm(
3811                                                     ctx,
3812                                                     expr0_0,
3813                                                     expr1_0,
3814                                                     pattern13_0,
3815                                                 )?;
3816                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3817                                                 return Some(expr3_0);
3818                                             }
3819                                         }
3820                                     }
3821                                 }
3822                             }
3823                             // Rule at src/isa/aarch64/lower.isle line 901.
3824                             let expr0_0: Type = I32;
3825                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3826                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3827                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
3828                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3829                             return Some(expr4_0);
3830                         }
3831                         _ => {}
3832                     }
3833                 }
3834                 &InstructionData::Unary {
3835                     opcode: ref pattern5_0,
3836                     arg: pattern5_1,
3837                 } => {
3838                     if let &Opcode::Popcnt = pattern5_0 {
3839                         // Rule at src/isa/aarch64/lower.isle line 1111.
3840                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3841                         let expr1_0 = ScalarSize::Size32;
3842                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3843                         let expr3_0 = VectorSize::Size8x8;
3844                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3845                         let expr5_0 = VectorSize::Size8x8;
3846                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
3847                         let expr7_0: u8 = 0;
3848                         let expr8_0 = VectorSize::Size8x16;
3849                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3850                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3851                         return Some(expr10_0);
3852                     }
3853                 }
3854                 _ => {}
3855             }
3856         }
3857         if pattern2_0 == I64 {
3858             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3859             match &pattern4_0 {
3860                 &InstructionData::Binary {
3861                     opcode: ref pattern5_0,
3862                     args: ref pattern5_1,
3863                 } => {
3864                     match pattern5_0 {
3865                         &Opcode::Umulhi => {
3866                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3867                             // Rule at src/isa/aarch64/lower.isle line 371.
3868                             let expr0_0: Type = I64;
3869                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3870                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3871                             let expr3_0 = constructor_umulh(ctx, expr0_0, expr1_0, expr2_0)?;
3872                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3873                             return Some(expr4_0);
3874                         }
3875                         &Opcode::Smulhi => {
3876                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3877                             // Rule at src/isa/aarch64/lower.isle line 359.
3878                             let expr0_0: Type = I64;
3879                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3880                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3881                             let expr3_0 = constructor_smulh(ctx, expr0_0, expr1_0, expr2_0)?;
3882                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3883                             return Some(expr4_0);
3884                         }
3885                         &Opcode::Band => {
3886                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3887                             // Rule at src/isa/aarch64/lower.isle line 592.
3888                             let expr0_0 = ALUOp::And;
3889                             let expr1_0: Type = I64;
3890                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3891                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3892                             )?;
3893                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3894                             return Some(expr3_0);
3895                         }
3896                         &Opcode::Bor => {
3897                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3898                             // Rule at src/isa/aarch64/lower.isle line 605.
3899                             let expr0_0 = ALUOp::Orr;
3900                             let expr1_0: Type = I64;
3901                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3902                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3903                             )?;
3904                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3905                             return Some(expr3_0);
3906                         }
3907                         &Opcode::Bxor => {
3908                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3909                             // Rule at src/isa/aarch64/lower.isle line 618.
3910                             let expr0_0 = ALUOp::Eor;
3911                             let expr1_0: Type = I64;
3912                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3913                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3914                             )?;
3915                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3916                             return Some(expr3_0);
3917                         }
3918                         &Opcode::BandNot => {
3919                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3920                             // Rule at src/isa/aarch64/lower.isle line 631.
3921                             let expr0_0 = ALUOp::AndNot;
3922                             let expr1_0: Type = I64;
3923                             let expr2_0 = constructor_alu_rs_imm_logic(
3924                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3925                             )?;
3926                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3927                             return Some(expr3_0);
3928                         }
3929                         &Opcode::BorNot => {
3930                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3931                             // Rule at src/isa/aarch64/lower.isle line 644.
3932                             let expr0_0 = ALUOp::OrrNot;
3933                             let expr1_0: Type = I64;
3934                             let expr2_0 = constructor_alu_rs_imm_logic(
3935                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3936                             )?;
3937                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3938                             return Some(expr3_0);
3939                         }
3940                         &Opcode::BxorNot => {
3941                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3942                             // Rule at src/isa/aarch64/lower.isle line 654.
3943                             let expr0_0 = ALUOp::EorNot;
3944                             let expr1_0: Type = I64;
3945                             let expr2_0 = constructor_alu_rs_imm_logic(
3946                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3947                             )?;
3948                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3949                             return Some(expr3_0);
3950                         }
3951                         &Opcode::Rotl => {
3952                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3953                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3954                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3955                                 if let &InstructionData::UnaryImm {
3956                                     opcode: ref pattern10_0,
3957                                     imm: pattern10_1,
3958                                 } = &pattern9_0
3959                                 {
3960                                     if let &Opcode::Iconst = pattern10_0 {
3961                                         let closure12 = || {
3962                                             let expr0_0: Type = I64;
3963                                             return Some(expr0_0);
3964                                         };
3965                                         if let Some(pattern12_0) = closure12() {
3966                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3967                                                 ctx,
3968                                                 pattern10_1,
3969                                                 pattern12_0,
3970                                             ) {
3971                                                 // Rule at src/isa/aarch64/lower.isle line 875.
3972                                                 let expr0_0: Type = I64;
3973                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3974                                                 let expr2_0: Type = I64;
3975                                                 let expr3_0 =
3976                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3977                                                 let expr4_0 = constructor_a64_rotr_imm(
3978                                                     ctx, expr0_0, expr1_0, expr3_0,
3979                                                 )?;
3980                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3981                                                 return Some(expr5_0);
3982                                             }
3983                                         }
3984                                     }
3985                                 }
3986                             }
3987                             // Rule at src/isa/aarch64/lower.isle line 866.
3988                             let expr0_0: Type = I64;
3989                             let expr1_0 = C::zero_reg(ctx);
3990                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3991                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3992                             let expr4_0: Type = I64;
3993                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3994                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3995                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3996                             return Some(expr7_0);
3997                         }
3998                         &Opcode::Rotr => {
3999                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4000                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
4001                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
4002                                 if let &InstructionData::UnaryImm {
4003                                     opcode: ref pattern10_0,
4004                                     imm: pattern10_1,
4005                                 } = &pattern9_0
4006                                 {
4007                                     if let &Opcode::Iconst = pattern10_0 {
4008                                         let closure12 = || {
4009                                             let expr0_0: Type = I64;
4010                                             return Some(expr0_0);
4011                                         };
4012                                         if let Some(pattern12_0) = closure12() {
4013                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4014                                                 ctx,
4015                                                 pattern10_1,
4016                                                 pattern12_0,
4017                                             ) {
4018                                                 // Rule at src/isa/aarch64/lower.isle line 917.
4019                                                 let expr0_0: Type = I64;
4020                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4021                                                 let expr2_0 = constructor_a64_rotr_imm(
4022                                                     ctx,
4023                                                     expr0_0,
4024                                                     expr1_0,
4025                                                     pattern13_0,
4026                                                 )?;
4027                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4028                                                 return Some(expr3_0);
4029                                             }
4030                                         }
4031                                     }
4032                                 }
4033                             }
4034                             // Rule at src/isa/aarch64/lower.isle line 905.
4035                             let expr0_0: Type = I64;
4036                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4037                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4038                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
4039                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4040                             return Some(expr4_0);
4041                         }
4042                         &Opcode::Ishl => {
4043                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4044                             // Rule at src/isa/aarch64/lower.isle line 666.
4045                             let expr0_0 = ALUOp::Lsl;
4046                             let expr1_0: Type = I64;
4047                             let expr2_0 = C::put_in_reg(ctx, pattern7_0);
4048                             let expr3_0 =
4049                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4050                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4051                             return Some(expr4_0);
4052                         }
4053                         &Opcode::Ushr => {
4054                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4055                             // Rule at src/isa/aarch64/lower.isle line 750.
4056                             let expr0_0 = ALUOp::Lsr;
4057                             let expr1_0: Type = I64;
4058                             let expr2_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
4059                             let expr3_0 =
4060                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4061                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4062                             return Some(expr4_0);
4063                         }
4064                         &Opcode::Sshr => {
4065                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4066                             // Rule at src/isa/aarch64/lower.isle line 797.
4067                             let expr0_0 = ALUOp::Asr;
4068                             let expr1_0: Type = I64;
4069                             let expr2_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
4070                             let expr3_0 =
4071                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4072                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4073                             return Some(expr4_0);
4074                         }
4075                         _ => {}
4076                     }
4077                 }
4078                 &InstructionData::Unary {
4079                     opcode: ref pattern5_0,
4080                     arg: pattern5_1,
4081                 } => {
4082                     if let &Opcode::Popcnt = pattern5_0 {
4083                         // Rule at src/isa/aarch64/lower.isle line 1117.
4084                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4085                         let expr1_0 = ScalarSize::Size64;
4086                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
4087                         let expr3_0 = VectorSize::Size8x8;
4088                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
4089                         let expr5_0 = VectorSize::Size8x8;
4090                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
4091                         let expr7_0: u8 = 0;
4092                         let expr8_0 = VectorSize::Size8x16;
4093                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
4094                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
4095                         return Some(expr10_0);
4096                     }
4097                 }
4098                 _ => {}
4099             }
4100         }
4101         if pattern2_0 == I128 {
4102             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4103             match &pattern4_0 {
4104                 &InstructionData::Binary {
4105                     opcode: ref pattern5_0,
4106                     args: ref pattern5_1,
4107                 } => {
4108                     match pattern5_0 {
4109                         &Opcode::Iadd => {
4110                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4111                             // Rule at src/isa/aarch64/lower.isle line 83.
4112                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4113                             let expr1_0: usize = 0;
4114                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4115                             let expr3_0: usize = 1;
4116                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4117                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4118                             let expr6_0: usize = 0;
4119                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4120                             let expr8_0: usize = 1;
4121                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4122                             let expr10_0: Type = I64;
4123                             let expr11_0 =
4124                                 constructor_add_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4125                             let expr12_0: Type = I64;
4126                             let expr13_0 = constructor_adc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4127                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4128                             let expr15_0 = C::output(ctx, expr14_0);
4129                             return Some(expr15_0);
4130                         }
4131                         &Opcode::Isub => {
4132                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4133                             // Rule at src/isa/aarch64/lower.isle line 133.
4134                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4135                             let expr1_0: usize = 0;
4136                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4137                             let expr3_0: usize = 1;
4138                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4139                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4140                             let expr6_0: usize = 0;
4141                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4142                             let expr8_0: usize = 1;
4143                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4144                             let expr10_0: Type = I64;
4145                             let expr11_0 =
4146                                 constructor_sub_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4147                             let expr12_0: Type = I64;
4148                             let expr13_0 = constructor_sbc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4149                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4150                             let expr15_0 = C::output(ctx, expr14_0);
4151                             return Some(expr15_0);
4152                         }
4153                         &Opcode::Imul => {
4154                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4155                             // Rule at src/isa/aarch64/lower.isle line 187.
4156                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4157                             let expr1_0: usize = 0;
4158                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4159                             let expr3_0: usize = 1;
4160                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4161                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4162                             let expr6_0: usize = 0;
4163                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4164                             let expr8_0: usize = 1;
4165                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4166                             let expr10_0: Type = I64;
4167                             let expr11_0 = constructor_umulh(ctx, expr10_0, expr2_0, expr7_0)?;
4168                             let expr12_0: Type = I64;
4169                             let expr13_0 =
4170                                 constructor_madd(ctx, expr12_0, expr2_0, expr9_0, expr11_0)?;
4171                             let expr14_0: Type = I64;
4172                             let expr15_0 =
4173                                 constructor_madd(ctx, expr14_0, expr4_0, expr7_0, expr13_0)?;
4174                             let expr16_0: Type = I64;
4175                             let expr17_0 = C::zero_reg(ctx);
4176                             let expr18_0 =
4177                                 constructor_madd(ctx, expr16_0, expr2_0, expr7_0, expr17_0)?;
4178                             let expr19_0 = C::value_regs(ctx, expr18_0, expr15_0);
4179                             let expr20_0 = C::output(ctx, expr19_0);
4180                             return Some(expr20_0);
4181                         }
4182                         &Opcode::Band => {
4183                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4184                             // Rule at src/isa/aarch64/lower.isle line 595.
4185                             let expr0_0 = ALUOp::And;
4186                             let expr1_0: Type = I64;
4187                             let expr2_0 = constructor_i128_alu_bitop(
4188                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4189                             )?;
4190                             let expr3_0 = C::output(ctx, expr2_0);
4191                             return Some(expr3_0);
4192                         }
4193                         &Opcode::Bor => {
4194                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4195                             // Rule at src/isa/aarch64/lower.isle line 608.
4196                             let expr0_0 = ALUOp::Orr;
4197                             let expr1_0: Type = I64;
4198                             let expr2_0 = constructor_i128_alu_bitop(
4199                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4200                             )?;
4201                             let expr3_0 = C::output(ctx, expr2_0);
4202                             return Some(expr3_0);
4203                         }
4204                         &Opcode::Bxor => {
4205                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4206                             // Rule at src/isa/aarch64/lower.isle line 621.
4207                             let expr0_0 = ALUOp::Eor;
4208                             let expr1_0: Type = I64;
4209                             let expr2_0 = constructor_i128_alu_bitop(
4210                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4211                             )?;
4212                             let expr3_0 = C::output(ctx, expr2_0);
4213                             return Some(expr3_0);
4214                         }
4215                         &Opcode::BandNot => {
4216                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4217                             // Rule at src/isa/aarch64/lower.isle line 634.
4218                             let expr0_0 = ALUOp::AndNot;
4219                             let expr1_0: Type = I64;
4220                             let expr2_0 = constructor_i128_alu_bitop(
4221                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4222                             )?;
4223                             let expr3_0 = C::output(ctx, expr2_0);
4224                             return Some(expr3_0);
4225                         }
4226                         &Opcode::BorNot => {
4227                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4228                             // Rule at src/isa/aarch64/lower.isle line 647.
4229                             let expr0_0 = ALUOp::OrrNot;
4230                             let expr1_0: Type = I64;
4231                             let expr2_0 = constructor_i128_alu_bitop(
4232                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4233                             )?;
4234                             let expr3_0 = C::output(ctx, expr2_0);
4235                             return Some(expr3_0);
4236                         }
4237                         &Opcode::BxorNot => {
4238                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4239                             // Rule at src/isa/aarch64/lower.isle line 657.
4240                             let expr0_0 = ALUOp::EorNot;
4241                             let expr1_0: Type = I64;
4242                             let expr2_0 = constructor_i128_alu_bitop(
4243                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4244                             )?;
4245                             let expr3_0 = C::output(ctx, expr2_0);
4246                             return Some(expr3_0);
4247                         }
4248                         &Opcode::Rotl => {
4249                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4250                             // Rule at src/isa/aarch64/lower.isle line 884.
4251                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4252                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4253                             let expr2_0: usize = 0;
4254                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4255                             let expr4_0: Type = I64;
4256                             let expr5_0: Type = I64;
4257                             let expr6_0: u64 = 128;
4258                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4259                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4260                             let expr9_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4261                             let expr10_0 = constructor_lower_ushr128(ctx, expr0_0, expr8_0)?;
4262                             let expr11_0: Type = I64;
4263                             let expr12_0: usize = 0;
4264                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4265                             let expr14_0: usize = 0;
4266                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4267                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4268                             let expr17_0: Type = I64;
4269                             let expr18_0: usize = 1;
4270                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4271                             let expr20_0: usize = 1;
4272                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4273                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4274                             let expr23_0 = C::value_regs(ctx, expr16_0, expr22_0);
4275                             let expr24_0 = C::output(ctx, expr23_0);
4276                             return Some(expr24_0);
4277                         }
4278                         &Opcode::Rotr => {
4279                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4280                             // Rule at src/isa/aarch64/lower.isle line 965.
4281                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4282                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4283                             let expr2_0: usize = 0;
4284                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4285                             let expr4_0: Type = I64;
4286                             let expr5_0: Type = I64;
4287                             let expr6_0: u64 = 128;
4288                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4289                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4290                             let expr9_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4291                             let expr10_0 = constructor_lower_shl128(ctx, expr0_0, expr8_0)?;
4292                             let expr11_0: Type = I64;
4293                             let expr12_0: usize = 1;
4294                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4295                             let expr14_0: usize = 1;
4296                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4297                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4298                             let expr17_0: Type = I64;
4299                             let expr18_0: usize = 0;
4300                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4301                             let expr20_0: usize = 0;
4302                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4303                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4304                             let expr23_0 = C::value_regs(ctx, expr22_0, expr16_0);
4305                             let expr24_0 = C::output(ctx, expr23_0);
4306                             return Some(expr24_0);
4307                         }
4308                         &Opcode::Ishl => {
4309                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4310                             // Rule at src/isa/aarch64/lower.isle line 670.
4311                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4312                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4313                             let expr2_0: usize = 0;
4314                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4315                             let expr4_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4316                             let expr5_0 = C::output(ctx, expr4_0);
4317                             return Some(expr5_0);
4318                         }
4319                         &Opcode::Ushr => {
4320                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4321                             // Rule at src/isa/aarch64/lower.isle line 754.
4322                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4323                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4324                             let expr2_0: usize = 0;
4325                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4326                             let expr4_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4327                             let expr5_0 = C::output(ctx, expr4_0);
4328                             return Some(expr5_0);
4329                         }
4330                         &Opcode::Sshr => {
4331                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4332                             // Rule at src/isa/aarch64/lower.isle line 801.
4333                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4334                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4335                             let expr2_0: usize = 0;
4336                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4337                             let expr4_0 = constructor_lower_sshr128(ctx, expr0_0, expr3_0)?;
4338                             let expr5_0 = C::output(ctx, expr4_0);
4339                             return Some(expr5_0);
4340                         }
4341                         _ => {}
4342                     }
4343                 }
4344                 &InstructionData::Unary {
4345                     opcode: ref pattern5_0,
4346                     arg: pattern5_1,
4347                 } => {
4348                     match pattern5_0 {
4349                         &Opcode::Bnot => {
4350                             // Rule at src/isa/aarch64/lower.isle line 575.
4351                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4352                             let expr1_0: usize = 0;
4353                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4354                             let expr3_0: usize = 1;
4355                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4356                             let expr5_0: Type = I64;
4357                             let expr6_0 = C::zero_reg(ctx);
4358                             let expr7_0 = constructor_orr_not(ctx, expr5_0, expr6_0, expr2_0)?;
4359                             let expr8_0: Type = I64;
4360                             let expr9_0 = C::zero_reg(ctx);
4361                             let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, expr4_0)?;
4362                             let expr11_0 = C::value_regs(ctx, expr7_0, expr10_0);
4363                             let expr12_0 = C::output(ctx, expr11_0);
4364                             return Some(expr12_0);
4365                         }
4366                         &Opcode::Bitrev => {
4367                             // Rule at src/isa/aarch64/lower.isle line 989.
4368                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4369                             let expr1_0: Type = I64;
4370                             let expr2_0: usize = 0;
4371                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4372                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4373                             let expr5_0: Type = I64;
4374                             let expr6_0: usize = 1;
4375                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4376                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4377                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4378                             let expr10_0 = C::output(ctx, expr9_0);
4379                             return Some(expr10_0);
4380                         }
4381                         &Opcode::Clz => {
4382                             // Rule at src/isa/aarch64/lower.isle line 1007.
4383                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4384                             let expr1_0 = constructor_lower_clz128(ctx, expr0_0)?;
4385                             let expr2_0 = C::output(ctx, expr1_0);
4386                             return Some(expr2_0);
4387                         }
4388                         &Opcode::Cls => {
4389                             // Rule at src/isa/aarch64/lower.isle line 1063.
4390                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4391                             let expr1_0: usize = 0;
4392                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4393                             let expr3_0: usize = 1;
4394                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4395                             let expr5_0: Type = I64;
4396                             let expr6_0 = constructor_a64_cls(ctx, expr5_0, expr2_0)?;
4397                             let expr7_0: Type = I64;
4398                             let expr8_0 = constructor_a64_cls(ctx, expr7_0, expr4_0)?;
4399                             let expr9_0: Type = I64;
4400                             let expr10_0 = constructor_eon(ctx, expr9_0, expr4_0, expr2_0)?;
4401                             let expr11_0: Type = I64;
4402                             let expr12_0: u8 = 63;
4403                             let expr13_0 = C::imm_shift_from_u8(ctx, expr12_0);
4404                             let expr14_0 = constructor_lsr_imm(ctx, expr11_0, expr10_0, expr13_0)?;
4405                             let expr15_0: Type = I64;
4406                             let expr16_0 =
4407                                 constructor_madd(ctx, expr15_0, expr6_0, expr14_0, expr14_0)?;
4408                             let expr17_0: u8 = 63;
4409                             let expr18_0 = C::u8_into_imm12(ctx, expr17_0);
4410                             let expr19_0 = constructor_cmp64_imm(ctx, expr8_0, expr18_0)?;
4411                             let expr20_0 = Cond::Eq;
4412                             let expr21_0 = C::zero_reg(ctx);
4413                             let expr22_0 = constructor_csel(ctx, &expr20_0, expr16_0, expr21_0)?;
4414                             let expr23_0 = constructor_with_flags_reg(ctx, &expr19_0, &expr22_0)?;
4415                             let expr24_0: Type = I64;
4416                             let expr25_0 = constructor_add(ctx, expr24_0, expr23_0, expr8_0)?;
4417                             let expr26_0: Type = I64;
4418                             let expr27_0: u64 = 0;
4419                             let expr28_0 = constructor_imm(ctx, expr26_0, expr27_0)?;
4420                             let expr29_0 = C::value_regs(ctx, expr25_0, expr28_0);
4421                             let expr30_0 = C::output(ctx, expr29_0);
4422                             return Some(expr30_0);
4423                         }
4424                         &Opcode::Ctz => {
4425                             // Rule at src/isa/aarch64/lower.isle line 1037.
4426                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4427                             let expr1_0: Type = I64;
4428                             let expr2_0: usize = 0;
4429                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4430                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4431                             let expr5_0: Type = I64;
4432                             let expr6_0: usize = 1;
4433                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4434                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4435                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4436                             let expr10_0 = constructor_lower_clz128(ctx, expr9_0)?;
4437                             let expr11_0 = C::output(ctx, expr10_0);
4438                             return Some(expr11_0);
4439                         }
4440                         &Opcode::Popcnt => {
4441                             // Rule at src/isa/aarch64/lower.isle line 1123.
4442                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4443                             let expr1_0: usize = 0;
4444                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4445                             let expr3_0 = ScalarSize::Size64;
4446                             let expr4_0 = constructor_mov_to_fpu(ctx, expr2_0, &expr3_0)?;
4447                             let expr5_0: usize = 1;
4448                             let expr6_0 = C::value_regs_get(ctx, expr0_0, expr5_0);
4449                             let expr7_0: u8 = 1;
4450                             let expr8_0 = VectorSize::Size64x2;
4451                             let expr9_0 =
4452                                 constructor_mov_to_vec(ctx, expr4_0, expr6_0, expr7_0, &expr8_0)?;
4453                             let expr10_0 = VectorSize::Size8x16;
4454                             let expr11_0 = constructor_vec_cnt(ctx, expr9_0, &expr10_0)?;
4455                             let expr12_0 = VectorSize::Size8x16;
4456                             let expr13_0 = constructor_addv(ctx, expr11_0, &expr12_0)?;
4457                             let expr14_0: u8 = 0;
4458                             let expr15_0 = VectorSize::Size8x16;
4459                             let expr16_0 =
4460                                 constructor_mov_from_vec(ctx, expr13_0, expr14_0, &expr15_0)?;
4461                             let expr17_0: Type = I64;
4462                             let expr18_0: u64 = 0;
4463                             let expr19_0 = constructor_imm(ctx, expr17_0, expr18_0)?;
4464                             let expr20_0 = C::value_regs(ctx, expr16_0, expr19_0);
4465                             let expr21_0 = C::output(ctx, expr20_0);
4466                             return Some(expr21_0);
4467                         }
4468                         &Opcode::Uextend => {
4469                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4470                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4471                                 if let &InstructionData::BinaryImm8 {
4472                                     opcode: ref pattern9_0,
4473                                     arg: pattern9_1,
4474                                     imm: pattern9_2,
4475                                 } = &pattern8_0
4476                                 {
4477                                     if let &Opcode::Extractlane = pattern9_0 {
4478                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4479                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
4480                                         // Rule at src/isa/aarch64/lower.isle line 505.
4481                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4482                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
4483                                         let expr2_0 = constructor_mov_from_vec(
4484                                             ctx,
4485                                             expr0_0,
4486                                             pattern12_0,
4487                                             &expr1_0,
4488                                         )?;
4489                                         let expr3_0: Type = I64;
4490                                         let expr4_0: u64 = 0;
4491                                         let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
4492                                         let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
4493                                         let expr7_0 = C::output(ctx, expr6_0);
4494                                         return Some(expr7_0);
4495                                     }
4496                                 }
4497                             }
4498                             // Rule at src/isa/aarch64/lower.isle line 500.
4499                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
4500                             let expr1_0: Type = I64;
4501                             let expr2_0: u64 = 0;
4502                             let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
4503                             let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
4504                             let expr5_0 = C::output(ctx, expr4_0);
4505                             return Some(expr5_0);
4506                         }
4507                         &Opcode::Sextend => {
4508                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4509                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4510                                 if let &InstructionData::BinaryImm8 {
4511                                     opcode: ref pattern9_0,
4512                                     arg: pattern9_1,
4513                                     imm: pattern9_2,
4514                                 } = &pattern8_0
4515                                 {
4516                                     if let &Opcode::Extractlane = pattern9_0 {
4517                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4518                                         if pattern11_0 == I64X2 {
4519                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4520                                             // Rule at src/isa/aarch64/lower.isle line 549.
4521                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4522                                             let expr1_0 = VectorSize::Size64x2;
4523                                             let expr2_0 = constructor_mov_from_vec(
4524                                                 ctx,
4525                                                 expr0_0,
4526                                                 pattern13_0,
4527                                                 &expr1_0,
4528                                             )?;
4529                                             let expr3_0: Type = I64;
4530                                             let expr4_0: u8 = 63;
4531                                             let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
4532                                             let expr6_0 = constructor_asr_imm(
4533                                                 ctx, expr3_0, expr2_0, expr5_0,
4534                                             )?;
4535                                             let expr7_0 = C::value_regs(ctx, expr2_0, expr6_0);
4536                                             let expr8_0 = C::output(ctx, expr7_0);
4537                                             return Some(expr8_0);
4538                                         }
4539                                         if let Some(()) = C::not_i64x2(ctx, pattern11_0) {
4540                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4541                                             // Rule at src/isa/aarch64/lower.isle line 538.
4542                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4543                                             let expr1_0 =
4544                                                 constructor_vector_size(ctx, pattern11_0)?;
4545                                             let expr2_0: Type = I64;
4546                                             let expr3_0 = constructor_size_from_ty(ctx, expr2_0)?;
4547                                             let expr4_0 = constructor_mov_from_vec_signed(
4548                                                 ctx,
4549                                                 expr0_0,
4550                                                 pattern13_0,
4551                                                 &expr1_0,
4552                                                 &expr3_0,
4553                                             )?;
4554                                             let expr5_0: Type = I64;
4555                                             let expr6_0: u8 = 63;
4556                                             let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
4557                                             let expr8_0 = constructor_asr_imm(
4558                                                 ctx, expr5_0, expr4_0, expr7_0,
4559                                             )?;
4560                                             let expr9_0 = C::value_regs(ctx, expr4_0, expr8_0);
4561                                             let expr10_0 = C::output(ctx, expr9_0);
4562                                             return Some(expr10_0);
4563                                         }
4564                                     }
4565                                 }
4566                             }
4567                             // Rule at src/isa/aarch64/lower.isle line 528.
4568                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
4569                             let expr1_0: Type = I64;
4570                             let expr2_0: u8 = 63;
4571                             let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0);
4572                             let expr4_0 = constructor_asr_imm(ctx, expr1_0, expr0_0, expr3_0)?;
4573                             let expr5_0 = C::value_regs(ctx, expr0_0, expr4_0);
4574                             let expr6_0 = C::output(ctx, expr5_0);
4575                             return Some(expr6_0);
4576                         }
4577                         _ => {}
4578                     }
4579                 }
4580                 _ => {}
4581             }
4582         }
4583         if pattern2_0 == I8X16 {
4584             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4585             if let &InstructionData::Unary {
4586                 opcode: ref pattern5_0,
4587                 arg: pattern5_1,
4588             } = &pattern4_0
4589             {
4590                 if let &Opcode::Popcnt = pattern5_0 {
4591                     // Rule at src/isa/aarch64/lower.isle line 1131.
4592                     let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4593                     let expr1_0 = VectorSize::Size8x16;
4594                     let expr2_0 = constructor_vec_cnt(ctx, expr0_0, &expr1_0)?;
4595                     let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4596                     return Some(expr3_0);
4597                 }
4598             }
4599         }
4600         if pattern2_0 == I16X8 {
4601             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4602             if let &InstructionData::Binary {
4603                 opcode: ref pattern5_0,
4604                 args: ref pattern5_1,
4605             } = &pattern4_0
4606             {
4607                 if let &Opcode::Imul = pattern5_0 {
4608                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4609                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4610                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4611                         if let &InstructionData::Unary {
4612                             opcode: ref pattern10_0,
4613                             arg: pattern10_1,
4614                         } = &pattern9_0
4615                         {
4616                             match pattern10_0 {
4617                                 &Opcode::SwidenLow => {
4618                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4619                                     if pattern12_0 == I8X16 {
4620                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4621                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4622                                             if let &InstructionData::Unary {
4623                                                 opcode: ref pattern16_0,
4624                                                 arg: pattern16_1,
4625                                             } = &pattern15_0
4626                                             {
4627                                                 if let &Opcode::SwidenLow = pattern16_0 {
4628                                                     let pattern18_0 =
4629                                                         C::value_type(ctx, pattern16_1);
4630                                                     if pattern18_0 == I8X16 {
4631                                                         // Rule at src/isa/aarch64/lower.isle line 286.
4632                                                         let expr0_0 =
4633                                                             C::put_in_reg(ctx, pattern10_1);
4634                                                         let expr1_0 =
4635                                                             C::put_in_reg(ctx, pattern16_1);
4636                                                         let expr2_0: bool = false;
4637                                                         let expr3_0 = constructor_smull8(
4638                                                             ctx, expr0_0, expr1_0, expr2_0,
4639                                                         )?;
4640                                                         let expr4_0 =
4641                                                             constructor_output_reg(ctx, expr3_0)?;
4642                                                         return Some(expr4_0);
4643                                                     }
4644                                                 }
4645                                             }
4646                                         }
4647                                     }
4648                                 }
4649                                 &Opcode::SwidenHigh => {
4650                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4651                                     if pattern12_0 == I8X16 {
4652                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4653                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4654                                             if let &InstructionData::Unary {
4655                                                 opcode: ref pattern16_0,
4656                                                 arg: pattern16_1,
4657                                             } = &pattern15_0
4658                                             {
4659                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4660                                                     let pattern18_0 =
4661                                                         C::value_type(ctx, pattern16_1);
4662                                                     if pattern18_0 == I8X16 {
4663                                                         // Rule at src/isa/aarch64/lower.isle line 292.
4664                                                         let expr0_0 =
4665                                                             C::put_in_reg(ctx, pattern10_1);
4666                                                         let expr1_0 =
4667                                                             C::put_in_reg(ctx, pattern16_1);
4668                                                         let expr2_0: bool = true;
4669                                                         let expr3_0 = constructor_smull8(
4670                                                             ctx, expr0_0, expr1_0, expr2_0,
4671                                                         )?;
4672                                                         let expr4_0 =
4673                                                             constructor_output_reg(ctx, expr3_0)?;
4674                                                         return Some(expr4_0);
4675                                                     }
4676                                                 }
4677                                             }
4678                                         }
4679                                     }
4680                                 }
4681                                 &Opcode::UwidenLow => {
4682                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4683                                     if pattern12_0 == I8X16 {
4684                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4685                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4686                                             if let &InstructionData::Unary {
4687                                                 opcode: ref pattern16_0,
4688                                                 arg: pattern16_1,
4689                                             } = &pattern15_0
4690                                             {
4691                                                 if let &Opcode::UwidenLow = pattern16_0 {
4692                                                     let pattern18_0 =
4693                                                         C::value_type(ctx, pattern16_1);
4694                                                     if pattern18_0 == I8X16 {
4695                                                         // Rule at src/isa/aarch64/lower.isle line 298.
4696                                                         let expr0_0 =
4697                                                             C::put_in_reg(ctx, pattern10_1);
4698                                                         let expr1_0 =
4699                                                             C::put_in_reg(ctx, pattern16_1);
4700                                                         let expr2_0: bool = false;
4701                                                         let expr3_0 = constructor_umull8(
4702                                                             ctx, expr0_0, expr1_0, expr2_0,
4703                                                         )?;
4704                                                         let expr4_0 =
4705                                                             constructor_output_reg(ctx, expr3_0)?;
4706                                                         return Some(expr4_0);
4707                                                     }
4708                                                 }
4709                                             }
4710                                         }
4711                                     }
4712                                 }
4713                                 &Opcode::UwidenHigh => {
4714                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4715                                     if pattern12_0 == I8X16 {
4716                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4717                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4718                                             if let &InstructionData::Unary {
4719                                                 opcode: ref pattern16_0,
4720                                                 arg: pattern16_1,
4721                                             } = &pattern15_0
4722                                             {
4723                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4724                                                     let pattern18_0 =
4725                                                         C::value_type(ctx, pattern16_1);
4726                                                     if pattern18_0 == I8X16 {
4727                                                         // Rule at src/isa/aarch64/lower.isle line 304.
4728                                                         let expr0_0 =
4729                                                             C::put_in_reg(ctx, pattern10_1);
4730                                                         let expr1_0 =
4731                                                             C::put_in_reg(ctx, pattern16_1);
4732                                                         let expr2_0: bool = true;
4733                                                         let expr3_0 = constructor_umull8(
4734                                                             ctx, expr0_0, expr1_0, expr2_0,
4735                                                         )?;
4736                                                         let expr4_0 =
4737                                                             constructor_output_reg(ctx, expr3_0)?;
4738                                                         return Some(expr4_0);
4739                                                     }
4740                                                 }
4741                                             }
4742                                         }
4743                                     }
4744                                 }
4745                                 _ => {}
4746                             }
4747                         }
4748                     }
4749                 }
4750             }
4751         }
4752         if pattern2_0 == I32X4 {
4753             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4754             if let &InstructionData::Binary {
4755                 opcode: ref pattern5_0,
4756                 args: ref pattern5_1,
4757             } = &pattern4_0
4758             {
4759                 if let &Opcode::Imul = pattern5_0 {
4760                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4761                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4762                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4763                         if let &InstructionData::Unary {
4764                             opcode: ref pattern10_0,
4765                             arg: pattern10_1,
4766                         } = &pattern9_0
4767                         {
4768                             match pattern10_0 {
4769                                 &Opcode::SwidenLow => {
4770                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4771                                     if pattern12_0 == I16X8 {
4772                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4773                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4774                                             if let &InstructionData::Unary {
4775                                                 opcode: ref pattern16_0,
4776                                                 arg: pattern16_1,
4777                                             } = &pattern15_0
4778                                             {
4779                                                 if let &Opcode::SwidenLow = pattern16_0 {
4780                                                     let pattern18_0 =
4781                                                         C::value_type(ctx, pattern16_1);
4782                                                     if pattern18_0 == I16X8 {
4783                                                         // Rule at src/isa/aarch64/lower.isle line 310.
4784                                                         let expr0_0 =
4785                                                             C::put_in_reg(ctx, pattern10_1);
4786                                                         let expr1_0 =
4787                                                             C::put_in_reg(ctx, pattern16_1);
4788                                                         let expr2_0: bool = false;
4789                                                         let expr3_0 = constructor_smull16(
4790                                                             ctx, expr0_0, expr1_0, expr2_0,
4791                                                         )?;
4792                                                         let expr4_0 =
4793                                                             constructor_output_reg(ctx, expr3_0)?;
4794                                                         return Some(expr4_0);
4795                                                     }
4796                                                 }
4797                                             }
4798                                         }
4799                                     }
4800                                 }
4801                                 &Opcode::SwidenHigh => {
4802                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4803                                     if pattern12_0 == I16X8 {
4804                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4805                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4806                                             if let &InstructionData::Unary {
4807                                                 opcode: ref pattern16_0,
4808                                                 arg: pattern16_1,
4809                                             } = &pattern15_0
4810                                             {
4811                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4812                                                     let pattern18_0 =
4813                                                         C::value_type(ctx, pattern16_1);
4814                                                     if pattern18_0 == I16X8 {
4815                                                         // Rule at src/isa/aarch64/lower.isle line 316.
4816                                                         let expr0_0 =
4817                                                             C::put_in_reg(ctx, pattern10_1);
4818                                                         let expr1_0 =
4819                                                             C::put_in_reg(ctx, pattern16_1);
4820                                                         let expr2_0: bool = true;
4821                                                         let expr3_0 = constructor_smull16(
4822                                                             ctx, expr0_0, expr1_0, expr2_0,
4823                                                         )?;
4824                                                         let expr4_0 =
4825                                                             constructor_output_reg(ctx, expr3_0)?;
4826                                                         return Some(expr4_0);
4827                                                     }
4828                                                 }
4829                                             }
4830                                         }
4831                                     }
4832                                 }
4833                                 &Opcode::UwidenLow => {
4834                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4835                                     if pattern12_0 == I16X8 {
4836                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4837                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4838                                             if let &InstructionData::Unary {
4839                                                 opcode: ref pattern16_0,
4840                                                 arg: pattern16_1,
4841                                             } = &pattern15_0
4842                                             {
4843                                                 if let &Opcode::UwidenLow = pattern16_0 {
4844                                                     let pattern18_0 =
4845                                                         C::value_type(ctx, pattern16_1);
4846                                                     if pattern18_0 == I16X8 {
4847                                                         // Rule at src/isa/aarch64/lower.isle line 322.
4848                                                         let expr0_0 =
4849                                                             C::put_in_reg(ctx, pattern10_1);
4850                                                         let expr1_0 =
4851                                                             C::put_in_reg(ctx, pattern16_1);
4852                                                         let expr2_0: bool = false;
4853                                                         let expr3_0 = constructor_umull16(
4854                                                             ctx, expr0_0, expr1_0, expr2_0,
4855                                                         )?;
4856                                                         let expr4_0 =
4857                                                             constructor_output_reg(ctx, expr3_0)?;
4858                                                         return Some(expr4_0);
4859                                                     }
4860                                                 }
4861                                             }
4862                                         }
4863                                     }
4864                                 }
4865                                 &Opcode::UwidenHigh => {
4866                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4867                                     if pattern12_0 == I16X8 {
4868                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4869                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4870                                             if let &InstructionData::Unary {
4871                                                 opcode: ref pattern16_0,
4872                                                 arg: pattern16_1,
4873                                             } = &pattern15_0
4874                                             {
4875                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4876                                                     let pattern18_0 =
4877                                                         C::value_type(ctx, pattern16_1);
4878                                                     if pattern18_0 == I16X8 {
4879                                                         // Rule at src/isa/aarch64/lower.isle line 328.
4880                                                         let expr0_0 =
4881                                                             C::put_in_reg(ctx, pattern10_1);
4882                                                         let expr1_0 =
4883                                                             C::put_in_reg(ctx, pattern16_1);
4884                                                         let expr2_0: bool = true;
4885                                                         let expr3_0 = constructor_umull16(
4886                                                             ctx, expr0_0, expr1_0, expr2_0,
4887                                                         )?;
4888                                                         let expr4_0 =
4889                                                             constructor_output_reg(ctx, expr3_0)?;
4890                                                         return Some(expr4_0);
4891                                                     }
4892                                                 }
4893                                             }
4894                                         }
4895                                     }
4896                                 }
4897                                 _ => {}
4898                             }
4899                         }
4900                     }
4901                 }
4902             }
4903         }
4904         if pattern2_0 == I64X2 {
4905             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4906             if let &InstructionData::Binary {
4907                 opcode: ref pattern5_0,
4908                 args: ref pattern5_1,
4909             } = &pattern4_0
4910             {
4911                 if let &Opcode::Imul = pattern5_0 {
4912                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4913                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4914                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4915                         if let &InstructionData::Unary {
4916                             opcode: ref pattern10_0,
4917                             arg: pattern10_1,
4918                         } = &pattern9_0
4919                         {
4920                             match pattern10_0 {
4921                                 &Opcode::SwidenLow => {
4922                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4923                                     if pattern12_0 == I32X4 {
4924                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4925                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4926                                             if let &InstructionData::Unary {
4927                                                 opcode: ref pattern16_0,
4928                                                 arg: pattern16_1,
4929                                             } = &pattern15_0
4930                                             {
4931                                                 if let &Opcode::SwidenLow = pattern16_0 {
4932                                                     let pattern18_0 =
4933                                                         C::value_type(ctx, pattern16_1);
4934                                                     if pattern18_0 == I32X4 {
4935                                                         // Rule at src/isa/aarch64/lower.isle line 334.
4936                                                         let expr0_0 =
4937                                                             C::put_in_reg(ctx, pattern10_1);
4938                                                         let expr1_0 =
4939                                                             C::put_in_reg(ctx, pattern16_1);
4940                                                         let expr2_0: bool = false;
4941                                                         let expr3_0 = constructor_smull32(
4942                                                             ctx, expr0_0, expr1_0, expr2_0,
4943                                                         )?;
4944                                                         let expr4_0 =
4945                                                             constructor_output_reg(ctx, expr3_0)?;
4946                                                         return Some(expr4_0);
4947                                                     }
4948                                                 }
4949                                             }
4950                                         }
4951                                     }
4952                                 }
4953                                 &Opcode::SwidenHigh => {
4954                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4955                                     if pattern12_0 == I32X4 {
4956                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4957                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4958                                             if let &InstructionData::Unary {
4959                                                 opcode: ref pattern16_0,
4960                                                 arg: pattern16_1,
4961                                             } = &pattern15_0
4962                                             {
4963                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4964                                                     let pattern18_0 =
4965                                                         C::value_type(ctx, pattern16_1);
4966                                                     if pattern18_0 == I32X4 {
4967                                                         // Rule at src/isa/aarch64/lower.isle line 340.
4968                                                         let expr0_0 =
4969                                                             C::put_in_reg(ctx, pattern10_1);
4970                                                         let expr1_0 =
4971                                                             C::put_in_reg(ctx, pattern16_1);
4972                                                         let expr2_0: bool = true;
4973                                                         let expr3_0 = constructor_smull32(
4974                                                             ctx, expr0_0, expr1_0, expr2_0,
4975                                                         )?;
4976                                                         let expr4_0 =
4977                                                             constructor_output_reg(ctx, expr3_0)?;
4978                                                         return Some(expr4_0);
4979                                                     }
4980                                                 }
4981                                             }
4982                                         }
4983                                     }
4984                                 }
4985                                 &Opcode::UwidenLow => {
4986                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4987                                     if pattern12_0 == I32X4 {
4988                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4989                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4990                                             if let &InstructionData::Unary {
4991                                                 opcode: ref pattern16_0,
4992                                                 arg: pattern16_1,
4993                                             } = &pattern15_0
4994                                             {
4995                                                 if let &Opcode::UwidenLow = pattern16_0 {
4996                                                     let pattern18_0 =
4997                                                         C::value_type(ctx, pattern16_1);
4998                                                     if pattern18_0 == I32X4 {
4999                                                         // Rule at src/isa/aarch64/lower.isle line 346.
5000                                                         let expr0_0 =
5001                                                             C::put_in_reg(ctx, pattern10_1);
5002                                                         let expr1_0 =
5003                                                             C::put_in_reg(ctx, pattern16_1);
5004                                                         let expr2_0: bool = false;
5005                                                         let expr3_0 = constructor_umull32(
5006                                                             ctx, expr0_0, expr1_0, expr2_0,
5007                                                         )?;
5008                                                         let expr4_0 =
5009                                                             constructor_output_reg(ctx, expr3_0)?;
5010                                                         return Some(expr4_0);
5011                                                     }
5012                                                 }
5013                                             }
5014                                         }
5015                                     }
5016                                 }
5017                                 &Opcode::UwidenHigh => {
5018                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5019                                     if pattern12_0 == I32X4 {
5020                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5021                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5022                                             if let &InstructionData::Unary {
5023                                                 opcode: ref pattern16_0,
5024                                                 arg: pattern16_1,
5025                                             } = &pattern15_0
5026                                             {
5027                                                 if let &Opcode::UwidenHigh = pattern16_0 {
5028                                                     let pattern18_0 =
5029                                                         C::value_type(ctx, pattern16_1);
5030                                                     if pattern18_0 == I32X4 {
5031                                                         // Rule at src/isa/aarch64/lower.isle line 352.
5032                                                         let expr0_0 =
5033                                                             C::put_in_reg(ctx, pattern10_1);
5034                                                         let expr1_0 =
5035                                                             C::put_in_reg(ctx, pattern16_1);
5036                                                         let expr2_0: bool = true;
5037                                                         let expr3_0 = constructor_umull32(
5038                                                             ctx, expr0_0, expr1_0, expr2_0,
5039                                                         )?;
5040                                                         let expr4_0 =
5041                                                             constructor_output_reg(ctx, expr3_0)?;
5042                                                         return Some(expr4_0);
5043                                                     }
5044                                                 }
5045                                             }
5046                                         }
5047                                     }
5048                                 }
5049                                 _ => {}
5050                             }
5051                         }
5052                     }
5053                     // Rule at src/isa/aarch64/lower.isle line 247.
5054                     let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5055                     let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5056                     let expr2_0 = VectorSize::Size32x4;
5057                     let expr3_0 = constructor_rev64(ctx, expr1_0, &expr2_0)?;
5058                     let expr4_0 = VectorSize::Size32x4;
5059                     let expr5_0 = constructor_mul(ctx, expr3_0, expr0_0, &expr4_0)?;
5060                     let expr6_0: bool = false;
5061                     let expr7_0 = constructor_xtn64(ctx, expr0_0, expr6_0)?;
5062                     let expr8_0 = VectorSize::Size32x4;
5063                     let expr9_0 = constructor_addp(ctx, expr5_0, expr5_0, &expr8_0)?;
5064                     let expr10_0: bool = false;
5065                     let expr11_0 = constructor_xtn64(ctx, expr1_0, expr10_0)?;
5066                     let expr12_0: bool = false;
5067                     let expr13_0 = constructor_shll32(ctx, expr9_0, expr12_0)?;
5068                     let expr14_0: bool = false;
5069                     let expr15_0 = constructor_umlal32(ctx, expr13_0, expr11_0, expr7_0, expr14_0)?;
5070                     let expr16_0 = constructor_output_reg(ctx, expr15_0)?;
5071                     return Some(expr16_0);
5072                 }
5073             }
5074         }
5075         let pattern3_0 = C::inst_data(ctx, pattern0_0);
5076         match &pattern3_0 {
5077             &InstructionData::NullAry {
5078                 opcode: ref pattern4_0,
5079             } => {
5080                 if let &Opcode::Null = pattern4_0 {
5081                     // Rule at src/isa/aarch64/lower.isle line 22.
5082                     let expr0_0: u64 = 0;
5083                     let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5084                     let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5085                     return Some(expr2_0);
5086                 }
5087             }
5088             &InstructionData::UnaryImm {
5089                 opcode: ref pattern4_0,
5090                 imm: pattern4_1,
5091             } => {
5092                 if let &Opcode::Iconst = pattern4_0 {
5093                     let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1);
5094                     // Rule at src/isa/aarch64/lower.isle line 9.
5095                     let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?;
5096                     let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
5097                     return Some(expr1_0);
5098                 }
5099             }
5100             &InstructionData::UnaryBool {
5101                 opcode: ref pattern4_0,
5102                 imm: pattern4_1,
5103             } => {
5104                 if let &Opcode::Bconst = pattern4_0 {
5105                     if pattern4_1 == true {
5106                         // Rule at src/isa/aarch64/lower.isle line 17.
5107                         let expr0_0: u64 = 1;
5108                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5109                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5110                         return Some(expr2_0);
5111                     }
5112                     if pattern4_1 == false {
5113                         // Rule at src/isa/aarch64/lower.isle line 14.
5114                         let expr0_0: u64 = 0;
5115                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5116                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5117                         return Some(expr2_0);
5118                     }
5119                 }
5120             }
5121             &InstructionData::Unary {
5122                 opcode: ref pattern4_0,
5123                 arg: pattern4_1,
5124             } => {
5125                 match pattern4_0 {
5126                     &Opcode::Bitrev => {
5127                         // Rule at src/isa/aarch64/lower.isle line 995.
5128                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5129                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5130                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5131                         return Some(expr2_0);
5132                     }
5133                     &Opcode::Clz => {
5134                         // Rule at src/isa/aarch64/lower.isle line 1010.
5135                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5136                         let expr1_0 = constructor_a64_clz(ctx, pattern2_0, expr0_0)?;
5137                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5138                         return Some(expr2_0);
5139                     }
5140                     &Opcode::Cls => {
5141                         // Rule at src/isa/aarch64/lower.isle line 1077.
5142                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5143                         let expr1_0 = constructor_a64_cls(ctx, pattern2_0, expr0_0)?;
5144                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5145                         return Some(expr2_0);
5146                     }
5147                     &Opcode::Ctz => {
5148                         // Rule at src/isa/aarch64/lower.isle line 1043.
5149                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5150                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5151                         let expr2_0 = constructor_a64_clz(ctx, pattern2_0, expr1_0)?;
5152                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5153                         return Some(expr3_0);
5154                     }
5155                     _ => {}
5156                 }
5157             }
5158             _ => {}
5159         }
5160         if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) {
5161             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5162             match &pattern4_0 {
5163                 &InstructionData::Binary {
5164                     opcode: ref pattern5_0,
5165                     args: ref pattern5_1,
5166                 } => {
5167                     match pattern5_0 {
5168                         &Opcode::Iadd => {
5169                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5170                             // Rule at src/isa/aarch64/lower.isle line 79.
5171                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5172                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5173                             let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5174                             let expr3_0 = constructor_add_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5175                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5176                             return Some(expr4_0);
5177                         }
5178                         &Opcode::Isub => {
5179                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5180                             // Rule at src/isa/aarch64/lower.isle line 129.
5181                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5182                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5183                             let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5184                             let expr3_0 = constructor_sub_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5185                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5186                             return Some(expr4_0);
5187                         }
5188                         _ => {}
5189                     }
5190                 }
5191                 &InstructionData::FloatCompare {
5192                     opcode: ref pattern5_0,
5193                     args: ref pattern5_1,
5194                     cond: ref pattern5_2,
5195                 } => {
5196                     if let &Opcode::Fcmp = pattern5_0 {
5197                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5198                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5199                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5200                             if let &InstructionData::Unary {
5201                                 opcode: ref pattern10_0,
5202                                 arg: pattern10_1,
5203                             } = &pattern9_0
5204                             {
5205                                 if let &Opcode::Splat = pattern10_0 {
5206                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5207                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5208                                         match &pattern13_0 {
5209                                             &InstructionData::UnaryIeee32 {
5210                                                 opcode: ref pattern14_0,
5211                                                 imm: pattern14_1,
5212                                             } => {
5213                                                 if let &Opcode::F32const = pattern14_0 {
5214                                                     if let Some(pattern16_0) =
5215                                                         C::zero_value_f32(ctx, pattern14_1)
5216                                                     {
5217                                                         if let Some(pattern17_0) =
5218                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5219                                                         {
5220                                                             // Rule at src/isa/aarch64/lower.isle line 1151.
5221                                                             let expr0_0 =
5222                                                                 C::put_in_reg(ctx, pattern7_1);
5223                                                             let expr1_0 = constructor_vector_size(
5224                                                                 ctx, pattern2_0,
5225                                                             )?;
5226                                                             let expr2_0 =
5227                                                                 constructor_float_cmp_zero_swap(
5228                                                                     ctx,
5229                                                                     &pattern17_0,
5230                                                                     expr0_0,
5231                                                                     &expr1_0,
5232                                                                 )?;
5233                                                             let expr3_0 =
5234                                                                 C::value_reg(ctx, expr2_0);
5235                                                             let expr4_0 = C::output(ctx, expr3_0);
5236                                                             return Some(expr4_0);
5237                                                         }
5238                                                         if let Some(pattern17_0) =
5239                                                             C::fcmp_zero_cond_not_eq(
5240                                                                 ctx, pattern5_2,
5241                                                             )
5242                                                         {
5243                                                             // Rule at src/isa/aarch64/lower.isle line 1146.
5244                                                             let expr0_0 =
5245                                                                 C::put_in_reg(ctx, pattern7_1);
5246                                                             let expr1_0 = constructor_vector_size(
5247                                                                 ctx, pattern2_0,
5248                                                             )?;
5249                                                             let expr2_0 = constructor_fcmeq0(
5250                                                                 ctx, expr0_0, &expr1_0,
5251                                                             )?;
5252                                                             let expr3_0 = constructor_not(
5253                                                                 ctx, expr2_0, &expr1_0,
5254                                                             )?;
5255                                                             let expr4_0 =
5256                                                                 C::value_reg(ctx, expr3_0);
5257                                                             let expr5_0 = C::output(ctx, expr4_0);
5258                                                             return Some(expr5_0);
5259                                                         }
5260                                                     }
5261                                                 }
5262                                             }
5263                                             &InstructionData::UnaryIeee64 {
5264                                                 opcode: ref pattern14_0,
5265                                                 imm: pattern14_1,
5266                                             } => {
5267                                                 if let &Opcode::F64const = pattern14_0 {
5268                                                     if let Some(pattern16_0) =
5269                                                         C::zero_value_f64(ctx, pattern14_1)
5270                                                     {
5271                                                         if let Some(pattern17_0) =
5272                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5273                                                         {
5274                                                             // Rule at src/isa/aarch64/lower.isle line 1173.
5275                                                             let expr0_0 =
5276                                                                 C::put_in_reg(ctx, pattern7_1);
5277                                                             let expr1_0 = constructor_vector_size(
5278                                                                 ctx, pattern2_0,
5279                                                             )?;
5280                                                             let expr2_0 =
5281                                                                 constructor_float_cmp_zero_swap(
5282                                                                     ctx,
5283                                                                     &pattern17_0,
5284                                                                     expr0_0,
5285                                                                     &expr1_0,
5286                                                                 )?;
5287                                                             let expr3_0 =
5288                                                                 C::value_reg(ctx, expr2_0);
5289                                                             let expr4_0 = C::output(ctx, expr3_0);
5290                                                             return Some(expr4_0);
5291                                                         }
5292                                                         if let Some(pattern17_0) =
5293                                                             C::fcmp_zero_cond_not_eq(
5294                                                                 ctx, pattern5_2,
5295                                                             )
5296                                                         {
5297                                                             // Rule at src/isa/aarch64/lower.isle line 1168.
5298                                                             let expr0_0 =
5299                                                                 C::put_in_reg(ctx, pattern7_1);
5300                                                             let expr1_0 = constructor_vector_size(
5301                                                                 ctx, pattern2_0,
5302                                                             )?;
5303                                                             let expr2_0 = constructor_fcmeq0(
5304                                                                 ctx, expr0_0, &expr1_0,
5305                                                             )?;
5306                                                             let expr3_0 = constructor_not(
5307                                                                 ctx, expr2_0, &expr1_0,
5308                                                             )?;
5309                                                             let expr4_0 =
5310                                                                 C::value_reg(ctx, expr3_0);
5311                                                             let expr5_0 = C::output(ctx, expr4_0);
5312                                                             return Some(expr5_0);
5313                                                         }
5314                                                     }
5315                                                 }
5316                                             }
5317                                             _ => {}
5318                                         }
5319                                     }
5320                                 }
5321                             }
5322                         }
5323                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5324                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5325                             if let &InstructionData::Unary {
5326                                 opcode: ref pattern10_0,
5327                                 arg: pattern10_1,
5328                             } = &pattern9_0
5329                             {
5330                                 if let &Opcode::Splat = pattern10_0 {
5331                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5332                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5333                                         match &pattern13_0 {
5334                                             &InstructionData::UnaryIeee32 {
5335                                                 opcode: ref pattern14_0,
5336                                                 imm: pattern14_1,
5337                                             } => {
5338                                                 if let &Opcode::F32const = pattern14_0 {
5339                                                     if let Some(pattern16_0) =
5340                                                         C::zero_value_f32(ctx, pattern14_1)
5341                                                     {
5342                                                         if let Some(pattern17_0) =
5343                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5344                                                         {
5345                                                             // Rule at src/isa/aarch64/lower.isle line 1141.
5346                                                             let expr0_0 =
5347                                                                 C::put_in_reg(ctx, pattern7_0);
5348                                                             let expr1_0 = constructor_vector_size(
5349                                                                 ctx, pattern2_0,
5350                                                             )?;
5351                                                             let expr2_0 =
5352                                                                 constructor_float_cmp_zero(
5353                                                                     ctx,
5354                                                                     &pattern17_0,
5355                                                                     expr0_0,
5356                                                                     &expr1_0,
5357                                                                 )?;
5358                                                             let expr3_0 =
5359                                                                 C::value_reg(ctx, expr2_0);
5360                                                             let expr4_0 = C::output(ctx, expr3_0);
5361                                                             return Some(expr4_0);
5362                                                         }
5363                                                         if let Some(pattern17_0) =
5364                                                             C::fcmp_zero_cond_not_eq(
5365                                                                 ctx, pattern5_2,
5366                                                             )
5367                                                         {
5368                                                             // Rule at src/isa/aarch64/lower.isle line 1136.
5369                                                             let expr0_0 =
5370                                                                 C::put_in_reg(ctx, pattern7_0);
5371                                                             let expr1_0 = constructor_vector_size(
5372                                                                 ctx, pattern2_0,
5373                                                             )?;
5374                                                             let expr2_0 = constructor_fcmeq0(
5375                                                                 ctx, expr0_0, &expr1_0,
5376                                                             )?;
5377                                                             let expr3_0 = constructor_not(
5378                                                                 ctx, expr2_0, &expr1_0,
5379                                                             )?;
5380                                                             let expr4_0 =
5381                                                                 C::value_reg(ctx, expr3_0);
5382                                                             let expr5_0 = C::output(ctx, expr4_0);
5383                                                             return Some(expr5_0);
5384                                                         }
5385                                                     }
5386                                                 }
5387                                             }
5388                                             &InstructionData::UnaryIeee64 {
5389                                                 opcode: ref pattern14_0,
5390                                                 imm: pattern14_1,
5391                                             } => {
5392                                                 if let &Opcode::F64const = pattern14_0 {
5393                                                     if let Some(pattern16_0) =
5394                                                         C::zero_value_f64(ctx, pattern14_1)
5395                                                     {
5396                                                         if let Some(pattern17_0) =
5397                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5398                                                         {
5399                                                             // Rule at src/isa/aarch64/lower.isle line 1163.
5400                                                             let expr0_0 =
5401                                                                 C::put_in_reg(ctx, pattern7_0);
5402                                                             let expr1_0 = constructor_vector_size(
5403                                                                 ctx, pattern2_0,
5404                                                             )?;
5405                                                             let expr2_0 =
5406                                                                 constructor_float_cmp_zero(
5407                                                                     ctx,
5408                                                                     &pattern17_0,
5409                                                                     expr0_0,
5410                                                                     &expr1_0,
5411                                                                 )?;
5412                                                             let expr3_0 =
5413                                                                 C::value_reg(ctx, expr2_0);
5414                                                             let expr4_0 = C::output(ctx, expr3_0);
5415                                                             return Some(expr4_0);
5416                                                         }
5417                                                         if let Some(pattern17_0) =
5418                                                             C::fcmp_zero_cond_not_eq(
5419                                                                 ctx, pattern5_2,
5420                                                             )
5421                                                         {
5422                                                             // Rule at src/isa/aarch64/lower.isle line 1158.
5423                                                             let expr0_0 =
5424                                                                 C::put_in_reg(ctx, pattern7_0);
5425                                                             let expr1_0 = constructor_vector_size(
5426                                                                 ctx, pattern2_0,
5427                                                             )?;
5428                                                             let expr2_0 = constructor_fcmeq0(
5429                                                                 ctx, expr0_0, &expr1_0,
5430                                                             )?;
5431                                                             let expr3_0 = constructor_not(
5432                                                                 ctx, expr2_0, &expr1_0,
5433                                                             )?;
5434                                                             let expr4_0 =
5435                                                                 C::value_reg(ctx, expr3_0);
5436                                                             let expr5_0 = C::output(ctx, expr4_0);
5437                                                             return Some(expr5_0);
5438                                                         }
5439                                                     }
5440                                                 }
5441                                             }
5442                                             _ => {}
5443                                         }
5444                                     }
5445                                 }
5446                             }
5447                         }
5448                     }
5449                 }
5450                 &InstructionData::IntCompare {
5451                     opcode: ref pattern5_0,
5452                     args: ref pattern5_1,
5453                     cond: ref pattern5_2,
5454                 } => {
5455                     if let &Opcode::Icmp = pattern5_0 {
5456                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5457                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5458                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5459                             if let &InstructionData::Unary {
5460                                 opcode: ref pattern10_0,
5461                                 arg: pattern10_1,
5462                             } = &pattern9_0
5463                             {
5464                                 if let &Opcode::Splat = pattern10_0 {
5465                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5466                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5467                                         if let &InstructionData::UnaryImm {
5468                                             opcode: ref pattern14_0,
5469                                             imm: pattern14_1,
5470                                         } = &pattern13_0
5471                                         {
5472                                             if let &Opcode::Iconst = pattern14_0 {
5473                                                 if let Some(pattern16_0) =
5474                                                     C::zero_value(ctx, pattern14_1)
5475                                                 {
5476                                                     if let Some(pattern17_0) =
5477                                                         C::icmp_zero_cond(ctx, pattern5_2)
5478                                                     {
5479                                                         // Rule at src/isa/aarch64/lower.isle line 1195.
5480                                                         let expr0_0 =
5481                                                             C::put_in_reg(ctx, pattern7_1);
5482                                                         let expr1_0 = constructor_vector_size(
5483                                                             ctx, pattern2_0,
5484                                                         )?;
5485                                                         let expr2_0 =
5486                                                             constructor_int_cmp_zero_swap(
5487                                                                 ctx,
5488                                                                 &pattern17_0,
5489                                                                 expr0_0,
5490                                                                 &expr1_0,
5491                                                             )?;
5492                                                         let expr3_0 = C::value_reg(ctx, expr2_0);
5493                                                         let expr4_0 = C::output(ctx, expr3_0);
5494                                                         return Some(expr4_0);
5495                                                     }
5496                                                     if let Some(pattern17_0) =
5497                                                         C::icmp_zero_cond_not_eq(ctx, pattern5_2)
5498                                                     {
5499                                                         // Rule at src/isa/aarch64/lower.isle line 1190.
5500                                                         let expr0_0 =
5501                                                             C::put_in_reg(ctx, pattern7_1);
5502                                                         let expr1_0 = constructor_vector_size(
5503                                                             ctx, pattern2_0,
5504                                                         )?;
5505                                                         let expr2_0 = constructor_cmeq0(
5506                                                             ctx, expr0_0, &expr1_0,
5507                                                         )?;
5508                                                         let expr3_0 = constructor_not(
5509                                                             ctx, expr2_0, &expr1_0,
5510                                                         )?;
5511                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5512                                                         let expr5_0 = C::output(ctx, expr4_0);
5513                                                         return Some(expr5_0);
5514                                                     }
5515                                                 }
5516                                             }
5517                                         }
5518                                     }
5519                                 }
5520                             }
5521                         }
5522                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5523                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5524                             if let &InstructionData::Unary {
5525                                 opcode: ref pattern10_0,
5526                                 arg: pattern10_1,
5527                             } = &pattern9_0
5528                             {
5529                                 if let &Opcode::Splat = pattern10_0 {
5530                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5531                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5532                                         if let &InstructionData::UnaryImm {
5533                                             opcode: ref pattern14_0,
5534                                             imm: pattern14_1,
5535                                         } = &pattern13_0
5536                                         {
5537                                             if let &Opcode::Iconst = pattern14_0 {
5538                                                 if let Some(pattern16_0) =
5539                                                     C::zero_value(ctx, pattern14_1)
5540                                                 {
5541                                                     if let Some(pattern17_0) =
5542                                                         C::icmp_zero_cond(ctx, pattern5_2)
5543                                                     {
5544                                                         // Rule at src/isa/aarch64/lower.isle line 1185.
5545                                                         let expr0_0 =
5546                                                             C::put_in_reg(ctx, pattern7_0);
5547                                                         let expr1_0 = constructor_vector_size(
5548                                                             ctx, pattern2_0,
5549                                                         )?;
5550                                                         let expr2_0 = constructor_int_cmp_zero(
5551                                                             ctx,
5552                                                             &pattern17_0,
5553                                                             expr0_0,
5554                                                             &expr1_0,
5555                                                         )?;
5556                                                         let expr3_0 = C::value_reg(ctx, expr2_0);
5557                                                         let expr4_0 = C::output(ctx, expr3_0);
5558                                                         return Some(expr4_0);
5559                                                     }
5560                                                     if let Some(pattern17_0) =
5561                                                         C::icmp_zero_cond_not_eq(ctx, pattern5_2)
5562                                                     {
5563                                                         // Rule at src/isa/aarch64/lower.isle line 1180.
5564                                                         let expr0_0 =
5565                                                             C::put_in_reg(ctx, pattern7_0);
5566                                                         let expr1_0 = constructor_vector_size(
5567                                                             ctx, pattern2_0,
5568                                                         )?;
5569                                                         let expr2_0 = constructor_cmeq0(
5570                                                             ctx, expr0_0, &expr1_0,
5571                                                         )?;
5572                                                         let expr3_0 = constructor_not(
5573                                                             ctx, expr2_0, &expr1_0,
5574                                                         )?;
5575                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5576                                                         let expr5_0 = C::output(ctx, expr4_0);
5577                                                         return Some(expr5_0);
5578                                                     }
5579                                                 }
5580                                             }
5581                                         }
5582                                     }
5583                                 }
5584                             }
5585                         }
5586                     }
5587                 }
5588                 _ => {}
5589             }
5590         }
5591         if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
5592             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5593             if let &InstructionData::Binary {
5594                 opcode: ref pattern5_0,
5595                 args: ref pattern5_1,
5596             } = &pattern4_0
5597             {
5598                 match pattern5_0 {
5599                     &Opcode::Rotl => {
5600                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5601                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5602                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5603                             if let &InstructionData::UnaryImm {
5604                                 opcode: ref pattern10_0,
5605                                 imm: pattern10_1,
5606                             } = &pattern9_0
5607                             {
5608                                 if let &Opcode::Iconst = pattern10_0 {
5609                                     let closure12 = || {
5610                                         return Some(pattern3_0);
5611                                     };
5612                                     if let Some(pattern12_0) = closure12() {
5613                                         if let Some(pattern13_0) =
5614                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5615                                         {
5616                                             // Rule at src/isa/aarch64/lower.isle line 849.
5617                                             let expr0_0 =
5618                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5619                                             let expr1_0 =
5620                                                 C::negate_imm_shift(ctx, pattern3_0, pattern13_0);
5621                                             let expr2_0 = constructor_small_rotr_imm(
5622                                                 ctx, pattern3_0, expr0_0, expr1_0,
5623                                             )?;
5624                                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5625                                             return Some(expr3_0);
5626                                         }
5627                                     }
5628                                 }
5629                             }
5630                         }
5631                         // Rule at src/isa/aarch64/lower.isle line 844.
5632                         let expr0_0: Type = I32;
5633                         let expr1_0 = C::zero_reg(ctx);
5634                         let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5635                         let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
5636                         let expr4_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5637                         let expr5_0 = constructor_small_rotr(ctx, pattern3_0, expr4_0, expr3_0)?;
5638                         let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
5639                         return Some(expr6_0);
5640                     }
5641                     &Opcode::Rotr => {
5642                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5643                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5644                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5645                             if let &InstructionData::UnaryImm {
5646                                 opcode: ref pattern10_0,
5647                                 imm: pattern10_1,
5648                             } = &pattern9_0
5649                             {
5650                                 if let &Opcode::Iconst = pattern10_0 {
5651                                     let closure12 = || {
5652                                         return Some(pattern3_0);
5653                                     };
5654                                     if let Some(pattern12_0) = closure12() {
5655                                         if let Some(pattern13_0) =
5656                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5657                                         {
5658                                             // Rule at src/isa/aarch64/lower.isle line 909.
5659                                             let expr0_0 =
5660                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5661                                             let expr1_0 = constructor_small_rotr_imm(
5662                                                 ctx,
5663                                                 pattern3_0,
5664                                                 expr0_0,
5665                                                 pattern13_0,
5666                                             )?;
5667                                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5668                                             return Some(expr2_0);
5669                                         }
5670                                     }
5671                                 }
5672                             }
5673                         }
5674                         // Rule at src/isa/aarch64/lower.isle line 897.
5675                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5676                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5677                         let expr2_0 = constructor_small_rotr(ctx, pattern3_0, expr0_0, expr1_0)?;
5678                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5679                         return Some(expr3_0);
5680                     }
5681                     _ => {}
5682                 }
5683             }
5684         }
5685         if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
5686             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5687             if let &InstructionData::Binary {
5688                 opcode: ref pattern5_0,
5689                 args: ref pattern5_1,
5690             } = &pattern4_0
5691             {
5692                 match pattern5_0 {
5693                     &Opcode::Umulhi => {
5694                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5695                         // Rule at src/isa/aarch64/lower.isle line 374.
5696                         let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5697                         let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?;
5698                         let expr2_0: Type = I64;
5699                         let expr3_0 = C::zero_reg(ctx);
5700                         let expr4_0 = constructor_madd(ctx, expr2_0, expr0_0, expr1_0, expr3_0)?;
5701                         let expr5_0: Type = I64;
5702                         let expr6_0 = C::ty_bits(ctx, pattern3_0);
5703                         let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
5704                         let expr8_0 = constructor_lsr_imm(ctx, expr5_0, expr4_0, expr7_0)?;
5705                         let expr9_0 = C::value_reg(ctx, expr8_0);
5706                         let expr10_0 = C::output(ctx, expr9_0);
5707                         return Some(expr10_0);
5708                     }
5709                     &Opcode::Smulhi => {
5710                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5711                         // Rule at src/isa/aarch64/lower.isle line 362.
5712                         let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5713                         let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?;
5714                         let expr2_0: Type = I64;
5715                         let expr3_0 = C::zero_reg(ctx);
5716                         let expr4_0 = constructor_madd(ctx, expr2_0, expr0_0, expr1_0, expr3_0)?;
5717                         let expr5_0: Type = I64;
5718                         let expr6_0 = C::ty_bits(ctx, pattern3_0);
5719                         let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
5720                         let expr8_0 = constructor_asr_imm(ctx, expr5_0, expr4_0, expr7_0)?;
5721                         let expr9_0 = constructor_output_reg(ctx, expr8_0)?;
5722                         return Some(expr9_0);
5723                     }
5724                     &Opcode::Band => {
5725                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5726                         // Rule at src/isa/aarch64/lower.isle line 589.
5727                         let expr0_0 = ALUOp::And;
5728                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5729                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5730                         )?;
5731                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5732                         return Some(expr2_0);
5733                     }
5734                     &Opcode::Bor => {
5735                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5736                         // Rule at src/isa/aarch64/lower.isle line 602.
5737                         let expr0_0 = ALUOp::Orr;
5738                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5739                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5740                         )?;
5741                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5742                         return Some(expr2_0);
5743                     }
5744                     &Opcode::Bxor => {
5745                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5746                         // Rule at src/isa/aarch64/lower.isle line 615.
5747                         let expr0_0 = ALUOp::Eor;
5748                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5749                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5750                         )?;
5751                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5752                         return Some(expr2_0);
5753                     }
5754                     &Opcode::BandNot => {
5755                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5756                         // Rule at src/isa/aarch64/lower.isle line 628.
5757                         let expr0_0 = ALUOp::AndNot;
5758                         let expr1_0 = constructor_alu_rs_imm_logic(
5759                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5760                         )?;
5761                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5762                         return Some(expr2_0);
5763                     }
5764                     &Opcode::BorNot => {
5765                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5766                         // Rule at src/isa/aarch64/lower.isle line 641.
5767                         let expr0_0 = ALUOp::OrrNot;
5768                         let expr1_0 = constructor_alu_rs_imm_logic(
5769                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5770                         )?;
5771                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5772                         return Some(expr2_0);
5773                     }
5774                     &Opcode::BxorNot => {
5775                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5776                         // Rule at src/isa/aarch64/lower.isle line 651.
5777                         let expr0_0 = ALUOp::EorNot;
5778                         let expr1_0: Type = I32;
5779                         let expr2_0 = constructor_alu_rs_imm_logic(
5780                             ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
5781                         )?;
5782                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5783                         return Some(expr3_0);
5784                     }
5785                     &Opcode::Ishl => {
5786                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5787                         // Rule at src/isa/aarch64/lower.isle line 662.
5788                         let expr0_0 = ALUOp::Lsl;
5789                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
5790                         let expr2_0 =
5791                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5792                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5793                         return Some(expr3_0);
5794                     }
5795                     &Opcode::Ushr => {
5796                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5797                         // Rule at src/isa/aarch64/lower.isle line 746.
5798                         let expr0_0 = ALUOp::Lsr;
5799                         let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5800                         let expr2_0 =
5801                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5802                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5803                         return Some(expr3_0);
5804                     }
5805                     &Opcode::Sshr => {
5806                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5807                         // Rule at src/isa/aarch64/lower.isle line 793.
5808                         let expr0_0 = ALUOp::Asr;
5809                         let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
5810                         let expr2_0 =
5811                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5812                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5813                         return Some(expr3_0);
5814                     }
5815                     _ => {}
5816                 }
5817             }
5818         }
5819         if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
5820             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5821             match &pattern4_0 {
5822                 &InstructionData::Binary {
5823                     opcode: ref pattern5_0,
5824                     args: ref pattern5_1,
5825                 } => {
5826                     match pattern5_0 {
5827                         &Opcode::Iadd => {
5828                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5829                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5830                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5831                                 match &pattern9_0 {
5832                                     &InstructionData::UnaryImm {
5833                                         opcode: ref pattern10_0,
5834                                         imm: pattern10_1,
5835                                     } => {
5836                                         if let &Opcode::Iconst = pattern10_0 {
5837                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5838                                             if let Some(pattern13_0) =
5839                                                 C::imm12_from_u64(ctx, pattern12_0)
5840                                             {
5841                                                 // Rule at src/isa/aarch64/lower.isle line 37.
5842                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5843                                                 let expr1_0 = constructor_add_imm(
5844                                                     ctx,
5845                                                     pattern3_0,
5846                                                     expr0_0,
5847                                                     pattern13_0,
5848                                                 )?;
5849                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5850                                                 return Some(expr2_0);
5851                                             }
5852                                             if let Some(pattern13_0) =
5853                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5854                                             {
5855                                                 // Rule at src/isa/aarch64/lower.isle line 45.
5856                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5857                                                 let expr1_0 = constructor_sub_imm(
5858                                                     ctx,
5859                                                     pattern3_0,
5860                                                     expr0_0,
5861                                                     pattern13_0,
5862                                                 )?;
5863                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5864                                                 return Some(expr2_0);
5865                                             }
5866                                         }
5867                                     }
5868                                     &InstructionData::Binary {
5869                                         opcode: ref pattern10_0,
5870                                         args: ref pattern10_1,
5871                                     } => {
5872                                         match pattern10_0 {
5873                                             &Opcode::Imul => {
5874                                                 let (pattern12_0, pattern12_1) =
5875                                                     C::unpack_value_array_2(ctx, pattern10_1);
5876                                                 // Rule at src/isa/aarch64/lower.isle line 70.
5877                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5878                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5879                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5880                                                 let expr3_0 = constructor_madd(
5881                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5882                                                 )?;
5883                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5884                                                 return Some(expr4_0);
5885                                             }
5886                                             &Opcode::Ishl => {
5887                                                 let (pattern12_0, pattern12_1) =
5888                                                     C::unpack_value_array_2(ctx, pattern10_1);
5889                                                 if let Some(pattern13_0) =
5890                                                     C::def_inst(ctx, pattern12_1)
5891                                                 {
5892                                                     let pattern14_0 =
5893                                                         C::inst_data(ctx, pattern13_0);
5894                                                     if let &InstructionData::UnaryImm {
5895                                                         opcode: ref pattern15_0,
5896                                                         imm: pattern15_1,
5897                                                     } = &pattern14_0
5898                                                     {
5899                                                         if let &Opcode::Iconst = pattern15_0 {
5900                                                             let closure17 = || {
5901                                                                 return Some(pattern3_0);
5902                                                             };
5903                                                             if let Some(pattern17_0) = closure17() {
5904                                                                 if let Some(pattern18_0) =
5905                                                                     C::lshl_from_imm64(
5906                                                                         ctx,
5907                                                                         pattern15_1,
5908                                                                         pattern17_0,
5909                                                                     )
5910                                                                 {
5911                                                                     // Rule at src/isa/aarch64/lower.isle line 62.
5912                                                                     let expr0_0 = C::put_in_reg(
5913                                                                         ctx, pattern7_1,
5914                                                                     );
5915                                                                     let expr1_0 = C::put_in_reg(
5916                                                                         ctx,
5917                                                                         pattern12_0,
5918                                                                     );
5919                                                                     let expr2_0 =
5920                                                                         constructor_add_shift(
5921                                                                             ctx,
5922                                                                             pattern3_0,
5923                                                                             expr0_0,
5924                                                                             expr1_0,
5925                                                                             pattern18_0,
5926                                                                         )?;
5927                                                                     let expr3_0 =
5928                                                                         constructor_output_reg(
5929                                                                             ctx, expr2_0,
5930                                                                         )?;
5931                                                                     return Some(expr3_0);
5932                                                                 }
5933                                                             }
5934                                                         }
5935                                                     }
5936                                                 }
5937                                             }
5938                                             _ => {}
5939                                         }
5940                                     }
5941                                     _ => {}
5942                                 }
5943                             }
5944                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0)
5945                             {
5946                                 // Rule at src/isa/aarch64/lower.isle line 53.
5947                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5948                                 let expr1_0 =
5949                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5950                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5951                                 return Some(expr2_0);
5952                             }
5953                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5954                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5955                                 match &pattern9_0 {
5956                                     &InstructionData::UnaryImm {
5957                                         opcode: ref pattern10_0,
5958                                         imm: pattern10_1,
5959                                     } => {
5960                                         if let &Opcode::Iconst = pattern10_0 {
5961                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5962                                             if let Some(pattern13_0) =
5963                                                 C::imm12_from_u64(ctx, pattern12_0)
5964                                             {
5965                                                 // Rule at src/isa/aarch64/lower.isle line 34.
5966                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5967                                                 let expr1_0 = constructor_add_imm(
5968                                                     ctx,
5969                                                     pattern3_0,
5970                                                     expr0_0,
5971                                                     pattern13_0,
5972                                                 )?;
5973                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5974                                                 return Some(expr2_0);
5975                                             }
5976                                             if let Some(pattern13_0) =
5977                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5978                                             {
5979                                                 // Rule at src/isa/aarch64/lower.isle line 42.
5980                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5981                                                 let expr1_0 = constructor_sub_imm(
5982                                                     ctx,
5983                                                     pattern3_0,
5984                                                     expr0_0,
5985                                                     pattern13_0,
5986                                                 )?;
5987                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5988                                                 return Some(expr2_0);
5989                                             }
5990                                         }
5991                                     }
5992                                     &InstructionData::Binary {
5993                                         opcode: ref pattern10_0,
5994                                         args: ref pattern10_1,
5995                                     } => {
5996                                         match pattern10_0 {
5997                                             &Opcode::Imul => {
5998                                                 let (pattern12_0, pattern12_1) =
5999                                                     C::unpack_value_array_2(ctx, pattern10_1);
6000                                                 // Rule at src/isa/aarch64/lower.isle line 67.
6001                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
6002                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
6003                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
6004                                                 let expr3_0 = constructor_madd(
6005                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
6006                                                 )?;
6007                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6008                                                 return Some(expr4_0);
6009                                             }
6010                                             &Opcode::Ishl => {
6011                                                 let (pattern12_0, pattern12_1) =
6012                                                     C::unpack_value_array_2(ctx, pattern10_1);
6013                                                 if let Some(pattern13_0) =
6014                                                     C::def_inst(ctx, pattern12_1)
6015                                                 {
6016                                                     let pattern14_0 =
6017                                                         C::inst_data(ctx, pattern13_0);
6018                                                     if let &InstructionData::UnaryImm {
6019                                                         opcode: ref pattern15_0,
6020                                                         imm: pattern15_1,
6021                                                     } = &pattern14_0
6022                                                     {
6023                                                         if let &Opcode::Iconst = pattern15_0 {
6024                                                             let closure17 = || {
6025                                                                 return Some(pattern3_0);
6026                                                             };
6027                                                             if let Some(pattern17_0) = closure17() {
6028                                                                 if let Some(pattern18_0) =
6029                                                                     C::lshl_from_imm64(
6030                                                                         ctx,
6031                                                                         pattern15_1,
6032                                                                         pattern17_0,
6033                                                                     )
6034                                                                 {
6035                                                                     // Rule at src/isa/aarch64/lower.isle line 58.
6036                                                                     let expr0_0 = C::put_in_reg(
6037                                                                         ctx, pattern7_0,
6038                                                                     );
6039                                                                     let expr1_0 = C::put_in_reg(
6040                                                                         ctx,
6041                                                                         pattern12_0,
6042                                                                     );
6043                                                                     let expr2_0 =
6044                                                                         constructor_add_shift(
6045                                                                             ctx,
6046                                                                             pattern3_0,
6047                                                                             expr0_0,
6048                                                                             expr1_0,
6049                                                                             pattern18_0,
6050                                                                         )?;
6051                                                                     let expr3_0 =
6052                                                                         constructor_output_reg(
6053                                                                             ctx, expr2_0,
6054                                                                         )?;
6055                                                                     return Some(expr3_0);
6056                                                                 }
6057                                                             }
6058                                                         }
6059                                                     }
6060                                                 }
6061                                             }
6062                                             _ => {}
6063                                         }
6064                                     }
6065                                     _ => {}
6066                                 }
6067                             }
6068                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
6069                             {
6070                                 // Rule at src/isa/aarch64/lower.isle line 50.
6071                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6072                                 let expr1_0 =
6073                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6074                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6075                                 return Some(expr2_0);
6076                             }
6077                             // Rule at src/isa/aarch64/lower.isle line 30.
6078                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6079                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6080                             let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, expr1_0)?;
6081                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6082                             return Some(expr3_0);
6083                         }
6084                         &Opcode::Isub => {
6085                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6086                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6087                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6088                                 match &pattern9_0 {
6089                                     &InstructionData::UnaryImm {
6090                                         opcode: ref pattern10_0,
6091                                         imm: pattern10_1,
6092                                     } => {
6093                                         if let &Opcode::Iconst = pattern10_0 {
6094                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
6095                                             if let Some(pattern13_0) =
6096                                                 C::imm12_from_u64(ctx, pattern12_0)
6097                                             {
6098                                                 // Rule at src/isa/aarch64/lower.isle line 109.
6099                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6100                                                 let expr1_0 = constructor_sub_imm(
6101                                                     ctx,
6102                                                     pattern3_0,
6103                                                     expr0_0,
6104                                                     pattern13_0,
6105                                                 )?;
6106                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6107                                                 return Some(expr2_0);
6108                                             }
6109                                             if let Some(pattern13_0) =
6110                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
6111                                             {
6112                                                 // Rule at src/isa/aarch64/lower.isle line 114.
6113                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6114                                                 let expr1_0 = constructor_add_imm(
6115                                                     ctx,
6116                                                     pattern3_0,
6117                                                     expr0_0,
6118                                                     pattern13_0,
6119                                                 )?;
6120                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6121                                                 return Some(expr2_0);
6122                                             }
6123                                         }
6124                                     }
6125                                     &InstructionData::Binary {
6126                                         opcode: ref pattern10_0,
6127                                         args: ref pattern10_1,
6128                                     } => {
6129                                         match pattern10_0 {
6130                                             &Opcode::Imul => {
6131                                                 let (pattern12_0, pattern12_1) =
6132                                                     C::unpack_value_array_2(ctx, pattern10_1);
6133                                                 // Rule at src/isa/aarch64/lower.isle line 74.
6134                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
6135                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
6136                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
6137                                                 let expr3_0 = constructor_msub(
6138                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
6139                                                 )?;
6140                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6141                                                 return Some(expr4_0);
6142                                             }
6143                                             &Opcode::Ishl => {
6144                                                 let (pattern12_0, pattern12_1) =
6145                                                     C::unpack_value_array_2(ctx, pattern10_1);
6146                                                 if let Some(pattern13_0) =
6147                                                     C::def_inst(ctx, pattern12_1)
6148                                                 {
6149                                                     let pattern14_0 =
6150                                                         C::inst_data(ctx, pattern13_0);
6151                                                     if let &InstructionData::UnaryImm {
6152                                                         opcode: ref pattern15_0,
6153                                                         imm: pattern15_1,
6154                                                     } = &pattern14_0
6155                                                     {
6156                                                         if let &Opcode::Iconst = pattern15_0 {
6157                                                             let closure17 = || {
6158                                                                 return Some(pattern3_0);
6159                                                             };
6160                                                             if let Some(pattern17_0) = closure17() {
6161                                                                 if let Some(pattern18_0) =
6162                                                                     C::lshl_from_imm64(
6163                                                                         ctx,
6164                                                                         pattern15_1,
6165                                                                         pattern17_0,
6166                                                                     )
6167                                                                 {
6168                                                                     // Rule at src/isa/aarch64/lower.isle line 124.
6169                                                                     let expr0_0 = C::put_in_reg(
6170                                                                         ctx, pattern7_0,
6171                                                                     );
6172                                                                     let expr1_0 = C::put_in_reg(
6173                                                                         ctx,
6174                                                                         pattern12_0,
6175                                                                     );
6176                                                                     let expr2_0 =
6177                                                                         constructor_sub_shift(
6178                                                                             ctx,
6179                                                                             pattern3_0,
6180                                                                             expr0_0,
6181                                                                             expr1_0,
6182                                                                             pattern18_0,
6183                                                                         )?;
6184                                                                     let expr3_0 =
6185                                                                         constructor_output_reg(
6186                                                                             ctx, expr2_0,
6187                                                                         )?;
6188                                                                     return Some(expr3_0);
6189                                                                 }
6190                                                             }
6191                                                         }
6192                                                     }
6193                                                 }
6194                                             }
6195                                             _ => {}
6196                                         }
6197                                     }
6198                                     _ => {}
6199                                 }
6200                             }
6201                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
6202                             {
6203                                 // Rule at src/isa/aarch64/lower.isle line 119.
6204                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6205                                 let expr1_0 =
6206                                     constructor_sub_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6207                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6208                                 return Some(expr2_0);
6209                             }
6210                             // Rule at src/isa/aarch64/lower.isle line 105.
6211                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6212                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6213                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
6214                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6215                             return Some(expr3_0);
6216                         }
6217                         &Opcode::Imul => {
6218                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6219                             // Rule at src/isa/aarch64/lower.isle line 183.
6220                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6221                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6222                             let expr2_0 = C::zero_reg(ctx);
6223                             let expr3_0 =
6224                                 constructor_madd(ctx, pattern3_0, expr0_0, expr1_0, expr2_0)?;
6225                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6226                             return Some(expr4_0);
6227                         }
6228                         &Opcode::Udiv => {
6229                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6230                             // Rule at src/isa/aarch64/lower.isle line 390.
6231                             let expr0_0: Type = I64;
6232                             let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
6233                             let expr2_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
6234                             let expr3_0 = constructor_a64_udiv(ctx, expr0_0, expr1_0, expr2_0)?;
6235                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6236                             return Some(expr4_0);
6237                         }
6238                         &Opcode::Sdiv => {
6239                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6240                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6241                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6242                                 if let &InstructionData::UnaryImm {
6243                                     opcode: ref pattern10_0,
6244                                     imm: pattern10_1,
6245                                 } = &pattern9_0
6246                                 {
6247                                     if let &Opcode::Iconst = pattern10_0 {
6248                                         if let Some(pattern12_0) =
6249                                             C::safe_divisor_from_imm64(ctx, pattern10_1)
6250                                         {
6251                                             // Rule at src/isa/aarch64/lower.isle line 436.
6252                                             let expr0_0: Type = I64;
6253                                             let expr1_0 =
6254                                                 constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6255                                             let expr2_0 =
6256                                                 constructor_imm(ctx, pattern3_0, pattern12_0)?;
6257                                             let expr3_0 = constructor_a64_sdiv(
6258                                                 ctx, expr0_0, expr1_0, expr2_0,
6259                                             )?;
6260                                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6261                                             return Some(expr4_0);
6262                                         }
6263                                     }
6264                                 }
6265                             }
6266                             // Rule at src/isa/aarch64/lower.isle line 423.
6267                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6268                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
6269                             let expr2_0 = constructor_trap_if_div_overflow(
6270                                 ctx, pattern3_0, expr0_0, expr1_0,
6271                             )?;
6272                             let expr3_0: Type = I64;
6273                             let expr4_0 = constructor_a64_sdiv(ctx, expr3_0, expr2_0, expr1_0)?;
6274                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6275                             return Some(expr5_0);
6276                         }
6277                         &Opcode::Urem => {
6278                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6279                             // Rule at src/isa/aarch64/lower.isle line 464.
6280                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
6281                             let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
6282                             let expr2_0: Type = I64;
6283                             let expr3_0 = constructor_a64_udiv(ctx, expr2_0, expr0_0, expr1_0)?;
6284                             let expr4_0: Type = I64;
6285                             let expr5_0 =
6286                                 constructor_msub(ctx, expr4_0, expr3_0, expr1_0, expr0_0)?;
6287                             let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
6288                             return Some(expr6_0);
6289                         }
6290                         &Opcode::Srem => {
6291                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6292                             // Rule at src/isa/aarch64/lower.isle line 471.
6293                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6294                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
6295                             let expr2_0: Type = I64;
6296                             let expr3_0 = constructor_a64_sdiv(ctx, expr2_0, expr0_0, expr1_0)?;
6297                             let expr4_0: Type = I64;
6298                             let expr5_0 =
6299                                 constructor_msub(ctx, expr4_0, expr3_0, expr1_0, expr0_0)?;
6300                             let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
6301                             return Some(expr6_0);
6302                         }
6303                         _ => {}
6304                     }
6305                 }
6306                 &InstructionData::Unary {
6307                     opcode: ref pattern5_0,
6308                     arg: pattern5_1,
6309                 } => {
6310                     match pattern5_0 {
6311                         &Opcode::Ineg => {
6312                             // Rule at src/isa/aarch64/lower.isle line 173.
6313                             let expr0_0 = C::zero_reg(ctx);
6314                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6315                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
6316                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6317                             return Some(expr3_0);
6318                         }
6319                         &Opcode::Bnot => {
6320                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6321                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6322                                 if let &InstructionData::Binary {
6323                                     opcode: ref pattern9_0,
6324                                     args: ref pattern9_1,
6325                                 } = &pattern8_0
6326                                 {
6327                                     if let &Opcode::Ishl = pattern9_0 {
6328                                         let (pattern11_0, pattern11_1) =
6329                                             C::unpack_value_array_2(ctx, pattern9_1);
6330                                         if let Some(pattern12_0) = C::def_inst(ctx, pattern11_1) {
6331                                             let pattern13_0 = C::inst_data(ctx, pattern12_0);
6332                                             if let &InstructionData::UnaryImm {
6333                                                 opcode: ref pattern14_0,
6334                                                 imm: pattern14_1,
6335                                             } = &pattern13_0
6336                                             {
6337                                                 if let &Opcode::Iconst = pattern14_0 {
6338                                                     let closure16 = || {
6339                                                         return Some(pattern3_0);
6340                                                     };
6341                                                     if let Some(pattern16_0) = closure16() {
6342                                                         if let Some(pattern17_0) =
6343                                                             C::lshl_from_imm64(
6344                                                                 ctx,
6345                                                                 pattern14_1,
6346                                                                 pattern16_0,
6347                                                             )
6348                                                         {
6349                                                             // Rule at src/isa/aarch64/lower.isle line 570.
6350                                                             let expr0_0 = C::zero_reg(ctx);
6351                                                             let expr1_0 =
6352                                                                 C::put_in_reg(ctx, pattern11_0);
6353                                                             let expr2_0 =
6354                                                                 constructor_orr_not_shift(
6355                                                                     ctx,
6356                                                                     pattern3_0,
6357                                                                     expr0_0,
6358                                                                     expr1_0,
6359                                                                     pattern17_0,
6360                                                                 )?;
6361                                                             let expr3_0 = constructor_output_reg(
6362                                                                 ctx, expr2_0,
6363                                                             )?;
6364                                                             return Some(expr3_0);
6365                                                         }
6366                                                     }
6367                                                 }
6368                                             }
6369                                         }
6370                                     }
6371                                 }
6372                             }
6373                             // Rule at src/isa/aarch64/lower.isle line 565.
6374                             let expr0_0 = C::zero_reg(ctx);
6375                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6376                             let expr2_0 = constructor_orr_not(ctx, pattern3_0, expr0_0, expr1_0)?;
6377                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6378                             return Some(expr3_0);
6379                         }
6380                         &Opcode::Uextend => {
6381                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6382                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6383                                 if let &InstructionData::BinaryImm8 {
6384                                     opcode: ref pattern9_0,
6385                                     arg: pattern9_1,
6386                                     imm: pattern9_2,
6387                                 } = &pattern8_0
6388                                 {
6389                                     if let &Opcode::Extractlane = pattern9_0 {
6390                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6391                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6392                                         // Rule at src/isa/aarch64/lower.isle line 487.
6393                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6394                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6395                                         let expr2_0 = constructor_mov_from_vec(
6396                                             ctx,
6397                                             expr0_0,
6398                                             pattern12_0,
6399                                             &expr1_0,
6400                                         )?;
6401                                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6402                                         return Some(expr3_0);
6403                                     }
6404                                 }
6405                             }
6406                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6407                             if let Some(pattern8_0) = C::sinkable_atomic_load(ctx, pattern5_1) {
6408                                 // Rule at src/isa/aarch64/lower.isle line 494.
6409                                 let expr0_0 = C::sink_atomic_load(ctx, &pattern8_0);
6410                                 let expr1_0 = constructor_load_acquire(ctx, pattern7_0, expr0_0)?;
6411                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6412                                 return Some(expr2_0);
6413                             }
6414                             // Rule at src/isa/aarch64/lower.isle line 482.
6415                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6416                             let expr1_0: bool = false;
6417                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6418                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6419                             let expr4_0 =
6420                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6421                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6422                             return Some(expr5_0);
6423                         }
6424                         &Opcode::Sextend => {
6425                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6426                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6427                                 if let &InstructionData::BinaryImm8 {
6428                                     opcode: ref pattern9_0,
6429                                     arg: pattern9_1,
6430                                     imm: pattern9_2,
6431                                 } = &pattern8_0
6432                                 {
6433                                     if let &Opcode::Extractlane = pattern9_0 {
6434                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6435                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6436                                         // Rule at src/isa/aarch64/lower.isle line 519.
6437                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6438                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6439                                         let expr2_0 = constructor_size_from_ty(ctx, pattern3_0)?;
6440                                         let expr3_0 = constructor_mov_from_vec_signed(
6441                                             ctx,
6442                                             expr0_0,
6443                                             pattern12_0,
6444                                             &expr1_0,
6445                                             &expr2_0,
6446                                         )?;
6447                                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6448                                         return Some(expr4_0);
6449                                     }
6450                                 }
6451                             }
6452                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6453                             // Rule at src/isa/aarch64/lower.isle line 514.
6454                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6455                             let expr1_0: bool = true;
6456                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6457                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6458                             let expr4_0 =
6459                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6460                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6461                             return Some(expr5_0);
6462                         }
6463                         _ => {}
6464                     }
6465                 }
6466                 _ => {}
6467             }
6468         }
6469         if let Some(pattern3_0) = C::ty_vec128(ctx, pattern2_0) {
6470             let pattern4_0 = C::inst_data(ctx, pattern0_0);
6471             match &pattern4_0 {
6472                 &InstructionData::Binary {
6473                     opcode: ref pattern5_0,
6474                     args: ref pattern5_1,
6475                 } => {
6476                     match pattern5_0 {
6477                         &Opcode::UaddSat => {
6478                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6479                             // Rule at src/isa/aarch64/lower.isle line 152.
6480                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6481                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6482                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6483                             let expr3_0 = constructor_uqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6484                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6485                             return Some(expr4_0);
6486                         }
6487                         &Opcode::SaddSat => {
6488                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6489                             // Rule at src/isa/aarch64/lower.isle line 157.
6490                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6491                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6492                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6493                             let expr3_0 = constructor_sqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6494                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6495                             return Some(expr4_0);
6496                         }
6497                         &Opcode::UsubSat => {
6498                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6499                             // Rule at src/isa/aarch64/lower.isle line 162.
6500                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6501                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6502                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6503                             let expr3_0 = constructor_uqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6504                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6505                             return Some(expr4_0);
6506                         }
6507                         &Opcode::SsubSat => {
6508                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6509                             // Rule at src/isa/aarch64/lower.isle line 167.
6510                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6511                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6512                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6513                             let expr3_0 = constructor_sqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6514                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6515                             return Some(expr4_0);
6516                         }
6517                         &Opcode::Band => {
6518                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6519                             // Rule at src/isa/aarch64/lower.isle line 597.
6520                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6521                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6522                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6523                             let expr3_0 = constructor_and_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6524                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6525                             return Some(expr4_0);
6526                         }
6527                         &Opcode::Bor => {
6528                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6529                             // Rule at src/isa/aarch64/lower.isle line 610.
6530                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6531                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6532                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6533                             let expr3_0 = constructor_orr_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6534                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6535                             return Some(expr4_0);
6536                         }
6537                         &Opcode::Bxor => {
6538                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6539                             // Rule at src/isa/aarch64/lower.isle line 623.
6540                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6541                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6542                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6543                             let expr3_0 = constructor_eor_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6544                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6545                             return Some(expr4_0);
6546                         }
6547                         &Opcode::BandNot => {
6548                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6549                             // Rule at src/isa/aarch64/lower.isle line 636.
6550                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6551                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6552                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6553                             let expr3_0 = constructor_bic_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6554                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6555                             return Some(expr4_0);
6556                         }
6557                         &Opcode::Ishl => {
6558                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6559                             // Rule at src/isa/aarch64/lower.isle line 700.
6560                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6561                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6562                             let expr2_0 = constructor_vec_dup(ctx, expr1_0, &expr0_0)?;
6563                             let expr3_0 = C::put_in_reg(ctx, pattern7_0);
6564                             let expr4_0 = constructor_sshl(ctx, expr3_0, expr2_0, &expr0_0)?;
6565                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6566                             return Some(expr5_0);
6567                         }
6568                         &Opcode::Ushr => {
6569                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6570                             // Rule at src/isa/aarch64/lower.isle line 758.
6571                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6572                             let expr1_0: Type = I32;
6573                             let expr2_0 = C::zero_reg(ctx);
6574                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6575                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6576                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6577                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6578                             let expr7_0 = constructor_ushl(ctx, expr6_0, expr5_0, &expr0_0)?;
6579                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6580                             return Some(expr8_0);
6581                         }
6582                         &Opcode::Sshr => {
6583                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6584                             // Rule at src/isa/aarch64/lower.isle line 807.
6585                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6586                             let expr1_0: Type = I32;
6587                             let expr2_0 = C::zero_reg(ctx);
6588                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6589                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6590                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6591                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6592                             let expr7_0 = constructor_sshl(ctx, expr6_0, expr5_0, &expr0_0)?;
6593                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6594                             return Some(expr8_0);
6595                         }
6596                         _ => {}
6597                     }
6598                 }
6599                 &InstructionData::Unary {
6600                     opcode: ref pattern5_0,
6601                     arg: pattern5_1,
6602                 } => {
6603                     match pattern5_0 {
6604                         &Opcode::Ineg => {
6605                             // Rule at src/isa/aarch64/lower.isle line 177.
6606                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6607                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6608                             let expr2_0 = constructor_neg(ctx, expr0_0, &expr1_0)?;
6609                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6610                             return Some(expr3_0);
6611                         }
6612                         &Opcode::Bnot => {
6613                             // Rule at src/isa/aarch64/lower.isle line 584.
6614                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6615                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6616                             let expr2_0 = constructor_not(ctx, expr0_0, &expr1_0)?;
6617                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6618                             return Some(expr3_0);
6619                         }
6620                         _ => {}
6621                     }
6622                 }
6623                 _ => {}
6624             }
6625             if let Some(()) = C::not_i64x2(ctx, pattern3_0) {
6626                 let pattern5_0 = C::inst_data(ctx, pattern0_0);
6627                 if let &InstructionData::Binary {
6628                     opcode: ref pattern6_0,
6629                     args: ref pattern6_1,
6630                 } = &pattern5_0
6631                 {
6632                     if let &Opcode::Imul = pattern6_0 {
6633                         let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
6634                         // Rule at src/isa/aarch64/lower.isle line 215.
6635                         let expr0_0 = C::put_in_reg(ctx, pattern8_0);
6636                         let expr1_0 = C::put_in_reg(ctx, pattern8_1);
6637                         let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6638                         let expr3_0 = constructor_mul(ctx, expr0_0, expr1_0, &expr2_0)?;
6639                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6640                         return Some(expr4_0);
6641                     }
6642                 }
6643             }
6644         }
6645     }
6646     return None;
6647 }
6648 
6649 // Generated as internal constructor for term put_nonzero_in_reg_zext64.
6650 pub fn constructor_put_nonzero_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6651     let pattern0_0 = arg0;
6652     let pattern1_0 = C::value_type(ctx, pattern0_0);
6653     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6654         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6655         if let &InstructionData::UnaryImm {
6656             opcode: ref pattern4_0,
6657             imm: pattern4_1,
6658         } = &pattern3_0
6659         {
6660             if let &Opcode::Iconst = pattern4_0 {
6661                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6662                     // Rule at src/isa/aarch64/lower.isle line 400.
6663                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6664                     return Some(expr0_0);
6665                 }
6666             }
6667         }
6668     }
6669     // Rule at src/isa/aarch64/lower.isle line 395.
6670     let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern0_0)?;
6671     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6672     return Some(expr1_0);
6673 }
6674 
6675 // Generated as internal constructor for term put_nonzero_in_reg_sext64.
6676 pub fn constructor_put_nonzero_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6677     let pattern0_0 = arg0;
6678     let pattern1_0 = C::value_type(ctx, pattern0_0);
6679     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6680         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6681         if let &InstructionData::UnaryImm {
6682             opcode: ref pattern4_0,
6683             imm: pattern4_1,
6684         } = &pattern3_0
6685         {
6686             if let &Opcode::Iconst = pattern4_0 {
6687                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6688                     // Rule at src/isa/aarch64/lower.isle line 446.
6689                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6690                     return Some(expr0_0);
6691                 }
6692             }
6693         }
6694     }
6695     // Rule at src/isa/aarch64/lower.isle line 441.
6696     let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern0_0)?;
6697     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6698     return Some(expr1_0);
6699 }
6700 
6701 // Generated as internal constructor for term lower_shl128.
6702 pub fn constructor_lower_shl128<C: Context>(
6703     ctx: &mut C,
6704     arg0: ValueRegs,
6705     arg1: Reg,
6706 ) -> Option<ValueRegs> {
6707     let pattern0_0 = arg0;
6708     let pattern1_0 = arg1;
6709     // Rule at src/isa/aarch64/lower.isle line 683.
6710     let expr0_0: usize = 0;
6711     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6712     let expr2_0: usize = 1;
6713     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6714     let expr4_0: Type = I64;
6715     let expr5_0 = constructor_lsl(ctx, expr4_0, expr1_0, pattern1_0)?;
6716     let expr6_0: Type = I64;
6717     let expr7_0 = constructor_lsl(ctx, expr6_0, expr3_0, pattern1_0)?;
6718     let expr8_0: Type = I32;
6719     let expr9_0 = C::zero_reg(ctx);
6720     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6721     let expr11_0: Type = I64;
6722     let expr12_0: Type = I64;
6723     let expr13_0: u8 = 1;
6724     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6725     let expr15_0 = constructor_lsr_imm(ctx, expr12_0, expr1_0, expr14_0)?;
6726     let expr16_0 = constructor_lsr(ctx, expr11_0, expr15_0, expr10_0)?;
6727     let expr17_0: Type = I64;
6728     let expr18_0 = constructor_orr(ctx, expr17_0, expr7_0, expr16_0)?;
6729     let expr19_0: Type = I64;
6730     let expr20_0: Type = I64;
6731     let expr21_0: u64 = 64;
6732     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6733     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6734     let expr24_0 = Cond::Ne;
6735     let expr25_0 = C::zero_reg(ctx);
6736     let expr26_0 = constructor_csel(ctx, &expr24_0, expr25_0, expr5_0)?;
6737     let expr27_0 = Cond::Ne;
6738     let expr28_0 = constructor_csel(ctx, &expr27_0, expr5_0, expr18_0)?;
6739     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr26_0, &expr28_0)?;
6740     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6741     return Some(expr30_0);
6742 }
6743 
6744 // Generated as internal constructor for term do_shift.
6745 pub fn constructor_do_shift<C: Context>(
6746     ctx: &mut C,
6747     arg0: &ALUOp,
6748     arg1: Type,
6749     arg2: Reg,
6750     arg3: Value,
6751 ) -> Option<Reg> {
6752     let pattern0_0 = arg0;
6753     let pattern1_0 = arg1;
6754     let pattern2_0 = arg2;
6755     let pattern3_0 = arg3;
6756     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
6757         let pattern5_0 = C::inst_data(ctx, pattern4_0);
6758         if let &InstructionData::UnaryImm {
6759             opcode: ref pattern6_0,
6760             imm: pattern6_1,
6761         } = &pattern5_0
6762         {
6763             if let &Opcode::Iconst = pattern6_0 {
6764                 let closure8 = || {
6765                     return Some(pattern1_0);
6766                 };
6767                 if let Some(pattern8_0) = closure8() {
6768                     if let Some(pattern9_0) = C::imm_shift_from_imm64(ctx, pattern6_1, pattern8_0) {
6769                         // Rule at src/isa/aarch64/lower.isle line 740.
6770                         let expr0_0 = constructor_alu_rr_imm_shift(
6771                             ctx, pattern0_0, pattern1_0, pattern2_0, pattern9_0,
6772                         )?;
6773                         return Some(expr0_0);
6774                     }
6775                 }
6776             }
6777         }
6778     }
6779     let pattern0_0 = arg0;
6780     let pattern1_0 = arg1;
6781     if pattern1_0 == I32 {
6782         let pattern3_0 = arg2;
6783         let pattern4_0 = arg3;
6784         // Rule at src/isa/aarch64/lower.isle line 731.
6785         let expr0_0: Type = I32;
6786         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6787         let expr2_0: usize = 0;
6788         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6789         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6790         return Some(expr4_0);
6791     }
6792     if pattern1_0 == I64 {
6793         let pattern3_0 = arg2;
6794         let pattern4_0 = arg3;
6795         // Rule at src/isa/aarch64/lower.isle line 732.
6796         let expr0_0: Type = I64;
6797         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6798         let expr2_0: usize = 0;
6799         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6800         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6801         return Some(expr4_0);
6802     }
6803     if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
6804         let pattern3_0 = arg2;
6805         let pattern4_0 = arg3;
6806         // Rule at src/isa/aarch64/lower.isle line 722.
6807         let expr0_0 = C::put_in_regs(ctx, pattern4_0);
6808         let expr1_0: usize = 0;
6809         let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
6810         let expr3_0: Type = I32;
6811         let expr4_0 = C::shift_mask(ctx, pattern2_0);
6812         let expr5_0 = constructor_and_imm(ctx, expr3_0, expr2_0, expr4_0)?;
6813         let expr6_0: Type = I32;
6814         let expr7_0 = constructor_alu_rrr(ctx, pattern0_0, expr6_0, pattern3_0, expr5_0)?;
6815         return Some(expr7_0);
6816     }
6817     return None;
6818 }
6819 
6820 // Generated as internal constructor for term lower_ushr128.
6821 pub fn constructor_lower_ushr128<C: Context>(
6822     ctx: &mut C,
6823     arg0: ValueRegs,
6824     arg1: Reg,
6825 ) -> Option<ValueRegs> {
6826     let pattern0_0 = arg0;
6827     let pattern1_0 = arg1;
6828     // Rule at src/isa/aarch64/lower.isle line 773.
6829     let expr0_0: usize = 0;
6830     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6831     let expr2_0: usize = 1;
6832     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6833     let expr4_0: Type = I64;
6834     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6835     let expr6_0: Type = I64;
6836     let expr7_0 = constructor_lsr(ctx, expr6_0, expr3_0, pattern1_0)?;
6837     let expr8_0: Type = I32;
6838     let expr9_0 = C::zero_reg(ctx);
6839     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6840     let expr11_0: Type = I64;
6841     let expr12_0: Type = I64;
6842     let expr13_0: u8 = 1;
6843     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6844     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6845     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6846     let expr17_0: Type = I64;
6847     let expr18_0 = constructor_orr(ctx, expr17_0, expr5_0, expr16_0)?;
6848     let expr19_0: Type = I64;
6849     let expr20_0: Type = I64;
6850     let expr21_0: u64 = 64;
6851     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6852     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6853     let expr24_0 = Cond::Ne;
6854     let expr25_0 = constructor_csel(ctx, &expr24_0, expr7_0, expr18_0)?;
6855     let expr26_0 = Cond::Ne;
6856     let expr27_0 = C::zero_reg(ctx);
6857     let expr28_0 = constructor_csel(ctx, &expr26_0, expr27_0, expr7_0)?;
6858     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr25_0, &expr28_0)?;
6859     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6860     return Some(expr30_0);
6861 }
6862 
6863 // Generated as internal constructor for term lower_sshr128.
6864 pub fn constructor_lower_sshr128<C: Context>(
6865     ctx: &mut C,
6866     arg0: ValueRegs,
6867     arg1: Reg,
6868 ) -> Option<ValueRegs> {
6869     let pattern0_0 = arg0;
6870     let pattern1_0 = arg1;
6871     // Rule at src/isa/aarch64/lower.isle line 823.
6872     let expr0_0: usize = 0;
6873     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6874     let expr2_0: usize = 1;
6875     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6876     let expr4_0: Type = I64;
6877     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6878     let expr6_0: Type = I64;
6879     let expr7_0 = constructor_asr(ctx, expr6_0, expr3_0, pattern1_0)?;
6880     let expr8_0: Type = I32;
6881     let expr9_0 = C::zero_reg(ctx);
6882     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6883     let expr11_0: Type = I64;
6884     let expr12_0: Type = I64;
6885     let expr13_0: u8 = 1;
6886     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6887     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6888     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6889     let expr17_0: Type = I64;
6890     let expr18_0: u8 = 63;
6891     let expr19_0 = C::imm_shift_from_u8(ctx, expr18_0);
6892     let expr20_0 = constructor_asr_imm(ctx, expr17_0, expr3_0, expr19_0)?;
6893     let expr21_0: Type = I64;
6894     let expr22_0 = constructor_orr(ctx, expr21_0, expr5_0, expr16_0)?;
6895     let expr23_0: Type = I64;
6896     let expr24_0: Type = I64;
6897     let expr25_0: u64 = 64;
6898     let expr26_0 = C::u64_into_imm_logic(ctx, expr24_0, expr25_0);
6899     let expr27_0 = constructor_tst_imm(ctx, expr23_0, pattern1_0, expr26_0)?;
6900     let expr28_0 = Cond::Ne;
6901     let expr29_0 = constructor_csel(ctx, &expr28_0, expr7_0, expr22_0)?;
6902     let expr30_0 = Cond::Ne;
6903     let expr31_0 = constructor_csel(ctx, &expr30_0, expr20_0, expr7_0)?;
6904     let expr32_0 = constructor_consumes_flags_concat(ctx, &expr29_0, &expr31_0)?;
6905     let expr33_0 = constructor_with_flags(ctx, &expr27_0, &expr32_0)?;
6906     return Some(expr33_0);
6907 }
6908 
6909 // Generated as internal constructor for term small_rotr.
6910 pub fn constructor_small_rotr<C: Context>(
6911     ctx: &mut C,
6912     arg0: Type,
6913     arg1: Reg,
6914     arg2: Reg,
6915 ) -> Option<Reg> {
6916     let pattern0_0 = arg0;
6917     let pattern1_0 = arg1;
6918     let pattern2_0 = arg2;
6919     // Rule at src/isa/aarch64/lower.isle line 933.
6920     let expr0_0: Type = I32;
6921     let expr1_0 = C::rotr_mask(ctx, pattern0_0);
6922     let expr2_0 = constructor_and_imm(ctx, expr0_0, pattern2_0, expr1_0)?;
6923     let expr3_0: Type = I32;
6924     let expr4_0 = C::ty_bits(ctx, pattern0_0);
6925     let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
6926     let expr6_0 = constructor_sub_imm(ctx, expr3_0, expr2_0, expr5_0)?;
6927     let expr7_0: Type = I32;
6928     let expr8_0 = C::zero_reg(ctx);
6929     let expr9_0 = constructor_sub(ctx, expr7_0, expr8_0, expr6_0)?;
6930     let expr10_0: Type = I32;
6931     let expr11_0 = constructor_lsr(ctx, expr10_0, pattern1_0, expr2_0)?;
6932     let expr12_0: Type = I32;
6933     let expr13_0 = constructor_lsl(ctx, expr12_0, pattern1_0, expr9_0)?;
6934     let expr14_0: Type = I32;
6935     let expr15_0 = constructor_orr(ctx, expr14_0, expr13_0, expr11_0)?;
6936     return Some(expr15_0);
6937 }
6938 
6939 // Generated as internal constructor for term small_rotr_imm.
6940 pub fn constructor_small_rotr_imm<C: Context>(
6941     ctx: &mut C,
6942     arg0: Type,
6943     arg1: Reg,
6944     arg2: ImmShift,
6945 ) -> Option<Reg> {
6946     let pattern0_0 = arg0;
6947     let pattern1_0 = arg1;
6948     let pattern2_0 = arg2;
6949     // Rule at src/isa/aarch64/lower.isle line 954.
6950     let expr0_0: Type = I32;
6951     let expr1_0 = constructor_lsr_imm(ctx, expr0_0, pattern1_0, pattern2_0)?;
6952     let expr2_0: Type = I32;
6953     let expr3_0 = C::rotr_opposite_amount(ctx, pattern0_0, pattern2_0);
6954     let expr4_0 = constructor_lsl_imm(ctx, expr2_0, pattern1_0, expr3_0)?;
6955     let expr5_0: Type = I32;
6956     let expr6_0 = constructor_orr(ctx, expr5_0, expr4_0, expr1_0)?;
6957     return Some(expr6_0);
6958 }
6959 
6960 // Generated as internal constructor for term lower_clz128.
6961 pub fn constructor_lower_clz128<C: Context>(ctx: &mut C, arg0: ValueRegs) -> Option<ValueRegs> {
6962     let pattern0_0 = arg0;
6963     // Rule at src/isa/aarch64/lower.isle line 1019.
6964     let expr0_0: Type = I64;
6965     let expr1_0: usize = 1;
6966     let expr2_0 = C::value_regs_get(ctx, pattern0_0, expr1_0);
6967     let expr3_0 = constructor_a64_clz(ctx, expr0_0, expr2_0)?;
6968     let expr4_0: Type = I64;
6969     let expr5_0: usize = 0;
6970     let expr6_0 = C::value_regs_get(ctx, pattern0_0, expr5_0);
6971     let expr7_0 = constructor_a64_clz(ctx, expr4_0, expr6_0)?;
6972     let expr8_0: Type = I64;
6973     let expr9_0: u8 = 6;
6974     let expr10_0 = C::imm_shift_from_u8(ctx, expr9_0);
6975     let expr11_0 = constructor_lsr_imm(ctx, expr8_0, expr3_0, expr10_0)?;
6976     let expr12_0: Type = I64;
6977     let expr13_0 = constructor_madd(ctx, expr12_0, expr7_0, expr11_0, expr3_0)?;
6978     let expr14_0: Type = I64;
6979     let expr15_0: u64 = 0;
6980     let expr16_0 = constructor_imm(ctx, expr14_0, expr15_0)?;
6981     let expr17_0 = C::value_regs(ctx, expr13_0, expr16_0);
6982     return Some(expr17_0);
6983 }
6984