1 // GENERATED BY ISLE. DO NOT EDIT!
2 //
3 // Generated automatically from the instruction-selection DSL code in:
4 // - src/clif.isle
5 // - src/prelude.isle
6 // - src/isa/aarch64/inst.isle
7 // - src/isa/aarch64/lower.isle
8 
9 #![allow(dead_code, unreachable_code, unreachable_patterns)]
10 #![allow(unused_imports, unused_variables, non_snake_case)]
11 #![allow(irrefutable_let_patterns)]
12 
13 use super::*; // Pulls in all external types.
14 
15 /// Context during lowering: an implementation of this trait
16 /// must be provided with all external constructors and extractors.
17 /// A mutable borrow is passed along through all lowering logic.
18 pub trait Context {
19     fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
20     fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
21     fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
22     fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
23     fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
24     fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
25     fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
26     fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
27     fn value_regs_invalid(&mut self) -> ValueRegs;
28     fn output_none(&mut self) -> InstOutput;
29     fn output(&mut self, arg0: ValueRegs) -> InstOutput;
30     fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput;
31     fn output_builder_new(&mut self) -> InstOutputBuilder;
32     fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit;
33     fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput;
34     fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
35     fn invalid_reg(&mut self) -> Reg;
36     fn put_in_reg(&mut self, arg0: Value) -> Reg;
37     fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
38     fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
39     fn u8_as_u64(&mut self, arg0: u8) -> u64;
40     fn u16_as_u64(&mut self, arg0: u16) -> u64;
41     fn u32_as_u64(&mut self, arg0: u32) -> u64;
42     fn i64_as_u64(&mut self, arg0: i64) -> u64;
43     fn u64_add(&mut self, arg0: u64, arg1: u64) -> u64;
44     fn u64_sub(&mut self, arg0: u64, arg1: u64) -> u64;
45     fn u64_and(&mut self, arg0: u64, arg1: u64) -> u64;
46     fn ty_bits(&mut self, arg0: Type) -> u8;
47     fn ty_bits_u16(&mut self, arg0: Type) -> u16;
48     fn ty_bits_u64(&mut self, arg0: Type) -> u64;
49     fn ty_mask(&mut self, arg0: Type) -> u64;
50     fn ty_bytes(&mut self, arg0: Type) -> u16;
51     fn lane_type(&mut self, arg0: Type) -> Type;
52     fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
53     fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
54     fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
55     fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
56     fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
57     fn ty_int_bool_64(&mut self, arg0: Type) -> Option<Type>;
58     fn ty_int_bool_128(&mut self, arg0: Type) -> Option<Type>;
59     fn ty_scalar_float(&mut self, arg0: Type) -> Option<Type>;
60     fn ty_vec128(&mut self, arg0: Type) -> Option<Type>;
61     fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
62     fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
63     fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>;
64     fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>;
65     fn value_slice_len(&mut self, arg0: ValueSlice) -> usize;
66     fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value;
67     fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
68     fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
69     fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
70     fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
71     fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
72     fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
73     fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
74     fn first_result(&mut self, arg0: Inst) -> Option<Value>;
75     fn inst_data(&mut self, arg0: Inst) -> InstructionData;
76     fn value_type(&mut self, arg0: Value) -> Type;
77     fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
78     fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
79     fn emit(&mut self, arg0: &MInst) -> Unit;
80     fn emit_safepoint(&mut self, arg0: &MInst) -> Unit;
81     fn trap_code_division_by_zero(&mut self) -> TrapCode;
82     fn trap_code_integer_overflow(&mut self) -> TrapCode;
83     fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
84     fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
85     fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
86     fn symbol_value_data(
87         &mut self,
88         arg0: GlobalValue,
89     ) -> Option<(ExternalName, RelocDistance, i64)>;
90     fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
91     fn move_wide_const_from_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
92     fn move_wide_const_from_negated_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
93     fn imm_logic_from_u64(&mut self, arg0: u64, arg1: Type) -> Option<ImmLogic>;
94     fn imm_logic_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmLogic>;
95     fn imm_shift_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmShift>;
96     fn imm_shift_from_u8(&mut self, arg0: u8) -> ImmShift;
97     fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12>;
98     fn u8_into_uimm5(&mut self, arg0: u8) -> UImm5;
99     fn u8_into_imm12(&mut self, arg0: u8) -> Imm12;
100     fn u64_into_imm_logic(&mut self, arg0: Type, arg1: u64) -> ImmLogic;
101     fn imm12_from_negated_u64(&mut self, arg0: u64) -> Option<Imm12>;
102     fn lshl_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ShiftOpAndAmt>;
103     fn integral_ty(&mut self, arg0: Type) -> Option<Type>;
104     fn extended_value_from_value(&mut self, arg0: Value) -> Option<ExtendedValue>;
105     fn put_extended_in_reg(&mut self, arg0: &ExtendedValue) -> Reg;
106     fn get_extended_op(&mut self, arg0: &ExtendedValue) -> ExtendOp;
107     fn nzcv(&mut self, arg0: bool, arg1: bool, arg2: bool, arg3: bool) -> NZCV;
108     fn cond_br_zero(&mut self, arg0: Reg) -> CondBrKind;
109     fn cond_br_cond(&mut self, arg0: &Cond) -> CondBrKind;
110     fn zero_reg(&mut self) -> Reg;
111     fn writable_zero_reg(&mut self) -> WritableReg;
112     fn load_constant64_full(&mut self, arg0: u64) -> Reg;
113     fn sinkable_atomic_load(&mut self, arg0: Value) -> Option<SinkableAtomicLoad>;
114     fn sink_atomic_load(&mut self, arg0: &SinkableAtomicLoad) -> Reg;
115     fn zero_value_f32(&mut self, arg0: Ieee32) -> Option<Ieee32>;
116     fn zero_value_f64(&mut self, arg0: Ieee64) -> Option<Ieee64>;
117     fn float_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &FloatCC) -> VecMisc2;
118     fn float_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &FloatCC) -> VecMisc2;
119     fn fcmp_zero_cond(&mut self, arg0: &FloatCC) -> Option<FloatCC>;
120     fn fcmp_zero_cond_not_eq(&mut self, arg0: &FloatCC) -> Option<FloatCC>;
121     fn zero_value(&mut self, arg0: Imm64) -> Option<Imm64>;
122     fn int_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &IntCC) -> VecMisc2;
123     fn int_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &IntCC) -> VecMisc2;
124     fn icmp_zero_cond(&mut self, arg0: &IntCC) -> Option<IntCC>;
125     fn icmp_zero_cond_not_eq(&mut self, arg0: &IntCC) -> Option<IntCC>;
126     fn safe_divisor_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
127     fn shift_mask(&mut self, arg0: Type) -> ImmLogic;
128     fn negate_imm_shift(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
129     fn rotr_mask(&mut self, arg0: Type) -> ImmLogic;
130     fn rotr_opposite_amount(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
131 }
132 
133 /// Internal type SideEffectNoResult: defined at src/prelude.isle line 397.
134 #[derive(Clone, Debug)]
135 pub enum SideEffectNoResult {
136     Inst { inst: MInst },
137 }
138 
139 /// Internal type ProducesFlags: defined at src/prelude.isle line 419.
140 #[derive(Clone, Debug)]
141 pub enum ProducesFlags {
142     ProducesFlagsSideEffect { inst: MInst },
143     ProducesFlagsReturnsReg { inst: MInst, result: Reg },
144     ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg },
145 }
146 
147 /// Internal type ConsumesFlags: defined at src/prelude.isle line 430.
148 #[derive(Clone, Debug)]
149 pub enum ConsumesFlags {
150     ConsumesFlagsReturnsResultWithProducer {
151         inst: MInst,
152         result: Reg,
153     },
154     ConsumesFlagsReturnsReg {
155         inst: MInst,
156         result: Reg,
157     },
158     ConsumesFlagsTwiceReturnsValueRegs {
159         inst1: MInst,
160         inst2: MInst,
161         result: ValueRegs,
162     },
163     ConsumesFlagsFourTimesReturnsValueRegs {
164         inst1: MInst,
165         inst2: MInst,
166         inst3: MInst,
167         inst4: MInst,
168         result: ValueRegs,
169     },
170 }
171 
172 /// Internal type MInst: defined at src/isa/aarch64/inst.isle line 2.
173 #[derive(Clone, Debug)]
174 pub enum MInst {
175     Nop0,
176     Nop4,
177     AluRRR {
178         alu_op: ALUOp,
179         size: OperandSize,
180         rd: WritableReg,
181         rn: Reg,
182         rm: Reg,
183     },
184     AluRRRR {
185         alu_op: ALUOp3,
186         rd: WritableReg,
187         rn: Reg,
188         rm: Reg,
189         ra: Reg,
190     },
191     AluRRImm12 {
192         alu_op: ALUOp,
193         size: OperandSize,
194         rd: WritableReg,
195         rn: Reg,
196         imm12: Imm12,
197     },
198     AluRRImmLogic {
199         alu_op: ALUOp,
200         size: OperandSize,
201         rd: WritableReg,
202         rn: Reg,
203         imml: ImmLogic,
204     },
205     AluRRImmShift {
206         alu_op: ALUOp,
207         size: OperandSize,
208         rd: WritableReg,
209         rn: Reg,
210         immshift: ImmShift,
211     },
212     AluRRRShift {
213         alu_op: ALUOp,
214         size: OperandSize,
215         rd: WritableReg,
216         rn: Reg,
217         rm: Reg,
218         shiftop: ShiftOpAndAmt,
219     },
220     AluRRRExtend {
221         alu_op: ALUOp,
222         size: OperandSize,
223         rd: WritableReg,
224         rn: Reg,
225         rm: Reg,
226         extendop: ExtendOp,
227     },
228     BitRR {
229         op: BitOp,
230         size: OperandSize,
231         rd: WritableReg,
232         rn: Reg,
233     },
234     ULoad8 {
235         rd: WritableReg,
236         mem: AMode,
237         flags: MemFlags,
238     },
239     SLoad8 {
240         rd: WritableReg,
241         mem: AMode,
242         flags: MemFlags,
243     },
244     ULoad16 {
245         rd: WritableReg,
246         mem: AMode,
247         flags: MemFlags,
248     },
249     SLoad16 {
250         rd: WritableReg,
251         mem: AMode,
252         flags: MemFlags,
253     },
254     ULoad32 {
255         rd: WritableReg,
256         mem: AMode,
257         flags: MemFlags,
258     },
259     SLoad32 {
260         rd: WritableReg,
261         mem: AMode,
262         flags: MemFlags,
263     },
264     ULoad64 {
265         rd: WritableReg,
266         mem: AMode,
267         flags: MemFlags,
268     },
269     Store8 {
270         rd: Reg,
271         mem: AMode,
272         flags: MemFlags,
273     },
274     Store16 {
275         rd: Reg,
276         mem: AMode,
277         flags: MemFlags,
278     },
279     Store32 {
280         rd: Reg,
281         mem: AMode,
282         flags: MemFlags,
283     },
284     Store64 {
285         rd: Reg,
286         mem: AMode,
287         flags: MemFlags,
288     },
289     StoreP64 {
290         rt: Reg,
291         rt2: Reg,
292         mem: PairAMode,
293         flags: MemFlags,
294     },
295     LoadP64 {
296         rt: WritableReg,
297         rt2: WritableReg,
298         mem: PairAMode,
299         flags: MemFlags,
300     },
301     Mov64 {
302         rd: WritableReg,
303         rm: Reg,
304     },
305     Mov32 {
306         rd: WritableReg,
307         rm: Reg,
308     },
309     MovZ {
310         rd: WritableReg,
311         imm: MoveWideConst,
312         size: OperandSize,
313     },
314     MovN {
315         rd: WritableReg,
316         imm: MoveWideConst,
317         size: OperandSize,
318     },
319     MovK {
320         rd: WritableReg,
321         imm: MoveWideConst,
322         size: OperandSize,
323     },
324     Extend {
325         rd: WritableReg,
326         rn: Reg,
327         signed: bool,
328         from_bits: u8,
329         to_bits: u8,
330     },
331     CSel {
332         rd: WritableReg,
333         cond: Cond,
334         rn: Reg,
335         rm: Reg,
336     },
337     CSet {
338         rd: WritableReg,
339         cond: Cond,
340     },
341     CSetm {
342         rd: WritableReg,
343         cond: Cond,
344     },
345     CCmpImm {
346         size: OperandSize,
347         rn: Reg,
348         imm: UImm5,
349         nzcv: NZCV,
350         cond: Cond,
351     },
352     AtomicRMWLoop {
353         ty: Type,
354         op: AtomicRmwOp,
355     },
356     AtomicRMW {
357         op: AtomicRMWOp,
358         rs: Reg,
359         rt: WritableReg,
360         rn: Reg,
361         ty: Type,
362     },
363     AtomicCAS {
364         rs: WritableReg,
365         rt: Reg,
366         rn: Reg,
367         ty: Type,
368     },
369     AtomicCASLoop {
370         ty: Type,
371     },
372     LoadAcquire {
373         access_ty: Type,
374         rt: WritableReg,
375         rn: Reg,
376     },
377     StoreRelease {
378         access_ty: Type,
379         rt: Reg,
380         rn: Reg,
381     },
382     Fence,
383     FpuMove64 {
384         rd: WritableReg,
385         rn: Reg,
386     },
387     FpuMove128 {
388         rd: WritableReg,
389         rn: Reg,
390     },
391     FpuMoveFromVec {
392         rd: WritableReg,
393         rn: Reg,
394         idx: u8,
395         size: VectorSize,
396     },
397     FpuExtend {
398         rd: WritableReg,
399         rn: Reg,
400         size: ScalarSize,
401     },
402     FpuRR {
403         fpu_op: FPUOp1,
404         rd: WritableReg,
405         rn: Reg,
406     },
407     FpuRRR {
408         fpu_op: FPUOp2,
409         rd: WritableReg,
410         rn: Reg,
411         rm: Reg,
412     },
413     FpuRRI {
414         fpu_op: FPUOpRI,
415         rd: WritableReg,
416         rn: Reg,
417     },
418     FpuRRRR {
419         fpu_op: FPUOp3,
420         rd: WritableReg,
421         rn: Reg,
422         rm: Reg,
423         ra: Reg,
424     },
425     FpuCmp32 {
426         rn: Reg,
427         rm: Reg,
428     },
429     FpuCmp64 {
430         rn: Reg,
431         rm: Reg,
432     },
433     FpuLoad32 {
434         rd: WritableReg,
435         mem: AMode,
436         flags: MemFlags,
437     },
438     FpuStore32 {
439         rd: Reg,
440         mem: AMode,
441         flags: MemFlags,
442     },
443     FpuLoad64 {
444         rd: WritableReg,
445         mem: AMode,
446         flags: MemFlags,
447     },
448     FpuStore64 {
449         rd: Reg,
450         mem: AMode,
451         flags: MemFlags,
452     },
453     FpuLoad128 {
454         rd: WritableReg,
455         mem: AMode,
456         flags: MemFlags,
457     },
458     FpuStore128 {
459         rd: Reg,
460         mem: AMode,
461         flags: MemFlags,
462     },
463     FpuLoadP64 {
464         rt: WritableReg,
465         rt2: WritableReg,
466         mem: PairAMode,
467         flags: MemFlags,
468     },
469     FpuStoreP64 {
470         rt: Reg,
471         rt2: Reg,
472         mem: PairAMode,
473         flags: MemFlags,
474     },
475     FpuLoadP128 {
476         rt: WritableReg,
477         rt2: WritableReg,
478         mem: PairAMode,
479         flags: MemFlags,
480     },
481     FpuStoreP128 {
482         rt: Reg,
483         rt2: Reg,
484         mem: PairAMode,
485         flags: MemFlags,
486     },
487     LoadFpuConst64 {
488         rd: WritableReg,
489         const_data: u64,
490     },
491     LoadFpuConst128 {
492         rd: WritableReg,
493         const_data: u128,
494     },
495     FpuToInt {
496         op: FpuToIntOp,
497         rd: WritableReg,
498         rn: Reg,
499     },
500     IntToFpu {
501         op: IntToFpuOp,
502         rd: WritableReg,
503         rn: Reg,
504     },
505     FpuCSel32 {
506         rd: WritableReg,
507         rn: Reg,
508         rm: Reg,
509         cond: Cond,
510     },
511     FpuCSel64 {
512         rd: WritableReg,
513         rn: Reg,
514         rm: Reg,
515         cond: Cond,
516     },
517     FpuRound {
518         op: FpuRoundMode,
519         rd: WritableReg,
520         rn: Reg,
521     },
522     MovToFpu {
523         rd: WritableReg,
524         rn: Reg,
525         size: ScalarSize,
526     },
527     FpuMoveFPImm {
528         rd: WritableReg,
529         imm: ASIMDFPModImm,
530         size: ScalarSize,
531     },
532     MovToVec {
533         rd: WritableReg,
534         rn: Reg,
535         idx: u8,
536         size: VectorSize,
537     },
538     MovFromVec {
539         rd: WritableReg,
540         rn: Reg,
541         idx: u8,
542         size: VectorSize,
543     },
544     MovFromVecSigned {
545         rd: WritableReg,
546         rn: Reg,
547         idx: u8,
548         size: VectorSize,
549         scalar_size: OperandSize,
550     },
551     VecDup {
552         rd: WritableReg,
553         rn: Reg,
554         size: VectorSize,
555     },
556     VecDupFromFpu {
557         rd: WritableReg,
558         rn: Reg,
559         size: VectorSize,
560     },
561     VecDupFPImm {
562         rd: WritableReg,
563         imm: ASIMDFPModImm,
564         size: VectorSize,
565     },
566     VecDupImm {
567         rd: WritableReg,
568         imm: ASIMDMovModImm,
569         invert: bool,
570         size: VectorSize,
571     },
572     VecExtend {
573         t: VecExtendOp,
574         rd: WritableReg,
575         rn: Reg,
576         high_half: bool,
577     },
578     VecMovElement {
579         rd: WritableReg,
580         rn: Reg,
581         dest_idx: u8,
582         src_idx: u8,
583         size: VectorSize,
584     },
585     VecRRLong {
586         op: VecRRLongOp,
587         rd: WritableReg,
588         rn: Reg,
589         high_half: bool,
590     },
591     VecRRNarrow {
592         op: VecRRNarrowOp,
593         rd: WritableReg,
594         rn: Reg,
595         high_half: bool,
596     },
597     VecRRPair {
598         op: VecPairOp,
599         rd: WritableReg,
600         rn: Reg,
601     },
602     VecRRRLong {
603         alu_op: VecRRRLongOp,
604         rd: WritableReg,
605         rn: Reg,
606         rm: Reg,
607         high_half: bool,
608     },
609     VecRRPairLong {
610         op: VecRRPairLongOp,
611         rd: WritableReg,
612         rn: Reg,
613     },
614     VecRRR {
615         alu_op: VecALUOp,
616         rd: WritableReg,
617         rn: Reg,
618         rm: Reg,
619         size: VectorSize,
620     },
621     VecMisc {
622         op: VecMisc2,
623         rd: WritableReg,
624         rn: Reg,
625         size: VectorSize,
626     },
627     VecLanes {
628         op: VecLanesOp,
629         rd: WritableReg,
630         rn: Reg,
631         size: VectorSize,
632     },
633     VecShiftImm {
634         op: VecShiftImmOp,
635         rd: WritableReg,
636         rn: Reg,
637         size: VectorSize,
638         imm: u8,
639     },
640     VecExtract {
641         rd: WritableReg,
642         rn: Reg,
643         rm: Reg,
644         imm4: u8,
645     },
646     VecTbl {
647         rd: WritableReg,
648         rn: Reg,
649         rm: Reg,
650         is_extension: bool,
651     },
652     VecTbl2 {
653         rd: WritableReg,
654         rn: Reg,
655         rn2: Reg,
656         rm: Reg,
657         is_extension: bool,
658     },
659     VecLoadReplicate {
660         rd: WritableReg,
661         rn: Reg,
662         size: VectorSize,
663     },
664     VecCSel {
665         rd: WritableReg,
666         rn: Reg,
667         rm: Reg,
668         cond: Cond,
669     },
670     MovToNZCV {
671         rn: Reg,
672     },
673     MovFromNZCV {
674         rd: WritableReg,
675     },
676     Call {
677         info: BoxCallInfo,
678     },
679     CallInd {
680         info: BoxCallIndInfo,
681     },
682     Ret,
683     EpiloguePlaceholder,
684     Jump {
685         dest: BranchTarget,
686     },
687     CondBr {
688         taken: BranchTarget,
689         not_taken: BranchTarget,
690         kind: CondBrKind,
691     },
692     TrapIf {
693         kind: CondBrKind,
694         trap_code: TrapCode,
695     },
696     IndirectBr {
697         rn: Reg,
698         targets: VecMachLabel,
699     },
700     Brk,
701     Udf {
702         trap_code: TrapCode,
703     },
704     Adr {
705         rd: WritableReg,
706         off: i32,
707     },
708     Word4 {
709         data: u32,
710     },
711     Word8 {
712         data: u64,
713     },
714     JTSequence {
715         info: BoxJTSequenceInfo,
716         ridx: Reg,
717         rtmp1: WritableReg,
718         rtmp2: WritableReg,
719     },
720     LoadExtName {
721         rd: WritableReg,
722         name: BoxExternalName,
723         offset: i64,
724     },
725     LoadAddr {
726         rd: WritableReg,
727         mem: AMode,
728     },
729     VirtualSPOffsetAdj {
730         offset: i64,
731     },
732     EmitIsland {
733         needed_space: CodeOffset,
734     },
735     ElfTlsGetAddr {
736         symbol: ExternalName,
737     },
738     ValueLabelMarker {
739         reg: Reg,
740         label: ValueLabel,
741     },
742     Unwind {
743         inst: UnwindInst,
744     },
745 }
746 
747 /// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 796.
748 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
749 pub enum ALUOp {
750     Add,
751     Sub,
752     Orr,
753     OrrNot,
754     And,
755     AndS,
756     AndNot,
757     Eor,
758     EorNot,
759     AddS,
760     SubS,
761     SMulH,
762     UMulH,
763     SDiv,
764     UDiv,
765     RotR,
766     Lsr,
767     Asr,
768     Lsl,
769     Adc,
770     AdcS,
771     Sbc,
772     SbcS,
773 }
774 
775 /// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 834.
776 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
777 pub enum ALUOp3 {
778     MAdd32,
779     MAdd64,
780     MSub32,
781     MSub64,
782 }
783 
784 /// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 877.
785 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
786 pub enum BitOp {
787     RBit,
788     Clz,
789     Cls,
790 }
791 
792 /// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 944.
793 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
794 pub enum FPUOp1 {
795     Abs32,
796     Abs64,
797     Neg32,
798     Neg64,
799     Sqrt32,
800     Sqrt64,
801     Cvt32To64,
802     Cvt64To32,
803 }
804 
805 /// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 957.
806 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
807 pub enum FPUOp2 {
808     Add32,
809     Add64,
810     Sub32,
811     Sub64,
812     Mul32,
813     Mul64,
814     Div32,
815     Div64,
816     Max32,
817     Max64,
818     Min32,
819     Min64,
820     Sqadd64,
821     Uqadd64,
822     Sqsub64,
823     Uqsub64,
824 }
825 
826 /// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 982.
827 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
828 pub enum FPUOp3 {
829     MAdd32,
830     MAdd64,
831 }
832 
833 /// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 989.
834 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
835 pub enum FpuToIntOp {
836     F32ToU32,
837     F32ToI32,
838     F32ToU64,
839     F32ToI64,
840     F64ToU32,
841     F64ToI32,
842     F64ToU64,
843     F64ToI64,
844 }
845 
846 /// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 1002.
847 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
848 pub enum IntToFpuOp {
849     U32ToF32,
850     I32ToF32,
851     U32ToF64,
852     I32ToF64,
853     U64ToF32,
854     I64ToF32,
855     U64ToF64,
856     I64ToF64,
857 }
858 
859 /// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 1016.
860 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
861 pub enum FpuRoundMode {
862     Minus32,
863     Minus64,
864     Plus32,
865     Plus64,
866     Zero32,
867     Zero64,
868     Nearest32,
869     Nearest64,
870 }
871 
872 /// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 1029.
873 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
874 pub enum VecExtendOp {
875     Sxtl8,
876     Sxtl16,
877     Sxtl32,
878     Uxtl8,
879     Uxtl16,
880     Uxtl32,
881 }
882 
883 /// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1046.
884 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
885 pub enum VecALUOp {
886     Sqadd,
887     Uqadd,
888     Sqsub,
889     Uqsub,
890     Cmeq,
891     Cmge,
892     Cmgt,
893     Cmhs,
894     Cmhi,
895     Fcmeq,
896     Fcmgt,
897     Fcmge,
898     And,
899     Bic,
900     Orr,
901     Eor,
902     Bsl,
903     Umaxp,
904     Add,
905     Sub,
906     Mul,
907     Sshl,
908     Ushl,
909     Umin,
910     Smin,
911     Umax,
912     Smax,
913     Urhadd,
914     Fadd,
915     Fsub,
916     Fdiv,
917     Fmax,
918     Fmin,
919     Fmul,
920     Addp,
921     Zip1,
922     Sqrdmulh,
923 }
924 
925 /// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1125.
926 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
927 pub enum VecMisc2 {
928     Not,
929     Neg,
930     Abs,
931     Fabs,
932     Fneg,
933     Fsqrt,
934     Rev64,
935     Fcvtzs,
936     Fcvtzu,
937     Scvtf,
938     Ucvtf,
939     Frintn,
940     Frintz,
941     Frintm,
942     Frintp,
943     Cnt,
944     Cmeq0,
945     Cmge0,
946     Cmgt0,
947     Cmle0,
948     Cmlt0,
949     Fcmeq0,
950     Fcmge0,
951     Fcmgt0,
952     Fcmle0,
953     Fcmlt0,
954 }
955 
956 /// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1182.
957 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
958 pub enum VecRRLongOp {
959     Fcvtl16,
960     Fcvtl32,
961     Shll8,
962     Shll16,
963     Shll32,
964 }
965 
966 /// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1197.
967 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
968 pub enum VecRRNarrowOp {
969     Xtn16,
970     Xtn32,
971     Xtn64,
972     Sqxtn16,
973     Sqxtn32,
974     Sqxtn64,
975     Sqxtun16,
976     Sqxtun32,
977     Sqxtun64,
978     Uqxtn16,
979     Uqxtn32,
980     Uqxtn64,
981     Fcvtn32,
982     Fcvtn64,
983 }
984 
985 /// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1229.
986 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
987 pub enum VecRRRLongOp {
988     Smull8,
989     Smull16,
990     Smull32,
991     Umull8,
992     Umull16,
993     Umull32,
994     Umlal8,
995     Umlal16,
996     Umlal32,
997 }
998 
999 /// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1246.
1000 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1001 pub enum VecPairOp {
1002     Addp,
1003 }
1004 
1005 /// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1254.
1006 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1007 pub enum VecRRPairLongOp {
1008     Saddlp8,
1009     Saddlp16,
1010     Uaddlp8,
1011     Uaddlp16,
1012 }
1013 
1014 /// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1265.
1015 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1016 pub enum VecLanesOp {
1017     Addv,
1018     Uminv,
1019 }
1020 
1021 /// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1274.
1022 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1023 pub enum VecShiftImmOp {
1024     Shl,
1025     Ushr,
1026     Sshr,
1027 }
1028 
1029 /// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1285.
1030 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1031 pub enum AtomicRMWOp {
1032     Add,
1033     Clr,
1034     Eor,
1035     Set,
1036     Smax,
1037     Smin,
1038     Umax,
1039     Umin,
1040 }
1041 
1042 // Generated as internal constructor for term output_reg.
1043 pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
1044     let pattern0_0 = arg0;
1045     // Rule at src/prelude.isle line 86.
1046     let expr0_0 = C::value_reg(ctx, pattern0_0);
1047     let expr1_0 = C::output(ctx, expr0_0);
1048     return Some(expr1_0);
1049 }
1050 
1051 // Generated as internal constructor for term output_value.
1052 pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> {
1053     let pattern0_0 = arg0;
1054     // Rule at src/prelude.isle line 90.
1055     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1056     let expr1_0 = C::output(ctx, expr0_0);
1057     return Some(expr1_0);
1058 }
1059 
1060 // Generated as internal constructor for term temp_reg.
1061 pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
1062     let pattern0_0 = arg0;
1063     // Rule at src/prelude.isle line 110.
1064     let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
1065     let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
1066     return Some(expr1_0);
1067 }
1068 
1069 // Generated as internal constructor for term lo_reg.
1070 pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
1071     let pattern0_0 = arg0;
1072     // Rule at src/prelude.isle line 145.
1073     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1074     let expr1_0: usize = 0;
1075     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1076     return Some(expr2_0);
1077 }
1078 
1079 // Generated as internal constructor for term side_effect.
1080 pub fn constructor_side_effect<C: Context>(
1081     ctx: &mut C,
1082     arg0: &SideEffectNoResult,
1083 ) -> Option<InstOutput> {
1084     let pattern0_0 = arg0;
1085     if let &SideEffectNoResult::Inst {
1086         inst: ref pattern1_0,
1087     } = pattern0_0
1088     {
1089         // Rule at src/prelude.isle line 402.
1090         let expr0_0 = C::emit(ctx, pattern1_0);
1091         let expr1_0 = C::output_none(ctx);
1092         return Some(expr1_0);
1093     }
1094     return None;
1095 }
1096 
1097 // Generated as internal constructor for term safepoint.
1098 pub fn constructor_safepoint<C: Context>(
1099     ctx: &mut C,
1100     arg0: &SideEffectNoResult,
1101 ) -> Option<InstOutput> {
1102     let pattern0_0 = arg0;
1103     if let &SideEffectNoResult::Inst {
1104         inst: ref pattern1_0,
1105     } = pattern0_0
1106     {
1107         // Rule at src/prelude.isle line 408.
1108         let expr0_0 = C::emit_safepoint(ctx, pattern1_0);
1109         let expr1_0 = C::output_none(ctx);
1110         return Some(expr1_0);
1111     }
1112     return None;
1113 }
1114 
1115 // Generated as internal constructor for term produces_flags_get_reg.
1116 pub fn constructor_produces_flags_get_reg<C: Context>(
1117     ctx: &mut C,
1118     arg0: &ProducesFlags,
1119 ) -> Option<Reg> {
1120     let pattern0_0 = arg0;
1121     if let &ProducesFlags::ProducesFlagsReturnsReg {
1122         inst: ref pattern1_0,
1123         result: pattern1_1,
1124     } = pattern0_0
1125     {
1126         // Rule at src/prelude.isle line 446.
1127         return Some(pattern1_1);
1128     }
1129     return None;
1130 }
1131 
1132 // Generated as internal constructor for term produces_flags_ignore.
1133 pub fn constructor_produces_flags_ignore<C: Context>(
1134     ctx: &mut C,
1135     arg0: &ProducesFlags,
1136 ) -> Option<ProducesFlags> {
1137     let pattern0_0 = arg0;
1138     match pattern0_0 {
1139         &ProducesFlags::ProducesFlagsReturnsReg {
1140             inst: ref pattern1_0,
1141             result: pattern1_1,
1142         } => {
1143             // Rule at src/prelude.isle line 451.
1144             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1145                 inst: pattern1_0.clone(),
1146             };
1147             return Some(expr0_0);
1148         }
1149         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1150             inst: ref pattern1_0,
1151             result: pattern1_1,
1152         } => {
1153             // Rule at src/prelude.isle line 453.
1154             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1155                 inst: pattern1_0.clone(),
1156             };
1157             return Some(expr0_0);
1158         }
1159         _ => {}
1160     }
1161     return None;
1162 }
1163 
1164 // Generated as internal constructor for term consumes_flags_concat.
1165 pub fn constructor_consumes_flags_concat<C: Context>(
1166     ctx: &mut C,
1167     arg0: &ConsumesFlags,
1168     arg1: &ConsumesFlags,
1169 ) -> Option<ConsumesFlags> {
1170     let pattern0_0 = arg0;
1171     if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1172         inst: ref pattern1_0,
1173         result: pattern1_1,
1174     } = pattern0_0
1175     {
1176         let pattern2_0 = arg1;
1177         if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1178             inst: ref pattern3_0,
1179             result: pattern3_1,
1180         } = pattern2_0
1181         {
1182             // Rule at src/prelude.isle line 460.
1183             let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1184             let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1185                 inst1: pattern1_0.clone(),
1186                 inst2: pattern3_0.clone(),
1187                 result: expr0_0,
1188             };
1189             return Some(expr1_0);
1190         }
1191     }
1192     return None;
1193 }
1194 
1195 // Generated as internal constructor for term with_flags.
1196 pub fn constructor_with_flags<C: Context>(
1197     ctx: &mut C,
1198     arg0: &ProducesFlags,
1199     arg1: &ConsumesFlags,
1200 ) -> Option<ValueRegs> {
1201     let pattern0_0 = arg0;
1202     match pattern0_0 {
1203         &ProducesFlags::ProducesFlagsSideEffect {
1204             inst: ref pattern1_0,
1205         } => {
1206             let pattern2_0 = arg1;
1207             match pattern2_0 {
1208                 &ConsumesFlags::ConsumesFlagsReturnsReg {
1209                     inst: ref pattern3_0,
1210                     result: pattern3_1,
1211                 } => {
1212                     // Rule at src/prelude.isle line 485.
1213                     let expr0_0 = C::emit(ctx, pattern1_0);
1214                     let expr1_0 = C::emit(ctx, pattern3_0);
1215                     let expr2_0 = C::value_reg(ctx, pattern3_1);
1216                     return Some(expr2_0);
1217                 }
1218                 &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1219                     inst1: ref pattern3_0,
1220                     inst2: ref pattern3_1,
1221                     result: pattern3_2,
1222                 } => {
1223                     // Rule at src/prelude.isle line 491.
1224                     let expr0_0 = C::emit(ctx, pattern1_0);
1225                     let expr1_0 = C::emit(ctx, pattern3_0);
1226                     let expr2_0 = C::emit(ctx, pattern3_1);
1227                     return Some(pattern3_2);
1228                 }
1229                 &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs {
1230                     inst1: ref pattern3_0,
1231                     inst2: ref pattern3_1,
1232                     inst3: ref pattern3_2,
1233                     inst4: ref pattern3_3,
1234                     result: pattern3_4,
1235                 } => {
1236                     // Rule at src/prelude.isle line 503.
1237                     let expr0_0 = C::emit(ctx, pattern1_0);
1238                     let expr1_0 = C::emit(ctx, pattern3_0);
1239                     let expr2_0 = C::emit(ctx, pattern3_1);
1240                     let expr3_0 = C::emit(ctx, pattern3_2);
1241                     let expr4_0 = C::emit(ctx, pattern3_3);
1242                     return Some(pattern3_4);
1243                 }
1244                 _ => {}
1245             }
1246         }
1247         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1248             inst: ref pattern1_0,
1249             result: pattern1_1,
1250         } => {
1251             let pattern2_0 = arg1;
1252             if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1253                 inst: ref pattern3_0,
1254                 result: pattern3_1,
1255             } = pattern2_0
1256             {
1257                 // Rule at src/prelude.isle line 479.
1258                 let expr0_0 = C::emit(ctx, pattern1_0);
1259                 let expr1_0 = C::emit(ctx, pattern3_0);
1260                 let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1261                 return Some(expr2_0);
1262             }
1263         }
1264         _ => {}
1265     }
1266     return None;
1267 }
1268 
1269 // Generated as internal constructor for term with_flags_reg.
1270 pub fn constructor_with_flags_reg<C: Context>(
1271     ctx: &mut C,
1272     arg0: &ProducesFlags,
1273     arg1: &ConsumesFlags,
1274 ) -> Option<Reg> {
1275     let pattern0_0 = arg0;
1276     let pattern1_0 = arg1;
1277     // Rule at src/prelude.isle line 520.
1278     let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?;
1279     let expr1_0: usize = 0;
1280     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1281     return Some(expr2_0);
1282 }
1283 
1284 // Generated as internal constructor for term operand_size.
1285 pub fn constructor_operand_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
1286     let pattern0_0 = arg0;
1287     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
1288         // Rule at src/isa/aarch64/inst.isle line 895.
1289         let expr0_0 = OperandSize::Size32;
1290         return Some(expr0_0);
1291     }
1292     if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
1293         // Rule at src/isa/aarch64/inst.isle line 896.
1294         let expr0_0 = OperandSize::Size64;
1295         return Some(expr0_0);
1296     }
1297     return None;
1298 }
1299 
1300 // Generated as internal constructor for term vector_size.
1301 pub fn constructor_vector_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<VectorSize> {
1302     let pattern0_0 = arg0;
1303     if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
1304         if pattern1_0 == 8 {
1305             if pattern1_1 == 16 {
1306                 // Rule at src/isa/aarch64/inst.isle line 938.
1307                 let expr0_0 = VectorSize::Size8x16;
1308                 return Some(expr0_0);
1309             }
1310         }
1311         if pattern1_0 == 16 {
1312             if pattern1_1 == 8 {
1313                 // Rule at src/isa/aarch64/inst.isle line 939.
1314                 let expr0_0 = VectorSize::Size16x8;
1315                 return Some(expr0_0);
1316             }
1317         }
1318         if pattern1_0 == 32 {
1319             if pattern1_1 == 4 {
1320                 // Rule at src/isa/aarch64/inst.isle line 940.
1321                 let expr0_0 = VectorSize::Size32x4;
1322                 return Some(expr0_0);
1323             }
1324         }
1325         if pattern1_0 == 64 {
1326             if pattern1_1 == 2 {
1327                 // Rule at src/isa/aarch64/inst.isle line 941.
1328                 let expr0_0 = VectorSize::Size64x2;
1329                 return Some(expr0_0);
1330             }
1331         }
1332     }
1333     return None;
1334 }
1335 
1336 // Generated as internal constructor for term movz.
1337 pub fn constructor_movz<C: Context>(
1338     ctx: &mut C,
1339     arg0: MoveWideConst,
1340     arg1: &OperandSize,
1341 ) -> Option<Reg> {
1342     let pattern0_0 = arg0;
1343     let pattern1_0 = arg1;
1344     // Rule at src/isa/aarch64/inst.isle line 1381.
1345     let expr0_0: Type = I64;
1346     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1347     let expr2_0 = MInst::MovZ {
1348         rd: expr1_0,
1349         imm: pattern0_0,
1350         size: pattern1_0.clone(),
1351     };
1352     let expr3_0 = C::emit(ctx, &expr2_0);
1353     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1354     return Some(expr4_0);
1355 }
1356 
1357 // Generated as internal constructor for term movn.
1358 pub fn constructor_movn<C: Context>(
1359     ctx: &mut C,
1360     arg0: MoveWideConst,
1361     arg1: &OperandSize,
1362 ) -> Option<Reg> {
1363     let pattern0_0 = arg0;
1364     let pattern1_0 = arg1;
1365     // Rule at src/isa/aarch64/inst.isle line 1388.
1366     let expr0_0: Type = I64;
1367     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1368     let expr2_0 = MInst::MovN {
1369         rd: expr1_0,
1370         imm: pattern0_0,
1371         size: pattern1_0.clone(),
1372     };
1373     let expr3_0 = C::emit(ctx, &expr2_0);
1374     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1375     return Some(expr4_0);
1376 }
1377 
1378 // Generated as internal constructor for term alu_rr_imm_logic.
1379 pub fn constructor_alu_rr_imm_logic<C: Context>(
1380     ctx: &mut C,
1381     arg0: &ALUOp,
1382     arg1: Type,
1383     arg2: Reg,
1384     arg3: ImmLogic,
1385 ) -> Option<Reg> {
1386     let pattern0_0 = arg0;
1387     let pattern1_0 = arg1;
1388     let pattern2_0 = arg2;
1389     let pattern3_0 = arg3;
1390     // Rule at src/isa/aarch64/inst.isle line 1395.
1391     let expr0_0: Type = I64;
1392     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1393     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1394     let expr3_0 = MInst::AluRRImmLogic {
1395         alu_op: pattern0_0.clone(),
1396         size: expr2_0,
1397         rd: expr1_0,
1398         rn: pattern2_0,
1399         imml: pattern3_0,
1400     };
1401     let expr4_0 = C::emit(ctx, &expr3_0);
1402     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1403     return Some(expr5_0);
1404 }
1405 
1406 // Generated as internal constructor for term alu_rr_imm_shift.
1407 pub fn constructor_alu_rr_imm_shift<C: Context>(
1408     ctx: &mut C,
1409     arg0: &ALUOp,
1410     arg1: Type,
1411     arg2: Reg,
1412     arg3: ImmShift,
1413 ) -> Option<Reg> {
1414     let pattern0_0 = arg0;
1415     let pattern1_0 = arg1;
1416     let pattern2_0 = arg2;
1417     let pattern3_0 = arg3;
1418     // Rule at src/isa/aarch64/inst.isle line 1402.
1419     let expr0_0: Type = I64;
1420     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1421     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1422     let expr3_0 = MInst::AluRRImmShift {
1423         alu_op: pattern0_0.clone(),
1424         size: expr2_0,
1425         rd: expr1_0,
1426         rn: pattern2_0,
1427         immshift: pattern3_0,
1428     };
1429     let expr4_0 = C::emit(ctx, &expr3_0);
1430     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1431     return Some(expr5_0);
1432 }
1433 
1434 // Generated as internal constructor for term alu_rrr.
1435 pub fn constructor_alu_rrr<C: Context>(
1436     ctx: &mut C,
1437     arg0: &ALUOp,
1438     arg1: Type,
1439     arg2: Reg,
1440     arg3: Reg,
1441 ) -> Option<Reg> {
1442     let pattern0_0 = arg0;
1443     let pattern1_0 = arg1;
1444     let pattern2_0 = arg2;
1445     let pattern3_0 = arg3;
1446     // Rule at src/isa/aarch64/inst.isle line 1409.
1447     let expr0_0: Type = I64;
1448     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1449     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1450     let expr3_0 = MInst::AluRRR {
1451         alu_op: pattern0_0.clone(),
1452         size: expr2_0,
1453         rd: expr1_0,
1454         rn: pattern2_0,
1455         rm: pattern3_0,
1456     };
1457     let expr4_0 = C::emit(ctx, &expr3_0);
1458     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1459     return Some(expr5_0);
1460 }
1461 
1462 // Generated as internal constructor for term vec_rrr.
1463 pub fn constructor_vec_rrr<C: Context>(
1464     ctx: &mut C,
1465     arg0: &VecALUOp,
1466     arg1: Reg,
1467     arg2: Reg,
1468     arg3: &VectorSize,
1469 ) -> Option<Reg> {
1470     let pattern0_0 = arg0;
1471     let pattern1_0 = arg1;
1472     let pattern2_0 = arg2;
1473     let pattern3_0 = arg3;
1474     // Rule at src/isa/aarch64/inst.isle line 1416.
1475     let expr0_0: Type = I8X16;
1476     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1477     let expr2_0 = MInst::VecRRR {
1478         alu_op: pattern0_0.clone(),
1479         rd: expr1_0,
1480         rn: pattern1_0,
1481         rm: pattern2_0,
1482         size: pattern3_0.clone(),
1483     };
1484     let expr3_0 = C::emit(ctx, &expr2_0);
1485     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1486     return Some(expr4_0);
1487 }
1488 
1489 // Generated as internal constructor for term vec_lanes.
1490 pub fn constructor_vec_lanes<C: Context>(
1491     ctx: &mut C,
1492     arg0: &VecLanesOp,
1493     arg1: Reg,
1494     arg2: &VectorSize,
1495 ) -> Option<Reg> {
1496     let pattern0_0 = arg0;
1497     let pattern1_0 = arg1;
1498     let pattern2_0 = arg2;
1499     // Rule at src/isa/aarch64/inst.isle line 1423.
1500     let expr0_0: Type = I8X16;
1501     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1502     let expr2_0 = MInst::VecLanes {
1503         op: pattern0_0.clone(),
1504         rd: expr1_0,
1505         rn: pattern1_0,
1506         size: pattern2_0.clone(),
1507     };
1508     let expr3_0 = C::emit(ctx, &expr2_0);
1509     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1510     return Some(expr4_0);
1511 }
1512 
1513 // Generated as internal constructor for term vec_dup.
1514 pub fn constructor_vec_dup<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
1515     let pattern0_0 = arg0;
1516     let pattern1_0 = arg1;
1517     // Rule at src/isa/aarch64/inst.isle line 1430.
1518     let expr0_0: Type = I8X16;
1519     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1520     let expr2_0 = MInst::VecDup {
1521         rd: expr1_0,
1522         rn: pattern0_0,
1523         size: pattern1_0.clone(),
1524     };
1525     let expr3_0 = C::emit(ctx, &expr2_0);
1526     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1527     return Some(expr4_0);
1528 }
1529 
1530 // Generated as internal constructor for term alu_rr_imm12.
1531 pub fn constructor_alu_rr_imm12<C: Context>(
1532     ctx: &mut C,
1533     arg0: &ALUOp,
1534     arg1: Type,
1535     arg2: Reg,
1536     arg3: Imm12,
1537 ) -> Option<Reg> {
1538     let pattern0_0 = arg0;
1539     let pattern1_0 = arg1;
1540     let pattern2_0 = arg2;
1541     let pattern3_0 = arg3;
1542     // Rule at src/isa/aarch64/inst.isle line 1437.
1543     let expr0_0: Type = I64;
1544     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1545     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1546     let expr3_0 = MInst::AluRRImm12 {
1547         alu_op: pattern0_0.clone(),
1548         size: expr2_0,
1549         rd: expr1_0,
1550         rn: pattern2_0,
1551         imm12: pattern3_0,
1552     };
1553     let expr4_0 = C::emit(ctx, &expr3_0);
1554     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1555     return Some(expr5_0);
1556 }
1557 
1558 // Generated as internal constructor for term alu_rrr_shift.
1559 pub fn constructor_alu_rrr_shift<C: Context>(
1560     ctx: &mut C,
1561     arg0: &ALUOp,
1562     arg1: Type,
1563     arg2: Reg,
1564     arg3: Reg,
1565     arg4: ShiftOpAndAmt,
1566 ) -> Option<Reg> {
1567     let pattern0_0 = arg0;
1568     let pattern1_0 = arg1;
1569     let pattern2_0 = arg2;
1570     let pattern3_0 = arg3;
1571     let pattern4_0 = arg4;
1572     // Rule at src/isa/aarch64/inst.isle line 1444.
1573     let expr0_0: Type = I64;
1574     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1575     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1576     let expr3_0 = MInst::AluRRRShift {
1577         alu_op: pattern0_0.clone(),
1578         size: expr2_0,
1579         rd: expr1_0,
1580         rn: pattern2_0,
1581         rm: pattern3_0,
1582         shiftop: pattern4_0,
1583     };
1584     let expr4_0 = C::emit(ctx, &expr3_0);
1585     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1586     return Some(expr5_0);
1587 }
1588 
1589 // Generated as internal constructor for term alu_rrr_extend.
1590 pub fn constructor_alu_rrr_extend<C: Context>(
1591     ctx: &mut C,
1592     arg0: &ALUOp,
1593     arg1: Type,
1594     arg2: Reg,
1595     arg3: Reg,
1596     arg4: &ExtendOp,
1597 ) -> Option<Reg> {
1598     let pattern0_0 = arg0;
1599     let pattern1_0 = arg1;
1600     let pattern2_0 = arg2;
1601     let pattern3_0 = arg3;
1602     let pattern4_0 = arg4;
1603     // Rule at src/isa/aarch64/inst.isle line 1451.
1604     let expr0_0: Type = I64;
1605     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1606     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1607     let expr3_0 = MInst::AluRRRExtend {
1608         alu_op: pattern0_0.clone(),
1609         size: expr2_0,
1610         rd: expr1_0,
1611         rn: pattern2_0,
1612         rm: pattern3_0,
1613         extendop: pattern4_0.clone(),
1614     };
1615     let expr4_0 = C::emit(ctx, &expr3_0);
1616     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1617     return Some(expr5_0);
1618 }
1619 
1620 // Generated as internal constructor for term alu_rr_extend_reg.
1621 pub fn constructor_alu_rr_extend_reg<C: Context>(
1622     ctx: &mut C,
1623     arg0: &ALUOp,
1624     arg1: Type,
1625     arg2: Reg,
1626     arg3: &ExtendedValue,
1627 ) -> Option<Reg> {
1628     let pattern0_0 = arg0;
1629     let pattern1_0 = arg1;
1630     let pattern2_0 = arg2;
1631     let pattern3_0 = arg3;
1632     // Rule at src/isa/aarch64/inst.isle line 1459.
1633     let expr0_0 = C::put_extended_in_reg(ctx, pattern3_0);
1634     let expr1_0 = C::get_extended_op(ctx, pattern3_0);
1635     let expr2_0 =
1636         constructor_alu_rrr_extend(ctx, pattern0_0, pattern1_0, pattern2_0, expr0_0, &expr1_0)?;
1637     return Some(expr2_0);
1638 }
1639 
1640 // Generated as internal constructor for term alu_rrrr.
1641 pub fn constructor_alu_rrrr<C: Context>(
1642     ctx: &mut C,
1643     arg0: &ALUOp3,
1644     arg1: Reg,
1645     arg2: Reg,
1646     arg3: Reg,
1647 ) -> Option<Reg> {
1648     let pattern0_0 = arg0;
1649     let pattern1_0 = arg1;
1650     let pattern2_0 = arg2;
1651     let pattern3_0 = arg3;
1652     // Rule at src/isa/aarch64/inst.isle line 1466.
1653     let expr0_0: Type = I64;
1654     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1655     let expr2_0 = MInst::AluRRRR {
1656         alu_op: pattern0_0.clone(),
1657         rd: expr1_0,
1658         rn: pattern1_0,
1659         rm: pattern2_0,
1660         ra: pattern3_0,
1661     };
1662     let expr3_0 = C::emit(ctx, &expr2_0);
1663     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1664     return Some(expr4_0);
1665 }
1666 
1667 // Generated as internal constructor for term bit_rr.
1668 pub fn constructor_bit_rr<C: Context>(
1669     ctx: &mut C,
1670     arg0: &BitOp,
1671     arg1: Type,
1672     arg2: Reg,
1673 ) -> Option<Reg> {
1674     let pattern0_0 = arg0;
1675     let pattern1_0 = arg1;
1676     let pattern2_0 = arg2;
1677     // Rule at src/isa/aarch64/inst.isle line 1473.
1678     let expr0_0: Type = I64;
1679     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1680     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1681     let expr3_0 = MInst::BitRR {
1682         op: pattern0_0.clone(),
1683         size: expr2_0,
1684         rd: expr1_0,
1685         rn: pattern2_0,
1686     };
1687     let expr4_0 = C::emit(ctx, &expr3_0);
1688     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1689     return Some(expr5_0);
1690 }
1691 
1692 // Generated as internal constructor for term add_with_flags_paired.
1693 pub fn constructor_add_with_flags_paired<C: Context>(
1694     ctx: &mut C,
1695     arg0: Type,
1696     arg1: Reg,
1697     arg2: Reg,
1698 ) -> Option<ProducesFlags> {
1699     let pattern0_0 = arg0;
1700     let pattern1_0 = arg1;
1701     let pattern2_0 = arg2;
1702     // Rule at src/isa/aarch64/inst.isle line 1480.
1703     let expr0_0: Type = I64;
1704     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1705     let expr2_0 = ALUOp::AddS;
1706     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1707     let expr4_0 = MInst::AluRRR {
1708         alu_op: expr2_0,
1709         size: expr3_0,
1710         rd: expr1_0,
1711         rn: pattern1_0,
1712         rm: pattern2_0,
1713     };
1714     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1715     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1716         inst: expr4_0,
1717         result: expr5_0,
1718     };
1719     return Some(expr6_0);
1720 }
1721 
1722 // Generated as internal constructor for term adc_paired.
1723 pub fn constructor_adc_paired<C: Context>(
1724     ctx: &mut C,
1725     arg0: Type,
1726     arg1: Reg,
1727     arg2: Reg,
1728 ) -> Option<ConsumesFlags> {
1729     let pattern0_0 = arg0;
1730     let pattern1_0 = arg1;
1731     let pattern2_0 = arg2;
1732     // Rule at src/isa/aarch64/inst.isle line 1488.
1733     let expr0_0: Type = I64;
1734     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1735     let expr2_0 = ALUOp::Adc;
1736     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1737     let expr4_0 = MInst::AluRRR {
1738         alu_op: expr2_0,
1739         size: expr3_0,
1740         rd: expr1_0,
1741         rn: pattern1_0,
1742         rm: pattern2_0,
1743     };
1744     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1745     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1746         inst: expr4_0,
1747         result: expr5_0,
1748     };
1749     return Some(expr6_0);
1750 }
1751 
1752 // Generated as internal constructor for term sub_with_flags_paired.
1753 pub fn constructor_sub_with_flags_paired<C: Context>(
1754     ctx: &mut C,
1755     arg0: Type,
1756     arg1: Reg,
1757     arg2: Reg,
1758 ) -> Option<ProducesFlags> {
1759     let pattern0_0 = arg0;
1760     let pattern1_0 = arg1;
1761     let pattern2_0 = arg2;
1762     // Rule at src/isa/aarch64/inst.isle line 1496.
1763     let expr0_0: Type = I64;
1764     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1765     let expr2_0 = ALUOp::SubS;
1766     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1767     let expr4_0 = MInst::AluRRR {
1768         alu_op: expr2_0,
1769         size: expr3_0,
1770         rd: expr1_0,
1771         rn: pattern1_0,
1772         rm: pattern2_0,
1773     };
1774     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1775     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1776         inst: expr4_0,
1777         result: expr5_0,
1778     };
1779     return Some(expr6_0);
1780 }
1781 
1782 // Generated as internal constructor for term cmp64_imm.
1783 pub fn constructor_cmp64_imm<C: Context>(
1784     ctx: &mut C,
1785     arg0: Reg,
1786     arg1: Imm12,
1787 ) -> Option<ProducesFlags> {
1788     let pattern0_0 = arg0;
1789     let pattern1_0 = arg1;
1790     // Rule at src/isa/aarch64/inst.isle line 1503.
1791     let expr0_0 = ALUOp::SubS;
1792     let expr1_0 = OperandSize::Size64;
1793     let expr2_0 = C::writable_zero_reg(ctx);
1794     let expr3_0 = MInst::AluRRImm12 {
1795         alu_op: expr0_0,
1796         size: expr1_0,
1797         rd: expr2_0,
1798         rn: pattern0_0,
1799         imm12: pattern1_0,
1800     };
1801     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
1802     return Some(expr4_0);
1803 }
1804 
1805 // Generated as internal constructor for term sbc_paired.
1806 pub fn constructor_sbc_paired<C: Context>(
1807     ctx: &mut C,
1808     arg0: Type,
1809     arg1: Reg,
1810     arg2: Reg,
1811 ) -> Option<ConsumesFlags> {
1812     let pattern0_0 = arg0;
1813     let pattern1_0 = arg1;
1814     let pattern2_0 = arg2;
1815     // Rule at src/isa/aarch64/inst.isle line 1510.
1816     let expr0_0: Type = I64;
1817     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1818     let expr2_0 = ALUOp::Sbc;
1819     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1820     let expr4_0 = MInst::AluRRR {
1821         alu_op: expr2_0,
1822         size: expr3_0,
1823         rd: expr1_0,
1824         rn: pattern1_0,
1825         rm: pattern2_0,
1826     };
1827     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1828     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1829         inst: expr4_0,
1830         result: expr5_0,
1831     };
1832     return Some(expr6_0);
1833 }
1834 
1835 // Generated as internal constructor for term vec_misc.
1836 pub fn constructor_vec_misc<C: Context>(
1837     ctx: &mut C,
1838     arg0: &VecMisc2,
1839     arg1: Reg,
1840     arg2: &VectorSize,
1841 ) -> Option<Reg> {
1842     let pattern0_0 = arg0;
1843     let pattern1_0 = arg1;
1844     let pattern2_0 = arg2;
1845     // Rule at src/isa/aarch64/inst.isle line 1518.
1846     let expr0_0: Type = I8X16;
1847     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1848     let expr2_0 = MInst::VecMisc {
1849         op: pattern0_0.clone(),
1850         rd: expr1_0,
1851         rn: pattern1_0,
1852         size: pattern2_0.clone(),
1853     };
1854     let expr3_0 = C::emit(ctx, &expr2_0);
1855     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1856     return Some(expr4_0);
1857 }
1858 
1859 // Generated as internal constructor for term vec_rrr_long.
1860 pub fn constructor_vec_rrr_long<C: Context>(
1861     ctx: &mut C,
1862     arg0: &VecRRRLongOp,
1863     arg1: Reg,
1864     arg2: Reg,
1865     arg3: bool,
1866 ) -> Option<Reg> {
1867     let pattern0_0 = arg0;
1868     let pattern1_0 = arg1;
1869     let pattern2_0 = arg2;
1870     let pattern3_0 = arg3;
1871     // Rule at src/isa/aarch64/inst.isle line 1525.
1872     let expr0_0: Type = I8X16;
1873     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1874     let expr2_0 = MInst::VecRRRLong {
1875         alu_op: pattern0_0.clone(),
1876         rd: expr1_0,
1877         rn: pattern1_0,
1878         rm: pattern2_0,
1879         high_half: pattern3_0,
1880     };
1881     let expr3_0 = C::emit(ctx, &expr2_0);
1882     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1883     return Some(expr4_0);
1884 }
1885 
1886 // Generated as internal constructor for term vec_rrrr_long.
1887 pub fn constructor_vec_rrrr_long<C: Context>(
1888     ctx: &mut C,
1889     arg0: &VecRRRLongOp,
1890     arg1: Reg,
1891     arg2: Reg,
1892     arg3: Reg,
1893     arg4: bool,
1894 ) -> Option<Reg> {
1895     let pattern0_0 = arg0;
1896     let pattern1_0 = arg1;
1897     let pattern2_0 = arg2;
1898     let pattern3_0 = arg3;
1899     let pattern4_0 = arg4;
1900     // Rule at src/isa/aarch64/inst.isle line 1535.
1901     let expr0_0: Type = I8X16;
1902     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1903     let expr2_0 = MInst::FpuMove128 {
1904         rd: expr1_0,
1905         rn: pattern1_0,
1906     };
1907     let expr3_0 = C::emit(ctx, &expr2_0);
1908     let expr4_0 = MInst::VecRRRLong {
1909         alu_op: pattern0_0.clone(),
1910         rd: expr1_0,
1911         rn: pattern2_0,
1912         rm: pattern3_0,
1913         high_half: pattern4_0,
1914     };
1915     let expr5_0 = C::emit(ctx, &expr4_0);
1916     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1917     return Some(expr6_0);
1918 }
1919 
1920 // Generated as internal constructor for term vec_rr_narrow.
1921 pub fn constructor_vec_rr_narrow<C: Context>(
1922     ctx: &mut C,
1923     arg0: &VecRRNarrowOp,
1924     arg1: Reg,
1925     arg2: bool,
1926 ) -> Option<Reg> {
1927     let pattern0_0 = arg0;
1928     let pattern1_0 = arg1;
1929     let pattern2_0 = arg2;
1930     // Rule at src/isa/aarch64/inst.isle line 1543.
1931     let expr0_0: Type = I8X16;
1932     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1933     let expr2_0 = MInst::VecRRNarrow {
1934         op: pattern0_0.clone(),
1935         rd: expr1_0,
1936         rn: pattern1_0,
1937         high_half: pattern2_0,
1938     };
1939     let expr3_0 = C::emit(ctx, &expr2_0);
1940     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1941     return Some(expr4_0);
1942 }
1943 
1944 // Generated as internal constructor for term vec_rr_long.
1945 pub fn constructor_vec_rr_long<C: Context>(
1946     ctx: &mut C,
1947     arg0: &VecRRLongOp,
1948     arg1: Reg,
1949     arg2: bool,
1950 ) -> Option<Reg> {
1951     let pattern0_0 = arg0;
1952     let pattern1_0 = arg1;
1953     let pattern2_0 = arg2;
1954     // Rule at src/isa/aarch64/inst.isle line 1550.
1955     let expr0_0: Type = I8X16;
1956     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1957     let expr2_0 = MInst::VecRRLong {
1958         op: pattern0_0.clone(),
1959         rd: expr1_0,
1960         rn: pattern1_0,
1961         high_half: pattern2_0,
1962     };
1963     let expr3_0 = C::emit(ctx, &expr2_0);
1964     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1965     return Some(expr4_0);
1966 }
1967 
1968 // Generated as internal constructor for term mov_to_fpu.
1969 pub fn constructor_mov_to_fpu<C: Context>(
1970     ctx: &mut C,
1971     arg0: Reg,
1972     arg1: &ScalarSize,
1973 ) -> Option<Reg> {
1974     let pattern0_0 = arg0;
1975     let pattern1_0 = arg1;
1976     // Rule at src/isa/aarch64/inst.isle line 1557.
1977     let expr0_0: Type = I8X16;
1978     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1979     let expr2_0 = MInst::MovToFpu {
1980         rd: expr1_0,
1981         rn: pattern0_0,
1982         size: pattern1_0.clone(),
1983     };
1984     let expr3_0 = C::emit(ctx, &expr2_0);
1985     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1986     return Some(expr4_0);
1987 }
1988 
1989 // Generated as internal constructor for term mov_to_vec.
1990 pub fn constructor_mov_to_vec<C: Context>(
1991     ctx: &mut C,
1992     arg0: Reg,
1993     arg1: Reg,
1994     arg2: u8,
1995     arg3: &VectorSize,
1996 ) -> Option<Reg> {
1997     let pattern0_0 = arg0;
1998     let pattern1_0 = arg1;
1999     let pattern2_0 = arg2;
2000     let pattern3_0 = arg3;
2001     // Rule at src/isa/aarch64/inst.isle line 1564.
2002     let expr0_0: Type = I8X16;
2003     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2004     let expr2_0 = MInst::FpuMove128 {
2005         rd: expr1_0,
2006         rn: pattern0_0,
2007     };
2008     let expr3_0 = C::emit(ctx, &expr2_0);
2009     let expr4_0 = MInst::MovToVec {
2010         rd: expr1_0,
2011         rn: pattern1_0,
2012         idx: pattern2_0,
2013         size: pattern3_0.clone(),
2014     };
2015     let expr5_0 = C::emit(ctx, &expr4_0);
2016     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
2017     return Some(expr6_0);
2018 }
2019 
2020 // Generated as internal constructor for term mov_from_vec.
2021 pub fn constructor_mov_from_vec<C: Context>(
2022     ctx: &mut C,
2023     arg0: Reg,
2024     arg1: u8,
2025     arg2: &VectorSize,
2026 ) -> Option<Reg> {
2027     let pattern0_0 = arg0;
2028     let pattern1_0 = arg1;
2029     let pattern2_0 = arg2;
2030     // Rule at src/isa/aarch64/inst.isle line 1572.
2031     let expr0_0: Type = I64;
2032     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2033     let expr2_0 = MInst::MovFromVec {
2034         rd: expr1_0,
2035         rn: pattern0_0,
2036         idx: pattern1_0,
2037         size: pattern2_0.clone(),
2038     };
2039     let expr3_0 = C::emit(ctx, &expr2_0);
2040     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2041     return Some(expr4_0);
2042 }
2043 
2044 // Generated as internal constructor for term mov_from_vec_signed.
2045 pub fn constructor_mov_from_vec_signed<C: Context>(
2046     ctx: &mut C,
2047     arg0: Reg,
2048     arg1: u8,
2049     arg2: &VectorSize,
2050     arg3: &OperandSize,
2051 ) -> Option<Reg> {
2052     let pattern0_0 = arg0;
2053     let pattern1_0 = arg1;
2054     let pattern2_0 = arg2;
2055     let pattern3_0 = arg3;
2056     // Rule at src/isa/aarch64/inst.isle line 1579.
2057     let expr0_0: Type = I64;
2058     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2059     let expr2_0 = MInst::MovFromVecSigned {
2060         rd: expr1_0,
2061         rn: pattern0_0,
2062         idx: pattern1_0,
2063         size: pattern2_0.clone(),
2064         scalar_size: pattern3_0.clone(),
2065     };
2066     let expr3_0 = C::emit(ctx, &expr2_0);
2067     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2068     return Some(expr4_0);
2069 }
2070 
2071 // Generated as internal constructor for term extend.
2072 pub fn constructor_extend<C: Context>(
2073     ctx: &mut C,
2074     arg0: Reg,
2075     arg1: bool,
2076     arg2: u8,
2077     arg3: u8,
2078 ) -> Option<Reg> {
2079     let pattern0_0 = arg0;
2080     let pattern1_0 = arg1;
2081     let pattern2_0 = arg2;
2082     let pattern3_0 = arg3;
2083     // Rule at src/isa/aarch64/inst.isle line 1586.
2084     let expr0_0: Type = I64;
2085     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2086     let expr2_0 = MInst::Extend {
2087         rd: expr1_0,
2088         rn: pattern0_0,
2089         signed: pattern1_0,
2090         from_bits: pattern2_0,
2091         to_bits: pattern3_0,
2092     };
2093     let expr3_0 = C::emit(ctx, &expr2_0);
2094     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2095     return Some(expr4_0);
2096 }
2097 
2098 // Generated as internal constructor for term load_acquire.
2099 pub fn constructor_load_acquire<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2100     let pattern0_0 = arg0;
2101     let pattern1_0 = arg1;
2102     // Rule at src/isa/aarch64/inst.isle line 1593.
2103     let expr0_0: Type = I64;
2104     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2105     let expr2_0 = MInst::LoadAcquire {
2106         access_ty: pattern0_0,
2107         rt: expr1_0,
2108         rn: pattern1_0,
2109     };
2110     let expr3_0 = C::emit(ctx, &expr2_0);
2111     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2112     return Some(expr4_0);
2113 }
2114 
2115 // Generated as internal constructor for term tst_imm.
2116 pub fn constructor_tst_imm<C: Context>(
2117     ctx: &mut C,
2118     arg0: Type,
2119     arg1: Reg,
2120     arg2: ImmLogic,
2121 ) -> Option<ProducesFlags> {
2122     let pattern0_0 = arg0;
2123     let pattern1_0 = arg1;
2124     let pattern2_0 = arg2;
2125     // Rule at src/isa/aarch64/inst.isle line 1603.
2126     let expr0_0 = ALUOp::AndS;
2127     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
2128     let expr2_0 = C::writable_zero_reg(ctx);
2129     let expr3_0 = MInst::AluRRImmLogic {
2130         alu_op: expr0_0,
2131         size: expr1_0,
2132         rd: expr2_0,
2133         rn: pattern1_0,
2134         imml: pattern2_0,
2135     };
2136     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
2137     return Some(expr4_0);
2138 }
2139 
2140 // Generated as internal constructor for term csel.
2141 pub fn constructor_csel<C: Context>(
2142     ctx: &mut C,
2143     arg0: &Cond,
2144     arg1: Reg,
2145     arg2: Reg,
2146 ) -> Option<ConsumesFlags> {
2147     let pattern0_0 = arg0;
2148     let pattern1_0 = arg1;
2149     let pattern2_0 = arg2;
2150     // Rule at src/isa/aarch64/inst.isle line 1617.
2151     let expr0_0: Type = I64;
2152     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2153     let expr2_0 = MInst::CSel {
2154         rd: expr1_0,
2155         cond: pattern0_0.clone(),
2156         rn: pattern1_0,
2157         rm: pattern2_0,
2158     };
2159     let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
2160     let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
2161         inst: expr2_0,
2162         result: expr3_0,
2163     };
2164     return Some(expr4_0);
2165 }
2166 
2167 // Generated as internal constructor for term add.
2168 pub fn constructor_add<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2169     let pattern0_0 = arg0;
2170     let pattern1_0 = arg1;
2171     let pattern2_0 = arg2;
2172     // Rule at src/isa/aarch64/inst.isle line 1626.
2173     let expr0_0 = ALUOp::Add;
2174     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2175     return Some(expr1_0);
2176 }
2177 
2178 // Generated as internal constructor for term add_imm.
2179 pub fn constructor_add_imm<C: Context>(
2180     ctx: &mut C,
2181     arg0: Type,
2182     arg1: Reg,
2183     arg2: Imm12,
2184 ) -> Option<Reg> {
2185     let pattern0_0 = arg0;
2186     let pattern1_0 = arg1;
2187     let pattern2_0 = arg2;
2188     // Rule at src/isa/aarch64/inst.isle line 1629.
2189     let expr0_0 = ALUOp::Add;
2190     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2191     return Some(expr1_0);
2192 }
2193 
2194 // Generated as internal constructor for term add_extend.
2195 pub fn constructor_add_extend<C: Context>(
2196     ctx: &mut C,
2197     arg0: Type,
2198     arg1: Reg,
2199     arg2: &ExtendedValue,
2200 ) -> Option<Reg> {
2201     let pattern0_0 = arg0;
2202     let pattern1_0 = arg1;
2203     let pattern2_0 = arg2;
2204     // Rule at src/isa/aarch64/inst.isle line 1632.
2205     let expr0_0 = ALUOp::Add;
2206     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2207     return Some(expr1_0);
2208 }
2209 
2210 // Generated as internal constructor for term add_shift.
2211 pub fn constructor_add_shift<C: Context>(
2212     ctx: &mut C,
2213     arg0: Type,
2214     arg1: Reg,
2215     arg2: Reg,
2216     arg3: ShiftOpAndAmt,
2217 ) -> Option<Reg> {
2218     let pattern0_0 = arg0;
2219     let pattern1_0 = arg1;
2220     let pattern2_0 = arg2;
2221     let pattern3_0 = arg3;
2222     // Rule at src/isa/aarch64/inst.isle line 1635.
2223     let expr0_0 = ALUOp::Add;
2224     let expr1_0 = constructor_alu_rrr_shift(
2225         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2226     )?;
2227     return Some(expr1_0);
2228 }
2229 
2230 // Generated as internal constructor for term add_vec.
2231 pub fn constructor_add_vec<C: Context>(
2232     ctx: &mut C,
2233     arg0: Reg,
2234     arg1: Reg,
2235     arg2: &VectorSize,
2236 ) -> Option<Reg> {
2237     let pattern0_0 = arg0;
2238     let pattern1_0 = arg1;
2239     let pattern2_0 = arg2;
2240     // Rule at src/isa/aarch64/inst.isle line 1638.
2241     let expr0_0 = VecALUOp::Add;
2242     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2243     return Some(expr1_0);
2244 }
2245 
2246 // Generated as internal constructor for term sub.
2247 pub fn constructor_sub<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2248     let pattern0_0 = arg0;
2249     let pattern1_0 = arg1;
2250     let pattern2_0 = arg2;
2251     // Rule at src/isa/aarch64/inst.isle line 1643.
2252     let expr0_0 = ALUOp::Sub;
2253     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2254     return Some(expr1_0);
2255 }
2256 
2257 // Generated as internal constructor for term sub_imm.
2258 pub fn constructor_sub_imm<C: Context>(
2259     ctx: &mut C,
2260     arg0: Type,
2261     arg1: Reg,
2262     arg2: Imm12,
2263 ) -> Option<Reg> {
2264     let pattern0_0 = arg0;
2265     let pattern1_0 = arg1;
2266     let pattern2_0 = arg2;
2267     // Rule at src/isa/aarch64/inst.isle line 1646.
2268     let expr0_0 = ALUOp::Sub;
2269     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2270     return Some(expr1_0);
2271 }
2272 
2273 // Generated as internal constructor for term sub_extend.
2274 pub fn constructor_sub_extend<C: Context>(
2275     ctx: &mut C,
2276     arg0: Type,
2277     arg1: Reg,
2278     arg2: &ExtendedValue,
2279 ) -> Option<Reg> {
2280     let pattern0_0 = arg0;
2281     let pattern1_0 = arg1;
2282     let pattern2_0 = arg2;
2283     // Rule at src/isa/aarch64/inst.isle line 1649.
2284     let expr0_0 = ALUOp::Sub;
2285     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2286     return Some(expr1_0);
2287 }
2288 
2289 // Generated as internal constructor for term sub_shift.
2290 pub fn constructor_sub_shift<C: Context>(
2291     ctx: &mut C,
2292     arg0: Type,
2293     arg1: Reg,
2294     arg2: Reg,
2295     arg3: ShiftOpAndAmt,
2296 ) -> Option<Reg> {
2297     let pattern0_0 = arg0;
2298     let pattern1_0 = arg1;
2299     let pattern2_0 = arg2;
2300     let pattern3_0 = arg3;
2301     // Rule at src/isa/aarch64/inst.isle line 1652.
2302     let expr0_0 = ALUOp::Sub;
2303     let expr1_0 = constructor_alu_rrr_shift(
2304         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2305     )?;
2306     return Some(expr1_0);
2307 }
2308 
2309 // Generated as internal constructor for term sub_vec.
2310 pub fn constructor_sub_vec<C: Context>(
2311     ctx: &mut C,
2312     arg0: Reg,
2313     arg1: Reg,
2314     arg2: &VectorSize,
2315 ) -> Option<Reg> {
2316     let pattern0_0 = arg0;
2317     let pattern1_0 = arg1;
2318     let pattern2_0 = arg2;
2319     // Rule at src/isa/aarch64/inst.isle line 1655.
2320     let expr0_0 = VecALUOp::Sub;
2321     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2322     return Some(expr1_0);
2323 }
2324 
2325 // Generated as internal constructor for term madd.
2326 pub fn constructor_madd<C: Context>(
2327     ctx: &mut C,
2328     arg0: Type,
2329     arg1: Reg,
2330     arg2: Reg,
2331     arg3: Reg,
2332 ) -> Option<Reg> {
2333     let pattern0_0 = arg0;
2334     if pattern0_0 == I64 {
2335         let pattern2_0 = arg1;
2336         let pattern3_0 = arg2;
2337         let pattern4_0 = arg3;
2338         // Rule at src/isa/aarch64/inst.isle line 1661.
2339         let expr0_0 = constructor_madd64(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2340         return Some(expr0_0);
2341     }
2342     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2343         let pattern2_0 = arg1;
2344         let pattern3_0 = arg2;
2345         let pattern4_0 = arg3;
2346         // Rule at src/isa/aarch64/inst.isle line 1660.
2347         let expr0_0 = constructor_madd32(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2348         return Some(expr0_0);
2349     }
2350     return None;
2351 }
2352 
2353 // Generated as internal constructor for term madd32.
2354 pub fn constructor_madd32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2355     let pattern0_0 = arg0;
2356     let pattern1_0 = arg1;
2357     let pattern2_0 = arg2;
2358     // Rule at src/isa/aarch64/inst.isle line 1664.
2359     let expr0_0 = ALUOp3::MAdd32;
2360     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2361     return Some(expr1_0);
2362 }
2363 
2364 // Generated as internal constructor for term madd64.
2365 pub fn constructor_madd64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2366     let pattern0_0 = arg0;
2367     let pattern1_0 = arg1;
2368     let pattern2_0 = arg2;
2369     // Rule at src/isa/aarch64/inst.isle line 1667.
2370     let expr0_0 = ALUOp3::MAdd64;
2371     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2372     return Some(expr1_0);
2373 }
2374 
2375 // Generated as internal constructor for term msub64.
2376 pub fn constructor_msub64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2377     let pattern0_0 = arg0;
2378     let pattern1_0 = arg1;
2379     let pattern2_0 = arg2;
2380     // Rule at src/isa/aarch64/inst.isle line 1672.
2381     let expr0_0 = ALUOp3::MSub64;
2382     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2383     return Some(expr1_0);
2384 }
2385 
2386 // Generated as internal constructor for term uqadd.
2387 pub fn constructor_uqadd<C: Context>(
2388     ctx: &mut C,
2389     arg0: Reg,
2390     arg1: Reg,
2391     arg2: &VectorSize,
2392 ) -> Option<Reg> {
2393     let pattern0_0 = arg0;
2394     let pattern1_0 = arg1;
2395     let pattern2_0 = arg2;
2396     // Rule at src/isa/aarch64/inst.isle line 1676.
2397     let expr0_0 = VecALUOp::Uqadd;
2398     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2399     return Some(expr1_0);
2400 }
2401 
2402 // Generated as internal constructor for term sqadd.
2403 pub fn constructor_sqadd<C: Context>(
2404     ctx: &mut C,
2405     arg0: Reg,
2406     arg1: Reg,
2407     arg2: &VectorSize,
2408 ) -> Option<Reg> {
2409     let pattern0_0 = arg0;
2410     let pattern1_0 = arg1;
2411     let pattern2_0 = arg2;
2412     // Rule at src/isa/aarch64/inst.isle line 1680.
2413     let expr0_0 = VecALUOp::Sqadd;
2414     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2415     return Some(expr1_0);
2416 }
2417 
2418 // Generated as internal constructor for term uqsub.
2419 pub fn constructor_uqsub<C: Context>(
2420     ctx: &mut C,
2421     arg0: Reg,
2422     arg1: Reg,
2423     arg2: &VectorSize,
2424 ) -> Option<Reg> {
2425     let pattern0_0 = arg0;
2426     let pattern1_0 = arg1;
2427     let pattern2_0 = arg2;
2428     // Rule at src/isa/aarch64/inst.isle line 1684.
2429     let expr0_0 = VecALUOp::Uqsub;
2430     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2431     return Some(expr1_0);
2432 }
2433 
2434 // Generated as internal constructor for term sqsub.
2435 pub fn constructor_sqsub<C: Context>(
2436     ctx: &mut C,
2437     arg0: Reg,
2438     arg1: Reg,
2439     arg2: &VectorSize,
2440 ) -> Option<Reg> {
2441     let pattern0_0 = arg0;
2442     let pattern1_0 = arg1;
2443     let pattern2_0 = arg2;
2444     // Rule at src/isa/aarch64/inst.isle line 1688.
2445     let expr0_0 = VecALUOp::Sqsub;
2446     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2447     return Some(expr1_0);
2448 }
2449 
2450 // Generated as internal constructor for term umulh.
2451 pub fn constructor_umulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2452     let pattern0_0 = arg0;
2453     let pattern1_0 = arg1;
2454     let pattern2_0 = arg2;
2455     // Rule at src/isa/aarch64/inst.isle line 1692.
2456     let expr0_0 = ALUOp::UMulH;
2457     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2458     return Some(expr1_0);
2459 }
2460 
2461 // Generated as internal constructor for term smulh.
2462 pub fn constructor_smulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2463     let pattern0_0 = arg0;
2464     let pattern1_0 = arg1;
2465     let pattern2_0 = arg2;
2466     // Rule at src/isa/aarch64/inst.isle line 1696.
2467     let expr0_0 = ALUOp::SMulH;
2468     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2469     return Some(expr1_0);
2470 }
2471 
2472 // Generated as internal constructor for term mul.
2473 pub fn constructor_mul<C: Context>(
2474     ctx: &mut C,
2475     arg0: Reg,
2476     arg1: Reg,
2477     arg2: &VectorSize,
2478 ) -> Option<Reg> {
2479     let pattern0_0 = arg0;
2480     let pattern1_0 = arg1;
2481     let pattern2_0 = arg2;
2482     // Rule at src/isa/aarch64/inst.isle line 1700.
2483     let expr0_0 = VecALUOp::Mul;
2484     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2485     return Some(expr1_0);
2486 }
2487 
2488 // Generated as internal constructor for term neg.
2489 pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2490     let pattern0_0 = arg0;
2491     let pattern1_0 = arg1;
2492     // Rule at src/isa/aarch64/inst.isle line 1704.
2493     let expr0_0 = VecMisc2::Neg;
2494     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2495     return Some(expr1_0);
2496 }
2497 
2498 // Generated as internal constructor for term rev64.
2499 pub fn constructor_rev64<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2500     let pattern0_0 = arg0;
2501     let pattern1_0 = arg1;
2502     // Rule at src/isa/aarch64/inst.isle line 1708.
2503     let expr0_0 = VecMisc2::Rev64;
2504     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2505     return Some(expr1_0);
2506 }
2507 
2508 // Generated as internal constructor for term xtn64.
2509 pub fn constructor_xtn64<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2510     let pattern0_0 = arg0;
2511     let pattern1_0 = arg1;
2512     // Rule at src/isa/aarch64/inst.isle line 1712.
2513     let expr0_0 = VecRRNarrowOp::Xtn64;
2514     let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2515     return Some(expr1_0);
2516 }
2517 
2518 // Generated as internal constructor for term addp.
2519 pub fn constructor_addp<C: Context>(
2520     ctx: &mut C,
2521     arg0: Reg,
2522     arg1: Reg,
2523     arg2: &VectorSize,
2524 ) -> Option<Reg> {
2525     let pattern0_0 = arg0;
2526     let pattern1_0 = arg1;
2527     let pattern2_0 = arg2;
2528     // Rule at src/isa/aarch64/inst.isle line 1716.
2529     let expr0_0 = VecALUOp::Addp;
2530     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2531     return Some(expr1_0);
2532 }
2533 
2534 // Generated as internal constructor for term addv.
2535 pub fn constructor_addv<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2536     let pattern0_0 = arg0;
2537     let pattern1_0 = arg1;
2538     // Rule at src/isa/aarch64/inst.isle line 1720.
2539     let expr0_0 = VecLanesOp::Addv;
2540     let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2541     return Some(expr1_0);
2542 }
2543 
2544 // Generated as internal constructor for term shll32.
2545 pub fn constructor_shll32<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2546     let pattern0_0 = arg0;
2547     let pattern1_0 = arg1;
2548     // Rule at src/isa/aarch64/inst.isle line 1724.
2549     let expr0_0 = VecRRLongOp::Shll32;
2550     let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2551     return Some(expr1_0);
2552 }
2553 
2554 // Generated as internal constructor for term umlal32.
2555 pub fn constructor_umlal32<C: Context>(
2556     ctx: &mut C,
2557     arg0: Reg,
2558     arg1: Reg,
2559     arg2: Reg,
2560     arg3: bool,
2561 ) -> Option<Reg> {
2562     let pattern0_0 = arg0;
2563     let pattern1_0 = arg1;
2564     let pattern2_0 = arg2;
2565     let pattern3_0 = arg3;
2566     // Rule at src/isa/aarch64/inst.isle line 1728.
2567     let expr0_0 = VecRRRLongOp::Umlal32;
2568     let expr1_0 = constructor_vec_rrrr_long(
2569         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2570     )?;
2571     return Some(expr1_0);
2572 }
2573 
2574 // Generated as internal constructor for term smull8.
2575 pub fn constructor_smull8<C: Context>(
2576     ctx: &mut C,
2577     arg0: Reg,
2578     arg1: Reg,
2579     arg2: bool,
2580 ) -> Option<Reg> {
2581     let pattern0_0 = arg0;
2582     let pattern1_0 = arg1;
2583     let pattern2_0 = arg2;
2584     // Rule at src/isa/aarch64/inst.isle line 1732.
2585     let expr0_0 = VecRRRLongOp::Smull8;
2586     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2587     return Some(expr1_0);
2588 }
2589 
2590 // Generated as internal constructor for term umull8.
2591 pub fn constructor_umull8<C: Context>(
2592     ctx: &mut C,
2593     arg0: Reg,
2594     arg1: Reg,
2595     arg2: bool,
2596 ) -> Option<Reg> {
2597     let pattern0_0 = arg0;
2598     let pattern1_0 = arg1;
2599     let pattern2_0 = arg2;
2600     // Rule at src/isa/aarch64/inst.isle line 1736.
2601     let expr0_0 = VecRRRLongOp::Umull8;
2602     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2603     return Some(expr1_0);
2604 }
2605 
2606 // Generated as internal constructor for term smull16.
2607 pub fn constructor_smull16<C: Context>(
2608     ctx: &mut C,
2609     arg0: Reg,
2610     arg1: Reg,
2611     arg2: bool,
2612 ) -> Option<Reg> {
2613     let pattern0_0 = arg0;
2614     let pattern1_0 = arg1;
2615     let pattern2_0 = arg2;
2616     // Rule at src/isa/aarch64/inst.isle line 1740.
2617     let expr0_0 = VecRRRLongOp::Smull16;
2618     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2619     return Some(expr1_0);
2620 }
2621 
2622 // Generated as internal constructor for term umull16.
2623 pub fn constructor_umull16<C: Context>(
2624     ctx: &mut C,
2625     arg0: Reg,
2626     arg1: Reg,
2627     arg2: bool,
2628 ) -> Option<Reg> {
2629     let pattern0_0 = arg0;
2630     let pattern1_0 = arg1;
2631     let pattern2_0 = arg2;
2632     // Rule at src/isa/aarch64/inst.isle line 1744.
2633     let expr0_0 = VecRRRLongOp::Umull16;
2634     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2635     return Some(expr1_0);
2636 }
2637 
2638 // Generated as internal constructor for term smull32.
2639 pub fn constructor_smull32<C: Context>(
2640     ctx: &mut C,
2641     arg0: Reg,
2642     arg1: Reg,
2643     arg2: bool,
2644 ) -> Option<Reg> {
2645     let pattern0_0 = arg0;
2646     let pattern1_0 = arg1;
2647     let pattern2_0 = arg2;
2648     // Rule at src/isa/aarch64/inst.isle line 1748.
2649     let expr0_0 = VecRRRLongOp::Smull32;
2650     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2651     return Some(expr1_0);
2652 }
2653 
2654 // Generated as internal constructor for term umull32.
2655 pub fn constructor_umull32<C: Context>(
2656     ctx: &mut C,
2657     arg0: Reg,
2658     arg1: Reg,
2659     arg2: bool,
2660 ) -> Option<Reg> {
2661     let pattern0_0 = arg0;
2662     let pattern1_0 = arg1;
2663     let pattern2_0 = arg2;
2664     // Rule at src/isa/aarch64/inst.isle line 1752.
2665     let expr0_0 = VecRRRLongOp::Umull32;
2666     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2667     return Some(expr1_0);
2668 }
2669 
2670 // Generated as internal constructor for term asr.
2671 pub fn constructor_asr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2672     let pattern0_0 = arg0;
2673     let pattern1_0 = arg1;
2674     let pattern2_0 = arg2;
2675     // Rule at src/isa/aarch64/inst.isle line 1756.
2676     let expr0_0 = ALUOp::Asr;
2677     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2678     return Some(expr1_0);
2679 }
2680 
2681 // Generated as internal constructor for term asr_imm.
2682 pub fn constructor_asr_imm<C: Context>(
2683     ctx: &mut C,
2684     arg0: Type,
2685     arg1: Reg,
2686     arg2: ImmShift,
2687 ) -> Option<Reg> {
2688     let pattern0_0 = arg0;
2689     let pattern1_0 = arg1;
2690     let pattern2_0 = arg2;
2691     // Rule at src/isa/aarch64/inst.isle line 1759.
2692     let expr0_0 = ALUOp::Asr;
2693     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2694     return Some(expr1_0);
2695 }
2696 
2697 // Generated as internal constructor for term lsr.
2698 pub fn constructor_lsr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2699     let pattern0_0 = arg0;
2700     let pattern1_0 = arg1;
2701     let pattern2_0 = arg2;
2702     // Rule at src/isa/aarch64/inst.isle line 1763.
2703     let expr0_0 = ALUOp::Lsr;
2704     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2705     return Some(expr1_0);
2706 }
2707 
2708 // Generated as internal constructor for term lsr_imm.
2709 pub fn constructor_lsr_imm<C: Context>(
2710     ctx: &mut C,
2711     arg0: Type,
2712     arg1: Reg,
2713     arg2: ImmShift,
2714 ) -> Option<Reg> {
2715     let pattern0_0 = arg0;
2716     let pattern1_0 = arg1;
2717     let pattern2_0 = arg2;
2718     // Rule at src/isa/aarch64/inst.isle line 1766.
2719     let expr0_0 = ALUOp::Lsr;
2720     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2721     return Some(expr1_0);
2722 }
2723 
2724 // Generated as internal constructor for term lsl.
2725 pub fn constructor_lsl<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2726     let pattern0_0 = arg0;
2727     let pattern1_0 = arg1;
2728     let pattern2_0 = arg2;
2729     // Rule at src/isa/aarch64/inst.isle line 1770.
2730     let expr0_0 = ALUOp::Lsl;
2731     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2732     return Some(expr1_0);
2733 }
2734 
2735 // Generated as internal constructor for term lsl_imm.
2736 pub fn constructor_lsl_imm<C: Context>(
2737     ctx: &mut C,
2738     arg0: Type,
2739     arg1: Reg,
2740     arg2: ImmShift,
2741 ) -> Option<Reg> {
2742     let pattern0_0 = arg0;
2743     let pattern1_0 = arg1;
2744     let pattern2_0 = arg2;
2745     // Rule at src/isa/aarch64/inst.isle line 1773.
2746     let expr0_0 = ALUOp::Lsl;
2747     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2748     return Some(expr1_0);
2749 }
2750 
2751 // Generated as internal constructor for term a64_udiv.
2752 pub fn constructor_a64_udiv<C: Context>(
2753     ctx: &mut C,
2754     arg0: Type,
2755     arg1: Reg,
2756     arg2: Reg,
2757 ) -> Option<Reg> {
2758     let pattern0_0 = arg0;
2759     let pattern1_0 = arg1;
2760     let pattern2_0 = arg2;
2761     // Rule at src/isa/aarch64/inst.isle line 1777.
2762     let expr0_0 = ALUOp::UDiv;
2763     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2764     return Some(expr1_0);
2765 }
2766 
2767 // Generated as internal constructor for term a64_sdiv.
2768 pub fn constructor_a64_sdiv<C: Context>(
2769     ctx: &mut C,
2770     arg0: Type,
2771     arg1: Reg,
2772     arg2: Reg,
2773 ) -> Option<Reg> {
2774     let pattern0_0 = arg0;
2775     let pattern1_0 = arg1;
2776     let pattern2_0 = arg2;
2777     // Rule at src/isa/aarch64/inst.isle line 1781.
2778     let expr0_0 = ALUOp::SDiv;
2779     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2780     return Some(expr1_0);
2781 }
2782 
2783 // Generated as internal constructor for term not.
2784 pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2785     let pattern0_0 = arg0;
2786     let pattern1_0 = arg1;
2787     // Rule at src/isa/aarch64/inst.isle line 1785.
2788     let expr0_0 = VecMisc2::Not;
2789     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2790     return Some(expr1_0);
2791 }
2792 
2793 // Generated as internal constructor for term orr_not.
2794 pub fn constructor_orr_not<C: Context>(
2795     ctx: &mut C,
2796     arg0: Type,
2797     arg1: Reg,
2798     arg2: Reg,
2799 ) -> Option<Reg> {
2800     let pattern0_0 = arg0;
2801     let pattern1_0 = arg1;
2802     let pattern2_0 = arg2;
2803     // Rule at src/isa/aarch64/inst.isle line 1790.
2804     let expr0_0 = ALUOp::OrrNot;
2805     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2806     return Some(expr1_0);
2807 }
2808 
2809 // Generated as internal constructor for term orr_not_shift.
2810 pub fn constructor_orr_not_shift<C: Context>(
2811     ctx: &mut C,
2812     arg0: Type,
2813     arg1: Reg,
2814     arg2: Reg,
2815     arg3: ShiftOpAndAmt,
2816 ) -> Option<Reg> {
2817     let pattern0_0 = arg0;
2818     let pattern1_0 = arg1;
2819     let pattern2_0 = arg2;
2820     let pattern3_0 = arg3;
2821     // Rule at src/isa/aarch64/inst.isle line 1793.
2822     let expr0_0 = ALUOp::OrrNot;
2823     let expr1_0 = constructor_alu_rrr_shift(
2824         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2825     )?;
2826     return Some(expr1_0);
2827 }
2828 
2829 // Generated as internal constructor for term orr.
2830 pub fn constructor_orr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2831     let pattern0_0 = arg0;
2832     let pattern1_0 = arg1;
2833     let pattern2_0 = arg2;
2834     // Rule at src/isa/aarch64/inst.isle line 1798.
2835     let expr0_0 = ALUOp::Orr;
2836     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2837     return Some(expr1_0);
2838 }
2839 
2840 // Generated as internal constructor for term orr_imm.
2841 pub fn constructor_orr_imm<C: Context>(
2842     ctx: &mut C,
2843     arg0: Type,
2844     arg1: Reg,
2845     arg2: ImmLogic,
2846 ) -> Option<Reg> {
2847     let pattern0_0 = arg0;
2848     let pattern1_0 = arg1;
2849     let pattern2_0 = arg2;
2850     // Rule at src/isa/aarch64/inst.isle line 1801.
2851     let expr0_0 = ALUOp::Orr;
2852     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2853     return Some(expr1_0);
2854 }
2855 
2856 // Generated as internal constructor for term orr_vec.
2857 pub fn constructor_orr_vec<C: Context>(
2858     ctx: &mut C,
2859     arg0: Reg,
2860     arg1: Reg,
2861     arg2: &VectorSize,
2862 ) -> Option<Reg> {
2863     let pattern0_0 = arg0;
2864     let pattern1_0 = arg1;
2865     let pattern2_0 = arg2;
2866     // Rule at src/isa/aarch64/inst.isle line 1804.
2867     let expr0_0 = VecALUOp::Orr;
2868     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2869     return Some(expr1_0);
2870 }
2871 
2872 // Generated as internal constructor for term and_imm.
2873 pub fn constructor_and_imm<C: Context>(
2874     ctx: &mut C,
2875     arg0: Type,
2876     arg1: Reg,
2877     arg2: ImmLogic,
2878 ) -> Option<Reg> {
2879     let pattern0_0 = arg0;
2880     let pattern1_0 = arg1;
2881     let pattern2_0 = arg2;
2882     // Rule at src/isa/aarch64/inst.isle line 1809.
2883     let expr0_0 = ALUOp::And;
2884     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2885     return Some(expr1_0);
2886 }
2887 
2888 // Generated as internal constructor for term and_vec.
2889 pub fn constructor_and_vec<C: Context>(
2890     ctx: &mut C,
2891     arg0: Reg,
2892     arg1: Reg,
2893     arg2: &VectorSize,
2894 ) -> Option<Reg> {
2895     let pattern0_0 = arg0;
2896     let pattern1_0 = arg1;
2897     let pattern2_0 = arg2;
2898     // Rule at src/isa/aarch64/inst.isle line 1812.
2899     let expr0_0 = VecALUOp::And;
2900     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2901     return Some(expr1_0);
2902 }
2903 
2904 // Generated as internal constructor for term eor_vec.
2905 pub fn constructor_eor_vec<C: Context>(
2906     ctx: &mut C,
2907     arg0: Reg,
2908     arg1: Reg,
2909     arg2: &VectorSize,
2910 ) -> Option<Reg> {
2911     let pattern0_0 = arg0;
2912     let pattern1_0 = arg1;
2913     let pattern2_0 = arg2;
2914     // Rule at src/isa/aarch64/inst.isle line 1816.
2915     let expr0_0 = VecALUOp::Eor;
2916     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2917     return Some(expr1_0);
2918 }
2919 
2920 // Generated as internal constructor for term bic_vec.
2921 pub fn constructor_bic_vec<C: Context>(
2922     ctx: &mut C,
2923     arg0: Reg,
2924     arg1: Reg,
2925     arg2: &VectorSize,
2926 ) -> Option<Reg> {
2927     let pattern0_0 = arg0;
2928     let pattern1_0 = arg1;
2929     let pattern2_0 = arg2;
2930     // Rule at src/isa/aarch64/inst.isle line 1820.
2931     let expr0_0 = VecALUOp::Bic;
2932     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2933     return Some(expr1_0);
2934 }
2935 
2936 // Generated as internal constructor for term sshl.
2937 pub fn constructor_sshl<C: Context>(
2938     ctx: &mut C,
2939     arg0: Reg,
2940     arg1: Reg,
2941     arg2: &VectorSize,
2942 ) -> Option<Reg> {
2943     let pattern0_0 = arg0;
2944     let pattern1_0 = arg1;
2945     let pattern2_0 = arg2;
2946     // Rule at src/isa/aarch64/inst.isle line 1824.
2947     let expr0_0 = VecALUOp::Sshl;
2948     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2949     return Some(expr1_0);
2950 }
2951 
2952 // Generated as internal constructor for term ushl.
2953 pub fn constructor_ushl<C: Context>(
2954     ctx: &mut C,
2955     arg0: Reg,
2956     arg1: Reg,
2957     arg2: &VectorSize,
2958 ) -> Option<Reg> {
2959     let pattern0_0 = arg0;
2960     let pattern1_0 = arg1;
2961     let pattern2_0 = arg2;
2962     // Rule at src/isa/aarch64/inst.isle line 1828.
2963     let expr0_0 = VecALUOp::Ushl;
2964     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2965     return Some(expr1_0);
2966 }
2967 
2968 // Generated as internal constructor for term a64_rotr.
2969 pub fn constructor_a64_rotr<C: Context>(
2970     ctx: &mut C,
2971     arg0: Type,
2972     arg1: Reg,
2973     arg2: Reg,
2974 ) -> Option<Reg> {
2975     let pattern0_0 = arg0;
2976     let pattern1_0 = arg1;
2977     let pattern2_0 = arg2;
2978     // Rule at src/isa/aarch64/inst.isle line 1833.
2979     let expr0_0 = ALUOp::RotR;
2980     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2981     return Some(expr1_0);
2982 }
2983 
2984 // Generated as internal constructor for term a64_rotr_imm.
2985 pub fn constructor_a64_rotr_imm<C: Context>(
2986     ctx: &mut C,
2987     arg0: Type,
2988     arg1: Reg,
2989     arg2: ImmShift,
2990 ) -> Option<Reg> {
2991     let pattern0_0 = arg0;
2992     let pattern1_0 = arg1;
2993     let pattern2_0 = arg2;
2994     // Rule at src/isa/aarch64/inst.isle line 1836.
2995     let expr0_0 = ALUOp::RotR;
2996     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2997     return Some(expr1_0);
2998 }
2999 
3000 // Generated as internal constructor for term rbit.
3001 pub fn constructor_rbit<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
3002     let pattern0_0 = arg0;
3003     let pattern1_0 = arg1;
3004     // Rule at src/isa/aarch64/inst.isle line 1841.
3005     let expr0_0 = BitOp::RBit;
3006     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3007     return Some(expr1_0);
3008 }
3009 
3010 // Generated as internal constructor for term a64_clz.
3011 pub fn constructor_a64_clz<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
3012     let pattern0_0 = arg0;
3013     let pattern1_0 = arg1;
3014     // Rule at src/isa/aarch64/inst.isle line 1846.
3015     let expr0_0 = BitOp::Clz;
3016     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3017     return Some(expr1_0);
3018 }
3019 
3020 // Generated as internal constructor for term a64_cls.
3021 pub fn constructor_a64_cls<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
3022     let pattern0_0 = arg0;
3023     let pattern1_0 = arg1;
3024     // Rule at src/isa/aarch64/inst.isle line 1851.
3025     let expr0_0 = BitOp::Cls;
3026     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3027     return Some(expr1_0);
3028 }
3029 
3030 // Generated as internal constructor for term eon.
3031 pub fn constructor_eon<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
3032     let pattern0_0 = arg0;
3033     let pattern1_0 = arg1;
3034     let pattern2_0 = arg2;
3035     // Rule at src/isa/aarch64/inst.isle line 1856.
3036     let expr0_0 = ALUOp::EorNot;
3037     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3038     return Some(expr1_0);
3039 }
3040 
3041 // Generated as internal constructor for term vec_cnt.
3042 pub fn constructor_vec_cnt<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3043     let pattern0_0 = arg0;
3044     let pattern1_0 = arg1;
3045     // Rule at src/isa/aarch64/inst.isle line 1861.
3046     let expr0_0 = VecMisc2::Cnt;
3047     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3048     return Some(expr1_0);
3049 }
3050 
3051 // Generated as internal constructor for term imm.
3052 pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
3053     let pattern0_0 = arg0;
3054     if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) {
3055         let pattern2_0 = arg1;
3056         let closure3 = || {
3057             let expr0_0: Type = I64;
3058             return Some(expr0_0);
3059         };
3060         if let Some(pattern3_0) = closure3() {
3061             if let Some(pattern4_0) = C::imm_logic_from_u64(ctx, pattern2_0, pattern3_0) {
3062                 // Rule at src/isa/aarch64/inst.isle line 1876.
3063                 let expr0_0: Type = I64;
3064                 let expr1_0 = C::zero_reg(ctx);
3065                 let expr2_0 = constructor_orr_imm(ctx, expr0_0, expr1_0, pattern4_0)?;
3066                 return Some(expr2_0);
3067             }
3068         }
3069         if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) {
3070             // Rule at src/isa/aarch64/inst.isle line 1868.
3071             let expr0_0 = OperandSize::Size64;
3072             let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?;
3073             return Some(expr1_0);
3074         }
3075         if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) {
3076             // Rule at src/isa/aarch64/inst.isle line 1872.
3077             let expr0_0 = OperandSize::Size64;
3078             let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?;
3079             return Some(expr1_0);
3080         }
3081         // Rule at src/isa/aarch64/inst.isle line 1883.
3082         let expr0_0 = C::load_constant64_full(ctx, pattern2_0);
3083         return Some(expr0_0);
3084     }
3085     return None;
3086 }
3087 
3088 // Generated as internal constructor for term put_in_reg_sext32.
3089 pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3090     let pattern0_0 = arg0;
3091     let pattern1_0 = C::value_type(ctx, pattern0_0);
3092     if pattern1_0 == I32 {
3093         // Rule at src/isa/aarch64/inst.isle line 1894.
3094         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3095         return Some(expr0_0);
3096     }
3097     if pattern1_0 == I64 {
3098         // Rule at src/isa/aarch64/inst.isle line 1895.
3099         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3100         return Some(expr0_0);
3101     }
3102     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3103         // Rule at src/isa/aarch64/inst.isle line 1890.
3104         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3105         let expr1_0: bool = true;
3106         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3107         let expr3_0: u8 = 32;
3108         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3109         return Some(expr4_0);
3110     }
3111     return None;
3112 }
3113 
3114 // Generated as internal constructor for term put_in_reg_zext32.
3115 pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3116     let pattern0_0 = arg0;
3117     let pattern1_0 = C::value_type(ctx, pattern0_0);
3118     if pattern1_0 == I32 {
3119         // Rule at src/isa/aarch64/inst.isle line 1903.
3120         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3121         return Some(expr0_0);
3122     }
3123     if pattern1_0 == I64 {
3124         // Rule at src/isa/aarch64/inst.isle line 1904.
3125         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3126         return Some(expr0_0);
3127     }
3128     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3129         // Rule at src/isa/aarch64/inst.isle line 1899.
3130         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3131         let expr1_0: bool = false;
3132         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3133         let expr3_0: u8 = 32;
3134         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3135         return Some(expr4_0);
3136     }
3137     return None;
3138 }
3139 
3140 // Generated as internal constructor for term put_in_reg_sext64.
3141 pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3142     let pattern0_0 = arg0;
3143     let pattern1_0 = C::value_type(ctx, pattern0_0);
3144     if pattern1_0 == I64 {
3145         // Rule at src/isa/aarch64/inst.isle line 1912.
3146         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3147         return Some(expr0_0);
3148     }
3149     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3150         // Rule at src/isa/aarch64/inst.isle line 1908.
3151         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3152         let expr1_0: bool = true;
3153         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3154         let expr3_0: u8 = 64;
3155         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3156         return Some(expr4_0);
3157     }
3158     return None;
3159 }
3160 
3161 // Generated as internal constructor for term put_in_reg_zext64.
3162 pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3163     let pattern0_0 = arg0;
3164     let pattern1_0 = C::value_type(ctx, pattern0_0);
3165     if pattern1_0 == I64 {
3166         // Rule at src/isa/aarch64/inst.isle line 1920.
3167         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3168         return Some(expr0_0);
3169     }
3170     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3171         // Rule at src/isa/aarch64/inst.isle line 1916.
3172         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3173         let expr1_0: bool = false;
3174         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3175         let expr3_0: u8 = 64;
3176         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3177         return Some(expr4_0);
3178     }
3179     return None;
3180 }
3181 
3182 // Generated as internal constructor for term trap_if_zero_divisor.
3183 pub fn constructor_trap_if_zero_divisor<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3184     let pattern0_0 = arg0;
3185     // Rule at src/isa/aarch64/inst.isle line 1925.
3186     let expr0_0 = C::cond_br_zero(ctx, pattern0_0);
3187     let expr1_0 = C::trap_code_division_by_zero(ctx);
3188     let expr2_0 = MInst::TrapIf {
3189         kind: expr0_0,
3190         trap_code: expr1_0,
3191     };
3192     let expr3_0 = C::emit(ctx, &expr2_0);
3193     return Some(pattern0_0);
3194 }
3195 
3196 // Generated as internal constructor for term size_from_ty.
3197 pub fn constructor_size_from_ty<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
3198     let pattern0_0 = arg0;
3199     if pattern0_0 == I64 {
3200         // Rule at src/isa/aarch64/inst.isle line 1931.
3201         let expr0_0 = OperandSize::Size64;
3202         return Some(expr0_0);
3203     }
3204     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
3205         // Rule at src/isa/aarch64/inst.isle line 1930.
3206         let expr0_0 = OperandSize::Size32;
3207         return Some(expr0_0);
3208     }
3209     return None;
3210 }
3211 
3212 // Generated as internal constructor for term trap_if_div_overflow.
3213 pub fn constructor_trap_if_div_overflow<C: Context>(
3214     ctx: &mut C,
3215     arg0: Type,
3216     arg1: Reg,
3217     arg2: Reg,
3218 ) -> Option<Reg> {
3219     let pattern0_0 = arg0;
3220     let pattern1_0 = arg1;
3221     let pattern2_0 = arg2;
3222     // Rule at src/isa/aarch64/inst.isle line 1937.
3223     let expr0_0 = ALUOp::AddS;
3224     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
3225     let expr2_0 = C::writable_zero_reg(ctx);
3226     let expr3_0: u8 = 1;
3227     let expr4_0 = C::u8_into_imm12(ctx, expr3_0);
3228     let expr5_0 = MInst::AluRRImm12 {
3229         alu_op: expr0_0,
3230         size: expr1_0,
3231         rd: expr2_0,
3232         rn: pattern2_0,
3233         imm12: expr4_0,
3234     };
3235     let expr6_0 = C::emit(ctx, &expr5_0);
3236     let expr7_0 = constructor_size_from_ty(ctx, pattern0_0)?;
3237     let expr8_0: u8 = 1;
3238     let expr9_0 = C::u8_into_uimm5(ctx, expr8_0);
3239     let expr10_0: bool = false;
3240     let expr11_0: bool = false;
3241     let expr12_0: bool = false;
3242     let expr13_0: bool = false;
3243     let expr14_0 = C::nzcv(ctx, expr10_0, expr11_0, expr12_0, expr13_0);
3244     let expr15_0 = Cond::Eq;
3245     let expr16_0 = MInst::CCmpImm {
3246         size: expr7_0,
3247         rn: pattern1_0,
3248         imm: expr9_0,
3249         nzcv: expr14_0,
3250         cond: expr15_0,
3251     };
3252     let expr17_0 = C::emit(ctx, &expr16_0);
3253     let expr18_0 = Cond::Vs;
3254     let expr19_0 = C::cond_br_cond(ctx, &expr18_0);
3255     let expr20_0 = C::trap_code_integer_overflow(ctx);
3256     let expr21_0 = MInst::TrapIf {
3257         kind: expr19_0,
3258         trap_code: expr20_0,
3259     };
3260     let expr22_0 = C::emit(ctx, &expr21_0);
3261     return Some(pattern1_0);
3262 }
3263 
3264 // Generated as internal constructor for term alu_rs_imm_logic_commutative.
3265 pub fn constructor_alu_rs_imm_logic_commutative<C: Context>(
3266     ctx: &mut C,
3267     arg0: &ALUOp,
3268     arg1: Type,
3269     arg2: Value,
3270     arg3: Value,
3271 ) -> Option<Reg> {
3272     let pattern0_0 = arg0;
3273     let pattern1_0 = arg1;
3274     let pattern2_0 = arg2;
3275     if let Some(pattern3_0) = C::def_inst(ctx, pattern2_0) {
3276         let pattern4_0 = C::inst_data(ctx, pattern3_0);
3277         match &pattern4_0 {
3278             &InstructionData::UnaryImm {
3279                 opcode: ref pattern5_0,
3280                 imm: pattern5_1,
3281             } => {
3282                 if let &Opcode::Iconst = pattern5_0 {
3283                     let closure7 = || {
3284                         return Some(pattern1_0);
3285                     };
3286                     if let Some(pattern7_0) = closure7() {
3287                         if let Some(pattern8_0) =
3288                             C::imm_logic_from_imm64(ctx, pattern5_1, pattern7_0)
3289                         {
3290                             let pattern9_0 = arg3;
3291                             // Rule at src/isa/aarch64/inst.isle line 1982.
3292                             let expr0_0 = C::put_in_reg(ctx, pattern9_0);
3293                             let expr1_0 = constructor_alu_rr_imm_logic(
3294                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0,
3295                             )?;
3296                             return Some(expr1_0);
3297                         }
3298                     }
3299                 }
3300             }
3301             &InstructionData::Binary {
3302                 opcode: ref pattern5_0,
3303                 args: ref pattern5_1,
3304             } => {
3305                 if let &Opcode::Ishl = pattern5_0 {
3306                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3307                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3308                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
3309                         if let &InstructionData::UnaryImm {
3310                             opcode: ref pattern10_0,
3311                             imm: pattern10_1,
3312                         } = &pattern9_0
3313                         {
3314                             if let &Opcode::Iconst = pattern10_0 {
3315                                 let closure12 = || {
3316                                     return Some(pattern1_0);
3317                                 };
3318                                 if let Some(pattern12_0) = closure12() {
3319                                     if let Some(pattern13_0) =
3320                                         C::lshl_from_imm64(ctx, pattern10_1, pattern12_0)
3321                                     {
3322                                         let pattern14_0 = arg3;
3323                                         // Rule at src/isa/aarch64/inst.isle line 1988.
3324                                         let expr0_0 = C::put_in_reg(ctx, pattern14_0);
3325                                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3326                                         let expr2_0 = constructor_alu_rrr_shift(
3327                                             ctx,
3328                                             pattern0_0,
3329                                             pattern1_0,
3330                                             expr0_0,
3331                                             expr1_0,
3332                                             pattern13_0,
3333                                         )?;
3334                                         return Some(expr2_0);
3335                                     }
3336                                 }
3337                             }
3338                         }
3339                     }
3340                 }
3341             }
3342             _ => {}
3343         }
3344     }
3345     let pattern3_0 = arg3;
3346     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3347         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3348         match &pattern5_0 {
3349             &InstructionData::UnaryImm {
3350                 opcode: ref pattern6_0,
3351                 imm: pattern6_1,
3352             } => {
3353                 if let &Opcode::Iconst = pattern6_0 {
3354                     let closure8 = || {
3355                         return Some(pattern1_0);
3356                     };
3357                     if let Some(pattern8_0) = closure8() {
3358                         if let Some(pattern9_0) =
3359                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3360                         {
3361                             // Rule at src/isa/aarch64/inst.isle line 1980.
3362                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3363                             let expr1_0 = constructor_alu_rr_imm_logic(
3364                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3365                             )?;
3366                             return Some(expr1_0);
3367                         }
3368                     }
3369                 }
3370             }
3371             &InstructionData::Binary {
3372                 opcode: ref pattern6_0,
3373                 args: ref pattern6_1,
3374             } => {
3375                 if let &Opcode::Ishl = pattern6_0 {
3376                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3377                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3378                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3379                         if let &InstructionData::UnaryImm {
3380                             opcode: ref pattern11_0,
3381                             imm: pattern11_1,
3382                         } = &pattern10_0
3383                         {
3384                             if let &Opcode::Iconst = pattern11_0 {
3385                                 let closure13 = || {
3386                                     return Some(pattern1_0);
3387                                 };
3388                                 if let Some(pattern13_0) = closure13() {
3389                                     if let Some(pattern14_0) =
3390                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3391                                     {
3392                                         // Rule at src/isa/aarch64/inst.isle line 1986.
3393                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3394                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3395                                         let expr2_0 = constructor_alu_rrr_shift(
3396                                             ctx,
3397                                             pattern0_0,
3398                                             pattern1_0,
3399                                             expr0_0,
3400                                             expr1_0,
3401                                             pattern14_0,
3402                                         )?;
3403                                         return Some(expr2_0);
3404                                     }
3405                                 }
3406                             }
3407                         }
3408                     }
3409                 }
3410             }
3411             _ => {}
3412         }
3413     }
3414     // Rule at src/isa/aarch64/inst.isle line 1976.
3415     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3416     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3417     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3418     return Some(expr2_0);
3419 }
3420 
3421 // Generated as internal constructor for term alu_rs_imm_logic.
3422 pub fn constructor_alu_rs_imm_logic<C: Context>(
3423     ctx: &mut C,
3424     arg0: &ALUOp,
3425     arg1: Type,
3426     arg2: Value,
3427     arg3: Value,
3428 ) -> Option<Reg> {
3429     let pattern0_0 = arg0;
3430     let pattern1_0 = arg1;
3431     let pattern2_0 = arg2;
3432     let pattern3_0 = arg3;
3433     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3434         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3435         match &pattern5_0 {
3436             &InstructionData::UnaryImm {
3437                 opcode: ref pattern6_0,
3438                 imm: pattern6_1,
3439             } => {
3440                 if let &Opcode::Iconst = pattern6_0 {
3441                     let closure8 = || {
3442                         return Some(pattern1_0);
3443                     };
3444                     if let Some(pattern8_0) = closure8() {
3445                         if let Some(pattern9_0) =
3446                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3447                         {
3448                             // Rule at src/isa/aarch64/inst.isle line 1996.
3449                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3450                             let expr1_0 = constructor_alu_rr_imm_logic(
3451                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3452                             )?;
3453                             return Some(expr1_0);
3454                         }
3455                     }
3456                 }
3457             }
3458             &InstructionData::Binary {
3459                 opcode: ref pattern6_0,
3460                 args: ref pattern6_1,
3461             } => {
3462                 if let &Opcode::Ishl = pattern6_0 {
3463                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3464                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3465                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3466                         if let &InstructionData::UnaryImm {
3467                             opcode: ref pattern11_0,
3468                             imm: pattern11_1,
3469                         } = &pattern10_0
3470                         {
3471                             if let &Opcode::Iconst = pattern11_0 {
3472                                 let closure13 = || {
3473                                     return Some(pattern1_0);
3474                                 };
3475                                 if let Some(pattern13_0) = closure13() {
3476                                     if let Some(pattern14_0) =
3477                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3478                                     {
3479                                         // Rule at src/isa/aarch64/inst.isle line 1998.
3480                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3481                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3482                                         let expr2_0 = constructor_alu_rrr_shift(
3483                                             ctx,
3484                                             pattern0_0,
3485                                             pattern1_0,
3486                                             expr0_0,
3487                                             expr1_0,
3488                                             pattern14_0,
3489                                         )?;
3490                                         return Some(expr2_0);
3491                                     }
3492                                 }
3493                             }
3494                         }
3495                     }
3496                 }
3497             }
3498             _ => {}
3499         }
3500     }
3501     // Rule at src/isa/aarch64/inst.isle line 1994.
3502     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3503     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3504     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3505     return Some(expr2_0);
3506 }
3507 
3508 // Generated as internal constructor for term i128_alu_bitop.
3509 pub fn constructor_i128_alu_bitop<C: Context>(
3510     ctx: &mut C,
3511     arg0: &ALUOp,
3512     arg1: Type,
3513     arg2: Value,
3514     arg3: Value,
3515 ) -> Option<ValueRegs> {
3516     let pattern0_0 = arg0;
3517     let pattern1_0 = arg1;
3518     let pattern2_0 = arg2;
3519     let pattern3_0 = arg3;
3520     // Rule at src/isa/aarch64/inst.isle line 2006.
3521     let expr0_0 = C::put_in_regs(ctx, pattern2_0);
3522     let expr1_0: usize = 0;
3523     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3524     let expr3_0: usize = 1;
3525     let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
3526     let expr5_0 = C::put_in_regs(ctx, pattern3_0);
3527     let expr6_0: usize = 0;
3528     let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
3529     let expr8_0: usize = 1;
3530     let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
3531     let expr10_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr2_0, expr7_0)?;
3532     let expr11_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr4_0, expr9_0)?;
3533     let expr12_0 = C::value_regs(ctx, expr10_0, expr11_0);
3534     return Some(expr12_0);
3535 }
3536 
3537 // Generated as internal constructor for term float_cmp_zero.
3538 pub fn constructor_float_cmp_zero<C: Context>(
3539     ctx: &mut C,
3540     arg0: &FloatCC,
3541     arg1: Reg,
3542     arg2: &VectorSize,
3543 ) -> Option<Reg> {
3544     let pattern0_0 = arg0;
3545     let pattern1_0 = arg1;
3546     let pattern2_0 = arg2;
3547     // Rule at src/isa/aarch64/inst.isle line 2046.
3548     let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0);
3549     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3550     return Some(expr1_0);
3551 }
3552 
3553 // Generated as internal constructor for term float_cmp_zero_swap.
3554 pub fn constructor_float_cmp_zero_swap<C: Context>(
3555     ctx: &mut C,
3556     arg0: &FloatCC,
3557     arg1: Reg,
3558     arg2: &VectorSize,
3559 ) -> Option<Reg> {
3560     let pattern0_0 = arg0;
3561     let pattern1_0 = arg1;
3562     let pattern2_0 = arg2;
3563     // Rule at src/isa/aarch64/inst.isle line 2051.
3564     let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0);
3565     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3566     return Some(expr1_0);
3567 }
3568 
3569 // Generated as internal constructor for term fcmeq0.
3570 pub fn constructor_fcmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3571     let pattern0_0 = arg0;
3572     let pattern1_0 = arg1;
3573     // Rule at src/isa/aarch64/inst.isle line 2056.
3574     let expr0_0 = VecMisc2::Fcmeq0;
3575     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3576     return Some(expr1_0);
3577 }
3578 
3579 // Generated as internal constructor for term int_cmp_zero.
3580 pub fn constructor_int_cmp_zero<C: Context>(
3581     ctx: &mut C,
3582     arg0: &IntCC,
3583     arg1: Reg,
3584     arg2: &VectorSize,
3585 ) -> Option<Reg> {
3586     let pattern0_0 = arg0;
3587     let pattern1_0 = arg1;
3588     let pattern2_0 = arg2;
3589     // Rule at src/isa/aarch64/inst.isle line 2082.
3590     let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0);
3591     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3592     return Some(expr1_0);
3593 }
3594 
3595 // Generated as internal constructor for term int_cmp_zero_swap.
3596 pub fn constructor_int_cmp_zero_swap<C: Context>(
3597     ctx: &mut C,
3598     arg0: &IntCC,
3599     arg1: Reg,
3600     arg2: &VectorSize,
3601 ) -> Option<Reg> {
3602     let pattern0_0 = arg0;
3603     let pattern1_0 = arg1;
3604     let pattern2_0 = arg2;
3605     // Rule at src/isa/aarch64/inst.isle line 2087.
3606     let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0);
3607     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3608     return Some(expr1_0);
3609 }
3610 
3611 // Generated as internal constructor for term cmeq0.
3612 pub fn constructor_cmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3613     let pattern0_0 = arg0;
3614     let pattern1_0 = arg1;
3615     // Rule at src/isa/aarch64/inst.isle line 2092.
3616     let expr0_0 = VecMisc2::Cmeq0;
3617     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3618     return Some(expr1_0);
3619 }
3620 
3621 // Generated as internal constructor for term lower.
3622 pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> {
3623     let pattern0_0 = arg0;
3624     if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
3625         let pattern2_0 = C::value_type(ctx, pattern1_0);
3626         if pattern2_0 == I8 {
3627             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3628             if let &InstructionData::Unary {
3629                 opcode: ref pattern5_0,
3630                 arg: pattern5_1,
3631             } = &pattern4_0
3632             {
3633                 match pattern5_0 {
3634                     &Opcode::Bitrev => {
3635                         // Rule at src/isa/aarch64/lower.isle line 974.
3636                         let expr0_0: Type = I32;
3637                         let expr1_0: Type = I32;
3638                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3639                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3640                         let expr4_0: u8 = 24;
3641                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3642                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3643                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3644                         return Some(expr7_0);
3645                     }
3646                     &Opcode::Clz => {
3647                         // Rule at src/isa/aarch64/lower.isle line 995.
3648                         let expr0_0: Type = I32;
3649                         let expr1_0: Type = I32;
3650                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3651                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3652                         let expr4_0: u8 = 24;
3653                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3654                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3655                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3656                         return Some(expr7_0);
3657                     }
3658                     &Opcode::Cls => {
3659                         // Rule at src/isa/aarch64/lower.isle line 1042.
3660                         let expr0_0: Type = I32;
3661                         let expr1_0: Type = I32;
3662                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3663                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3664                         let expr4_0: u8 = 24;
3665                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3666                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3667                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3668                         return Some(expr7_0);
3669                     }
3670                     &Opcode::Ctz => {
3671                         // Rule at src/isa/aarch64/lower.isle line 1025.
3672                         let expr0_0: Type = I32;
3673                         let expr1_0: Type = I32;
3674                         let expr2_0: Type = I32;
3675                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3676                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3677                         let expr5_0: Type = I32;
3678                         let expr6_0: u64 = 8388608;
3679                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3680                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3681                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3682                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3683                         return Some(expr10_0);
3684                     }
3685                     &Opcode::Popcnt => {
3686                         // Rule at src/isa/aarch64/lower.isle line 1093.
3687                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3688                         let expr1_0 = ScalarSize::Size32;
3689                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3690                         let expr3_0 = VectorSize::Size8x8;
3691                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3692                         let expr5_0: u8 = 0;
3693                         let expr6_0 = VectorSize::Size8x16;
3694                         let expr7_0 = constructor_mov_from_vec(ctx, expr4_0, expr5_0, &expr6_0)?;
3695                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
3696                         return Some(expr8_0);
3697                     }
3698                     _ => {}
3699                 }
3700             }
3701         }
3702         if pattern2_0 == I16 {
3703             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3704             if let &InstructionData::Unary {
3705                 opcode: ref pattern5_0,
3706                 arg: pattern5_1,
3707             } = &pattern4_0
3708             {
3709                 match pattern5_0 {
3710                     &Opcode::Bitrev => {
3711                         // Rule at src/isa/aarch64/lower.isle line 980.
3712                         let expr0_0: Type = I32;
3713                         let expr1_0: Type = I32;
3714                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3715                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3716                         let expr4_0: u8 = 16;
3717                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3718                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3719                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3720                         return Some(expr7_0);
3721                     }
3722                     &Opcode::Clz => {
3723                         // Rule at src/isa/aarch64/lower.isle line 998.
3724                         let expr0_0: Type = I32;
3725                         let expr1_0: Type = I32;
3726                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3727                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3728                         let expr4_0: u8 = 16;
3729                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3730                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3731                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3732                         return Some(expr7_0);
3733                     }
3734                     &Opcode::Cls => {
3735                         // Rule at src/isa/aarch64/lower.isle line 1045.
3736                         let expr0_0: Type = I32;
3737                         let expr1_0: Type = I32;
3738                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3739                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3740                         let expr4_0: u8 = 16;
3741                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3742                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3743                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3744                         return Some(expr7_0);
3745                     }
3746                     &Opcode::Ctz => {
3747                         // Rule at src/isa/aarch64/lower.isle line 1028.
3748                         let expr0_0: Type = I32;
3749                         let expr1_0: Type = I32;
3750                         let expr2_0: Type = I32;
3751                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3752                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3753                         let expr5_0: Type = I32;
3754                         let expr6_0: u64 = 32768;
3755                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3756                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3757                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3758                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3759                         return Some(expr10_0);
3760                     }
3761                     &Opcode::Popcnt => {
3762                         // Rule at src/isa/aarch64/lower.isle line 1099.
3763                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3764                         let expr1_0 = ScalarSize::Size32;
3765                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3766                         let expr3_0 = VectorSize::Size8x8;
3767                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3768                         let expr5_0 = VectorSize::Size8x8;
3769                         let expr6_0 = constructor_addp(ctx, expr4_0, expr4_0, &expr5_0)?;
3770                         let expr7_0: u8 = 0;
3771                         let expr8_0 = VectorSize::Size8x16;
3772                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3773                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3774                         return Some(expr10_0);
3775                     }
3776                     _ => {}
3777                 }
3778             }
3779         }
3780         if pattern2_0 == I32 {
3781             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3782             match &pattern4_0 {
3783                 &InstructionData::Binary {
3784                     opcode: ref pattern5_0,
3785                     args: ref pattern5_1,
3786                 } => {
3787                     match pattern5_0 {
3788                         &Opcode::Rotl => {
3789                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3790                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3791                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3792                                 if let &InstructionData::UnaryImm {
3793                                     opcode: ref pattern10_0,
3794                                     imm: pattern10_1,
3795                                 } = &pattern9_0
3796                                 {
3797                                     if let &Opcode::Iconst = pattern10_0 {
3798                                         let closure12 = || {
3799                                             let expr0_0: Type = I32;
3800                                             return Some(expr0_0);
3801                                         };
3802                                         if let Some(pattern12_0) = closure12() {
3803                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3804                                                 ctx,
3805                                                 pattern10_1,
3806                                                 pattern12_0,
3807                                             ) {
3808                                                 // Rule at src/isa/aarch64/lower.isle line 865.
3809                                                 let expr0_0: Type = I32;
3810                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3811                                                 let expr2_0: Type = I32;
3812                                                 let expr3_0 =
3813                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3814                                                 let expr4_0 = constructor_a64_rotr_imm(
3815                                                     ctx, expr0_0, expr1_0, expr3_0,
3816                                                 )?;
3817                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3818                                                 return Some(expr5_0);
3819                                             }
3820                                         }
3821                                     }
3822                                 }
3823                             }
3824                             // Rule at src/isa/aarch64/lower.isle line 855.
3825                             let expr0_0: Type = I32;
3826                             let expr1_0 = C::zero_reg(ctx);
3827                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3828                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3829                             let expr4_0: Type = I32;
3830                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3831                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3832                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3833                             return Some(expr7_0);
3834                         }
3835                         &Opcode::Rotr => {
3836                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3837                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3838                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3839                                 if let &InstructionData::UnaryImm {
3840                                     opcode: ref pattern10_0,
3841                                     imm: pattern10_1,
3842                                 } = &pattern9_0
3843                                 {
3844                                     if let &Opcode::Iconst = pattern10_0 {
3845                                         let closure12 = || {
3846                                             let expr0_0: Type = I32;
3847                                             return Some(expr0_0);
3848                                         };
3849                                         if let Some(pattern12_0) = closure12() {
3850                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3851                                                 ctx,
3852                                                 pattern10_1,
3853                                                 pattern12_0,
3854                                             ) {
3855                                                 // Rule at src/isa/aarch64/lower.isle line 907.
3856                                                 let expr0_0: Type = I32;
3857                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3858                                                 let expr2_0 = constructor_a64_rotr_imm(
3859                                                     ctx,
3860                                                     expr0_0,
3861                                                     expr1_0,
3862                                                     pattern13_0,
3863                                                 )?;
3864                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3865                                                 return Some(expr3_0);
3866                                             }
3867                                         }
3868                                     }
3869                                 }
3870                             }
3871                             // Rule at src/isa/aarch64/lower.isle line 895.
3872                             let expr0_0: Type = I32;
3873                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3874                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3875                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
3876                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3877                             return Some(expr4_0);
3878                         }
3879                         _ => {}
3880                     }
3881                 }
3882                 &InstructionData::Unary {
3883                     opcode: ref pattern5_0,
3884                     arg: pattern5_1,
3885                 } => {
3886                     if let &Opcode::Popcnt = pattern5_0 {
3887                         // Rule at src/isa/aarch64/lower.isle line 1105.
3888                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3889                         let expr1_0 = ScalarSize::Size32;
3890                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3891                         let expr3_0 = VectorSize::Size8x8;
3892                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3893                         let expr5_0 = VectorSize::Size8x8;
3894                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
3895                         let expr7_0: u8 = 0;
3896                         let expr8_0 = VectorSize::Size8x16;
3897                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3898                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3899                         return Some(expr10_0);
3900                     }
3901                 }
3902                 _ => {}
3903             }
3904         }
3905         if pattern2_0 == I64 {
3906             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3907             match &pattern4_0 {
3908                 &InstructionData::Binary {
3909                     opcode: ref pattern5_0,
3910                     args: ref pattern5_1,
3911                 } => {
3912                     match pattern5_0 {
3913                         &Opcode::Umulhi => {
3914                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3915                             // Rule at src/isa/aarch64/lower.isle line 367.
3916                             let expr0_0: Type = I64;
3917                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3918                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3919                             let expr3_0 = constructor_umulh(ctx, expr0_0, expr1_0, expr2_0)?;
3920                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3921                             return Some(expr4_0);
3922                         }
3923                         &Opcode::Smulhi => {
3924                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3925                             // Rule at src/isa/aarch64/lower.isle line 355.
3926                             let expr0_0: Type = I64;
3927                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3928                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3929                             let expr3_0 = constructor_smulh(ctx, expr0_0, expr1_0, expr2_0)?;
3930                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3931                             return Some(expr4_0);
3932                         }
3933                         &Opcode::Band => {
3934                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3935                             // Rule at src/isa/aarch64/lower.isle line 586.
3936                             let expr0_0 = ALUOp::And;
3937                             let expr1_0: Type = I64;
3938                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3939                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3940                             )?;
3941                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3942                             return Some(expr3_0);
3943                         }
3944                         &Opcode::Bor => {
3945                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3946                             // Rule at src/isa/aarch64/lower.isle line 599.
3947                             let expr0_0 = ALUOp::Orr;
3948                             let expr1_0: Type = I64;
3949                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3950                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3951                             )?;
3952                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3953                             return Some(expr3_0);
3954                         }
3955                         &Opcode::Bxor => {
3956                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3957                             // Rule at src/isa/aarch64/lower.isle line 612.
3958                             let expr0_0 = ALUOp::Eor;
3959                             let expr1_0: Type = I64;
3960                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3961                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3962                             )?;
3963                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3964                             return Some(expr3_0);
3965                         }
3966                         &Opcode::BandNot => {
3967                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3968                             // Rule at src/isa/aarch64/lower.isle line 625.
3969                             let expr0_0 = ALUOp::AndNot;
3970                             let expr1_0: Type = I64;
3971                             let expr2_0 = constructor_alu_rs_imm_logic(
3972                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3973                             )?;
3974                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3975                             return Some(expr3_0);
3976                         }
3977                         &Opcode::BorNot => {
3978                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3979                             // Rule at src/isa/aarch64/lower.isle line 638.
3980                             let expr0_0 = ALUOp::OrrNot;
3981                             let expr1_0: Type = I64;
3982                             let expr2_0 = constructor_alu_rs_imm_logic(
3983                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3984                             )?;
3985                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3986                             return Some(expr3_0);
3987                         }
3988                         &Opcode::BxorNot => {
3989                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3990                             // Rule at src/isa/aarch64/lower.isle line 648.
3991                             let expr0_0 = ALUOp::EorNot;
3992                             let expr1_0: Type = I64;
3993                             let expr2_0 = constructor_alu_rs_imm_logic(
3994                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3995                             )?;
3996                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3997                             return Some(expr3_0);
3998                         }
3999                         &Opcode::Rotl => {
4000                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4001                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
4002                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
4003                                 if let &InstructionData::UnaryImm {
4004                                     opcode: ref pattern10_0,
4005                                     imm: pattern10_1,
4006                                 } = &pattern9_0
4007                                 {
4008                                     if let &Opcode::Iconst = pattern10_0 {
4009                                         let closure12 = || {
4010                                             let expr0_0: Type = I64;
4011                                             return Some(expr0_0);
4012                                         };
4013                                         if let Some(pattern12_0) = closure12() {
4014                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4015                                                 ctx,
4016                                                 pattern10_1,
4017                                                 pattern12_0,
4018                                             ) {
4019                                                 // Rule at src/isa/aarch64/lower.isle line 869.
4020                                                 let expr0_0: Type = I64;
4021                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4022                                                 let expr2_0: Type = I64;
4023                                                 let expr3_0 =
4024                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
4025                                                 let expr4_0 = constructor_a64_rotr_imm(
4026                                                     ctx, expr0_0, expr1_0, expr3_0,
4027                                                 )?;
4028                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
4029                                                 return Some(expr5_0);
4030                                             }
4031                                         }
4032                                     }
4033                                 }
4034                             }
4035                             // Rule at src/isa/aarch64/lower.isle line 860.
4036                             let expr0_0: Type = I64;
4037                             let expr1_0 = C::zero_reg(ctx);
4038                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4039                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
4040                             let expr4_0: Type = I64;
4041                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
4042                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
4043                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
4044                             return Some(expr7_0);
4045                         }
4046                         &Opcode::Rotr => {
4047                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4048                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
4049                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
4050                                 if let &InstructionData::UnaryImm {
4051                                     opcode: ref pattern10_0,
4052                                     imm: pattern10_1,
4053                                 } = &pattern9_0
4054                                 {
4055                                     if let &Opcode::Iconst = pattern10_0 {
4056                                         let closure12 = || {
4057                                             let expr0_0: Type = I64;
4058                                             return Some(expr0_0);
4059                                         };
4060                                         if let Some(pattern12_0) = closure12() {
4061                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4062                                                 ctx,
4063                                                 pattern10_1,
4064                                                 pattern12_0,
4065                                             ) {
4066                                                 // Rule at src/isa/aarch64/lower.isle line 911.
4067                                                 let expr0_0: Type = I64;
4068                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4069                                                 let expr2_0 = constructor_a64_rotr_imm(
4070                                                     ctx,
4071                                                     expr0_0,
4072                                                     expr1_0,
4073                                                     pattern13_0,
4074                                                 )?;
4075                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4076                                                 return Some(expr3_0);
4077                                             }
4078                                         }
4079                                     }
4080                                 }
4081                             }
4082                             // Rule at src/isa/aarch64/lower.isle line 899.
4083                             let expr0_0: Type = I64;
4084                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4085                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4086                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
4087                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4088                             return Some(expr4_0);
4089                         }
4090                         &Opcode::Ishl => {
4091                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4092                             // Rule at src/isa/aarch64/lower.isle line 660.
4093                             let expr0_0 = ALUOp::Lsl;
4094                             let expr1_0: Type = I64;
4095                             let expr2_0 = C::put_in_reg(ctx, pattern7_0);
4096                             let expr3_0 =
4097                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4098                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4099                             return Some(expr4_0);
4100                         }
4101                         &Opcode::Ushr => {
4102                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4103                             // Rule at src/isa/aarch64/lower.isle line 744.
4104                             let expr0_0 = ALUOp::Lsr;
4105                             let expr1_0: Type = I64;
4106                             let expr2_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
4107                             let expr3_0 =
4108                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4109                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4110                             return Some(expr4_0);
4111                         }
4112                         &Opcode::Sshr => {
4113                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4114                             // Rule at src/isa/aarch64/lower.isle line 791.
4115                             let expr0_0 = ALUOp::Asr;
4116                             let expr1_0: Type = I64;
4117                             let expr2_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
4118                             let expr3_0 =
4119                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4120                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4121                             return Some(expr4_0);
4122                         }
4123                         _ => {}
4124                     }
4125                 }
4126                 &InstructionData::Unary {
4127                     opcode: ref pattern5_0,
4128                     arg: pattern5_1,
4129                 } => {
4130                     if let &Opcode::Popcnt = pattern5_0 {
4131                         // Rule at src/isa/aarch64/lower.isle line 1111.
4132                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4133                         let expr1_0 = ScalarSize::Size64;
4134                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
4135                         let expr3_0 = VectorSize::Size8x8;
4136                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
4137                         let expr5_0 = VectorSize::Size8x8;
4138                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
4139                         let expr7_0: u8 = 0;
4140                         let expr8_0 = VectorSize::Size8x16;
4141                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
4142                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
4143                         return Some(expr10_0);
4144                     }
4145                 }
4146                 _ => {}
4147             }
4148         }
4149         if pattern2_0 == I128 {
4150             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4151             match &pattern4_0 {
4152                 &InstructionData::Binary {
4153                     opcode: ref pattern5_0,
4154                     args: ref pattern5_1,
4155                 } => {
4156                     match pattern5_0 {
4157                         &Opcode::Iadd => {
4158                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4159                             // Rule at src/isa/aarch64/lower.isle line 79.
4160                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4161                             let expr1_0: usize = 0;
4162                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4163                             let expr3_0: usize = 1;
4164                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4165                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4166                             let expr6_0: usize = 0;
4167                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4168                             let expr8_0: usize = 1;
4169                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4170                             let expr10_0: Type = I64;
4171                             let expr11_0 =
4172                                 constructor_add_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4173                             let expr12_0: Type = I64;
4174                             let expr13_0 = constructor_adc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4175                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4176                             let expr15_0 = C::output(ctx, expr14_0);
4177                             return Some(expr15_0);
4178                         }
4179                         &Opcode::Isub => {
4180                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4181                             // Rule at src/isa/aarch64/lower.isle line 129.
4182                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4183                             let expr1_0: usize = 0;
4184                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4185                             let expr3_0: usize = 1;
4186                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4187                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4188                             let expr6_0: usize = 0;
4189                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4190                             let expr8_0: usize = 1;
4191                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4192                             let expr10_0: Type = I64;
4193                             let expr11_0 =
4194                                 constructor_sub_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4195                             let expr12_0: Type = I64;
4196                             let expr13_0 = constructor_sbc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4197                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4198                             let expr15_0 = C::output(ctx, expr14_0);
4199                             return Some(expr15_0);
4200                         }
4201                         &Opcode::Imul => {
4202                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4203                             // Rule at src/isa/aarch64/lower.isle line 183.
4204                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4205                             let expr1_0: usize = 0;
4206                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4207                             let expr3_0: usize = 1;
4208                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4209                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4210                             let expr6_0: usize = 0;
4211                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4212                             let expr8_0: usize = 1;
4213                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4214                             let expr10_0: Type = I64;
4215                             let expr11_0 = constructor_umulh(ctx, expr10_0, expr2_0, expr7_0)?;
4216                             let expr12_0 = constructor_madd64(ctx, expr2_0, expr9_0, expr11_0)?;
4217                             let expr13_0 = constructor_madd64(ctx, expr4_0, expr7_0, expr12_0)?;
4218                             let expr14_0 = C::zero_reg(ctx);
4219                             let expr15_0 = constructor_madd64(ctx, expr2_0, expr7_0, expr14_0)?;
4220                             let expr16_0 = C::value_regs(ctx, expr15_0, expr13_0);
4221                             let expr17_0 = C::output(ctx, expr16_0);
4222                             return Some(expr17_0);
4223                         }
4224                         &Opcode::Band => {
4225                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4226                             // Rule at src/isa/aarch64/lower.isle line 589.
4227                             let expr0_0 = ALUOp::And;
4228                             let expr1_0: Type = I64;
4229                             let expr2_0 = constructor_i128_alu_bitop(
4230                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4231                             )?;
4232                             let expr3_0 = C::output(ctx, expr2_0);
4233                             return Some(expr3_0);
4234                         }
4235                         &Opcode::Bor => {
4236                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4237                             // Rule at src/isa/aarch64/lower.isle line 602.
4238                             let expr0_0 = ALUOp::Orr;
4239                             let expr1_0: Type = I64;
4240                             let expr2_0 = constructor_i128_alu_bitop(
4241                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4242                             )?;
4243                             let expr3_0 = C::output(ctx, expr2_0);
4244                             return Some(expr3_0);
4245                         }
4246                         &Opcode::Bxor => {
4247                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4248                             // Rule at src/isa/aarch64/lower.isle line 615.
4249                             let expr0_0 = ALUOp::Eor;
4250                             let expr1_0: Type = I64;
4251                             let expr2_0 = constructor_i128_alu_bitop(
4252                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4253                             )?;
4254                             let expr3_0 = C::output(ctx, expr2_0);
4255                             return Some(expr3_0);
4256                         }
4257                         &Opcode::BandNot => {
4258                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4259                             // Rule at src/isa/aarch64/lower.isle line 628.
4260                             let expr0_0 = ALUOp::AndNot;
4261                             let expr1_0: Type = I64;
4262                             let expr2_0 = constructor_i128_alu_bitop(
4263                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4264                             )?;
4265                             let expr3_0 = C::output(ctx, expr2_0);
4266                             return Some(expr3_0);
4267                         }
4268                         &Opcode::BorNot => {
4269                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4270                             // Rule at src/isa/aarch64/lower.isle line 641.
4271                             let expr0_0 = ALUOp::OrrNot;
4272                             let expr1_0: Type = I64;
4273                             let expr2_0 = constructor_i128_alu_bitop(
4274                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4275                             )?;
4276                             let expr3_0 = C::output(ctx, expr2_0);
4277                             return Some(expr3_0);
4278                         }
4279                         &Opcode::BxorNot => {
4280                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4281                             // Rule at src/isa/aarch64/lower.isle line 651.
4282                             let expr0_0 = ALUOp::EorNot;
4283                             let expr1_0: Type = I64;
4284                             let expr2_0 = constructor_i128_alu_bitop(
4285                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4286                             )?;
4287                             let expr3_0 = C::output(ctx, expr2_0);
4288                             return Some(expr3_0);
4289                         }
4290                         &Opcode::Rotl => {
4291                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4292                             // Rule at src/isa/aarch64/lower.isle line 878.
4293                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4294                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4295                             let expr2_0: usize = 0;
4296                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4297                             let expr4_0: Type = I64;
4298                             let expr5_0: Type = I64;
4299                             let expr6_0: u64 = 128;
4300                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4301                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4302                             let expr9_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4303                             let expr10_0 = constructor_lower_ushr128(ctx, expr0_0, expr8_0)?;
4304                             let expr11_0: Type = I64;
4305                             let expr12_0: usize = 0;
4306                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4307                             let expr14_0: usize = 0;
4308                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4309                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4310                             let expr17_0: Type = I64;
4311                             let expr18_0: usize = 1;
4312                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4313                             let expr20_0: usize = 1;
4314                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4315                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4316                             let expr23_0 = C::value_regs(ctx, expr16_0, expr22_0);
4317                             let expr24_0 = C::output(ctx, expr23_0);
4318                             return Some(expr24_0);
4319                         }
4320                         &Opcode::Rotr => {
4321                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4322                             // Rule at src/isa/aarch64/lower.isle line 959.
4323                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4324                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4325                             let expr2_0: usize = 0;
4326                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4327                             let expr4_0: Type = I64;
4328                             let expr5_0: Type = I64;
4329                             let expr6_0: u64 = 128;
4330                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4331                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4332                             let expr9_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4333                             let expr10_0 = constructor_lower_shl128(ctx, expr0_0, expr8_0)?;
4334                             let expr11_0: Type = I64;
4335                             let expr12_0: usize = 1;
4336                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4337                             let expr14_0: usize = 1;
4338                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4339                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4340                             let expr17_0: Type = I64;
4341                             let expr18_0: usize = 0;
4342                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4343                             let expr20_0: usize = 0;
4344                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4345                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4346                             let expr23_0 = C::value_regs(ctx, expr22_0, expr16_0);
4347                             let expr24_0 = C::output(ctx, expr23_0);
4348                             return Some(expr24_0);
4349                         }
4350                         &Opcode::Ishl => {
4351                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4352                             // Rule at src/isa/aarch64/lower.isle line 664.
4353                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4354                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4355                             let expr2_0: usize = 0;
4356                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4357                             let expr4_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4358                             let expr5_0 = C::output(ctx, expr4_0);
4359                             return Some(expr5_0);
4360                         }
4361                         &Opcode::Ushr => {
4362                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4363                             // Rule at src/isa/aarch64/lower.isle line 748.
4364                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4365                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4366                             let expr2_0: usize = 0;
4367                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4368                             let expr4_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4369                             let expr5_0 = C::output(ctx, expr4_0);
4370                             return Some(expr5_0);
4371                         }
4372                         &Opcode::Sshr => {
4373                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4374                             // Rule at src/isa/aarch64/lower.isle line 795.
4375                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4376                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4377                             let expr2_0: usize = 0;
4378                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4379                             let expr4_0 = constructor_lower_sshr128(ctx, expr0_0, expr3_0)?;
4380                             let expr5_0 = C::output(ctx, expr4_0);
4381                             return Some(expr5_0);
4382                         }
4383                         _ => {}
4384                     }
4385                 }
4386                 &InstructionData::Unary {
4387                     opcode: ref pattern5_0,
4388                     arg: pattern5_1,
4389                 } => {
4390                     match pattern5_0 {
4391                         &Opcode::Bnot => {
4392                             // Rule at src/isa/aarch64/lower.isle line 569.
4393                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4394                             let expr1_0: usize = 0;
4395                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4396                             let expr3_0: usize = 1;
4397                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4398                             let expr5_0: Type = I64;
4399                             let expr6_0 = C::zero_reg(ctx);
4400                             let expr7_0 = constructor_orr_not(ctx, expr5_0, expr6_0, expr2_0)?;
4401                             let expr8_0: Type = I64;
4402                             let expr9_0 = C::zero_reg(ctx);
4403                             let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, expr4_0)?;
4404                             let expr11_0 = C::value_regs(ctx, expr7_0, expr10_0);
4405                             let expr12_0 = C::output(ctx, expr11_0);
4406                             return Some(expr12_0);
4407                         }
4408                         &Opcode::Bitrev => {
4409                             // Rule at src/isa/aarch64/lower.isle line 983.
4410                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4411                             let expr1_0: Type = I64;
4412                             let expr2_0: usize = 0;
4413                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4414                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4415                             let expr5_0: Type = I64;
4416                             let expr6_0: usize = 1;
4417                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4418                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4419                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4420                             let expr10_0 = C::output(ctx, expr9_0);
4421                             return Some(expr10_0);
4422                         }
4423                         &Opcode::Clz => {
4424                             // Rule at src/isa/aarch64/lower.isle line 1001.
4425                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4426                             let expr1_0 = constructor_lower_clz128(ctx, expr0_0)?;
4427                             let expr2_0 = C::output(ctx, expr1_0);
4428                             return Some(expr2_0);
4429                         }
4430                         &Opcode::Cls => {
4431                             // Rule at src/isa/aarch64/lower.isle line 1057.
4432                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4433                             let expr1_0: usize = 0;
4434                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4435                             let expr3_0: usize = 1;
4436                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4437                             let expr5_0: Type = I64;
4438                             let expr6_0 = constructor_a64_cls(ctx, expr5_0, expr2_0)?;
4439                             let expr7_0: Type = I64;
4440                             let expr8_0 = constructor_a64_cls(ctx, expr7_0, expr4_0)?;
4441                             let expr9_0: Type = I64;
4442                             let expr10_0 = constructor_eon(ctx, expr9_0, expr4_0, expr2_0)?;
4443                             let expr11_0: Type = I64;
4444                             let expr12_0: u8 = 63;
4445                             let expr13_0 = C::imm_shift_from_u8(ctx, expr12_0);
4446                             let expr14_0 = constructor_lsr_imm(ctx, expr11_0, expr10_0, expr13_0)?;
4447                             let expr15_0 = constructor_madd64(ctx, expr6_0, expr14_0, expr14_0)?;
4448                             let expr16_0: u8 = 63;
4449                             let expr17_0 = C::u8_into_imm12(ctx, expr16_0);
4450                             let expr18_0 = constructor_cmp64_imm(ctx, expr8_0, expr17_0)?;
4451                             let expr19_0 = Cond::Eq;
4452                             let expr20_0 = C::zero_reg(ctx);
4453                             let expr21_0 = constructor_csel(ctx, &expr19_0, expr15_0, expr20_0)?;
4454                             let expr22_0 = constructor_with_flags_reg(ctx, &expr18_0, &expr21_0)?;
4455                             let expr23_0: Type = I64;
4456                             let expr24_0 = constructor_add(ctx, expr23_0, expr22_0, expr8_0)?;
4457                             let expr25_0: Type = I64;
4458                             let expr26_0: u64 = 0;
4459                             let expr27_0 = constructor_imm(ctx, expr25_0, expr26_0)?;
4460                             let expr28_0 = C::value_regs(ctx, expr24_0, expr27_0);
4461                             let expr29_0 = C::output(ctx, expr28_0);
4462                             return Some(expr29_0);
4463                         }
4464                         &Opcode::Ctz => {
4465                             // Rule at src/isa/aarch64/lower.isle line 1031.
4466                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4467                             let expr1_0: Type = I64;
4468                             let expr2_0: usize = 0;
4469                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4470                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4471                             let expr5_0: Type = I64;
4472                             let expr6_0: usize = 1;
4473                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4474                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4475                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4476                             let expr10_0 = constructor_lower_clz128(ctx, expr9_0)?;
4477                             let expr11_0 = C::output(ctx, expr10_0);
4478                             return Some(expr11_0);
4479                         }
4480                         &Opcode::Popcnt => {
4481                             // Rule at src/isa/aarch64/lower.isle line 1117.
4482                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4483                             let expr1_0: usize = 0;
4484                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4485                             let expr3_0 = ScalarSize::Size64;
4486                             let expr4_0 = constructor_mov_to_fpu(ctx, expr2_0, &expr3_0)?;
4487                             let expr5_0: usize = 1;
4488                             let expr6_0 = C::value_regs_get(ctx, expr0_0, expr5_0);
4489                             let expr7_0: u8 = 1;
4490                             let expr8_0 = VectorSize::Size64x2;
4491                             let expr9_0 =
4492                                 constructor_mov_to_vec(ctx, expr4_0, expr6_0, expr7_0, &expr8_0)?;
4493                             let expr10_0 = VectorSize::Size8x16;
4494                             let expr11_0 = constructor_vec_cnt(ctx, expr9_0, &expr10_0)?;
4495                             let expr12_0 = VectorSize::Size8x16;
4496                             let expr13_0 = constructor_addv(ctx, expr11_0, &expr12_0)?;
4497                             let expr14_0: u8 = 0;
4498                             let expr15_0 = VectorSize::Size8x16;
4499                             let expr16_0 =
4500                                 constructor_mov_from_vec(ctx, expr13_0, expr14_0, &expr15_0)?;
4501                             let expr17_0: Type = I64;
4502                             let expr18_0: u64 = 0;
4503                             let expr19_0 = constructor_imm(ctx, expr17_0, expr18_0)?;
4504                             let expr20_0 = C::value_regs(ctx, expr16_0, expr19_0);
4505                             let expr21_0 = C::output(ctx, expr20_0);
4506                             return Some(expr21_0);
4507                         }
4508                         &Opcode::Uextend => {
4509                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4510                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4511                                 if let &InstructionData::BinaryImm8 {
4512                                     opcode: ref pattern9_0,
4513                                     arg: pattern9_1,
4514                                     imm: pattern9_2,
4515                                 } = &pattern8_0
4516                                 {
4517                                     if let &Opcode::Extractlane = pattern9_0 {
4518                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4519                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
4520                                         // Rule at src/isa/aarch64/lower.isle line 499.
4521                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4522                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
4523                                         let expr2_0 = constructor_mov_from_vec(
4524                                             ctx,
4525                                             expr0_0,
4526                                             pattern12_0,
4527                                             &expr1_0,
4528                                         )?;
4529                                         let expr3_0: Type = I64;
4530                                         let expr4_0: u64 = 0;
4531                                         let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
4532                                         let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
4533                                         let expr7_0 = C::output(ctx, expr6_0);
4534                                         return Some(expr7_0);
4535                                     }
4536                                 }
4537                             }
4538                             // Rule at src/isa/aarch64/lower.isle line 494.
4539                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
4540                             let expr1_0: Type = I64;
4541                             let expr2_0: u64 = 0;
4542                             let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
4543                             let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
4544                             let expr5_0 = C::output(ctx, expr4_0);
4545                             return Some(expr5_0);
4546                         }
4547                         &Opcode::Sextend => {
4548                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4549                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4550                                 if let &InstructionData::BinaryImm8 {
4551                                     opcode: ref pattern9_0,
4552                                     arg: pattern9_1,
4553                                     imm: pattern9_2,
4554                                 } = &pattern8_0
4555                                 {
4556                                     if let &Opcode::Extractlane = pattern9_0 {
4557                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4558                                         if pattern11_0 == I64X2 {
4559                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4560                                             // Rule at src/isa/aarch64/lower.isle line 543.
4561                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4562                                             let expr1_0 = VectorSize::Size64x2;
4563                                             let expr2_0 = constructor_mov_from_vec(
4564                                                 ctx,
4565                                                 expr0_0,
4566                                                 pattern13_0,
4567                                                 &expr1_0,
4568                                             )?;
4569                                             let expr3_0: Type = I64;
4570                                             let expr4_0: u8 = 63;
4571                                             let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
4572                                             let expr6_0 = constructor_asr_imm(
4573                                                 ctx, expr3_0, expr2_0, expr5_0,
4574                                             )?;
4575                                             let expr7_0 = C::value_regs(ctx, expr2_0, expr6_0);
4576                                             let expr8_0 = C::output(ctx, expr7_0);
4577                                             return Some(expr8_0);
4578                                         }
4579                                         if let Some(()) = C::not_i64x2(ctx, pattern11_0) {
4580                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4581                                             // Rule at src/isa/aarch64/lower.isle line 532.
4582                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4583                                             let expr1_0 =
4584                                                 constructor_vector_size(ctx, pattern11_0)?;
4585                                             let expr2_0: Type = I64;
4586                                             let expr3_0 = constructor_size_from_ty(ctx, expr2_0)?;
4587                                             let expr4_0 = constructor_mov_from_vec_signed(
4588                                                 ctx,
4589                                                 expr0_0,
4590                                                 pattern13_0,
4591                                                 &expr1_0,
4592                                                 &expr3_0,
4593                                             )?;
4594                                             let expr5_0: Type = I64;
4595                                             let expr6_0: u8 = 63;
4596                                             let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
4597                                             let expr8_0 = constructor_asr_imm(
4598                                                 ctx, expr5_0, expr4_0, expr7_0,
4599                                             )?;
4600                                             let expr9_0 = C::value_regs(ctx, expr4_0, expr8_0);
4601                                             let expr10_0 = C::output(ctx, expr9_0);
4602                                             return Some(expr10_0);
4603                                         }
4604                                     }
4605                                 }
4606                             }
4607                             // Rule at src/isa/aarch64/lower.isle line 522.
4608                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
4609                             let expr1_0: Type = I64;
4610                             let expr2_0: u8 = 63;
4611                             let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0);
4612                             let expr4_0 = constructor_asr_imm(ctx, expr1_0, expr0_0, expr3_0)?;
4613                             let expr5_0 = C::value_regs(ctx, expr0_0, expr4_0);
4614                             let expr6_0 = C::output(ctx, expr5_0);
4615                             return Some(expr6_0);
4616                         }
4617                         _ => {}
4618                     }
4619                 }
4620                 _ => {}
4621             }
4622         }
4623         if pattern2_0 == I8X16 {
4624             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4625             if let &InstructionData::Unary {
4626                 opcode: ref pattern5_0,
4627                 arg: pattern5_1,
4628             } = &pattern4_0
4629             {
4630                 if let &Opcode::Popcnt = pattern5_0 {
4631                     // Rule at src/isa/aarch64/lower.isle line 1125.
4632                     let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4633                     let expr1_0 = VectorSize::Size8x16;
4634                     let expr2_0 = constructor_vec_cnt(ctx, expr0_0, &expr1_0)?;
4635                     let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4636                     return Some(expr3_0);
4637                 }
4638             }
4639         }
4640         if pattern2_0 == I16X8 {
4641             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4642             if let &InstructionData::Binary {
4643                 opcode: ref pattern5_0,
4644                 args: ref pattern5_1,
4645             } = &pattern4_0
4646             {
4647                 if let &Opcode::Imul = pattern5_0 {
4648                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4649                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4650                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4651                         if let &InstructionData::Unary {
4652                             opcode: ref pattern10_0,
4653                             arg: pattern10_1,
4654                         } = &pattern9_0
4655                         {
4656                             match pattern10_0 {
4657                                 &Opcode::SwidenLow => {
4658                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4659                                     if pattern12_0 == I8X16 {
4660                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4661                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4662                                             if let &InstructionData::Unary {
4663                                                 opcode: ref pattern16_0,
4664                                                 arg: pattern16_1,
4665                                             } = &pattern15_0
4666                                             {
4667                                                 if let &Opcode::SwidenLow = pattern16_0 {
4668                                                     let pattern18_0 =
4669                                                         C::value_type(ctx, pattern16_1);
4670                                                     if pattern18_0 == I8X16 {
4671                                                         // Rule at src/isa/aarch64/lower.isle line 282.
4672                                                         let expr0_0 =
4673                                                             C::put_in_reg(ctx, pattern10_1);
4674                                                         let expr1_0 =
4675                                                             C::put_in_reg(ctx, pattern16_1);
4676                                                         let expr2_0: bool = false;
4677                                                         let expr3_0 = constructor_smull8(
4678                                                             ctx, expr0_0, expr1_0, expr2_0,
4679                                                         )?;
4680                                                         let expr4_0 =
4681                                                             constructor_output_reg(ctx, expr3_0)?;
4682                                                         return Some(expr4_0);
4683                                                     }
4684                                                 }
4685                                             }
4686                                         }
4687                                     }
4688                                 }
4689                                 &Opcode::SwidenHigh => {
4690                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4691                                     if pattern12_0 == I8X16 {
4692                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4693                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4694                                             if let &InstructionData::Unary {
4695                                                 opcode: ref pattern16_0,
4696                                                 arg: pattern16_1,
4697                                             } = &pattern15_0
4698                                             {
4699                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4700                                                     let pattern18_0 =
4701                                                         C::value_type(ctx, pattern16_1);
4702                                                     if pattern18_0 == I8X16 {
4703                                                         // Rule at src/isa/aarch64/lower.isle line 288.
4704                                                         let expr0_0 =
4705                                                             C::put_in_reg(ctx, pattern10_1);
4706                                                         let expr1_0 =
4707                                                             C::put_in_reg(ctx, pattern16_1);
4708                                                         let expr2_0: bool = true;
4709                                                         let expr3_0 = constructor_smull8(
4710                                                             ctx, expr0_0, expr1_0, expr2_0,
4711                                                         )?;
4712                                                         let expr4_0 =
4713                                                             constructor_output_reg(ctx, expr3_0)?;
4714                                                         return Some(expr4_0);
4715                                                     }
4716                                                 }
4717                                             }
4718                                         }
4719                                     }
4720                                 }
4721                                 &Opcode::UwidenLow => {
4722                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4723                                     if pattern12_0 == I8X16 {
4724                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4725                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4726                                             if let &InstructionData::Unary {
4727                                                 opcode: ref pattern16_0,
4728                                                 arg: pattern16_1,
4729                                             } = &pattern15_0
4730                                             {
4731                                                 if let &Opcode::UwidenLow = pattern16_0 {
4732                                                     let pattern18_0 =
4733                                                         C::value_type(ctx, pattern16_1);
4734                                                     if pattern18_0 == I8X16 {
4735                                                         // Rule at src/isa/aarch64/lower.isle line 294.
4736                                                         let expr0_0 =
4737                                                             C::put_in_reg(ctx, pattern10_1);
4738                                                         let expr1_0 =
4739                                                             C::put_in_reg(ctx, pattern16_1);
4740                                                         let expr2_0: bool = false;
4741                                                         let expr3_0 = constructor_umull8(
4742                                                             ctx, expr0_0, expr1_0, expr2_0,
4743                                                         )?;
4744                                                         let expr4_0 =
4745                                                             constructor_output_reg(ctx, expr3_0)?;
4746                                                         return Some(expr4_0);
4747                                                     }
4748                                                 }
4749                                             }
4750                                         }
4751                                     }
4752                                 }
4753                                 &Opcode::UwidenHigh => {
4754                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4755                                     if pattern12_0 == I8X16 {
4756                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4757                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4758                                             if let &InstructionData::Unary {
4759                                                 opcode: ref pattern16_0,
4760                                                 arg: pattern16_1,
4761                                             } = &pattern15_0
4762                                             {
4763                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4764                                                     let pattern18_0 =
4765                                                         C::value_type(ctx, pattern16_1);
4766                                                     if pattern18_0 == I8X16 {
4767                                                         // Rule at src/isa/aarch64/lower.isle line 300.
4768                                                         let expr0_0 =
4769                                                             C::put_in_reg(ctx, pattern10_1);
4770                                                         let expr1_0 =
4771                                                             C::put_in_reg(ctx, pattern16_1);
4772                                                         let expr2_0: bool = true;
4773                                                         let expr3_0 = constructor_umull8(
4774                                                             ctx, expr0_0, expr1_0, expr2_0,
4775                                                         )?;
4776                                                         let expr4_0 =
4777                                                             constructor_output_reg(ctx, expr3_0)?;
4778                                                         return Some(expr4_0);
4779                                                     }
4780                                                 }
4781                                             }
4782                                         }
4783                                     }
4784                                 }
4785                                 _ => {}
4786                             }
4787                         }
4788                     }
4789                 }
4790             }
4791         }
4792         if pattern2_0 == I32X4 {
4793             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4794             if let &InstructionData::Binary {
4795                 opcode: ref pattern5_0,
4796                 args: ref pattern5_1,
4797             } = &pattern4_0
4798             {
4799                 if let &Opcode::Imul = pattern5_0 {
4800                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4801                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4802                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4803                         if let &InstructionData::Unary {
4804                             opcode: ref pattern10_0,
4805                             arg: pattern10_1,
4806                         } = &pattern9_0
4807                         {
4808                             match pattern10_0 {
4809                                 &Opcode::SwidenLow => {
4810                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4811                                     if pattern12_0 == I16X8 {
4812                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4813                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4814                                             if let &InstructionData::Unary {
4815                                                 opcode: ref pattern16_0,
4816                                                 arg: pattern16_1,
4817                                             } = &pattern15_0
4818                                             {
4819                                                 if let &Opcode::SwidenLow = pattern16_0 {
4820                                                     let pattern18_0 =
4821                                                         C::value_type(ctx, pattern16_1);
4822                                                     if pattern18_0 == I16X8 {
4823                                                         // Rule at src/isa/aarch64/lower.isle line 306.
4824                                                         let expr0_0 =
4825                                                             C::put_in_reg(ctx, pattern10_1);
4826                                                         let expr1_0 =
4827                                                             C::put_in_reg(ctx, pattern16_1);
4828                                                         let expr2_0: bool = false;
4829                                                         let expr3_0 = constructor_smull16(
4830                                                             ctx, expr0_0, expr1_0, expr2_0,
4831                                                         )?;
4832                                                         let expr4_0 =
4833                                                             constructor_output_reg(ctx, expr3_0)?;
4834                                                         return Some(expr4_0);
4835                                                     }
4836                                                 }
4837                                             }
4838                                         }
4839                                     }
4840                                 }
4841                                 &Opcode::SwidenHigh => {
4842                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4843                                     if pattern12_0 == I16X8 {
4844                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4845                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4846                                             if let &InstructionData::Unary {
4847                                                 opcode: ref pattern16_0,
4848                                                 arg: pattern16_1,
4849                                             } = &pattern15_0
4850                                             {
4851                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4852                                                     let pattern18_0 =
4853                                                         C::value_type(ctx, pattern16_1);
4854                                                     if pattern18_0 == I16X8 {
4855                                                         // Rule at src/isa/aarch64/lower.isle line 312.
4856                                                         let expr0_0 =
4857                                                             C::put_in_reg(ctx, pattern10_1);
4858                                                         let expr1_0 =
4859                                                             C::put_in_reg(ctx, pattern16_1);
4860                                                         let expr2_0: bool = true;
4861                                                         let expr3_0 = constructor_smull16(
4862                                                             ctx, expr0_0, expr1_0, expr2_0,
4863                                                         )?;
4864                                                         let expr4_0 =
4865                                                             constructor_output_reg(ctx, expr3_0)?;
4866                                                         return Some(expr4_0);
4867                                                     }
4868                                                 }
4869                                             }
4870                                         }
4871                                     }
4872                                 }
4873                                 &Opcode::UwidenLow => {
4874                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4875                                     if pattern12_0 == I16X8 {
4876                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4877                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4878                                             if let &InstructionData::Unary {
4879                                                 opcode: ref pattern16_0,
4880                                                 arg: pattern16_1,
4881                                             } = &pattern15_0
4882                                             {
4883                                                 if let &Opcode::UwidenLow = pattern16_0 {
4884                                                     let pattern18_0 =
4885                                                         C::value_type(ctx, pattern16_1);
4886                                                     if pattern18_0 == I16X8 {
4887                                                         // Rule at src/isa/aarch64/lower.isle line 318.
4888                                                         let expr0_0 =
4889                                                             C::put_in_reg(ctx, pattern10_1);
4890                                                         let expr1_0 =
4891                                                             C::put_in_reg(ctx, pattern16_1);
4892                                                         let expr2_0: bool = false;
4893                                                         let expr3_0 = constructor_umull16(
4894                                                             ctx, expr0_0, expr1_0, expr2_0,
4895                                                         )?;
4896                                                         let expr4_0 =
4897                                                             constructor_output_reg(ctx, expr3_0)?;
4898                                                         return Some(expr4_0);
4899                                                     }
4900                                                 }
4901                                             }
4902                                         }
4903                                     }
4904                                 }
4905                                 &Opcode::UwidenHigh => {
4906                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4907                                     if pattern12_0 == I16X8 {
4908                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4909                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4910                                             if let &InstructionData::Unary {
4911                                                 opcode: ref pattern16_0,
4912                                                 arg: pattern16_1,
4913                                             } = &pattern15_0
4914                                             {
4915                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4916                                                     let pattern18_0 =
4917                                                         C::value_type(ctx, pattern16_1);
4918                                                     if pattern18_0 == I16X8 {
4919                                                         // Rule at src/isa/aarch64/lower.isle line 324.
4920                                                         let expr0_0 =
4921                                                             C::put_in_reg(ctx, pattern10_1);
4922                                                         let expr1_0 =
4923                                                             C::put_in_reg(ctx, pattern16_1);
4924                                                         let expr2_0: bool = true;
4925                                                         let expr3_0 = constructor_umull16(
4926                                                             ctx, expr0_0, expr1_0, expr2_0,
4927                                                         )?;
4928                                                         let expr4_0 =
4929                                                             constructor_output_reg(ctx, expr3_0)?;
4930                                                         return Some(expr4_0);
4931                                                     }
4932                                                 }
4933                                             }
4934                                         }
4935                                     }
4936                                 }
4937                                 _ => {}
4938                             }
4939                         }
4940                     }
4941                 }
4942             }
4943         }
4944         if pattern2_0 == I64X2 {
4945             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4946             if let &InstructionData::Binary {
4947                 opcode: ref pattern5_0,
4948                 args: ref pattern5_1,
4949             } = &pattern4_0
4950             {
4951                 if let &Opcode::Imul = pattern5_0 {
4952                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4953                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4954                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4955                         if let &InstructionData::Unary {
4956                             opcode: ref pattern10_0,
4957                             arg: pattern10_1,
4958                         } = &pattern9_0
4959                         {
4960                             match pattern10_0 {
4961                                 &Opcode::SwidenLow => {
4962                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4963                                     if pattern12_0 == I32X4 {
4964                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4965                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4966                                             if let &InstructionData::Unary {
4967                                                 opcode: ref pattern16_0,
4968                                                 arg: pattern16_1,
4969                                             } = &pattern15_0
4970                                             {
4971                                                 if let &Opcode::SwidenLow = pattern16_0 {
4972                                                     let pattern18_0 =
4973                                                         C::value_type(ctx, pattern16_1);
4974                                                     if pattern18_0 == I32X4 {
4975                                                         // Rule at src/isa/aarch64/lower.isle line 330.
4976                                                         let expr0_0 =
4977                                                             C::put_in_reg(ctx, pattern10_1);
4978                                                         let expr1_0 =
4979                                                             C::put_in_reg(ctx, pattern16_1);
4980                                                         let expr2_0: bool = false;
4981                                                         let expr3_0 = constructor_smull32(
4982                                                             ctx, expr0_0, expr1_0, expr2_0,
4983                                                         )?;
4984                                                         let expr4_0 =
4985                                                             constructor_output_reg(ctx, expr3_0)?;
4986                                                         return Some(expr4_0);
4987                                                     }
4988                                                 }
4989                                             }
4990                                         }
4991                                     }
4992                                 }
4993                                 &Opcode::SwidenHigh => {
4994                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4995                                     if pattern12_0 == I32X4 {
4996                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4997                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4998                                             if let &InstructionData::Unary {
4999                                                 opcode: ref pattern16_0,
5000                                                 arg: pattern16_1,
5001                                             } = &pattern15_0
5002                                             {
5003                                                 if let &Opcode::SwidenHigh = pattern16_0 {
5004                                                     let pattern18_0 =
5005                                                         C::value_type(ctx, pattern16_1);
5006                                                     if pattern18_0 == I32X4 {
5007                                                         // Rule at src/isa/aarch64/lower.isle line 336.
5008                                                         let expr0_0 =
5009                                                             C::put_in_reg(ctx, pattern10_1);
5010                                                         let expr1_0 =
5011                                                             C::put_in_reg(ctx, pattern16_1);
5012                                                         let expr2_0: bool = true;
5013                                                         let expr3_0 = constructor_smull32(
5014                                                             ctx, expr0_0, expr1_0, expr2_0,
5015                                                         )?;
5016                                                         let expr4_0 =
5017                                                             constructor_output_reg(ctx, expr3_0)?;
5018                                                         return Some(expr4_0);
5019                                                     }
5020                                                 }
5021                                             }
5022                                         }
5023                                     }
5024                                 }
5025                                 &Opcode::UwidenLow => {
5026                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5027                                     if pattern12_0 == I32X4 {
5028                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5029                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5030                                             if let &InstructionData::Unary {
5031                                                 opcode: ref pattern16_0,
5032                                                 arg: pattern16_1,
5033                                             } = &pattern15_0
5034                                             {
5035                                                 if let &Opcode::UwidenLow = pattern16_0 {
5036                                                     let pattern18_0 =
5037                                                         C::value_type(ctx, pattern16_1);
5038                                                     if pattern18_0 == I32X4 {
5039                                                         // Rule at src/isa/aarch64/lower.isle line 342.
5040                                                         let expr0_0 =
5041                                                             C::put_in_reg(ctx, pattern10_1);
5042                                                         let expr1_0 =
5043                                                             C::put_in_reg(ctx, pattern16_1);
5044                                                         let expr2_0: bool = false;
5045                                                         let expr3_0 = constructor_umull32(
5046                                                             ctx, expr0_0, expr1_0, expr2_0,
5047                                                         )?;
5048                                                         let expr4_0 =
5049                                                             constructor_output_reg(ctx, expr3_0)?;
5050                                                         return Some(expr4_0);
5051                                                     }
5052                                                 }
5053                                             }
5054                                         }
5055                                     }
5056                                 }
5057                                 &Opcode::UwidenHigh => {
5058                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5059                                     if pattern12_0 == I32X4 {
5060                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5061                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5062                                             if let &InstructionData::Unary {
5063                                                 opcode: ref pattern16_0,
5064                                                 arg: pattern16_1,
5065                                             } = &pattern15_0
5066                                             {
5067                                                 if let &Opcode::UwidenHigh = pattern16_0 {
5068                                                     let pattern18_0 =
5069                                                         C::value_type(ctx, pattern16_1);
5070                                                     if pattern18_0 == I32X4 {
5071                                                         // Rule at src/isa/aarch64/lower.isle line 348.
5072                                                         let expr0_0 =
5073                                                             C::put_in_reg(ctx, pattern10_1);
5074                                                         let expr1_0 =
5075                                                             C::put_in_reg(ctx, pattern16_1);
5076                                                         let expr2_0: bool = true;
5077                                                         let expr3_0 = constructor_umull32(
5078                                                             ctx, expr0_0, expr1_0, expr2_0,
5079                                                         )?;
5080                                                         let expr4_0 =
5081                                                             constructor_output_reg(ctx, expr3_0)?;
5082                                                         return Some(expr4_0);
5083                                                     }
5084                                                 }
5085                                             }
5086                                         }
5087                                     }
5088                                 }
5089                                 _ => {}
5090                             }
5091                         }
5092                     }
5093                     // Rule at src/isa/aarch64/lower.isle line 243.
5094                     let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5095                     let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5096                     let expr2_0 = VectorSize::Size32x4;
5097                     let expr3_0 = constructor_rev64(ctx, expr1_0, &expr2_0)?;
5098                     let expr4_0 = VectorSize::Size32x4;
5099                     let expr5_0 = constructor_mul(ctx, expr3_0, expr0_0, &expr4_0)?;
5100                     let expr6_0: bool = false;
5101                     let expr7_0 = constructor_xtn64(ctx, expr0_0, expr6_0)?;
5102                     let expr8_0 = VectorSize::Size32x4;
5103                     let expr9_0 = constructor_addp(ctx, expr5_0, expr5_0, &expr8_0)?;
5104                     let expr10_0: bool = false;
5105                     let expr11_0 = constructor_xtn64(ctx, expr1_0, expr10_0)?;
5106                     let expr12_0: bool = false;
5107                     let expr13_0 = constructor_shll32(ctx, expr9_0, expr12_0)?;
5108                     let expr14_0: bool = false;
5109                     let expr15_0 = constructor_umlal32(ctx, expr13_0, expr11_0, expr7_0, expr14_0)?;
5110                     let expr16_0 = constructor_output_reg(ctx, expr15_0)?;
5111                     return Some(expr16_0);
5112                 }
5113             }
5114         }
5115         let pattern3_0 = C::inst_data(ctx, pattern0_0);
5116         match &pattern3_0 {
5117             &InstructionData::NullAry {
5118                 opcode: ref pattern4_0,
5119             } => {
5120                 if let &Opcode::Null = pattern4_0 {
5121                     // Rule at src/isa/aarch64/lower.isle line 22.
5122                     let expr0_0: u64 = 0;
5123                     let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5124                     let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5125                     return Some(expr2_0);
5126                 }
5127             }
5128             &InstructionData::UnaryImm {
5129                 opcode: ref pattern4_0,
5130                 imm: pattern4_1,
5131             } => {
5132                 if let &Opcode::Iconst = pattern4_0 {
5133                     let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1);
5134                     // Rule at src/isa/aarch64/lower.isle line 9.
5135                     let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?;
5136                     let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
5137                     return Some(expr1_0);
5138                 }
5139             }
5140             &InstructionData::UnaryBool {
5141                 opcode: ref pattern4_0,
5142                 imm: pattern4_1,
5143             } => {
5144                 if let &Opcode::Bconst = pattern4_0 {
5145                     if pattern4_1 == true {
5146                         // Rule at src/isa/aarch64/lower.isle line 17.
5147                         let expr0_0: u64 = 1;
5148                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5149                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5150                         return Some(expr2_0);
5151                     }
5152                     if pattern4_1 == false {
5153                         // Rule at src/isa/aarch64/lower.isle line 14.
5154                         let expr0_0: u64 = 0;
5155                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5156                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5157                         return Some(expr2_0);
5158                     }
5159                 }
5160             }
5161             &InstructionData::Unary {
5162                 opcode: ref pattern4_0,
5163                 arg: pattern4_1,
5164             } => {
5165                 match pattern4_0 {
5166                     &Opcode::Bitrev => {
5167                         // Rule at src/isa/aarch64/lower.isle line 989.
5168                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5169                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5170                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5171                         return Some(expr2_0);
5172                     }
5173                     &Opcode::Clz => {
5174                         // Rule at src/isa/aarch64/lower.isle line 1004.
5175                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5176                         let expr1_0 = constructor_a64_clz(ctx, pattern2_0, expr0_0)?;
5177                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5178                         return Some(expr2_0);
5179                     }
5180                     &Opcode::Cls => {
5181                         // Rule at src/isa/aarch64/lower.isle line 1071.
5182                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5183                         let expr1_0 = constructor_a64_cls(ctx, pattern2_0, expr0_0)?;
5184                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5185                         return Some(expr2_0);
5186                     }
5187                     &Opcode::Ctz => {
5188                         // Rule at src/isa/aarch64/lower.isle line 1037.
5189                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5190                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5191                         let expr2_0 = constructor_a64_clz(ctx, pattern2_0, expr1_0)?;
5192                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5193                         return Some(expr3_0);
5194                     }
5195                     _ => {}
5196                 }
5197             }
5198             _ => {}
5199         }
5200         if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) {
5201             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5202             match &pattern4_0 {
5203                 &InstructionData::Binary {
5204                     opcode: ref pattern5_0,
5205                     args: ref pattern5_1,
5206                 } => {
5207                     match pattern5_0 {
5208                         &Opcode::Iadd => {
5209                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5210                             // Rule at src/isa/aarch64/lower.isle line 75.
5211                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5212                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5213                             let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5214                             let expr3_0 = constructor_add_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5215                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5216                             return Some(expr4_0);
5217                         }
5218                         &Opcode::Isub => {
5219                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5220                             // Rule at src/isa/aarch64/lower.isle line 125.
5221                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5222                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5223                             let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5224                             let expr3_0 = constructor_sub_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5225                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5226                             return Some(expr4_0);
5227                         }
5228                         _ => {}
5229                     }
5230                 }
5231                 &InstructionData::FloatCompare {
5232                     opcode: ref pattern5_0,
5233                     args: ref pattern5_1,
5234                     cond: ref pattern5_2,
5235                 } => {
5236                     if let &Opcode::Fcmp = pattern5_0 {
5237                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5238                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5239                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5240                             if let &InstructionData::Unary {
5241                                 opcode: ref pattern10_0,
5242                                 arg: pattern10_1,
5243                             } = &pattern9_0
5244                             {
5245                                 if let &Opcode::Splat = pattern10_0 {
5246                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5247                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5248                                         match &pattern13_0 {
5249                                             &InstructionData::UnaryIeee32 {
5250                                                 opcode: ref pattern14_0,
5251                                                 imm: pattern14_1,
5252                                             } => {
5253                                                 if let &Opcode::F32const = pattern14_0 {
5254                                                     if let Some(pattern16_0) =
5255                                                         C::zero_value_f32(ctx, pattern14_1)
5256                                                     {
5257                                                         if let Some(pattern17_0) =
5258                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5259                                                         {
5260                                                             // Rule at src/isa/aarch64/lower.isle line 1145.
5261                                                             let expr0_0 =
5262                                                                 C::put_in_reg(ctx, pattern7_1);
5263                                                             let expr1_0 = constructor_vector_size(
5264                                                                 ctx, pattern2_0,
5265                                                             )?;
5266                                                             let expr2_0 =
5267                                                                 constructor_float_cmp_zero_swap(
5268                                                                     ctx,
5269                                                                     &pattern17_0,
5270                                                                     expr0_0,
5271                                                                     &expr1_0,
5272                                                                 )?;
5273                                                             let expr3_0 =
5274                                                                 C::value_reg(ctx, expr2_0);
5275                                                             let expr4_0 = C::output(ctx, expr3_0);
5276                                                             return Some(expr4_0);
5277                                                         }
5278                                                         if let Some(pattern17_0) =
5279                                                             C::fcmp_zero_cond_not_eq(
5280                                                                 ctx, pattern5_2,
5281                                                             )
5282                                                         {
5283                                                             // Rule at src/isa/aarch64/lower.isle line 1140.
5284                                                             let expr0_0 =
5285                                                                 C::put_in_reg(ctx, pattern7_1);
5286                                                             let expr1_0 = constructor_vector_size(
5287                                                                 ctx, pattern2_0,
5288                                                             )?;
5289                                                             let expr2_0 = constructor_fcmeq0(
5290                                                                 ctx, expr0_0, &expr1_0,
5291                                                             )?;
5292                                                             let expr3_0 = constructor_not(
5293                                                                 ctx, expr2_0, &expr1_0,
5294                                                             )?;
5295                                                             let expr4_0 =
5296                                                                 C::value_reg(ctx, expr3_0);
5297                                                             let expr5_0 = C::output(ctx, expr4_0);
5298                                                             return Some(expr5_0);
5299                                                         }
5300                                                     }
5301                                                 }
5302                                             }
5303                                             &InstructionData::UnaryIeee64 {
5304                                                 opcode: ref pattern14_0,
5305                                                 imm: pattern14_1,
5306                                             } => {
5307                                                 if let &Opcode::F64const = pattern14_0 {
5308                                                     if let Some(pattern16_0) =
5309                                                         C::zero_value_f64(ctx, pattern14_1)
5310                                                     {
5311                                                         if let Some(pattern17_0) =
5312                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5313                                                         {
5314                                                             // Rule at src/isa/aarch64/lower.isle line 1167.
5315                                                             let expr0_0 =
5316                                                                 C::put_in_reg(ctx, pattern7_1);
5317                                                             let expr1_0 = constructor_vector_size(
5318                                                                 ctx, pattern2_0,
5319                                                             )?;
5320                                                             let expr2_0 =
5321                                                                 constructor_float_cmp_zero_swap(
5322                                                                     ctx,
5323                                                                     &pattern17_0,
5324                                                                     expr0_0,
5325                                                                     &expr1_0,
5326                                                                 )?;
5327                                                             let expr3_0 =
5328                                                                 C::value_reg(ctx, expr2_0);
5329                                                             let expr4_0 = C::output(ctx, expr3_0);
5330                                                             return Some(expr4_0);
5331                                                         }
5332                                                         if let Some(pattern17_0) =
5333                                                             C::fcmp_zero_cond_not_eq(
5334                                                                 ctx, pattern5_2,
5335                                                             )
5336                                                         {
5337                                                             // Rule at src/isa/aarch64/lower.isle line 1162.
5338                                                             let expr0_0 =
5339                                                                 C::put_in_reg(ctx, pattern7_1);
5340                                                             let expr1_0 = constructor_vector_size(
5341                                                                 ctx, pattern2_0,
5342                                                             )?;
5343                                                             let expr2_0 = constructor_fcmeq0(
5344                                                                 ctx, expr0_0, &expr1_0,
5345                                                             )?;
5346                                                             let expr3_0 = constructor_not(
5347                                                                 ctx, expr2_0, &expr1_0,
5348                                                             )?;
5349                                                             let expr4_0 =
5350                                                                 C::value_reg(ctx, expr3_0);
5351                                                             let expr5_0 = C::output(ctx, expr4_0);
5352                                                             return Some(expr5_0);
5353                                                         }
5354                                                     }
5355                                                 }
5356                                             }
5357                                             _ => {}
5358                                         }
5359                                     }
5360                                 }
5361                             }
5362                         }
5363                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5364                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5365                             if let &InstructionData::Unary {
5366                                 opcode: ref pattern10_0,
5367                                 arg: pattern10_1,
5368                             } = &pattern9_0
5369                             {
5370                                 if let &Opcode::Splat = pattern10_0 {
5371                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5372                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5373                                         match &pattern13_0 {
5374                                             &InstructionData::UnaryIeee32 {
5375                                                 opcode: ref pattern14_0,
5376                                                 imm: pattern14_1,
5377                                             } => {
5378                                                 if let &Opcode::F32const = pattern14_0 {
5379                                                     if let Some(pattern16_0) =
5380                                                         C::zero_value_f32(ctx, pattern14_1)
5381                                                     {
5382                                                         if let Some(pattern17_0) =
5383                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5384                                                         {
5385                                                             // Rule at src/isa/aarch64/lower.isle line 1135.
5386                                                             let expr0_0 =
5387                                                                 C::put_in_reg(ctx, pattern7_0);
5388                                                             let expr1_0 = constructor_vector_size(
5389                                                                 ctx, pattern2_0,
5390                                                             )?;
5391                                                             let expr2_0 =
5392                                                                 constructor_float_cmp_zero(
5393                                                                     ctx,
5394                                                                     &pattern17_0,
5395                                                                     expr0_0,
5396                                                                     &expr1_0,
5397                                                                 )?;
5398                                                             let expr3_0 =
5399                                                                 C::value_reg(ctx, expr2_0);
5400                                                             let expr4_0 = C::output(ctx, expr3_0);
5401                                                             return Some(expr4_0);
5402                                                         }
5403                                                         if let Some(pattern17_0) =
5404                                                             C::fcmp_zero_cond_not_eq(
5405                                                                 ctx, pattern5_2,
5406                                                             )
5407                                                         {
5408                                                             // Rule at src/isa/aarch64/lower.isle line 1130.
5409                                                             let expr0_0 =
5410                                                                 C::put_in_reg(ctx, pattern7_0);
5411                                                             let expr1_0 = constructor_vector_size(
5412                                                                 ctx, pattern2_0,
5413                                                             )?;
5414                                                             let expr2_0 = constructor_fcmeq0(
5415                                                                 ctx, expr0_0, &expr1_0,
5416                                                             )?;
5417                                                             let expr3_0 = constructor_not(
5418                                                                 ctx, expr2_0, &expr1_0,
5419                                                             )?;
5420                                                             let expr4_0 =
5421                                                                 C::value_reg(ctx, expr3_0);
5422                                                             let expr5_0 = C::output(ctx, expr4_0);
5423                                                             return Some(expr5_0);
5424                                                         }
5425                                                     }
5426                                                 }
5427                                             }
5428                                             &InstructionData::UnaryIeee64 {
5429                                                 opcode: ref pattern14_0,
5430                                                 imm: pattern14_1,
5431                                             } => {
5432                                                 if let &Opcode::F64const = pattern14_0 {
5433                                                     if let Some(pattern16_0) =
5434                                                         C::zero_value_f64(ctx, pattern14_1)
5435                                                     {
5436                                                         if let Some(pattern17_0) =
5437                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5438                                                         {
5439                                                             // Rule at src/isa/aarch64/lower.isle line 1157.
5440                                                             let expr0_0 =
5441                                                                 C::put_in_reg(ctx, pattern7_0);
5442                                                             let expr1_0 = constructor_vector_size(
5443                                                                 ctx, pattern2_0,
5444                                                             )?;
5445                                                             let expr2_0 =
5446                                                                 constructor_float_cmp_zero(
5447                                                                     ctx,
5448                                                                     &pattern17_0,
5449                                                                     expr0_0,
5450                                                                     &expr1_0,
5451                                                                 )?;
5452                                                             let expr3_0 =
5453                                                                 C::value_reg(ctx, expr2_0);
5454                                                             let expr4_0 = C::output(ctx, expr3_0);
5455                                                             return Some(expr4_0);
5456                                                         }
5457                                                         if let Some(pattern17_0) =
5458                                                             C::fcmp_zero_cond_not_eq(
5459                                                                 ctx, pattern5_2,
5460                                                             )
5461                                                         {
5462                                                             // Rule at src/isa/aarch64/lower.isle line 1152.
5463                                                             let expr0_0 =
5464                                                                 C::put_in_reg(ctx, pattern7_0);
5465                                                             let expr1_0 = constructor_vector_size(
5466                                                                 ctx, pattern2_0,
5467                                                             )?;
5468                                                             let expr2_0 = constructor_fcmeq0(
5469                                                                 ctx, expr0_0, &expr1_0,
5470                                                             )?;
5471                                                             let expr3_0 = constructor_not(
5472                                                                 ctx, expr2_0, &expr1_0,
5473                                                             )?;
5474                                                             let expr4_0 =
5475                                                                 C::value_reg(ctx, expr3_0);
5476                                                             let expr5_0 = C::output(ctx, expr4_0);
5477                                                             return Some(expr5_0);
5478                                                         }
5479                                                     }
5480                                                 }
5481                                             }
5482                                             _ => {}
5483                                         }
5484                                     }
5485                                 }
5486                             }
5487                         }
5488                     }
5489                 }
5490                 &InstructionData::IntCompare {
5491                     opcode: ref pattern5_0,
5492                     args: ref pattern5_1,
5493                     cond: ref pattern5_2,
5494                 } => {
5495                     if let &Opcode::Icmp = pattern5_0 {
5496                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5497                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5498                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5499                             if let &InstructionData::Unary {
5500                                 opcode: ref pattern10_0,
5501                                 arg: pattern10_1,
5502                             } = &pattern9_0
5503                             {
5504                                 if let &Opcode::Splat = pattern10_0 {
5505                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5506                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5507                                         if let &InstructionData::UnaryImm {
5508                                             opcode: ref pattern14_0,
5509                                             imm: pattern14_1,
5510                                         } = &pattern13_0
5511                                         {
5512                                             if let &Opcode::Iconst = pattern14_0 {
5513                                                 if let Some(pattern16_0) =
5514                                                     C::zero_value(ctx, pattern14_1)
5515                                                 {
5516                                                     if let Some(pattern17_0) =
5517                                                         C::icmp_zero_cond(ctx, pattern5_2)
5518                                                     {
5519                                                         // Rule at src/isa/aarch64/lower.isle line 1189.
5520                                                         let expr0_0 =
5521                                                             C::put_in_reg(ctx, pattern7_1);
5522                                                         let expr1_0 = constructor_vector_size(
5523                                                             ctx, pattern2_0,
5524                                                         )?;
5525                                                         let expr2_0 =
5526                                                             constructor_int_cmp_zero_swap(
5527                                                                 ctx,
5528                                                                 &pattern17_0,
5529                                                                 expr0_0,
5530                                                                 &expr1_0,
5531                                                             )?;
5532                                                         let expr3_0 = C::value_reg(ctx, expr2_0);
5533                                                         let expr4_0 = C::output(ctx, expr3_0);
5534                                                         return Some(expr4_0);
5535                                                     }
5536                                                     if let Some(pattern17_0) =
5537                                                         C::icmp_zero_cond_not_eq(ctx, pattern5_2)
5538                                                     {
5539                                                         // Rule at src/isa/aarch64/lower.isle line 1184.
5540                                                         let expr0_0 =
5541                                                             C::put_in_reg(ctx, pattern7_1);
5542                                                         let expr1_0 = constructor_vector_size(
5543                                                             ctx, pattern2_0,
5544                                                         )?;
5545                                                         let expr2_0 = constructor_cmeq0(
5546                                                             ctx, expr0_0, &expr1_0,
5547                                                         )?;
5548                                                         let expr3_0 = constructor_not(
5549                                                             ctx, expr2_0, &expr1_0,
5550                                                         )?;
5551                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5552                                                         let expr5_0 = C::output(ctx, expr4_0);
5553                                                         return Some(expr5_0);
5554                                                     }
5555                                                 }
5556                                             }
5557                                         }
5558                                     }
5559                                 }
5560                             }
5561                         }
5562                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5563                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5564                             if let &InstructionData::Unary {
5565                                 opcode: ref pattern10_0,
5566                                 arg: pattern10_1,
5567                             } = &pattern9_0
5568                             {
5569                                 if let &Opcode::Splat = pattern10_0 {
5570                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5571                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5572                                         if let &InstructionData::UnaryImm {
5573                                             opcode: ref pattern14_0,
5574                                             imm: pattern14_1,
5575                                         } = &pattern13_0
5576                                         {
5577                                             if let &Opcode::Iconst = pattern14_0 {
5578                                                 if let Some(pattern16_0) =
5579                                                     C::zero_value(ctx, pattern14_1)
5580                                                 {
5581                                                     if let Some(pattern17_0) =
5582                                                         C::icmp_zero_cond(ctx, pattern5_2)
5583                                                     {
5584                                                         // Rule at src/isa/aarch64/lower.isle line 1179.
5585                                                         let expr0_0 =
5586                                                             C::put_in_reg(ctx, pattern7_0);
5587                                                         let expr1_0 = constructor_vector_size(
5588                                                             ctx, pattern2_0,
5589                                                         )?;
5590                                                         let expr2_0 = constructor_int_cmp_zero(
5591                                                             ctx,
5592                                                             &pattern17_0,
5593                                                             expr0_0,
5594                                                             &expr1_0,
5595                                                         )?;
5596                                                         let expr3_0 = C::value_reg(ctx, expr2_0);
5597                                                         let expr4_0 = C::output(ctx, expr3_0);
5598                                                         return Some(expr4_0);
5599                                                     }
5600                                                     if let Some(pattern17_0) =
5601                                                         C::icmp_zero_cond_not_eq(ctx, pattern5_2)
5602                                                     {
5603                                                         // Rule at src/isa/aarch64/lower.isle line 1174.
5604                                                         let expr0_0 =
5605                                                             C::put_in_reg(ctx, pattern7_0);
5606                                                         let expr1_0 = constructor_vector_size(
5607                                                             ctx, pattern2_0,
5608                                                         )?;
5609                                                         let expr2_0 = constructor_cmeq0(
5610                                                             ctx, expr0_0, &expr1_0,
5611                                                         )?;
5612                                                         let expr3_0 = constructor_not(
5613                                                             ctx, expr2_0, &expr1_0,
5614                                                         )?;
5615                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5616                                                         let expr5_0 = C::output(ctx, expr4_0);
5617                                                         return Some(expr5_0);
5618                                                     }
5619                                                 }
5620                                             }
5621                                         }
5622                                     }
5623                                 }
5624                             }
5625                         }
5626                     }
5627                 }
5628                 _ => {}
5629             }
5630         }
5631         if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
5632             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5633             if let &InstructionData::Binary {
5634                 opcode: ref pattern5_0,
5635                 args: ref pattern5_1,
5636             } = &pattern4_0
5637             {
5638                 match pattern5_0 {
5639                     &Opcode::Rotl => {
5640                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5641                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5642                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5643                             if let &InstructionData::UnaryImm {
5644                                 opcode: ref pattern10_0,
5645                                 imm: pattern10_1,
5646                             } = &pattern9_0
5647                             {
5648                                 if let &Opcode::Iconst = pattern10_0 {
5649                                     let closure12 = || {
5650                                         return Some(pattern3_0);
5651                                     };
5652                                     if let Some(pattern12_0) = closure12() {
5653                                         if let Some(pattern13_0) =
5654                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5655                                         {
5656                                             // Rule at src/isa/aarch64/lower.isle line 843.
5657                                             let expr0_0 =
5658                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5659                                             let expr1_0 =
5660                                                 C::negate_imm_shift(ctx, pattern3_0, pattern13_0);
5661                                             let expr2_0 = constructor_small_rotr_imm(
5662                                                 ctx, pattern3_0, expr0_0, expr1_0,
5663                                             )?;
5664                                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5665                                             return Some(expr3_0);
5666                                         }
5667                                     }
5668                                 }
5669                             }
5670                         }
5671                         // Rule at src/isa/aarch64/lower.isle line 838.
5672                         let expr0_0: Type = I32;
5673                         let expr1_0 = C::zero_reg(ctx);
5674                         let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5675                         let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
5676                         let expr4_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5677                         let expr5_0 = constructor_small_rotr(ctx, pattern3_0, expr4_0, expr3_0)?;
5678                         let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
5679                         return Some(expr6_0);
5680                     }
5681                     &Opcode::Rotr => {
5682                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5683                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5684                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5685                             if let &InstructionData::UnaryImm {
5686                                 opcode: ref pattern10_0,
5687                                 imm: pattern10_1,
5688                             } = &pattern9_0
5689                             {
5690                                 if let &Opcode::Iconst = pattern10_0 {
5691                                     let closure12 = || {
5692                                         return Some(pattern3_0);
5693                                     };
5694                                     if let Some(pattern12_0) = closure12() {
5695                                         if let Some(pattern13_0) =
5696                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5697                                         {
5698                                             // Rule at src/isa/aarch64/lower.isle line 903.
5699                                             let expr0_0 =
5700                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5701                                             let expr1_0 = constructor_small_rotr_imm(
5702                                                 ctx,
5703                                                 pattern3_0,
5704                                                 expr0_0,
5705                                                 pattern13_0,
5706                                             )?;
5707                                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5708                                             return Some(expr2_0);
5709                                         }
5710                                     }
5711                                 }
5712                             }
5713                         }
5714                         // Rule at src/isa/aarch64/lower.isle line 891.
5715                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5716                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5717                         let expr2_0 = constructor_small_rotr(ctx, pattern3_0, expr0_0, expr1_0)?;
5718                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5719                         return Some(expr3_0);
5720                     }
5721                     _ => {}
5722                 }
5723             }
5724         }
5725         if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
5726             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5727             if let &InstructionData::Binary {
5728                 opcode: ref pattern5_0,
5729                 args: ref pattern5_1,
5730             } = &pattern4_0
5731             {
5732                 match pattern5_0 {
5733                     &Opcode::Umulhi => {
5734                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5735                         // Rule at src/isa/aarch64/lower.isle line 370.
5736                         let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5737                         let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?;
5738                         let expr2_0 = C::zero_reg(ctx);
5739                         let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
5740                         let expr4_0: Type = I64;
5741                         let expr5_0 = C::ty_bits(ctx, pattern3_0);
5742                         let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
5743                         let expr7_0 = constructor_lsr_imm(ctx, expr4_0, expr3_0, expr6_0)?;
5744                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
5745                         return Some(expr8_0);
5746                     }
5747                     &Opcode::Smulhi => {
5748                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5749                         // Rule at src/isa/aarch64/lower.isle line 358.
5750                         let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5751                         let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?;
5752                         let expr2_0 = C::zero_reg(ctx);
5753                         let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
5754                         let expr4_0: Type = I64;
5755                         let expr5_0 = C::ty_bits(ctx, pattern3_0);
5756                         let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
5757                         let expr7_0 = constructor_asr_imm(ctx, expr4_0, expr3_0, expr6_0)?;
5758                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
5759                         return Some(expr8_0);
5760                     }
5761                     &Opcode::Band => {
5762                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5763                         // Rule at src/isa/aarch64/lower.isle line 583.
5764                         let expr0_0 = ALUOp::And;
5765                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5766                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5767                         )?;
5768                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5769                         return Some(expr2_0);
5770                     }
5771                     &Opcode::Bor => {
5772                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5773                         // Rule at src/isa/aarch64/lower.isle line 596.
5774                         let expr0_0 = ALUOp::Orr;
5775                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5776                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5777                         )?;
5778                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5779                         return Some(expr2_0);
5780                     }
5781                     &Opcode::Bxor => {
5782                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5783                         // Rule at src/isa/aarch64/lower.isle line 609.
5784                         let expr0_0 = ALUOp::Eor;
5785                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5786                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5787                         )?;
5788                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5789                         return Some(expr2_0);
5790                     }
5791                     &Opcode::BandNot => {
5792                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5793                         // Rule at src/isa/aarch64/lower.isle line 622.
5794                         let expr0_0 = ALUOp::AndNot;
5795                         let expr1_0 = constructor_alu_rs_imm_logic(
5796                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5797                         )?;
5798                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5799                         return Some(expr2_0);
5800                     }
5801                     &Opcode::BorNot => {
5802                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5803                         // Rule at src/isa/aarch64/lower.isle line 635.
5804                         let expr0_0 = ALUOp::OrrNot;
5805                         let expr1_0 = constructor_alu_rs_imm_logic(
5806                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5807                         )?;
5808                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5809                         return Some(expr2_0);
5810                     }
5811                     &Opcode::BxorNot => {
5812                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5813                         // Rule at src/isa/aarch64/lower.isle line 645.
5814                         let expr0_0 = ALUOp::EorNot;
5815                         let expr1_0: Type = I32;
5816                         let expr2_0 = constructor_alu_rs_imm_logic(
5817                             ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
5818                         )?;
5819                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5820                         return Some(expr3_0);
5821                     }
5822                     &Opcode::Ishl => {
5823                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5824                         // Rule at src/isa/aarch64/lower.isle line 656.
5825                         let expr0_0 = ALUOp::Lsl;
5826                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
5827                         let expr2_0 =
5828                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5829                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5830                         return Some(expr3_0);
5831                     }
5832                     &Opcode::Ushr => {
5833                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5834                         // Rule at src/isa/aarch64/lower.isle line 740.
5835                         let expr0_0 = ALUOp::Lsr;
5836                         let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5837                         let expr2_0 =
5838                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5839                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5840                         return Some(expr3_0);
5841                     }
5842                     &Opcode::Sshr => {
5843                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5844                         // Rule at src/isa/aarch64/lower.isle line 787.
5845                         let expr0_0 = ALUOp::Asr;
5846                         let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
5847                         let expr2_0 =
5848                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5849                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5850                         return Some(expr3_0);
5851                     }
5852                     _ => {}
5853                 }
5854             }
5855         }
5856         if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
5857             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5858             match &pattern4_0 {
5859                 &InstructionData::Binary {
5860                     opcode: ref pattern5_0,
5861                     args: ref pattern5_1,
5862                 } => {
5863                     match pattern5_0 {
5864                         &Opcode::Iadd => {
5865                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5866                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5867                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5868                                 match &pattern9_0 {
5869                                     &InstructionData::UnaryImm {
5870                                         opcode: ref pattern10_0,
5871                                         imm: pattern10_1,
5872                                     } => {
5873                                         if let &Opcode::Iconst = pattern10_0 {
5874                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5875                                             if let Some(pattern13_0) =
5876                                                 C::imm12_from_u64(ctx, pattern12_0)
5877                                             {
5878                                                 // Rule at src/isa/aarch64/lower.isle line 37.
5879                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5880                                                 let expr1_0 = constructor_add_imm(
5881                                                     ctx,
5882                                                     pattern3_0,
5883                                                     expr0_0,
5884                                                     pattern13_0,
5885                                                 )?;
5886                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5887                                                 return Some(expr2_0);
5888                                             }
5889                                             if let Some(pattern13_0) =
5890                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5891                                             {
5892                                                 // Rule at src/isa/aarch64/lower.isle line 45.
5893                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5894                                                 let expr1_0 = constructor_sub_imm(
5895                                                     ctx,
5896                                                     pattern3_0,
5897                                                     expr0_0,
5898                                                     pattern13_0,
5899                                                 )?;
5900                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5901                                                 return Some(expr2_0);
5902                                             }
5903                                         }
5904                                     }
5905                                     &InstructionData::Binary {
5906                                         opcode: ref pattern10_0,
5907                                         args: ref pattern10_1,
5908                                     } => {
5909                                         match pattern10_0 {
5910                                             &Opcode::Imul => {
5911                                                 let (pattern12_0, pattern12_1) =
5912                                                     C::unpack_value_array_2(ctx, pattern10_1);
5913                                                 // Rule at src/isa/aarch64/lower.isle line 70.
5914                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5915                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5916                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5917                                                 let expr3_0 = constructor_madd(
5918                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5919                                                 )?;
5920                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5921                                                 return Some(expr4_0);
5922                                             }
5923                                             &Opcode::Ishl => {
5924                                                 let (pattern12_0, pattern12_1) =
5925                                                     C::unpack_value_array_2(ctx, pattern10_1);
5926                                                 if let Some(pattern13_0) =
5927                                                     C::def_inst(ctx, pattern12_1)
5928                                                 {
5929                                                     let pattern14_0 =
5930                                                         C::inst_data(ctx, pattern13_0);
5931                                                     if let &InstructionData::UnaryImm {
5932                                                         opcode: ref pattern15_0,
5933                                                         imm: pattern15_1,
5934                                                     } = &pattern14_0
5935                                                     {
5936                                                         if let &Opcode::Iconst = pattern15_0 {
5937                                                             let closure17 = || {
5938                                                                 return Some(pattern3_0);
5939                                                             };
5940                                                             if let Some(pattern17_0) = closure17() {
5941                                                                 if let Some(pattern18_0) =
5942                                                                     C::lshl_from_imm64(
5943                                                                         ctx,
5944                                                                         pattern15_1,
5945                                                                         pattern17_0,
5946                                                                     )
5947                                                                 {
5948                                                                     // Rule at src/isa/aarch64/lower.isle line 62.
5949                                                                     let expr0_0 = C::put_in_reg(
5950                                                                         ctx, pattern7_1,
5951                                                                     );
5952                                                                     let expr1_0 = C::put_in_reg(
5953                                                                         ctx,
5954                                                                         pattern12_0,
5955                                                                     );
5956                                                                     let expr2_0 =
5957                                                                         constructor_add_shift(
5958                                                                             ctx,
5959                                                                             pattern3_0,
5960                                                                             expr0_0,
5961                                                                             expr1_0,
5962                                                                             pattern18_0,
5963                                                                         )?;
5964                                                                     let expr3_0 =
5965                                                                         constructor_output_reg(
5966                                                                             ctx, expr2_0,
5967                                                                         )?;
5968                                                                     return Some(expr3_0);
5969                                                                 }
5970                                                             }
5971                                                         }
5972                                                     }
5973                                                 }
5974                                             }
5975                                             _ => {}
5976                                         }
5977                                     }
5978                                     _ => {}
5979                                 }
5980                             }
5981                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0)
5982                             {
5983                                 // Rule at src/isa/aarch64/lower.isle line 53.
5984                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5985                                 let expr1_0 =
5986                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5987                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5988                                 return Some(expr2_0);
5989                             }
5990                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5991                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5992                                 match &pattern9_0 {
5993                                     &InstructionData::UnaryImm {
5994                                         opcode: ref pattern10_0,
5995                                         imm: pattern10_1,
5996                                     } => {
5997                                         if let &Opcode::Iconst = pattern10_0 {
5998                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5999                                             if let Some(pattern13_0) =
6000                                                 C::imm12_from_u64(ctx, pattern12_0)
6001                                             {
6002                                                 // Rule at src/isa/aarch64/lower.isle line 34.
6003                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6004                                                 let expr1_0 = constructor_add_imm(
6005                                                     ctx,
6006                                                     pattern3_0,
6007                                                     expr0_0,
6008                                                     pattern13_0,
6009                                                 )?;
6010                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6011                                                 return Some(expr2_0);
6012                                             }
6013                                             if let Some(pattern13_0) =
6014                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
6015                                             {
6016                                                 // Rule at src/isa/aarch64/lower.isle line 42.
6017                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6018                                                 let expr1_0 = constructor_sub_imm(
6019                                                     ctx,
6020                                                     pattern3_0,
6021                                                     expr0_0,
6022                                                     pattern13_0,
6023                                                 )?;
6024                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6025                                                 return Some(expr2_0);
6026                                             }
6027                                         }
6028                                     }
6029                                     &InstructionData::Binary {
6030                                         opcode: ref pattern10_0,
6031                                         args: ref pattern10_1,
6032                                     } => {
6033                                         match pattern10_0 {
6034                                             &Opcode::Imul => {
6035                                                 let (pattern12_0, pattern12_1) =
6036                                                     C::unpack_value_array_2(ctx, pattern10_1);
6037                                                 // Rule at src/isa/aarch64/lower.isle line 67.
6038                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
6039                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
6040                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
6041                                                 let expr3_0 = constructor_madd(
6042                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
6043                                                 )?;
6044                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6045                                                 return Some(expr4_0);
6046                                             }
6047                                             &Opcode::Ishl => {
6048                                                 let (pattern12_0, pattern12_1) =
6049                                                     C::unpack_value_array_2(ctx, pattern10_1);
6050                                                 if let Some(pattern13_0) =
6051                                                     C::def_inst(ctx, pattern12_1)
6052                                                 {
6053                                                     let pattern14_0 =
6054                                                         C::inst_data(ctx, pattern13_0);
6055                                                     if let &InstructionData::UnaryImm {
6056                                                         opcode: ref pattern15_0,
6057                                                         imm: pattern15_1,
6058                                                     } = &pattern14_0
6059                                                     {
6060                                                         if let &Opcode::Iconst = pattern15_0 {
6061                                                             let closure17 = || {
6062                                                                 return Some(pattern3_0);
6063                                                             };
6064                                                             if let Some(pattern17_0) = closure17() {
6065                                                                 if let Some(pattern18_0) =
6066                                                                     C::lshl_from_imm64(
6067                                                                         ctx,
6068                                                                         pattern15_1,
6069                                                                         pattern17_0,
6070                                                                     )
6071                                                                 {
6072                                                                     // Rule at src/isa/aarch64/lower.isle line 58.
6073                                                                     let expr0_0 = C::put_in_reg(
6074                                                                         ctx, pattern7_0,
6075                                                                     );
6076                                                                     let expr1_0 = C::put_in_reg(
6077                                                                         ctx,
6078                                                                         pattern12_0,
6079                                                                     );
6080                                                                     let expr2_0 =
6081                                                                         constructor_add_shift(
6082                                                                             ctx,
6083                                                                             pattern3_0,
6084                                                                             expr0_0,
6085                                                                             expr1_0,
6086                                                                             pattern18_0,
6087                                                                         )?;
6088                                                                     let expr3_0 =
6089                                                                         constructor_output_reg(
6090                                                                             ctx, expr2_0,
6091                                                                         )?;
6092                                                                     return Some(expr3_0);
6093                                                                 }
6094                                                             }
6095                                                         }
6096                                                     }
6097                                                 }
6098                                             }
6099                                             _ => {}
6100                                         }
6101                                     }
6102                                     _ => {}
6103                                 }
6104                             }
6105                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
6106                             {
6107                                 // Rule at src/isa/aarch64/lower.isle line 50.
6108                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6109                                 let expr1_0 =
6110                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6111                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6112                                 return Some(expr2_0);
6113                             }
6114                             // Rule at src/isa/aarch64/lower.isle line 30.
6115                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6116                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6117                             let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, expr1_0)?;
6118                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6119                             return Some(expr3_0);
6120                         }
6121                         &Opcode::Isub => {
6122                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6123                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6124                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6125                                 match &pattern9_0 {
6126                                     &InstructionData::UnaryImm {
6127                                         opcode: ref pattern10_0,
6128                                         imm: pattern10_1,
6129                                     } => {
6130                                         if let &Opcode::Iconst = pattern10_0 {
6131                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
6132                                             if let Some(pattern13_0) =
6133                                                 C::imm12_from_u64(ctx, pattern12_0)
6134                                             {
6135                                                 // Rule at src/isa/aarch64/lower.isle line 105.
6136                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6137                                                 let expr1_0 = constructor_sub_imm(
6138                                                     ctx,
6139                                                     pattern3_0,
6140                                                     expr0_0,
6141                                                     pattern13_0,
6142                                                 )?;
6143                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6144                                                 return Some(expr2_0);
6145                                             }
6146                                             if let Some(pattern13_0) =
6147                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
6148                                             {
6149                                                 // Rule at src/isa/aarch64/lower.isle line 110.
6150                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6151                                                 let expr1_0 = constructor_add_imm(
6152                                                     ctx,
6153                                                     pattern3_0,
6154                                                     expr0_0,
6155                                                     pattern13_0,
6156                                                 )?;
6157                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6158                                                 return Some(expr2_0);
6159                                             }
6160                                         }
6161                                     }
6162                                     &InstructionData::Binary {
6163                                         opcode: ref pattern10_0,
6164                                         args: ref pattern10_1,
6165                                     } => {
6166                                         if let &Opcode::Ishl = pattern10_0 {
6167                                             let (pattern12_0, pattern12_1) =
6168                                                 C::unpack_value_array_2(ctx, pattern10_1);
6169                                             if let Some(pattern13_0) = C::def_inst(ctx, pattern12_1)
6170                                             {
6171                                                 let pattern14_0 = C::inst_data(ctx, pattern13_0);
6172                                                 if let &InstructionData::UnaryImm {
6173                                                     opcode: ref pattern15_0,
6174                                                     imm: pattern15_1,
6175                                                 } = &pattern14_0
6176                                                 {
6177                                                     if let &Opcode::Iconst = pattern15_0 {
6178                                                         let closure17 = || {
6179                                                             return Some(pattern3_0);
6180                                                         };
6181                                                         if let Some(pattern17_0) = closure17() {
6182                                                             if let Some(pattern18_0) =
6183                                                                 C::lshl_from_imm64(
6184                                                                     ctx,
6185                                                                     pattern15_1,
6186                                                                     pattern17_0,
6187                                                                 )
6188                                                             {
6189                                                                 // Rule at src/isa/aarch64/lower.isle line 120.
6190                                                                 let expr0_0 =
6191                                                                     C::put_in_reg(ctx, pattern7_0);
6192                                                                 let expr1_0 =
6193                                                                     C::put_in_reg(ctx, pattern12_0);
6194                                                                 let expr2_0 =
6195                                                                     constructor_sub_shift(
6196                                                                         ctx,
6197                                                                         pattern3_0,
6198                                                                         expr0_0,
6199                                                                         expr1_0,
6200                                                                         pattern18_0,
6201                                                                     )?;
6202                                                                 let expr3_0 =
6203                                                                     constructor_output_reg(
6204                                                                         ctx, expr2_0,
6205                                                                     )?;
6206                                                                 return Some(expr3_0);
6207                                                             }
6208                                                         }
6209                                                     }
6210                                                 }
6211                                             }
6212                                         }
6213                                     }
6214                                     _ => {}
6215                                 }
6216                             }
6217                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
6218                             {
6219                                 // Rule at src/isa/aarch64/lower.isle line 115.
6220                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6221                                 let expr1_0 =
6222                                     constructor_sub_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6223                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6224                                 return Some(expr2_0);
6225                             }
6226                             // Rule at src/isa/aarch64/lower.isle line 101.
6227                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6228                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6229                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
6230                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6231                             return Some(expr3_0);
6232                         }
6233                         &Opcode::Imul => {
6234                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6235                             // Rule at src/isa/aarch64/lower.isle line 179.
6236                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6237                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6238                             let expr2_0 = C::zero_reg(ctx);
6239                             let expr3_0 =
6240                                 constructor_madd(ctx, pattern3_0, expr0_0, expr1_0, expr2_0)?;
6241                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6242                             return Some(expr4_0);
6243                         }
6244                         &Opcode::Udiv => {
6245                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6246                             // Rule at src/isa/aarch64/lower.isle line 384.
6247                             let expr0_0: Type = I64;
6248                             let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
6249                             let expr2_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
6250                             let expr3_0 = constructor_a64_udiv(ctx, expr0_0, expr1_0, expr2_0)?;
6251                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6252                             return Some(expr4_0);
6253                         }
6254                         &Opcode::Sdiv => {
6255                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6256                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6257                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6258                                 if let &InstructionData::UnaryImm {
6259                                     opcode: ref pattern10_0,
6260                                     imm: pattern10_1,
6261                                 } = &pattern9_0
6262                                 {
6263                                     if let &Opcode::Iconst = pattern10_0 {
6264                                         if let Some(pattern12_0) =
6265                                             C::safe_divisor_from_imm64(ctx, pattern10_1)
6266                                         {
6267                                             // Rule at src/isa/aarch64/lower.isle line 430.
6268                                             let expr0_0: Type = I64;
6269                                             let expr1_0 =
6270                                                 constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6271                                             let expr2_0 =
6272                                                 constructor_imm(ctx, pattern3_0, pattern12_0)?;
6273                                             let expr3_0 = constructor_a64_sdiv(
6274                                                 ctx, expr0_0, expr1_0, expr2_0,
6275                                             )?;
6276                                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6277                                             return Some(expr4_0);
6278                                         }
6279                                     }
6280                                 }
6281                             }
6282                             // Rule at src/isa/aarch64/lower.isle line 417.
6283                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6284                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
6285                             let expr2_0 = constructor_trap_if_div_overflow(
6286                                 ctx, pattern3_0, expr0_0, expr1_0,
6287                             )?;
6288                             let expr3_0: Type = I64;
6289                             let expr4_0 = constructor_a64_sdiv(ctx, expr3_0, expr2_0, expr1_0)?;
6290                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6291                             return Some(expr5_0);
6292                         }
6293                         &Opcode::Urem => {
6294                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6295                             // Rule at src/isa/aarch64/lower.isle line 458.
6296                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
6297                             let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
6298                             let expr2_0: Type = I64;
6299                             let expr3_0 = constructor_a64_udiv(ctx, expr2_0, expr0_0, expr1_0)?;
6300                             let expr4_0 = constructor_msub64(ctx, expr3_0, expr1_0, expr0_0)?;
6301                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6302                             return Some(expr5_0);
6303                         }
6304                         &Opcode::Srem => {
6305                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6306                             // Rule at src/isa/aarch64/lower.isle line 465.
6307                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6308                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
6309                             let expr2_0: Type = I64;
6310                             let expr3_0 = constructor_a64_sdiv(ctx, expr2_0, expr0_0, expr1_0)?;
6311                             let expr4_0 = constructor_msub64(ctx, expr3_0, expr1_0, expr0_0)?;
6312                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6313                             return Some(expr5_0);
6314                         }
6315                         _ => {}
6316                     }
6317                 }
6318                 &InstructionData::Unary {
6319                     opcode: ref pattern5_0,
6320                     arg: pattern5_1,
6321                 } => {
6322                     match pattern5_0 {
6323                         &Opcode::Ineg => {
6324                             // Rule at src/isa/aarch64/lower.isle line 169.
6325                             let expr0_0 = C::zero_reg(ctx);
6326                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6327                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
6328                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6329                             return Some(expr3_0);
6330                         }
6331                         &Opcode::Bnot => {
6332                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6333                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6334                                 if let &InstructionData::Binary {
6335                                     opcode: ref pattern9_0,
6336                                     args: ref pattern9_1,
6337                                 } = &pattern8_0
6338                                 {
6339                                     if let &Opcode::Ishl = pattern9_0 {
6340                                         let (pattern11_0, pattern11_1) =
6341                                             C::unpack_value_array_2(ctx, pattern9_1);
6342                                         if let Some(pattern12_0) = C::def_inst(ctx, pattern11_1) {
6343                                             let pattern13_0 = C::inst_data(ctx, pattern12_0);
6344                                             if let &InstructionData::UnaryImm {
6345                                                 opcode: ref pattern14_0,
6346                                                 imm: pattern14_1,
6347                                             } = &pattern13_0
6348                                             {
6349                                                 if let &Opcode::Iconst = pattern14_0 {
6350                                                     let closure16 = || {
6351                                                         return Some(pattern3_0);
6352                                                     };
6353                                                     if let Some(pattern16_0) = closure16() {
6354                                                         if let Some(pattern17_0) =
6355                                                             C::lshl_from_imm64(
6356                                                                 ctx,
6357                                                                 pattern14_1,
6358                                                                 pattern16_0,
6359                                                             )
6360                                                         {
6361                                                             // Rule at src/isa/aarch64/lower.isle line 564.
6362                                                             let expr0_0 = C::zero_reg(ctx);
6363                                                             let expr1_0 =
6364                                                                 C::put_in_reg(ctx, pattern11_0);
6365                                                             let expr2_0 =
6366                                                                 constructor_orr_not_shift(
6367                                                                     ctx,
6368                                                                     pattern3_0,
6369                                                                     expr0_0,
6370                                                                     expr1_0,
6371                                                                     pattern17_0,
6372                                                                 )?;
6373                                                             let expr3_0 = constructor_output_reg(
6374                                                                 ctx, expr2_0,
6375                                                             )?;
6376                                                             return Some(expr3_0);
6377                                                         }
6378                                                     }
6379                                                 }
6380                                             }
6381                                         }
6382                                     }
6383                                 }
6384                             }
6385                             // Rule at src/isa/aarch64/lower.isle line 559.
6386                             let expr0_0 = C::zero_reg(ctx);
6387                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6388                             let expr2_0 = constructor_orr_not(ctx, pattern3_0, expr0_0, expr1_0)?;
6389                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6390                             return Some(expr3_0);
6391                         }
6392                         &Opcode::Uextend => {
6393                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6394                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6395                                 if let &InstructionData::BinaryImm8 {
6396                                     opcode: ref pattern9_0,
6397                                     arg: pattern9_1,
6398                                     imm: pattern9_2,
6399                                 } = &pattern8_0
6400                                 {
6401                                     if let &Opcode::Extractlane = pattern9_0 {
6402                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6403                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6404                                         // Rule at src/isa/aarch64/lower.isle line 481.
6405                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6406                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6407                                         let expr2_0 = constructor_mov_from_vec(
6408                                             ctx,
6409                                             expr0_0,
6410                                             pattern12_0,
6411                                             &expr1_0,
6412                                         )?;
6413                                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6414                                         return Some(expr3_0);
6415                                     }
6416                                 }
6417                             }
6418                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6419                             if let Some(pattern8_0) = C::sinkable_atomic_load(ctx, pattern5_1) {
6420                                 // Rule at src/isa/aarch64/lower.isle line 488.
6421                                 let expr0_0 = C::sink_atomic_load(ctx, &pattern8_0);
6422                                 let expr1_0 = constructor_load_acquire(ctx, pattern7_0, expr0_0)?;
6423                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6424                                 return Some(expr2_0);
6425                             }
6426                             // Rule at src/isa/aarch64/lower.isle line 476.
6427                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6428                             let expr1_0: bool = false;
6429                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6430                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6431                             let expr4_0 =
6432                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6433                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6434                             return Some(expr5_0);
6435                         }
6436                         &Opcode::Sextend => {
6437                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6438                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6439                                 if let &InstructionData::BinaryImm8 {
6440                                     opcode: ref pattern9_0,
6441                                     arg: pattern9_1,
6442                                     imm: pattern9_2,
6443                                 } = &pattern8_0
6444                                 {
6445                                     if let &Opcode::Extractlane = pattern9_0 {
6446                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6447                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6448                                         // Rule at src/isa/aarch64/lower.isle line 513.
6449                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6450                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6451                                         let expr2_0 = constructor_size_from_ty(ctx, pattern3_0)?;
6452                                         let expr3_0 = constructor_mov_from_vec_signed(
6453                                             ctx,
6454                                             expr0_0,
6455                                             pattern12_0,
6456                                             &expr1_0,
6457                                             &expr2_0,
6458                                         )?;
6459                                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6460                                         return Some(expr4_0);
6461                                     }
6462                                 }
6463                             }
6464                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6465                             // Rule at src/isa/aarch64/lower.isle line 508.
6466                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6467                             let expr1_0: bool = true;
6468                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6469                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6470                             let expr4_0 =
6471                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6472                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6473                             return Some(expr5_0);
6474                         }
6475                         _ => {}
6476                     }
6477                 }
6478                 _ => {}
6479             }
6480         }
6481         if let Some(pattern3_0) = C::ty_vec128(ctx, pattern2_0) {
6482             let pattern4_0 = C::inst_data(ctx, pattern0_0);
6483             match &pattern4_0 {
6484                 &InstructionData::Binary {
6485                     opcode: ref pattern5_0,
6486                     args: ref pattern5_1,
6487                 } => {
6488                     match pattern5_0 {
6489                         &Opcode::UaddSat => {
6490                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6491                             // Rule at src/isa/aarch64/lower.isle line 148.
6492                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6493                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6494                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6495                             let expr3_0 = constructor_uqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6496                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6497                             return Some(expr4_0);
6498                         }
6499                         &Opcode::SaddSat => {
6500                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6501                             // Rule at src/isa/aarch64/lower.isle line 153.
6502                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6503                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6504                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6505                             let expr3_0 = constructor_sqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6506                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6507                             return Some(expr4_0);
6508                         }
6509                         &Opcode::UsubSat => {
6510                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6511                             // Rule at src/isa/aarch64/lower.isle line 158.
6512                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6513                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6514                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6515                             let expr3_0 = constructor_uqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6516                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6517                             return Some(expr4_0);
6518                         }
6519                         &Opcode::SsubSat => {
6520                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6521                             // Rule at src/isa/aarch64/lower.isle line 163.
6522                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6523                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6524                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6525                             let expr3_0 = constructor_sqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6526                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6527                             return Some(expr4_0);
6528                         }
6529                         &Opcode::Band => {
6530                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6531                             // Rule at src/isa/aarch64/lower.isle line 591.
6532                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6533                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6534                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6535                             let expr3_0 = constructor_and_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6536                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6537                             return Some(expr4_0);
6538                         }
6539                         &Opcode::Bor => {
6540                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6541                             // Rule at src/isa/aarch64/lower.isle line 604.
6542                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6543                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6544                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6545                             let expr3_0 = constructor_orr_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6546                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6547                             return Some(expr4_0);
6548                         }
6549                         &Opcode::Bxor => {
6550                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6551                             // Rule at src/isa/aarch64/lower.isle line 617.
6552                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6553                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6554                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6555                             let expr3_0 = constructor_eor_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6556                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6557                             return Some(expr4_0);
6558                         }
6559                         &Opcode::BandNot => {
6560                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6561                             // Rule at src/isa/aarch64/lower.isle line 630.
6562                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6563                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6564                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6565                             let expr3_0 = constructor_bic_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6566                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6567                             return Some(expr4_0);
6568                         }
6569                         &Opcode::Ishl => {
6570                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6571                             // Rule at src/isa/aarch64/lower.isle line 694.
6572                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6573                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6574                             let expr2_0 = constructor_vec_dup(ctx, expr1_0, &expr0_0)?;
6575                             let expr3_0 = C::put_in_reg(ctx, pattern7_0);
6576                             let expr4_0 = constructor_sshl(ctx, expr3_0, expr2_0, &expr0_0)?;
6577                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6578                             return Some(expr5_0);
6579                         }
6580                         &Opcode::Ushr => {
6581                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6582                             // Rule at src/isa/aarch64/lower.isle line 752.
6583                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6584                             let expr1_0: Type = I32;
6585                             let expr2_0 = C::zero_reg(ctx);
6586                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6587                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6588                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6589                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6590                             let expr7_0 = constructor_ushl(ctx, expr6_0, expr5_0, &expr0_0)?;
6591                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6592                             return Some(expr8_0);
6593                         }
6594                         &Opcode::Sshr => {
6595                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6596                             // Rule at src/isa/aarch64/lower.isle line 801.
6597                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6598                             let expr1_0: Type = I32;
6599                             let expr2_0 = C::zero_reg(ctx);
6600                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6601                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6602                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6603                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6604                             let expr7_0 = constructor_sshl(ctx, expr6_0, expr5_0, &expr0_0)?;
6605                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6606                             return Some(expr8_0);
6607                         }
6608                         _ => {}
6609                     }
6610                 }
6611                 &InstructionData::Unary {
6612                     opcode: ref pattern5_0,
6613                     arg: pattern5_1,
6614                 } => {
6615                     match pattern5_0 {
6616                         &Opcode::Ineg => {
6617                             // Rule at src/isa/aarch64/lower.isle line 173.
6618                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6619                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6620                             let expr2_0 = constructor_neg(ctx, expr0_0, &expr1_0)?;
6621                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6622                             return Some(expr3_0);
6623                         }
6624                         &Opcode::Bnot => {
6625                             // Rule at src/isa/aarch64/lower.isle line 578.
6626                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6627                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6628                             let expr2_0 = constructor_not(ctx, expr0_0, &expr1_0)?;
6629                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6630                             return Some(expr3_0);
6631                         }
6632                         _ => {}
6633                     }
6634                 }
6635                 _ => {}
6636             }
6637             if let Some(()) = C::not_i64x2(ctx, pattern3_0) {
6638                 let pattern5_0 = C::inst_data(ctx, pattern0_0);
6639                 if let &InstructionData::Binary {
6640                     opcode: ref pattern6_0,
6641                     args: ref pattern6_1,
6642                 } = &pattern5_0
6643                 {
6644                     if let &Opcode::Imul = pattern6_0 {
6645                         let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
6646                         // Rule at src/isa/aarch64/lower.isle line 211.
6647                         let expr0_0 = C::put_in_reg(ctx, pattern8_0);
6648                         let expr1_0 = C::put_in_reg(ctx, pattern8_1);
6649                         let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6650                         let expr3_0 = constructor_mul(ctx, expr0_0, expr1_0, &expr2_0)?;
6651                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6652                         return Some(expr4_0);
6653                     }
6654                 }
6655             }
6656         }
6657     }
6658     return None;
6659 }
6660 
6661 // Generated as internal constructor for term put_nonzero_in_reg_zext64.
6662 pub fn constructor_put_nonzero_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6663     let pattern0_0 = arg0;
6664     let pattern1_0 = C::value_type(ctx, pattern0_0);
6665     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6666         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6667         if let &InstructionData::UnaryImm {
6668             opcode: ref pattern4_0,
6669             imm: pattern4_1,
6670         } = &pattern3_0
6671         {
6672             if let &Opcode::Iconst = pattern4_0 {
6673                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6674                     // Rule at src/isa/aarch64/lower.isle line 394.
6675                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6676                     return Some(expr0_0);
6677                 }
6678             }
6679         }
6680     }
6681     // Rule at src/isa/aarch64/lower.isle line 389.
6682     let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern0_0)?;
6683     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6684     return Some(expr1_0);
6685 }
6686 
6687 // Generated as internal constructor for term put_nonzero_in_reg_sext64.
6688 pub fn constructor_put_nonzero_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6689     let pattern0_0 = arg0;
6690     let pattern1_0 = C::value_type(ctx, pattern0_0);
6691     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6692         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6693         if let &InstructionData::UnaryImm {
6694             opcode: ref pattern4_0,
6695             imm: pattern4_1,
6696         } = &pattern3_0
6697         {
6698             if let &Opcode::Iconst = pattern4_0 {
6699                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6700                     // Rule at src/isa/aarch64/lower.isle line 440.
6701                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6702                     return Some(expr0_0);
6703                 }
6704             }
6705         }
6706     }
6707     // Rule at src/isa/aarch64/lower.isle line 435.
6708     let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern0_0)?;
6709     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6710     return Some(expr1_0);
6711 }
6712 
6713 // Generated as internal constructor for term lower_shl128.
6714 pub fn constructor_lower_shl128<C: Context>(
6715     ctx: &mut C,
6716     arg0: ValueRegs,
6717     arg1: Reg,
6718 ) -> Option<ValueRegs> {
6719     let pattern0_0 = arg0;
6720     let pattern1_0 = arg1;
6721     // Rule at src/isa/aarch64/lower.isle line 677.
6722     let expr0_0: usize = 0;
6723     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6724     let expr2_0: usize = 1;
6725     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6726     let expr4_0: Type = I64;
6727     let expr5_0 = constructor_lsl(ctx, expr4_0, expr1_0, pattern1_0)?;
6728     let expr6_0: Type = I64;
6729     let expr7_0 = constructor_lsl(ctx, expr6_0, expr3_0, pattern1_0)?;
6730     let expr8_0: Type = I32;
6731     let expr9_0 = C::zero_reg(ctx);
6732     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6733     let expr11_0: Type = I64;
6734     let expr12_0: Type = I64;
6735     let expr13_0: u8 = 1;
6736     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6737     let expr15_0 = constructor_lsr_imm(ctx, expr12_0, expr1_0, expr14_0)?;
6738     let expr16_0 = constructor_lsr(ctx, expr11_0, expr15_0, expr10_0)?;
6739     let expr17_0: Type = I64;
6740     let expr18_0 = constructor_orr(ctx, expr17_0, expr7_0, expr16_0)?;
6741     let expr19_0: Type = I64;
6742     let expr20_0: Type = I64;
6743     let expr21_0: u64 = 64;
6744     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6745     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6746     let expr24_0 = Cond::Ne;
6747     let expr25_0 = C::zero_reg(ctx);
6748     let expr26_0 = constructor_csel(ctx, &expr24_0, expr25_0, expr5_0)?;
6749     let expr27_0 = Cond::Ne;
6750     let expr28_0 = constructor_csel(ctx, &expr27_0, expr5_0, expr18_0)?;
6751     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr26_0, &expr28_0)?;
6752     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6753     return Some(expr30_0);
6754 }
6755 
6756 // Generated as internal constructor for term do_shift.
6757 pub fn constructor_do_shift<C: Context>(
6758     ctx: &mut C,
6759     arg0: &ALUOp,
6760     arg1: Type,
6761     arg2: Reg,
6762     arg3: Value,
6763 ) -> Option<Reg> {
6764     let pattern0_0 = arg0;
6765     let pattern1_0 = arg1;
6766     let pattern2_0 = arg2;
6767     let pattern3_0 = arg3;
6768     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
6769         let pattern5_0 = C::inst_data(ctx, pattern4_0);
6770         if let &InstructionData::UnaryImm {
6771             opcode: ref pattern6_0,
6772             imm: pattern6_1,
6773         } = &pattern5_0
6774         {
6775             if let &Opcode::Iconst = pattern6_0 {
6776                 let closure8 = || {
6777                     return Some(pattern1_0);
6778                 };
6779                 if let Some(pattern8_0) = closure8() {
6780                     if let Some(pattern9_0) = C::imm_shift_from_imm64(ctx, pattern6_1, pattern8_0) {
6781                         // Rule at src/isa/aarch64/lower.isle line 734.
6782                         let expr0_0 = constructor_alu_rr_imm_shift(
6783                             ctx, pattern0_0, pattern1_0, pattern2_0, pattern9_0,
6784                         )?;
6785                         return Some(expr0_0);
6786                     }
6787                 }
6788             }
6789         }
6790     }
6791     let pattern0_0 = arg0;
6792     let pattern1_0 = arg1;
6793     if pattern1_0 == I32 {
6794         let pattern3_0 = arg2;
6795         let pattern4_0 = arg3;
6796         // Rule at src/isa/aarch64/lower.isle line 725.
6797         let expr0_0: Type = I32;
6798         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6799         let expr2_0: usize = 0;
6800         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6801         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6802         return Some(expr4_0);
6803     }
6804     if pattern1_0 == I64 {
6805         let pattern3_0 = arg2;
6806         let pattern4_0 = arg3;
6807         // Rule at src/isa/aarch64/lower.isle line 726.
6808         let expr0_0: Type = I64;
6809         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6810         let expr2_0: usize = 0;
6811         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6812         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6813         return Some(expr4_0);
6814     }
6815     if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
6816         let pattern3_0 = arg2;
6817         let pattern4_0 = arg3;
6818         // Rule at src/isa/aarch64/lower.isle line 716.
6819         let expr0_0 = C::put_in_regs(ctx, pattern4_0);
6820         let expr1_0: usize = 0;
6821         let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
6822         let expr3_0: Type = I32;
6823         let expr4_0 = C::shift_mask(ctx, pattern2_0);
6824         let expr5_0 = constructor_and_imm(ctx, expr3_0, expr2_0, expr4_0)?;
6825         let expr6_0: Type = I32;
6826         let expr7_0 = constructor_alu_rrr(ctx, pattern0_0, expr6_0, pattern3_0, expr5_0)?;
6827         return Some(expr7_0);
6828     }
6829     return None;
6830 }
6831 
6832 // Generated as internal constructor for term lower_ushr128.
6833 pub fn constructor_lower_ushr128<C: Context>(
6834     ctx: &mut C,
6835     arg0: ValueRegs,
6836     arg1: Reg,
6837 ) -> Option<ValueRegs> {
6838     let pattern0_0 = arg0;
6839     let pattern1_0 = arg1;
6840     // Rule at src/isa/aarch64/lower.isle line 767.
6841     let expr0_0: usize = 0;
6842     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6843     let expr2_0: usize = 1;
6844     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6845     let expr4_0: Type = I64;
6846     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6847     let expr6_0: Type = I64;
6848     let expr7_0 = constructor_lsr(ctx, expr6_0, expr3_0, pattern1_0)?;
6849     let expr8_0: Type = I32;
6850     let expr9_0 = C::zero_reg(ctx);
6851     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6852     let expr11_0: Type = I64;
6853     let expr12_0: Type = I64;
6854     let expr13_0: u8 = 1;
6855     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6856     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6857     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6858     let expr17_0: Type = I64;
6859     let expr18_0 = constructor_orr(ctx, expr17_0, expr5_0, expr16_0)?;
6860     let expr19_0: Type = I64;
6861     let expr20_0: Type = I64;
6862     let expr21_0: u64 = 64;
6863     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6864     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6865     let expr24_0 = Cond::Ne;
6866     let expr25_0 = constructor_csel(ctx, &expr24_0, expr7_0, expr18_0)?;
6867     let expr26_0 = Cond::Ne;
6868     let expr27_0 = C::zero_reg(ctx);
6869     let expr28_0 = constructor_csel(ctx, &expr26_0, expr27_0, expr7_0)?;
6870     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr25_0, &expr28_0)?;
6871     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6872     return Some(expr30_0);
6873 }
6874 
6875 // Generated as internal constructor for term lower_sshr128.
6876 pub fn constructor_lower_sshr128<C: Context>(
6877     ctx: &mut C,
6878     arg0: ValueRegs,
6879     arg1: Reg,
6880 ) -> Option<ValueRegs> {
6881     let pattern0_0 = arg0;
6882     let pattern1_0 = arg1;
6883     // Rule at src/isa/aarch64/lower.isle line 817.
6884     let expr0_0: usize = 0;
6885     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6886     let expr2_0: usize = 1;
6887     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6888     let expr4_0: Type = I64;
6889     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6890     let expr6_0: Type = I64;
6891     let expr7_0 = constructor_asr(ctx, expr6_0, expr3_0, pattern1_0)?;
6892     let expr8_0: Type = I32;
6893     let expr9_0 = C::zero_reg(ctx);
6894     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6895     let expr11_0: Type = I64;
6896     let expr12_0: Type = I64;
6897     let expr13_0: u8 = 1;
6898     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6899     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6900     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6901     let expr17_0: Type = I64;
6902     let expr18_0: u8 = 63;
6903     let expr19_0 = C::imm_shift_from_u8(ctx, expr18_0);
6904     let expr20_0 = constructor_asr_imm(ctx, expr17_0, expr3_0, expr19_0)?;
6905     let expr21_0: Type = I64;
6906     let expr22_0 = constructor_orr(ctx, expr21_0, expr5_0, expr16_0)?;
6907     let expr23_0: Type = I64;
6908     let expr24_0: Type = I64;
6909     let expr25_0: u64 = 64;
6910     let expr26_0 = C::u64_into_imm_logic(ctx, expr24_0, expr25_0);
6911     let expr27_0 = constructor_tst_imm(ctx, expr23_0, pattern1_0, expr26_0)?;
6912     let expr28_0 = Cond::Ne;
6913     let expr29_0 = constructor_csel(ctx, &expr28_0, expr7_0, expr22_0)?;
6914     let expr30_0 = Cond::Ne;
6915     let expr31_0 = constructor_csel(ctx, &expr30_0, expr20_0, expr7_0)?;
6916     let expr32_0 = constructor_consumes_flags_concat(ctx, &expr29_0, &expr31_0)?;
6917     let expr33_0 = constructor_with_flags(ctx, &expr27_0, &expr32_0)?;
6918     return Some(expr33_0);
6919 }
6920 
6921 // Generated as internal constructor for term small_rotr.
6922 pub fn constructor_small_rotr<C: Context>(
6923     ctx: &mut C,
6924     arg0: Type,
6925     arg1: Reg,
6926     arg2: Reg,
6927 ) -> Option<Reg> {
6928     let pattern0_0 = arg0;
6929     let pattern1_0 = arg1;
6930     let pattern2_0 = arg2;
6931     // Rule at src/isa/aarch64/lower.isle line 927.
6932     let expr0_0: Type = I32;
6933     let expr1_0 = C::rotr_mask(ctx, pattern0_0);
6934     let expr2_0 = constructor_and_imm(ctx, expr0_0, pattern2_0, expr1_0)?;
6935     let expr3_0: Type = I32;
6936     let expr4_0 = C::ty_bits(ctx, pattern0_0);
6937     let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
6938     let expr6_0 = constructor_sub_imm(ctx, expr3_0, expr2_0, expr5_0)?;
6939     let expr7_0: Type = I32;
6940     let expr8_0 = C::zero_reg(ctx);
6941     let expr9_0 = constructor_sub(ctx, expr7_0, expr8_0, expr6_0)?;
6942     let expr10_0: Type = I32;
6943     let expr11_0 = constructor_lsr(ctx, expr10_0, pattern1_0, expr2_0)?;
6944     let expr12_0: Type = I32;
6945     let expr13_0 = constructor_lsl(ctx, expr12_0, pattern1_0, expr9_0)?;
6946     let expr14_0: Type = I32;
6947     let expr15_0 = constructor_orr(ctx, expr14_0, expr13_0, expr11_0)?;
6948     return Some(expr15_0);
6949 }
6950 
6951 // Generated as internal constructor for term small_rotr_imm.
6952 pub fn constructor_small_rotr_imm<C: Context>(
6953     ctx: &mut C,
6954     arg0: Type,
6955     arg1: Reg,
6956     arg2: ImmShift,
6957 ) -> Option<Reg> {
6958     let pattern0_0 = arg0;
6959     let pattern1_0 = arg1;
6960     let pattern2_0 = arg2;
6961     // Rule at src/isa/aarch64/lower.isle line 948.
6962     let expr0_0: Type = I32;
6963     let expr1_0 = constructor_lsr_imm(ctx, expr0_0, pattern1_0, pattern2_0)?;
6964     let expr2_0: Type = I32;
6965     let expr3_0 = C::rotr_opposite_amount(ctx, pattern0_0, pattern2_0);
6966     let expr4_0 = constructor_lsl_imm(ctx, expr2_0, pattern1_0, expr3_0)?;
6967     let expr5_0: Type = I32;
6968     let expr6_0 = constructor_orr(ctx, expr5_0, expr4_0, expr1_0)?;
6969     return Some(expr6_0);
6970 }
6971 
6972 // Generated as internal constructor for term lower_clz128.
6973 pub fn constructor_lower_clz128<C: Context>(ctx: &mut C, arg0: ValueRegs) -> Option<ValueRegs> {
6974     let pattern0_0 = arg0;
6975     // Rule at src/isa/aarch64/lower.isle line 1013.
6976     let expr0_0: Type = I64;
6977     let expr1_0: usize = 1;
6978     let expr2_0 = C::value_regs_get(ctx, pattern0_0, expr1_0);
6979     let expr3_0 = constructor_a64_clz(ctx, expr0_0, expr2_0)?;
6980     let expr4_0: Type = I64;
6981     let expr5_0: usize = 0;
6982     let expr6_0 = C::value_regs_get(ctx, pattern0_0, expr5_0);
6983     let expr7_0 = constructor_a64_clz(ctx, expr4_0, expr6_0)?;
6984     let expr8_0: Type = I64;
6985     let expr9_0: u8 = 6;
6986     let expr10_0 = C::imm_shift_from_u8(ctx, expr9_0);
6987     let expr11_0 = constructor_lsr_imm(ctx, expr8_0, expr3_0, expr10_0)?;
6988     let expr12_0 = constructor_madd64(ctx, expr7_0, expr11_0, expr3_0)?;
6989     let expr13_0: Type = I64;
6990     let expr14_0: u64 = 0;
6991     let expr15_0 = constructor_imm(ctx, expr13_0, expr14_0)?;
6992     let expr16_0 = C::value_regs(ctx, expr12_0, expr15_0);
6993     return Some(expr16_0);
6994 }
6995