1 // GENERATED BY ISLE. DO NOT EDIT!
2 //
3 // Generated automatically from the instruction-selection DSL code in:
4 // - src/clif.isle
5 // - src/prelude.isle
6 // - src/isa/aarch64/inst.isle
7 // - src/isa/aarch64/lower.isle
8 
9 #![allow(dead_code, unreachable_code, unreachable_patterns)]
10 #![allow(unused_imports, unused_variables, non_snake_case)]
11 #![allow(irrefutable_let_patterns)]
12 
13 use super::*; // Pulls in all external types.
14 
15 /// Context during lowering: an implementation of this trait
16 /// must be provided with all external constructors and extractors.
17 /// A mutable borrow is passed along through all lowering logic.
18 pub trait Context {
19     fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
20     fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
21     fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
22     fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
23     fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
24     fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
25     fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
26     fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
27     fn value_regs_invalid(&mut self) -> ValueRegs;
28     fn output_none(&mut self) -> InstOutput;
29     fn output(&mut self, arg0: ValueRegs) -> InstOutput;
30     fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput;
31     fn output_builder_new(&mut self) -> InstOutputBuilder;
32     fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit;
33     fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput;
34     fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
35     fn invalid_reg(&mut self) -> Reg;
36     fn put_in_reg(&mut self, arg0: Value) -> Reg;
37     fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
38     fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
39     fn u8_as_u64(&mut self, arg0: u8) -> u64;
40     fn u16_as_u64(&mut self, arg0: u16) -> u64;
41     fn u32_as_u64(&mut self, arg0: u32) -> u64;
42     fn ty_bits(&mut self, arg0: Type) -> u8;
43     fn ty_bits_u16(&mut self, arg0: Type) -> u16;
44     fn ty_bytes(&mut self, arg0: Type) -> u16;
45     fn lane_type(&mut self, arg0: Type) -> Type;
46     fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
47     fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
48     fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
49     fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
50     fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
51     fn vec128(&mut self, arg0: Type) -> Option<Type>;
52     fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
53     fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
54     fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>;
55     fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>;
56     fn value_slice_len(&mut self, arg0: ValueSlice) -> usize;
57     fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value;
58     fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
59     fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
60     fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
61     fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
62     fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
63     fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
64     fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
65     fn first_result(&mut self, arg0: Inst) -> Option<Value>;
66     fn inst_data(&mut self, arg0: Inst) -> InstructionData;
67     fn value_type(&mut self, arg0: Value) -> Type;
68     fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
69     fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
70     fn emit(&mut self, arg0: &MInst) -> Unit;
71     fn emit_safepoint(&mut self, arg0: &MInst) -> Unit;
72     fn trap_code_division_by_zero(&mut self) -> TrapCode;
73     fn trap_code_integer_overflow(&mut self) -> TrapCode;
74     fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
75     fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
76     fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
77     fn symbol_value_data(
78         &mut self,
79         arg0: GlobalValue,
80     ) -> Option<(ExternalName, RelocDistance, i64)>;
81     fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
82     fn move_wide_const_from_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
83     fn move_wide_const_from_negated_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
84     fn imm_logic_from_u64(&mut self, arg0: u64, arg1: Type) -> Option<ImmLogic>;
85     fn imm_logic_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmLogic>;
86     fn imm_shift_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmShift>;
87     fn imm_shift_from_u8(&mut self, arg0: u8) -> ImmShift;
88     fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12>;
89     fn u8_into_uimm5(&mut self, arg0: u8) -> UImm5;
90     fn u8_into_imm12(&mut self, arg0: u8) -> Imm12;
91     fn u64_into_imm_logic(&mut self, arg0: Type, arg1: u64) -> ImmLogic;
92     fn imm12_from_negated_u64(&mut self, arg0: u64) -> Option<Imm12>;
93     fn lshl_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ShiftOpAndAmt>;
94     fn integral_ty(&mut self, arg0: Type) -> Option<Type>;
95     fn extended_value_from_value(&mut self, arg0: Value) -> Option<ExtendedValue>;
96     fn put_extended_in_reg(&mut self, arg0: &ExtendedValue) -> Reg;
97     fn get_extended_op(&mut self, arg0: &ExtendedValue) -> ExtendOp;
98     fn nzcv(&mut self, arg0: bool, arg1: bool, arg2: bool, arg3: bool) -> NZCV;
99     fn cond_br_zero(&mut self, arg0: Reg) -> CondBrKind;
100     fn cond_br_cond(&mut self, arg0: &Cond) -> CondBrKind;
101     fn zero_reg(&mut self) -> Reg;
102     fn writable_zero_reg(&mut self) -> WritableReg;
103     fn load_constant64_full(&mut self, arg0: u64) -> Reg;
104     fn sinkable_atomic_load(&mut self, arg0: Value) -> Option<SinkableAtomicLoad>;
105     fn sink_atomic_load(&mut self, arg0: &SinkableAtomicLoad) -> Reg;
106     fn safe_divisor_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
107     fn shift_mask(&mut self, arg0: Type) -> ImmLogic;
108     fn negate_imm_shift(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
109     fn rotr_mask(&mut self, arg0: Type) -> ImmLogic;
110     fn rotr_opposite_amount(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
111 }
112 
113 /// Internal type SideEffectNoResult: defined at src/prelude.isle line 363.
114 #[derive(Clone, Debug)]
115 pub enum SideEffectNoResult {
116     Inst { inst: MInst },
117 }
118 
119 /// Internal type ProducesFlags: defined at src/prelude.isle line 385.
120 #[derive(Clone, Debug)]
121 pub enum ProducesFlags {
122     ProducesFlagsSideEffect { inst: MInst },
123     ProducesFlagsReturnsReg { inst: MInst, result: Reg },
124     ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg },
125 }
126 
127 /// Internal type ConsumesFlags: defined at src/prelude.isle line 396.
128 #[derive(Clone, Debug)]
129 pub enum ConsumesFlags {
130     ConsumesFlagsReturnsResultWithProducer {
131         inst: MInst,
132         result: Reg,
133     },
134     ConsumesFlagsReturnsReg {
135         inst: MInst,
136         result: Reg,
137     },
138     ConsumesFlagsTwiceReturnsValueRegs {
139         inst1: MInst,
140         inst2: MInst,
141         result: ValueRegs,
142     },
143 }
144 
145 /// Internal type MInst: defined at src/isa/aarch64/inst.isle line 2.
146 #[derive(Clone, Debug)]
147 pub enum MInst {
148     Nop0,
149     Nop4,
150     AluRRR {
151         alu_op: ALUOp,
152         size: OperandSize,
153         rd: WritableReg,
154         rn: Reg,
155         rm: Reg,
156     },
157     AluRRRR {
158         alu_op: ALUOp3,
159         rd: WritableReg,
160         rn: Reg,
161         rm: Reg,
162         ra: Reg,
163     },
164     AluRRImm12 {
165         alu_op: ALUOp,
166         size: OperandSize,
167         rd: WritableReg,
168         rn: Reg,
169         imm12: Imm12,
170     },
171     AluRRImmLogic {
172         alu_op: ALUOp,
173         size: OperandSize,
174         rd: WritableReg,
175         rn: Reg,
176         imml: ImmLogic,
177     },
178     AluRRImmShift {
179         alu_op: ALUOp,
180         size: OperandSize,
181         rd: WritableReg,
182         rn: Reg,
183         immshift: ImmShift,
184     },
185     AluRRRShift {
186         alu_op: ALUOp,
187         size: OperandSize,
188         rd: WritableReg,
189         rn: Reg,
190         rm: Reg,
191         shiftop: ShiftOpAndAmt,
192     },
193     AluRRRExtend {
194         alu_op: ALUOp,
195         size: OperandSize,
196         rd: WritableReg,
197         rn: Reg,
198         rm: Reg,
199         extendop: ExtendOp,
200     },
201     BitRR {
202         op: BitOp,
203         size: OperandSize,
204         rd: WritableReg,
205         rn: Reg,
206     },
207     ULoad8 {
208         rd: WritableReg,
209         mem: AMode,
210         flags: MemFlags,
211     },
212     SLoad8 {
213         rd: WritableReg,
214         mem: AMode,
215         flags: MemFlags,
216     },
217     ULoad16 {
218         rd: WritableReg,
219         mem: AMode,
220         flags: MemFlags,
221     },
222     SLoad16 {
223         rd: WritableReg,
224         mem: AMode,
225         flags: MemFlags,
226     },
227     ULoad32 {
228         rd: WritableReg,
229         mem: AMode,
230         flags: MemFlags,
231     },
232     SLoad32 {
233         rd: WritableReg,
234         mem: AMode,
235         flags: MemFlags,
236     },
237     ULoad64 {
238         rd: WritableReg,
239         mem: AMode,
240         flags: MemFlags,
241     },
242     Store8 {
243         rd: Reg,
244         mem: AMode,
245         flags: MemFlags,
246     },
247     Store16 {
248         rd: Reg,
249         mem: AMode,
250         flags: MemFlags,
251     },
252     Store32 {
253         rd: Reg,
254         mem: AMode,
255         flags: MemFlags,
256     },
257     Store64 {
258         rd: Reg,
259         mem: AMode,
260         flags: MemFlags,
261     },
262     StoreP64 {
263         rt: Reg,
264         rt2: Reg,
265         mem: PairAMode,
266         flags: MemFlags,
267     },
268     LoadP64 {
269         rt: WritableReg,
270         rt2: WritableReg,
271         mem: PairAMode,
272         flags: MemFlags,
273     },
274     Mov64 {
275         rd: WritableReg,
276         rm: Reg,
277     },
278     Mov32 {
279         rd: WritableReg,
280         rm: Reg,
281     },
282     MovZ {
283         rd: WritableReg,
284         imm: MoveWideConst,
285         size: OperandSize,
286     },
287     MovN {
288         rd: WritableReg,
289         imm: MoveWideConst,
290         size: OperandSize,
291     },
292     MovK {
293         rd: WritableReg,
294         imm: MoveWideConst,
295         size: OperandSize,
296     },
297     Extend {
298         rd: WritableReg,
299         rn: Reg,
300         signed: bool,
301         from_bits: u8,
302         to_bits: u8,
303     },
304     CSel {
305         rd: WritableReg,
306         cond: Cond,
307         rn: Reg,
308         rm: Reg,
309     },
310     CSet {
311         rd: WritableReg,
312         cond: Cond,
313     },
314     CSetm {
315         rd: WritableReg,
316         cond: Cond,
317     },
318     CCmpImm {
319         size: OperandSize,
320         rn: Reg,
321         imm: UImm5,
322         nzcv: NZCV,
323         cond: Cond,
324     },
325     AtomicRMWLoop {
326         ty: Type,
327         op: AtomicRmwOp,
328     },
329     AtomicRMW {
330         op: AtomicRMWOp,
331         rs: Reg,
332         rt: WritableReg,
333         rn: Reg,
334         ty: Type,
335     },
336     AtomicCAS {
337         rs: WritableReg,
338         rt: Reg,
339         rn: Reg,
340         ty: Type,
341     },
342     AtomicCASLoop {
343         ty: Type,
344     },
345     LoadAcquire {
346         access_ty: Type,
347         rt: WritableReg,
348         rn: Reg,
349     },
350     StoreRelease {
351         access_ty: Type,
352         rt: Reg,
353         rn: Reg,
354     },
355     Fence,
356     FpuMove64 {
357         rd: WritableReg,
358         rn: Reg,
359     },
360     FpuMove128 {
361         rd: WritableReg,
362         rn: Reg,
363     },
364     FpuMoveFromVec {
365         rd: WritableReg,
366         rn: Reg,
367         idx: u8,
368         size: VectorSize,
369     },
370     FpuExtend {
371         rd: WritableReg,
372         rn: Reg,
373         size: ScalarSize,
374     },
375     FpuRR {
376         fpu_op: FPUOp1,
377         rd: WritableReg,
378         rn: Reg,
379     },
380     FpuRRR {
381         fpu_op: FPUOp2,
382         rd: WritableReg,
383         rn: Reg,
384         rm: Reg,
385     },
386     FpuRRI {
387         fpu_op: FPUOpRI,
388         rd: WritableReg,
389         rn: Reg,
390     },
391     FpuRRRR {
392         fpu_op: FPUOp3,
393         rd: WritableReg,
394         rn: Reg,
395         rm: Reg,
396         ra: Reg,
397     },
398     FpuCmp32 {
399         rn: Reg,
400         rm: Reg,
401     },
402     FpuCmp64 {
403         rn: Reg,
404         rm: Reg,
405     },
406     FpuLoad32 {
407         rd: WritableReg,
408         mem: AMode,
409         flags: MemFlags,
410     },
411     FpuStore32 {
412         rd: Reg,
413         mem: AMode,
414         flags: MemFlags,
415     },
416     FpuLoad64 {
417         rd: WritableReg,
418         mem: AMode,
419         flags: MemFlags,
420     },
421     FpuStore64 {
422         rd: Reg,
423         mem: AMode,
424         flags: MemFlags,
425     },
426     FpuLoad128 {
427         rd: WritableReg,
428         mem: AMode,
429         flags: MemFlags,
430     },
431     FpuStore128 {
432         rd: Reg,
433         mem: AMode,
434         flags: MemFlags,
435     },
436     FpuLoadP64 {
437         rt: WritableReg,
438         rt2: WritableReg,
439         mem: PairAMode,
440         flags: MemFlags,
441     },
442     FpuStoreP64 {
443         rt: Reg,
444         rt2: Reg,
445         mem: PairAMode,
446         flags: MemFlags,
447     },
448     FpuLoadP128 {
449         rt: WritableReg,
450         rt2: WritableReg,
451         mem: PairAMode,
452         flags: MemFlags,
453     },
454     FpuStoreP128 {
455         rt: Reg,
456         rt2: Reg,
457         mem: PairAMode,
458         flags: MemFlags,
459     },
460     LoadFpuConst64 {
461         rd: WritableReg,
462         const_data: u64,
463     },
464     LoadFpuConst128 {
465         rd: WritableReg,
466         const_data: u128,
467     },
468     FpuToInt {
469         op: FpuToIntOp,
470         rd: WritableReg,
471         rn: Reg,
472     },
473     IntToFpu {
474         op: IntToFpuOp,
475         rd: WritableReg,
476         rn: Reg,
477     },
478     FpuCSel32 {
479         rd: WritableReg,
480         rn: Reg,
481         rm: Reg,
482         cond: Cond,
483     },
484     FpuCSel64 {
485         rd: WritableReg,
486         rn: Reg,
487         rm: Reg,
488         cond: Cond,
489     },
490     FpuRound {
491         op: FpuRoundMode,
492         rd: WritableReg,
493         rn: Reg,
494     },
495     MovToFpu {
496         rd: WritableReg,
497         rn: Reg,
498         size: ScalarSize,
499     },
500     FpuMoveFPImm {
501         rd: WritableReg,
502         imm: ASIMDFPModImm,
503         size: ScalarSize,
504     },
505     MovToVec {
506         rd: WritableReg,
507         rn: Reg,
508         idx: u8,
509         size: VectorSize,
510     },
511     MovFromVec {
512         rd: WritableReg,
513         rn: Reg,
514         idx: u8,
515         size: VectorSize,
516     },
517     MovFromVecSigned {
518         rd: WritableReg,
519         rn: Reg,
520         idx: u8,
521         size: VectorSize,
522         scalar_size: OperandSize,
523     },
524     VecDup {
525         rd: WritableReg,
526         rn: Reg,
527         size: VectorSize,
528     },
529     VecDupFromFpu {
530         rd: WritableReg,
531         rn: Reg,
532         size: VectorSize,
533     },
534     VecDupFPImm {
535         rd: WritableReg,
536         imm: ASIMDFPModImm,
537         size: VectorSize,
538     },
539     VecDupImm {
540         rd: WritableReg,
541         imm: ASIMDMovModImm,
542         invert: bool,
543         size: VectorSize,
544     },
545     VecExtend {
546         t: VecExtendOp,
547         rd: WritableReg,
548         rn: Reg,
549         high_half: bool,
550     },
551     VecMovElement {
552         rd: WritableReg,
553         rn: Reg,
554         dest_idx: u8,
555         src_idx: u8,
556         size: VectorSize,
557     },
558     VecRRLong {
559         op: VecRRLongOp,
560         rd: WritableReg,
561         rn: Reg,
562         high_half: bool,
563     },
564     VecRRNarrow {
565         op: VecRRNarrowOp,
566         rd: WritableReg,
567         rn: Reg,
568         high_half: bool,
569     },
570     VecRRPair {
571         op: VecPairOp,
572         rd: WritableReg,
573         rn: Reg,
574     },
575     VecRRRLong {
576         alu_op: VecRRRLongOp,
577         rd: WritableReg,
578         rn: Reg,
579         rm: Reg,
580         high_half: bool,
581     },
582     VecRRPairLong {
583         op: VecRRPairLongOp,
584         rd: WritableReg,
585         rn: Reg,
586     },
587     VecRRR {
588         alu_op: VecALUOp,
589         rd: WritableReg,
590         rn: Reg,
591         rm: Reg,
592         size: VectorSize,
593     },
594     VecMisc {
595         op: VecMisc2,
596         rd: WritableReg,
597         rn: Reg,
598         size: VectorSize,
599     },
600     VecLanes {
601         op: VecLanesOp,
602         rd: WritableReg,
603         rn: Reg,
604         size: VectorSize,
605     },
606     VecShiftImm {
607         op: VecShiftImmOp,
608         rd: WritableReg,
609         rn: Reg,
610         size: VectorSize,
611         imm: u8,
612     },
613     VecExtract {
614         rd: WritableReg,
615         rn: Reg,
616         rm: Reg,
617         imm4: u8,
618     },
619     VecTbl {
620         rd: WritableReg,
621         rn: Reg,
622         rm: Reg,
623         is_extension: bool,
624     },
625     VecTbl2 {
626         rd: WritableReg,
627         rn: Reg,
628         rn2: Reg,
629         rm: Reg,
630         is_extension: bool,
631     },
632     VecLoadReplicate {
633         rd: WritableReg,
634         rn: Reg,
635         size: VectorSize,
636     },
637     VecCSel {
638         rd: WritableReg,
639         rn: Reg,
640         rm: Reg,
641         cond: Cond,
642     },
643     MovToNZCV {
644         rn: Reg,
645     },
646     MovFromNZCV {
647         rd: WritableReg,
648     },
649     Call {
650         info: BoxCallInfo,
651     },
652     CallInd {
653         info: BoxCallIndInfo,
654     },
655     Ret,
656     EpiloguePlaceholder,
657     Jump {
658         dest: BranchTarget,
659     },
660     CondBr {
661         taken: BranchTarget,
662         not_taken: BranchTarget,
663         kind: CondBrKind,
664     },
665     TrapIf {
666         kind: CondBrKind,
667         trap_code: TrapCode,
668     },
669     IndirectBr {
670         rn: Reg,
671         targets: VecMachLabel,
672     },
673     Brk,
674     Udf {
675         trap_code: TrapCode,
676     },
677     Adr {
678         rd: WritableReg,
679         off: i32,
680     },
681     Word4 {
682         data: u32,
683     },
684     Word8 {
685         data: u64,
686     },
687     JTSequence {
688         info: BoxJTSequenceInfo,
689         ridx: Reg,
690         rtmp1: WritableReg,
691         rtmp2: WritableReg,
692     },
693     LoadExtName {
694         rd: WritableReg,
695         name: BoxExternalName,
696         offset: i64,
697     },
698     LoadAddr {
699         rd: WritableReg,
700         mem: AMode,
701     },
702     VirtualSPOffsetAdj {
703         offset: i64,
704     },
705     EmitIsland {
706         needed_space: CodeOffset,
707     },
708     ElfTlsGetAddr {
709         symbol: ExternalName,
710     },
711     ValueLabelMarker {
712         reg: Reg,
713         label: ValueLabel,
714     },
715     Unwind {
716         inst: UnwindInst,
717     },
718 }
719 
720 /// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 796.
721 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
722 pub enum ALUOp {
723     Add,
724     Sub,
725     Orr,
726     OrrNot,
727     And,
728     AndS,
729     AndNot,
730     Eor,
731     EorNot,
732     AddS,
733     SubS,
734     SMulH,
735     UMulH,
736     SDiv,
737     UDiv,
738     RotR,
739     Lsr,
740     Asr,
741     Lsl,
742     Adc,
743     AdcS,
744     Sbc,
745     SbcS,
746 }
747 
748 /// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 834.
749 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
750 pub enum ALUOp3 {
751     MAdd32,
752     MAdd64,
753     MSub32,
754     MSub64,
755 }
756 
757 /// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 877.
758 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
759 pub enum BitOp {
760     RBit,
761     Clz,
762     Cls,
763 }
764 
765 /// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 944.
766 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
767 pub enum FPUOp1 {
768     Abs32,
769     Abs64,
770     Neg32,
771     Neg64,
772     Sqrt32,
773     Sqrt64,
774     Cvt32To64,
775     Cvt64To32,
776 }
777 
778 /// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 957.
779 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
780 pub enum FPUOp2 {
781     Add32,
782     Add64,
783     Sub32,
784     Sub64,
785     Mul32,
786     Mul64,
787     Div32,
788     Div64,
789     Max32,
790     Max64,
791     Min32,
792     Min64,
793     Sqadd64,
794     Uqadd64,
795     Sqsub64,
796     Uqsub64,
797 }
798 
799 /// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 982.
800 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
801 pub enum FPUOp3 {
802     MAdd32,
803     MAdd64,
804 }
805 
806 /// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 989.
807 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
808 pub enum FpuToIntOp {
809     F32ToU32,
810     F32ToI32,
811     F32ToU64,
812     F32ToI64,
813     F64ToU32,
814     F64ToI32,
815     F64ToU64,
816     F64ToI64,
817 }
818 
819 /// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 1002.
820 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
821 pub enum IntToFpuOp {
822     U32ToF32,
823     I32ToF32,
824     U32ToF64,
825     I32ToF64,
826     U64ToF32,
827     I64ToF32,
828     U64ToF64,
829     I64ToF64,
830 }
831 
832 /// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 1016.
833 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
834 pub enum FpuRoundMode {
835     Minus32,
836     Minus64,
837     Plus32,
838     Plus64,
839     Zero32,
840     Zero64,
841     Nearest32,
842     Nearest64,
843 }
844 
845 /// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 1029.
846 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
847 pub enum VecExtendOp {
848     Sxtl8,
849     Sxtl16,
850     Sxtl32,
851     Uxtl8,
852     Uxtl16,
853     Uxtl32,
854 }
855 
856 /// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1046.
857 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
858 pub enum VecALUOp {
859     Sqadd,
860     Uqadd,
861     Sqsub,
862     Uqsub,
863     Cmeq,
864     Cmge,
865     Cmgt,
866     Cmhs,
867     Cmhi,
868     Fcmeq,
869     Fcmgt,
870     Fcmge,
871     And,
872     Bic,
873     Orr,
874     Eor,
875     Bsl,
876     Umaxp,
877     Add,
878     Sub,
879     Mul,
880     Sshl,
881     Ushl,
882     Umin,
883     Smin,
884     Umax,
885     Smax,
886     Urhadd,
887     Fadd,
888     Fsub,
889     Fdiv,
890     Fmax,
891     Fmin,
892     Fmul,
893     Addp,
894     Zip1,
895     Sqrdmulh,
896 }
897 
898 /// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1125.
899 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
900 pub enum VecMisc2 {
901     Not,
902     Neg,
903     Abs,
904     Fabs,
905     Fneg,
906     Fsqrt,
907     Rev64,
908     Fcvtzs,
909     Fcvtzu,
910     Scvtf,
911     Ucvtf,
912     Frintn,
913     Frintz,
914     Frintm,
915     Frintp,
916     Cnt,
917     Cmeq0,
918 }
919 
920 /// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1164.
921 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
922 pub enum VecRRLongOp {
923     Fcvtl16,
924     Fcvtl32,
925     Shll8,
926     Shll16,
927     Shll32,
928 }
929 
930 /// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1179.
931 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
932 pub enum VecRRNarrowOp {
933     Xtn16,
934     Xtn32,
935     Xtn64,
936     Sqxtn16,
937     Sqxtn32,
938     Sqxtn64,
939     Sqxtun16,
940     Sqxtun32,
941     Sqxtun64,
942     Uqxtn16,
943     Uqxtn32,
944     Uqxtn64,
945     Fcvtn32,
946     Fcvtn64,
947 }
948 
949 /// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1211.
950 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
951 pub enum VecRRRLongOp {
952     Smull8,
953     Smull16,
954     Smull32,
955     Umull8,
956     Umull16,
957     Umull32,
958     Umlal8,
959     Umlal16,
960     Umlal32,
961 }
962 
963 /// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1228.
964 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
965 pub enum VecPairOp {
966     Addp,
967 }
968 
969 /// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1236.
970 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
971 pub enum VecRRPairLongOp {
972     Saddlp8,
973     Saddlp16,
974     Uaddlp8,
975     Uaddlp16,
976 }
977 
978 /// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1247.
979 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
980 pub enum VecLanesOp {
981     Addv,
982     Uminv,
983 }
984 
985 /// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1256.
986 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
987 pub enum VecShiftImmOp {
988     Shl,
989     Ushr,
990     Sshr,
991 }
992 
993 /// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1267.
994 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
995 pub enum AtomicRMWOp {
996     Add,
997     Clr,
998     Eor,
999     Set,
1000     Smax,
1001     Smin,
1002     Umax,
1003     Umin,
1004 }
1005 
1006 // Generated as internal constructor for term output_reg.
1007 pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
1008     let pattern0_0 = arg0;
1009     // Rule at src/prelude.isle line 86.
1010     let expr0_0 = C::value_reg(ctx, pattern0_0);
1011     let expr1_0 = C::output(ctx, expr0_0);
1012     return Some(expr1_0);
1013 }
1014 
1015 // Generated as internal constructor for term output_value.
1016 pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> {
1017     let pattern0_0 = arg0;
1018     // Rule at src/prelude.isle line 90.
1019     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1020     let expr1_0 = C::output(ctx, expr0_0);
1021     return Some(expr1_0);
1022 }
1023 
1024 // Generated as internal constructor for term temp_reg.
1025 pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
1026     let pattern0_0 = arg0;
1027     // Rule at src/prelude.isle line 110.
1028     let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
1029     let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
1030     return Some(expr1_0);
1031 }
1032 
1033 // Generated as internal constructor for term lo_reg.
1034 pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
1035     let pattern0_0 = arg0;
1036     // Rule at src/prelude.isle line 145.
1037     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1038     let expr1_0: usize = 0;
1039     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1040     return Some(expr2_0);
1041 }
1042 
1043 // Generated as internal constructor for term side_effect.
1044 pub fn constructor_side_effect<C: Context>(
1045     ctx: &mut C,
1046     arg0: &SideEffectNoResult,
1047 ) -> Option<InstOutput> {
1048     let pattern0_0 = arg0;
1049     if let &SideEffectNoResult::Inst {
1050         inst: ref pattern1_0,
1051     } = pattern0_0
1052     {
1053         // Rule at src/prelude.isle line 368.
1054         let expr0_0 = C::emit(ctx, pattern1_0);
1055         let expr1_0 = C::output_none(ctx);
1056         return Some(expr1_0);
1057     }
1058     return None;
1059 }
1060 
1061 // Generated as internal constructor for term safepoint.
1062 pub fn constructor_safepoint<C: Context>(
1063     ctx: &mut C,
1064     arg0: &SideEffectNoResult,
1065 ) -> Option<InstOutput> {
1066     let pattern0_0 = arg0;
1067     if let &SideEffectNoResult::Inst {
1068         inst: ref pattern1_0,
1069     } = pattern0_0
1070     {
1071         // Rule at src/prelude.isle line 374.
1072         let expr0_0 = C::emit_safepoint(ctx, pattern1_0);
1073         let expr1_0 = C::output_none(ctx);
1074         return Some(expr1_0);
1075     }
1076     return None;
1077 }
1078 
1079 // Generated as internal constructor for term consumes_flags_concat.
1080 pub fn constructor_consumes_flags_concat<C: Context>(
1081     ctx: &mut C,
1082     arg0: &ConsumesFlags,
1083     arg1: &ConsumesFlags,
1084 ) -> Option<ConsumesFlags> {
1085     let pattern0_0 = arg0;
1086     if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1087         inst: ref pattern1_0,
1088         result: pattern1_1,
1089     } = pattern0_0
1090     {
1091         let pattern2_0 = arg1;
1092         if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1093             inst: ref pattern3_0,
1094             result: pattern3_1,
1095         } = pattern2_0
1096         {
1097             // Rule at src/prelude.isle line 408.
1098             let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1099             let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1100                 inst1: pattern1_0.clone(),
1101                 inst2: pattern3_0.clone(),
1102                 result: expr0_0,
1103             };
1104             return Some(expr1_0);
1105         }
1106     }
1107     return None;
1108 }
1109 
1110 // Generated as internal constructor for term with_flags.
1111 pub fn constructor_with_flags<C: Context>(
1112     ctx: &mut C,
1113     arg0: &ProducesFlags,
1114     arg1: &ConsumesFlags,
1115 ) -> Option<ValueRegs> {
1116     let pattern0_0 = arg0;
1117     match pattern0_0 {
1118         &ProducesFlags::ProducesFlagsSideEffect {
1119             inst: ref pattern1_0,
1120         } => {
1121             let pattern2_0 = arg1;
1122             match pattern2_0 {
1123                 &ConsumesFlags::ConsumesFlagsReturnsReg {
1124                     inst: ref pattern3_0,
1125                     result: pattern3_1,
1126                 } => {
1127                     // Rule at src/prelude.isle line 433.
1128                     let expr0_0 = C::emit(ctx, pattern1_0);
1129                     let expr1_0 = C::emit(ctx, pattern3_0);
1130                     let expr2_0 = C::value_reg(ctx, pattern3_1);
1131                     return Some(expr2_0);
1132                 }
1133                 &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1134                     inst1: ref pattern3_0,
1135                     inst2: ref pattern3_1,
1136                     result: pattern3_2,
1137                 } => {
1138                     // Rule at src/prelude.isle line 439.
1139                     let expr0_0 = C::emit(ctx, pattern1_0);
1140                     let expr1_0 = C::emit(ctx, pattern3_1);
1141                     let expr2_0 = C::emit(ctx, pattern3_0);
1142                     return Some(pattern3_2);
1143                 }
1144                 _ => {}
1145             }
1146         }
1147         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1148             inst: ref pattern1_0,
1149             result: pattern1_1,
1150         } => {
1151             let pattern2_0 = arg1;
1152             if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1153                 inst: ref pattern3_0,
1154                 result: pattern3_1,
1155             } = pattern2_0
1156             {
1157                 // Rule at src/prelude.isle line 427.
1158                 let expr0_0 = C::emit(ctx, pattern1_0);
1159                 let expr1_0 = C::emit(ctx, pattern3_0);
1160                 let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1161                 return Some(expr2_0);
1162             }
1163         }
1164         _ => {}
1165     }
1166     return None;
1167 }
1168 
1169 // Generated as internal constructor for term with_flags_reg.
1170 pub fn constructor_with_flags_reg<C: Context>(
1171     ctx: &mut C,
1172     arg0: &ProducesFlags,
1173     arg1: &ConsumesFlags,
1174 ) -> Option<Reg> {
1175     let pattern0_0 = arg0;
1176     let pattern1_0 = arg1;
1177     // Rule at src/prelude.isle line 452.
1178     let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?;
1179     let expr1_0: usize = 0;
1180     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1181     return Some(expr2_0);
1182 }
1183 
1184 // Generated as internal constructor for term operand_size.
1185 pub fn constructor_operand_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
1186     let pattern0_0 = arg0;
1187     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
1188         // Rule at src/isa/aarch64/inst.isle line 895.
1189         let expr0_0 = OperandSize::Size32;
1190         return Some(expr0_0);
1191     }
1192     if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
1193         // Rule at src/isa/aarch64/inst.isle line 896.
1194         let expr0_0 = OperandSize::Size64;
1195         return Some(expr0_0);
1196     }
1197     return None;
1198 }
1199 
1200 // Generated as internal constructor for term vector_size.
1201 pub fn constructor_vector_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<VectorSize> {
1202     let pattern0_0 = arg0;
1203     if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
1204         if pattern1_0 == 8 {
1205             if pattern1_1 == 16 {
1206                 // Rule at src/isa/aarch64/inst.isle line 938.
1207                 let expr0_0 = VectorSize::Size8x16;
1208                 return Some(expr0_0);
1209             }
1210         }
1211         if pattern1_0 == 16 {
1212             if pattern1_1 == 8 {
1213                 // Rule at src/isa/aarch64/inst.isle line 939.
1214                 let expr0_0 = VectorSize::Size16x8;
1215                 return Some(expr0_0);
1216             }
1217         }
1218         if pattern1_0 == 32 {
1219             if pattern1_1 == 4 {
1220                 // Rule at src/isa/aarch64/inst.isle line 940.
1221                 let expr0_0 = VectorSize::Size32x4;
1222                 return Some(expr0_0);
1223             }
1224         }
1225         if pattern1_0 == 64 {
1226             if pattern1_1 == 2 {
1227                 // Rule at src/isa/aarch64/inst.isle line 941.
1228                 let expr0_0 = VectorSize::Size64x2;
1229                 return Some(expr0_0);
1230             }
1231         }
1232     }
1233     return None;
1234 }
1235 
1236 // Generated as internal constructor for term movz.
1237 pub fn constructor_movz<C: Context>(
1238     ctx: &mut C,
1239     arg0: MoveWideConst,
1240     arg1: &OperandSize,
1241 ) -> Option<Reg> {
1242     let pattern0_0 = arg0;
1243     let pattern1_0 = arg1;
1244     // Rule at src/isa/aarch64/inst.isle line 1363.
1245     let expr0_0: Type = I64;
1246     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1247     let expr2_0 = MInst::MovZ {
1248         rd: expr1_0,
1249         imm: pattern0_0,
1250         size: pattern1_0.clone(),
1251     };
1252     let expr3_0 = C::emit(ctx, &expr2_0);
1253     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1254     return Some(expr4_0);
1255 }
1256 
1257 // Generated as internal constructor for term movn.
1258 pub fn constructor_movn<C: Context>(
1259     ctx: &mut C,
1260     arg0: MoveWideConst,
1261     arg1: &OperandSize,
1262 ) -> Option<Reg> {
1263     let pattern0_0 = arg0;
1264     let pattern1_0 = arg1;
1265     // Rule at src/isa/aarch64/inst.isle line 1370.
1266     let expr0_0: Type = I64;
1267     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1268     let expr2_0 = MInst::MovN {
1269         rd: expr1_0,
1270         imm: pattern0_0,
1271         size: pattern1_0.clone(),
1272     };
1273     let expr3_0 = C::emit(ctx, &expr2_0);
1274     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1275     return Some(expr4_0);
1276 }
1277 
1278 // Generated as internal constructor for term alu_rr_imm_logic.
1279 pub fn constructor_alu_rr_imm_logic<C: Context>(
1280     ctx: &mut C,
1281     arg0: &ALUOp,
1282     arg1: Type,
1283     arg2: Reg,
1284     arg3: ImmLogic,
1285 ) -> Option<Reg> {
1286     let pattern0_0 = arg0;
1287     let pattern1_0 = arg1;
1288     let pattern2_0 = arg2;
1289     let pattern3_0 = arg3;
1290     // Rule at src/isa/aarch64/inst.isle line 1377.
1291     let expr0_0: Type = I64;
1292     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1293     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1294     let expr3_0 = MInst::AluRRImmLogic {
1295         alu_op: pattern0_0.clone(),
1296         size: expr2_0,
1297         rd: expr1_0,
1298         rn: pattern2_0,
1299         imml: pattern3_0,
1300     };
1301     let expr4_0 = C::emit(ctx, &expr3_0);
1302     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1303     return Some(expr5_0);
1304 }
1305 
1306 // Generated as internal constructor for term alu_rr_imm_shift.
1307 pub fn constructor_alu_rr_imm_shift<C: Context>(
1308     ctx: &mut C,
1309     arg0: &ALUOp,
1310     arg1: Type,
1311     arg2: Reg,
1312     arg3: ImmShift,
1313 ) -> Option<Reg> {
1314     let pattern0_0 = arg0;
1315     let pattern1_0 = arg1;
1316     let pattern2_0 = arg2;
1317     let pattern3_0 = arg3;
1318     // Rule at src/isa/aarch64/inst.isle line 1384.
1319     let expr0_0: Type = I64;
1320     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1321     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1322     let expr3_0 = MInst::AluRRImmShift {
1323         alu_op: pattern0_0.clone(),
1324         size: expr2_0,
1325         rd: expr1_0,
1326         rn: pattern2_0,
1327         immshift: pattern3_0,
1328     };
1329     let expr4_0 = C::emit(ctx, &expr3_0);
1330     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1331     return Some(expr5_0);
1332 }
1333 
1334 // Generated as internal constructor for term alu_rrr.
1335 pub fn constructor_alu_rrr<C: Context>(
1336     ctx: &mut C,
1337     arg0: &ALUOp,
1338     arg1: Type,
1339     arg2: Reg,
1340     arg3: Reg,
1341 ) -> Option<Reg> {
1342     let pattern0_0 = arg0;
1343     let pattern1_0 = arg1;
1344     let pattern2_0 = arg2;
1345     let pattern3_0 = arg3;
1346     // Rule at src/isa/aarch64/inst.isle line 1391.
1347     let expr0_0: Type = I64;
1348     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1349     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1350     let expr3_0 = MInst::AluRRR {
1351         alu_op: pattern0_0.clone(),
1352         size: expr2_0,
1353         rd: expr1_0,
1354         rn: pattern2_0,
1355         rm: pattern3_0,
1356     };
1357     let expr4_0 = C::emit(ctx, &expr3_0);
1358     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1359     return Some(expr5_0);
1360 }
1361 
1362 // Generated as internal constructor for term vec_rrr.
1363 pub fn constructor_vec_rrr<C: Context>(
1364     ctx: &mut C,
1365     arg0: &VecALUOp,
1366     arg1: Reg,
1367     arg2: Reg,
1368     arg3: &VectorSize,
1369 ) -> Option<Reg> {
1370     let pattern0_0 = arg0;
1371     let pattern1_0 = arg1;
1372     let pattern2_0 = arg2;
1373     let pattern3_0 = arg3;
1374     // Rule at src/isa/aarch64/inst.isle line 1398.
1375     let expr0_0: Type = I8X16;
1376     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1377     let expr2_0 = MInst::VecRRR {
1378         alu_op: pattern0_0.clone(),
1379         rd: expr1_0,
1380         rn: pattern1_0,
1381         rm: pattern2_0,
1382         size: pattern3_0.clone(),
1383     };
1384     let expr3_0 = C::emit(ctx, &expr2_0);
1385     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1386     return Some(expr4_0);
1387 }
1388 
1389 // Generated as internal constructor for term vec_lanes.
1390 pub fn constructor_vec_lanes<C: Context>(
1391     ctx: &mut C,
1392     arg0: &VecLanesOp,
1393     arg1: Reg,
1394     arg2: &VectorSize,
1395 ) -> Option<Reg> {
1396     let pattern0_0 = arg0;
1397     let pattern1_0 = arg1;
1398     let pattern2_0 = arg2;
1399     // Rule at src/isa/aarch64/inst.isle line 1405.
1400     let expr0_0: Type = I8X16;
1401     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1402     let expr2_0 = MInst::VecLanes {
1403         op: pattern0_0.clone(),
1404         rd: expr1_0,
1405         rn: pattern1_0,
1406         size: pattern2_0.clone(),
1407     };
1408     let expr3_0 = C::emit(ctx, &expr2_0);
1409     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1410     return Some(expr4_0);
1411 }
1412 
1413 // Generated as internal constructor for term vec_dup.
1414 pub fn constructor_vec_dup<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
1415     let pattern0_0 = arg0;
1416     let pattern1_0 = arg1;
1417     // Rule at src/isa/aarch64/inst.isle line 1412.
1418     let expr0_0: Type = I8X16;
1419     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1420     let expr2_0 = MInst::VecDup {
1421         rd: expr1_0,
1422         rn: pattern0_0,
1423         size: pattern1_0.clone(),
1424     };
1425     let expr3_0 = C::emit(ctx, &expr2_0);
1426     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1427     return Some(expr4_0);
1428 }
1429 
1430 // Generated as internal constructor for term alu_rr_imm12.
1431 pub fn constructor_alu_rr_imm12<C: Context>(
1432     ctx: &mut C,
1433     arg0: &ALUOp,
1434     arg1: Type,
1435     arg2: Reg,
1436     arg3: Imm12,
1437 ) -> Option<Reg> {
1438     let pattern0_0 = arg0;
1439     let pattern1_0 = arg1;
1440     let pattern2_0 = arg2;
1441     let pattern3_0 = arg3;
1442     // Rule at src/isa/aarch64/inst.isle line 1419.
1443     let expr0_0: Type = I64;
1444     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1445     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1446     let expr3_0 = MInst::AluRRImm12 {
1447         alu_op: pattern0_0.clone(),
1448         size: expr2_0,
1449         rd: expr1_0,
1450         rn: pattern2_0,
1451         imm12: pattern3_0,
1452     };
1453     let expr4_0 = C::emit(ctx, &expr3_0);
1454     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1455     return Some(expr5_0);
1456 }
1457 
1458 // Generated as internal constructor for term alu_rrr_shift.
1459 pub fn constructor_alu_rrr_shift<C: Context>(
1460     ctx: &mut C,
1461     arg0: &ALUOp,
1462     arg1: Type,
1463     arg2: Reg,
1464     arg3: Reg,
1465     arg4: ShiftOpAndAmt,
1466 ) -> Option<Reg> {
1467     let pattern0_0 = arg0;
1468     let pattern1_0 = arg1;
1469     let pattern2_0 = arg2;
1470     let pattern3_0 = arg3;
1471     let pattern4_0 = arg4;
1472     // Rule at src/isa/aarch64/inst.isle line 1426.
1473     let expr0_0: Type = I64;
1474     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1475     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1476     let expr3_0 = MInst::AluRRRShift {
1477         alu_op: pattern0_0.clone(),
1478         size: expr2_0,
1479         rd: expr1_0,
1480         rn: pattern2_0,
1481         rm: pattern3_0,
1482         shiftop: pattern4_0,
1483     };
1484     let expr4_0 = C::emit(ctx, &expr3_0);
1485     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1486     return Some(expr5_0);
1487 }
1488 
1489 // Generated as internal constructor for term alu_rrr_extend.
1490 pub fn constructor_alu_rrr_extend<C: Context>(
1491     ctx: &mut C,
1492     arg0: &ALUOp,
1493     arg1: Type,
1494     arg2: Reg,
1495     arg3: Reg,
1496     arg4: &ExtendOp,
1497 ) -> Option<Reg> {
1498     let pattern0_0 = arg0;
1499     let pattern1_0 = arg1;
1500     let pattern2_0 = arg2;
1501     let pattern3_0 = arg3;
1502     let pattern4_0 = arg4;
1503     // Rule at src/isa/aarch64/inst.isle line 1433.
1504     let expr0_0: Type = I64;
1505     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1506     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1507     let expr3_0 = MInst::AluRRRExtend {
1508         alu_op: pattern0_0.clone(),
1509         size: expr2_0,
1510         rd: expr1_0,
1511         rn: pattern2_0,
1512         rm: pattern3_0,
1513         extendop: pattern4_0.clone(),
1514     };
1515     let expr4_0 = C::emit(ctx, &expr3_0);
1516     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1517     return Some(expr5_0);
1518 }
1519 
1520 // Generated as internal constructor for term alu_rr_extend_reg.
1521 pub fn constructor_alu_rr_extend_reg<C: Context>(
1522     ctx: &mut C,
1523     arg0: &ALUOp,
1524     arg1: Type,
1525     arg2: Reg,
1526     arg3: &ExtendedValue,
1527 ) -> Option<Reg> {
1528     let pattern0_0 = arg0;
1529     let pattern1_0 = arg1;
1530     let pattern2_0 = arg2;
1531     let pattern3_0 = arg3;
1532     // Rule at src/isa/aarch64/inst.isle line 1441.
1533     let expr0_0 = C::put_extended_in_reg(ctx, pattern3_0);
1534     let expr1_0 = C::get_extended_op(ctx, pattern3_0);
1535     let expr2_0 =
1536         constructor_alu_rrr_extend(ctx, pattern0_0, pattern1_0, pattern2_0, expr0_0, &expr1_0)?;
1537     return Some(expr2_0);
1538 }
1539 
1540 // Generated as internal constructor for term alu_rrrr.
1541 pub fn constructor_alu_rrrr<C: Context>(
1542     ctx: &mut C,
1543     arg0: &ALUOp3,
1544     arg1: Reg,
1545     arg2: Reg,
1546     arg3: Reg,
1547 ) -> Option<Reg> {
1548     let pattern0_0 = arg0;
1549     let pattern1_0 = arg1;
1550     let pattern2_0 = arg2;
1551     let pattern3_0 = arg3;
1552     // Rule at src/isa/aarch64/inst.isle line 1448.
1553     let expr0_0: Type = I64;
1554     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1555     let expr2_0 = MInst::AluRRRR {
1556         alu_op: pattern0_0.clone(),
1557         rd: expr1_0,
1558         rn: pattern1_0,
1559         rm: pattern2_0,
1560         ra: pattern3_0,
1561     };
1562     let expr3_0 = C::emit(ctx, &expr2_0);
1563     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1564     return Some(expr4_0);
1565 }
1566 
1567 // Generated as internal constructor for term bit_rr.
1568 pub fn constructor_bit_rr<C: Context>(
1569     ctx: &mut C,
1570     arg0: &BitOp,
1571     arg1: Type,
1572     arg2: Reg,
1573 ) -> Option<Reg> {
1574     let pattern0_0 = arg0;
1575     let pattern1_0 = arg1;
1576     let pattern2_0 = arg2;
1577     // Rule at src/isa/aarch64/inst.isle line 1455.
1578     let expr0_0: Type = I64;
1579     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1580     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1581     let expr3_0 = MInst::BitRR {
1582         op: pattern0_0.clone(),
1583         size: expr2_0,
1584         rd: expr1_0,
1585         rn: pattern2_0,
1586     };
1587     let expr4_0 = C::emit(ctx, &expr3_0);
1588     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1589     return Some(expr5_0);
1590 }
1591 
1592 // Generated as internal constructor for term add_with_flags_paired.
1593 pub fn constructor_add_with_flags_paired<C: Context>(
1594     ctx: &mut C,
1595     arg0: Type,
1596     arg1: Reg,
1597     arg2: Reg,
1598 ) -> Option<ProducesFlags> {
1599     let pattern0_0 = arg0;
1600     let pattern1_0 = arg1;
1601     let pattern2_0 = arg2;
1602     // Rule at src/isa/aarch64/inst.isle line 1462.
1603     let expr0_0: Type = I64;
1604     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1605     let expr2_0 = ALUOp::AddS;
1606     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1607     let expr4_0 = MInst::AluRRR {
1608         alu_op: expr2_0,
1609         size: expr3_0,
1610         rd: expr1_0,
1611         rn: pattern1_0,
1612         rm: pattern2_0,
1613     };
1614     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1615     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1616         inst: expr4_0,
1617         result: expr5_0,
1618     };
1619     return Some(expr6_0);
1620 }
1621 
1622 // Generated as internal constructor for term adc_paired.
1623 pub fn constructor_adc_paired<C: Context>(
1624     ctx: &mut C,
1625     arg0: Type,
1626     arg1: Reg,
1627     arg2: Reg,
1628 ) -> Option<ConsumesFlags> {
1629     let pattern0_0 = arg0;
1630     let pattern1_0 = arg1;
1631     let pattern2_0 = arg2;
1632     // Rule at src/isa/aarch64/inst.isle line 1470.
1633     let expr0_0: Type = I64;
1634     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1635     let expr2_0 = ALUOp::Adc;
1636     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1637     let expr4_0 = MInst::AluRRR {
1638         alu_op: expr2_0,
1639         size: expr3_0,
1640         rd: expr1_0,
1641         rn: pattern1_0,
1642         rm: pattern2_0,
1643     };
1644     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1645     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1646         inst: expr4_0,
1647         result: expr5_0,
1648     };
1649     return Some(expr6_0);
1650 }
1651 
1652 // Generated as internal constructor for term sub_with_flags_paired.
1653 pub fn constructor_sub_with_flags_paired<C: Context>(
1654     ctx: &mut C,
1655     arg0: Type,
1656     arg1: Reg,
1657     arg2: Reg,
1658 ) -> Option<ProducesFlags> {
1659     let pattern0_0 = arg0;
1660     let pattern1_0 = arg1;
1661     let pattern2_0 = arg2;
1662     // Rule at src/isa/aarch64/inst.isle line 1478.
1663     let expr0_0: Type = I64;
1664     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1665     let expr2_0 = ALUOp::SubS;
1666     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1667     let expr4_0 = MInst::AluRRR {
1668         alu_op: expr2_0,
1669         size: expr3_0,
1670         rd: expr1_0,
1671         rn: pattern1_0,
1672         rm: pattern2_0,
1673     };
1674     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1675     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1676         inst: expr4_0,
1677         result: expr5_0,
1678     };
1679     return Some(expr6_0);
1680 }
1681 
1682 // Generated as internal constructor for term cmp64_imm.
1683 pub fn constructor_cmp64_imm<C: Context>(
1684     ctx: &mut C,
1685     arg0: Reg,
1686     arg1: Imm12,
1687 ) -> Option<ProducesFlags> {
1688     let pattern0_0 = arg0;
1689     let pattern1_0 = arg1;
1690     // Rule at src/isa/aarch64/inst.isle line 1485.
1691     let expr0_0 = ALUOp::SubS;
1692     let expr1_0 = OperandSize::Size64;
1693     let expr2_0 = C::writable_zero_reg(ctx);
1694     let expr3_0 = MInst::AluRRImm12 {
1695         alu_op: expr0_0,
1696         size: expr1_0,
1697         rd: expr2_0,
1698         rn: pattern0_0,
1699         imm12: pattern1_0,
1700     };
1701     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
1702     return Some(expr4_0);
1703 }
1704 
1705 // Generated as internal constructor for term sbc_paired.
1706 pub fn constructor_sbc_paired<C: Context>(
1707     ctx: &mut C,
1708     arg0: Type,
1709     arg1: Reg,
1710     arg2: Reg,
1711 ) -> Option<ConsumesFlags> {
1712     let pattern0_0 = arg0;
1713     let pattern1_0 = arg1;
1714     let pattern2_0 = arg2;
1715     // Rule at src/isa/aarch64/inst.isle line 1492.
1716     let expr0_0: Type = I64;
1717     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1718     let expr2_0 = ALUOp::Sbc;
1719     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1720     let expr4_0 = MInst::AluRRR {
1721         alu_op: expr2_0,
1722         size: expr3_0,
1723         rd: expr1_0,
1724         rn: pattern1_0,
1725         rm: pattern2_0,
1726     };
1727     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1728     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1729         inst: expr4_0,
1730         result: expr5_0,
1731     };
1732     return Some(expr6_0);
1733 }
1734 
1735 // Generated as internal constructor for term vec_misc.
1736 pub fn constructor_vec_misc<C: Context>(
1737     ctx: &mut C,
1738     arg0: &VecMisc2,
1739     arg1: Reg,
1740     arg2: &VectorSize,
1741 ) -> Option<Reg> {
1742     let pattern0_0 = arg0;
1743     let pattern1_0 = arg1;
1744     let pattern2_0 = arg2;
1745     // Rule at src/isa/aarch64/inst.isle line 1500.
1746     let expr0_0: Type = I8X16;
1747     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1748     let expr2_0 = MInst::VecMisc {
1749         op: pattern0_0.clone(),
1750         rd: expr1_0,
1751         rn: pattern1_0,
1752         size: pattern2_0.clone(),
1753     };
1754     let expr3_0 = C::emit(ctx, &expr2_0);
1755     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1756     return Some(expr4_0);
1757 }
1758 
1759 // Generated as internal constructor for term vec_rrr_long.
1760 pub fn constructor_vec_rrr_long<C: Context>(
1761     ctx: &mut C,
1762     arg0: &VecRRRLongOp,
1763     arg1: Reg,
1764     arg2: Reg,
1765     arg3: bool,
1766 ) -> Option<Reg> {
1767     let pattern0_0 = arg0;
1768     let pattern1_0 = arg1;
1769     let pattern2_0 = arg2;
1770     let pattern3_0 = arg3;
1771     // Rule at src/isa/aarch64/inst.isle line 1507.
1772     let expr0_0: Type = I8X16;
1773     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1774     let expr2_0 = MInst::VecRRRLong {
1775         alu_op: pattern0_0.clone(),
1776         rd: expr1_0,
1777         rn: pattern1_0,
1778         rm: pattern2_0,
1779         high_half: pattern3_0,
1780     };
1781     let expr3_0 = C::emit(ctx, &expr2_0);
1782     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1783     return Some(expr4_0);
1784 }
1785 
1786 // Generated as internal constructor for term vec_rrrr_long.
1787 pub fn constructor_vec_rrrr_long<C: Context>(
1788     ctx: &mut C,
1789     arg0: &VecRRRLongOp,
1790     arg1: Reg,
1791     arg2: Reg,
1792     arg3: Reg,
1793     arg4: bool,
1794 ) -> Option<Reg> {
1795     let pattern0_0 = arg0;
1796     let pattern1_0 = arg1;
1797     let pattern2_0 = arg2;
1798     let pattern3_0 = arg3;
1799     let pattern4_0 = arg4;
1800     // Rule at src/isa/aarch64/inst.isle line 1517.
1801     let expr0_0: Type = I8X16;
1802     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1803     let expr2_0 = MInst::FpuMove128 {
1804         rd: expr1_0,
1805         rn: pattern1_0,
1806     };
1807     let expr3_0 = C::emit(ctx, &expr2_0);
1808     let expr4_0 = MInst::VecRRRLong {
1809         alu_op: pattern0_0.clone(),
1810         rd: expr1_0,
1811         rn: pattern2_0,
1812         rm: pattern3_0,
1813         high_half: pattern4_0,
1814     };
1815     let expr5_0 = C::emit(ctx, &expr4_0);
1816     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1817     return Some(expr6_0);
1818 }
1819 
1820 // Generated as internal constructor for term vec_rr_narrow.
1821 pub fn constructor_vec_rr_narrow<C: Context>(
1822     ctx: &mut C,
1823     arg0: &VecRRNarrowOp,
1824     arg1: Reg,
1825     arg2: bool,
1826 ) -> Option<Reg> {
1827     let pattern0_0 = arg0;
1828     let pattern1_0 = arg1;
1829     let pattern2_0 = arg2;
1830     // Rule at src/isa/aarch64/inst.isle line 1525.
1831     let expr0_0: Type = I8X16;
1832     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1833     let expr2_0 = MInst::VecRRNarrow {
1834         op: pattern0_0.clone(),
1835         rd: expr1_0,
1836         rn: pattern1_0,
1837         high_half: pattern2_0,
1838     };
1839     let expr3_0 = C::emit(ctx, &expr2_0);
1840     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1841     return Some(expr4_0);
1842 }
1843 
1844 // Generated as internal constructor for term vec_rr_long.
1845 pub fn constructor_vec_rr_long<C: Context>(
1846     ctx: &mut C,
1847     arg0: &VecRRLongOp,
1848     arg1: Reg,
1849     arg2: bool,
1850 ) -> Option<Reg> {
1851     let pattern0_0 = arg0;
1852     let pattern1_0 = arg1;
1853     let pattern2_0 = arg2;
1854     // Rule at src/isa/aarch64/inst.isle line 1532.
1855     let expr0_0: Type = I8X16;
1856     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1857     let expr2_0 = MInst::VecRRLong {
1858         op: pattern0_0.clone(),
1859         rd: expr1_0,
1860         rn: pattern1_0,
1861         high_half: pattern2_0,
1862     };
1863     let expr3_0 = C::emit(ctx, &expr2_0);
1864     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1865     return Some(expr4_0);
1866 }
1867 
1868 // Generated as internal constructor for term mov_to_fpu.
1869 pub fn constructor_mov_to_fpu<C: Context>(
1870     ctx: &mut C,
1871     arg0: Reg,
1872     arg1: &ScalarSize,
1873 ) -> Option<Reg> {
1874     let pattern0_0 = arg0;
1875     let pattern1_0 = arg1;
1876     // Rule at src/isa/aarch64/inst.isle line 1539.
1877     let expr0_0: Type = I8X16;
1878     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1879     let expr2_0 = MInst::MovToFpu {
1880         rd: expr1_0,
1881         rn: pattern0_0,
1882         size: pattern1_0.clone(),
1883     };
1884     let expr3_0 = C::emit(ctx, &expr2_0);
1885     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1886     return Some(expr4_0);
1887 }
1888 
1889 // Generated as internal constructor for term mov_to_vec.
1890 pub fn constructor_mov_to_vec<C: Context>(
1891     ctx: &mut C,
1892     arg0: Reg,
1893     arg1: Reg,
1894     arg2: u8,
1895     arg3: &VectorSize,
1896 ) -> Option<Reg> {
1897     let pattern0_0 = arg0;
1898     let pattern1_0 = arg1;
1899     let pattern2_0 = arg2;
1900     let pattern3_0 = arg3;
1901     // Rule at src/isa/aarch64/inst.isle line 1546.
1902     let expr0_0: Type = I8X16;
1903     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1904     let expr2_0 = MInst::FpuMove128 {
1905         rd: expr1_0,
1906         rn: pattern0_0,
1907     };
1908     let expr3_0 = C::emit(ctx, &expr2_0);
1909     let expr4_0 = MInst::MovToVec {
1910         rd: expr1_0,
1911         rn: pattern1_0,
1912         idx: pattern2_0,
1913         size: pattern3_0.clone(),
1914     };
1915     let expr5_0 = C::emit(ctx, &expr4_0);
1916     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1917     return Some(expr6_0);
1918 }
1919 
1920 // Generated as internal constructor for term mov_from_vec.
1921 pub fn constructor_mov_from_vec<C: Context>(
1922     ctx: &mut C,
1923     arg0: Reg,
1924     arg1: u8,
1925     arg2: &VectorSize,
1926 ) -> Option<Reg> {
1927     let pattern0_0 = arg0;
1928     let pattern1_0 = arg1;
1929     let pattern2_0 = arg2;
1930     // Rule at src/isa/aarch64/inst.isle line 1554.
1931     let expr0_0: Type = I64;
1932     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1933     let expr2_0 = MInst::MovFromVec {
1934         rd: expr1_0,
1935         rn: pattern0_0,
1936         idx: pattern1_0,
1937         size: pattern2_0.clone(),
1938     };
1939     let expr3_0 = C::emit(ctx, &expr2_0);
1940     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1941     return Some(expr4_0);
1942 }
1943 
1944 // Generated as internal constructor for term mov_from_vec_signed.
1945 pub fn constructor_mov_from_vec_signed<C: Context>(
1946     ctx: &mut C,
1947     arg0: Reg,
1948     arg1: u8,
1949     arg2: &VectorSize,
1950     arg3: &OperandSize,
1951 ) -> Option<Reg> {
1952     let pattern0_0 = arg0;
1953     let pattern1_0 = arg1;
1954     let pattern2_0 = arg2;
1955     let pattern3_0 = arg3;
1956     // Rule at src/isa/aarch64/inst.isle line 1561.
1957     let expr0_0: Type = I64;
1958     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1959     let expr2_0 = MInst::MovFromVecSigned {
1960         rd: expr1_0,
1961         rn: pattern0_0,
1962         idx: pattern1_0,
1963         size: pattern2_0.clone(),
1964         scalar_size: pattern3_0.clone(),
1965     };
1966     let expr3_0 = C::emit(ctx, &expr2_0);
1967     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1968     return Some(expr4_0);
1969 }
1970 
1971 // Generated as internal constructor for term extend.
1972 pub fn constructor_extend<C: Context>(
1973     ctx: &mut C,
1974     arg0: Reg,
1975     arg1: bool,
1976     arg2: u8,
1977     arg3: u8,
1978 ) -> Option<Reg> {
1979     let pattern0_0 = arg0;
1980     let pattern1_0 = arg1;
1981     let pattern2_0 = arg2;
1982     let pattern3_0 = arg3;
1983     // Rule at src/isa/aarch64/inst.isle line 1568.
1984     let expr0_0: Type = I64;
1985     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1986     let expr2_0 = MInst::Extend {
1987         rd: expr1_0,
1988         rn: pattern0_0,
1989         signed: pattern1_0,
1990         from_bits: pattern2_0,
1991         to_bits: pattern3_0,
1992     };
1993     let expr3_0 = C::emit(ctx, &expr2_0);
1994     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1995     return Some(expr4_0);
1996 }
1997 
1998 // Generated as internal constructor for term load_acquire.
1999 pub fn constructor_load_acquire<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2000     let pattern0_0 = arg0;
2001     let pattern1_0 = arg1;
2002     // Rule at src/isa/aarch64/inst.isle line 1575.
2003     let expr0_0: Type = I64;
2004     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2005     let expr2_0 = MInst::LoadAcquire {
2006         access_ty: pattern0_0,
2007         rt: expr1_0,
2008         rn: pattern1_0,
2009     };
2010     let expr3_0 = C::emit(ctx, &expr2_0);
2011     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2012     return Some(expr4_0);
2013 }
2014 
2015 // Generated as internal constructor for term tst_imm.
2016 pub fn constructor_tst_imm<C: Context>(
2017     ctx: &mut C,
2018     arg0: Type,
2019     arg1: Reg,
2020     arg2: ImmLogic,
2021 ) -> Option<ProducesFlags> {
2022     let pattern0_0 = arg0;
2023     let pattern1_0 = arg1;
2024     let pattern2_0 = arg2;
2025     // Rule at src/isa/aarch64/inst.isle line 1585.
2026     let expr0_0 = ALUOp::AndS;
2027     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
2028     let expr2_0 = C::writable_zero_reg(ctx);
2029     let expr3_0 = MInst::AluRRImmLogic {
2030         alu_op: expr0_0,
2031         size: expr1_0,
2032         rd: expr2_0,
2033         rn: pattern1_0,
2034         imml: pattern2_0,
2035     };
2036     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
2037     return Some(expr4_0);
2038 }
2039 
2040 // Generated as internal constructor for term csel.
2041 pub fn constructor_csel<C: Context>(
2042     ctx: &mut C,
2043     arg0: &Cond,
2044     arg1: Reg,
2045     arg2: Reg,
2046 ) -> Option<ConsumesFlags> {
2047     let pattern0_0 = arg0;
2048     let pattern1_0 = arg1;
2049     let pattern2_0 = arg2;
2050     // Rule at src/isa/aarch64/inst.isle line 1599.
2051     let expr0_0: Type = I64;
2052     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2053     let expr2_0 = MInst::CSel {
2054         rd: expr1_0,
2055         cond: pattern0_0.clone(),
2056         rn: pattern1_0,
2057         rm: pattern2_0,
2058     };
2059     let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
2060     let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
2061         inst: expr2_0,
2062         result: expr3_0,
2063     };
2064     return Some(expr4_0);
2065 }
2066 
2067 // Generated as internal constructor for term add.
2068 pub fn constructor_add<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2069     let pattern0_0 = arg0;
2070     let pattern1_0 = arg1;
2071     let pattern2_0 = arg2;
2072     // Rule at src/isa/aarch64/inst.isle line 1608.
2073     let expr0_0 = ALUOp::Add;
2074     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2075     return Some(expr1_0);
2076 }
2077 
2078 // Generated as internal constructor for term add_imm.
2079 pub fn constructor_add_imm<C: Context>(
2080     ctx: &mut C,
2081     arg0: Type,
2082     arg1: Reg,
2083     arg2: Imm12,
2084 ) -> Option<Reg> {
2085     let pattern0_0 = arg0;
2086     let pattern1_0 = arg1;
2087     let pattern2_0 = arg2;
2088     // Rule at src/isa/aarch64/inst.isle line 1611.
2089     let expr0_0 = ALUOp::Add;
2090     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2091     return Some(expr1_0);
2092 }
2093 
2094 // Generated as internal constructor for term add_extend.
2095 pub fn constructor_add_extend<C: Context>(
2096     ctx: &mut C,
2097     arg0: Type,
2098     arg1: Reg,
2099     arg2: &ExtendedValue,
2100 ) -> Option<Reg> {
2101     let pattern0_0 = arg0;
2102     let pattern1_0 = arg1;
2103     let pattern2_0 = arg2;
2104     // Rule at src/isa/aarch64/inst.isle line 1614.
2105     let expr0_0 = ALUOp::Add;
2106     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2107     return Some(expr1_0);
2108 }
2109 
2110 // Generated as internal constructor for term add_shift.
2111 pub fn constructor_add_shift<C: Context>(
2112     ctx: &mut C,
2113     arg0: Type,
2114     arg1: Reg,
2115     arg2: Reg,
2116     arg3: ShiftOpAndAmt,
2117 ) -> Option<Reg> {
2118     let pattern0_0 = arg0;
2119     let pattern1_0 = arg1;
2120     let pattern2_0 = arg2;
2121     let pattern3_0 = arg3;
2122     // Rule at src/isa/aarch64/inst.isle line 1617.
2123     let expr0_0 = ALUOp::Add;
2124     let expr1_0 = constructor_alu_rrr_shift(
2125         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2126     )?;
2127     return Some(expr1_0);
2128 }
2129 
2130 // Generated as internal constructor for term add_vec.
2131 pub fn constructor_add_vec<C: Context>(
2132     ctx: &mut C,
2133     arg0: Reg,
2134     arg1: Reg,
2135     arg2: &VectorSize,
2136 ) -> Option<Reg> {
2137     let pattern0_0 = arg0;
2138     let pattern1_0 = arg1;
2139     let pattern2_0 = arg2;
2140     // Rule at src/isa/aarch64/inst.isle line 1620.
2141     let expr0_0 = VecALUOp::Add;
2142     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2143     return Some(expr1_0);
2144 }
2145 
2146 // Generated as internal constructor for term sub.
2147 pub fn constructor_sub<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2148     let pattern0_0 = arg0;
2149     let pattern1_0 = arg1;
2150     let pattern2_0 = arg2;
2151     // Rule at src/isa/aarch64/inst.isle line 1625.
2152     let expr0_0 = ALUOp::Sub;
2153     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2154     return Some(expr1_0);
2155 }
2156 
2157 // Generated as internal constructor for term sub_imm.
2158 pub fn constructor_sub_imm<C: Context>(
2159     ctx: &mut C,
2160     arg0: Type,
2161     arg1: Reg,
2162     arg2: Imm12,
2163 ) -> Option<Reg> {
2164     let pattern0_0 = arg0;
2165     let pattern1_0 = arg1;
2166     let pattern2_0 = arg2;
2167     // Rule at src/isa/aarch64/inst.isle line 1628.
2168     let expr0_0 = ALUOp::Sub;
2169     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2170     return Some(expr1_0);
2171 }
2172 
2173 // Generated as internal constructor for term sub_extend.
2174 pub fn constructor_sub_extend<C: Context>(
2175     ctx: &mut C,
2176     arg0: Type,
2177     arg1: Reg,
2178     arg2: &ExtendedValue,
2179 ) -> Option<Reg> {
2180     let pattern0_0 = arg0;
2181     let pattern1_0 = arg1;
2182     let pattern2_0 = arg2;
2183     // Rule at src/isa/aarch64/inst.isle line 1631.
2184     let expr0_0 = ALUOp::Sub;
2185     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2186     return Some(expr1_0);
2187 }
2188 
2189 // Generated as internal constructor for term sub_shift.
2190 pub fn constructor_sub_shift<C: Context>(
2191     ctx: &mut C,
2192     arg0: Type,
2193     arg1: Reg,
2194     arg2: Reg,
2195     arg3: ShiftOpAndAmt,
2196 ) -> Option<Reg> {
2197     let pattern0_0 = arg0;
2198     let pattern1_0 = arg1;
2199     let pattern2_0 = arg2;
2200     let pattern3_0 = arg3;
2201     // Rule at src/isa/aarch64/inst.isle line 1634.
2202     let expr0_0 = ALUOp::Sub;
2203     let expr1_0 = constructor_alu_rrr_shift(
2204         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2205     )?;
2206     return Some(expr1_0);
2207 }
2208 
2209 // Generated as internal constructor for term sub_vec.
2210 pub fn constructor_sub_vec<C: Context>(
2211     ctx: &mut C,
2212     arg0: Reg,
2213     arg1: Reg,
2214     arg2: &VectorSize,
2215 ) -> Option<Reg> {
2216     let pattern0_0 = arg0;
2217     let pattern1_0 = arg1;
2218     let pattern2_0 = arg2;
2219     // Rule at src/isa/aarch64/inst.isle line 1637.
2220     let expr0_0 = VecALUOp::Sub;
2221     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2222     return Some(expr1_0);
2223 }
2224 
2225 // Generated as internal constructor for term madd.
2226 pub fn constructor_madd<C: Context>(
2227     ctx: &mut C,
2228     arg0: Type,
2229     arg1: Reg,
2230     arg2: Reg,
2231     arg3: Reg,
2232 ) -> Option<Reg> {
2233     let pattern0_0 = arg0;
2234     if pattern0_0 == I64 {
2235         let pattern2_0 = arg1;
2236         let pattern3_0 = arg2;
2237         let pattern4_0 = arg3;
2238         // Rule at src/isa/aarch64/inst.isle line 1643.
2239         let expr0_0 = constructor_madd64(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2240         return Some(expr0_0);
2241     }
2242     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2243         let pattern2_0 = arg1;
2244         let pattern3_0 = arg2;
2245         let pattern4_0 = arg3;
2246         // Rule at src/isa/aarch64/inst.isle line 1642.
2247         let expr0_0 = constructor_madd32(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2248         return Some(expr0_0);
2249     }
2250     return None;
2251 }
2252 
2253 // Generated as internal constructor for term madd32.
2254 pub fn constructor_madd32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2255     let pattern0_0 = arg0;
2256     let pattern1_0 = arg1;
2257     let pattern2_0 = arg2;
2258     // Rule at src/isa/aarch64/inst.isle line 1646.
2259     let expr0_0 = ALUOp3::MAdd32;
2260     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2261     return Some(expr1_0);
2262 }
2263 
2264 // Generated as internal constructor for term madd64.
2265 pub fn constructor_madd64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2266     let pattern0_0 = arg0;
2267     let pattern1_0 = arg1;
2268     let pattern2_0 = arg2;
2269     // Rule at src/isa/aarch64/inst.isle line 1649.
2270     let expr0_0 = ALUOp3::MAdd64;
2271     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2272     return Some(expr1_0);
2273 }
2274 
2275 // Generated as internal constructor for term msub64.
2276 pub fn constructor_msub64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2277     let pattern0_0 = arg0;
2278     let pattern1_0 = arg1;
2279     let pattern2_0 = arg2;
2280     // Rule at src/isa/aarch64/inst.isle line 1654.
2281     let expr0_0 = ALUOp3::MSub64;
2282     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2283     return Some(expr1_0);
2284 }
2285 
2286 // Generated as internal constructor for term uqadd.
2287 pub fn constructor_uqadd<C: Context>(
2288     ctx: &mut C,
2289     arg0: Reg,
2290     arg1: Reg,
2291     arg2: &VectorSize,
2292 ) -> Option<Reg> {
2293     let pattern0_0 = arg0;
2294     let pattern1_0 = arg1;
2295     let pattern2_0 = arg2;
2296     // Rule at src/isa/aarch64/inst.isle line 1658.
2297     let expr0_0 = VecALUOp::Uqadd;
2298     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2299     return Some(expr1_0);
2300 }
2301 
2302 // Generated as internal constructor for term sqadd.
2303 pub fn constructor_sqadd<C: Context>(
2304     ctx: &mut C,
2305     arg0: Reg,
2306     arg1: Reg,
2307     arg2: &VectorSize,
2308 ) -> Option<Reg> {
2309     let pattern0_0 = arg0;
2310     let pattern1_0 = arg1;
2311     let pattern2_0 = arg2;
2312     // Rule at src/isa/aarch64/inst.isle line 1662.
2313     let expr0_0 = VecALUOp::Sqadd;
2314     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2315     return Some(expr1_0);
2316 }
2317 
2318 // Generated as internal constructor for term uqsub.
2319 pub fn constructor_uqsub<C: Context>(
2320     ctx: &mut C,
2321     arg0: Reg,
2322     arg1: Reg,
2323     arg2: &VectorSize,
2324 ) -> Option<Reg> {
2325     let pattern0_0 = arg0;
2326     let pattern1_0 = arg1;
2327     let pattern2_0 = arg2;
2328     // Rule at src/isa/aarch64/inst.isle line 1666.
2329     let expr0_0 = VecALUOp::Uqsub;
2330     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2331     return Some(expr1_0);
2332 }
2333 
2334 // Generated as internal constructor for term sqsub.
2335 pub fn constructor_sqsub<C: Context>(
2336     ctx: &mut C,
2337     arg0: Reg,
2338     arg1: Reg,
2339     arg2: &VectorSize,
2340 ) -> Option<Reg> {
2341     let pattern0_0 = arg0;
2342     let pattern1_0 = arg1;
2343     let pattern2_0 = arg2;
2344     // Rule at src/isa/aarch64/inst.isle line 1670.
2345     let expr0_0 = VecALUOp::Sqsub;
2346     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2347     return Some(expr1_0);
2348 }
2349 
2350 // Generated as internal constructor for term umulh.
2351 pub fn constructor_umulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2352     let pattern0_0 = arg0;
2353     let pattern1_0 = arg1;
2354     let pattern2_0 = arg2;
2355     // Rule at src/isa/aarch64/inst.isle line 1674.
2356     let expr0_0 = ALUOp::UMulH;
2357     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2358     return Some(expr1_0);
2359 }
2360 
2361 // Generated as internal constructor for term smulh.
2362 pub fn constructor_smulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2363     let pattern0_0 = arg0;
2364     let pattern1_0 = arg1;
2365     let pattern2_0 = arg2;
2366     // Rule at src/isa/aarch64/inst.isle line 1678.
2367     let expr0_0 = ALUOp::SMulH;
2368     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2369     return Some(expr1_0);
2370 }
2371 
2372 // Generated as internal constructor for term mul.
2373 pub fn constructor_mul<C: Context>(
2374     ctx: &mut C,
2375     arg0: Reg,
2376     arg1: Reg,
2377     arg2: &VectorSize,
2378 ) -> Option<Reg> {
2379     let pattern0_0 = arg0;
2380     let pattern1_0 = arg1;
2381     let pattern2_0 = arg2;
2382     // Rule at src/isa/aarch64/inst.isle line 1682.
2383     let expr0_0 = VecALUOp::Mul;
2384     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2385     return Some(expr1_0);
2386 }
2387 
2388 // Generated as internal constructor for term neg.
2389 pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2390     let pattern0_0 = arg0;
2391     let pattern1_0 = arg1;
2392     // Rule at src/isa/aarch64/inst.isle line 1686.
2393     let expr0_0 = VecMisc2::Neg;
2394     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2395     return Some(expr1_0);
2396 }
2397 
2398 // Generated as internal constructor for term rev64.
2399 pub fn constructor_rev64<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2400     let pattern0_0 = arg0;
2401     let pattern1_0 = arg1;
2402     // Rule at src/isa/aarch64/inst.isle line 1690.
2403     let expr0_0 = VecMisc2::Rev64;
2404     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2405     return Some(expr1_0);
2406 }
2407 
2408 // Generated as internal constructor for term xtn64.
2409 pub fn constructor_xtn64<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2410     let pattern0_0 = arg0;
2411     let pattern1_0 = arg1;
2412     // Rule at src/isa/aarch64/inst.isle line 1694.
2413     let expr0_0 = VecRRNarrowOp::Xtn64;
2414     let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2415     return Some(expr1_0);
2416 }
2417 
2418 // Generated as internal constructor for term addp.
2419 pub fn constructor_addp<C: Context>(
2420     ctx: &mut C,
2421     arg0: Reg,
2422     arg1: Reg,
2423     arg2: &VectorSize,
2424 ) -> Option<Reg> {
2425     let pattern0_0 = arg0;
2426     let pattern1_0 = arg1;
2427     let pattern2_0 = arg2;
2428     // Rule at src/isa/aarch64/inst.isle line 1698.
2429     let expr0_0 = VecALUOp::Addp;
2430     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2431     return Some(expr1_0);
2432 }
2433 
2434 // Generated as internal constructor for term addv.
2435 pub fn constructor_addv<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2436     let pattern0_0 = arg0;
2437     let pattern1_0 = arg1;
2438     // Rule at src/isa/aarch64/inst.isle line 1702.
2439     let expr0_0 = VecLanesOp::Addv;
2440     let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2441     return Some(expr1_0);
2442 }
2443 
2444 // Generated as internal constructor for term shll32.
2445 pub fn constructor_shll32<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2446     let pattern0_0 = arg0;
2447     let pattern1_0 = arg1;
2448     // Rule at src/isa/aarch64/inst.isle line 1706.
2449     let expr0_0 = VecRRLongOp::Shll32;
2450     let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2451     return Some(expr1_0);
2452 }
2453 
2454 // Generated as internal constructor for term umlal32.
2455 pub fn constructor_umlal32<C: Context>(
2456     ctx: &mut C,
2457     arg0: Reg,
2458     arg1: Reg,
2459     arg2: Reg,
2460     arg3: bool,
2461 ) -> Option<Reg> {
2462     let pattern0_0 = arg0;
2463     let pattern1_0 = arg1;
2464     let pattern2_0 = arg2;
2465     let pattern3_0 = arg3;
2466     // Rule at src/isa/aarch64/inst.isle line 1710.
2467     let expr0_0 = VecRRRLongOp::Umlal32;
2468     let expr1_0 = constructor_vec_rrrr_long(
2469         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2470     )?;
2471     return Some(expr1_0);
2472 }
2473 
2474 // Generated as internal constructor for term smull8.
2475 pub fn constructor_smull8<C: Context>(
2476     ctx: &mut C,
2477     arg0: Reg,
2478     arg1: Reg,
2479     arg2: bool,
2480 ) -> Option<Reg> {
2481     let pattern0_0 = arg0;
2482     let pattern1_0 = arg1;
2483     let pattern2_0 = arg2;
2484     // Rule at src/isa/aarch64/inst.isle line 1714.
2485     let expr0_0 = VecRRRLongOp::Smull8;
2486     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2487     return Some(expr1_0);
2488 }
2489 
2490 // Generated as internal constructor for term umull8.
2491 pub fn constructor_umull8<C: Context>(
2492     ctx: &mut C,
2493     arg0: Reg,
2494     arg1: Reg,
2495     arg2: bool,
2496 ) -> Option<Reg> {
2497     let pattern0_0 = arg0;
2498     let pattern1_0 = arg1;
2499     let pattern2_0 = arg2;
2500     // Rule at src/isa/aarch64/inst.isle line 1718.
2501     let expr0_0 = VecRRRLongOp::Umull8;
2502     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2503     return Some(expr1_0);
2504 }
2505 
2506 // Generated as internal constructor for term smull16.
2507 pub fn constructor_smull16<C: Context>(
2508     ctx: &mut C,
2509     arg0: Reg,
2510     arg1: Reg,
2511     arg2: bool,
2512 ) -> Option<Reg> {
2513     let pattern0_0 = arg0;
2514     let pattern1_0 = arg1;
2515     let pattern2_0 = arg2;
2516     // Rule at src/isa/aarch64/inst.isle line 1722.
2517     let expr0_0 = VecRRRLongOp::Smull16;
2518     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2519     return Some(expr1_0);
2520 }
2521 
2522 // Generated as internal constructor for term umull16.
2523 pub fn constructor_umull16<C: Context>(
2524     ctx: &mut C,
2525     arg0: Reg,
2526     arg1: Reg,
2527     arg2: bool,
2528 ) -> Option<Reg> {
2529     let pattern0_0 = arg0;
2530     let pattern1_0 = arg1;
2531     let pattern2_0 = arg2;
2532     // Rule at src/isa/aarch64/inst.isle line 1726.
2533     let expr0_0 = VecRRRLongOp::Umull16;
2534     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2535     return Some(expr1_0);
2536 }
2537 
2538 // Generated as internal constructor for term smull32.
2539 pub fn constructor_smull32<C: Context>(
2540     ctx: &mut C,
2541     arg0: Reg,
2542     arg1: Reg,
2543     arg2: bool,
2544 ) -> Option<Reg> {
2545     let pattern0_0 = arg0;
2546     let pattern1_0 = arg1;
2547     let pattern2_0 = arg2;
2548     // Rule at src/isa/aarch64/inst.isle line 1730.
2549     let expr0_0 = VecRRRLongOp::Smull32;
2550     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2551     return Some(expr1_0);
2552 }
2553 
2554 // Generated as internal constructor for term umull32.
2555 pub fn constructor_umull32<C: Context>(
2556     ctx: &mut C,
2557     arg0: Reg,
2558     arg1: Reg,
2559     arg2: bool,
2560 ) -> Option<Reg> {
2561     let pattern0_0 = arg0;
2562     let pattern1_0 = arg1;
2563     let pattern2_0 = arg2;
2564     // Rule at src/isa/aarch64/inst.isle line 1734.
2565     let expr0_0 = VecRRRLongOp::Umull32;
2566     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2567     return Some(expr1_0);
2568 }
2569 
2570 // Generated as internal constructor for term asr.
2571 pub fn constructor_asr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2572     let pattern0_0 = arg0;
2573     let pattern1_0 = arg1;
2574     let pattern2_0 = arg2;
2575     // Rule at src/isa/aarch64/inst.isle line 1738.
2576     let expr0_0 = ALUOp::Asr;
2577     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2578     return Some(expr1_0);
2579 }
2580 
2581 // Generated as internal constructor for term asr_imm.
2582 pub fn constructor_asr_imm<C: Context>(
2583     ctx: &mut C,
2584     arg0: Type,
2585     arg1: Reg,
2586     arg2: ImmShift,
2587 ) -> Option<Reg> {
2588     let pattern0_0 = arg0;
2589     let pattern1_0 = arg1;
2590     let pattern2_0 = arg2;
2591     // Rule at src/isa/aarch64/inst.isle line 1741.
2592     let expr0_0 = ALUOp::Asr;
2593     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2594     return Some(expr1_0);
2595 }
2596 
2597 // Generated as internal constructor for term lsr.
2598 pub fn constructor_lsr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2599     let pattern0_0 = arg0;
2600     let pattern1_0 = arg1;
2601     let pattern2_0 = arg2;
2602     // Rule at src/isa/aarch64/inst.isle line 1745.
2603     let expr0_0 = ALUOp::Lsr;
2604     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2605     return Some(expr1_0);
2606 }
2607 
2608 // Generated as internal constructor for term lsr_imm.
2609 pub fn constructor_lsr_imm<C: Context>(
2610     ctx: &mut C,
2611     arg0: Type,
2612     arg1: Reg,
2613     arg2: ImmShift,
2614 ) -> Option<Reg> {
2615     let pattern0_0 = arg0;
2616     let pattern1_0 = arg1;
2617     let pattern2_0 = arg2;
2618     // Rule at src/isa/aarch64/inst.isle line 1748.
2619     let expr0_0 = ALUOp::Lsr;
2620     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2621     return Some(expr1_0);
2622 }
2623 
2624 // Generated as internal constructor for term lsl.
2625 pub fn constructor_lsl<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2626     let pattern0_0 = arg0;
2627     let pattern1_0 = arg1;
2628     let pattern2_0 = arg2;
2629     // Rule at src/isa/aarch64/inst.isle line 1752.
2630     let expr0_0 = ALUOp::Lsl;
2631     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2632     return Some(expr1_0);
2633 }
2634 
2635 // Generated as internal constructor for term lsl_imm.
2636 pub fn constructor_lsl_imm<C: Context>(
2637     ctx: &mut C,
2638     arg0: Type,
2639     arg1: Reg,
2640     arg2: ImmShift,
2641 ) -> Option<Reg> {
2642     let pattern0_0 = arg0;
2643     let pattern1_0 = arg1;
2644     let pattern2_0 = arg2;
2645     // Rule at src/isa/aarch64/inst.isle line 1755.
2646     let expr0_0 = ALUOp::Lsl;
2647     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2648     return Some(expr1_0);
2649 }
2650 
2651 // Generated as internal constructor for term a64_udiv.
2652 pub fn constructor_a64_udiv<C: Context>(
2653     ctx: &mut C,
2654     arg0: Type,
2655     arg1: Reg,
2656     arg2: Reg,
2657 ) -> Option<Reg> {
2658     let pattern0_0 = arg0;
2659     let pattern1_0 = arg1;
2660     let pattern2_0 = arg2;
2661     // Rule at src/isa/aarch64/inst.isle line 1759.
2662     let expr0_0 = ALUOp::UDiv;
2663     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2664     return Some(expr1_0);
2665 }
2666 
2667 // Generated as internal constructor for term a64_sdiv.
2668 pub fn constructor_a64_sdiv<C: Context>(
2669     ctx: &mut C,
2670     arg0: Type,
2671     arg1: Reg,
2672     arg2: Reg,
2673 ) -> Option<Reg> {
2674     let pattern0_0 = arg0;
2675     let pattern1_0 = arg1;
2676     let pattern2_0 = arg2;
2677     // Rule at src/isa/aarch64/inst.isle line 1763.
2678     let expr0_0 = ALUOp::SDiv;
2679     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2680     return Some(expr1_0);
2681 }
2682 
2683 // Generated as internal constructor for term not.
2684 pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2685     let pattern0_0 = arg0;
2686     let pattern1_0 = arg1;
2687     // Rule at src/isa/aarch64/inst.isle line 1767.
2688     let expr0_0 = VecMisc2::Not;
2689     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2690     return Some(expr1_0);
2691 }
2692 
2693 // Generated as internal constructor for term orr_not.
2694 pub fn constructor_orr_not<C: Context>(
2695     ctx: &mut C,
2696     arg0: Type,
2697     arg1: Reg,
2698     arg2: Reg,
2699 ) -> Option<Reg> {
2700     let pattern0_0 = arg0;
2701     let pattern1_0 = arg1;
2702     let pattern2_0 = arg2;
2703     // Rule at src/isa/aarch64/inst.isle line 1772.
2704     let expr0_0 = ALUOp::OrrNot;
2705     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2706     return Some(expr1_0);
2707 }
2708 
2709 // Generated as internal constructor for term orr_not_shift.
2710 pub fn constructor_orr_not_shift<C: Context>(
2711     ctx: &mut C,
2712     arg0: Type,
2713     arg1: Reg,
2714     arg2: Reg,
2715     arg3: ShiftOpAndAmt,
2716 ) -> Option<Reg> {
2717     let pattern0_0 = arg0;
2718     let pattern1_0 = arg1;
2719     let pattern2_0 = arg2;
2720     let pattern3_0 = arg3;
2721     // Rule at src/isa/aarch64/inst.isle line 1775.
2722     let expr0_0 = ALUOp::OrrNot;
2723     let expr1_0 = constructor_alu_rrr_shift(
2724         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2725     )?;
2726     return Some(expr1_0);
2727 }
2728 
2729 // Generated as internal constructor for term orr.
2730 pub fn constructor_orr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2731     let pattern0_0 = arg0;
2732     let pattern1_0 = arg1;
2733     let pattern2_0 = arg2;
2734     // Rule at src/isa/aarch64/inst.isle line 1780.
2735     let expr0_0 = ALUOp::Orr;
2736     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2737     return Some(expr1_0);
2738 }
2739 
2740 // Generated as internal constructor for term orr_imm.
2741 pub fn constructor_orr_imm<C: Context>(
2742     ctx: &mut C,
2743     arg0: Type,
2744     arg1: Reg,
2745     arg2: ImmLogic,
2746 ) -> Option<Reg> {
2747     let pattern0_0 = arg0;
2748     let pattern1_0 = arg1;
2749     let pattern2_0 = arg2;
2750     // Rule at src/isa/aarch64/inst.isle line 1783.
2751     let expr0_0 = ALUOp::Orr;
2752     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2753     return Some(expr1_0);
2754 }
2755 
2756 // Generated as internal constructor for term orr_vec.
2757 pub fn constructor_orr_vec<C: Context>(
2758     ctx: &mut C,
2759     arg0: Reg,
2760     arg1: Reg,
2761     arg2: &VectorSize,
2762 ) -> Option<Reg> {
2763     let pattern0_0 = arg0;
2764     let pattern1_0 = arg1;
2765     let pattern2_0 = arg2;
2766     // Rule at src/isa/aarch64/inst.isle line 1786.
2767     let expr0_0 = VecALUOp::Orr;
2768     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2769     return Some(expr1_0);
2770 }
2771 
2772 // Generated as internal constructor for term and_imm.
2773 pub fn constructor_and_imm<C: Context>(
2774     ctx: &mut C,
2775     arg0: Type,
2776     arg1: Reg,
2777     arg2: ImmLogic,
2778 ) -> Option<Reg> {
2779     let pattern0_0 = arg0;
2780     let pattern1_0 = arg1;
2781     let pattern2_0 = arg2;
2782     // Rule at src/isa/aarch64/inst.isle line 1791.
2783     let expr0_0 = ALUOp::And;
2784     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2785     return Some(expr1_0);
2786 }
2787 
2788 // Generated as internal constructor for term and_vec.
2789 pub fn constructor_and_vec<C: Context>(
2790     ctx: &mut C,
2791     arg0: Reg,
2792     arg1: Reg,
2793     arg2: &VectorSize,
2794 ) -> Option<Reg> {
2795     let pattern0_0 = arg0;
2796     let pattern1_0 = arg1;
2797     let pattern2_0 = arg2;
2798     // Rule at src/isa/aarch64/inst.isle line 1794.
2799     let expr0_0 = VecALUOp::And;
2800     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2801     return Some(expr1_0);
2802 }
2803 
2804 // Generated as internal constructor for term eor_vec.
2805 pub fn constructor_eor_vec<C: Context>(
2806     ctx: &mut C,
2807     arg0: Reg,
2808     arg1: Reg,
2809     arg2: &VectorSize,
2810 ) -> Option<Reg> {
2811     let pattern0_0 = arg0;
2812     let pattern1_0 = arg1;
2813     let pattern2_0 = arg2;
2814     // Rule at src/isa/aarch64/inst.isle line 1798.
2815     let expr0_0 = VecALUOp::Eor;
2816     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2817     return Some(expr1_0);
2818 }
2819 
2820 // Generated as internal constructor for term bic_vec.
2821 pub fn constructor_bic_vec<C: Context>(
2822     ctx: &mut C,
2823     arg0: Reg,
2824     arg1: Reg,
2825     arg2: &VectorSize,
2826 ) -> Option<Reg> {
2827     let pattern0_0 = arg0;
2828     let pattern1_0 = arg1;
2829     let pattern2_0 = arg2;
2830     // Rule at src/isa/aarch64/inst.isle line 1802.
2831     let expr0_0 = VecALUOp::Bic;
2832     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2833     return Some(expr1_0);
2834 }
2835 
2836 // Generated as internal constructor for term sshl.
2837 pub fn constructor_sshl<C: Context>(
2838     ctx: &mut C,
2839     arg0: Reg,
2840     arg1: Reg,
2841     arg2: &VectorSize,
2842 ) -> Option<Reg> {
2843     let pattern0_0 = arg0;
2844     let pattern1_0 = arg1;
2845     let pattern2_0 = arg2;
2846     // Rule at src/isa/aarch64/inst.isle line 1806.
2847     let expr0_0 = VecALUOp::Sshl;
2848     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2849     return Some(expr1_0);
2850 }
2851 
2852 // Generated as internal constructor for term ushl.
2853 pub fn constructor_ushl<C: Context>(
2854     ctx: &mut C,
2855     arg0: Reg,
2856     arg1: Reg,
2857     arg2: &VectorSize,
2858 ) -> Option<Reg> {
2859     let pattern0_0 = arg0;
2860     let pattern1_0 = arg1;
2861     let pattern2_0 = arg2;
2862     // Rule at src/isa/aarch64/inst.isle line 1810.
2863     let expr0_0 = VecALUOp::Ushl;
2864     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2865     return Some(expr1_0);
2866 }
2867 
2868 // Generated as internal constructor for term a64_rotr.
2869 pub fn constructor_a64_rotr<C: Context>(
2870     ctx: &mut C,
2871     arg0: Type,
2872     arg1: Reg,
2873     arg2: Reg,
2874 ) -> Option<Reg> {
2875     let pattern0_0 = arg0;
2876     let pattern1_0 = arg1;
2877     let pattern2_0 = arg2;
2878     // Rule at src/isa/aarch64/inst.isle line 1815.
2879     let expr0_0 = ALUOp::RotR;
2880     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2881     return Some(expr1_0);
2882 }
2883 
2884 // Generated as internal constructor for term a64_rotr_imm.
2885 pub fn constructor_a64_rotr_imm<C: Context>(
2886     ctx: &mut C,
2887     arg0: Type,
2888     arg1: Reg,
2889     arg2: ImmShift,
2890 ) -> Option<Reg> {
2891     let pattern0_0 = arg0;
2892     let pattern1_0 = arg1;
2893     let pattern2_0 = arg2;
2894     // Rule at src/isa/aarch64/inst.isle line 1818.
2895     let expr0_0 = ALUOp::RotR;
2896     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2897     return Some(expr1_0);
2898 }
2899 
2900 // Generated as internal constructor for term rbit.
2901 pub fn constructor_rbit<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2902     let pattern0_0 = arg0;
2903     let pattern1_0 = arg1;
2904     // Rule at src/isa/aarch64/inst.isle line 1823.
2905     let expr0_0 = BitOp::RBit;
2906     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2907     return Some(expr1_0);
2908 }
2909 
2910 // Generated as internal constructor for term a64_clz.
2911 pub fn constructor_a64_clz<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2912     let pattern0_0 = arg0;
2913     let pattern1_0 = arg1;
2914     // Rule at src/isa/aarch64/inst.isle line 1828.
2915     let expr0_0 = BitOp::Clz;
2916     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2917     return Some(expr1_0);
2918 }
2919 
2920 // Generated as internal constructor for term a64_cls.
2921 pub fn constructor_a64_cls<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2922     let pattern0_0 = arg0;
2923     let pattern1_0 = arg1;
2924     // Rule at src/isa/aarch64/inst.isle line 1833.
2925     let expr0_0 = BitOp::Cls;
2926     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2927     return Some(expr1_0);
2928 }
2929 
2930 // Generated as internal constructor for term eon.
2931 pub fn constructor_eon<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2932     let pattern0_0 = arg0;
2933     let pattern1_0 = arg1;
2934     let pattern2_0 = arg2;
2935     // Rule at src/isa/aarch64/inst.isle line 1838.
2936     let expr0_0 = ALUOp::EorNot;
2937     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2938     return Some(expr1_0);
2939 }
2940 
2941 // Generated as internal constructor for term vec_cnt.
2942 pub fn constructor_vec_cnt<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2943     let pattern0_0 = arg0;
2944     let pattern1_0 = arg1;
2945     // Rule at src/isa/aarch64/inst.isle line 1843.
2946     let expr0_0 = VecMisc2::Cnt;
2947     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2948     return Some(expr1_0);
2949 }
2950 
2951 // Generated as internal constructor for term imm.
2952 pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
2953     let pattern0_0 = arg0;
2954     if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) {
2955         let pattern2_0 = arg1;
2956         let closure3 = || {
2957             let expr0_0: Type = I64;
2958             return Some(expr0_0);
2959         };
2960         if let Some(pattern3_0) = closure3() {
2961             if let Some(pattern4_0) = C::imm_logic_from_u64(ctx, pattern2_0, pattern3_0) {
2962                 // Rule at src/isa/aarch64/inst.isle line 1858.
2963                 let expr0_0: Type = I64;
2964                 let expr1_0 = C::zero_reg(ctx);
2965                 let expr2_0 = constructor_orr_imm(ctx, expr0_0, expr1_0, pattern4_0)?;
2966                 return Some(expr2_0);
2967             }
2968         }
2969         if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) {
2970             // Rule at src/isa/aarch64/inst.isle line 1850.
2971             let expr0_0 = OperandSize::Size64;
2972             let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?;
2973             return Some(expr1_0);
2974         }
2975         if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) {
2976             // Rule at src/isa/aarch64/inst.isle line 1854.
2977             let expr0_0 = OperandSize::Size64;
2978             let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?;
2979             return Some(expr1_0);
2980         }
2981         // Rule at src/isa/aarch64/inst.isle line 1865.
2982         let expr0_0 = C::load_constant64_full(ctx, pattern2_0);
2983         return Some(expr0_0);
2984     }
2985     return None;
2986 }
2987 
2988 // Generated as internal constructor for term put_in_reg_sext32.
2989 pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
2990     let pattern0_0 = arg0;
2991     let pattern1_0 = C::value_type(ctx, pattern0_0);
2992     if pattern1_0 == I32 {
2993         // Rule at src/isa/aarch64/inst.isle line 1876.
2994         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
2995         return Some(expr0_0);
2996     }
2997     if pattern1_0 == I64 {
2998         // Rule at src/isa/aarch64/inst.isle line 1877.
2999         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3000         return Some(expr0_0);
3001     }
3002     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3003         // Rule at src/isa/aarch64/inst.isle line 1872.
3004         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3005         let expr1_0: bool = true;
3006         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3007         let expr3_0: u8 = 32;
3008         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3009         return Some(expr4_0);
3010     }
3011     return None;
3012 }
3013 
3014 // Generated as internal constructor for term put_in_reg_zext32.
3015 pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3016     let pattern0_0 = arg0;
3017     let pattern1_0 = C::value_type(ctx, pattern0_0);
3018     if pattern1_0 == I32 {
3019         // Rule at src/isa/aarch64/inst.isle line 1885.
3020         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3021         return Some(expr0_0);
3022     }
3023     if pattern1_0 == I64 {
3024         // Rule at src/isa/aarch64/inst.isle line 1886.
3025         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3026         return Some(expr0_0);
3027     }
3028     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3029         // Rule at src/isa/aarch64/inst.isle line 1881.
3030         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3031         let expr1_0: bool = false;
3032         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3033         let expr3_0: u8 = 32;
3034         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3035         return Some(expr4_0);
3036     }
3037     return None;
3038 }
3039 
3040 // Generated as internal constructor for term put_in_reg_sext64.
3041 pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3042     let pattern0_0 = arg0;
3043     let pattern1_0 = C::value_type(ctx, pattern0_0);
3044     if pattern1_0 == I64 {
3045         // Rule at src/isa/aarch64/inst.isle line 1894.
3046         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3047         return Some(expr0_0);
3048     }
3049     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3050         // Rule at src/isa/aarch64/inst.isle line 1890.
3051         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3052         let expr1_0: bool = true;
3053         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3054         let expr3_0: u8 = 64;
3055         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3056         return Some(expr4_0);
3057     }
3058     return None;
3059 }
3060 
3061 // Generated as internal constructor for term put_in_reg_zext64.
3062 pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3063     let pattern0_0 = arg0;
3064     let pattern1_0 = C::value_type(ctx, pattern0_0);
3065     if pattern1_0 == I64 {
3066         // Rule at src/isa/aarch64/inst.isle line 1902.
3067         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3068         return Some(expr0_0);
3069     }
3070     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3071         // Rule at src/isa/aarch64/inst.isle line 1898.
3072         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3073         let expr1_0: bool = false;
3074         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3075         let expr3_0: u8 = 64;
3076         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3077         return Some(expr4_0);
3078     }
3079     return None;
3080 }
3081 
3082 // Generated as internal constructor for term trap_if_zero_divisor.
3083 pub fn constructor_trap_if_zero_divisor<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3084     let pattern0_0 = arg0;
3085     // Rule at src/isa/aarch64/inst.isle line 1907.
3086     let expr0_0 = C::cond_br_zero(ctx, pattern0_0);
3087     let expr1_0 = C::trap_code_division_by_zero(ctx);
3088     let expr2_0 = MInst::TrapIf {
3089         kind: expr0_0,
3090         trap_code: expr1_0,
3091     };
3092     let expr3_0 = C::emit(ctx, &expr2_0);
3093     return Some(pattern0_0);
3094 }
3095 
3096 // Generated as internal constructor for term size_from_ty.
3097 pub fn constructor_size_from_ty<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
3098     let pattern0_0 = arg0;
3099     if pattern0_0 == I64 {
3100         // Rule at src/isa/aarch64/inst.isle line 1913.
3101         let expr0_0 = OperandSize::Size64;
3102         return Some(expr0_0);
3103     }
3104     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
3105         // Rule at src/isa/aarch64/inst.isle line 1912.
3106         let expr0_0 = OperandSize::Size32;
3107         return Some(expr0_0);
3108     }
3109     return None;
3110 }
3111 
3112 // Generated as internal constructor for term trap_if_div_overflow.
3113 pub fn constructor_trap_if_div_overflow<C: Context>(
3114     ctx: &mut C,
3115     arg0: Type,
3116     arg1: Reg,
3117     arg2: Reg,
3118 ) -> Option<Reg> {
3119     let pattern0_0 = arg0;
3120     let pattern1_0 = arg1;
3121     let pattern2_0 = arg2;
3122     // Rule at src/isa/aarch64/inst.isle line 1919.
3123     let expr0_0 = ALUOp::AddS;
3124     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
3125     let expr2_0 = C::writable_zero_reg(ctx);
3126     let expr3_0: u8 = 1;
3127     let expr4_0 = C::u8_into_imm12(ctx, expr3_0);
3128     let expr5_0 = MInst::AluRRImm12 {
3129         alu_op: expr0_0,
3130         size: expr1_0,
3131         rd: expr2_0,
3132         rn: pattern2_0,
3133         imm12: expr4_0,
3134     };
3135     let expr6_0 = C::emit(ctx, &expr5_0);
3136     let expr7_0 = constructor_size_from_ty(ctx, pattern0_0)?;
3137     let expr8_0: u8 = 1;
3138     let expr9_0 = C::u8_into_uimm5(ctx, expr8_0);
3139     let expr10_0: bool = false;
3140     let expr11_0: bool = false;
3141     let expr12_0: bool = false;
3142     let expr13_0: bool = false;
3143     let expr14_0 = C::nzcv(ctx, expr10_0, expr11_0, expr12_0, expr13_0);
3144     let expr15_0 = Cond::Eq;
3145     let expr16_0 = MInst::CCmpImm {
3146         size: expr7_0,
3147         rn: pattern1_0,
3148         imm: expr9_0,
3149         nzcv: expr14_0,
3150         cond: expr15_0,
3151     };
3152     let expr17_0 = C::emit(ctx, &expr16_0);
3153     let expr18_0 = Cond::Vs;
3154     let expr19_0 = C::cond_br_cond(ctx, &expr18_0);
3155     let expr20_0 = C::trap_code_integer_overflow(ctx);
3156     let expr21_0 = MInst::TrapIf {
3157         kind: expr19_0,
3158         trap_code: expr20_0,
3159     };
3160     let expr22_0 = C::emit(ctx, &expr21_0);
3161     return Some(pattern1_0);
3162 }
3163 
3164 // Generated as internal constructor for term alu_rs_imm_logic_commutative.
3165 pub fn constructor_alu_rs_imm_logic_commutative<C: Context>(
3166     ctx: &mut C,
3167     arg0: &ALUOp,
3168     arg1: Type,
3169     arg2: Value,
3170     arg3: Value,
3171 ) -> Option<Reg> {
3172     let pattern0_0 = arg0;
3173     let pattern1_0 = arg1;
3174     let pattern2_0 = arg2;
3175     if let Some(pattern3_0) = C::def_inst(ctx, pattern2_0) {
3176         let pattern4_0 = C::inst_data(ctx, pattern3_0);
3177         match &pattern4_0 {
3178             &InstructionData::UnaryImm {
3179                 opcode: ref pattern5_0,
3180                 imm: pattern5_1,
3181             } => {
3182                 if let &Opcode::Iconst = pattern5_0 {
3183                     let closure7 = || {
3184                         return Some(pattern1_0);
3185                     };
3186                     if let Some(pattern7_0) = closure7() {
3187                         if let Some(pattern8_0) =
3188                             C::imm_logic_from_imm64(ctx, pattern5_1, pattern7_0)
3189                         {
3190                             let pattern9_0 = arg3;
3191                             // Rule at src/isa/aarch64/inst.isle line 1964.
3192                             let expr0_0 = C::put_in_reg(ctx, pattern9_0);
3193                             let expr1_0 = constructor_alu_rr_imm_logic(
3194                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0,
3195                             )?;
3196                             return Some(expr1_0);
3197                         }
3198                     }
3199                 }
3200             }
3201             &InstructionData::Binary {
3202                 opcode: ref pattern5_0,
3203                 args: ref pattern5_1,
3204             } => {
3205                 if let &Opcode::Ishl = pattern5_0 {
3206                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3207                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3208                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
3209                         if let &InstructionData::UnaryImm {
3210                             opcode: ref pattern10_0,
3211                             imm: pattern10_1,
3212                         } = &pattern9_0
3213                         {
3214                             if let &Opcode::Iconst = pattern10_0 {
3215                                 let closure12 = || {
3216                                     return Some(pattern1_0);
3217                                 };
3218                                 if let Some(pattern12_0) = closure12() {
3219                                     if let Some(pattern13_0) =
3220                                         C::lshl_from_imm64(ctx, pattern10_1, pattern12_0)
3221                                     {
3222                                         let pattern14_0 = arg3;
3223                                         // Rule at src/isa/aarch64/inst.isle line 1970.
3224                                         let expr0_0 = C::put_in_reg(ctx, pattern14_0);
3225                                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3226                                         let expr2_0 = constructor_alu_rrr_shift(
3227                                             ctx,
3228                                             pattern0_0,
3229                                             pattern1_0,
3230                                             expr0_0,
3231                                             expr1_0,
3232                                             pattern13_0,
3233                                         )?;
3234                                         return Some(expr2_0);
3235                                     }
3236                                 }
3237                             }
3238                         }
3239                     }
3240                 }
3241             }
3242             _ => {}
3243         }
3244     }
3245     let pattern3_0 = arg3;
3246     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3247         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3248         match &pattern5_0 {
3249             &InstructionData::UnaryImm {
3250                 opcode: ref pattern6_0,
3251                 imm: pattern6_1,
3252             } => {
3253                 if let &Opcode::Iconst = pattern6_0 {
3254                     let closure8 = || {
3255                         return Some(pattern1_0);
3256                     };
3257                     if let Some(pattern8_0) = closure8() {
3258                         if let Some(pattern9_0) =
3259                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3260                         {
3261                             // Rule at src/isa/aarch64/inst.isle line 1962.
3262                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3263                             let expr1_0 = constructor_alu_rr_imm_logic(
3264                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3265                             )?;
3266                             return Some(expr1_0);
3267                         }
3268                     }
3269                 }
3270             }
3271             &InstructionData::Binary {
3272                 opcode: ref pattern6_0,
3273                 args: ref pattern6_1,
3274             } => {
3275                 if let &Opcode::Ishl = pattern6_0 {
3276                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3277                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3278                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3279                         if let &InstructionData::UnaryImm {
3280                             opcode: ref pattern11_0,
3281                             imm: pattern11_1,
3282                         } = &pattern10_0
3283                         {
3284                             if let &Opcode::Iconst = pattern11_0 {
3285                                 let closure13 = || {
3286                                     return Some(pattern1_0);
3287                                 };
3288                                 if let Some(pattern13_0) = closure13() {
3289                                     if let Some(pattern14_0) =
3290                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3291                                     {
3292                                         // Rule at src/isa/aarch64/inst.isle line 1968.
3293                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3294                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3295                                         let expr2_0 = constructor_alu_rrr_shift(
3296                                             ctx,
3297                                             pattern0_0,
3298                                             pattern1_0,
3299                                             expr0_0,
3300                                             expr1_0,
3301                                             pattern14_0,
3302                                         )?;
3303                                         return Some(expr2_0);
3304                                     }
3305                                 }
3306                             }
3307                         }
3308                     }
3309                 }
3310             }
3311             _ => {}
3312         }
3313     }
3314     // Rule at src/isa/aarch64/inst.isle line 1958.
3315     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3316     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3317     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3318     return Some(expr2_0);
3319 }
3320 
3321 // Generated as internal constructor for term alu_rs_imm_logic.
3322 pub fn constructor_alu_rs_imm_logic<C: Context>(
3323     ctx: &mut C,
3324     arg0: &ALUOp,
3325     arg1: Type,
3326     arg2: Value,
3327     arg3: Value,
3328 ) -> Option<Reg> {
3329     let pattern0_0 = arg0;
3330     let pattern1_0 = arg1;
3331     let pattern2_0 = arg2;
3332     let pattern3_0 = arg3;
3333     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3334         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3335         match &pattern5_0 {
3336             &InstructionData::UnaryImm {
3337                 opcode: ref pattern6_0,
3338                 imm: pattern6_1,
3339             } => {
3340                 if let &Opcode::Iconst = pattern6_0 {
3341                     let closure8 = || {
3342                         return Some(pattern1_0);
3343                     };
3344                     if let Some(pattern8_0) = closure8() {
3345                         if let Some(pattern9_0) =
3346                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3347                         {
3348                             // Rule at src/isa/aarch64/inst.isle line 1978.
3349                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3350                             let expr1_0 = constructor_alu_rr_imm_logic(
3351                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3352                             )?;
3353                             return Some(expr1_0);
3354                         }
3355                     }
3356                 }
3357             }
3358             &InstructionData::Binary {
3359                 opcode: ref pattern6_0,
3360                 args: ref pattern6_1,
3361             } => {
3362                 if let &Opcode::Ishl = pattern6_0 {
3363                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3364                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3365                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3366                         if let &InstructionData::UnaryImm {
3367                             opcode: ref pattern11_0,
3368                             imm: pattern11_1,
3369                         } = &pattern10_0
3370                         {
3371                             if let &Opcode::Iconst = pattern11_0 {
3372                                 let closure13 = || {
3373                                     return Some(pattern1_0);
3374                                 };
3375                                 if let Some(pattern13_0) = closure13() {
3376                                     if let Some(pattern14_0) =
3377                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3378                                     {
3379                                         // Rule at src/isa/aarch64/inst.isle line 1980.
3380                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3381                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3382                                         let expr2_0 = constructor_alu_rrr_shift(
3383                                             ctx,
3384                                             pattern0_0,
3385                                             pattern1_0,
3386                                             expr0_0,
3387                                             expr1_0,
3388                                             pattern14_0,
3389                                         )?;
3390                                         return Some(expr2_0);
3391                                     }
3392                                 }
3393                             }
3394                         }
3395                     }
3396                 }
3397             }
3398             _ => {}
3399         }
3400     }
3401     // Rule at src/isa/aarch64/inst.isle line 1976.
3402     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3403     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3404     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3405     return Some(expr2_0);
3406 }
3407 
3408 // Generated as internal constructor for term i128_alu_bitop.
3409 pub fn constructor_i128_alu_bitop<C: Context>(
3410     ctx: &mut C,
3411     arg0: &ALUOp,
3412     arg1: Type,
3413     arg2: Value,
3414     arg3: Value,
3415 ) -> Option<ValueRegs> {
3416     let pattern0_0 = arg0;
3417     let pattern1_0 = arg1;
3418     let pattern2_0 = arg2;
3419     let pattern3_0 = arg3;
3420     // Rule at src/isa/aarch64/inst.isle line 1988.
3421     let expr0_0 = C::put_in_regs(ctx, pattern2_0);
3422     let expr1_0: usize = 0;
3423     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3424     let expr3_0: usize = 1;
3425     let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
3426     let expr5_0 = C::put_in_regs(ctx, pattern3_0);
3427     let expr6_0: usize = 0;
3428     let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
3429     let expr8_0: usize = 1;
3430     let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
3431     let expr10_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr2_0, expr7_0)?;
3432     let expr11_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr4_0, expr9_0)?;
3433     let expr12_0 = C::value_regs(ctx, expr10_0, expr11_0);
3434     return Some(expr12_0);
3435 }
3436 
3437 // Generated as internal constructor for term lower.
3438 pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> {
3439     let pattern0_0 = arg0;
3440     if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
3441         let pattern2_0 = C::value_type(ctx, pattern1_0);
3442         if pattern2_0 == I8 {
3443             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3444             if let &InstructionData::Unary {
3445                 opcode: ref pattern5_0,
3446                 arg: pattern5_1,
3447             } = &pattern4_0
3448             {
3449                 match pattern5_0 {
3450                     &Opcode::Bitrev => {
3451                         // Rule at src/isa/aarch64/lower.isle line 974.
3452                         let expr0_0: Type = I32;
3453                         let expr1_0: Type = I32;
3454                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3455                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3456                         let expr4_0: u8 = 24;
3457                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3458                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3459                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3460                         return Some(expr7_0);
3461                     }
3462                     &Opcode::Clz => {
3463                         // Rule at src/isa/aarch64/lower.isle line 995.
3464                         let expr0_0: Type = I32;
3465                         let expr1_0: Type = I32;
3466                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3467                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3468                         let expr4_0: u8 = 24;
3469                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3470                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3471                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3472                         return Some(expr7_0);
3473                     }
3474                     &Opcode::Cls => {
3475                         // Rule at src/isa/aarch64/lower.isle line 1042.
3476                         let expr0_0: Type = I32;
3477                         let expr1_0: Type = I32;
3478                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3479                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3480                         let expr4_0: u8 = 24;
3481                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3482                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3483                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3484                         return Some(expr7_0);
3485                     }
3486                     &Opcode::Ctz => {
3487                         // Rule at src/isa/aarch64/lower.isle line 1025.
3488                         let expr0_0: Type = I32;
3489                         let expr1_0: Type = I32;
3490                         let expr2_0: Type = I32;
3491                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3492                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3493                         let expr5_0: Type = I32;
3494                         let expr6_0: u64 = 8388608;
3495                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3496                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3497                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3498                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3499                         return Some(expr10_0);
3500                     }
3501                     &Opcode::Popcnt => {
3502                         // Rule at src/isa/aarch64/lower.isle line 1093.
3503                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3504                         let expr1_0 = ScalarSize::Size32;
3505                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3506                         let expr3_0 = VectorSize::Size8x8;
3507                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3508                         let expr5_0: u8 = 0;
3509                         let expr6_0 = VectorSize::Size8x16;
3510                         let expr7_0 = constructor_mov_from_vec(ctx, expr4_0, expr5_0, &expr6_0)?;
3511                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
3512                         return Some(expr8_0);
3513                     }
3514                     _ => {}
3515                 }
3516             }
3517         }
3518         if pattern2_0 == I16 {
3519             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3520             if let &InstructionData::Unary {
3521                 opcode: ref pattern5_0,
3522                 arg: pattern5_1,
3523             } = &pattern4_0
3524             {
3525                 match pattern5_0 {
3526                     &Opcode::Bitrev => {
3527                         // Rule at src/isa/aarch64/lower.isle line 980.
3528                         let expr0_0: Type = I32;
3529                         let expr1_0: Type = I32;
3530                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3531                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3532                         let expr4_0: u8 = 16;
3533                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3534                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3535                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3536                         return Some(expr7_0);
3537                     }
3538                     &Opcode::Clz => {
3539                         // Rule at src/isa/aarch64/lower.isle line 998.
3540                         let expr0_0: Type = I32;
3541                         let expr1_0: Type = I32;
3542                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3543                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3544                         let expr4_0: u8 = 16;
3545                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3546                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3547                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3548                         return Some(expr7_0);
3549                     }
3550                     &Opcode::Cls => {
3551                         // Rule at src/isa/aarch64/lower.isle line 1045.
3552                         let expr0_0: Type = I32;
3553                         let expr1_0: Type = I32;
3554                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3555                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3556                         let expr4_0: u8 = 16;
3557                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3558                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3559                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3560                         return Some(expr7_0);
3561                     }
3562                     &Opcode::Ctz => {
3563                         // Rule at src/isa/aarch64/lower.isle line 1028.
3564                         let expr0_0: Type = I32;
3565                         let expr1_0: Type = I32;
3566                         let expr2_0: Type = I32;
3567                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3568                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3569                         let expr5_0: Type = I32;
3570                         let expr6_0: u64 = 32768;
3571                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3572                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3573                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3574                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3575                         return Some(expr10_0);
3576                     }
3577                     &Opcode::Popcnt => {
3578                         // Rule at src/isa/aarch64/lower.isle line 1099.
3579                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3580                         let expr1_0 = ScalarSize::Size32;
3581                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3582                         let expr3_0 = VectorSize::Size8x8;
3583                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3584                         let expr5_0 = VectorSize::Size8x8;
3585                         let expr6_0 = constructor_addp(ctx, expr4_0, expr4_0, &expr5_0)?;
3586                         let expr7_0: u8 = 0;
3587                         let expr8_0 = VectorSize::Size8x16;
3588                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3589                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3590                         return Some(expr10_0);
3591                     }
3592                     _ => {}
3593                 }
3594             }
3595         }
3596         if pattern2_0 == I32 {
3597             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3598             match &pattern4_0 {
3599                 &InstructionData::Binary {
3600                     opcode: ref pattern5_0,
3601                     args: ref pattern5_1,
3602                 } => {
3603                     match pattern5_0 {
3604                         &Opcode::Rotl => {
3605                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3606                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3607                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3608                                 if let &InstructionData::UnaryImm {
3609                                     opcode: ref pattern10_0,
3610                                     imm: pattern10_1,
3611                                 } = &pattern9_0
3612                                 {
3613                                     if let &Opcode::Iconst = pattern10_0 {
3614                                         let closure12 = || {
3615                                             let expr0_0: Type = I32;
3616                                             return Some(expr0_0);
3617                                         };
3618                                         if let Some(pattern12_0) = closure12() {
3619                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3620                                                 ctx,
3621                                                 pattern10_1,
3622                                                 pattern12_0,
3623                                             ) {
3624                                                 // Rule at src/isa/aarch64/lower.isle line 865.
3625                                                 let expr0_0: Type = I32;
3626                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3627                                                 let expr2_0: Type = I32;
3628                                                 let expr3_0 =
3629                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3630                                                 let expr4_0 = constructor_a64_rotr_imm(
3631                                                     ctx, expr0_0, expr1_0, expr3_0,
3632                                                 )?;
3633                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3634                                                 return Some(expr5_0);
3635                                             }
3636                                         }
3637                                     }
3638                                 }
3639                             }
3640                             // Rule at src/isa/aarch64/lower.isle line 855.
3641                             let expr0_0: Type = I32;
3642                             let expr1_0 = C::zero_reg(ctx);
3643                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3644                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3645                             let expr4_0: Type = I32;
3646                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3647                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3648                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3649                             return Some(expr7_0);
3650                         }
3651                         &Opcode::Rotr => {
3652                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3653                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3654                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3655                                 if let &InstructionData::UnaryImm {
3656                                     opcode: ref pattern10_0,
3657                                     imm: pattern10_1,
3658                                 } = &pattern9_0
3659                                 {
3660                                     if let &Opcode::Iconst = pattern10_0 {
3661                                         let closure12 = || {
3662                                             let expr0_0: Type = I32;
3663                                             return Some(expr0_0);
3664                                         };
3665                                         if let Some(pattern12_0) = closure12() {
3666                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3667                                                 ctx,
3668                                                 pattern10_1,
3669                                                 pattern12_0,
3670                                             ) {
3671                                                 // Rule at src/isa/aarch64/lower.isle line 907.
3672                                                 let expr0_0: Type = I32;
3673                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3674                                                 let expr2_0 = constructor_a64_rotr_imm(
3675                                                     ctx,
3676                                                     expr0_0,
3677                                                     expr1_0,
3678                                                     pattern13_0,
3679                                                 )?;
3680                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3681                                                 return Some(expr3_0);
3682                                             }
3683                                         }
3684                                     }
3685                                 }
3686                             }
3687                             // Rule at src/isa/aarch64/lower.isle line 895.
3688                             let expr0_0: Type = I32;
3689                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3690                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3691                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
3692                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3693                             return Some(expr4_0);
3694                         }
3695                         _ => {}
3696                     }
3697                 }
3698                 &InstructionData::Unary {
3699                     opcode: ref pattern5_0,
3700                     arg: pattern5_1,
3701                 } => {
3702                     if let &Opcode::Popcnt = pattern5_0 {
3703                         // Rule at src/isa/aarch64/lower.isle line 1105.
3704                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3705                         let expr1_0 = ScalarSize::Size32;
3706                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3707                         let expr3_0 = VectorSize::Size8x8;
3708                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3709                         let expr5_0 = VectorSize::Size8x8;
3710                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
3711                         let expr7_0: u8 = 0;
3712                         let expr8_0 = VectorSize::Size8x16;
3713                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3714                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3715                         return Some(expr10_0);
3716                     }
3717                 }
3718                 _ => {}
3719             }
3720         }
3721         if pattern2_0 == I64 {
3722             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3723             match &pattern4_0 {
3724                 &InstructionData::Binary {
3725                     opcode: ref pattern5_0,
3726                     args: ref pattern5_1,
3727                 } => {
3728                     match pattern5_0 {
3729                         &Opcode::Umulhi => {
3730                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3731                             // Rule at src/isa/aarch64/lower.isle line 367.
3732                             let expr0_0: Type = I64;
3733                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3734                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3735                             let expr3_0 = constructor_umulh(ctx, expr0_0, expr1_0, expr2_0)?;
3736                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3737                             return Some(expr4_0);
3738                         }
3739                         &Opcode::Smulhi => {
3740                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3741                             // Rule at src/isa/aarch64/lower.isle line 355.
3742                             let expr0_0: Type = I64;
3743                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3744                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3745                             let expr3_0 = constructor_smulh(ctx, expr0_0, expr1_0, expr2_0)?;
3746                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3747                             return Some(expr4_0);
3748                         }
3749                         &Opcode::Band => {
3750                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3751                             // Rule at src/isa/aarch64/lower.isle line 586.
3752                             let expr0_0 = ALUOp::And;
3753                             let expr1_0: Type = I64;
3754                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3755                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3756                             )?;
3757                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3758                             return Some(expr3_0);
3759                         }
3760                         &Opcode::Bor => {
3761                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3762                             // Rule at src/isa/aarch64/lower.isle line 599.
3763                             let expr0_0 = ALUOp::Orr;
3764                             let expr1_0: Type = I64;
3765                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3766                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3767                             )?;
3768                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3769                             return Some(expr3_0);
3770                         }
3771                         &Opcode::Bxor => {
3772                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3773                             // Rule at src/isa/aarch64/lower.isle line 612.
3774                             let expr0_0 = ALUOp::Eor;
3775                             let expr1_0: Type = I64;
3776                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3777                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3778                             )?;
3779                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3780                             return Some(expr3_0);
3781                         }
3782                         &Opcode::BandNot => {
3783                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3784                             // Rule at src/isa/aarch64/lower.isle line 625.
3785                             let expr0_0 = ALUOp::AndNot;
3786                             let expr1_0: Type = I64;
3787                             let expr2_0 = constructor_alu_rs_imm_logic(
3788                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3789                             )?;
3790                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3791                             return Some(expr3_0);
3792                         }
3793                         &Opcode::BorNot => {
3794                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3795                             // Rule at src/isa/aarch64/lower.isle line 638.
3796                             let expr0_0 = ALUOp::OrrNot;
3797                             let expr1_0: Type = I64;
3798                             let expr2_0 = constructor_alu_rs_imm_logic(
3799                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3800                             )?;
3801                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3802                             return Some(expr3_0);
3803                         }
3804                         &Opcode::BxorNot => {
3805                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3806                             // Rule at src/isa/aarch64/lower.isle line 648.
3807                             let expr0_0 = ALUOp::EorNot;
3808                             let expr1_0: Type = I64;
3809                             let expr2_0 = constructor_alu_rs_imm_logic(
3810                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3811                             )?;
3812                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3813                             return Some(expr3_0);
3814                         }
3815                         &Opcode::Rotl => {
3816                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3817                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3818                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3819                                 if let &InstructionData::UnaryImm {
3820                                     opcode: ref pattern10_0,
3821                                     imm: pattern10_1,
3822                                 } = &pattern9_0
3823                                 {
3824                                     if let &Opcode::Iconst = pattern10_0 {
3825                                         let closure12 = || {
3826                                             let expr0_0: Type = I64;
3827                                             return Some(expr0_0);
3828                                         };
3829                                         if let Some(pattern12_0) = closure12() {
3830                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3831                                                 ctx,
3832                                                 pattern10_1,
3833                                                 pattern12_0,
3834                                             ) {
3835                                                 // Rule at src/isa/aarch64/lower.isle line 869.
3836                                                 let expr0_0: Type = I64;
3837                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3838                                                 let expr2_0: Type = I64;
3839                                                 let expr3_0 =
3840                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3841                                                 let expr4_0 = constructor_a64_rotr_imm(
3842                                                     ctx, expr0_0, expr1_0, expr3_0,
3843                                                 )?;
3844                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3845                                                 return Some(expr5_0);
3846                                             }
3847                                         }
3848                                     }
3849                                 }
3850                             }
3851                             // Rule at src/isa/aarch64/lower.isle line 860.
3852                             let expr0_0: Type = I64;
3853                             let expr1_0 = C::zero_reg(ctx);
3854                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3855                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3856                             let expr4_0: Type = I64;
3857                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3858                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3859                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3860                             return Some(expr7_0);
3861                         }
3862                         &Opcode::Rotr => {
3863                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3864                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3865                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3866                                 if let &InstructionData::UnaryImm {
3867                                     opcode: ref pattern10_0,
3868                                     imm: pattern10_1,
3869                                 } = &pattern9_0
3870                                 {
3871                                     if let &Opcode::Iconst = pattern10_0 {
3872                                         let closure12 = || {
3873                                             let expr0_0: Type = I64;
3874                                             return Some(expr0_0);
3875                                         };
3876                                         if let Some(pattern12_0) = closure12() {
3877                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3878                                                 ctx,
3879                                                 pattern10_1,
3880                                                 pattern12_0,
3881                                             ) {
3882                                                 // Rule at src/isa/aarch64/lower.isle line 911.
3883                                                 let expr0_0: Type = I64;
3884                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3885                                                 let expr2_0 = constructor_a64_rotr_imm(
3886                                                     ctx,
3887                                                     expr0_0,
3888                                                     expr1_0,
3889                                                     pattern13_0,
3890                                                 )?;
3891                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3892                                                 return Some(expr3_0);
3893                                             }
3894                                         }
3895                                     }
3896                                 }
3897                             }
3898                             // Rule at src/isa/aarch64/lower.isle line 899.
3899                             let expr0_0: Type = I64;
3900                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3901                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3902                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
3903                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3904                             return Some(expr4_0);
3905                         }
3906                         &Opcode::Ishl => {
3907                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3908                             // Rule at src/isa/aarch64/lower.isle line 660.
3909                             let expr0_0 = ALUOp::Lsl;
3910                             let expr1_0: Type = I64;
3911                             let expr2_0 = C::put_in_reg(ctx, pattern7_0);
3912                             let expr3_0 =
3913                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
3914                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3915                             return Some(expr4_0);
3916                         }
3917                         &Opcode::Ushr => {
3918                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3919                             // Rule at src/isa/aarch64/lower.isle line 744.
3920                             let expr0_0 = ALUOp::Lsr;
3921                             let expr1_0: Type = I64;
3922                             let expr2_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
3923                             let expr3_0 =
3924                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
3925                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3926                             return Some(expr4_0);
3927                         }
3928                         &Opcode::Sshr => {
3929                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3930                             // Rule at src/isa/aarch64/lower.isle line 791.
3931                             let expr0_0 = ALUOp::Asr;
3932                             let expr1_0: Type = I64;
3933                             let expr2_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
3934                             let expr3_0 =
3935                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
3936                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3937                             return Some(expr4_0);
3938                         }
3939                         _ => {}
3940                     }
3941                 }
3942                 &InstructionData::Unary {
3943                     opcode: ref pattern5_0,
3944                     arg: pattern5_1,
3945                 } => {
3946                     if let &Opcode::Popcnt = pattern5_0 {
3947                         // Rule at src/isa/aarch64/lower.isle line 1111.
3948                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3949                         let expr1_0 = ScalarSize::Size64;
3950                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3951                         let expr3_0 = VectorSize::Size8x8;
3952                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3953                         let expr5_0 = VectorSize::Size8x8;
3954                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
3955                         let expr7_0: u8 = 0;
3956                         let expr8_0 = VectorSize::Size8x16;
3957                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3958                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3959                         return Some(expr10_0);
3960                     }
3961                 }
3962                 _ => {}
3963             }
3964         }
3965         if pattern2_0 == I128 {
3966             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3967             match &pattern4_0 {
3968                 &InstructionData::Binary {
3969                     opcode: ref pattern5_0,
3970                     args: ref pattern5_1,
3971                 } => {
3972                     match pattern5_0 {
3973                         &Opcode::Iadd => {
3974                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3975                             // Rule at src/isa/aarch64/lower.isle line 79.
3976                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
3977                             let expr1_0: usize = 0;
3978                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3979                             let expr3_0: usize = 1;
3980                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
3981                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
3982                             let expr6_0: usize = 0;
3983                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
3984                             let expr8_0: usize = 1;
3985                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
3986                             let expr10_0: Type = I64;
3987                             let expr11_0 =
3988                                 constructor_add_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
3989                             let expr12_0: Type = I64;
3990                             let expr13_0 = constructor_adc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
3991                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
3992                             let expr15_0 = C::output(ctx, expr14_0);
3993                             return Some(expr15_0);
3994                         }
3995                         &Opcode::Isub => {
3996                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3997                             // Rule at src/isa/aarch64/lower.isle line 129.
3998                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
3999                             let expr1_0: usize = 0;
4000                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4001                             let expr3_0: usize = 1;
4002                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4003                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4004                             let expr6_0: usize = 0;
4005                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4006                             let expr8_0: usize = 1;
4007                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4008                             let expr10_0: Type = I64;
4009                             let expr11_0 =
4010                                 constructor_sub_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4011                             let expr12_0: Type = I64;
4012                             let expr13_0 = constructor_sbc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4013                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4014                             let expr15_0 = C::output(ctx, expr14_0);
4015                             return Some(expr15_0);
4016                         }
4017                         &Opcode::Imul => {
4018                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4019                             // Rule at src/isa/aarch64/lower.isle line 183.
4020                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4021                             let expr1_0: usize = 0;
4022                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4023                             let expr3_0: usize = 1;
4024                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4025                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4026                             let expr6_0: usize = 0;
4027                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4028                             let expr8_0: usize = 1;
4029                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4030                             let expr10_0: Type = I64;
4031                             let expr11_0 = constructor_umulh(ctx, expr10_0, expr2_0, expr7_0)?;
4032                             let expr12_0 = constructor_madd64(ctx, expr2_0, expr9_0, expr11_0)?;
4033                             let expr13_0 = constructor_madd64(ctx, expr4_0, expr7_0, expr12_0)?;
4034                             let expr14_0 = C::zero_reg(ctx);
4035                             let expr15_0 = constructor_madd64(ctx, expr2_0, expr7_0, expr14_0)?;
4036                             let expr16_0 = C::value_regs(ctx, expr15_0, expr13_0);
4037                             let expr17_0 = C::output(ctx, expr16_0);
4038                             return Some(expr17_0);
4039                         }
4040                         &Opcode::Band => {
4041                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4042                             // Rule at src/isa/aarch64/lower.isle line 589.
4043                             let expr0_0 = ALUOp::And;
4044                             let expr1_0: Type = I64;
4045                             let expr2_0 = constructor_i128_alu_bitop(
4046                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4047                             )?;
4048                             let expr3_0 = C::output(ctx, expr2_0);
4049                             return Some(expr3_0);
4050                         }
4051                         &Opcode::Bor => {
4052                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4053                             // Rule at src/isa/aarch64/lower.isle line 602.
4054                             let expr0_0 = ALUOp::Orr;
4055                             let expr1_0: Type = I64;
4056                             let expr2_0 = constructor_i128_alu_bitop(
4057                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4058                             )?;
4059                             let expr3_0 = C::output(ctx, expr2_0);
4060                             return Some(expr3_0);
4061                         }
4062                         &Opcode::Bxor => {
4063                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4064                             // Rule at src/isa/aarch64/lower.isle line 615.
4065                             let expr0_0 = ALUOp::Eor;
4066                             let expr1_0: Type = I64;
4067                             let expr2_0 = constructor_i128_alu_bitop(
4068                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4069                             )?;
4070                             let expr3_0 = C::output(ctx, expr2_0);
4071                             return Some(expr3_0);
4072                         }
4073                         &Opcode::BandNot => {
4074                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4075                             // Rule at src/isa/aarch64/lower.isle line 628.
4076                             let expr0_0 = ALUOp::AndNot;
4077                             let expr1_0: Type = I64;
4078                             let expr2_0 = constructor_i128_alu_bitop(
4079                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4080                             )?;
4081                             let expr3_0 = C::output(ctx, expr2_0);
4082                             return Some(expr3_0);
4083                         }
4084                         &Opcode::BorNot => {
4085                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4086                             // Rule at src/isa/aarch64/lower.isle line 641.
4087                             let expr0_0 = ALUOp::OrrNot;
4088                             let expr1_0: Type = I64;
4089                             let expr2_0 = constructor_i128_alu_bitop(
4090                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4091                             )?;
4092                             let expr3_0 = C::output(ctx, expr2_0);
4093                             return Some(expr3_0);
4094                         }
4095                         &Opcode::BxorNot => {
4096                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4097                             // Rule at src/isa/aarch64/lower.isle line 651.
4098                             let expr0_0 = ALUOp::EorNot;
4099                             let expr1_0: Type = I64;
4100                             let expr2_0 = constructor_i128_alu_bitop(
4101                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4102                             )?;
4103                             let expr3_0 = C::output(ctx, expr2_0);
4104                             return Some(expr3_0);
4105                         }
4106                         &Opcode::Rotl => {
4107                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4108                             // Rule at src/isa/aarch64/lower.isle line 878.
4109                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4110                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4111                             let expr2_0: usize = 0;
4112                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4113                             let expr4_0: Type = I64;
4114                             let expr5_0: Type = I64;
4115                             let expr6_0: u64 = 128;
4116                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4117                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4118                             let expr9_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4119                             let expr10_0 = constructor_lower_ushr128(ctx, expr0_0, expr8_0)?;
4120                             let expr11_0: Type = I64;
4121                             let expr12_0: usize = 0;
4122                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4123                             let expr14_0: usize = 0;
4124                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4125                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4126                             let expr17_0: Type = I64;
4127                             let expr18_0: usize = 1;
4128                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4129                             let expr20_0: usize = 1;
4130                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4131                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4132                             let expr23_0 = C::value_regs(ctx, expr16_0, expr22_0);
4133                             let expr24_0 = C::output(ctx, expr23_0);
4134                             return Some(expr24_0);
4135                         }
4136                         &Opcode::Rotr => {
4137                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4138                             // Rule at src/isa/aarch64/lower.isle line 959.
4139                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4140                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4141                             let expr2_0: usize = 0;
4142                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4143                             let expr4_0: Type = I64;
4144                             let expr5_0: Type = I64;
4145                             let expr6_0: u64 = 128;
4146                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4147                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4148                             let expr9_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4149                             let expr10_0 = constructor_lower_shl128(ctx, expr0_0, expr8_0)?;
4150                             let expr11_0: Type = I64;
4151                             let expr12_0: usize = 1;
4152                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4153                             let expr14_0: usize = 1;
4154                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4155                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4156                             let expr17_0: Type = I64;
4157                             let expr18_0: usize = 0;
4158                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4159                             let expr20_0: usize = 0;
4160                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4161                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4162                             let expr23_0 = C::value_regs(ctx, expr22_0, expr16_0);
4163                             let expr24_0 = C::output(ctx, expr23_0);
4164                             return Some(expr24_0);
4165                         }
4166                         &Opcode::Ishl => {
4167                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4168                             // Rule at src/isa/aarch64/lower.isle line 664.
4169                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4170                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4171                             let expr2_0: usize = 0;
4172                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4173                             let expr4_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4174                             let expr5_0 = C::output(ctx, expr4_0);
4175                             return Some(expr5_0);
4176                         }
4177                         &Opcode::Ushr => {
4178                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4179                             // Rule at src/isa/aarch64/lower.isle line 748.
4180                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4181                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4182                             let expr2_0: usize = 0;
4183                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4184                             let expr4_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4185                             let expr5_0 = C::output(ctx, expr4_0);
4186                             return Some(expr5_0);
4187                         }
4188                         &Opcode::Sshr => {
4189                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4190                             // Rule at src/isa/aarch64/lower.isle line 795.
4191                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4192                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4193                             let expr2_0: usize = 0;
4194                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4195                             let expr4_0 = constructor_lower_sshr128(ctx, expr0_0, expr3_0)?;
4196                             let expr5_0 = C::output(ctx, expr4_0);
4197                             return Some(expr5_0);
4198                         }
4199                         _ => {}
4200                     }
4201                 }
4202                 &InstructionData::Unary {
4203                     opcode: ref pattern5_0,
4204                     arg: pattern5_1,
4205                 } => {
4206                     match pattern5_0 {
4207                         &Opcode::Bnot => {
4208                             // Rule at src/isa/aarch64/lower.isle line 569.
4209                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4210                             let expr1_0: usize = 0;
4211                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4212                             let expr3_0: usize = 1;
4213                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4214                             let expr5_0: Type = I64;
4215                             let expr6_0 = C::zero_reg(ctx);
4216                             let expr7_0 = constructor_orr_not(ctx, expr5_0, expr6_0, expr2_0)?;
4217                             let expr8_0: Type = I64;
4218                             let expr9_0 = C::zero_reg(ctx);
4219                             let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, expr4_0)?;
4220                             let expr11_0 = C::value_regs(ctx, expr7_0, expr10_0);
4221                             let expr12_0 = C::output(ctx, expr11_0);
4222                             return Some(expr12_0);
4223                         }
4224                         &Opcode::Bitrev => {
4225                             // Rule at src/isa/aarch64/lower.isle line 983.
4226                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4227                             let expr1_0: Type = I64;
4228                             let expr2_0: usize = 0;
4229                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4230                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4231                             let expr5_0: Type = I64;
4232                             let expr6_0: usize = 1;
4233                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4234                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4235                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4236                             let expr10_0 = C::output(ctx, expr9_0);
4237                             return Some(expr10_0);
4238                         }
4239                         &Opcode::Clz => {
4240                             // Rule at src/isa/aarch64/lower.isle line 1001.
4241                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4242                             let expr1_0 = constructor_lower_clz128(ctx, expr0_0)?;
4243                             let expr2_0 = C::output(ctx, expr1_0);
4244                             return Some(expr2_0);
4245                         }
4246                         &Opcode::Cls => {
4247                             // Rule at src/isa/aarch64/lower.isle line 1057.
4248                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4249                             let expr1_0: usize = 0;
4250                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4251                             let expr3_0: usize = 1;
4252                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4253                             let expr5_0: Type = I64;
4254                             let expr6_0 = constructor_a64_cls(ctx, expr5_0, expr2_0)?;
4255                             let expr7_0: Type = I64;
4256                             let expr8_0 = constructor_a64_cls(ctx, expr7_0, expr4_0)?;
4257                             let expr9_0: Type = I64;
4258                             let expr10_0 = constructor_eon(ctx, expr9_0, expr4_0, expr2_0)?;
4259                             let expr11_0: Type = I64;
4260                             let expr12_0: u8 = 63;
4261                             let expr13_0 = C::imm_shift_from_u8(ctx, expr12_0);
4262                             let expr14_0 = constructor_lsr_imm(ctx, expr11_0, expr10_0, expr13_0)?;
4263                             let expr15_0 = constructor_madd64(ctx, expr6_0, expr14_0, expr14_0)?;
4264                             let expr16_0: u8 = 63;
4265                             let expr17_0 = C::u8_into_imm12(ctx, expr16_0);
4266                             let expr18_0 = constructor_cmp64_imm(ctx, expr8_0, expr17_0)?;
4267                             let expr19_0 = Cond::Eq;
4268                             let expr20_0 = C::zero_reg(ctx);
4269                             let expr21_0 = constructor_csel(ctx, &expr19_0, expr15_0, expr20_0)?;
4270                             let expr22_0 = constructor_with_flags_reg(ctx, &expr18_0, &expr21_0)?;
4271                             let expr23_0: Type = I64;
4272                             let expr24_0 = constructor_add(ctx, expr23_0, expr22_0, expr8_0)?;
4273                             let expr25_0: Type = I64;
4274                             let expr26_0: u64 = 0;
4275                             let expr27_0 = constructor_imm(ctx, expr25_0, expr26_0)?;
4276                             let expr28_0 = C::value_regs(ctx, expr24_0, expr27_0);
4277                             let expr29_0 = C::output(ctx, expr28_0);
4278                             return Some(expr29_0);
4279                         }
4280                         &Opcode::Ctz => {
4281                             // Rule at src/isa/aarch64/lower.isle line 1031.
4282                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4283                             let expr1_0: Type = I64;
4284                             let expr2_0: usize = 0;
4285                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4286                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4287                             let expr5_0: Type = I64;
4288                             let expr6_0: usize = 1;
4289                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4290                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4291                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4292                             let expr10_0 = constructor_lower_clz128(ctx, expr9_0)?;
4293                             let expr11_0 = C::output(ctx, expr10_0);
4294                             return Some(expr11_0);
4295                         }
4296                         &Opcode::Popcnt => {
4297                             // Rule at src/isa/aarch64/lower.isle line 1117.
4298                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4299                             let expr1_0: usize = 0;
4300                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4301                             let expr3_0 = ScalarSize::Size64;
4302                             let expr4_0 = constructor_mov_to_fpu(ctx, expr2_0, &expr3_0)?;
4303                             let expr5_0: usize = 1;
4304                             let expr6_0 = C::value_regs_get(ctx, expr0_0, expr5_0);
4305                             let expr7_0: u8 = 1;
4306                             let expr8_0 = VectorSize::Size64x2;
4307                             let expr9_0 =
4308                                 constructor_mov_to_vec(ctx, expr4_0, expr6_0, expr7_0, &expr8_0)?;
4309                             let expr10_0 = VectorSize::Size8x16;
4310                             let expr11_0 = constructor_vec_cnt(ctx, expr9_0, &expr10_0)?;
4311                             let expr12_0 = VectorSize::Size8x16;
4312                             let expr13_0 = constructor_addv(ctx, expr11_0, &expr12_0)?;
4313                             let expr14_0: u8 = 0;
4314                             let expr15_0 = VectorSize::Size8x16;
4315                             let expr16_0 =
4316                                 constructor_mov_from_vec(ctx, expr13_0, expr14_0, &expr15_0)?;
4317                             let expr17_0: Type = I64;
4318                             let expr18_0: u64 = 0;
4319                             let expr19_0 = constructor_imm(ctx, expr17_0, expr18_0)?;
4320                             let expr20_0 = C::value_regs(ctx, expr16_0, expr19_0);
4321                             let expr21_0 = C::output(ctx, expr20_0);
4322                             return Some(expr21_0);
4323                         }
4324                         &Opcode::Uextend => {
4325                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4326                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4327                                 if let &InstructionData::BinaryImm8 {
4328                                     opcode: ref pattern9_0,
4329                                     arg: pattern9_1,
4330                                     imm: pattern9_2,
4331                                 } = &pattern8_0
4332                                 {
4333                                     if let &Opcode::Extractlane = pattern9_0 {
4334                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4335                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
4336                                         // Rule at src/isa/aarch64/lower.isle line 499.
4337                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4338                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
4339                                         let expr2_0 = constructor_mov_from_vec(
4340                                             ctx,
4341                                             expr0_0,
4342                                             pattern12_0,
4343                                             &expr1_0,
4344                                         )?;
4345                                         let expr3_0: Type = I64;
4346                                         let expr4_0: u64 = 0;
4347                                         let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
4348                                         let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
4349                                         let expr7_0 = C::output(ctx, expr6_0);
4350                                         return Some(expr7_0);
4351                                     }
4352                                 }
4353                             }
4354                             // Rule at src/isa/aarch64/lower.isle line 494.
4355                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
4356                             let expr1_0: Type = I64;
4357                             let expr2_0: u64 = 0;
4358                             let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
4359                             let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
4360                             let expr5_0 = C::output(ctx, expr4_0);
4361                             return Some(expr5_0);
4362                         }
4363                         &Opcode::Sextend => {
4364                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4365                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4366                                 if let &InstructionData::BinaryImm8 {
4367                                     opcode: ref pattern9_0,
4368                                     arg: pattern9_1,
4369                                     imm: pattern9_2,
4370                                 } = &pattern8_0
4371                                 {
4372                                     if let &Opcode::Extractlane = pattern9_0 {
4373                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4374                                         if pattern11_0 == I64X2 {
4375                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4376                                             // Rule at src/isa/aarch64/lower.isle line 543.
4377                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4378                                             let expr1_0 = VectorSize::Size64x2;
4379                                             let expr2_0 = constructor_mov_from_vec(
4380                                                 ctx,
4381                                                 expr0_0,
4382                                                 pattern13_0,
4383                                                 &expr1_0,
4384                                             )?;
4385                                             let expr3_0: Type = I64;
4386                                             let expr4_0: u8 = 63;
4387                                             let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
4388                                             let expr6_0 = constructor_asr_imm(
4389                                                 ctx, expr3_0, expr2_0, expr5_0,
4390                                             )?;
4391                                             let expr7_0 = C::value_regs(ctx, expr2_0, expr6_0);
4392                                             let expr8_0 = C::output(ctx, expr7_0);
4393                                             return Some(expr8_0);
4394                                         }
4395                                         if let Some(()) = C::not_i64x2(ctx, pattern11_0) {
4396                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4397                                             // Rule at src/isa/aarch64/lower.isle line 532.
4398                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4399                                             let expr1_0 =
4400                                                 constructor_vector_size(ctx, pattern11_0)?;
4401                                             let expr2_0: Type = I64;
4402                                             let expr3_0 = constructor_size_from_ty(ctx, expr2_0)?;
4403                                             let expr4_0 = constructor_mov_from_vec_signed(
4404                                                 ctx,
4405                                                 expr0_0,
4406                                                 pattern13_0,
4407                                                 &expr1_0,
4408                                                 &expr3_0,
4409                                             )?;
4410                                             let expr5_0: Type = I64;
4411                                             let expr6_0: u8 = 63;
4412                                             let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
4413                                             let expr8_0 = constructor_asr_imm(
4414                                                 ctx, expr5_0, expr4_0, expr7_0,
4415                                             )?;
4416                                             let expr9_0 = C::value_regs(ctx, expr4_0, expr8_0);
4417                                             let expr10_0 = C::output(ctx, expr9_0);
4418                                             return Some(expr10_0);
4419                                         }
4420                                     }
4421                                 }
4422                             }
4423                             // Rule at src/isa/aarch64/lower.isle line 522.
4424                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
4425                             let expr1_0: Type = I64;
4426                             let expr2_0: u8 = 63;
4427                             let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0);
4428                             let expr4_0 = constructor_asr_imm(ctx, expr1_0, expr0_0, expr3_0)?;
4429                             let expr5_0 = C::value_regs(ctx, expr0_0, expr4_0);
4430                             let expr6_0 = C::output(ctx, expr5_0);
4431                             return Some(expr6_0);
4432                         }
4433                         _ => {}
4434                     }
4435                 }
4436                 _ => {}
4437             }
4438         }
4439         if pattern2_0 == I8X16 {
4440             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4441             if let &InstructionData::Unary {
4442                 opcode: ref pattern5_0,
4443                 arg: pattern5_1,
4444             } = &pattern4_0
4445             {
4446                 if let &Opcode::Popcnt = pattern5_0 {
4447                     // Rule at src/isa/aarch64/lower.isle line 1125.
4448                     let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4449                     let expr1_0 = VectorSize::Size8x16;
4450                     let expr2_0 = constructor_vec_cnt(ctx, expr0_0, &expr1_0)?;
4451                     let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4452                     return Some(expr3_0);
4453                 }
4454             }
4455         }
4456         if pattern2_0 == I16X8 {
4457             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4458             if let &InstructionData::Binary {
4459                 opcode: ref pattern5_0,
4460                 args: ref pattern5_1,
4461             } = &pattern4_0
4462             {
4463                 if let &Opcode::Imul = pattern5_0 {
4464                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4465                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4466                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4467                         if let &InstructionData::Unary {
4468                             opcode: ref pattern10_0,
4469                             arg: pattern10_1,
4470                         } = &pattern9_0
4471                         {
4472                             match pattern10_0 {
4473                                 &Opcode::SwidenLow => {
4474                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4475                                     if pattern12_0 == I8X16 {
4476                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4477                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4478                                             if let &InstructionData::Unary {
4479                                                 opcode: ref pattern16_0,
4480                                                 arg: pattern16_1,
4481                                             } = &pattern15_0
4482                                             {
4483                                                 if let &Opcode::SwidenLow = pattern16_0 {
4484                                                     let pattern18_0 =
4485                                                         C::value_type(ctx, pattern16_1);
4486                                                     if pattern18_0 == I8X16 {
4487                                                         // Rule at src/isa/aarch64/lower.isle line 282.
4488                                                         let expr0_0 =
4489                                                             C::put_in_reg(ctx, pattern10_1);
4490                                                         let expr1_0 =
4491                                                             C::put_in_reg(ctx, pattern16_1);
4492                                                         let expr2_0: bool = false;
4493                                                         let expr3_0 = constructor_smull8(
4494                                                             ctx, expr0_0, expr1_0, expr2_0,
4495                                                         )?;
4496                                                         let expr4_0 =
4497                                                             constructor_output_reg(ctx, expr3_0)?;
4498                                                         return Some(expr4_0);
4499                                                     }
4500                                                 }
4501                                             }
4502                                         }
4503                                     }
4504                                 }
4505                                 &Opcode::SwidenHigh => {
4506                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4507                                     if pattern12_0 == I8X16 {
4508                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4509                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4510                                             if let &InstructionData::Unary {
4511                                                 opcode: ref pattern16_0,
4512                                                 arg: pattern16_1,
4513                                             } = &pattern15_0
4514                                             {
4515                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4516                                                     let pattern18_0 =
4517                                                         C::value_type(ctx, pattern16_1);
4518                                                     if pattern18_0 == I8X16 {
4519                                                         // Rule at src/isa/aarch64/lower.isle line 288.
4520                                                         let expr0_0 =
4521                                                             C::put_in_reg(ctx, pattern10_1);
4522                                                         let expr1_0 =
4523                                                             C::put_in_reg(ctx, pattern16_1);
4524                                                         let expr2_0: bool = true;
4525                                                         let expr3_0 = constructor_smull8(
4526                                                             ctx, expr0_0, expr1_0, expr2_0,
4527                                                         )?;
4528                                                         let expr4_0 =
4529                                                             constructor_output_reg(ctx, expr3_0)?;
4530                                                         return Some(expr4_0);
4531                                                     }
4532                                                 }
4533                                             }
4534                                         }
4535                                     }
4536                                 }
4537                                 &Opcode::UwidenLow => {
4538                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4539                                     if pattern12_0 == I8X16 {
4540                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4541                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4542                                             if let &InstructionData::Unary {
4543                                                 opcode: ref pattern16_0,
4544                                                 arg: pattern16_1,
4545                                             } = &pattern15_0
4546                                             {
4547                                                 if let &Opcode::UwidenLow = pattern16_0 {
4548                                                     let pattern18_0 =
4549                                                         C::value_type(ctx, pattern16_1);
4550                                                     if pattern18_0 == I8X16 {
4551                                                         // Rule at src/isa/aarch64/lower.isle line 294.
4552                                                         let expr0_0 =
4553                                                             C::put_in_reg(ctx, pattern10_1);
4554                                                         let expr1_0 =
4555                                                             C::put_in_reg(ctx, pattern16_1);
4556                                                         let expr2_0: bool = false;
4557                                                         let expr3_0 = constructor_umull8(
4558                                                             ctx, expr0_0, expr1_0, expr2_0,
4559                                                         )?;
4560                                                         let expr4_0 =
4561                                                             constructor_output_reg(ctx, expr3_0)?;
4562                                                         return Some(expr4_0);
4563                                                     }
4564                                                 }
4565                                             }
4566                                         }
4567                                     }
4568                                 }
4569                                 &Opcode::UwidenHigh => {
4570                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4571                                     if pattern12_0 == I8X16 {
4572                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4573                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4574                                             if let &InstructionData::Unary {
4575                                                 opcode: ref pattern16_0,
4576                                                 arg: pattern16_1,
4577                                             } = &pattern15_0
4578                                             {
4579                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4580                                                     let pattern18_0 =
4581                                                         C::value_type(ctx, pattern16_1);
4582                                                     if pattern18_0 == I8X16 {
4583                                                         // Rule at src/isa/aarch64/lower.isle line 300.
4584                                                         let expr0_0 =
4585                                                             C::put_in_reg(ctx, pattern10_1);
4586                                                         let expr1_0 =
4587                                                             C::put_in_reg(ctx, pattern16_1);
4588                                                         let expr2_0: bool = true;
4589                                                         let expr3_0 = constructor_umull8(
4590                                                             ctx, expr0_0, expr1_0, expr2_0,
4591                                                         )?;
4592                                                         let expr4_0 =
4593                                                             constructor_output_reg(ctx, expr3_0)?;
4594                                                         return Some(expr4_0);
4595                                                     }
4596                                                 }
4597                                             }
4598                                         }
4599                                     }
4600                                 }
4601                                 _ => {}
4602                             }
4603                         }
4604                     }
4605                 }
4606             }
4607         }
4608         if pattern2_0 == I32X4 {
4609             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4610             if let &InstructionData::Binary {
4611                 opcode: ref pattern5_0,
4612                 args: ref pattern5_1,
4613             } = &pattern4_0
4614             {
4615                 if let &Opcode::Imul = pattern5_0 {
4616                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4617                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4618                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4619                         if let &InstructionData::Unary {
4620                             opcode: ref pattern10_0,
4621                             arg: pattern10_1,
4622                         } = &pattern9_0
4623                         {
4624                             match pattern10_0 {
4625                                 &Opcode::SwidenLow => {
4626                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4627                                     if pattern12_0 == I16X8 {
4628                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4629                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4630                                             if let &InstructionData::Unary {
4631                                                 opcode: ref pattern16_0,
4632                                                 arg: pattern16_1,
4633                                             } = &pattern15_0
4634                                             {
4635                                                 if let &Opcode::SwidenLow = pattern16_0 {
4636                                                     let pattern18_0 =
4637                                                         C::value_type(ctx, pattern16_1);
4638                                                     if pattern18_0 == I16X8 {
4639                                                         // Rule at src/isa/aarch64/lower.isle line 306.
4640                                                         let expr0_0 =
4641                                                             C::put_in_reg(ctx, pattern10_1);
4642                                                         let expr1_0 =
4643                                                             C::put_in_reg(ctx, pattern16_1);
4644                                                         let expr2_0: bool = false;
4645                                                         let expr3_0 = constructor_smull16(
4646                                                             ctx, expr0_0, expr1_0, expr2_0,
4647                                                         )?;
4648                                                         let expr4_0 =
4649                                                             constructor_output_reg(ctx, expr3_0)?;
4650                                                         return Some(expr4_0);
4651                                                     }
4652                                                 }
4653                                             }
4654                                         }
4655                                     }
4656                                 }
4657                                 &Opcode::SwidenHigh => {
4658                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4659                                     if pattern12_0 == I16X8 {
4660                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4661                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4662                                             if let &InstructionData::Unary {
4663                                                 opcode: ref pattern16_0,
4664                                                 arg: pattern16_1,
4665                                             } = &pattern15_0
4666                                             {
4667                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4668                                                     let pattern18_0 =
4669                                                         C::value_type(ctx, pattern16_1);
4670                                                     if pattern18_0 == I16X8 {
4671                                                         // Rule at src/isa/aarch64/lower.isle line 312.
4672                                                         let expr0_0 =
4673                                                             C::put_in_reg(ctx, pattern10_1);
4674                                                         let expr1_0 =
4675                                                             C::put_in_reg(ctx, pattern16_1);
4676                                                         let expr2_0: bool = true;
4677                                                         let expr3_0 = constructor_smull16(
4678                                                             ctx, expr0_0, expr1_0, expr2_0,
4679                                                         )?;
4680                                                         let expr4_0 =
4681                                                             constructor_output_reg(ctx, expr3_0)?;
4682                                                         return Some(expr4_0);
4683                                                     }
4684                                                 }
4685                                             }
4686                                         }
4687                                     }
4688                                 }
4689                                 &Opcode::UwidenLow => {
4690                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4691                                     if pattern12_0 == I16X8 {
4692                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4693                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4694                                             if let &InstructionData::Unary {
4695                                                 opcode: ref pattern16_0,
4696                                                 arg: pattern16_1,
4697                                             } = &pattern15_0
4698                                             {
4699                                                 if let &Opcode::UwidenLow = pattern16_0 {
4700                                                     let pattern18_0 =
4701                                                         C::value_type(ctx, pattern16_1);
4702                                                     if pattern18_0 == I16X8 {
4703                                                         // Rule at src/isa/aarch64/lower.isle line 318.
4704                                                         let expr0_0 =
4705                                                             C::put_in_reg(ctx, pattern10_1);
4706                                                         let expr1_0 =
4707                                                             C::put_in_reg(ctx, pattern16_1);
4708                                                         let expr2_0: bool = false;
4709                                                         let expr3_0 = constructor_umull16(
4710                                                             ctx, expr0_0, expr1_0, expr2_0,
4711                                                         )?;
4712                                                         let expr4_0 =
4713                                                             constructor_output_reg(ctx, expr3_0)?;
4714                                                         return Some(expr4_0);
4715                                                     }
4716                                                 }
4717                                             }
4718                                         }
4719                                     }
4720                                 }
4721                                 &Opcode::UwidenHigh => {
4722                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4723                                     if pattern12_0 == I16X8 {
4724                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4725                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4726                                             if let &InstructionData::Unary {
4727                                                 opcode: ref pattern16_0,
4728                                                 arg: pattern16_1,
4729                                             } = &pattern15_0
4730                                             {
4731                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4732                                                     let pattern18_0 =
4733                                                         C::value_type(ctx, pattern16_1);
4734                                                     if pattern18_0 == I16X8 {
4735                                                         // Rule at src/isa/aarch64/lower.isle line 324.
4736                                                         let expr0_0 =
4737                                                             C::put_in_reg(ctx, pattern10_1);
4738                                                         let expr1_0 =
4739                                                             C::put_in_reg(ctx, pattern16_1);
4740                                                         let expr2_0: bool = true;
4741                                                         let expr3_0 = constructor_umull16(
4742                                                             ctx, expr0_0, expr1_0, expr2_0,
4743                                                         )?;
4744                                                         let expr4_0 =
4745                                                             constructor_output_reg(ctx, expr3_0)?;
4746                                                         return Some(expr4_0);
4747                                                     }
4748                                                 }
4749                                             }
4750                                         }
4751                                     }
4752                                 }
4753                                 _ => {}
4754                             }
4755                         }
4756                     }
4757                 }
4758             }
4759         }
4760         if pattern2_0 == I64X2 {
4761             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4762             if let &InstructionData::Binary {
4763                 opcode: ref pattern5_0,
4764                 args: ref pattern5_1,
4765             } = &pattern4_0
4766             {
4767                 if let &Opcode::Imul = pattern5_0 {
4768                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4769                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4770                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4771                         if let &InstructionData::Unary {
4772                             opcode: ref pattern10_0,
4773                             arg: pattern10_1,
4774                         } = &pattern9_0
4775                         {
4776                             match pattern10_0 {
4777                                 &Opcode::SwidenLow => {
4778                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4779                                     if pattern12_0 == I32X4 {
4780                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4781                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4782                                             if let &InstructionData::Unary {
4783                                                 opcode: ref pattern16_0,
4784                                                 arg: pattern16_1,
4785                                             } = &pattern15_0
4786                                             {
4787                                                 if let &Opcode::SwidenLow = pattern16_0 {
4788                                                     let pattern18_0 =
4789                                                         C::value_type(ctx, pattern16_1);
4790                                                     if pattern18_0 == I32X4 {
4791                                                         // Rule at src/isa/aarch64/lower.isle line 330.
4792                                                         let expr0_0 =
4793                                                             C::put_in_reg(ctx, pattern10_1);
4794                                                         let expr1_0 =
4795                                                             C::put_in_reg(ctx, pattern16_1);
4796                                                         let expr2_0: bool = false;
4797                                                         let expr3_0 = constructor_smull32(
4798                                                             ctx, expr0_0, expr1_0, expr2_0,
4799                                                         )?;
4800                                                         let expr4_0 =
4801                                                             constructor_output_reg(ctx, expr3_0)?;
4802                                                         return Some(expr4_0);
4803                                                     }
4804                                                 }
4805                                             }
4806                                         }
4807                                     }
4808                                 }
4809                                 &Opcode::SwidenHigh => {
4810                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4811                                     if pattern12_0 == I32X4 {
4812                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4813                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4814                                             if let &InstructionData::Unary {
4815                                                 opcode: ref pattern16_0,
4816                                                 arg: pattern16_1,
4817                                             } = &pattern15_0
4818                                             {
4819                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4820                                                     let pattern18_0 =
4821                                                         C::value_type(ctx, pattern16_1);
4822                                                     if pattern18_0 == I32X4 {
4823                                                         // Rule at src/isa/aarch64/lower.isle line 336.
4824                                                         let expr0_0 =
4825                                                             C::put_in_reg(ctx, pattern10_1);
4826                                                         let expr1_0 =
4827                                                             C::put_in_reg(ctx, pattern16_1);
4828                                                         let expr2_0: bool = true;
4829                                                         let expr3_0 = constructor_smull32(
4830                                                             ctx, expr0_0, expr1_0, expr2_0,
4831                                                         )?;
4832                                                         let expr4_0 =
4833                                                             constructor_output_reg(ctx, expr3_0)?;
4834                                                         return Some(expr4_0);
4835                                                     }
4836                                                 }
4837                                             }
4838                                         }
4839                                     }
4840                                 }
4841                                 &Opcode::UwidenLow => {
4842                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4843                                     if pattern12_0 == I32X4 {
4844                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4845                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4846                                             if let &InstructionData::Unary {
4847                                                 opcode: ref pattern16_0,
4848                                                 arg: pattern16_1,
4849                                             } = &pattern15_0
4850                                             {
4851                                                 if let &Opcode::UwidenLow = pattern16_0 {
4852                                                     let pattern18_0 =
4853                                                         C::value_type(ctx, pattern16_1);
4854                                                     if pattern18_0 == I32X4 {
4855                                                         // Rule at src/isa/aarch64/lower.isle line 342.
4856                                                         let expr0_0 =
4857                                                             C::put_in_reg(ctx, pattern10_1);
4858                                                         let expr1_0 =
4859                                                             C::put_in_reg(ctx, pattern16_1);
4860                                                         let expr2_0: bool = false;
4861                                                         let expr3_0 = constructor_umull32(
4862                                                             ctx, expr0_0, expr1_0, expr2_0,
4863                                                         )?;
4864                                                         let expr4_0 =
4865                                                             constructor_output_reg(ctx, expr3_0)?;
4866                                                         return Some(expr4_0);
4867                                                     }
4868                                                 }
4869                                             }
4870                                         }
4871                                     }
4872                                 }
4873                                 &Opcode::UwidenHigh => {
4874                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4875                                     if pattern12_0 == I32X4 {
4876                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4877                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4878                                             if let &InstructionData::Unary {
4879                                                 opcode: ref pattern16_0,
4880                                                 arg: pattern16_1,
4881                                             } = &pattern15_0
4882                                             {
4883                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4884                                                     let pattern18_0 =
4885                                                         C::value_type(ctx, pattern16_1);
4886                                                     if pattern18_0 == I32X4 {
4887                                                         // Rule at src/isa/aarch64/lower.isle line 348.
4888                                                         let expr0_0 =
4889                                                             C::put_in_reg(ctx, pattern10_1);
4890                                                         let expr1_0 =
4891                                                             C::put_in_reg(ctx, pattern16_1);
4892                                                         let expr2_0: bool = true;
4893                                                         let expr3_0 = constructor_umull32(
4894                                                             ctx, expr0_0, expr1_0, expr2_0,
4895                                                         )?;
4896                                                         let expr4_0 =
4897                                                             constructor_output_reg(ctx, expr3_0)?;
4898                                                         return Some(expr4_0);
4899                                                     }
4900                                                 }
4901                                             }
4902                                         }
4903                                     }
4904                                 }
4905                                 _ => {}
4906                             }
4907                         }
4908                     }
4909                     // Rule at src/isa/aarch64/lower.isle line 243.
4910                     let expr0_0 = C::put_in_reg(ctx, pattern7_0);
4911                     let expr1_0 = C::put_in_reg(ctx, pattern7_1);
4912                     let expr2_0 = VectorSize::Size32x4;
4913                     let expr3_0 = constructor_rev64(ctx, expr1_0, &expr2_0)?;
4914                     let expr4_0 = VectorSize::Size32x4;
4915                     let expr5_0 = constructor_mul(ctx, expr3_0, expr0_0, &expr4_0)?;
4916                     let expr6_0: bool = false;
4917                     let expr7_0 = constructor_xtn64(ctx, expr0_0, expr6_0)?;
4918                     let expr8_0 = VectorSize::Size32x4;
4919                     let expr9_0 = constructor_addp(ctx, expr5_0, expr5_0, &expr8_0)?;
4920                     let expr10_0: bool = false;
4921                     let expr11_0 = constructor_xtn64(ctx, expr1_0, expr10_0)?;
4922                     let expr12_0: bool = false;
4923                     let expr13_0 = constructor_shll32(ctx, expr9_0, expr12_0)?;
4924                     let expr14_0: bool = false;
4925                     let expr15_0 = constructor_umlal32(ctx, expr13_0, expr11_0, expr7_0, expr14_0)?;
4926                     let expr16_0 = constructor_output_reg(ctx, expr15_0)?;
4927                     return Some(expr16_0);
4928                 }
4929             }
4930         }
4931         let pattern3_0 = C::inst_data(ctx, pattern0_0);
4932         match &pattern3_0 {
4933             &InstructionData::NullAry {
4934                 opcode: ref pattern4_0,
4935             } => {
4936                 if let &Opcode::Null = pattern4_0 {
4937                     // Rule at src/isa/aarch64/lower.isle line 22.
4938                     let expr0_0: u64 = 0;
4939                     let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
4940                     let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
4941                     return Some(expr2_0);
4942                 }
4943             }
4944             &InstructionData::UnaryImm {
4945                 opcode: ref pattern4_0,
4946                 imm: pattern4_1,
4947             } => {
4948                 if let &Opcode::Iconst = pattern4_0 {
4949                     let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1);
4950                     // Rule at src/isa/aarch64/lower.isle line 9.
4951                     let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?;
4952                     let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
4953                     return Some(expr1_0);
4954                 }
4955             }
4956             &InstructionData::UnaryBool {
4957                 opcode: ref pattern4_0,
4958                 imm: pattern4_1,
4959             } => {
4960                 if let &Opcode::Bconst = pattern4_0 {
4961                     if pattern4_1 == true {
4962                         // Rule at src/isa/aarch64/lower.isle line 17.
4963                         let expr0_0: u64 = 1;
4964                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
4965                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
4966                         return Some(expr2_0);
4967                     }
4968                     if pattern4_1 == false {
4969                         // Rule at src/isa/aarch64/lower.isle line 14.
4970                         let expr0_0: u64 = 0;
4971                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
4972                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
4973                         return Some(expr2_0);
4974                     }
4975                 }
4976             }
4977             &InstructionData::Unary {
4978                 opcode: ref pattern4_0,
4979                 arg: pattern4_1,
4980             } => {
4981                 match pattern4_0 {
4982                     &Opcode::Bitrev => {
4983                         // Rule at src/isa/aarch64/lower.isle line 989.
4984                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
4985                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
4986                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
4987                         return Some(expr2_0);
4988                     }
4989                     &Opcode::Clz => {
4990                         // Rule at src/isa/aarch64/lower.isle line 1004.
4991                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
4992                         let expr1_0 = constructor_a64_clz(ctx, pattern2_0, expr0_0)?;
4993                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
4994                         return Some(expr2_0);
4995                     }
4996                     &Opcode::Cls => {
4997                         // Rule at src/isa/aarch64/lower.isle line 1071.
4998                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
4999                         let expr1_0 = constructor_a64_cls(ctx, pattern2_0, expr0_0)?;
5000                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5001                         return Some(expr2_0);
5002                     }
5003                     &Opcode::Ctz => {
5004                         // Rule at src/isa/aarch64/lower.isle line 1037.
5005                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5006                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5007                         let expr2_0 = constructor_a64_clz(ctx, pattern2_0, expr1_0)?;
5008                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5009                         return Some(expr3_0);
5010                     }
5011                     _ => {}
5012                 }
5013             }
5014             _ => {}
5015         }
5016         if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) {
5017             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5018             if let &InstructionData::Binary {
5019                 opcode: ref pattern5_0,
5020                 args: ref pattern5_1,
5021             } = &pattern4_0
5022             {
5023                 match pattern5_0 {
5024                     &Opcode::Iadd => {
5025                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5026                         // Rule at src/isa/aarch64/lower.isle line 75.
5027                         let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5028                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5029                         let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5030                         let expr3_0 = constructor_add_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5031                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5032                         return Some(expr4_0);
5033                     }
5034                     &Opcode::Isub => {
5035                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5036                         // Rule at src/isa/aarch64/lower.isle line 125.
5037                         let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5038                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5039                         let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5040                         let expr3_0 = constructor_sub_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5041                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5042                         return Some(expr4_0);
5043                     }
5044                     _ => {}
5045                 }
5046             }
5047         }
5048         if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
5049             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5050             if let &InstructionData::Binary {
5051                 opcode: ref pattern5_0,
5052                 args: ref pattern5_1,
5053             } = &pattern4_0
5054             {
5055                 match pattern5_0 {
5056                     &Opcode::Rotl => {
5057                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5058                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5059                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5060                             if let &InstructionData::UnaryImm {
5061                                 opcode: ref pattern10_0,
5062                                 imm: pattern10_1,
5063                             } = &pattern9_0
5064                             {
5065                                 if let &Opcode::Iconst = pattern10_0 {
5066                                     let closure12 = || {
5067                                         return Some(pattern3_0);
5068                                     };
5069                                     if let Some(pattern12_0) = closure12() {
5070                                         if let Some(pattern13_0) =
5071                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5072                                         {
5073                                             // Rule at src/isa/aarch64/lower.isle line 843.
5074                                             let expr0_0 =
5075                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5076                                             let expr1_0 =
5077                                                 C::negate_imm_shift(ctx, pattern3_0, pattern13_0);
5078                                             let expr2_0 = constructor_small_rotr_imm(
5079                                                 ctx, pattern3_0, expr0_0, expr1_0,
5080                                             )?;
5081                                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5082                                             return Some(expr3_0);
5083                                         }
5084                                     }
5085                                 }
5086                             }
5087                         }
5088                         // Rule at src/isa/aarch64/lower.isle line 838.
5089                         let expr0_0: Type = I32;
5090                         let expr1_0 = C::zero_reg(ctx);
5091                         let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5092                         let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
5093                         let expr4_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5094                         let expr5_0 = constructor_small_rotr(ctx, pattern3_0, expr4_0, expr3_0)?;
5095                         let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
5096                         return Some(expr6_0);
5097                     }
5098                     &Opcode::Rotr => {
5099                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5100                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5101                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5102                             if let &InstructionData::UnaryImm {
5103                                 opcode: ref pattern10_0,
5104                                 imm: pattern10_1,
5105                             } = &pattern9_0
5106                             {
5107                                 if let &Opcode::Iconst = pattern10_0 {
5108                                     let closure12 = || {
5109                                         return Some(pattern3_0);
5110                                     };
5111                                     if let Some(pattern12_0) = closure12() {
5112                                         if let Some(pattern13_0) =
5113                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5114                                         {
5115                                             // Rule at src/isa/aarch64/lower.isle line 903.
5116                                             let expr0_0 =
5117                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5118                                             let expr1_0 = constructor_small_rotr_imm(
5119                                                 ctx,
5120                                                 pattern3_0,
5121                                                 expr0_0,
5122                                                 pattern13_0,
5123                                             )?;
5124                                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5125                                             return Some(expr2_0);
5126                                         }
5127                                     }
5128                                 }
5129                             }
5130                         }
5131                         // Rule at src/isa/aarch64/lower.isle line 891.
5132                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5133                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5134                         let expr2_0 = constructor_small_rotr(ctx, pattern3_0, expr0_0, expr1_0)?;
5135                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5136                         return Some(expr3_0);
5137                     }
5138                     _ => {}
5139                 }
5140             }
5141         }
5142         if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
5143             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5144             if let &InstructionData::Binary {
5145                 opcode: ref pattern5_0,
5146                 args: ref pattern5_1,
5147             } = &pattern4_0
5148             {
5149                 match pattern5_0 {
5150                     &Opcode::Umulhi => {
5151                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5152                         // Rule at src/isa/aarch64/lower.isle line 370.
5153                         let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5154                         let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?;
5155                         let expr2_0 = C::zero_reg(ctx);
5156                         let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
5157                         let expr4_0: Type = I64;
5158                         let expr5_0 = C::ty_bits(ctx, pattern3_0);
5159                         let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
5160                         let expr7_0 = constructor_lsr_imm(ctx, expr4_0, expr3_0, expr6_0)?;
5161                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
5162                         return Some(expr8_0);
5163                     }
5164                     &Opcode::Smulhi => {
5165                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5166                         // Rule at src/isa/aarch64/lower.isle line 358.
5167                         let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5168                         let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?;
5169                         let expr2_0 = C::zero_reg(ctx);
5170                         let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
5171                         let expr4_0: Type = I64;
5172                         let expr5_0 = C::ty_bits(ctx, pattern3_0);
5173                         let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
5174                         let expr7_0 = constructor_asr_imm(ctx, expr4_0, expr3_0, expr6_0)?;
5175                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
5176                         return Some(expr8_0);
5177                     }
5178                     &Opcode::Band => {
5179                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5180                         // Rule at src/isa/aarch64/lower.isle line 583.
5181                         let expr0_0 = ALUOp::And;
5182                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5183                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5184                         )?;
5185                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5186                         return Some(expr2_0);
5187                     }
5188                     &Opcode::Bor => {
5189                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5190                         // Rule at src/isa/aarch64/lower.isle line 596.
5191                         let expr0_0 = ALUOp::Orr;
5192                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5193                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5194                         )?;
5195                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5196                         return Some(expr2_0);
5197                     }
5198                     &Opcode::Bxor => {
5199                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5200                         // Rule at src/isa/aarch64/lower.isle line 609.
5201                         let expr0_0 = ALUOp::Eor;
5202                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5203                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5204                         )?;
5205                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5206                         return Some(expr2_0);
5207                     }
5208                     &Opcode::BandNot => {
5209                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5210                         // Rule at src/isa/aarch64/lower.isle line 622.
5211                         let expr0_0 = ALUOp::AndNot;
5212                         let expr1_0 = constructor_alu_rs_imm_logic(
5213                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5214                         )?;
5215                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5216                         return Some(expr2_0);
5217                     }
5218                     &Opcode::BorNot => {
5219                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5220                         // Rule at src/isa/aarch64/lower.isle line 635.
5221                         let expr0_0 = ALUOp::OrrNot;
5222                         let expr1_0 = constructor_alu_rs_imm_logic(
5223                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5224                         )?;
5225                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5226                         return Some(expr2_0);
5227                     }
5228                     &Opcode::BxorNot => {
5229                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5230                         // Rule at src/isa/aarch64/lower.isle line 645.
5231                         let expr0_0 = ALUOp::EorNot;
5232                         let expr1_0: Type = I32;
5233                         let expr2_0 = constructor_alu_rs_imm_logic(
5234                             ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
5235                         )?;
5236                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5237                         return Some(expr3_0);
5238                     }
5239                     &Opcode::Ishl => {
5240                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5241                         // Rule at src/isa/aarch64/lower.isle line 656.
5242                         let expr0_0 = ALUOp::Lsl;
5243                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
5244                         let expr2_0 =
5245                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5246                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5247                         return Some(expr3_0);
5248                     }
5249                     &Opcode::Ushr => {
5250                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5251                         // Rule at src/isa/aarch64/lower.isle line 740.
5252                         let expr0_0 = ALUOp::Lsr;
5253                         let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5254                         let expr2_0 =
5255                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5256                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5257                         return Some(expr3_0);
5258                     }
5259                     &Opcode::Sshr => {
5260                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5261                         // Rule at src/isa/aarch64/lower.isle line 787.
5262                         let expr0_0 = ALUOp::Asr;
5263                         let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
5264                         let expr2_0 =
5265                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5266                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5267                         return Some(expr3_0);
5268                     }
5269                     _ => {}
5270                 }
5271             }
5272         }
5273         if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
5274             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5275             match &pattern4_0 {
5276                 &InstructionData::Binary {
5277                     opcode: ref pattern5_0,
5278                     args: ref pattern5_1,
5279                 } => {
5280                     match pattern5_0 {
5281                         &Opcode::Iadd => {
5282                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5283                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5284                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5285                                 match &pattern9_0 {
5286                                     &InstructionData::UnaryImm {
5287                                         opcode: ref pattern10_0,
5288                                         imm: pattern10_1,
5289                                     } => {
5290                                         if let &Opcode::Iconst = pattern10_0 {
5291                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5292                                             if let Some(pattern13_0) =
5293                                                 C::imm12_from_u64(ctx, pattern12_0)
5294                                             {
5295                                                 // Rule at src/isa/aarch64/lower.isle line 37.
5296                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5297                                                 let expr1_0 = constructor_add_imm(
5298                                                     ctx,
5299                                                     pattern3_0,
5300                                                     expr0_0,
5301                                                     pattern13_0,
5302                                                 )?;
5303                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5304                                                 return Some(expr2_0);
5305                                             }
5306                                             if let Some(pattern13_0) =
5307                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5308                                             {
5309                                                 // Rule at src/isa/aarch64/lower.isle line 45.
5310                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5311                                                 let expr1_0 = constructor_sub_imm(
5312                                                     ctx,
5313                                                     pattern3_0,
5314                                                     expr0_0,
5315                                                     pattern13_0,
5316                                                 )?;
5317                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5318                                                 return Some(expr2_0);
5319                                             }
5320                                         }
5321                                     }
5322                                     &InstructionData::Binary {
5323                                         opcode: ref pattern10_0,
5324                                         args: ref pattern10_1,
5325                                     } => {
5326                                         match pattern10_0 {
5327                                             &Opcode::Imul => {
5328                                                 let (pattern12_0, pattern12_1) =
5329                                                     C::unpack_value_array_2(ctx, pattern10_1);
5330                                                 // Rule at src/isa/aarch64/lower.isle line 70.
5331                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5332                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5333                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5334                                                 let expr3_0 = constructor_madd(
5335                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5336                                                 )?;
5337                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5338                                                 return Some(expr4_0);
5339                                             }
5340                                             &Opcode::Ishl => {
5341                                                 let (pattern12_0, pattern12_1) =
5342                                                     C::unpack_value_array_2(ctx, pattern10_1);
5343                                                 if let Some(pattern13_0) =
5344                                                     C::def_inst(ctx, pattern12_1)
5345                                                 {
5346                                                     let pattern14_0 =
5347                                                         C::inst_data(ctx, pattern13_0);
5348                                                     if let &InstructionData::UnaryImm {
5349                                                         opcode: ref pattern15_0,
5350                                                         imm: pattern15_1,
5351                                                     } = &pattern14_0
5352                                                     {
5353                                                         if let &Opcode::Iconst = pattern15_0 {
5354                                                             let closure17 = || {
5355                                                                 return Some(pattern3_0);
5356                                                             };
5357                                                             if let Some(pattern17_0) = closure17() {
5358                                                                 if let Some(pattern18_0) =
5359                                                                     C::lshl_from_imm64(
5360                                                                         ctx,
5361                                                                         pattern15_1,
5362                                                                         pattern17_0,
5363                                                                     )
5364                                                                 {
5365                                                                     // Rule at src/isa/aarch64/lower.isle line 62.
5366                                                                     let expr0_0 = C::put_in_reg(
5367                                                                         ctx, pattern7_1,
5368                                                                     );
5369                                                                     let expr1_0 = C::put_in_reg(
5370                                                                         ctx,
5371                                                                         pattern12_0,
5372                                                                     );
5373                                                                     let expr2_0 =
5374                                                                         constructor_add_shift(
5375                                                                             ctx,
5376                                                                             pattern3_0,
5377                                                                             expr0_0,
5378                                                                             expr1_0,
5379                                                                             pattern18_0,
5380                                                                         )?;
5381                                                                     let expr3_0 =
5382                                                                         constructor_output_reg(
5383                                                                             ctx, expr2_0,
5384                                                                         )?;
5385                                                                     return Some(expr3_0);
5386                                                                 }
5387                                                             }
5388                                                         }
5389                                                     }
5390                                                 }
5391                                             }
5392                                             _ => {}
5393                                         }
5394                                     }
5395                                     _ => {}
5396                                 }
5397                             }
5398                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0)
5399                             {
5400                                 // Rule at src/isa/aarch64/lower.isle line 53.
5401                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5402                                 let expr1_0 =
5403                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5404                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5405                                 return Some(expr2_0);
5406                             }
5407                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5408                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5409                                 match &pattern9_0 {
5410                                     &InstructionData::UnaryImm {
5411                                         opcode: ref pattern10_0,
5412                                         imm: pattern10_1,
5413                                     } => {
5414                                         if let &Opcode::Iconst = pattern10_0 {
5415                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5416                                             if let Some(pattern13_0) =
5417                                                 C::imm12_from_u64(ctx, pattern12_0)
5418                                             {
5419                                                 // Rule at src/isa/aarch64/lower.isle line 34.
5420                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5421                                                 let expr1_0 = constructor_add_imm(
5422                                                     ctx,
5423                                                     pattern3_0,
5424                                                     expr0_0,
5425                                                     pattern13_0,
5426                                                 )?;
5427                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5428                                                 return Some(expr2_0);
5429                                             }
5430                                             if let Some(pattern13_0) =
5431                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5432                                             {
5433                                                 // Rule at src/isa/aarch64/lower.isle line 42.
5434                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5435                                                 let expr1_0 = constructor_sub_imm(
5436                                                     ctx,
5437                                                     pattern3_0,
5438                                                     expr0_0,
5439                                                     pattern13_0,
5440                                                 )?;
5441                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5442                                                 return Some(expr2_0);
5443                                             }
5444                                         }
5445                                     }
5446                                     &InstructionData::Binary {
5447                                         opcode: ref pattern10_0,
5448                                         args: ref pattern10_1,
5449                                     } => {
5450                                         match pattern10_0 {
5451                                             &Opcode::Imul => {
5452                                                 let (pattern12_0, pattern12_1) =
5453                                                     C::unpack_value_array_2(ctx, pattern10_1);
5454                                                 // Rule at src/isa/aarch64/lower.isle line 67.
5455                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5456                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5457                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
5458                                                 let expr3_0 = constructor_madd(
5459                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5460                                                 )?;
5461                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5462                                                 return Some(expr4_0);
5463                                             }
5464                                             &Opcode::Ishl => {
5465                                                 let (pattern12_0, pattern12_1) =
5466                                                     C::unpack_value_array_2(ctx, pattern10_1);
5467                                                 if let Some(pattern13_0) =
5468                                                     C::def_inst(ctx, pattern12_1)
5469                                                 {
5470                                                     let pattern14_0 =
5471                                                         C::inst_data(ctx, pattern13_0);
5472                                                     if let &InstructionData::UnaryImm {
5473                                                         opcode: ref pattern15_0,
5474                                                         imm: pattern15_1,
5475                                                     } = &pattern14_0
5476                                                     {
5477                                                         if let &Opcode::Iconst = pattern15_0 {
5478                                                             let closure17 = || {
5479                                                                 return Some(pattern3_0);
5480                                                             };
5481                                                             if let Some(pattern17_0) = closure17() {
5482                                                                 if let Some(pattern18_0) =
5483                                                                     C::lshl_from_imm64(
5484                                                                         ctx,
5485                                                                         pattern15_1,
5486                                                                         pattern17_0,
5487                                                                     )
5488                                                                 {
5489                                                                     // Rule at src/isa/aarch64/lower.isle line 58.
5490                                                                     let expr0_0 = C::put_in_reg(
5491                                                                         ctx, pattern7_0,
5492                                                                     );
5493                                                                     let expr1_0 = C::put_in_reg(
5494                                                                         ctx,
5495                                                                         pattern12_0,
5496                                                                     );
5497                                                                     let expr2_0 =
5498                                                                         constructor_add_shift(
5499                                                                             ctx,
5500                                                                             pattern3_0,
5501                                                                             expr0_0,
5502                                                                             expr1_0,
5503                                                                             pattern18_0,
5504                                                                         )?;
5505                                                                     let expr3_0 =
5506                                                                         constructor_output_reg(
5507                                                                             ctx, expr2_0,
5508                                                                         )?;
5509                                                                     return Some(expr3_0);
5510                                                                 }
5511                                                             }
5512                                                         }
5513                                                     }
5514                                                 }
5515                                             }
5516                                             _ => {}
5517                                         }
5518                                     }
5519                                     _ => {}
5520                                 }
5521                             }
5522                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
5523                             {
5524                                 // Rule at src/isa/aarch64/lower.isle line 50.
5525                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5526                                 let expr1_0 =
5527                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5528                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5529                                 return Some(expr2_0);
5530                             }
5531                             // Rule at src/isa/aarch64/lower.isle line 30.
5532                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5533                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5534                             let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, expr1_0)?;
5535                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5536                             return Some(expr3_0);
5537                         }
5538                         &Opcode::Isub => {
5539                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5540                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5541                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5542                                 match &pattern9_0 {
5543                                     &InstructionData::UnaryImm {
5544                                         opcode: ref pattern10_0,
5545                                         imm: pattern10_1,
5546                                     } => {
5547                                         if let &Opcode::Iconst = pattern10_0 {
5548                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5549                                             if let Some(pattern13_0) =
5550                                                 C::imm12_from_u64(ctx, pattern12_0)
5551                                             {
5552                                                 // Rule at src/isa/aarch64/lower.isle line 105.
5553                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5554                                                 let expr1_0 = constructor_sub_imm(
5555                                                     ctx,
5556                                                     pattern3_0,
5557                                                     expr0_0,
5558                                                     pattern13_0,
5559                                                 )?;
5560                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5561                                                 return Some(expr2_0);
5562                                             }
5563                                             if let Some(pattern13_0) =
5564                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5565                                             {
5566                                                 // Rule at src/isa/aarch64/lower.isle line 110.
5567                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5568                                                 let expr1_0 = constructor_add_imm(
5569                                                     ctx,
5570                                                     pattern3_0,
5571                                                     expr0_0,
5572                                                     pattern13_0,
5573                                                 )?;
5574                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5575                                                 return Some(expr2_0);
5576                                             }
5577                                         }
5578                                     }
5579                                     &InstructionData::Binary {
5580                                         opcode: ref pattern10_0,
5581                                         args: ref pattern10_1,
5582                                     } => {
5583                                         if let &Opcode::Ishl = pattern10_0 {
5584                                             let (pattern12_0, pattern12_1) =
5585                                                 C::unpack_value_array_2(ctx, pattern10_1);
5586                                             if let Some(pattern13_0) = C::def_inst(ctx, pattern12_1)
5587                                             {
5588                                                 let pattern14_0 = C::inst_data(ctx, pattern13_0);
5589                                                 if let &InstructionData::UnaryImm {
5590                                                     opcode: ref pattern15_0,
5591                                                     imm: pattern15_1,
5592                                                 } = &pattern14_0
5593                                                 {
5594                                                     if let &Opcode::Iconst = pattern15_0 {
5595                                                         let closure17 = || {
5596                                                             return Some(pattern3_0);
5597                                                         };
5598                                                         if let Some(pattern17_0) = closure17() {
5599                                                             if let Some(pattern18_0) =
5600                                                                 C::lshl_from_imm64(
5601                                                                     ctx,
5602                                                                     pattern15_1,
5603                                                                     pattern17_0,
5604                                                                 )
5605                                                             {
5606                                                                 // Rule at src/isa/aarch64/lower.isle line 120.
5607                                                                 let expr0_0 =
5608                                                                     C::put_in_reg(ctx, pattern7_0);
5609                                                                 let expr1_0 =
5610                                                                     C::put_in_reg(ctx, pattern12_0);
5611                                                                 let expr2_0 =
5612                                                                     constructor_sub_shift(
5613                                                                         ctx,
5614                                                                         pattern3_0,
5615                                                                         expr0_0,
5616                                                                         expr1_0,
5617                                                                         pattern18_0,
5618                                                                     )?;
5619                                                                 let expr3_0 =
5620                                                                     constructor_output_reg(
5621                                                                         ctx, expr2_0,
5622                                                                     )?;
5623                                                                 return Some(expr3_0);
5624                                                             }
5625                                                         }
5626                                                     }
5627                                                 }
5628                                             }
5629                                         }
5630                                     }
5631                                     _ => {}
5632                                 }
5633                             }
5634                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
5635                             {
5636                                 // Rule at src/isa/aarch64/lower.isle line 115.
5637                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5638                                 let expr1_0 =
5639                                     constructor_sub_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5640                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5641                                 return Some(expr2_0);
5642                             }
5643                             // Rule at src/isa/aarch64/lower.isle line 101.
5644                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5645                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5646                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
5647                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5648                             return Some(expr3_0);
5649                         }
5650                         &Opcode::Imul => {
5651                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5652                             // Rule at src/isa/aarch64/lower.isle line 179.
5653                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5654                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5655                             let expr2_0 = C::zero_reg(ctx);
5656                             let expr3_0 =
5657                                 constructor_madd(ctx, pattern3_0, expr0_0, expr1_0, expr2_0)?;
5658                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5659                             return Some(expr4_0);
5660                         }
5661                         &Opcode::Udiv => {
5662                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5663                             // Rule at src/isa/aarch64/lower.isle line 384.
5664                             let expr0_0: Type = I64;
5665                             let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5666                             let expr2_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
5667                             let expr3_0 = constructor_a64_udiv(ctx, expr0_0, expr1_0, expr2_0)?;
5668                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5669                             return Some(expr4_0);
5670                         }
5671                         &Opcode::Sdiv => {
5672                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5673                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5674                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5675                                 if let &InstructionData::UnaryImm {
5676                                     opcode: ref pattern10_0,
5677                                     imm: pattern10_1,
5678                                 } = &pattern9_0
5679                                 {
5680                                     if let &Opcode::Iconst = pattern10_0 {
5681                                         if let Some(pattern12_0) =
5682                                             C::safe_divisor_from_imm64(ctx, pattern10_1)
5683                                         {
5684                                             // Rule at src/isa/aarch64/lower.isle line 430.
5685                                             let expr0_0: Type = I64;
5686                                             let expr1_0 =
5687                                                 constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5688                                             let expr2_0 =
5689                                                 constructor_imm(ctx, pattern3_0, pattern12_0)?;
5690                                             let expr3_0 = constructor_a64_sdiv(
5691                                                 ctx, expr0_0, expr1_0, expr2_0,
5692                                             )?;
5693                                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5694                                             return Some(expr4_0);
5695                                         }
5696                                     }
5697                                 }
5698                             }
5699                             // Rule at src/isa/aarch64/lower.isle line 417.
5700                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5701                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
5702                             let expr2_0 = constructor_trap_if_div_overflow(
5703                                 ctx, pattern3_0, expr0_0, expr1_0,
5704                             )?;
5705                             let expr3_0: Type = I64;
5706                             let expr4_0 = constructor_a64_sdiv(ctx, expr3_0, expr2_0, expr1_0)?;
5707                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5708                             return Some(expr5_0);
5709                         }
5710                         &Opcode::Urem => {
5711                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5712                             // Rule at src/isa/aarch64/lower.isle line 458.
5713                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5714                             let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
5715                             let expr2_0: Type = I64;
5716                             let expr3_0 = constructor_a64_udiv(ctx, expr2_0, expr0_0, expr1_0)?;
5717                             let expr4_0 = constructor_msub64(ctx, expr3_0, expr1_0, expr0_0)?;
5718                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5719                             return Some(expr5_0);
5720                         }
5721                         &Opcode::Srem => {
5722                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5723                             // Rule at src/isa/aarch64/lower.isle line 465.
5724                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5725                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
5726                             let expr2_0: Type = I64;
5727                             let expr3_0 = constructor_a64_sdiv(ctx, expr2_0, expr0_0, expr1_0)?;
5728                             let expr4_0 = constructor_msub64(ctx, expr3_0, expr1_0, expr0_0)?;
5729                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5730                             return Some(expr5_0);
5731                         }
5732                         _ => {}
5733                     }
5734                 }
5735                 &InstructionData::Unary {
5736                     opcode: ref pattern5_0,
5737                     arg: pattern5_1,
5738                 } => {
5739                     match pattern5_0 {
5740                         &Opcode::Ineg => {
5741                             // Rule at src/isa/aarch64/lower.isle line 169.
5742                             let expr0_0 = C::zero_reg(ctx);
5743                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
5744                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
5745                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5746                             return Some(expr3_0);
5747                         }
5748                         &Opcode::Bnot => {
5749                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
5750                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
5751                                 if let &InstructionData::Binary {
5752                                     opcode: ref pattern9_0,
5753                                     args: ref pattern9_1,
5754                                 } = &pattern8_0
5755                                 {
5756                                     if let &Opcode::Ishl = pattern9_0 {
5757                                         let (pattern11_0, pattern11_1) =
5758                                             C::unpack_value_array_2(ctx, pattern9_1);
5759                                         if let Some(pattern12_0) = C::def_inst(ctx, pattern11_1) {
5760                                             let pattern13_0 = C::inst_data(ctx, pattern12_0);
5761                                             if let &InstructionData::UnaryImm {
5762                                                 opcode: ref pattern14_0,
5763                                                 imm: pattern14_1,
5764                                             } = &pattern13_0
5765                                             {
5766                                                 if let &Opcode::Iconst = pattern14_0 {
5767                                                     let closure16 = || {
5768                                                         return Some(pattern3_0);
5769                                                     };
5770                                                     if let Some(pattern16_0) = closure16() {
5771                                                         if let Some(pattern17_0) =
5772                                                             C::lshl_from_imm64(
5773                                                                 ctx,
5774                                                                 pattern14_1,
5775                                                                 pattern16_0,
5776                                                             )
5777                                                         {
5778                                                             // Rule at src/isa/aarch64/lower.isle line 564.
5779                                                             let expr0_0 = C::zero_reg(ctx);
5780                                                             let expr1_0 =
5781                                                                 C::put_in_reg(ctx, pattern11_0);
5782                                                             let expr2_0 =
5783                                                                 constructor_orr_not_shift(
5784                                                                     ctx,
5785                                                                     pattern3_0,
5786                                                                     expr0_0,
5787                                                                     expr1_0,
5788                                                                     pattern17_0,
5789                                                                 )?;
5790                                                             let expr3_0 = constructor_output_reg(
5791                                                                 ctx, expr2_0,
5792                                                             )?;
5793                                                             return Some(expr3_0);
5794                                                         }
5795                                                     }
5796                                                 }
5797                                             }
5798                                         }
5799                                     }
5800                                 }
5801                             }
5802                             // Rule at src/isa/aarch64/lower.isle line 559.
5803                             let expr0_0 = C::zero_reg(ctx);
5804                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
5805                             let expr2_0 = constructor_orr_not(ctx, pattern3_0, expr0_0, expr1_0)?;
5806                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5807                             return Some(expr3_0);
5808                         }
5809                         &Opcode::Uextend => {
5810                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
5811                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
5812                                 if let &InstructionData::BinaryImm8 {
5813                                     opcode: ref pattern9_0,
5814                                     arg: pattern9_1,
5815                                     imm: pattern9_2,
5816                                 } = &pattern8_0
5817                                 {
5818                                     if let &Opcode::Extractlane = pattern9_0 {
5819                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
5820                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
5821                                         // Rule at src/isa/aarch64/lower.isle line 481.
5822                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
5823                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
5824                                         let expr2_0 = constructor_mov_from_vec(
5825                                             ctx,
5826                                             expr0_0,
5827                                             pattern12_0,
5828                                             &expr1_0,
5829                                         )?;
5830                                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5831                                         return Some(expr3_0);
5832                                     }
5833                                 }
5834                             }
5835                             let pattern7_0 = C::value_type(ctx, pattern5_1);
5836                             if let Some(pattern8_0) = C::sinkable_atomic_load(ctx, pattern5_1) {
5837                                 // Rule at src/isa/aarch64/lower.isle line 488.
5838                                 let expr0_0 = C::sink_atomic_load(ctx, &pattern8_0);
5839                                 let expr1_0 = constructor_load_acquire(ctx, pattern7_0, expr0_0)?;
5840                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5841                                 return Some(expr2_0);
5842                             }
5843                             // Rule at src/isa/aarch64/lower.isle line 476.
5844                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
5845                             let expr1_0: bool = false;
5846                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
5847                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
5848                             let expr4_0 =
5849                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
5850                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5851                             return Some(expr5_0);
5852                         }
5853                         &Opcode::Sextend => {
5854                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
5855                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
5856                                 if let &InstructionData::BinaryImm8 {
5857                                     opcode: ref pattern9_0,
5858                                     arg: pattern9_1,
5859                                     imm: pattern9_2,
5860                                 } = &pattern8_0
5861                                 {
5862                                     if let &Opcode::Extractlane = pattern9_0 {
5863                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
5864                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
5865                                         // Rule at src/isa/aarch64/lower.isle line 513.
5866                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
5867                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
5868                                         let expr2_0 = constructor_size_from_ty(ctx, pattern3_0)?;
5869                                         let expr3_0 = constructor_mov_from_vec_signed(
5870                                             ctx,
5871                                             expr0_0,
5872                                             pattern12_0,
5873                                             &expr1_0,
5874                                             &expr2_0,
5875                                         )?;
5876                                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5877                                         return Some(expr4_0);
5878                                     }
5879                                 }
5880                             }
5881                             let pattern7_0 = C::value_type(ctx, pattern5_1);
5882                             // Rule at src/isa/aarch64/lower.isle line 508.
5883                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
5884                             let expr1_0: bool = true;
5885                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
5886                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
5887                             let expr4_0 =
5888                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
5889                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5890                             return Some(expr5_0);
5891                         }
5892                         _ => {}
5893                     }
5894                 }
5895                 _ => {}
5896             }
5897         }
5898         if let Some(pattern3_0) = C::vec128(ctx, pattern2_0) {
5899             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5900             match &pattern4_0 {
5901                 &InstructionData::Binary {
5902                     opcode: ref pattern5_0,
5903                     args: ref pattern5_1,
5904                 } => {
5905                     match pattern5_0 {
5906                         &Opcode::UaddSat => {
5907                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5908                             // Rule at src/isa/aarch64/lower.isle line 148.
5909                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5910                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5911                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5912                             let expr3_0 = constructor_uqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
5913                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5914                             return Some(expr4_0);
5915                         }
5916                         &Opcode::SaddSat => {
5917                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5918                             // Rule at src/isa/aarch64/lower.isle line 153.
5919                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5920                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5921                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5922                             let expr3_0 = constructor_sqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
5923                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5924                             return Some(expr4_0);
5925                         }
5926                         &Opcode::UsubSat => {
5927                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5928                             // Rule at src/isa/aarch64/lower.isle line 158.
5929                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5930                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5931                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5932                             let expr3_0 = constructor_uqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
5933                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5934                             return Some(expr4_0);
5935                         }
5936                         &Opcode::SsubSat => {
5937                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5938                             // Rule at src/isa/aarch64/lower.isle line 163.
5939                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5940                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5941                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5942                             let expr3_0 = constructor_sqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
5943                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5944                             return Some(expr4_0);
5945                         }
5946                         &Opcode::Band => {
5947                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5948                             // Rule at src/isa/aarch64/lower.isle line 591.
5949                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5950                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5951                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5952                             let expr3_0 = constructor_and_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5953                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5954                             return Some(expr4_0);
5955                         }
5956                         &Opcode::Bor => {
5957                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5958                             // Rule at src/isa/aarch64/lower.isle line 604.
5959                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5960                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5961                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5962                             let expr3_0 = constructor_orr_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5963                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5964                             return Some(expr4_0);
5965                         }
5966                         &Opcode::Bxor => {
5967                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5968                             // Rule at src/isa/aarch64/lower.isle line 617.
5969                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5970                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5971                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5972                             let expr3_0 = constructor_eor_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5973                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5974                             return Some(expr4_0);
5975                         }
5976                         &Opcode::BandNot => {
5977                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5978                             // Rule at src/isa/aarch64/lower.isle line 630.
5979                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5980                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5981                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5982                             let expr3_0 = constructor_bic_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5983                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5984                             return Some(expr4_0);
5985                         }
5986                         &Opcode::Ishl => {
5987                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5988                             // Rule at src/isa/aarch64/lower.isle line 694.
5989                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
5990                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5991                             let expr2_0 = constructor_vec_dup(ctx, expr1_0, &expr0_0)?;
5992                             let expr3_0 = C::put_in_reg(ctx, pattern7_0);
5993                             let expr4_0 = constructor_sshl(ctx, expr3_0, expr2_0, &expr0_0)?;
5994                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5995                             return Some(expr5_0);
5996                         }
5997                         &Opcode::Ushr => {
5998                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5999                             // Rule at src/isa/aarch64/lower.isle line 752.
6000                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6001                             let expr1_0: Type = I32;
6002                             let expr2_0 = C::zero_reg(ctx);
6003                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6004                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6005                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6006                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6007                             let expr7_0 = constructor_ushl(ctx, expr6_0, expr5_0, &expr0_0)?;
6008                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6009                             return Some(expr8_0);
6010                         }
6011                         &Opcode::Sshr => {
6012                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6013                             // Rule at src/isa/aarch64/lower.isle line 801.
6014                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6015                             let expr1_0: Type = I32;
6016                             let expr2_0 = C::zero_reg(ctx);
6017                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6018                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6019                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6020                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6021                             let expr7_0 = constructor_sshl(ctx, expr6_0, expr5_0, &expr0_0)?;
6022                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6023                             return Some(expr8_0);
6024                         }
6025                         _ => {}
6026                     }
6027                 }
6028                 &InstructionData::Unary {
6029                     opcode: ref pattern5_0,
6030                     arg: pattern5_1,
6031                 } => {
6032                     match pattern5_0 {
6033                         &Opcode::Ineg => {
6034                             // Rule at src/isa/aarch64/lower.isle line 173.
6035                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6036                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6037                             let expr2_0 = constructor_neg(ctx, expr0_0, &expr1_0)?;
6038                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6039                             return Some(expr3_0);
6040                         }
6041                         &Opcode::Bnot => {
6042                             // Rule at src/isa/aarch64/lower.isle line 578.
6043                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6044                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6045                             let expr2_0 = constructor_not(ctx, expr0_0, &expr1_0)?;
6046                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6047                             return Some(expr3_0);
6048                         }
6049                         _ => {}
6050                     }
6051                 }
6052                 _ => {}
6053             }
6054             if let Some(()) = C::not_i64x2(ctx, pattern3_0) {
6055                 let pattern5_0 = C::inst_data(ctx, pattern0_0);
6056                 if let &InstructionData::Binary {
6057                     opcode: ref pattern6_0,
6058                     args: ref pattern6_1,
6059                 } = &pattern5_0
6060                 {
6061                     if let &Opcode::Imul = pattern6_0 {
6062                         let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
6063                         // Rule at src/isa/aarch64/lower.isle line 211.
6064                         let expr0_0 = C::put_in_reg(ctx, pattern8_0);
6065                         let expr1_0 = C::put_in_reg(ctx, pattern8_1);
6066                         let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6067                         let expr3_0 = constructor_mul(ctx, expr0_0, expr1_0, &expr2_0)?;
6068                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6069                         return Some(expr4_0);
6070                     }
6071                 }
6072             }
6073         }
6074     }
6075     return None;
6076 }
6077 
6078 // Generated as internal constructor for term put_nonzero_in_reg_zext64.
6079 pub fn constructor_put_nonzero_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6080     let pattern0_0 = arg0;
6081     let pattern1_0 = C::value_type(ctx, pattern0_0);
6082     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6083         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6084         if let &InstructionData::UnaryImm {
6085             opcode: ref pattern4_0,
6086             imm: pattern4_1,
6087         } = &pattern3_0
6088         {
6089             if let &Opcode::Iconst = pattern4_0 {
6090                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6091                     // Rule at src/isa/aarch64/lower.isle line 394.
6092                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6093                     return Some(expr0_0);
6094                 }
6095             }
6096         }
6097     }
6098     // Rule at src/isa/aarch64/lower.isle line 389.
6099     let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern0_0)?;
6100     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6101     return Some(expr1_0);
6102 }
6103 
6104 // Generated as internal constructor for term put_nonzero_in_reg_sext64.
6105 pub fn constructor_put_nonzero_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6106     let pattern0_0 = arg0;
6107     let pattern1_0 = C::value_type(ctx, pattern0_0);
6108     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6109         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6110         if let &InstructionData::UnaryImm {
6111             opcode: ref pattern4_0,
6112             imm: pattern4_1,
6113         } = &pattern3_0
6114         {
6115             if let &Opcode::Iconst = pattern4_0 {
6116                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6117                     // Rule at src/isa/aarch64/lower.isle line 440.
6118                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6119                     return Some(expr0_0);
6120                 }
6121             }
6122         }
6123     }
6124     // Rule at src/isa/aarch64/lower.isle line 435.
6125     let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern0_0)?;
6126     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6127     return Some(expr1_0);
6128 }
6129 
6130 // Generated as internal constructor for term lower_shl128.
6131 pub fn constructor_lower_shl128<C: Context>(
6132     ctx: &mut C,
6133     arg0: ValueRegs,
6134     arg1: Reg,
6135 ) -> Option<ValueRegs> {
6136     let pattern0_0 = arg0;
6137     let pattern1_0 = arg1;
6138     // Rule at src/isa/aarch64/lower.isle line 677.
6139     let expr0_0: usize = 0;
6140     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6141     let expr2_0: usize = 1;
6142     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6143     let expr4_0: Type = I64;
6144     let expr5_0 = constructor_lsl(ctx, expr4_0, expr1_0, pattern1_0)?;
6145     let expr6_0: Type = I64;
6146     let expr7_0 = constructor_lsl(ctx, expr6_0, expr3_0, pattern1_0)?;
6147     let expr8_0: Type = I32;
6148     let expr9_0 = C::zero_reg(ctx);
6149     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6150     let expr11_0: Type = I64;
6151     let expr12_0: Type = I64;
6152     let expr13_0: u8 = 1;
6153     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6154     let expr15_0 = constructor_lsr_imm(ctx, expr12_0, expr1_0, expr14_0)?;
6155     let expr16_0 = constructor_lsr(ctx, expr11_0, expr15_0, expr10_0)?;
6156     let expr17_0: Type = I64;
6157     let expr18_0 = constructor_orr(ctx, expr17_0, expr7_0, expr16_0)?;
6158     let expr19_0: Type = I64;
6159     let expr20_0: Type = I64;
6160     let expr21_0: u64 = 64;
6161     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6162     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6163     let expr24_0 = Cond::Ne;
6164     let expr25_0 = C::zero_reg(ctx);
6165     let expr26_0 = constructor_csel(ctx, &expr24_0, expr25_0, expr5_0)?;
6166     let expr27_0 = Cond::Ne;
6167     let expr28_0 = constructor_csel(ctx, &expr27_0, expr5_0, expr18_0)?;
6168     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr26_0, &expr28_0)?;
6169     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6170     return Some(expr30_0);
6171 }
6172 
6173 // Generated as internal constructor for term do_shift.
6174 pub fn constructor_do_shift<C: Context>(
6175     ctx: &mut C,
6176     arg0: &ALUOp,
6177     arg1: Type,
6178     arg2: Reg,
6179     arg3: Value,
6180 ) -> Option<Reg> {
6181     let pattern0_0 = arg0;
6182     let pattern1_0 = arg1;
6183     let pattern2_0 = arg2;
6184     let pattern3_0 = arg3;
6185     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
6186         let pattern5_0 = C::inst_data(ctx, pattern4_0);
6187         if let &InstructionData::UnaryImm {
6188             opcode: ref pattern6_0,
6189             imm: pattern6_1,
6190         } = &pattern5_0
6191         {
6192             if let &Opcode::Iconst = pattern6_0 {
6193                 let closure8 = || {
6194                     return Some(pattern1_0);
6195                 };
6196                 if let Some(pattern8_0) = closure8() {
6197                     if let Some(pattern9_0) = C::imm_shift_from_imm64(ctx, pattern6_1, pattern8_0) {
6198                         // Rule at src/isa/aarch64/lower.isle line 734.
6199                         let expr0_0 = constructor_alu_rr_imm_shift(
6200                             ctx, pattern0_0, pattern1_0, pattern2_0, pattern9_0,
6201                         )?;
6202                         return Some(expr0_0);
6203                     }
6204                 }
6205             }
6206         }
6207     }
6208     let pattern0_0 = arg0;
6209     let pattern1_0 = arg1;
6210     if pattern1_0 == I32 {
6211         let pattern3_0 = arg2;
6212         let pattern4_0 = arg3;
6213         // Rule at src/isa/aarch64/lower.isle line 725.
6214         let expr0_0: Type = I32;
6215         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6216         let expr2_0: usize = 0;
6217         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6218         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6219         return Some(expr4_0);
6220     }
6221     if pattern1_0 == I64 {
6222         let pattern3_0 = arg2;
6223         let pattern4_0 = arg3;
6224         // Rule at src/isa/aarch64/lower.isle line 726.
6225         let expr0_0: Type = I64;
6226         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6227         let expr2_0: usize = 0;
6228         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6229         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6230         return Some(expr4_0);
6231     }
6232     if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
6233         let pattern3_0 = arg2;
6234         let pattern4_0 = arg3;
6235         // Rule at src/isa/aarch64/lower.isle line 716.
6236         let expr0_0 = C::put_in_regs(ctx, pattern4_0);
6237         let expr1_0: usize = 0;
6238         let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
6239         let expr3_0: Type = I32;
6240         let expr4_0 = C::shift_mask(ctx, pattern2_0);
6241         let expr5_0 = constructor_and_imm(ctx, expr3_0, expr2_0, expr4_0)?;
6242         let expr6_0: Type = I32;
6243         let expr7_0 = constructor_alu_rrr(ctx, pattern0_0, expr6_0, pattern3_0, expr5_0)?;
6244         return Some(expr7_0);
6245     }
6246     return None;
6247 }
6248 
6249 // Generated as internal constructor for term lower_ushr128.
6250 pub fn constructor_lower_ushr128<C: Context>(
6251     ctx: &mut C,
6252     arg0: ValueRegs,
6253     arg1: Reg,
6254 ) -> Option<ValueRegs> {
6255     let pattern0_0 = arg0;
6256     let pattern1_0 = arg1;
6257     // Rule at src/isa/aarch64/lower.isle line 767.
6258     let expr0_0: usize = 0;
6259     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6260     let expr2_0: usize = 1;
6261     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6262     let expr4_0: Type = I64;
6263     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6264     let expr6_0: Type = I64;
6265     let expr7_0 = constructor_lsr(ctx, expr6_0, expr3_0, pattern1_0)?;
6266     let expr8_0: Type = I32;
6267     let expr9_0 = C::zero_reg(ctx);
6268     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6269     let expr11_0: Type = I64;
6270     let expr12_0: Type = I64;
6271     let expr13_0: u8 = 1;
6272     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6273     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6274     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6275     let expr17_0: Type = I64;
6276     let expr18_0 = constructor_orr(ctx, expr17_0, expr5_0, expr16_0)?;
6277     let expr19_0: Type = I64;
6278     let expr20_0: Type = I64;
6279     let expr21_0: u64 = 64;
6280     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6281     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6282     let expr24_0 = Cond::Ne;
6283     let expr25_0 = constructor_csel(ctx, &expr24_0, expr7_0, expr18_0)?;
6284     let expr26_0 = Cond::Ne;
6285     let expr27_0 = C::zero_reg(ctx);
6286     let expr28_0 = constructor_csel(ctx, &expr26_0, expr27_0, expr7_0)?;
6287     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr25_0, &expr28_0)?;
6288     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6289     return Some(expr30_0);
6290 }
6291 
6292 // Generated as internal constructor for term lower_sshr128.
6293 pub fn constructor_lower_sshr128<C: Context>(
6294     ctx: &mut C,
6295     arg0: ValueRegs,
6296     arg1: Reg,
6297 ) -> Option<ValueRegs> {
6298     let pattern0_0 = arg0;
6299     let pattern1_0 = arg1;
6300     // Rule at src/isa/aarch64/lower.isle line 817.
6301     let expr0_0: usize = 0;
6302     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6303     let expr2_0: usize = 1;
6304     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6305     let expr4_0: Type = I64;
6306     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6307     let expr6_0: Type = I64;
6308     let expr7_0 = constructor_asr(ctx, expr6_0, expr3_0, pattern1_0)?;
6309     let expr8_0: Type = I32;
6310     let expr9_0 = C::zero_reg(ctx);
6311     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6312     let expr11_0: Type = I64;
6313     let expr12_0: Type = I64;
6314     let expr13_0: u8 = 1;
6315     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6316     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6317     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6318     let expr17_0: Type = I64;
6319     let expr18_0: u8 = 63;
6320     let expr19_0 = C::imm_shift_from_u8(ctx, expr18_0);
6321     let expr20_0 = constructor_asr_imm(ctx, expr17_0, expr3_0, expr19_0)?;
6322     let expr21_0: Type = I64;
6323     let expr22_0 = constructor_orr(ctx, expr21_0, expr5_0, expr16_0)?;
6324     let expr23_0: Type = I64;
6325     let expr24_0: Type = I64;
6326     let expr25_0: u64 = 64;
6327     let expr26_0 = C::u64_into_imm_logic(ctx, expr24_0, expr25_0);
6328     let expr27_0 = constructor_tst_imm(ctx, expr23_0, pattern1_0, expr26_0)?;
6329     let expr28_0 = Cond::Ne;
6330     let expr29_0 = constructor_csel(ctx, &expr28_0, expr7_0, expr22_0)?;
6331     let expr30_0 = Cond::Ne;
6332     let expr31_0 = constructor_csel(ctx, &expr30_0, expr20_0, expr7_0)?;
6333     let expr32_0 = constructor_consumes_flags_concat(ctx, &expr29_0, &expr31_0)?;
6334     let expr33_0 = constructor_with_flags(ctx, &expr27_0, &expr32_0)?;
6335     return Some(expr33_0);
6336 }
6337 
6338 // Generated as internal constructor for term small_rotr.
6339 pub fn constructor_small_rotr<C: Context>(
6340     ctx: &mut C,
6341     arg0: Type,
6342     arg1: Reg,
6343     arg2: Reg,
6344 ) -> Option<Reg> {
6345     let pattern0_0 = arg0;
6346     let pattern1_0 = arg1;
6347     let pattern2_0 = arg2;
6348     // Rule at src/isa/aarch64/lower.isle line 927.
6349     let expr0_0: Type = I32;
6350     let expr1_0 = C::rotr_mask(ctx, pattern0_0);
6351     let expr2_0 = constructor_and_imm(ctx, expr0_0, pattern2_0, expr1_0)?;
6352     let expr3_0: Type = I32;
6353     let expr4_0 = C::ty_bits(ctx, pattern0_0);
6354     let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
6355     let expr6_0 = constructor_sub_imm(ctx, expr3_0, expr2_0, expr5_0)?;
6356     let expr7_0: Type = I32;
6357     let expr8_0 = C::zero_reg(ctx);
6358     let expr9_0 = constructor_sub(ctx, expr7_0, expr8_0, expr6_0)?;
6359     let expr10_0: Type = I32;
6360     let expr11_0 = constructor_lsr(ctx, expr10_0, pattern1_0, expr2_0)?;
6361     let expr12_0: Type = I32;
6362     let expr13_0 = constructor_lsl(ctx, expr12_0, pattern1_0, expr9_0)?;
6363     let expr14_0: Type = I32;
6364     let expr15_0 = constructor_orr(ctx, expr14_0, expr13_0, expr11_0)?;
6365     return Some(expr15_0);
6366 }
6367 
6368 // Generated as internal constructor for term small_rotr_imm.
6369 pub fn constructor_small_rotr_imm<C: Context>(
6370     ctx: &mut C,
6371     arg0: Type,
6372     arg1: Reg,
6373     arg2: ImmShift,
6374 ) -> Option<Reg> {
6375     let pattern0_0 = arg0;
6376     let pattern1_0 = arg1;
6377     let pattern2_0 = arg2;
6378     // Rule at src/isa/aarch64/lower.isle line 948.
6379     let expr0_0: Type = I32;
6380     let expr1_0 = constructor_lsr_imm(ctx, expr0_0, pattern1_0, pattern2_0)?;
6381     let expr2_0: Type = I32;
6382     let expr3_0 = C::rotr_opposite_amount(ctx, pattern0_0, pattern2_0);
6383     let expr4_0 = constructor_lsl_imm(ctx, expr2_0, pattern1_0, expr3_0)?;
6384     let expr5_0: Type = I32;
6385     let expr6_0 = constructor_orr(ctx, expr5_0, expr4_0, expr1_0)?;
6386     return Some(expr6_0);
6387 }
6388 
6389 // Generated as internal constructor for term lower_clz128.
6390 pub fn constructor_lower_clz128<C: Context>(ctx: &mut C, arg0: ValueRegs) -> Option<ValueRegs> {
6391     let pattern0_0 = arg0;
6392     // Rule at src/isa/aarch64/lower.isle line 1013.
6393     let expr0_0: Type = I64;
6394     let expr1_0: usize = 1;
6395     let expr2_0 = C::value_regs_get(ctx, pattern0_0, expr1_0);
6396     let expr3_0 = constructor_a64_clz(ctx, expr0_0, expr2_0)?;
6397     let expr4_0: Type = I64;
6398     let expr5_0: usize = 0;
6399     let expr6_0 = C::value_regs_get(ctx, pattern0_0, expr5_0);
6400     let expr7_0 = constructor_a64_clz(ctx, expr4_0, expr6_0)?;
6401     let expr8_0: Type = I64;
6402     let expr9_0: u8 = 6;
6403     let expr10_0 = C::imm_shift_from_u8(ctx, expr9_0);
6404     let expr11_0 = constructor_lsr_imm(ctx, expr8_0, expr3_0, expr10_0)?;
6405     let expr12_0 = constructor_madd64(ctx, expr7_0, expr11_0, expr3_0)?;
6406     let expr13_0: Type = I64;
6407     let expr14_0: u64 = 0;
6408     let expr15_0 = constructor_imm(ctx, expr13_0, expr14_0)?;
6409     let expr16_0 = C::value_regs(ctx, expr12_0, expr15_0);
6410     return Some(expr16_0);
6411 }
6412