1 // GENERATED BY ISLE. DO NOT EDIT!
2 //
3 // Generated automatically from the instruction-selection DSL code in:
4 // - src/clif.isle
5 // - src/prelude.isle
6 // - src/isa/aarch64/inst.isle
7 // - src/isa/aarch64/lower.isle
8 
9 #![allow(dead_code, unreachable_code, unreachable_patterns)]
10 #![allow(unused_imports, unused_variables, non_snake_case)]
11 #![allow(irrefutable_let_patterns)]
12 
13 use super::*; // Pulls in all external types.
14 
15 /// Context during lowering: an implementation of this trait
16 /// must be provided with all external constructors and extractors.
17 /// A mutable borrow is passed along through all lowering logic.
18 pub trait Context {
19     fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
20     fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
21     fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
22     fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
23     fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
24     fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
25     fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
26     fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
27     fn value_regs_invalid(&mut self) -> ValueRegs;
28     fn output_none(&mut self) -> InstOutput;
29     fn output(&mut self, arg0: ValueRegs) -> InstOutput;
30     fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput;
31     fn output_builder_new(&mut self) -> InstOutputBuilder;
32     fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit;
33     fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput;
34     fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
35     fn invalid_reg(&mut self) -> Reg;
36     fn put_in_reg(&mut self, arg0: Value) -> Reg;
37     fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
38     fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
39     fn u8_as_u64(&mut self, arg0: u8) -> u64;
40     fn u16_as_u64(&mut self, arg0: u16) -> u64;
41     fn u32_as_u64(&mut self, arg0: u32) -> u64;
42     fn i64_as_u64(&mut self, arg0: i64) -> u64;
43     fn u64_add(&mut self, arg0: u64, arg1: u64) -> u64;
44     fn u64_sub(&mut self, arg0: u64, arg1: u64) -> u64;
45     fn u64_and(&mut self, arg0: u64, arg1: u64) -> u64;
46     fn ty_bits(&mut self, arg0: Type) -> u8;
47     fn ty_bits_u16(&mut self, arg0: Type) -> u16;
48     fn ty_bits_u64(&mut self, arg0: Type) -> u64;
49     fn ty_mask(&mut self, arg0: Type) -> u64;
50     fn ty_bytes(&mut self, arg0: Type) -> u16;
51     fn lane_type(&mut self, arg0: Type) -> Type;
52     fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
53     fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
54     fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
55     fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
56     fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
57     fn ty_int_bool_64(&mut self, arg0: Type) -> Option<Type>;
58     fn ty_int_bool_128(&mut self, arg0: Type) -> Option<Type>;
59     fn vec128(&mut self, arg0: Type) -> Option<Type>;
60     fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
61     fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
62     fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>;
63     fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>;
64     fn value_slice_len(&mut self, arg0: ValueSlice) -> usize;
65     fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value;
66     fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
67     fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
68     fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
69     fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
70     fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
71     fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
72     fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
73     fn first_result(&mut self, arg0: Inst) -> Option<Value>;
74     fn inst_data(&mut self, arg0: Inst) -> InstructionData;
75     fn value_type(&mut self, arg0: Value) -> Type;
76     fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
77     fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
78     fn emit(&mut self, arg0: &MInst) -> Unit;
79     fn emit_safepoint(&mut self, arg0: &MInst) -> Unit;
80     fn trap_code_division_by_zero(&mut self) -> TrapCode;
81     fn trap_code_integer_overflow(&mut self) -> TrapCode;
82     fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
83     fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
84     fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
85     fn symbol_value_data(
86         &mut self,
87         arg0: GlobalValue,
88     ) -> Option<(ExternalName, RelocDistance, i64)>;
89     fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
90     fn move_wide_const_from_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
91     fn move_wide_const_from_negated_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
92     fn imm_logic_from_u64(&mut self, arg0: u64, arg1: Type) -> Option<ImmLogic>;
93     fn imm_logic_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmLogic>;
94     fn imm_shift_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmShift>;
95     fn imm_shift_from_u8(&mut self, arg0: u8) -> ImmShift;
96     fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12>;
97     fn u8_into_uimm5(&mut self, arg0: u8) -> UImm5;
98     fn u8_into_imm12(&mut self, arg0: u8) -> Imm12;
99     fn u64_into_imm_logic(&mut self, arg0: Type, arg1: u64) -> ImmLogic;
100     fn imm12_from_negated_u64(&mut self, arg0: u64) -> Option<Imm12>;
101     fn lshl_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ShiftOpAndAmt>;
102     fn integral_ty(&mut self, arg0: Type) -> Option<Type>;
103     fn extended_value_from_value(&mut self, arg0: Value) -> Option<ExtendedValue>;
104     fn put_extended_in_reg(&mut self, arg0: &ExtendedValue) -> Reg;
105     fn get_extended_op(&mut self, arg0: &ExtendedValue) -> ExtendOp;
106     fn nzcv(&mut self, arg0: bool, arg1: bool, arg2: bool, arg3: bool) -> NZCV;
107     fn cond_br_zero(&mut self, arg0: Reg) -> CondBrKind;
108     fn cond_br_cond(&mut self, arg0: &Cond) -> CondBrKind;
109     fn zero_reg(&mut self) -> Reg;
110     fn writable_zero_reg(&mut self) -> WritableReg;
111     fn load_constant64_full(&mut self, arg0: u64) -> Reg;
112     fn sinkable_atomic_load(&mut self, arg0: Value) -> Option<SinkableAtomicLoad>;
113     fn sink_atomic_load(&mut self, arg0: &SinkableAtomicLoad) -> Reg;
114     fn safe_divisor_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
115     fn shift_mask(&mut self, arg0: Type) -> ImmLogic;
116     fn negate_imm_shift(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
117     fn rotr_mask(&mut self, arg0: Type) -> ImmLogic;
118     fn rotr_opposite_amount(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
119 }
120 
121 /// Internal type SideEffectNoResult: defined at src/prelude.isle line 393.
122 #[derive(Clone, Debug)]
123 pub enum SideEffectNoResult {
124     Inst { inst: MInst },
125 }
126 
127 /// Internal type ProducesFlags: defined at src/prelude.isle line 415.
128 #[derive(Clone, Debug)]
129 pub enum ProducesFlags {
130     ProducesFlagsSideEffect { inst: MInst },
131     ProducesFlagsReturnsReg { inst: MInst, result: Reg },
132     ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg },
133 }
134 
135 /// Internal type ConsumesFlags: defined at src/prelude.isle line 426.
136 #[derive(Clone, Debug)]
137 pub enum ConsumesFlags {
138     ConsumesFlagsReturnsResultWithProducer {
139         inst: MInst,
140         result: Reg,
141     },
142     ConsumesFlagsReturnsReg {
143         inst: MInst,
144         result: Reg,
145     },
146     ConsumesFlagsTwiceReturnsValueRegs {
147         inst1: MInst,
148         inst2: MInst,
149         result: ValueRegs,
150     },
151     ConsumesFlagsFourTimesReturnsValueRegs {
152         inst1: MInst,
153         inst2: MInst,
154         inst3: MInst,
155         inst4: MInst,
156         result: ValueRegs,
157     },
158 }
159 
160 /// Internal type MInst: defined at src/isa/aarch64/inst.isle line 2.
161 #[derive(Clone, Debug)]
162 pub enum MInst {
163     Nop0,
164     Nop4,
165     AluRRR {
166         alu_op: ALUOp,
167         size: OperandSize,
168         rd: WritableReg,
169         rn: Reg,
170         rm: Reg,
171     },
172     AluRRRR {
173         alu_op: ALUOp3,
174         rd: WritableReg,
175         rn: Reg,
176         rm: Reg,
177         ra: Reg,
178     },
179     AluRRImm12 {
180         alu_op: ALUOp,
181         size: OperandSize,
182         rd: WritableReg,
183         rn: Reg,
184         imm12: Imm12,
185     },
186     AluRRImmLogic {
187         alu_op: ALUOp,
188         size: OperandSize,
189         rd: WritableReg,
190         rn: Reg,
191         imml: ImmLogic,
192     },
193     AluRRImmShift {
194         alu_op: ALUOp,
195         size: OperandSize,
196         rd: WritableReg,
197         rn: Reg,
198         immshift: ImmShift,
199     },
200     AluRRRShift {
201         alu_op: ALUOp,
202         size: OperandSize,
203         rd: WritableReg,
204         rn: Reg,
205         rm: Reg,
206         shiftop: ShiftOpAndAmt,
207     },
208     AluRRRExtend {
209         alu_op: ALUOp,
210         size: OperandSize,
211         rd: WritableReg,
212         rn: Reg,
213         rm: Reg,
214         extendop: ExtendOp,
215     },
216     BitRR {
217         op: BitOp,
218         size: OperandSize,
219         rd: WritableReg,
220         rn: Reg,
221     },
222     ULoad8 {
223         rd: WritableReg,
224         mem: AMode,
225         flags: MemFlags,
226     },
227     SLoad8 {
228         rd: WritableReg,
229         mem: AMode,
230         flags: MemFlags,
231     },
232     ULoad16 {
233         rd: WritableReg,
234         mem: AMode,
235         flags: MemFlags,
236     },
237     SLoad16 {
238         rd: WritableReg,
239         mem: AMode,
240         flags: MemFlags,
241     },
242     ULoad32 {
243         rd: WritableReg,
244         mem: AMode,
245         flags: MemFlags,
246     },
247     SLoad32 {
248         rd: WritableReg,
249         mem: AMode,
250         flags: MemFlags,
251     },
252     ULoad64 {
253         rd: WritableReg,
254         mem: AMode,
255         flags: MemFlags,
256     },
257     Store8 {
258         rd: Reg,
259         mem: AMode,
260         flags: MemFlags,
261     },
262     Store16 {
263         rd: Reg,
264         mem: AMode,
265         flags: MemFlags,
266     },
267     Store32 {
268         rd: Reg,
269         mem: AMode,
270         flags: MemFlags,
271     },
272     Store64 {
273         rd: Reg,
274         mem: AMode,
275         flags: MemFlags,
276     },
277     StoreP64 {
278         rt: Reg,
279         rt2: Reg,
280         mem: PairAMode,
281         flags: MemFlags,
282     },
283     LoadP64 {
284         rt: WritableReg,
285         rt2: WritableReg,
286         mem: PairAMode,
287         flags: MemFlags,
288     },
289     Mov64 {
290         rd: WritableReg,
291         rm: Reg,
292     },
293     Mov32 {
294         rd: WritableReg,
295         rm: Reg,
296     },
297     MovZ {
298         rd: WritableReg,
299         imm: MoveWideConst,
300         size: OperandSize,
301     },
302     MovN {
303         rd: WritableReg,
304         imm: MoveWideConst,
305         size: OperandSize,
306     },
307     MovK {
308         rd: WritableReg,
309         imm: MoveWideConst,
310         size: OperandSize,
311     },
312     Extend {
313         rd: WritableReg,
314         rn: Reg,
315         signed: bool,
316         from_bits: u8,
317         to_bits: u8,
318     },
319     CSel {
320         rd: WritableReg,
321         cond: Cond,
322         rn: Reg,
323         rm: Reg,
324     },
325     CSet {
326         rd: WritableReg,
327         cond: Cond,
328     },
329     CSetm {
330         rd: WritableReg,
331         cond: Cond,
332     },
333     CCmpImm {
334         size: OperandSize,
335         rn: Reg,
336         imm: UImm5,
337         nzcv: NZCV,
338         cond: Cond,
339     },
340     AtomicRMWLoop {
341         ty: Type,
342         op: AtomicRmwOp,
343     },
344     AtomicRMW {
345         op: AtomicRMWOp,
346         rs: Reg,
347         rt: WritableReg,
348         rn: Reg,
349         ty: Type,
350     },
351     AtomicCAS {
352         rs: WritableReg,
353         rt: Reg,
354         rn: Reg,
355         ty: Type,
356     },
357     AtomicCASLoop {
358         ty: Type,
359     },
360     LoadAcquire {
361         access_ty: Type,
362         rt: WritableReg,
363         rn: Reg,
364     },
365     StoreRelease {
366         access_ty: Type,
367         rt: Reg,
368         rn: Reg,
369     },
370     Fence,
371     FpuMove64 {
372         rd: WritableReg,
373         rn: Reg,
374     },
375     FpuMove128 {
376         rd: WritableReg,
377         rn: Reg,
378     },
379     FpuMoveFromVec {
380         rd: WritableReg,
381         rn: Reg,
382         idx: u8,
383         size: VectorSize,
384     },
385     FpuExtend {
386         rd: WritableReg,
387         rn: Reg,
388         size: ScalarSize,
389     },
390     FpuRR {
391         fpu_op: FPUOp1,
392         rd: WritableReg,
393         rn: Reg,
394     },
395     FpuRRR {
396         fpu_op: FPUOp2,
397         rd: WritableReg,
398         rn: Reg,
399         rm: Reg,
400     },
401     FpuRRI {
402         fpu_op: FPUOpRI,
403         rd: WritableReg,
404         rn: Reg,
405     },
406     FpuRRRR {
407         fpu_op: FPUOp3,
408         rd: WritableReg,
409         rn: Reg,
410         rm: Reg,
411         ra: Reg,
412     },
413     FpuCmp32 {
414         rn: Reg,
415         rm: Reg,
416     },
417     FpuCmp64 {
418         rn: Reg,
419         rm: Reg,
420     },
421     FpuLoad32 {
422         rd: WritableReg,
423         mem: AMode,
424         flags: MemFlags,
425     },
426     FpuStore32 {
427         rd: Reg,
428         mem: AMode,
429         flags: MemFlags,
430     },
431     FpuLoad64 {
432         rd: WritableReg,
433         mem: AMode,
434         flags: MemFlags,
435     },
436     FpuStore64 {
437         rd: Reg,
438         mem: AMode,
439         flags: MemFlags,
440     },
441     FpuLoad128 {
442         rd: WritableReg,
443         mem: AMode,
444         flags: MemFlags,
445     },
446     FpuStore128 {
447         rd: Reg,
448         mem: AMode,
449         flags: MemFlags,
450     },
451     FpuLoadP64 {
452         rt: WritableReg,
453         rt2: WritableReg,
454         mem: PairAMode,
455         flags: MemFlags,
456     },
457     FpuStoreP64 {
458         rt: Reg,
459         rt2: Reg,
460         mem: PairAMode,
461         flags: MemFlags,
462     },
463     FpuLoadP128 {
464         rt: WritableReg,
465         rt2: WritableReg,
466         mem: PairAMode,
467         flags: MemFlags,
468     },
469     FpuStoreP128 {
470         rt: Reg,
471         rt2: Reg,
472         mem: PairAMode,
473         flags: MemFlags,
474     },
475     LoadFpuConst64 {
476         rd: WritableReg,
477         const_data: u64,
478     },
479     LoadFpuConst128 {
480         rd: WritableReg,
481         const_data: u128,
482     },
483     FpuToInt {
484         op: FpuToIntOp,
485         rd: WritableReg,
486         rn: Reg,
487     },
488     IntToFpu {
489         op: IntToFpuOp,
490         rd: WritableReg,
491         rn: Reg,
492     },
493     FpuCSel32 {
494         rd: WritableReg,
495         rn: Reg,
496         rm: Reg,
497         cond: Cond,
498     },
499     FpuCSel64 {
500         rd: WritableReg,
501         rn: Reg,
502         rm: Reg,
503         cond: Cond,
504     },
505     FpuRound {
506         op: FpuRoundMode,
507         rd: WritableReg,
508         rn: Reg,
509     },
510     MovToFpu {
511         rd: WritableReg,
512         rn: Reg,
513         size: ScalarSize,
514     },
515     FpuMoveFPImm {
516         rd: WritableReg,
517         imm: ASIMDFPModImm,
518         size: ScalarSize,
519     },
520     MovToVec {
521         rd: WritableReg,
522         rn: Reg,
523         idx: u8,
524         size: VectorSize,
525     },
526     MovFromVec {
527         rd: WritableReg,
528         rn: Reg,
529         idx: u8,
530         size: VectorSize,
531     },
532     MovFromVecSigned {
533         rd: WritableReg,
534         rn: Reg,
535         idx: u8,
536         size: VectorSize,
537         scalar_size: OperandSize,
538     },
539     VecDup {
540         rd: WritableReg,
541         rn: Reg,
542         size: VectorSize,
543     },
544     VecDupFromFpu {
545         rd: WritableReg,
546         rn: Reg,
547         size: VectorSize,
548     },
549     VecDupFPImm {
550         rd: WritableReg,
551         imm: ASIMDFPModImm,
552         size: VectorSize,
553     },
554     VecDupImm {
555         rd: WritableReg,
556         imm: ASIMDMovModImm,
557         invert: bool,
558         size: VectorSize,
559     },
560     VecExtend {
561         t: VecExtendOp,
562         rd: WritableReg,
563         rn: Reg,
564         high_half: bool,
565     },
566     VecMovElement {
567         rd: WritableReg,
568         rn: Reg,
569         dest_idx: u8,
570         src_idx: u8,
571         size: VectorSize,
572     },
573     VecRRLong {
574         op: VecRRLongOp,
575         rd: WritableReg,
576         rn: Reg,
577         high_half: bool,
578     },
579     VecRRNarrow {
580         op: VecRRNarrowOp,
581         rd: WritableReg,
582         rn: Reg,
583         high_half: bool,
584     },
585     VecRRPair {
586         op: VecPairOp,
587         rd: WritableReg,
588         rn: Reg,
589     },
590     VecRRRLong {
591         alu_op: VecRRRLongOp,
592         rd: WritableReg,
593         rn: Reg,
594         rm: Reg,
595         high_half: bool,
596     },
597     VecRRPairLong {
598         op: VecRRPairLongOp,
599         rd: WritableReg,
600         rn: Reg,
601     },
602     VecRRR {
603         alu_op: VecALUOp,
604         rd: WritableReg,
605         rn: Reg,
606         rm: Reg,
607         size: VectorSize,
608     },
609     VecMisc {
610         op: VecMisc2,
611         rd: WritableReg,
612         rn: Reg,
613         size: VectorSize,
614     },
615     VecLanes {
616         op: VecLanesOp,
617         rd: WritableReg,
618         rn: Reg,
619         size: VectorSize,
620     },
621     VecShiftImm {
622         op: VecShiftImmOp,
623         rd: WritableReg,
624         rn: Reg,
625         size: VectorSize,
626         imm: u8,
627     },
628     VecExtract {
629         rd: WritableReg,
630         rn: Reg,
631         rm: Reg,
632         imm4: u8,
633     },
634     VecTbl {
635         rd: WritableReg,
636         rn: Reg,
637         rm: Reg,
638         is_extension: bool,
639     },
640     VecTbl2 {
641         rd: WritableReg,
642         rn: Reg,
643         rn2: Reg,
644         rm: Reg,
645         is_extension: bool,
646     },
647     VecLoadReplicate {
648         rd: WritableReg,
649         rn: Reg,
650         size: VectorSize,
651     },
652     VecCSel {
653         rd: WritableReg,
654         rn: Reg,
655         rm: Reg,
656         cond: Cond,
657     },
658     MovToNZCV {
659         rn: Reg,
660     },
661     MovFromNZCV {
662         rd: WritableReg,
663     },
664     Call {
665         info: BoxCallInfo,
666     },
667     CallInd {
668         info: BoxCallIndInfo,
669     },
670     Ret,
671     EpiloguePlaceholder,
672     Jump {
673         dest: BranchTarget,
674     },
675     CondBr {
676         taken: BranchTarget,
677         not_taken: BranchTarget,
678         kind: CondBrKind,
679     },
680     TrapIf {
681         kind: CondBrKind,
682         trap_code: TrapCode,
683     },
684     IndirectBr {
685         rn: Reg,
686         targets: VecMachLabel,
687     },
688     Brk,
689     Udf {
690         trap_code: TrapCode,
691     },
692     Adr {
693         rd: WritableReg,
694         off: i32,
695     },
696     Word4 {
697         data: u32,
698     },
699     Word8 {
700         data: u64,
701     },
702     JTSequence {
703         info: BoxJTSequenceInfo,
704         ridx: Reg,
705         rtmp1: WritableReg,
706         rtmp2: WritableReg,
707     },
708     LoadExtName {
709         rd: WritableReg,
710         name: BoxExternalName,
711         offset: i64,
712     },
713     LoadAddr {
714         rd: WritableReg,
715         mem: AMode,
716     },
717     VirtualSPOffsetAdj {
718         offset: i64,
719     },
720     EmitIsland {
721         needed_space: CodeOffset,
722     },
723     ElfTlsGetAddr {
724         symbol: ExternalName,
725     },
726     ValueLabelMarker {
727         reg: Reg,
728         label: ValueLabel,
729     },
730     Unwind {
731         inst: UnwindInst,
732     },
733 }
734 
735 /// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 796.
736 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
737 pub enum ALUOp {
738     Add,
739     Sub,
740     Orr,
741     OrrNot,
742     And,
743     AndS,
744     AndNot,
745     Eor,
746     EorNot,
747     AddS,
748     SubS,
749     SMulH,
750     UMulH,
751     SDiv,
752     UDiv,
753     RotR,
754     Lsr,
755     Asr,
756     Lsl,
757     Adc,
758     AdcS,
759     Sbc,
760     SbcS,
761 }
762 
763 /// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 834.
764 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
765 pub enum ALUOp3 {
766     MAdd32,
767     MAdd64,
768     MSub32,
769     MSub64,
770 }
771 
772 /// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 877.
773 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
774 pub enum BitOp {
775     RBit,
776     Clz,
777     Cls,
778 }
779 
780 /// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 944.
781 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
782 pub enum FPUOp1 {
783     Abs32,
784     Abs64,
785     Neg32,
786     Neg64,
787     Sqrt32,
788     Sqrt64,
789     Cvt32To64,
790     Cvt64To32,
791 }
792 
793 /// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 957.
794 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
795 pub enum FPUOp2 {
796     Add32,
797     Add64,
798     Sub32,
799     Sub64,
800     Mul32,
801     Mul64,
802     Div32,
803     Div64,
804     Max32,
805     Max64,
806     Min32,
807     Min64,
808     Sqadd64,
809     Uqadd64,
810     Sqsub64,
811     Uqsub64,
812 }
813 
814 /// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 982.
815 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
816 pub enum FPUOp3 {
817     MAdd32,
818     MAdd64,
819 }
820 
821 /// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 989.
822 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
823 pub enum FpuToIntOp {
824     F32ToU32,
825     F32ToI32,
826     F32ToU64,
827     F32ToI64,
828     F64ToU32,
829     F64ToI32,
830     F64ToU64,
831     F64ToI64,
832 }
833 
834 /// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 1002.
835 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
836 pub enum IntToFpuOp {
837     U32ToF32,
838     I32ToF32,
839     U32ToF64,
840     I32ToF64,
841     U64ToF32,
842     I64ToF32,
843     U64ToF64,
844     I64ToF64,
845 }
846 
847 /// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 1016.
848 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
849 pub enum FpuRoundMode {
850     Minus32,
851     Minus64,
852     Plus32,
853     Plus64,
854     Zero32,
855     Zero64,
856     Nearest32,
857     Nearest64,
858 }
859 
860 /// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 1029.
861 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
862 pub enum VecExtendOp {
863     Sxtl8,
864     Sxtl16,
865     Sxtl32,
866     Uxtl8,
867     Uxtl16,
868     Uxtl32,
869 }
870 
871 /// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1046.
872 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
873 pub enum VecALUOp {
874     Sqadd,
875     Uqadd,
876     Sqsub,
877     Uqsub,
878     Cmeq,
879     Cmge,
880     Cmgt,
881     Cmhs,
882     Cmhi,
883     Fcmeq,
884     Fcmgt,
885     Fcmge,
886     And,
887     Bic,
888     Orr,
889     Eor,
890     Bsl,
891     Umaxp,
892     Add,
893     Sub,
894     Mul,
895     Sshl,
896     Ushl,
897     Umin,
898     Smin,
899     Umax,
900     Smax,
901     Urhadd,
902     Fadd,
903     Fsub,
904     Fdiv,
905     Fmax,
906     Fmin,
907     Fmul,
908     Addp,
909     Zip1,
910     Sqrdmulh,
911 }
912 
913 /// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1125.
914 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
915 pub enum VecMisc2 {
916     Not,
917     Neg,
918     Abs,
919     Fabs,
920     Fneg,
921     Fsqrt,
922     Rev64,
923     Fcvtzs,
924     Fcvtzu,
925     Scvtf,
926     Ucvtf,
927     Frintn,
928     Frintz,
929     Frintm,
930     Frintp,
931     Cnt,
932     Cmeq0,
933 }
934 
935 /// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1164.
936 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
937 pub enum VecRRLongOp {
938     Fcvtl16,
939     Fcvtl32,
940     Shll8,
941     Shll16,
942     Shll32,
943 }
944 
945 /// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1179.
946 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
947 pub enum VecRRNarrowOp {
948     Xtn16,
949     Xtn32,
950     Xtn64,
951     Sqxtn16,
952     Sqxtn32,
953     Sqxtn64,
954     Sqxtun16,
955     Sqxtun32,
956     Sqxtun64,
957     Uqxtn16,
958     Uqxtn32,
959     Uqxtn64,
960     Fcvtn32,
961     Fcvtn64,
962 }
963 
964 /// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1211.
965 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
966 pub enum VecRRRLongOp {
967     Smull8,
968     Smull16,
969     Smull32,
970     Umull8,
971     Umull16,
972     Umull32,
973     Umlal8,
974     Umlal16,
975     Umlal32,
976 }
977 
978 /// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1228.
979 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
980 pub enum VecPairOp {
981     Addp,
982 }
983 
984 /// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1236.
985 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
986 pub enum VecRRPairLongOp {
987     Saddlp8,
988     Saddlp16,
989     Uaddlp8,
990     Uaddlp16,
991 }
992 
993 /// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1247.
994 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
995 pub enum VecLanesOp {
996     Addv,
997     Uminv,
998 }
999 
1000 /// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1256.
1001 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1002 pub enum VecShiftImmOp {
1003     Shl,
1004     Ushr,
1005     Sshr,
1006 }
1007 
1008 /// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1267.
1009 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1010 pub enum AtomicRMWOp {
1011     Add,
1012     Clr,
1013     Eor,
1014     Set,
1015     Smax,
1016     Smin,
1017     Umax,
1018     Umin,
1019 }
1020 
1021 // Generated as internal constructor for term output_reg.
1022 pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
1023     let pattern0_0 = arg0;
1024     // Rule at src/prelude.isle line 86.
1025     let expr0_0 = C::value_reg(ctx, pattern0_0);
1026     let expr1_0 = C::output(ctx, expr0_0);
1027     return Some(expr1_0);
1028 }
1029 
1030 // Generated as internal constructor for term output_value.
1031 pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> {
1032     let pattern0_0 = arg0;
1033     // Rule at src/prelude.isle line 90.
1034     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1035     let expr1_0 = C::output(ctx, expr0_0);
1036     return Some(expr1_0);
1037 }
1038 
1039 // Generated as internal constructor for term temp_reg.
1040 pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
1041     let pattern0_0 = arg0;
1042     // Rule at src/prelude.isle line 110.
1043     let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
1044     let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
1045     return Some(expr1_0);
1046 }
1047 
1048 // Generated as internal constructor for term lo_reg.
1049 pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
1050     let pattern0_0 = arg0;
1051     // Rule at src/prelude.isle line 145.
1052     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1053     let expr1_0: usize = 0;
1054     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1055     return Some(expr2_0);
1056 }
1057 
1058 // Generated as internal constructor for term side_effect.
1059 pub fn constructor_side_effect<C: Context>(
1060     ctx: &mut C,
1061     arg0: &SideEffectNoResult,
1062 ) -> Option<InstOutput> {
1063     let pattern0_0 = arg0;
1064     if let &SideEffectNoResult::Inst {
1065         inst: ref pattern1_0,
1066     } = pattern0_0
1067     {
1068         // Rule at src/prelude.isle line 398.
1069         let expr0_0 = C::emit(ctx, pattern1_0);
1070         let expr1_0 = C::output_none(ctx);
1071         return Some(expr1_0);
1072     }
1073     return None;
1074 }
1075 
1076 // Generated as internal constructor for term safepoint.
1077 pub fn constructor_safepoint<C: Context>(
1078     ctx: &mut C,
1079     arg0: &SideEffectNoResult,
1080 ) -> Option<InstOutput> {
1081     let pattern0_0 = arg0;
1082     if let &SideEffectNoResult::Inst {
1083         inst: ref pattern1_0,
1084     } = pattern0_0
1085     {
1086         // Rule at src/prelude.isle line 404.
1087         let expr0_0 = C::emit_safepoint(ctx, pattern1_0);
1088         let expr1_0 = C::output_none(ctx);
1089         return Some(expr1_0);
1090     }
1091     return None;
1092 }
1093 
1094 // Generated as internal constructor for term produces_flags_get_reg.
1095 pub fn constructor_produces_flags_get_reg<C: Context>(
1096     ctx: &mut C,
1097     arg0: &ProducesFlags,
1098 ) -> Option<Reg> {
1099     let pattern0_0 = arg0;
1100     if let &ProducesFlags::ProducesFlagsReturnsReg {
1101         inst: ref pattern1_0,
1102         result: pattern1_1,
1103     } = pattern0_0
1104     {
1105         // Rule at src/prelude.isle line 442.
1106         return Some(pattern1_1);
1107     }
1108     return None;
1109 }
1110 
1111 // Generated as internal constructor for term produces_flags_ignore.
1112 pub fn constructor_produces_flags_ignore<C: Context>(
1113     ctx: &mut C,
1114     arg0: &ProducesFlags,
1115 ) -> Option<ProducesFlags> {
1116     let pattern0_0 = arg0;
1117     match pattern0_0 {
1118         &ProducesFlags::ProducesFlagsReturnsReg {
1119             inst: ref pattern1_0,
1120             result: pattern1_1,
1121         } => {
1122             // Rule at src/prelude.isle line 447.
1123             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1124                 inst: pattern1_0.clone(),
1125             };
1126             return Some(expr0_0);
1127         }
1128         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1129             inst: ref pattern1_0,
1130             result: pattern1_1,
1131         } => {
1132             // Rule at src/prelude.isle line 449.
1133             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1134                 inst: pattern1_0.clone(),
1135             };
1136             return Some(expr0_0);
1137         }
1138         _ => {}
1139     }
1140     return None;
1141 }
1142 
1143 // Generated as internal constructor for term consumes_flags_concat.
1144 pub fn constructor_consumes_flags_concat<C: Context>(
1145     ctx: &mut C,
1146     arg0: &ConsumesFlags,
1147     arg1: &ConsumesFlags,
1148 ) -> Option<ConsumesFlags> {
1149     let pattern0_0 = arg0;
1150     if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1151         inst: ref pattern1_0,
1152         result: pattern1_1,
1153     } = pattern0_0
1154     {
1155         let pattern2_0 = arg1;
1156         if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1157             inst: ref pattern3_0,
1158             result: pattern3_1,
1159         } = pattern2_0
1160         {
1161             // Rule at src/prelude.isle line 456.
1162             let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1163             let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1164                 inst1: pattern1_0.clone(),
1165                 inst2: pattern3_0.clone(),
1166                 result: expr0_0,
1167             };
1168             return Some(expr1_0);
1169         }
1170     }
1171     return None;
1172 }
1173 
1174 // Generated as internal constructor for term with_flags.
1175 pub fn constructor_with_flags<C: Context>(
1176     ctx: &mut C,
1177     arg0: &ProducesFlags,
1178     arg1: &ConsumesFlags,
1179 ) -> Option<ValueRegs> {
1180     let pattern0_0 = arg0;
1181     match pattern0_0 {
1182         &ProducesFlags::ProducesFlagsSideEffect {
1183             inst: ref pattern1_0,
1184         } => {
1185             let pattern2_0 = arg1;
1186             match pattern2_0 {
1187                 &ConsumesFlags::ConsumesFlagsReturnsReg {
1188                     inst: ref pattern3_0,
1189                     result: pattern3_1,
1190                 } => {
1191                     // Rule at src/prelude.isle line 481.
1192                     let expr0_0 = C::emit(ctx, pattern1_0);
1193                     let expr1_0 = C::emit(ctx, pattern3_0);
1194                     let expr2_0 = C::value_reg(ctx, pattern3_1);
1195                     return Some(expr2_0);
1196                 }
1197                 &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1198                     inst1: ref pattern3_0,
1199                     inst2: ref pattern3_1,
1200                     result: pattern3_2,
1201                 } => {
1202                     // Rule at src/prelude.isle line 487.
1203                     let expr0_0 = C::emit(ctx, pattern1_0);
1204                     let expr1_0 = C::emit(ctx, pattern3_0);
1205                     let expr2_0 = C::emit(ctx, pattern3_1);
1206                     return Some(pattern3_2);
1207                 }
1208                 &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs {
1209                     inst1: ref pattern3_0,
1210                     inst2: ref pattern3_1,
1211                     inst3: ref pattern3_2,
1212                     inst4: ref pattern3_3,
1213                     result: pattern3_4,
1214                 } => {
1215                     // Rule at src/prelude.isle line 499.
1216                     let expr0_0 = C::emit(ctx, pattern1_0);
1217                     let expr1_0 = C::emit(ctx, pattern3_0);
1218                     let expr2_0 = C::emit(ctx, pattern3_1);
1219                     let expr3_0 = C::emit(ctx, pattern3_2);
1220                     let expr4_0 = C::emit(ctx, pattern3_3);
1221                     return Some(pattern3_4);
1222                 }
1223                 _ => {}
1224             }
1225         }
1226         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1227             inst: ref pattern1_0,
1228             result: pattern1_1,
1229         } => {
1230             let pattern2_0 = arg1;
1231             if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1232                 inst: ref pattern3_0,
1233                 result: pattern3_1,
1234             } = pattern2_0
1235             {
1236                 // Rule at src/prelude.isle line 475.
1237                 let expr0_0 = C::emit(ctx, pattern1_0);
1238                 let expr1_0 = C::emit(ctx, pattern3_0);
1239                 let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1240                 return Some(expr2_0);
1241             }
1242         }
1243         _ => {}
1244     }
1245     return None;
1246 }
1247 
1248 // Generated as internal constructor for term with_flags_reg.
1249 pub fn constructor_with_flags_reg<C: Context>(
1250     ctx: &mut C,
1251     arg0: &ProducesFlags,
1252     arg1: &ConsumesFlags,
1253 ) -> Option<Reg> {
1254     let pattern0_0 = arg0;
1255     let pattern1_0 = arg1;
1256     // Rule at src/prelude.isle line 516.
1257     let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?;
1258     let expr1_0: usize = 0;
1259     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1260     return Some(expr2_0);
1261 }
1262 
1263 // Generated as internal constructor for term operand_size.
1264 pub fn constructor_operand_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
1265     let pattern0_0 = arg0;
1266     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
1267         // Rule at src/isa/aarch64/inst.isle line 895.
1268         let expr0_0 = OperandSize::Size32;
1269         return Some(expr0_0);
1270     }
1271     if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
1272         // Rule at src/isa/aarch64/inst.isle line 896.
1273         let expr0_0 = OperandSize::Size64;
1274         return Some(expr0_0);
1275     }
1276     return None;
1277 }
1278 
1279 // Generated as internal constructor for term vector_size.
1280 pub fn constructor_vector_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<VectorSize> {
1281     let pattern0_0 = arg0;
1282     if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
1283         if pattern1_0 == 8 {
1284             if pattern1_1 == 16 {
1285                 // Rule at src/isa/aarch64/inst.isle line 938.
1286                 let expr0_0 = VectorSize::Size8x16;
1287                 return Some(expr0_0);
1288             }
1289         }
1290         if pattern1_0 == 16 {
1291             if pattern1_1 == 8 {
1292                 // Rule at src/isa/aarch64/inst.isle line 939.
1293                 let expr0_0 = VectorSize::Size16x8;
1294                 return Some(expr0_0);
1295             }
1296         }
1297         if pattern1_0 == 32 {
1298             if pattern1_1 == 4 {
1299                 // Rule at src/isa/aarch64/inst.isle line 940.
1300                 let expr0_0 = VectorSize::Size32x4;
1301                 return Some(expr0_0);
1302             }
1303         }
1304         if pattern1_0 == 64 {
1305             if pattern1_1 == 2 {
1306                 // Rule at src/isa/aarch64/inst.isle line 941.
1307                 let expr0_0 = VectorSize::Size64x2;
1308                 return Some(expr0_0);
1309             }
1310         }
1311     }
1312     return None;
1313 }
1314 
1315 // Generated as internal constructor for term movz.
1316 pub fn constructor_movz<C: Context>(
1317     ctx: &mut C,
1318     arg0: MoveWideConst,
1319     arg1: &OperandSize,
1320 ) -> Option<Reg> {
1321     let pattern0_0 = arg0;
1322     let pattern1_0 = arg1;
1323     // Rule at src/isa/aarch64/inst.isle line 1363.
1324     let expr0_0: Type = I64;
1325     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1326     let expr2_0 = MInst::MovZ {
1327         rd: expr1_0,
1328         imm: pattern0_0,
1329         size: pattern1_0.clone(),
1330     };
1331     let expr3_0 = C::emit(ctx, &expr2_0);
1332     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1333     return Some(expr4_0);
1334 }
1335 
1336 // Generated as internal constructor for term movn.
1337 pub fn constructor_movn<C: Context>(
1338     ctx: &mut C,
1339     arg0: MoveWideConst,
1340     arg1: &OperandSize,
1341 ) -> Option<Reg> {
1342     let pattern0_0 = arg0;
1343     let pattern1_0 = arg1;
1344     // Rule at src/isa/aarch64/inst.isle line 1370.
1345     let expr0_0: Type = I64;
1346     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1347     let expr2_0 = MInst::MovN {
1348         rd: expr1_0,
1349         imm: pattern0_0,
1350         size: pattern1_0.clone(),
1351     };
1352     let expr3_0 = C::emit(ctx, &expr2_0);
1353     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1354     return Some(expr4_0);
1355 }
1356 
1357 // Generated as internal constructor for term alu_rr_imm_logic.
1358 pub fn constructor_alu_rr_imm_logic<C: Context>(
1359     ctx: &mut C,
1360     arg0: &ALUOp,
1361     arg1: Type,
1362     arg2: Reg,
1363     arg3: ImmLogic,
1364 ) -> Option<Reg> {
1365     let pattern0_0 = arg0;
1366     let pattern1_0 = arg1;
1367     let pattern2_0 = arg2;
1368     let pattern3_0 = arg3;
1369     // Rule at src/isa/aarch64/inst.isle line 1377.
1370     let expr0_0: Type = I64;
1371     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1372     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1373     let expr3_0 = MInst::AluRRImmLogic {
1374         alu_op: pattern0_0.clone(),
1375         size: expr2_0,
1376         rd: expr1_0,
1377         rn: pattern2_0,
1378         imml: pattern3_0,
1379     };
1380     let expr4_0 = C::emit(ctx, &expr3_0);
1381     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1382     return Some(expr5_0);
1383 }
1384 
1385 // Generated as internal constructor for term alu_rr_imm_shift.
1386 pub fn constructor_alu_rr_imm_shift<C: Context>(
1387     ctx: &mut C,
1388     arg0: &ALUOp,
1389     arg1: Type,
1390     arg2: Reg,
1391     arg3: ImmShift,
1392 ) -> Option<Reg> {
1393     let pattern0_0 = arg0;
1394     let pattern1_0 = arg1;
1395     let pattern2_0 = arg2;
1396     let pattern3_0 = arg3;
1397     // Rule at src/isa/aarch64/inst.isle line 1384.
1398     let expr0_0: Type = I64;
1399     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1400     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1401     let expr3_0 = MInst::AluRRImmShift {
1402         alu_op: pattern0_0.clone(),
1403         size: expr2_0,
1404         rd: expr1_0,
1405         rn: pattern2_0,
1406         immshift: pattern3_0,
1407     };
1408     let expr4_0 = C::emit(ctx, &expr3_0);
1409     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1410     return Some(expr5_0);
1411 }
1412 
1413 // Generated as internal constructor for term alu_rrr.
1414 pub fn constructor_alu_rrr<C: Context>(
1415     ctx: &mut C,
1416     arg0: &ALUOp,
1417     arg1: Type,
1418     arg2: Reg,
1419     arg3: Reg,
1420 ) -> Option<Reg> {
1421     let pattern0_0 = arg0;
1422     let pattern1_0 = arg1;
1423     let pattern2_0 = arg2;
1424     let pattern3_0 = arg3;
1425     // Rule at src/isa/aarch64/inst.isle line 1391.
1426     let expr0_0: Type = I64;
1427     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1428     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1429     let expr3_0 = MInst::AluRRR {
1430         alu_op: pattern0_0.clone(),
1431         size: expr2_0,
1432         rd: expr1_0,
1433         rn: pattern2_0,
1434         rm: pattern3_0,
1435     };
1436     let expr4_0 = C::emit(ctx, &expr3_0);
1437     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1438     return Some(expr5_0);
1439 }
1440 
1441 // Generated as internal constructor for term vec_rrr.
1442 pub fn constructor_vec_rrr<C: Context>(
1443     ctx: &mut C,
1444     arg0: &VecALUOp,
1445     arg1: Reg,
1446     arg2: Reg,
1447     arg3: &VectorSize,
1448 ) -> Option<Reg> {
1449     let pattern0_0 = arg0;
1450     let pattern1_0 = arg1;
1451     let pattern2_0 = arg2;
1452     let pattern3_0 = arg3;
1453     // Rule at src/isa/aarch64/inst.isle line 1398.
1454     let expr0_0: Type = I8X16;
1455     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1456     let expr2_0 = MInst::VecRRR {
1457         alu_op: pattern0_0.clone(),
1458         rd: expr1_0,
1459         rn: pattern1_0,
1460         rm: pattern2_0,
1461         size: pattern3_0.clone(),
1462     };
1463     let expr3_0 = C::emit(ctx, &expr2_0);
1464     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1465     return Some(expr4_0);
1466 }
1467 
1468 // Generated as internal constructor for term vec_lanes.
1469 pub fn constructor_vec_lanes<C: Context>(
1470     ctx: &mut C,
1471     arg0: &VecLanesOp,
1472     arg1: Reg,
1473     arg2: &VectorSize,
1474 ) -> Option<Reg> {
1475     let pattern0_0 = arg0;
1476     let pattern1_0 = arg1;
1477     let pattern2_0 = arg2;
1478     // Rule at src/isa/aarch64/inst.isle line 1405.
1479     let expr0_0: Type = I8X16;
1480     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1481     let expr2_0 = MInst::VecLanes {
1482         op: pattern0_0.clone(),
1483         rd: expr1_0,
1484         rn: pattern1_0,
1485         size: pattern2_0.clone(),
1486     };
1487     let expr3_0 = C::emit(ctx, &expr2_0);
1488     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1489     return Some(expr4_0);
1490 }
1491 
1492 // Generated as internal constructor for term vec_dup.
1493 pub fn constructor_vec_dup<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
1494     let pattern0_0 = arg0;
1495     let pattern1_0 = arg1;
1496     // Rule at src/isa/aarch64/inst.isle line 1412.
1497     let expr0_0: Type = I8X16;
1498     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1499     let expr2_0 = MInst::VecDup {
1500         rd: expr1_0,
1501         rn: pattern0_0,
1502         size: pattern1_0.clone(),
1503     };
1504     let expr3_0 = C::emit(ctx, &expr2_0);
1505     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1506     return Some(expr4_0);
1507 }
1508 
1509 // Generated as internal constructor for term alu_rr_imm12.
1510 pub fn constructor_alu_rr_imm12<C: Context>(
1511     ctx: &mut C,
1512     arg0: &ALUOp,
1513     arg1: Type,
1514     arg2: Reg,
1515     arg3: Imm12,
1516 ) -> Option<Reg> {
1517     let pattern0_0 = arg0;
1518     let pattern1_0 = arg1;
1519     let pattern2_0 = arg2;
1520     let pattern3_0 = arg3;
1521     // Rule at src/isa/aarch64/inst.isle line 1419.
1522     let expr0_0: Type = I64;
1523     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1524     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1525     let expr3_0 = MInst::AluRRImm12 {
1526         alu_op: pattern0_0.clone(),
1527         size: expr2_0,
1528         rd: expr1_0,
1529         rn: pattern2_0,
1530         imm12: pattern3_0,
1531     };
1532     let expr4_0 = C::emit(ctx, &expr3_0);
1533     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1534     return Some(expr5_0);
1535 }
1536 
1537 // Generated as internal constructor for term alu_rrr_shift.
1538 pub fn constructor_alu_rrr_shift<C: Context>(
1539     ctx: &mut C,
1540     arg0: &ALUOp,
1541     arg1: Type,
1542     arg2: Reg,
1543     arg3: Reg,
1544     arg4: ShiftOpAndAmt,
1545 ) -> Option<Reg> {
1546     let pattern0_0 = arg0;
1547     let pattern1_0 = arg1;
1548     let pattern2_0 = arg2;
1549     let pattern3_0 = arg3;
1550     let pattern4_0 = arg4;
1551     // Rule at src/isa/aarch64/inst.isle line 1426.
1552     let expr0_0: Type = I64;
1553     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1554     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1555     let expr3_0 = MInst::AluRRRShift {
1556         alu_op: pattern0_0.clone(),
1557         size: expr2_0,
1558         rd: expr1_0,
1559         rn: pattern2_0,
1560         rm: pattern3_0,
1561         shiftop: pattern4_0,
1562     };
1563     let expr4_0 = C::emit(ctx, &expr3_0);
1564     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1565     return Some(expr5_0);
1566 }
1567 
1568 // Generated as internal constructor for term alu_rrr_extend.
1569 pub fn constructor_alu_rrr_extend<C: Context>(
1570     ctx: &mut C,
1571     arg0: &ALUOp,
1572     arg1: Type,
1573     arg2: Reg,
1574     arg3: Reg,
1575     arg4: &ExtendOp,
1576 ) -> Option<Reg> {
1577     let pattern0_0 = arg0;
1578     let pattern1_0 = arg1;
1579     let pattern2_0 = arg2;
1580     let pattern3_0 = arg3;
1581     let pattern4_0 = arg4;
1582     // Rule at src/isa/aarch64/inst.isle line 1433.
1583     let expr0_0: Type = I64;
1584     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1585     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1586     let expr3_0 = MInst::AluRRRExtend {
1587         alu_op: pattern0_0.clone(),
1588         size: expr2_0,
1589         rd: expr1_0,
1590         rn: pattern2_0,
1591         rm: pattern3_0,
1592         extendop: pattern4_0.clone(),
1593     };
1594     let expr4_0 = C::emit(ctx, &expr3_0);
1595     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1596     return Some(expr5_0);
1597 }
1598 
1599 // Generated as internal constructor for term alu_rr_extend_reg.
1600 pub fn constructor_alu_rr_extend_reg<C: Context>(
1601     ctx: &mut C,
1602     arg0: &ALUOp,
1603     arg1: Type,
1604     arg2: Reg,
1605     arg3: &ExtendedValue,
1606 ) -> Option<Reg> {
1607     let pattern0_0 = arg0;
1608     let pattern1_0 = arg1;
1609     let pattern2_0 = arg2;
1610     let pattern3_0 = arg3;
1611     // Rule at src/isa/aarch64/inst.isle line 1441.
1612     let expr0_0 = C::put_extended_in_reg(ctx, pattern3_0);
1613     let expr1_0 = C::get_extended_op(ctx, pattern3_0);
1614     let expr2_0 =
1615         constructor_alu_rrr_extend(ctx, pattern0_0, pattern1_0, pattern2_0, expr0_0, &expr1_0)?;
1616     return Some(expr2_0);
1617 }
1618 
1619 // Generated as internal constructor for term alu_rrrr.
1620 pub fn constructor_alu_rrrr<C: Context>(
1621     ctx: &mut C,
1622     arg0: &ALUOp3,
1623     arg1: Reg,
1624     arg2: Reg,
1625     arg3: Reg,
1626 ) -> Option<Reg> {
1627     let pattern0_0 = arg0;
1628     let pattern1_0 = arg1;
1629     let pattern2_0 = arg2;
1630     let pattern3_0 = arg3;
1631     // Rule at src/isa/aarch64/inst.isle line 1448.
1632     let expr0_0: Type = I64;
1633     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1634     let expr2_0 = MInst::AluRRRR {
1635         alu_op: pattern0_0.clone(),
1636         rd: expr1_0,
1637         rn: pattern1_0,
1638         rm: pattern2_0,
1639         ra: pattern3_0,
1640     };
1641     let expr3_0 = C::emit(ctx, &expr2_0);
1642     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1643     return Some(expr4_0);
1644 }
1645 
1646 // Generated as internal constructor for term bit_rr.
1647 pub fn constructor_bit_rr<C: Context>(
1648     ctx: &mut C,
1649     arg0: &BitOp,
1650     arg1: Type,
1651     arg2: Reg,
1652 ) -> Option<Reg> {
1653     let pattern0_0 = arg0;
1654     let pattern1_0 = arg1;
1655     let pattern2_0 = arg2;
1656     // Rule at src/isa/aarch64/inst.isle line 1455.
1657     let expr0_0: Type = I64;
1658     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1659     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1660     let expr3_0 = MInst::BitRR {
1661         op: pattern0_0.clone(),
1662         size: expr2_0,
1663         rd: expr1_0,
1664         rn: pattern2_0,
1665     };
1666     let expr4_0 = C::emit(ctx, &expr3_0);
1667     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1668     return Some(expr5_0);
1669 }
1670 
1671 // Generated as internal constructor for term add_with_flags_paired.
1672 pub fn constructor_add_with_flags_paired<C: Context>(
1673     ctx: &mut C,
1674     arg0: Type,
1675     arg1: Reg,
1676     arg2: Reg,
1677 ) -> Option<ProducesFlags> {
1678     let pattern0_0 = arg0;
1679     let pattern1_0 = arg1;
1680     let pattern2_0 = arg2;
1681     // Rule at src/isa/aarch64/inst.isle line 1462.
1682     let expr0_0: Type = I64;
1683     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1684     let expr2_0 = ALUOp::AddS;
1685     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1686     let expr4_0 = MInst::AluRRR {
1687         alu_op: expr2_0,
1688         size: expr3_0,
1689         rd: expr1_0,
1690         rn: pattern1_0,
1691         rm: pattern2_0,
1692     };
1693     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1694     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1695         inst: expr4_0,
1696         result: expr5_0,
1697     };
1698     return Some(expr6_0);
1699 }
1700 
1701 // Generated as internal constructor for term adc_paired.
1702 pub fn constructor_adc_paired<C: Context>(
1703     ctx: &mut C,
1704     arg0: Type,
1705     arg1: Reg,
1706     arg2: Reg,
1707 ) -> Option<ConsumesFlags> {
1708     let pattern0_0 = arg0;
1709     let pattern1_0 = arg1;
1710     let pattern2_0 = arg2;
1711     // Rule at src/isa/aarch64/inst.isle line 1470.
1712     let expr0_0: Type = I64;
1713     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1714     let expr2_0 = ALUOp::Adc;
1715     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1716     let expr4_0 = MInst::AluRRR {
1717         alu_op: expr2_0,
1718         size: expr3_0,
1719         rd: expr1_0,
1720         rn: pattern1_0,
1721         rm: pattern2_0,
1722     };
1723     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1724     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1725         inst: expr4_0,
1726         result: expr5_0,
1727     };
1728     return Some(expr6_0);
1729 }
1730 
1731 // Generated as internal constructor for term sub_with_flags_paired.
1732 pub fn constructor_sub_with_flags_paired<C: Context>(
1733     ctx: &mut C,
1734     arg0: Type,
1735     arg1: Reg,
1736     arg2: Reg,
1737 ) -> Option<ProducesFlags> {
1738     let pattern0_0 = arg0;
1739     let pattern1_0 = arg1;
1740     let pattern2_0 = arg2;
1741     // Rule at src/isa/aarch64/inst.isle line 1478.
1742     let expr0_0: Type = I64;
1743     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1744     let expr2_0 = ALUOp::SubS;
1745     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1746     let expr4_0 = MInst::AluRRR {
1747         alu_op: expr2_0,
1748         size: expr3_0,
1749         rd: expr1_0,
1750         rn: pattern1_0,
1751         rm: pattern2_0,
1752     };
1753     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1754     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1755         inst: expr4_0,
1756         result: expr5_0,
1757     };
1758     return Some(expr6_0);
1759 }
1760 
1761 // Generated as internal constructor for term cmp64_imm.
1762 pub fn constructor_cmp64_imm<C: Context>(
1763     ctx: &mut C,
1764     arg0: Reg,
1765     arg1: Imm12,
1766 ) -> Option<ProducesFlags> {
1767     let pattern0_0 = arg0;
1768     let pattern1_0 = arg1;
1769     // Rule at src/isa/aarch64/inst.isle line 1485.
1770     let expr0_0 = ALUOp::SubS;
1771     let expr1_0 = OperandSize::Size64;
1772     let expr2_0 = C::writable_zero_reg(ctx);
1773     let expr3_0 = MInst::AluRRImm12 {
1774         alu_op: expr0_0,
1775         size: expr1_0,
1776         rd: expr2_0,
1777         rn: pattern0_0,
1778         imm12: pattern1_0,
1779     };
1780     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
1781     return Some(expr4_0);
1782 }
1783 
1784 // Generated as internal constructor for term sbc_paired.
1785 pub fn constructor_sbc_paired<C: Context>(
1786     ctx: &mut C,
1787     arg0: Type,
1788     arg1: Reg,
1789     arg2: Reg,
1790 ) -> Option<ConsumesFlags> {
1791     let pattern0_0 = arg0;
1792     let pattern1_0 = arg1;
1793     let pattern2_0 = arg2;
1794     // Rule at src/isa/aarch64/inst.isle line 1492.
1795     let expr0_0: Type = I64;
1796     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1797     let expr2_0 = ALUOp::Sbc;
1798     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1799     let expr4_0 = MInst::AluRRR {
1800         alu_op: expr2_0,
1801         size: expr3_0,
1802         rd: expr1_0,
1803         rn: pattern1_0,
1804         rm: pattern2_0,
1805     };
1806     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1807     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1808         inst: expr4_0,
1809         result: expr5_0,
1810     };
1811     return Some(expr6_0);
1812 }
1813 
1814 // Generated as internal constructor for term vec_misc.
1815 pub fn constructor_vec_misc<C: Context>(
1816     ctx: &mut C,
1817     arg0: &VecMisc2,
1818     arg1: Reg,
1819     arg2: &VectorSize,
1820 ) -> Option<Reg> {
1821     let pattern0_0 = arg0;
1822     let pattern1_0 = arg1;
1823     let pattern2_0 = arg2;
1824     // Rule at src/isa/aarch64/inst.isle line 1500.
1825     let expr0_0: Type = I8X16;
1826     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1827     let expr2_0 = MInst::VecMisc {
1828         op: pattern0_0.clone(),
1829         rd: expr1_0,
1830         rn: pattern1_0,
1831         size: pattern2_0.clone(),
1832     };
1833     let expr3_0 = C::emit(ctx, &expr2_0);
1834     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1835     return Some(expr4_0);
1836 }
1837 
1838 // Generated as internal constructor for term vec_rrr_long.
1839 pub fn constructor_vec_rrr_long<C: Context>(
1840     ctx: &mut C,
1841     arg0: &VecRRRLongOp,
1842     arg1: Reg,
1843     arg2: Reg,
1844     arg3: bool,
1845 ) -> Option<Reg> {
1846     let pattern0_0 = arg0;
1847     let pattern1_0 = arg1;
1848     let pattern2_0 = arg2;
1849     let pattern3_0 = arg3;
1850     // Rule at src/isa/aarch64/inst.isle line 1507.
1851     let expr0_0: Type = I8X16;
1852     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1853     let expr2_0 = MInst::VecRRRLong {
1854         alu_op: pattern0_0.clone(),
1855         rd: expr1_0,
1856         rn: pattern1_0,
1857         rm: pattern2_0,
1858         high_half: pattern3_0,
1859     };
1860     let expr3_0 = C::emit(ctx, &expr2_0);
1861     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1862     return Some(expr4_0);
1863 }
1864 
1865 // Generated as internal constructor for term vec_rrrr_long.
1866 pub fn constructor_vec_rrrr_long<C: Context>(
1867     ctx: &mut C,
1868     arg0: &VecRRRLongOp,
1869     arg1: Reg,
1870     arg2: Reg,
1871     arg3: Reg,
1872     arg4: bool,
1873 ) -> Option<Reg> {
1874     let pattern0_0 = arg0;
1875     let pattern1_0 = arg1;
1876     let pattern2_0 = arg2;
1877     let pattern3_0 = arg3;
1878     let pattern4_0 = arg4;
1879     // Rule at src/isa/aarch64/inst.isle line 1517.
1880     let expr0_0: Type = I8X16;
1881     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1882     let expr2_0 = MInst::FpuMove128 {
1883         rd: expr1_0,
1884         rn: pattern1_0,
1885     };
1886     let expr3_0 = C::emit(ctx, &expr2_0);
1887     let expr4_0 = MInst::VecRRRLong {
1888         alu_op: pattern0_0.clone(),
1889         rd: expr1_0,
1890         rn: pattern2_0,
1891         rm: pattern3_0,
1892         high_half: pattern4_0,
1893     };
1894     let expr5_0 = C::emit(ctx, &expr4_0);
1895     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1896     return Some(expr6_0);
1897 }
1898 
1899 // Generated as internal constructor for term vec_rr_narrow.
1900 pub fn constructor_vec_rr_narrow<C: Context>(
1901     ctx: &mut C,
1902     arg0: &VecRRNarrowOp,
1903     arg1: Reg,
1904     arg2: bool,
1905 ) -> Option<Reg> {
1906     let pattern0_0 = arg0;
1907     let pattern1_0 = arg1;
1908     let pattern2_0 = arg2;
1909     // Rule at src/isa/aarch64/inst.isle line 1525.
1910     let expr0_0: Type = I8X16;
1911     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1912     let expr2_0 = MInst::VecRRNarrow {
1913         op: pattern0_0.clone(),
1914         rd: expr1_0,
1915         rn: pattern1_0,
1916         high_half: pattern2_0,
1917     };
1918     let expr3_0 = C::emit(ctx, &expr2_0);
1919     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1920     return Some(expr4_0);
1921 }
1922 
1923 // Generated as internal constructor for term vec_rr_long.
1924 pub fn constructor_vec_rr_long<C: Context>(
1925     ctx: &mut C,
1926     arg0: &VecRRLongOp,
1927     arg1: Reg,
1928     arg2: bool,
1929 ) -> Option<Reg> {
1930     let pattern0_0 = arg0;
1931     let pattern1_0 = arg1;
1932     let pattern2_0 = arg2;
1933     // Rule at src/isa/aarch64/inst.isle line 1532.
1934     let expr0_0: Type = I8X16;
1935     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1936     let expr2_0 = MInst::VecRRLong {
1937         op: pattern0_0.clone(),
1938         rd: expr1_0,
1939         rn: pattern1_0,
1940         high_half: pattern2_0,
1941     };
1942     let expr3_0 = C::emit(ctx, &expr2_0);
1943     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1944     return Some(expr4_0);
1945 }
1946 
1947 // Generated as internal constructor for term mov_to_fpu.
1948 pub fn constructor_mov_to_fpu<C: Context>(
1949     ctx: &mut C,
1950     arg0: Reg,
1951     arg1: &ScalarSize,
1952 ) -> Option<Reg> {
1953     let pattern0_0 = arg0;
1954     let pattern1_0 = arg1;
1955     // Rule at src/isa/aarch64/inst.isle line 1539.
1956     let expr0_0: Type = I8X16;
1957     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1958     let expr2_0 = MInst::MovToFpu {
1959         rd: expr1_0,
1960         rn: pattern0_0,
1961         size: pattern1_0.clone(),
1962     };
1963     let expr3_0 = C::emit(ctx, &expr2_0);
1964     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1965     return Some(expr4_0);
1966 }
1967 
1968 // Generated as internal constructor for term mov_to_vec.
1969 pub fn constructor_mov_to_vec<C: Context>(
1970     ctx: &mut C,
1971     arg0: Reg,
1972     arg1: Reg,
1973     arg2: u8,
1974     arg3: &VectorSize,
1975 ) -> Option<Reg> {
1976     let pattern0_0 = arg0;
1977     let pattern1_0 = arg1;
1978     let pattern2_0 = arg2;
1979     let pattern3_0 = arg3;
1980     // Rule at src/isa/aarch64/inst.isle line 1546.
1981     let expr0_0: Type = I8X16;
1982     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1983     let expr2_0 = MInst::FpuMove128 {
1984         rd: expr1_0,
1985         rn: pattern0_0,
1986     };
1987     let expr3_0 = C::emit(ctx, &expr2_0);
1988     let expr4_0 = MInst::MovToVec {
1989         rd: expr1_0,
1990         rn: pattern1_0,
1991         idx: pattern2_0,
1992         size: pattern3_0.clone(),
1993     };
1994     let expr5_0 = C::emit(ctx, &expr4_0);
1995     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1996     return Some(expr6_0);
1997 }
1998 
1999 // Generated as internal constructor for term mov_from_vec.
2000 pub fn constructor_mov_from_vec<C: Context>(
2001     ctx: &mut C,
2002     arg0: Reg,
2003     arg1: u8,
2004     arg2: &VectorSize,
2005 ) -> Option<Reg> {
2006     let pattern0_0 = arg0;
2007     let pattern1_0 = arg1;
2008     let pattern2_0 = arg2;
2009     // Rule at src/isa/aarch64/inst.isle line 1554.
2010     let expr0_0: Type = I64;
2011     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2012     let expr2_0 = MInst::MovFromVec {
2013         rd: expr1_0,
2014         rn: pattern0_0,
2015         idx: pattern1_0,
2016         size: pattern2_0.clone(),
2017     };
2018     let expr3_0 = C::emit(ctx, &expr2_0);
2019     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2020     return Some(expr4_0);
2021 }
2022 
2023 // Generated as internal constructor for term mov_from_vec_signed.
2024 pub fn constructor_mov_from_vec_signed<C: Context>(
2025     ctx: &mut C,
2026     arg0: Reg,
2027     arg1: u8,
2028     arg2: &VectorSize,
2029     arg3: &OperandSize,
2030 ) -> Option<Reg> {
2031     let pattern0_0 = arg0;
2032     let pattern1_0 = arg1;
2033     let pattern2_0 = arg2;
2034     let pattern3_0 = arg3;
2035     // Rule at src/isa/aarch64/inst.isle line 1561.
2036     let expr0_0: Type = I64;
2037     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2038     let expr2_0 = MInst::MovFromVecSigned {
2039         rd: expr1_0,
2040         rn: pattern0_0,
2041         idx: pattern1_0,
2042         size: pattern2_0.clone(),
2043         scalar_size: pattern3_0.clone(),
2044     };
2045     let expr3_0 = C::emit(ctx, &expr2_0);
2046     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2047     return Some(expr4_0);
2048 }
2049 
2050 // Generated as internal constructor for term extend.
2051 pub fn constructor_extend<C: Context>(
2052     ctx: &mut C,
2053     arg0: Reg,
2054     arg1: bool,
2055     arg2: u8,
2056     arg3: u8,
2057 ) -> Option<Reg> {
2058     let pattern0_0 = arg0;
2059     let pattern1_0 = arg1;
2060     let pattern2_0 = arg2;
2061     let pattern3_0 = arg3;
2062     // Rule at src/isa/aarch64/inst.isle line 1568.
2063     let expr0_0: Type = I64;
2064     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2065     let expr2_0 = MInst::Extend {
2066         rd: expr1_0,
2067         rn: pattern0_0,
2068         signed: pattern1_0,
2069         from_bits: pattern2_0,
2070         to_bits: pattern3_0,
2071     };
2072     let expr3_0 = C::emit(ctx, &expr2_0);
2073     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2074     return Some(expr4_0);
2075 }
2076 
2077 // Generated as internal constructor for term load_acquire.
2078 pub fn constructor_load_acquire<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2079     let pattern0_0 = arg0;
2080     let pattern1_0 = arg1;
2081     // Rule at src/isa/aarch64/inst.isle line 1575.
2082     let expr0_0: Type = I64;
2083     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2084     let expr2_0 = MInst::LoadAcquire {
2085         access_ty: pattern0_0,
2086         rt: expr1_0,
2087         rn: pattern1_0,
2088     };
2089     let expr3_0 = C::emit(ctx, &expr2_0);
2090     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2091     return Some(expr4_0);
2092 }
2093 
2094 // Generated as internal constructor for term tst_imm.
2095 pub fn constructor_tst_imm<C: Context>(
2096     ctx: &mut C,
2097     arg0: Type,
2098     arg1: Reg,
2099     arg2: ImmLogic,
2100 ) -> Option<ProducesFlags> {
2101     let pattern0_0 = arg0;
2102     let pattern1_0 = arg1;
2103     let pattern2_0 = arg2;
2104     // Rule at src/isa/aarch64/inst.isle line 1585.
2105     let expr0_0 = ALUOp::AndS;
2106     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
2107     let expr2_0 = C::writable_zero_reg(ctx);
2108     let expr3_0 = MInst::AluRRImmLogic {
2109         alu_op: expr0_0,
2110         size: expr1_0,
2111         rd: expr2_0,
2112         rn: pattern1_0,
2113         imml: pattern2_0,
2114     };
2115     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
2116     return Some(expr4_0);
2117 }
2118 
2119 // Generated as internal constructor for term csel.
2120 pub fn constructor_csel<C: Context>(
2121     ctx: &mut C,
2122     arg0: &Cond,
2123     arg1: Reg,
2124     arg2: Reg,
2125 ) -> Option<ConsumesFlags> {
2126     let pattern0_0 = arg0;
2127     let pattern1_0 = arg1;
2128     let pattern2_0 = arg2;
2129     // Rule at src/isa/aarch64/inst.isle line 1599.
2130     let expr0_0: Type = I64;
2131     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2132     let expr2_0 = MInst::CSel {
2133         rd: expr1_0,
2134         cond: pattern0_0.clone(),
2135         rn: pattern1_0,
2136         rm: pattern2_0,
2137     };
2138     let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
2139     let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
2140         inst: expr2_0,
2141         result: expr3_0,
2142     };
2143     return Some(expr4_0);
2144 }
2145 
2146 // Generated as internal constructor for term add.
2147 pub fn constructor_add<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2148     let pattern0_0 = arg0;
2149     let pattern1_0 = arg1;
2150     let pattern2_0 = arg2;
2151     // Rule at src/isa/aarch64/inst.isle line 1608.
2152     let expr0_0 = ALUOp::Add;
2153     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2154     return Some(expr1_0);
2155 }
2156 
2157 // Generated as internal constructor for term add_imm.
2158 pub fn constructor_add_imm<C: Context>(
2159     ctx: &mut C,
2160     arg0: Type,
2161     arg1: Reg,
2162     arg2: Imm12,
2163 ) -> Option<Reg> {
2164     let pattern0_0 = arg0;
2165     let pattern1_0 = arg1;
2166     let pattern2_0 = arg2;
2167     // Rule at src/isa/aarch64/inst.isle line 1611.
2168     let expr0_0 = ALUOp::Add;
2169     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2170     return Some(expr1_0);
2171 }
2172 
2173 // Generated as internal constructor for term add_extend.
2174 pub fn constructor_add_extend<C: Context>(
2175     ctx: &mut C,
2176     arg0: Type,
2177     arg1: Reg,
2178     arg2: &ExtendedValue,
2179 ) -> Option<Reg> {
2180     let pattern0_0 = arg0;
2181     let pattern1_0 = arg1;
2182     let pattern2_0 = arg2;
2183     // Rule at src/isa/aarch64/inst.isle line 1614.
2184     let expr0_0 = ALUOp::Add;
2185     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2186     return Some(expr1_0);
2187 }
2188 
2189 // Generated as internal constructor for term add_shift.
2190 pub fn constructor_add_shift<C: Context>(
2191     ctx: &mut C,
2192     arg0: Type,
2193     arg1: Reg,
2194     arg2: Reg,
2195     arg3: ShiftOpAndAmt,
2196 ) -> Option<Reg> {
2197     let pattern0_0 = arg0;
2198     let pattern1_0 = arg1;
2199     let pattern2_0 = arg2;
2200     let pattern3_0 = arg3;
2201     // Rule at src/isa/aarch64/inst.isle line 1617.
2202     let expr0_0 = ALUOp::Add;
2203     let expr1_0 = constructor_alu_rrr_shift(
2204         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2205     )?;
2206     return Some(expr1_0);
2207 }
2208 
2209 // Generated as internal constructor for term add_vec.
2210 pub fn constructor_add_vec<C: Context>(
2211     ctx: &mut C,
2212     arg0: Reg,
2213     arg1: Reg,
2214     arg2: &VectorSize,
2215 ) -> Option<Reg> {
2216     let pattern0_0 = arg0;
2217     let pattern1_0 = arg1;
2218     let pattern2_0 = arg2;
2219     // Rule at src/isa/aarch64/inst.isle line 1620.
2220     let expr0_0 = VecALUOp::Add;
2221     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2222     return Some(expr1_0);
2223 }
2224 
2225 // Generated as internal constructor for term sub.
2226 pub fn constructor_sub<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2227     let pattern0_0 = arg0;
2228     let pattern1_0 = arg1;
2229     let pattern2_0 = arg2;
2230     // Rule at src/isa/aarch64/inst.isle line 1625.
2231     let expr0_0 = ALUOp::Sub;
2232     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2233     return Some(expr1_0);
2234 }
2235 
2236 // Generated as internal constructor for term sub_imm.
2237 pub fn constructor_sub_imm<C: Context>(
2238     ctx: &mut C,
2239     arg0: Type,
2240     arg1: Reg,
2241     arg2: Imm12,
2242 ) -> Option<Reg> {
2243     let pattern0_0 = arg0;
2244     let pattern1_0 = arg1;
2245     let pattern2_0 = arg2;
2246     // Rule at src/isa/aarch64/inst.isle line 1628.
2247     let expr0_0 = ALUOp::Sub;
2248     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2249     return Some(expr1_0);
2250 }
2251 
2252 // Generated as internal constructor for term sub_extend.
2253 pub fn constructor_sub_extend<C: Context>(
2254     ctx: &mut C,
2255     arg0: Type,
2256     arg1: Reg,
2257     arg2: &ExtendedValue,
2258 ) -> Option<Reg> {
2259     let pattern0_0 = arg0;
2260     let pattern1_0 = arg1;
2261     let pattern2_0 = arg2;
2262     // Rule at src/isa/aarch64/inst.isle line 1631.
2263     let expr0_0 = ALUOp::Sub;
2264     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2265     return Some(expr1_0);
2266 }
2267 
2268 // Generated as internal constructor for term sub_shift.
2269 pub fn constructor_sub_shift<C: Context>(
2270     ctx: &mut C,
2271     arg0: Type,
2272     arg1: Reg,
2273     arg2: Reg,
2274     arg3: ShiftOpAndAmt,
2275 ) -> Option<Reg> {
2276     let pattern0_0 = arg0;
2277     let pattern1_0 = arg1;
2278     let pattern2_0 = arg2;
2279     let pattern3_0 = arg3;
2280     // Rule at src/isa/aarch64/inst.isle line 1634.
2281     let expr0_0 = ALUOp::Sub;
2282     let expr1_0 = constructor_alu_rrr_shift(
2283         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2284     )?;
2285     return Some(expr1_0);
2286 }
2287 
2288 // Generated as internal constructor for term sub_vec.
2289 pub fn constructor_sub_vec<C: Context>(
2290     ctx: &mut C,
2291     arg0: Reg,
2292     arg1: Reg,
2293     arg2: &VectorSize,
2294 ) -> Option<Reg> {
2295     let pattern0_0 = arg0;
2296     let pattern1_0 = arg1;
2297     let pattern2_0 = arg2;
2298     // Rule at src/isa/aarch64/inst.isle line 1637.
2299     let expr0_0 = VecALUOp::Sub;
2300     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2301     return Some(expr1_0);
2302 }
2303 
2304 // Generated as internal constructor for term madd.
2305 pub fn constructor_madd<C: Context>(
2306     ctx: &mut C,
2307     arg0: Type,
2308     arg1: Reg,
2309     arg2: Reg,
2310     arg3: Reg,
2311 ) -> Option<Reg> {
2312     let pattern0_0 = arg0;
2313     if pattern0_0 == I64 {
2314         let pattern2_0 = arg1;
2315         let pattern3_0 = arg2;
2316         let pattern4_0 = arg3;
2317         // Rule at src/isa/aarch64/inst.isle line 1643.
2318         let expr0_0 = constructor_madd64(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2319         return Some(expr0_0);
2320     }
2321     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2322         let pattern2_0 = arg1;
2323         let pattern3_0 = arg2;
2324         let pattern4_0 = arg3;
2325         // Rule at src/isa/aarch64/inst.isle line 1642.
2326         let expr0_0 = constructor_madd32(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2327         return Some(expr0_0);
2328     }
2329     return None;
2330 }
2331 
2332 // Generated as internal constructor for term madd32.
2333 pub fn constructor_madd32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2334     let pattern0_0 = arg0;
2335     let pattern1_0 = arg1;
2336     let pattern2_0 = arg2;
2337     // Rule at src/isa/aarch64/inst.isle line 1646.
2338     let expr0_0 = ALUOp3::MAdd32;
2339     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2340     return Some(expr1_0);
2341 }
2342 
2343 // Generated as internal constructor for term madd64.
2344 pub fn constructor_madd64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2345     let pattern0_0 = arg0;
2346     let pattern1_0 = arg1;
2347     let pattern2_0 = arg2;
2348     // Rule at src/isa/aarch64/inst.isle line 1649.
2349     let expr0_0 = ALUOp3::MAdd64;
2350     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2351     return Some(expr1_0);
2352 }
2353 
2354 // Generated as internal constructor for term msub64.
2355 pub fn constructor_msub64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2356     let pattern0_0 = arg0;
2357     let pattern1_0 = arg1;
2358     let pattern2_0 = arg2;
2359     // Rule at src/isa/aarch64/inst.isle line 1654.
2360     let expr0_0 = ALUOp3::MSub64;
2361     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2362     return Some(expr1_0);
2363 }
2364 
2365 // Generated as internal constructor for term uqadd.
2366 pub fn constructor_uqadd<C: Context>(
2367     ctx: &mut C,
2368     arg0: Reg,
2369     arg1: Reg,
2370     arg2: &VectorSize,
2371 ) -> Option<Reg> {
2372     let pattern0_0 = arg0;
2373     let pattern1_0 = arg1;
2374     let pattern2_0 = arg2;
2375     // Rule at src/isa/aarch64/inst.isle line 1658.
2376     let expr0_0 = VecALUOp::Uqadd;
2377     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2378     return Some(expr1_0);
2379 }
2380 
2381 // Generated as internal constructor for term sqadd.
2382 pub fn constructor_sqadd<C: Context>(
2383     ctx: &mut C,
2384     arg0: Reg,
2385     arg1: Reg,
2386     arg2: &VectorSize,
2387 ) -> Option<Reg> {
2388     let pattern0_0 = arg0;
2389     let pattern1_0 = arg1;
2390     let pattern2_0 = arg2;
2391     // Rule at src/isa/aarch64/inst.isle line 1662.
2392     let expr0_0 = VecALUOp::Sqadd;
2393     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2394     return Some(expr1_0);
2395 }
2396 
2397 // Generated as internal constructor for term uqsub.
2398 pub fn constructor_uqsub<C: Context>(
2399     ctx: &mut C,
2400     arg0: Reg,
2401     arg1: Reg,
2402     arg2: &VectorSize,
2403 ) -> Option<Reg> {
2404     let pattern0_0 = arg0;
2405     let pattern1_0 = arg1;
2406     let pattern2_0 = arg2;
2407     // Rule at src/isa/aarch64/inst.isle line 1666.
2408     let expr0_0 = VecALUOp::Uqsub;
2409     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2410     return Some(expr1_0);
2411 }
2412 
2413 // Generated as internal constructor for term sqsub.
2414 pub fn constructor_sqsub<C: Context>(
2415     ctx: &mut C,
2416     arg0: Reg,
2417     arg1: Reg,
2418     arg2: &VectorSize,
2419 ) -> Option<Reg> {
2420     let pattern0_0 = arg0;
2421     let pattern1_0 = arg1;
2422     let pattern2_0 = arg2;
2423     // Rule at src/isa/aarch64/inst.isle line 1670.
2424     let expr0_0 = VecALUOp::Sqsub;
2425     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2426     return Some(expr1_0);
2427 }
2428 
2429 // Generated as internal constructor for term umulh.
2430 pub fn constructor_umulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2431     let pattern0_0 = arg0;
2432     let pattern1_0 = arg1;
2433     let pattern2_0 = arg2;
2434     // Rule at src/isa/aarch64/inst.isle line 1674.
2435     let expr0_0 = ALUOp::UMulH;
2436     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2437     return Some(expr1_0);
2438 }
2439 
2440 // Generated as internal constructor for term smulh.
2441 pub fn constructor_smulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2442     let pattern0_0 = arg0;
2443     let pattern1_0 = arg1;
2444     let pattern2_0 = arg2;
2445     // Rule at src/isa/aarch64/inst.isle line 1678.
2446     let expr0_0 = ALUOp::SMulH;
2447     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2448     return Some(expr1_0);
2449 }
2450 
2451 // Generated as internal constructor for term mul.
2452 pub fn constructor_mul<C: Context>(
2453     ctx: &mut C,
2454     arg0: Reg,
2455     arg1: Reg,
2456     arg2: &VectorSize,
2457 ) -> Option<Reg> {
2458     let pattern0_0 = arg0;
2459     let pattern1_0 = arg1;
2460     let pattern2_0 = arg2;
2461     // Rule at src/isa/aarch64/inst.isle line 1682.
2462     let expr0_0 = VecALUOp::Mul;
2463     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2464     return Some(expr1_0);
2465 }
2466 
2467 // Generated as internal constructor for term neg.
2468 pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2469     let pattern0_0 = arg0;
2470     let pattern1_0 = arg1;
2471     // Rule at src/isa/aarch64/inst.isle line 1686.
2472     let expr0_0 = VecMisc2::Neg;
2473     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2474     return Some(expr1_0);
2475 }
2476 
2477 // Generated as internal constructor for term rev64.
2478 pub fn constructor_rev64<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2479     let pattern0_0 = arg0;
2480     let pattern1_0 = arg1;
2481     // Rule at src/isa/aarch64/inst.isle line 1690.
2482     let expr0_0 = VecMisc2::Rev64;
2483     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2484     return Some(expr1_0);
2485 }
2486 
2487 // Generated as internal constructor for term xtn64.
2488 pub fn constructor_xtn64<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2489     let pattern0_0 = arg0;
2490     let pattern1_0 = arg1;
2491     // Rule at src/isa/aarch64/inst.isle line 1694.
2492     let expr0_0 = VecRRNarrowOp::Xtn64;
2493     let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2494     return Some(expr1_0);
2495 }
2496 
2497 // Generated as internal constructor for term addp.
2498 pub fn constructor_addp<C: Context>(
2499     ctx: &mut C,
2500     arg0: Reg,
2501     arg1: Reg,
2502     arg2: &VectorSize,
2503 ) -> Option<Reg> {
2504     let pattern0_0 = arg0;
2505     let pattern1_0 = arg1;
2506     let pattern2_0 = arg2;
2507     // Rule at src/isa/aarch64/inst.isle line 1698.
2508     let expr0_0 = VecALUOp::Addp;
2509     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2510     return Some(expr1_0);
2511 }
2512 
2513 // Generated as internal constructor for term addv.
2514 pub fn constructor_addv<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2515     let pattern0_0 = arg0;
2516     let pattern1_0 = arg1;
2517     // Rule at src/isa/aarch64/inst.isle line 1702.
2518     let expr0_0 = VecLanesOp::Addv;
2519     let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2520     return Some(expr1_0);
2521 }
2522 
2523 // Generated as internal constructor for term shll32.
2524 pub fn constructor_shll32<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2525     let pattern0_0 = arg0;
2526     let pattern1_0 = arg1;
2527     // Rule at src/isa/aarch64/inst.isle line 1706.
2528     let expr0_0 = VecRRLongOp::Shll32;
2529     let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2530     return Some(expr1_0);
2531 }
2532 
2533 // Generated as internal constructor for term umlal32.
2534 pub fn constructor_umlal32<C: Context>(
2535     ctx: &mut C,
2536     arg0: Reg,
2537     arg1: Reg,
2538     arg2: Reg,
2539     arg3: bool,
2540 ) -> Option<Reg> {
2541     let pattern0_0 = arg0;
2542     let pattern1_0 = arg1;
2543     let pattern2_0 = arg2;
2544     let pattern3_0 = arg3;
2545     // Rule at src/isa/aarch64/inst.isle line 1710.
2546     let expr0_0 = VecRRRLongOp::Umlal32;
2547     let expr1_0 = constructor_vec_rrrr_long(
2548         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2549     )?;
2550     return Some(expr1_0);
2551 }
2552 
2553 // Generated as internal constructor for term smull8.
2554 pub fn constructor_smull8<C: Context>(
2555     ctx: &mut C,
2556     arg0: Reg,
2557     arg1: Reg,
2558     arg2: bool,
2559 ) -> Option<Reg> {
2560     let pattern0_0 = arg0;
2561     let pattern1_0 = arg1;
2562     let pattern2_0 = arg2;
2563     // Rule at src/isa/aarch64/inst.isle line 1714.
2564     let expr0_0 = VecRRRLongOp::Smull8;
2565     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2566     return Some(expr1_0);
2567 }
2568 
2569 // Generated as internal constructor for term umull8.
2570 pub fn constructor_umull8<C: Context>(
2571     ctx: &mut C,
2572     arg0: Reg,
2573     arg1: Reg,
2574     arg2: bool,
2575 ) -> Option<Reg> {
2576     let pattern0_0 = arg0;
2577     let pattern1_0 = arg1;
2578     let pattern2_0 = arg2;
2579     // Rule at src/isa/aarch64/inst.isle line 1718.
2580     let expr0_0 = VecRRRLongOp::Umull8;
2581     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2582     return Some(expr1_0);
2583 }
2584 
2585 // Generated as internal constructor for term smull16.
2586 pub fn constructor_smull16<C: Context>(
2587     ctx: &mut C,
2588     arg0: Reg,
2589     arg1: Reg,
2590     arg2: bool,
2591 ) -> Option<Reg> {
2592     let pattern0_0 = arg0;
2593     let pattern1_0 = arg1;
2594     let pattern2_0 = arg2;
2595     // Rule at src/isa/aarch64/inst.isle line 1722.
2596     let expr0_0 = VecRRRLongOp::Smull16;
2597     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2598     return Some(expr1_0);
2599 }
2600 
2601 // Generated as internal constructor for term umull16.
2602 pub fn constructor_umull16<C: Context>(
2603     ctx: &mut C,
2604     arg0: Reg,
2605     arg1: Reg,
2606     arg2: bool,
2607 ) -> Option<Reg> {
2608     let pattern0_0 = arg0;
2609     let pattern1_0 = arg1;
2610     let pattern2_0 = arg2;
2611     // Rule at src/isa/aarch64/inst.isle line 1726.
2612     let expr0_0 = VecRRRLongOp::Umull16;
2613     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2614     return Some(expr1_0);
2615 }
2616 
2617 // Generated as internal constructor for term smull32.
2618 pub fn constructor_smull32<C: Context>(
2619     ctx: &mut C,
2620     arg0: Reg,
2621     arg1: Reg,
2622     arg2: bool,
2623 ) -> Option<Reg> {
2624     let pattern0_0 = arg0;
2625     let pattern1_0 = arg1;
2626     let pattern2_0 = arg2;
2627     // Rule at src/isa/aarch64/inst.isle line 1730.
2628     let expr0_0 = VecRRRLongOp::Smull32;
2629     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2630     return Some(expr1_0);
2631 }
2632 
2633 // Generated as internal constructor for term umull32.
2634 pub fn constructor_umull32<C: Context>(
2635     ctx: &mut C,
2636     arg0: Reg,
2637     arg1: Reg,
2638     arg2: bool,
2639 ) -> Option<Reg> {
2640     let pattern0_0 = arg0;
2641     let pattern1_0 = arg1;
2642     let pattern2_0 = arg2;
2643     // Rule at src/isa/aarch64/inst.isle line 1734.
2644     let expr0_0 = VecRRRLongOp::Umull32;
2645     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2646     return Some(expr1_0);
2647 }
2648 
2649 // Generated as internal constructor for term asr.
2650 pub fn constructor_asr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2651     let pattern0_0 = arg0;
2652     let pattern1_0 = arg1;
2653     let pattern2_0 = arg2;
2654     // Rule at src/isa/aarch64/inst.isle line 1738.
2655     let expr0_0 = ALUOp::Asr;
2656     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2657     return Some(expr1_0);
2658 }
2659 
2660 // Generated as internal constructor for term asr_imm.
2661 pub fn constructor_asr_imm<C: Context>(
2662     ctx: &mut C,
2663     arg0: Type,
2664     arg1: Reg,
2665     arg2: ImmShift,
2666 ) -> Option<Reg> {
2667     let pattern0_0 = arg0;
2668     let pattern1_0 = arg1;
2669     let pattern2_0 = arg2;
2670     // Rule at src/isa/aarch64/inst.isle line 1741.
2671     let expr0_0 = ALUOp::Asr;
2672     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2673     return Some(expr1_0);
2674 }
2675 
2676 // Generated as internal constructor for term lsr.
2677 pub fn constructor_lsr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2678     let pattern0_0 = arg0;
2679     let pattern1_0 = arg1;
2680     let pattern2_0 = arg2;
2681     // Rule at src/isa/aarch64/inst.isle line 1745.
2682     let expr0_0 = ALUOp::Lsr;
2683     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2684     return Some(expr1_0);
2685 }
2686 
2687 // Generated as internal constructor for term lsr_imm.
2688 pub fn constructor_lsr_imm<C: Context>(
2689     ctx: &mut C,
2690     arg0: Type,
2691     arg1: Reg,
2692     arg2: ImmShift,
2693 ) -> Option<Reg> {
2694     let pattern0_0 = arg0;
2695     let pattern1_0 = arg1;
2696     let pattern2_0 = arg2;
2697     // Rule at src/isa/aarch64/inst.isle line 1748.
2698     let expr0_0 = ALUOp::Lsr;
2699     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2700     return Some(expr1_0);
2701 }
2702 
2703 // Generated as internal constructor for term lsl.
2704 pub fn constructor_lsl<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2705     let pattern0_0 = arg0;
2706     let pattern1_0 = arg1;
2707     let pattern2_0 = arg2;
2708     // Rule at src/isa/aarch64/inst.isle line 1752.
2709     let expr0_0 = ALUOp::Lsl;
2710     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2711     return Some(expr1_0);
2712 }
2713 
2714 // Generated as internal constructor for term lsl_imm.
2715 pub fn constructor_lsl_imm<C: Context>(
2716     ctx: &mut C,
2717     arg0: Type,
2718     arg1: Reg,
2719     arg2: ImmShift,
2720 ) -> Option<Reg> {
2721     let pattern0_0 = arg0;
2722     let pattern1_0 = arg1;
2723     let pattern2_0 = arg2;
2724     // Rule at src/isa/aarch64/inst.isle line 1755.
2725     let expr0_0 = ALUOp::Lsl;
2726     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2727     return Some(expr1_0);
2728 }
2729 
2730 // Generated as internal constructor for term a64_udiv.
2731 pub fn constructor_a64_udiv<C: Context>(
2732     ctx: &mut C,
2733     arg0: Type,
2734     arg1: Reg,
2735     arg2: Reg,
2736 ) -> Option<Reg> {
2737     let pattern0_0 = arg0;
2738     let pattern1_0 = arg1;
2739     let pattern2_0 = arg2;
2740     // Rule at src/isa/aarch64/inst.isle line 1759.
2741     let expr0_0 = ALUOp::UDiv;
2742     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2743     return Some(expr1_0);
2744 }
2745 
2746 // Generated as internal constructor for term a64_sdiv.
2747 pub fn constructor_a64_sdiv<C: Context>(
2748     ctx: &mut C,
2749     arg0: Type,
2750     arg1: Reg,
2751     arg2: Reg,
2752 ) -> Option<Reg> {
2753     let pattern0_0 = arg0;
2754     let pattern1_0 = arg1;
2755     let pattern2_0 = arg2;
2756     // Rule at src/isa/aarch64/inst.isle line 1763.
2757     let expr0_0 = ALUOp::SDiv;
2758     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2759     return Some(expr1_0);
2760 }
2761 
2762 // Generated as internal constructor for term not.
2763 pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2764     let pattern0_0 = arg0;
2765     let pattern1_0 = arg1;
2766     // Rule at src/isa/aarch64/inst.isle line 1767.
2767     let expr0_0 = VecMisc2::Not;
2768     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2769     return Some(expr1_0);
2770 }
2771 
2772 // Generated as internal constructor for term orr_not.
2773 pub fn constructor_orr_not<C: Context>(
2774     ctx: &mut C,
2775     arg0: Type,
2776     arg1: Reg,
2777     arg2: Reg,
2778 ) -> Option<Reg> {
2779     let pattern0_0 = arg0;
2780     let pattern1_0 = arg1;
2781     let pattern2_0 = arg2;
2782     // Rule at src/isa/aarch64/inst.isle line 1772.
2783     let expr0_0 = ALUOp::OrrNot;
2784     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2785     return Some(expr1_0);
2786 }
2787 
2788 // Generated as internal constructor for term orr_not_shift.
2789 pub fn constructor_orr_not_shift<C: Context>(
2790     ctx: &mut C,
2791     arg0: Type,
2792     arg1: Reg,
2793     arg2: Reg,
2794     arg3: ShiftOpAndAmt,
2795 ) -> Option<Reg> {
2796     let pattern0_0 = arg0;
2797     let pattern1_0 = arg1;
2798     let pattern2_0 = arg2;
2799     let pattern3_0 = arg3;
2800     // Rule at src/isa/aarch64/inst.isle line 1775.
2801     let expr0_0 = ALUOp::OrrNot;
2802     let expr1_0 = constructor_alu_rrr_shift(
2803         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2804     )?;
2805     return Some(expr1_0);
2806 }
2807 
2808 // Generated as internal constructor for term orr.
2809 pub fn constructor_orr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2810     let pattern0_0 = arg0;
2811     let pattern1_0 = arg1;
2812     let pattern2_0 = arg2;
2813     // Rule at src/isa/aarch64/inst.isle line 1780.
2814     let expr0_0 = ALUOp::Orr;
2815     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2816     return Some(expr1_0);
2817 }
2818 
2819 // Generated as internal constructor for term orr_imm.
2820 pub fn constructor_orr_imm<C: Context>(
2821     ctx: &mut C,
2822     arg0: Type,
2823     arg1: Reg,
2824     arg2: ImmLogic,
2825 ) -> Option<Reg> {
2826     let pattern0_0 = arg0;
2827     let pattern1_0 = arg1;
2828     let pattern2_0 = arg2;
2829     // Rule at src/isa/aarch64/inst.isle line 1783.
2830     let expr0_0 = ALUOp::Orr;
2831     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2832     return Some(expr1_0);
2833 }
2834 
2835 // Generated as internal constructor for term orr_vec.
2836 pub fn constructor_orr_vec<C: Context>(
2837     ctx: &mut C,
2838     arg0: Reg,
2839     arg1: Reg,
2840     arg2: &VectorSize,
2841 ) -> Option<Reg> {
2842     let pattern0_0 = arg0;
2843     let pattern1_0 = arg1;
2844     let pattern2_0 = arg2;
2845     // Rule at src/isa/aarch64/inst.isle line 1786.
2846     let expr0_0 = VecALUOp::Orr;
2847     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2848     return Some(expr1_0);
2849 }
2850 
2851 // Generated as internal constructor for term and_imm.
2852 pub fn constructor_and_imm<C: Context>(
2853     ctx: &mut C,
2854     arg0: Type,
2855     arg1: Reg,
2856     arg2: ImmLogic,
2857 ) -> Option<Reg> {
2858     let pattern0_0 = arg0;
2859     let pattern1_0 = arg1;
2860     let pattern2_0 = arg2;
2861     // Rule at src/isa/aarch64/inst.isle line 1791.
2862     let expr0_0 = ALUOp::And;
2863     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2864     return Some(expr1_0);
2865 }
2866 
2867 // Generated as internal constructor for term and_vec.
2868 pub fn constructor_and_vec<C: Context>(
2869     ctx: &mut C,
2870     arg0: Reg,
2871     arg1: Reg,
2872     arg2: &VectorSize,
2873 ) -> Option<Reg> {
2874     let pattern0_0 = arg0;
2875     let pattern1_0 = arg1;
2876     let pattern2_0 = arg2;
2877     // Rule at src/isa/aarch64/inst.isle line 1794.
2878     let expr0_0 = VecALUOp::And;
2879     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2880     return Some(expr1_0);
2881 }
2882 
2883 // Generated as internal constructor for term eor_vec.
2884 pub fn constructor_eor_vec<C: Context>(
2885     ctx: &mut C,
2886     arg0: Reg,
2887     arg1: Reg,
2888     arg2: &VectorSize,
2889 ) -> Option<Reg> {
2890     let pattern0_0 = arg0;
2891     let pattern1_0 = arg1;
2892     let pattern2_0 = arg2;
2893     // Rule at src/isa/aarch64/inst.isle line 1798.
2894     let expr0_0 = VecALUOp::Eor;
2895     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2896     return Some(expr1_0);
2897 }
2898 
2899 // Generated as internal constructor for term bic_vec.
2900 pub fn constructor_bic_vec<C: Context>(
2901     ctx: &mut C,
2902     arg0: Reg,
2903     arg1: Reg,
2904     arg2: &VectorSize,
2905 ) -> Option<Reg> {
2906     let pattern0_0 = arg0;
2907     let pattern1_0 = arg1;
2908     let pattern2_0 = arg2;
2909     // Rule at src/isa/aarch64/inst.isle line 1802.
2910     let expr0_0 = VecALUOp::Bic;
2911     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2912     return Some(expr1_0);
2913 }
2914 
2915 // Generated as internal constructor for term sshl.
2916 pub fn constructor_sshl<C: Context>(
2917     ctx: &mut C,
2918     arg0: Reg,
2919     arg1: Reg,
2920     arg2: &VectorSize,
2921 ) -> Option<Reg> {
2922     let pattern0_0 = arg0;
2923     let pattern1_0 = arg1;
2924     let pattern2_0 = arg2;
2925     // Rule at src/isa/aarch64/inst.isle line 1806.
2926     let expr0_0 = VecALUOp::Sshl;
2927     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2928     return Some(expr1_0);
2929 }
2930 
2931 // Generated as internal constructor for term ushl.
2932 pub fn constructor_ushl<C: Context>(
2933     ctx: &mut C,
2934     arg0: Reg,
2935     arg1: Reg,
2936     arg2: &VectorSize,
2937 ) -> Option<Reg> {
2938     let pattern0_0 = arg0;
2939     let pattern1_0 = arg1;
2940     let pattern2_0 = arg2;
2941     // Rule at src/isa/aarch64/inst.isle line 1810.
2942     let expr0_0 = VecALUOp::Ushl;
2943     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2944     return Some(expr1_0);
2945 }
2946 
2947 // Generated as internal constructor for term a64_rotr.
2948 pub fn constructor_a64_rotr<C: Context>(
2949     ctx: &mut C,
2950     arg0: Type,
2951     arg1: Reg,
2952     arg2: Reg,
2953 ) -> Option<Reg> {
2954     let pattern0_0 = arg0;
2955     let pattern1_0 = arg1;
2956     let pattern2_0 = arg2;
2957     // Rule at src/isa/aarch64/inst.isle line 1815.
2958     let expr0_0 = ALUOp::RotR;
2959     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2960     return Some(expr1_0);
2961 }
2962 
2963 // Generated as internal constructor for term a64_rotr_imm.
2964 pub fn constructor_a64_rotr_imm<C: Context>(
2965     ctx: &mut C,
2966     arg0: Type,
2967     arg1: Reg,
2968     arg2: ImmShift,
2969 ) -> Option<Reg> {
2970     let pattern0_0 = arg0;
2971     let pattern1_0 = arg1;
2972     let pattern2_0 = arg2;
2973     // Rule at src/isa/aarch64/inst.isle line 1818.
2974     let expr0_0 = ALUOp::RotR;
2975     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2976     return Some(expr1_0);
2977 }
2978 
2979 // Generated as internal constructor for term rbit.
2980 pub fn constructor_rbit<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2981     let pattern0_0 = arg0;
2982     let pattern1_0 = arg1;
2983     // Rule at src/isa/aarch64/inst.isle line 1823.
2984     let expr0_0 = BitOp::RBit;
2985     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2986     return Some(expr1_0);
2987 }
2988 
2989 // Generated as internal constructor for term a64_clz.
2990 pub fn constructor_a64_clz<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2991     let pattern0_0 = arg0;
2992     let pattern1_0 = arg1;
2993     // Rule at src/isa/aarch64/inst.isle line 1828.
2994     let expr0_0 = BitOp::Clz;
2995     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2996     return Some(expr1_0);
2997 }
2998 
2999 // Generated as internal constructor for term a64_cls.
3000 pub fn constructor_a64_cls<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
3001     let pattern0_0 = arg0;
3002     let pattern1_0 = arg1;
3003     // Rule at src/isa/aarch64/inst.isle line 1833.
3004     let expr0_0 = BitOp::Cls;
3005     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3006     return Some(expr1_0);
3007 }
3008 
3009 // Generated as internal constructor for term eon.
3010 pub fn constructor_eon<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
3011     let pattern0_0 = arg0;
3012     let pattern1_0 = arg1;
3013     let pattern2_0 = arg2;
3014     // Rule at src/isa/aarch64/inst.isle line 1838.
3015     let expr0_0 = ALUOp::EorNot;
3016     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3017     return Some(expr1_0);
3018 }
3019 
3020 // Generated as internal constructor for term vec_cnt.
3021 pub fn constructor_vec_cnt<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3022     let pattern0_0 = arg0;
3023     let pattern1_0 = arg1;
3024     // Rule at src/isa/aarch64/inst.isle line 1843.
3025     let expr0_0 = VecMisc2::Cnt;
3026     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3027     return Some(expr1_0);
3028 }
3029 
3030 // Generated as internal constructor for term imm.
3031 pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
3032     let pattern0_0 = arg0;
3033     if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) {
3034         let pattern2_0 = arg1;
3035         let closure3 = || {
3036             let expr0_0: Type = I64;
3037             return Some(expr0_0);
3038         };
3039         if let Some(pattern3_0) = closure3() {
3040             if let Some(pattern4_0) = C::imm_logic_from_u64(ctx, pattern2_0, pattern3_0) {
3041                 // Rule at src/isa/aarch64/inst.isle line 1858.
3042                 let expr0_0: Type = I64;
3043                 let expr1_0 = C::zero_reg(ctx);
3044                 let expr2_0 = constructor_orr_imm(ctx, expr0_0, expr1_0, pattern4_0)?;
3045                 return Some(expr2_0);
3046             }
3047         }
3048         if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) {
3049             // Rule at src/isa/aarch64/inst.isle line 1850.
3050             let expr0_0 = OperandSize::Size64;
3051             let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?;
3052             return Some(expr1_0);
3053         }
3054         if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) {
3055             // Rule at src/isa/aarch64/inst.isle line 1854.
3056             let expr0_0 = OperandSize::Size64;
3057             let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?;
3058             return Some(expr1_0);
3059         }
3060         // Rule at src/isa/aarch64/inst.isle line 1865.
3061         let expr0_0 = C::load_constant64_full(ctx, pattern2_0);
3062         return Some(expr0_0);
3063     }
3064     return None;
3065 }
3066 
3067 // Generated as internal constructor for term put_in_reg_sext32.
3068 pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3069     let pattern0_0 = arg0;
3070     let pattern1_0 = C::value_type(ctx, pattern0_0);
3071     if pattern1_0 == I32 {
3072         // Rule at src/isa/aarch64/inst.isle line 1876.
3073         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3074         return Some(expr0_0);
3075     }
3076     if pattern1_0 == I64 {
3077         // Rule at src/isa/aarch64/inst.isle line 1877.
3078         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3079         return Some(expr0_0);
3080     }
3081     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3082         // Rule at src/isa/aarch64/inst.isle line 1872.
3083         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3084         let expr1_0: bool = true;
3085         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3086         let expr3_0: u8 = 32;
3087         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3088         return Some(expr4_0);
3089     }
3090     return None;
3091 }
3092 
3093 // Generated as internal constructor for term put_in_reg_zext32.
3094 pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3095     let pattern0_0 = arg0;
3096     let pattern1_0 = C::value_type(ctx, pattern0_0);
3097     if pattern1_0 == I32 {
3098         // Rule at src/isa/aarch64/inst.isle line 1885.
3099         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3100         return Some(expr0_0);
3101     }
3102     if pattern1_0 == I64 {
3103         // Rule at src/isa/aarch64/inst.isle line 1886.
3104         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3105         return Some(expr0_0);
3106     }
3107     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3108         // Rule at src/isa/aarch64/inst.isle line 1881.
3109         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3110         let expr1_0: bool = false;
3111         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3112         let expr3_0: u8 = 32;
3113         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3114         return Some(expr4_0);
3115     }
3116     return None;
3117 }
3118 
3119 // Generated as internal constructor for term put_in_reg_sext64.
3120 pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3121     let pattern0_0 = arg0;
3122     let pattern1_0 = C::value_type(ctx, pattern0_0);
3123     if pattern1_0 == I64 {
3124         // Rule at src/isa/aarch64/inst.isle line 1894.
3125         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3126         return Some(expr0_0);
3127     }
3128     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3129         // Rule at src/isa/aarch64/inst.isle line 1890.
3130         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3131         let expr1_0: bool = true;
3132         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3133         let expr3_0: u8 = 64;
3134         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3135         return Some(expr4_0);
3136     }
3137     return None;
3138 }
3139 
3140 // Generated as internal constructor for term put_in_reg_zext64.
3141 pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3142     let pattern0_0 = arg0;
3143     let pattern1_0 = C::value_type(ctx, pattern0_0);
3144     if pattern1_0 == I64 {
3145         // Rule at src/isa/aarch64/inst.isle line 1902.
3146         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3147         return Some(expr0_0);
3148     }
3149     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3150         // Rule at src/isa/aarch64/inst.isle line 1898.
3151         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3152         let expr1_0: bool = false;
3153         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3154         let expr3_0: u8 = 64;
3155         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3156         return Some(expr4_0);
3157     }
3158     return None;
3159 }
3160 
3161 // Generated as internal constructor for term trap_if_zero_divisor.
3162 pub fn constructor_trap_if_zero_divisor<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3163     let pattern0_0 = arg0;
3164     // Rule at src/isa/aarch64/inst.isle line 1907.
3165     let expr0_0 = C::cond_br_zero(ctx, pattern0_0);
3166     let expr1_0 = C::trap_code_division_by_zero(ctx);
3167     let expr2_0 = MInst::TrapIf {
3168         kind: expr0_0,
3169         trap_code: expr1_0,
3170     };
3171     let expr3_0 = C::emit(ctx, &expr2_0);
3172     return Some(pattern0_0);
3173 }
3174 
3175 // Generated as internal constructor for term size_from_ty.
3176 pub fn constructor_size_from_ty<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
3177     let pattern0_0 = arg0;
3178     if pattern0_0 == I64 {
3179         // Rule at src/isa/aarch64/inst.isle line 1913.
3180         let expr0_0 = OperandSize::Size64;
3181         return Some(expr0_0);
3182     }
3183     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
3184         // Rule at src/isa/aarch64/inst.isle line 1912.
3185         let expr0_0 = OperandSize::Size32;
3186         return Some(expr0_0);
3187     }
3188     return None;
3189 }
3190 
3191 // Generated as internal constructor for term trap_if_div_overflow.
3192 pub fn constructor_trap_if_div_overflow<C: Context>(
3193     ctx: &mut C,
3194     arg0: Type,
3195     arg1: Reg,
3196     arg2: Reg,
3197 ) -> Option<Reg> {
3198     let pattern0_0 = arg0;
3199     let pattern1_0 = arg1;
3200     let pattern2_0 = arg2;
3201     // Rule at src/isa/aarch64/inst.isle line 1919.
3202     let expr0_0 = ALUOp::AddS;
3203     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
3204     let expr2_0 = C::writable_zero_reg(ctx);
3205     let expr3_0: u8 = 1;
3206     let expr4_0 = C::u8_into_imm12(ctx, expr3_0);
3207     let expr5_0 = MInst::AluRRImm12 {
3208         alu_op: expr0_0,
3209         size: expr1_0,
3210         rd: expr2_0,
3211         rn: pattern2_0,
3212         imm12: expr4_0,
3213     };
3214     let expr6_0 = C::emit(ctx, &expr5_0);
3215     let expr7_0 = constructor_size_from_ty(ctx, pattern0_0)?;
3216     let expr8_0: u8 = 1;
3217     let expr9_0 = C::u8_into_uimm5(ctx, expr8_0);
3218     let expr10_0: bool = false;
3219     let expr11_0: bool = false;
3220     let expr12_0: bool = false;
3221     let expr13_0: bool = false;
3222     let expr14_0 = C::nzcv(ctx, expr10_0, expr11_0, expr12_0, expr13_0);
3223     let expr15_0 = Cond::Eq;
3224     let expr16_0 = MInst::CCmpImm {
3225         size: expr7_0,
3226         rn: pattern1_0,
3227         imm: expr9_0,
3228         nzcv: expr14_0,
3229         cond: expr15_0,
3230     };
3231     let expr17_0 = C::emit(ctx, &expr16_0);
3232     let expr18_0 = Cond::Vs;
3233     let expr19_0 = C::cond_br_cond(ctx, &expr18_0);
3234     let expr20_0 = C::trap_code_integer_overflow(ctx);
3235     let expr21_0 = MInst::TrapIf {
3236         kind: expr19_0,
3237         trap_code: expr20_0,
3238     };
3239     let expr22_0 = C::emit(ctx, &expr21_0);
3240     return Some(pattern1_0);
3241 }
3242 
3243 // Generated as internal constructor for term alu_rs_imm_logic_commutative.
3244 pub fn constructor_alu_rs_imm_logic_commutative<C: Context>(
3245     ctx: &mut C,
3246     arg0: &ALUOp,
3247     arg1: Type,
3248     arg2: Value,
3249     arg3: Value,
3250 ) -> Option<Reg> {
3251     let pattern0_0 = arg0;
3252     let pattern1_0 = arg1;
3253     let pattern2_0 = arg2;
3254     if let Some(pattern3_0) = C::def_inst(ctx, pattern2_0) {
3255         let pattern4_0 = C::inst_data(ctx, pattern3_0);
3256         match &pattern4_0 {
3257             &InstructionData::UnaryImm {
3258                 opcode: ref pattern5_0,
3259                 imm: pattern5_1,
3260             } => {
3261                 if let &Opcode::Iconst = pattern5_0 {
3262                     let closure7 = || {
3263                         return Some(pattern1_0);
3264                     };
3265                     if let Some(pattern7_0) = closure7() {
3266                         if let Some(pattern8_0) =
3267                             C::imm_logic_from_imm64(ctx, pattern5_1, pattern7_0)
3268                         {
3269                             let pattern9_0 = arg3;
3270                             // Rule at src/isa/aarch64/inst.isle line 1964.
3271                             let expr0_0 = C::put_in_reg(ctx, pattern9_0);
3272                             let expr1_0 = constructor_alu_rr_imm_logic(
3273                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0,
3274                             )?;
3275                             return Some(expr1_0);
3276                         }
3277                     }
3278                 }
3279             }
3280             &InstructionData::Binary {
3281                 opcode: ref pattern5_0,
3282                 args: ref pattern5_1,
3283             } => {
3284                 if let &Opcode::Ishl = pattern5_0 {
3285                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3286                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3287                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
3288                         if let &InstructionData::UnaryImm {
3289                             opcode: ref pattern10_0,
3290                             imm: pattern10_1,
3291                         } = &pattern9_0
3292                         {
3293                             if let &Opcode::Iconst = pattern10_0 {
3294                                 let closure12 = || {
3295                                     return Some(pattern1_0);
3296                                 };
3297                                 if let Some(pattern12_0) = closure12() {
3298                                     if let Some(pattern13_0) =
3299                                         C::lshl_from_imm64(ctx, pattern10_1, pattern12_0)
3300                                     {
3301                                         let pattern14_0 = arg3;
3302                                         // Rule at src/isa/aarch64/inst.isle line 1970.
3303                                         let expr0_0 = C::put_in_reg(ctx, pattern14_0);
3304                                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3305                                         let expr2_0 = constructor_alu_rrr_shift(
3306                                             ctx,
3307                                             pattern0_0,
3308                                             pattern1_0,
3309                                             expr0_0,
3310                                             expr1_0,
3311                                             pattern13_0,
3312                                         )?;
3313                                         return Some(expr2_0);
3314                                     }
3315                                 }
3316                             }
3317                         }
3318                     }
3319                 }
3320             }
3321             _ => {}
3322         }
3323     }
3324     let pattern3_0 = arg3;
3325     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3326         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3327         match &pattern5_0 {
3328             &InstructionData::UnaryImm {
3329                 opcode: ref pattern6_0,
3330                 imm: pattern6_1,
3331             } => {
3332                 if let &Opcode::Iconst = pattern6_0 {
3333                     let closure8 = || {
3334                         return Some(pattern1_0);
3335                     };
3336                     if let Some(pattern8_0) = closure8() {
3337                         if let Some(pattern9_0) =
3338                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3339                         {
3340                             // Rule at src/isa/aarch64/inst.isle line 1962.
3341                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3342                             let expr1_0 = constructor_alu_rr_imm_logic(
3343                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3344                             )?;
3345                             return Some(expr1_0);
3346                         }
3347                     }
3348                 }
3349             }
3350             &InstructionData::Binary {
3351                 opcode: ref pattern6_0,
3352                 args: ref pattern6_1,
3353             } => {
3354                 if let &Opcode::Ishl = pattern6_0 {
3355                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3356                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3357                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3358                         if let &InstructionData::UnaryImm {
3359                             opcode: ref pattern11_0,
3360                             imm: pattern11_1,
3361                         } = &pattern10_0
3362                         {
3363                             if let &Opcode::Iconst = pattern11_0 {
3364                                 let closure13 = || {
3365                                     return Some(pattern1_0);
3366                                 };
3367                                 if let Some(pattern13_0) = closure13() {
3368                                     if let Some(pattern14_0) =
3369                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3370                                     {
3371                                         // Rule at src/isa/aarch64/inst.isle line 1968.
3372                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3373                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3374                                         let expr2_0 = constructor_alu_rrr_shift(
3375                                             ctx,
3376                                             pattern0_0,
3377                                             pattern1_0,
3378                                             expr0_0,
3379                                             expr1_0,
3380                                             pattern14_0,
3381                                         )?;
3382                                         return Some(expr2_0);
3383                                     }
3384                                 }
3385                             }
3386                         }
3387                     }
3388                 }
3389             }
3390             _ => {}
3391         }
3392     }
3393     // Rule at src/isa/aarch64/inst.isle line 1958.
3394     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3395     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3396     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3397     return Some(expr2_0);
3398 }
3399 
3400 // Generated as internal constructor for term alu_rs_imm_logic.
3401 pub fn constructor_alu_rs_imm_logic<C: Context>(
3402     ctx: &mut C,
3403     arg0: &ALUOp,
3404     arg1: Type,
3405     arg2: Value,
3406     arg3: Value,
3407 ) -> Option<Reg> {
3408     let pattern0_0 = arg0;
3409     let pattern1_0 = arg1;
3410     let pattern2_0 = arg2;
3411     let pattern3_0 = arg3;
3412     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3413         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3414         match &pattern5_0 {
3415             &InstructionData::UnaryImm {
3416                 opcode: ref pattern6_0,
3417                 imm: pattern6_1,
3418             } => {
3419                 if let &Opcode::Iconst = pattern6_0 {
3420                     let closure8 = || {
3421                         return Some(pattern1_0);
3422                     };
3423                     if let Some(pattern8_0) = closure8() {
3424                         if let Some(pattern9_0) =
3425                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3426                         {
3427                             // Rule at src/isa/aarch64/inst.isle line 1978.
3428                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3429                             let expr1_0 = constructor_alu_rr_imm_logic(
3430                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3431                             )?;
3432                             return Some(expr1_0);
3433                         }
3434                     }
3435                 }
3436             }
3437             &InstructionData::Binary {
3438                 opcode: ref pattern6_0,
3439                 args: ref pattern6_1,
3440             } => {
3441                 if let &Opcode::Ishl = pattern6_0 {
3442                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3443                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3444                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3445                         if let &InstructionData::UnaryImm {
3446                             opcode: ref pattern11_0,
3447                             imm: pattern11_1,
3448                         } = &pattern10_0
3449                         {
3450                             if let &Opcode::Iconst = pattern11_0 {
3451                                 let closure13 = || {
3452                                     return Some(pattern1_0);
3453                                 };
3454                                 if let Some(pattern13_0) = closure13() {
3455                                     if let Some(pattern14_0) =
3456                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3457                                     {
3458                                         // Rule at src/isa/aarch64/inst.isle line 1980.
3459                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3460                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3461                                         let expr2_0 = constructor_alu_rrr_shift(
3462                                             ctx,
3463                                             pattern0_0,
3464                                             pattern1_0,
3465                                             expr0_0,
3466                                             expr1_0,
3467                                             pattern14_0,
3468                                         )?;
3469                                         return Some(expr2_0);
3470                                     }
3471                                 }
3472                             }
3473                         }
3474                     }
3475                 }
3476             }
3477             _ => {}
3478         }
3479     }
3480     // Rule at src/isa/aarch64/inst.isle line 1976.
3481     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3482     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3483     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3484     return Some(expr2_0);
3485 }
3486 
3487 // Generated as internal constructor for term i128_alu_bitop.
3488 pub fn constructor_i128_alu_bitop<C: Context>(
3489     ctx: &mut C,
3490     arg0: &ALUOp,
3491     arg1: Type,
3492     arg2: Value,
3493     arg3: Value,
3494 ) -> Option<ValueRegs> {
3495     let pattern0_0 = arg0;
3496     let pattern1_0 = arg1;
3497     let pattern2_0 = arg2;
3498     let pattern3_0 = arg3;
3499     // Rule at src/isa/aarch64/inst.isle line 1988.
3500     let expr0_0 = C::put_in_regs(ctx, pattern2_0);
3501     let expr1_0: usize = 0;
3502     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3503     let expr3_0: usize = 1;
3504     let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
3505     let expr5_0 = C::put_in_regs(ctx, pattern3_0);
3506     let expr6_0: usize = 0;
3507     let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
3508     let expr8_0: usize = 1;
3509     let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
3510     let expr10_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr2_0, expr7_0)?;
3511     let expr11_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr4_0, expr9_0)?;
3512     let expr12_0 = C::value_regs(ctx, expr10_0, expr11_0);
3513     return Some(expr12_0);
3514 }
3515 
3516 // Generated as internal constructor for term lower.
3517 pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> {
3518     let pattern0_0 = arg0;
3519     if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
3520         let pattern2_0 = C::value_type(ctx, pattern1_0);
3521         if pattern2_0 == I8 {
3522             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3523             if let &InstructionData::Unary {
3524                 opcode: ref pattern5_0,
3525                 arg: pattern5_1,
3526             } = &pattern4_0
3527             {
3528                 match pattern5_0 {
3529                     &Opcode::Bitrev => {
3530                         // Rule at src/isa/aarch64/lower.isle line 974.
3531                         let expr0_0: Type = I32;
3532                         let expr1_0: Type = I32;
3533                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3534                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3535                         let expr4_0: u8 = 24;
3536                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3537                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3538                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3539                         return Some(expr7_0);
3540                     }
3541                     &Opcode::Clz => {
3542                         // Rule at src/isa/aarch64/lower.isle line 995.
3543                         let expr0_0: Type = I32;
3544                         let expr1_0: Type = I32;
3545                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3546                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3547                         let expr4_0: u8 = 24;
3548                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3549                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3550                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3551                         return Some(expr7_0);
3552                     }
3553                     &Opcode::Cls => {
3554                         // Rule at src/isa/aarch64/lower.isle line 1042.
3555                         let expr0_0: Type = I32;
3556                         let expr1_0: Type = I32;
3557                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3558                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3559                         let expr4_0: u8 = 24;
3560                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3561                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3562                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3563                         return Some(expr7_0);
3564                     }
3565                     &Opcode::Ctz => {
3566                         // Rule at src/isa/aarch64/lower.isle line 1025.
3567                         let expr0_0: Type = I32;
3568                         let expr1_0: Type = I32;
3569                         let expr2_0: Type = I32;
3570                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3571                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3572                         let expr5_0: Type = I32;
3573                         let expr6_0: u64 = 8388608;
3574                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3575                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3576                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3577                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3578                         return Some(expr10_0);
3579                     }
3580                     &Opcode::Popcnt => {
3581                         // Rule at src/isa/aarch64/lower.isle line 1093.
3582                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3583                         let expr1_0 = ScalarSize::Size32;
3584                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3585                         let expr3_0 = VectorSize::Size8x8;
3586                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3587                         let expr5_0: u8 = 0;
3588                         let expr6_0 = VectorSize::Size8x16;
3589                         let expr7_0 = constructor_mov_from_vec(ctx, expr4_0, expr5_0, &expr6_0)?;
3590                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
3591                         return Some(expr8_0);
3592                     }
3593                     _ => {}
3594                 }
3595             }
3596         }
3597         if pattern2_0 == I16 {
3598             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3599             if let &InstructionData::Unary {
3600                 opcode: ref pattern5_0,
3601                 arg: pattern5_1,
3602             } = &pattern4_0
3603             {
3604                 match pattern5_0 {
3605                     &Opcode::Bitrev => {
3606                         // Rule at src/isa/aarch64/lower.isle line 980.
3607                         let expr0_0: Type = I32;
3608                         let expr1_0: Type = I32;
3609                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3610                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3611                         let expr4_0: u8 = 16;
3612                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3613                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3614                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3615                         return Some(expr7_0);
3616                     }
3617                     &Opcode::Clz => {
3618                         // Rule at src/isa/aarch64/lower.isle line 998.
3619                         let expr0_0: Type = I32;
3620                         let expr1_0: Type = I32;
3621                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3622                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3623                         let expr4_0: u8 = 16;
3624                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3625                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3626                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3627                         return Some(expr7_0);
3628                     }
3629                     &Opcode::Cls => {
3630                         // Rule at src/isa/aarch64/lower.isle line 1045.
3631                         let expr0_0: Type = I32;
3632                         let expr1_0: Type = I32;
3633                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3634                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3635                         let expr4_0: u8 = 16;
3636                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3637                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3638                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3639                         return Some(expr7_0);
3640                     }
3641                     &Opcode::Ctz => {
3642                         // Rule at src/isa/aarch64/lower.isle line 1028.
3643                         let expr0_0: Type = I32;
3644                         let expr1_0: Type = I32;
3645                         let expr2_0: Type = I32;
3646                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3647                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3648                         let expr5_0: Type = I32;
3649                         let expr6_0: u64 = 32768;
3650                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3651                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3652                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3653                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3654                         return Some(expr10_0);
3655                     }
3656                     &Opcode::Popcnt => {
3657                         // Rule at src/isa/aarch64/lower.isle line 1099.
3658                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3659                         let expr1_0 = ScalarSize::Size32;
3660                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3661                         let expr3_0 = VectorSize::Size8x8;
3662                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3663                         let expr5_0 = VectorSize::Size8x8;
3664                         let expr6_0 = constructor_addp(ctx, expr4_0, expr4_0, &expr5_0)?;
3665                         let expr7_0: u8 = 0;
3666                         let expr8_0 = VectorSize::Size8x16;
3667                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3668                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3669                         return Some(expr10_0);
3670                     }
3671                     _ => {}
3672                 }
3673             }
3674         }
3675         if pattern2_0 == I32 {
3676             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3677             match &pattern4_0 {
3678                 &InstructionData::Binary {
3679                     opcode: ref pattern5_0,
3680                     args: ref pattern5_1,
3681                 } => {
3682                     match pattern5_0 {
3683                         &Opcode::Rotl => {
3684                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3685                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3686                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3687                                 if let &InstructionData::UnaryImm {
3688                                     opcode: ref pattern10_0,
3689                                     imm: pattern10_1,
3690                                 } = &pattern9_0
3691                                 {
3692                                     if let &Opcode::Iconst = pattern10_0 {
3693                                         let closure12 = || {
3694                                             let expr0_0: Type = I32;
3695                                             return Some(expr0_0);
3696                                         };
3697                                         if let Some(pattern12_0) = closure12() {
3698                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3699                                                 ctx,
3700                                                 pattern10_1,
3701                                                 pattern12_0,
3702                                             ) {
3703                                                 // Rule at src/isa/aarch64/lower.isle line 865.
3704                                                 let expr0_0: Type = I32;
3705                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3706                                                 let expr2_0: Type = I32;
3707                                                 let expr3_0 =
3708                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3709                                                 let expr4_0 = constructor_a64_rotr_imm(
3710                                                     ctx, expr0_0, expr1_0, expr3_0,
3711                                                 )?;
3712                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3713                                                 return Some(expr5_0);
3714                                             }
3715                                         }
3716                                     }
3717                                 }
3718                             }
3719                             // Rule at src/isa/aarch64/lower.isle line 855.
3720                             let expr0_0: Type = I32;
3721                             let expr1_0 = C::zero_reg(ctx);
3722                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3723                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3724                             let expr4_0: Type = I32;
3725                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3726                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3727                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3728                             return Some(expr7_0);
3729                         }
3730                         &Opcode::Rotr => {
3731                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3732                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3733                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3734                                 if let &InstructionData::UnaryImm {
3735                                     opcode: ref pattern10_0,
3736                                     imm: pattern10_1,
3737                                 } = &pattern9_0
3738                                 {
3739                                     if let &Opcode::Iconst = pattern10_0 {
3740                                         let closure12 = || {
3741                                             let expr0_0: Type = I32;
3742                                             return Some(expr0_0);
3743                                         };
3744                                         if let Some(pattern12_0) = closure12() {
3745                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3746                                                 ctx,
3747                                                 pattern10_1,
3748                                                 pattern12_0,
3749                                             ) {
3750                                                 // Rule at src/isa/aarch64/lower.isle line 907.
3751                                                 let expr0_0: Type = I32;
3752                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3753                                                 let expr2_0 = constructor_a64_rotr_imm(
3754                                                     ctx,
3755                                                     expr0_0,
3756                                                     expr1_0,
3757                                                     pattern13_0,
3758                                                 )?;
3759                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3760                                                 return Some(expr3_0);
3761                                             }
3762                                         }
3763                                     }
3764                                 }
3765                             }
3766                             // Rule at src/isa/aarch64/lower.isle line 895.
3767                             let expr0_0: Type = I32;
3768                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3769                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3770                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
3771                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3772                             return Some(expr4_0);
3773                         }
3774                         _ => {}
3775                     }
3776                 }
3777                 &InstructionData::Unary {
3778                     opcode: ref pattern5_0,
3779                     arg: pattern5_1,
3780                 } => {
3781                     if let &Opcode::Popcnt = pattern5_0 {
3782                         // Rule at src/isa/aarch64/lower.isle line 1105.
3783                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3784                         let expr1_0 = ScalarSize::Size32;
3785                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3786                         let expr3_0 = VectorSize::Size8x8;
3787                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3788                         let expr5_0 = VectorSize::Size8x8;
3789                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
3790                         let expr7_0: u8 = 0;
3791                         let expr8_0 = VectorSize::Size8x16;
3792                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3793                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3794                         return Some(expr10_0);
3795                     }
3796                 }
3797                 _ => {}
3798             }
3799         }
3800         if pattern2_0 == I64 {
3801             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3802             match &pattern4_0 {
3803                 &InstructionData::Binary {
3804                     opcode: ref pattern5_0,
3805                     args: ref pattern5_1,
3806                 } => {
3807                     match pattern5_0 {
3808                         &Opcode::Umulhi => {
3809                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3810                             // Rule at src/isa/aarch64/lower.isle line 367.
3811                             let expr0_0: Type = I64;
3812                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3813                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3814                             let expr3_0 = constructor_umulh(ctx, expr0_0, expr1_0, expr2_0)?;
3815                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3816                             return Some(expr4_0);
3817                         }
3818                         &Opcode::Smulhi => {
3819                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3820                             // Rule at src/isa/aarch64/lower.isle line 355.
3821                             let expr0_0: Type = I64;
3822                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3823                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3824                             let expr3_0 = constructor_smulh(ctx, expr0_0, expr1_0, expr2_0)?;
3825                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3826                             return Some(expr4_0);
3827                         }
3828                         &Opcode::Band => {
3829                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3830                             // Rule at src/isa/aarch64/lower.isle line 586.
3831                             let expr0_0 = ALUOp::And;
3832                             let expr1_0: Type = I64;
3833                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3834                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3835                             )?;
3836                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3837                             return Some(expr3_0);
3838                         }
3839                         &Opcode::Bor => {
3840                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3841                             // Rule at src/isa/aarch64/lower.isle line 599.
3842                             let expr0_0 = ALUOp::Orr;
3843                             let expr1_0: Type = I64;
3844                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3845                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3846                             )?;
3847                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3848                             return Some(expr3_0);
3849                         }
3850                         &Opcode::Bxor => {
3851                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3852                             // Rule at src/isa/aarch64/lower.isle line 612.
3853                             let expr0_0 = ALUOp::Eor;
3854                             let expr1_0: Type = I64;
3855                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3856                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3857                             )?;
3858                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3859                             return Some(expr3_0);
3860                         }
3861                         &Opcode::BandNot => {
3862                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3863                             // Rule at src/isa/aarch64/lower.isle line 625.
3864                             let expr0_0 = ALUOp::AndNot;
3865                             let expr1_0: Type = I64;
3866                             let expr2_0 = constructor_alu_rs_imm_logic(
3867                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3868                             )?;
3869                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3870                             return Some(expr3_0);
3871                         }
3872                         &Opcode::BorNot => {
3873                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3874                             // Rule at src/isa/aarch64/lower.isle line 638.
3875                             let expr0_0 = ALUOp::OrrNot;
3876                             let expr1_0: Type = I64;
3877                             let expr2_0 = constructor_alu_rs_imm_logic(
3878                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3879                             )?;
3880                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3881                             return Some(expr3_0);
3882                         }
3883                         &Opcode::BxorNot => {
3884                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3885                             // Rule at src/isa/aarch64/lower.isle line 648.
3886                             let expr0_0 = ALUOp::EorNot;
3887                             let expr1_0: Type = I64;
3888                             let expr2_0 = constructor_alu_rs_imm_logic(
3889                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3890                             )?;
3891                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3892                             return Some(expr3_0);
3893                         }
3894                         &Opcode::Rotl => {
3895                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3896                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3897                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3898                                 if let &InstructionData::UnaryImm {
3899                                     opcode: ref pattern10_0,
3900                                     imm: pattern10_1,
3901                                 } = &pattern9_0
3902                                 {
3903                                     if let &Opcode::Iconst = pattern10_0 {
3904                                         let closure12 = || {
3905                                             let expr0_0: Type = I64;
3906                                             return Some(expr0_0);
3907                                         };
3908                                         if let Some(pattern12_0) = closure12() {
3909                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3910                                                 ctx,
3911                                                 pattern10_1,
3912                                                 pattern12_0,
3913                                             ) {
3914                                                 // Rule at src/isa/aarch64/lower.isle line 869.
3915                                                 let expr0_0: Type = I64;
3916                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3917                                                 let expr2_0: Type = I64;
3918                                                 let expr3_0 =
3919                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3920                                                 let expr4_0 = constructor_a64_rotr_imm(
3921                                                     ctx, expr0_0, expr1_0, expr3_0,
3922                                                 )?;
3923                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3924                                                 return Some(expr5_0);
3925                                             }
3926                                         }
3927                                     }
3928                                 }
3929                             }
3930                             // Rule at src/isa/aarch64/lower.isle line 860.
3931                             let expr0_0: Type = I64;
3932                             let expr1_0 = C::zero_reg(ctx);
3933                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3934                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3935                             let expr4_0: Type = I64;
3936                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3937                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3938                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3939                             return Some(expr7_0);
3940                         }
3941                         &Opcode::Rotr => {
3942                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3943                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3944                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3945                                 if let &InstructionData::UnaryImm {
3946                                     opcode: ref pattern10_0,
3947                                     imm: pattern10_1,
3948                                 } = &pattern9_0
3949                                 {
3950                                     if let &Opcode::Iconst = pattern10_0 {
3951                                         let closure12 = || {
3952                                             let expr0_0: Type = I64;
3953                                             return Some(expr0_0);
3954                                         };
3955                                         if let Some(pattern12_0) = closure12() {
3956                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3957                                                 ctx,
3958                                                 pattern10_1,
3959                                                 pattern12_0,
3960                                             ) {
3961                                                 // Rule at src/isa/aarch64/lower.isle line 911.
3962                                                 let expr0_0: Type = I64;
3963                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3964                                                 let expr2_0 = constructor_a64_rotr_imm(
3965                                                     ctx,
3966                                                     expr0_0,
3967                                                     expr1_0,
3968                                                     pattern13_0,
3969                                                 )?;
3970                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3971                                                 return Some(expr3_0);
3972                                             }
3973                                         }
3974                                     }
3975                                 }
3976                             }
3977                             // Rule at src/isa/aarch64/lower.isle line 899.
3978                             let expr0_0: Type = I64;
3979                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3980                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3981                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
3982                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3983                             return Some(expr4_0);
3984                         }
3985                         &Opcode::Ishl => {
3986                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3987                             // Rule at src/isa/aarch64/lower.isle line 660.
3988                             let expr0_0 = ALUOp::Lsl;
3989                             let expr1_0: Type = I64;
3990                             let expr2_0 = C::put_in_reg(ctx, pattern7_0);
3991                             let expr3_0 =
3992                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
3993                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3994                             return Some(expr4_0);
3995                         }
3996                         &Opcode::Ushr => {
3997                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3998                             // Rule at src/isa/aarch64/lower.isle line 744.
3999                             let expr0_0 = ALUOp::Lsr;
4000                             let expr1_0: Type = I64;
4001                             let expr2_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
4002                             let expr3_0 =
4003                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4004                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4005                             return Some(expr4_0);
4006                         }
4007                         &Opcode::Sshr => {
4008                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4009                             // Rule at src/isa/aarch64/lower.isle line 791.
4010                             let expr0_0 = ALUOp::Asr;
4011                             let expr1_0: Type = I64;
4012                             let expr2_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
4013                             let expr3_0 =
4014                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4015                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4016                             return Some(expr4_0);
4017                         }
4018                         _ => {}
4019                     }
4020                 }
4021                 &InstructionData::Unary {
4022                     opcode: ref pattern5_0,
4023                     arg: pattern5_1,
4024                 } => {
4025                     if let &Opcode::Popcnt = pattern5_0 {
4026                         // Rule at src/isa/aarch64/lower.isle line 1111.
4027                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4028                         let expr1_0 = ScalarSize::Size64;
4029                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
4030                         let expr3_0 = VectorSize::Size8x8;
4031                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
4032                         let expr5_0 = VectorSize::Size8x8;
4033                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
4034                         let expr7_0: u8 = 0;
4035                         let expr8_0 = VectorSize::Size8x16;
4036                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
4037                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
4038                         return Some(expr10_0);
4039                     }
4040                 }
4041                 _ => {}
4042             }
4043         }
4044         if pattern2_0 == I128 {
4045             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4046             match &pattern4_0 {
4047                 &InstructionData::Binary {
4048                     opcode: ref pattern5_0,
4049                     args: ref pattern5_1,
4050                 } => {
4051                     match pattern5_0 {
4052                         &Opcode::Iadd => {
4053                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4054                             // Rule at src/isa/aarch64/lower.isle line 79.
4055                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4056                             let expr1_0: usize = 0;
4057                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4058                             let expr3_0: usize = 1;
4059                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4060                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4061                             let expr6_0: usize = 0;
4062                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4063                             let expr8_0: usize = 1;
4064                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4065                             let expr10_0: Type = I64;
4066                             let expr11_0 =
4067                                 constructor_add_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4068                             let expr12_0: Type = I64;
4069                             let expr13_0 = constructor_adc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4070                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4071                             let expr15_0 = C::output(ctx, expr14_0);
4072                             return Some(expr15_0);
4073                         }
4074                         &Opcode::Isub => {
4075                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4076                             // Rule at src/isa/aarch64/lower.isle line 129.
4077                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4078                             let expr1_0: usize = 0;
4079                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4080                             let expr3_0: usize = 1;
4081                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4082                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4083                             let expr6_0: usize = 0;
4084                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4085                             let expr8_0: usize = 1;
4086                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4087                             let expr10_0: Type = I64;
4088                             let expr11_0 =
4089                                 constructor_sub_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4090                             let expr12_0: Type = I64;
4091                             let expr13_0 = constructor_sbc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4092                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4093                             let expr15_0 = C::output(ctx, expr14_0);
4094                             return Some(expr15_0);
4095                         }
4096                         &Opcode::Imul => {
4097                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4098                             // Rule at src/isa/aarch64/lower.isle line 183.
4099                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4100                             let expr1_0: usize = 0;
4101                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4102                             let expr3_0: usize = 1;
4103                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4104                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4105                             let expr6_0: usize = 0;
4106                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4107                             let expr8_0: usize = 1;
4108                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4109                             let expr10_0: Type = I64;
4110                             let expr11_0 = constructor_umulh(ctx, expr10_0, expr2_0, expr7_0)?;
4111                             let expr12_0 = constructor_madd64(ctx, expr2_0, expr9_0, expr11_0)?;
4112                             let expr13_0 = constructor_madd64(ctx, expr4_0, expr7_0, expr12_0)?;
4113                             let expr14_0 = C::zero_reg(ctx);
4114                             let expr15_0 = constructor_madd64(ctx, expr2_0, expr7_0, expr14_0)?;
4115                             let expr16_0 = C::value_regs(ctx, expr15_0, expr13_0);
4116                             let expr17_0 = C::output(ctx, expr16_0);
4117                             return Some(expr17_0);
4118                         }
4119                         &Opcode::Band => {
4120                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4121                             // Rule at src/isa/aarch64/lower.isle line 589.
4122                             let expr0_0 = ALUOp::And;
4123                             let expr1_0: Type = I64;
4124                             let expr2_0 = constructor_i128_alu_bitop(
4125                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4126                             )?;
4127                             let expr3_0 = C::output(ctx, expr2_0);
4128                             return Some(expr3_0);
4129                         }
4130                         &Opcode::Bor => {
4131                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4132                             // Rule at src/isa/aarch64/lower.isle line 602.
4133                             let expr0_0 = ALUOp::Orr;
4134                             let expr1_0: Type = I64;
4135                             let expr2_0 = constructor_i128_alu_bitop(
4136                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4137                             )?;
4138                             let expr3_0 = C::output(ctx, expr2_0);
4139                             return Some(expr3_0);
4140                         }
4141                         &Opcode::Bxor => {
4142                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4143                             // Rule at src/isa/aarch64/lower.isle line 615.
4144                             let expr0_0 = ALUOp::Eor;
4145                             let expr1_0: Type = I64;
4146                             let expr2_0 = constructor_i128_alu_bitop(
4147                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4148                             )?;
4149                             let expr3_0 = C::output(ctx, expr2_0);
4150                             return Some(expr3_0);
4151                         }
4152                         &Opcode::BandNot => {
4153                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4154                             // Rule at src/isa/aarch64/lower.isle line 628.
4155                             let expr0_0 = ALUOp::AndNot;
4156                             let expr1_0: Type = I64;
4157                             let expr2_0 = constructor_i128_alu_bitop(
4158                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4159                             )?;
4160                             let expr3_0 = C::output(ctx, expr2_0);
4161                             return Some(expr3_0);
4162                         }
4163                         &Opcode::BorNot => {
4164                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4165                             // Rule at src/isa/aarch64/lower.isle line 641.
4166                             let expr0_0 = ALUOp::OrrNot;
4167                             let expr1_0: Type = I64;
4168                             let expr2_0 = constructor_i128_alu_bitop(
4169                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4170                             )?;
4171                             let expr3_0 = C::output(ctx, expr2_0);
4172                             return Some(expr3_0);
4173                         }
4174                         &Opcode::BxorNot => {
4175                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4176                             // Rule at src/isa/aarch64/lower.isle line 651.
4177                             let expr0_0 = ALUOp::EorNot;
4178                             let expr1_0: Type = I64;
4179                             let expr2_0 = constructor_i128_alu_bitop(
4180                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4181                             )?;
4182                             let expr3_0 = C::output(ctx, expr2_0);
4183                             return Some(expr3_0);
4184                         }
4185                         &Opcode::Rotl => {
4186                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4187                             // Rule at src/isa/aarch64/lower.isle line 878.
4188                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4189                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4190                             let expr2_0: usize = 0;
4191                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4192                             let expr4_0: Type = I64;
4193                             let expr5_0: Type = I64;
4194                             let expr6_0: u64 = 128;
4195                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4196                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4197                             let expr9_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4198                             let expr10_0 = constructor_lower_ushr128(ctx, expr0_0, expr8_0)?;
4199                             let expr11_0: Type = I64;
4200                             let expr12_0: usize = 0;
4201                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4202                             let expr14_0: usize = 0;
4203                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4204                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4205                             let expr17_0: Type = I64;
4206                             let expr18_0: usize = 1;
4207                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4208                             let expr20_0: usize = 1;
4209                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4210                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4211                             let expr23_0 = C::value_regs(ctx, expr16_0, expr22_0);
4212                             let expr24_0 = C::output(ctx, expr23_0);
4213                             return Some(expr24_0);
4214                         }
4215                         &Opcode::Rotr => {
4216                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4217                             // Rule at src/isa/aarch64/lower.isle line 959.
4218                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4219                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4220                             let expr2_0: usize = 0;
4221                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4222                             let expr4_0: Type = I64;
4223                             let expr5_0: Type = I64;
4224                             let expr6_0: u64 = 128;
4225                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4226                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4227                             let expr9_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4228                             let expr10_0 = constructor_lower_shl128(ctx, expr0_0, expr8_0)?;
4229                             let expr11_0: Type = I64;
4230                             let expr12_0: usize = 1;
4231                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4232                             let expr14_0: usize = 1;
4233                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4234                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4235                             let expr17_0: Type = I64;
4236                             let expr18_0: usize = 0;
4237                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4238                             let expr20_0: usize = 0;
4239                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4240                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4241                             let expr23_0 = C::value_regs(ctx, expr22_0, expr16_0);
4242                             let expr24_0 = C::output(ctx, expr23_0);
4243                             return Some(expr24_0);
4244                         }
4245                         &Opcode::Ishl => {
4246                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4247                             // Rule at src/isa/aarch64/lower.isle line 664.
4248                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4249                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4250                             let expr2_0: usize = 0;
4251                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4252                             let expr4_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4253                             let expr5_0 = C::output(ctx, expr4_0);
4254                             return Some(expr5_0);
4255                         }
4256                         &Opcode::Ushr => {
4257                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4258                             // Rule at src/isa/aarch64/lower.isle line 748.
4259                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4260                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4261                             let expr2_0: usize = 0;
4262                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4263                             let expr4_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4264                             let expr5_0 = C::output(ctx, expr4_0);
4265                             return Some(expr5_0);
4266                         }
4267                         &Opcode::Sshr => {
4268                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4269                             // Rule at src/isa/aarch64/lower.isle line 795.
4270                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4271                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4272                             let expr2_0: usize = 0;
4273                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4274                             let expr4_0 = constructor_lower_sshr128(ctx, expr0_0, expr3_0)?;
4275                             let expr5_0 = C::output(ctx, expr4_0);
4276                             return Some(expr5_0);
4277                         }
4278                         _ => {}
4279                     }
4280                 }
4281                 &InstructionData::Unary {
4282                     opcode: ref pattern5_0,
4283                     arg: pattern5_1,
4284                 } => {
4285                     match pattern5_0 {
4286                         &Opcode::Bnot => {
4287                             // Rule at src/isa/aarch64/lower.isle line 569.
4288                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4289                             let expr1_0: usize = 0;
4290                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4291                             let expr3_0: usize = 1;
4292                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4293                             let expr5_0: Type = I64;
4294                             let expr6_0 = C::zero_reg(ctx);
4295                             let expr7_0 = constructor_orr_not(ctx, expr5_0, expr6_0, expr2_0)?;
4296                             let expr8_0: Type = I64;
4297                             let expr9_0 = C::zero_reg(ctx);
4298                             let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, expr4_0)?;
4299                             let expr11_0 = C::value_regs(ctx, expr7_0, expr10_0);
4300                             let expr12_0 = C::output(ctx, expr11_0);
4301                             return Some(expr12_0);
4302                         }
4303                         &Opcode::Bitrev => {
4304                             // Rule at src/isa/aarch64/lower.isle line 983.
4305                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4306                             let expr1_0: Type = I64;
4307                             let expr2_0: usize = 0;
4308                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4309                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4310                             let expr5_0: Type = I64;
4311                             let expr6_0: usize = 1;
4312                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4313                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4314                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4315                             let expr10_0 = C::output(ctx, expr9_0);
4316                             return Some(expr10_0);
4317                         }
4318                         &Opcode::Clz => {
4319                             // Rule at src/isa/aarch64/lower.isle line 1001.
4320                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4321                             let expr1_0 = constructor_lower_clz128(ctx, expr0_0)?;
4322                             let expr2_0 = C::output(ctx, expr1_0);
4323                             return Some(expr2_0);
4324                         }
4325                         &Opcode::Cls => {
4326                             // Rule at src/isa/aarch64/lower.isle line 1057.
4327                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4328                             let expr1_0: usize = 0;
4329                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4330                             let expr3_0: usize = 1;
4331                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4332                             let expr5_0: Type = I64;
4333                             let expr6_0 = constructor_a64_cls(ctx, expr5_0, expr2_0)?;
4334                             let expr7_0: Type = I64;
4335                             let expr8_0 = constructor_a64_cls(ctx, expr7_0, expr4_0)?;
4336                             let expr9_0: Type = I64;
4337                             let expr10_0 = constructor_eon(ctx, expr9_0, expr4_0, expr2_0)?;
4338                             let expr11_0: Type = I64;
4339                             let expr12_0: u8 = 63;
4340                             let expr13_0 = C::imm_shift_from_u8(ctx, expr12_0);
4341                             let expr14_0 = constructor_lsr_imm(ctx, expr11_0, expr10_0, expr13_0)?;
4342                             let expr15_0 = constructor_madd64(ctx, expr6_0, expr14_0, expr14_0)?;
4343                             let expr16_0: u8 = 63;
4344                             let expr17_0 = C::u8_into_imm12(ctx, expr16_0);
4345                             let expr18_0 = constructor_cmp64_imm(ctx, expr8_0, expr17_0)?;
4346                             let expr19_0 = Cond::Eq;
4347                             let expr20_0 = C::zero_reg(ctx);
4348                             let expr21_0 = constructor_csel(ctx, &expr19_0, expr15_0, expr20_0)?;
4349                             let expr22_0 = constructor_with_flags_reg(ctx, &expr18_0, &expr21_0)?;
4350                             let expr23_0: Type = I64;
4351                             let expr24_0 = constructor_add(ctx, expr23_0, expr22_0, expr8_0)?;
4352                             let expr25_0: Type = I64;
4353                             let expr26_0: u64 = 0;
4354                             let expr27_0 = constructor_imm(ctx, expr25_0, expr26_0)?;
4355                             let expr28_0 = C::value_regs(ctx, expr24_0, expr27_0);
4356                             let expr29_0 = C::output(ctx, expr28_0);
4357                             return Some(expr29_0);
4358                         }
4359                         &Opcode::Ctz => {
4360                             // Rule at src/isa/aarch64/lower.isle line 1031.
4361                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4362                             let expr1_0: Type = I64;
4363                             let expr2_0: usize = 0;
4364                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4365                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4366                             let expr5_0: Type = I64;
4367                             let expr6_0: usize = 1;
4368                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4369                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4370                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4371                             let expr10_0 = constructor_lower_clz128(ctx, expr9_0)?;
4372                             let expr11_0 = C::output(ctx, expr10_0);
4373                             return Some(expr11_0);
4374                         }
4375                         &Opcode::Popcnt => {
4376                             // Rule at src/isa/aarch64/lower.isle line 1117.
4377                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4378                             let expr1_0: usize = 0;
4379                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4380                             let expr3_0 = ScalarSize::Size64;
4381                             let expr4_0 = constructor_mov_to_fpu(ctx, expr2_0, &expr3_0)?;
4382                             let expr5_0: usize = 1;
4383                             let expr6_0 = C::value_regs_get(ctx, expr0_0, expr5_0);
4384                             let expr7_0: u8 = 1;
4385                             let expr8_0 = VectorSize::Size64x2;
4386                             let expr9_0 =
4387                                 constructor_mov_to_vec(ctx, expr4_0, expr6_0, expr7_0, &expr8_0)?;
4388                             let expr10_0 = VectorSize::Size8x16;
4389                             let expr11_0 = constructor_vec_cnt(ctx, expr9_0, &expr10_0)?;
4390                             let expr12_0 = VectorSize::Size8x16;
4391                             let expr13_0 = constructor_addv(ctx, expr11_0, &expr12_0)?;
4392                             let expr14_0: u8 = 0;
4393                             let expr15_0 = VectorSize::Size8x16;
4394                             let expr16_0 =
4395                                 constructor_mov_from_vec(ctx, expr13_0, expr14_0, &expr15_0)?;
4396                             let expr17_0: Type = I64;
4397                             let expr18_0: u64 = 0;
4398                             let expr19_0 = constructor_imm(ctx, expr17_0, expr18_0)?;
4399                             let expr20_0 = C::value_regs(ctx, expr16_0, expr19_0);
4400                             let expr21_0 = C::output(ctx, expr20_0);
4401                             return Some(expr21_0);
4402                         }
4403                         &Opcode::Uextend => {
4404                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4405                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4406                                 if let &InstructionData::BinaryImm8 {
4407                                     opcode: ref pattern9_0,
4408                                     arg: pattern9_1,
4409                                     imm: pattern9_2,
4410                                 } = &pattern8_0
4411                                 {
4412                                     if let &Opcode::Extractlane = pattern9_0 {
4413                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4414                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
4415                                         // Rule at src/isa/aarch64/lower.isle line 499.
4416                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4417                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
4418                                         let expr2_0 = constructor_mov_from_vec(
4419                                             ctx,
4420                                             expr0_0,
4421                                             pattern12_0,
4422                                             &expr1_0,
4423                                         )?;
4424                                         let expr3_0: Type = I64;
4425                                         let expr4_0: u64 = 0;
4426                                         let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
4427                                         let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
4428                                         let expr7_0 = C::output(ctx, expr6_0);
4429                                         return Some(expr7_0);
4430                                     }
4431                                 }
4432                             }
4433                             // Rule at src/isa/aarch64/lower.isle line 494.
4434                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
4435                             let expr1_0: Type = I64;
4436                             let expr2_0: u64 = 0;
4437                             let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
4438                             let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
4439                             let expr5_0 = C::output(ctx, expr4_0);
4440                             return Some(expr5_0);
4441                         }
4442                         &Opcode::Sextend => {
4443                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4444                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4445                                 if let &InstructionData::BinaryImm8 {
4446                                     opcode: ref pattern9_0,
4447                                     arg: pattern9_1,
4448                                     imm: pattern9_2,
4449                                 } = &pattern8_0
4450                                 {
4451                                     if let &Opcode::Extractlane = pattern9_0 {
4452                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4453                                         if pattern11_0 == I64X2 {
4454                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4455                                             // Rule at src/isa/aarch64/lower.isle line 543.
4456                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4457                                             let expr1_0 = VectorSize::Size64x2;
4458                                             let expr2_0 = constructor_mov_from_vec(
4459                                                 ctx,
4460                                                 expr0_0,
4461                                                 pattern13_0,
4462                                                 &expr1_0,
4463                                             )?;
4464                                             let expr3_0: Type = I64;
4465                                             let expr4_0: u8 = 63;
4466                                             let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
4467                                             let expr6_0 = constructor_asr_imm(
4468                                                 ctx, expr3_0, expr2_0, expr5_0,
4469                                             )?;
4470                                             let expr7_0 = C::value_regs(ctx, expr2_0, expr6_0);
4471                                             let expr8_0 = C::output(ctx, expr7_0);
4472                                             return Some(expr8_0);
4473                                         }
4474                                         if let Some(()) = C::not_i64x2(ctx, pattern11_0) {
4475                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4476                                             // Rule at src/isa/aarch64/lower.isle line 532.
4477                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4478                                             let expr1_0 =
4479                                                 constructor_vector_size(ctx, pattern11_0)?;
4480                                             let expr2_0: Type = I64;
4481                                             let expr3_0 = constructor_size_from_ty(ctx, expr2_0)?;
4482                                             let expr4_0 = constructor_mov_from_vec_signed(
4483                                                 ctx,
4484                                                 expr0_0,
4485                                                 pattern13_0,
4486                                                 &expr1_0,
4487                                                 &expr3_0,
4488                                             )?;
4489                                             let expr5_0: Type = I64;
4490                                             let expr6_0: u8 = 63;
4491                                             let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
4492                                             let expr8_0 = constructor_asr_imm(
4493                                                 ctx, expr5_0, expr4_0, expr7_0,
4494                                             )?;
4495                                             let expr9_0 = C::value_regs(ctx, expr4_0, expr8_0);
4496                                             let expr10_0 = C::output(ctx, expr9_0);
4497                                             return Some(expr10_0);
4498                                         }
4499                                     }
4500                                 }
4501                             }
4502                             // Rule at src/isa/aarch64/lower.isle line 522.
4503                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
4504                             let expr1_0: Type = I64;
4505                             let expr2_0: u8 = 63;
4506                             let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0);
4507                             let expr4_0 = constructor_asr_imm(ctx, expr1_0, expr0_0, expr3_0)?;
4508                             let expr5_0 = C::value_regs(ctx, expr0_0, expr4_0);
4509                             let expr6_0 = C::output(ctx, expr5_0);
4510                             return Some(expr6_0);
4511                         }
4512                         _ => {}
4513                     }
4514                 }
4515                 _ => {}
4516             }
4517         }
4518         if pattern2_0 == I8X16 {
4519             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4520             if let &InstructionData::Unary {
4521                 opcode: ref pattern5_0,
4522                 arg: pattern5_1,
4523             } = &pattern4_0
4524             {
4525                 if let &Opcode::Popcnt = pattern5_0 {
4526                     // Rule at src/isa/aarch64/lower.isle line 1125.
4527                     let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4528                     let expr1_0 = VectorSize::Size8x16;
4529                     let expr2_0 = constructor_vec_cnt(ctx, expr0_0, &expr1_0)?;
4530                     let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4531                     return Some(expr3_0);
4532                 }
4533             }
4534         }
4535         if pattern2_0 == I16X8 {
4536             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4537             if let &InstructionData::Binary {
4538                 opcode: ref pattern5_0,
4539                 args: ref pattern5_1,
4540             } = &pattern4_0
4541             {
4542                 if let &Opcode::Imul = pattern5_0 {
4543                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4544                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4545                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4546                         if let &InstructionData::Unary {
4547                             opcode: ref pattern10_0,
4548                             arg: pattern10_1,
4549                         } = &pattern9_0
4550                         {
4551                             match pattern10_0 {
4552                                 &Opcode::SwidenLow => {
4553                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4554                                     if pattern12_0 == I8X16 {
4555                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4556                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4557                                             if let &InstructionData::Unary {
4558                                                 opcode: ref pattern16_0,
4559                                                 arg: pattern16_1,
4560                                             } = &pattern15_0
4561                                             {
4562                                                 if let &Opcode::SwidenLow = pattern16_0 {
4563                                                     let pattern18_0 =
4564                                                         C::value_type(ctx, pattern16_1);
4565                                                     if pattern18_0 == I8X16 {
4566                                                         // Rule at src/isa/aarch64/lower.isle line 282.
4567                                                         let expr0_0 =
4568                                                             C::put_in_reg(ctx, pattern10_1);
4569                                                         let expr1_0 =
4570                                                             C::put_in_reg(ctx, pattern16_1);
4571                                                         let expr2_0: bool = false;
4572                                                         let expr3_0 = constructor_smull8(
4573                                                             ctx, expr0_0, expr1_0, expr2_0,
4574                                                         )?;
4575                                                         let expr4_0 =
4576                                                             constructor_output_reg(ctx, expr3_0)?;
4577                                                         return Some(expr4_0);
4578                                                     }
4579                                                 }
4580                                             }
4581                                         }
4582                                     }
4583                                 }
4584                                 &Opcode::SwidenHigh => {
4585                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4586                                     if pattern12_0 == I8X16 {
4587                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4588                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4589                                             if let &InstructionData::Unary {
4590                                                 opcode: ref pattern16_0,
4591                                                 arg: pattern16_1,
4592                                             } = &pattern15_0
4593                                             {
4594                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4595                                                     let pattern18_0 =
4596                                                         C::value_type(ctx, pattern16_1);
4597                                                     if pattern18_0 == I8X16 {
4598                                                         // Rule at src/isa/aarch64/lower.isle line 288.
4599                                                         let expr0_0 =
4600                                                             C::put_in_reg(ctx, pattern10_1);
4601                                                         let expr1_0 =
4602                                                             C::put_in_reg(ctx, pattern16_1);
4603                                                         let expr2_0: bool = true;
4604                                                         let expr3_0 = constructor_smull8(
4605                                                             ctx, expr0_0, expr1_0, expr2_0,
4606                                                         )?;
4607                                                         let expr4_0 =
4608                                                             constructor_output_reg(ctx, expr3_0)?;
4609                                                         return Some(expr4_0);
4610                                                     }
4611                                                 }
4612                                             }
4613                                         }
4614                                     }
4615                                 }
4616                                 &Opcode::UwidenLow => {
4617                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4618                                     if pattern12_0 == I8X16 {
4619                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4620                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4621                                             if let &InstructionData::Unary {
4622                                                 opcode: ref pattern16_0,
4623                                                 arg: pattern16_1,
4624                                             } = &pattern15_0
4625                                             {
4626                                                 if let &Opcode::UwidenLow = pattern16_0 {
4627                                                     let pattern18_0 =
4628                                                         C::value_type(ctx, pattern16_1);
4629                                                     if pattern18_0 == I8X16 {
4630                                                         // Rule at src/isa/aarch64/lower.isle line 294.
4631                                                         let expr0_0 =
4632                                                             C::put_in_reg(ctx, pattern10_1);
4633                                                         let expr1_0 =
4634                                                             C::put_in_reg(ctx, pattern16_1);
4635                                                         let expr2_0: bool = false;
4636                                                         let expr3_0 = constructor_umull8(
4637                                                             ctx, expr0_0, expr1_0, expr2_0,
4638                                                         )?;
4639                                                         let expr4_0 =
4640                                                             constructor_output_reg(ctx, expr3_0)?;
4641                                                         return Some(expr4_0);
4642                                                     }
4643                                                 }
4644                                             }
4645                                         }
4646                                     }
4647                                 }
4648                                 &Opcode::UwidenHigh => {
4649                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4650                                     if pattern12_0 == I8X16 {
4651                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4652                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4653                                             if let &InstructionData::Unary {
4654                                                 opcode: ref pattern16_0,
4655                                                 arg: pattern16_1,
4656                                             } = &pattern15_0
4657                                             {
4658                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4659                                                     let pattern18_0 =
4660                                                         C::value_type(ctx, pattern16_1);
4661                                                     if pattern18_0 == I8X16 {
4662                                                         // Rule at src/isa/aarch64/lower.isle line 300.
4663                                                         let expr0_0 =
4664                                                             C::put_in_reg(ctx, pattern10_1);
4665                                                         let expr1_0 =
4666                                                             C::put_in_reg(ctx, pattern16_1);
4667                                                         let expr2_0: bool = true;
4668                                                         let expr3_0 = constructor_umull8(
4669                                                             ctx, expr0_0, expr1_0, expr2_0,
4670                                                         )?;
4671                                                         let expr4_0 =
4672                                                             constructor_output_reg(ctx, expr3_0)?;
4673                                                         return Some(expr4_0);
4674                                                     }
4675                                                 }
4676                                             }
4677                                         }
4678                                     }
4679                                 }
4680                                 _ => {}
4681                             }
4682                         }
4683                     }
4684                 }
4685             }
4686         }
4687         if pattern2_0 == I32X4 {
4688             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4689             if let &InstructionData::Binary {
4690                 opcode: ref pattern5_0,
4691                 args: ref pattern5_1,
4692             } = &pattern4_0
4693             {
4694                 if let &Opcode::Imul = pattern5_0 {
4695                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4696                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4697                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4698                         if let &InstructionData::Unary {
4699                             opcode: ref pattern10_0,
4700                             arg: pattern10_1,
4701                         } = &pattern9_0
4702                         {
4703                             match pattern10_0 {
4704                                 &Opcode::SwidenLow => {
4705                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4706                                     if pattern12_0 == I16X8 {
4707                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4708                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4709                                             if let &InstructionData::Unary {
4710                                                 opcode: ref pattern16_0,
4711                                                 arg: pattern16_1,
4712                                             } = &pattern15_0
4713                                             {
4714                                                 if let &Opcode::SwidenLow = pattern16_0 {
4715                                                     let pattern18_0 =
4716                                                         C::value_type(ctx, pattern16_1);
4717                                                     if pattern18_0 == I16X8 {
4718                                                         // Rule at src/isa/aarch64/lower.isle line 306.
4719                                                         let expr0_0 =
4720                                                             C::put_in_reg(ctx, pattern10_1);
4721                                                         let expr1_0 =
4722                                                             C::put_in_reg(ctx, pattern16_1);
4723                                                         let expr2_0: bool = false;
4724                                                         let expr3_0 = constructor_smull16(
4725                                                             ctx, expr0_0, expr1_0, expr2_0,
4726                                                         )?;
4727                                                         let expr4_0 =
4728                                                             constructor_output_reg(ctx, expr3_0)?;
4729                                                         return Some(expr4_0);
4730                                                     }
4731                                                 }
4732                                             }
4733                                         }
4734                                     }
4735                                 }
4736                                 &Opcode::SwidenHigh => {
4737                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4738                                     if pattern12_0 == I16X8 {
4739                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4740                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4741                                             if let &InstructionData::Unary {
4742                                                 opcode: ref pattern16_0,
4743                                                 arg: pattern16_1,
4744                                             } = &pattern15_0
4745                                             {
4746                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4747                                                     let pattern18_0 =
4748                                                         C::value_type(ctx, pattern16_1);
4749                                                     if pattern18_0 == I16X8 {
4750                                                         // Rule at src/isa/aarch64/lower.isle line 312.
4751                                                         let expr0_0 =
4752                                                             C::put_in_reg(ctx, pattern10_1);
4753                                                         let expr1_0 =
4754                                                             C::put_in_reg(ctx, pattern16_1);
4755                                                         let expr2_0: bool = true;
4756                                                         let expr3_0 = constructor_smull16(
4757                                                             ctx, expr0_0, expr1_0, expr2_0,
4758                                                         )?;
4759                                                         let expr4_0 =
4760                                                             constructor_output_reg(ctx, expr3_0)?;
4761                                                         return Some(expr4_0);
4762                                                     }
4763                                                 }
4764                                             }
4765                                         }
4766                                     }
4767                                 }
4768                                 &Opcode::UwidenLow => {
4769                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4770                                     if pattern12_0 == I16X8 {
4771                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4772                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4773                                             if let &InstructionData::Unary {
4774                                                 opcode: ref pattern16_0,
4775                                                 arg: pattern16_1,
4776                                             } = &pattern15_0
4777                                             {
4778                                                 if let &Opcode::UwidenLow = pattern16_0 {
4779                                                     let pattern18_0 =
4780                                                         C::value_type(ctx, pattern16_1);
4781                                                     if pattern18_0 == I16X8 {
4782                                                         // Rule at src/isa/aarch64/lower.isle line 318.
4783                                                         let expr0_0 =
4784                                                             C::put_in_reg(ctx, pattern10_1);
4785                                                         let expr1_0 =
4786                                                             C::put_in_reg(ctx, pattern16_1);
4787                                                         let expr2_0: bool = false;
4788                                                         let expr3_0 = constructor_umull16(
4789                                                             ctx, expr0_0, expr1_0, expr2_0,
4790                                                         )?;
4791                                                         let expr4_0 =
4792                                                             constructor_output_reg(ctx, expr3_0)?;
4793                                                         return Some(expr4_0);
4794                                                     }
4795                                                 }
4796                                             }
4797                                         }
4798                                     }
4799                                 }
4800                                 &Opcode::UwidenHigh => {
4801                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4802                                     if pattern12_0 == I16X8 {
4803                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4804                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4805                                             if let &InstructionData::Unary {
4806                                                 opcode: ref pattern16_0,
4807                                                 arg: pattern16_1,
4808                                             } = &pattern15_0
4809                                             {
4810                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4811                                                     let pattern18_0 =
4812                                                         C::value_type(ctx, pattern16_1);
4813                                                     if pattern18_0 == I16X8 {
4814                                                         // Rule at src/isa/aarch64/lower.isle line 324.
4815                                                         let expr0_0 =
4816                                                             C::put_in_reg(ctx, pattern10_1);
4817                                                         let expr1_0 =
4818                                                             C::put_in_reg(ctx, pattern16_1);
4819                                                         let expr2_0: bool = true;
4820                                                         let expr3_0 = constructor_umull16(
4821                                                             ctx, expr0_0, expr1_0, expr2_0,
4822                                                         )?;
4823                                                         let expr4_0 =
4824                                                             constructor_output_reg(ctx, expr3_0)?;
4825                                                         return Some(expr4_0);
4826                                                     }
4827                                                 }
4828                                             }
4829                                         }
4830                                     }
4831                                 }
4832                                 _ => {}
4833                             }
4834                         }
4835                     }
4836                 }
4837             }
4838         }
4839         if pattern2_0 == I64X2 {
4840             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4841             if let &InstructionData::Binary {
4842                 opcode: ref pattern5_0,
4843                 args: ref pattern5_1,
4844             } = &pattern4_0
4845             {
4846                 if let &Opcode::Imul = pattern5_0 {
4847                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4848                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4849                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4850                         if let &InstructionData::Unary {
4851                             opcode: ref pattern10_0,
4852                             arg: pattern10_1,
4853                         } = &pattern9_0
4854                         {
4855                             match pattern10_0 {
4856                                 &Opcode::SwidenLow => {
4857                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4858                                     if pattern12_0 == I32X4 {
4859                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4860                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4861                                             if let &InstructionData::Unary {
4862                                                 opcode: ref pattern16_0,
4863                                                 arg: pattern16_1,
4864                                             } = &pattern15_0
4865                                             {
4866                                                 if let &Opcode::SwidenLow = pattern16_0 {
4867                                                     let pattern18_0 =
4868                                                         C::value_type(ctx, pattern16_1);
4869                                                     if pattern18_0 == I32X4 {
4870                                                         // Rule at src/isa/aarch64/lower.isle line 330.
4871                                                         let expr0_0 =
4872                                                             C::put_in_reg(ctx, pattern10_1);
4873                                                         let expr1_0 =
4874                                                             C::put_in_reg(ctx, pattern16_1);
4875                                                         let expr2_0: bool = false;
4876                                                         let expr3_0 = constructor_smull32(
4877                                                             ctx, expr0_0, expr1_0, expr2_0,
4878                                                         )?;
4879                                                         let expr4_0 =
4880                                                             constructor_output_reg(ctx, expr3_0)?;
4881                                                         return Some(expr4_0);
4882                                                     }
4883                                                 }
4884                                             }
4885                                         }
4886                                     }
4887                                 }
4888                                 &Opcode::SwidenHigh => {
4889                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4890                                     if pattern12_0 == I32X4 {
4891                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4892                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4893                                             if let &InstructionData::Unary {
4894                                                 opcode: ref pattern16_0,
4895                                                 arg: pattern16_1,
4896                                             } = &pattern15_0
4897                                             {
4898                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4899                                                     let pattern18_0 =
4900                                                         C::value_type(ctx, pattern16_1);
4901                                                     if pattern18_0 == I32X4 {
4902                                                         // Rule at src/isa/aarch64/lower.isle line 336.
4903                                                         let expr0_0 =
4904                                                             C::put_in_reg(ctx, pattern10_1);
4905                                                         let expr1_0 =
4906                                                             C::put_in_reg(ctx, pattern16_1);
4907                                                         let expr2_0: bool = true;
4908                                                         let expr3_0 = constructor_smull32(
4909                                                             ctx, expr0_0, expr1_0, expr2_0,
4910                                                         )?;
4911                                                         let expr4_0 =
4912                                                             constructor_output_reg(ctx, expr3_0)?;
4913                                                         return Some(expr4_0);
4914                                                     }
4915                                                 }
4916                                             }
4917                                         }
4918                                     }
4919                                 }
4920                                 &Opcode::UwidenLow => {
4921                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4922                                     if pattern12_0 == I32X4 {
4923                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4924                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4925                                             if let &InstructionData::Unary {
4926                                                 opcode: ref pattern16_0,
4927                                                 arg: pattern16_1,
4928                                             } = &pattern15_0
4929                                             {
4930                                                 if let &Opcode::UwidenLow = pattern16_0 {
4931                                                     let pattern18_0 =
4932                                                         C::value_type(ctx, pattern16_1);
4933                                                     if pattern18_0 == I32X4 {
4934                                                         // Rule at src/isa/aarch64/lower.isle line 342.
4935                                                         let expr0_0 =
4936                                                             C::put_in_reg(ctx, pattern10_1);
4937                                                         let expr1_0 =
4938                                                             C::put_in_reg(ctx, pattern16_1);
4939                                                         let expr2_0: bool = false;
4940                                                         let expr3_0 = constructor_umull32(
4941                                                             ctx, expr0_0, expr1_0, expr2_0,
4942                                                         )?;
4943                                                         let expr4_0 =
4944                                                             constructor_output_reg(ctx, expr3_0)?;
4945                                                         return Some(expr4_0);
4946                                                     }
4947                                                 }
4948                                             }
4949                                         }
4950                                     }
4951                                 }
4952                                 &Opcode::UwidenHigh => {
4953                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4954                                     if pattern12_0 == I32X4 {
4955                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4956                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4957                                             if let &InstructionData::Unary {
4958                                                 opcode: ref pattern16_0,
4959                                                 arg: pattern16_1,
4960                                             } = &pattern15_0
4961                                             {
4962                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4963                                                     let pattern18_0 =
4964                                                         C::value_type(ctx, pattern16_1);
4965                                                     if pattern18_0 == I32X4 {
4966                                                         // Rule at src/isa/aarch64/lower.isle line 348.
4967                                                         let expr0_0 =
4968                                                             C::put_in_reg(ctx, pattern10_1);
4969                                                         let expr1_0 =
4970                                                             C::put_in_reg(ctx, pattern16_1);
4971                                                         let expr2_0: bool = true;
4972                                                         let expr3_0 = constructor_umull32(
4973                                                             ctx, expr0_0, expr1_0, expr2_0,
4974                                                         )?;
4975                                                         let expr4_0 =
4976                                                             constructor_output_reg(ctx, expr3_0)?;
4977                                                         return Some(expr4_0);
4978                                                     }
4979                                                 }
4980                                             }
4981                                         }
4982                                     }
4983                                 }
4984                                 _ => {}
4985                             }
4986                         }
4987                     }
4988                     // Rule at src/isa/aarch64/lower.isle line 243.
4989                     let expr0_0 = C::put_in_reg(ctx, pattern7_0);
4990                     let expr1_0 = C::put_in_reg(ctx, pattern7_1);
4991                     let expr2_0 = VectorSize::Size32x4;
4992                     let expr3_0 = constructor_rev64(ctx, expr1_0, &expr2_0)?;
4993                     let expr4_0 = VectorSize::Size32x4;
4994                     let expr5_0 = constructor_mul(ctx, expr3_0, expr0_0, &expr4_0)?;
4995                     let expr6_0: bool = false;
4996                     let expr7_0 = constructor_xtn64(ctx, expr0_0, expr6_0)?;
4997                     let expr8_0 = VectorSize::Size32x4;
4998                     let expr9_0 = constructor_addp(ctx, expr5_0, expr5_0, &expr8_0)?;
4999                     let expr10_0: bool = false;
5000                     let expr11_0 = constructor_xtn64(ctx, expr1_0, expr10_0)?;
5001                     let expr12_0: bool = false;
5002                     let expr13_0 = constructor_shll32(ctx, expr9_0, expr12_0)?;
5003                     let expr14_0: bool = false;
5004                     let expr15_0 = constructor_umlal32(ctx, expr13_0, expr11_0, expr7_0, expr14_0)?;
5005                     let expr16_0 = constructor_output_reg(ctx, expr15_0)?;
5006                     return Some(expr16_0);
5007                 }
5008             }
5009         }
5010         let pattern3_0 = C::inst_data(ctx, pattern0_0);
5011         match &pattern3_0 {
5012             &InstructionData::NullAry {
5013                 opcode: ref pattern4_0,
5014             } => {
5015                 if let &Opcode::Null = pattern4_0 {
5016                     // Rule at src/isa/aarch64/lower.isle line 22.
5017                     let expr0_0: u64 = 0;
5018                     let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5019                     let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5020                     return Some(expr2_0);
5021                 }
5022             }
5023             &InstructionData::UnaryImm {
5024                 opcode: ref pattern4_0,
5025                 imm: pattern4_1,
5026             } => {
5027                 if let &Opcode::Iconst = pattern4_0 {
5028                     let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1);
5029                     // Rule at src/isa/aarch64/lower.isle line 9.
5030                     let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?;
5031                     let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
5032                     return Some(expr1_0);
5033                 }
5034             }
5035             &InstructionData::UnaryBool {
5036                 opcode: ref pattern4_0,
5037                 imm: pattern4_1,
5038             } => {
5039                 if let &Opcode::Bconst = pattern4_0 {
5040                     if pattern4_1 == true {
5041                         // Rule at src/isa/aarch64/lower.isle line 17.
5042                         let expr0_0: u64 = 1;
5043                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5044                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5045                         return Some(expr2_0);
5046                     }
5047                     if pattern4_1 == false {
5048                         // Rule at src/isa/aarch64/lower.isle line 14.
5049                         let expr0_0: u64 = 0;
5050                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5051                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5052                         return Some(expr2_0);
5053                     }
5054                 }
5055             }
5056             &InstructionData::Unary {
5057                 opcode: ref pattern4_0,
5058                 arg: pattern4_1,
5059             } => {
5060                 match pattern4_0 {
5061                     &Opcode::Bitrev => {
5062                         // Rule at src/isa/aarch64/lower.isle line 989.
5063                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5064                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5065                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5066                         return Some(expr2_0);
5067                     }
5068                     &Opcode::Clz => {
5069                         // Rule at src/isa/aarch64/lower.isle line 1004.
5070                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5071                         let expr1_0 = constructor_a64_clz(ctx, pattern2_0, expr0_0)?;
5072                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5073                         return Some(expr2_0);
5074                     }
5075                     &Opcode::Cls => {
5076                         // Rule at src/isa/aarch64/lower.isle line 1071.
5077                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5078                         let expr1_0 = constructor_a64_cls(ctx, pattern2_0, expr0_0)?;
5079                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5080                         return Some(expr2_0);
5081                     }
5082                     &Opcode::Ctz => {
5083                         // Rule at src/isa/aarch64/lower.isle line 1037.
5084                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5085                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5086                         let expr2_0 = constructor_a64_clz(ctx, pattern2_0, expr1_0)?;
5087                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5088                         return Some(expr3_0);
5089                     }
5090                     _ => {}
5091                 }
5092             }
5093             _ => {}
5094         }
5095         if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) {
5096             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5097             if let &InstructionData::Binary {
5098                 opcode: ref pattern5_0,
5099                 args: ref pattern5_1,
5100             } = &pattern4_0
5101             {
5102                 match pattern5_0 {
5103                     &Opcode::Iadd => {
5104                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5105                         // Rule at src/isa/aarch64/lower.isle line 75.
5106                         let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5107                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5108                         let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5109                         let expr3_0 = constructor_add_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5110                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5111                         return Some(expr4_0);
5112                     }
5113                     &Opcode::Isub => {
5114                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5115                         // Rule at src/isa/aarch64/lower.isle line 125.
5116                         let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5117                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5118                         let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5119                         let expr3_0 = constructor_sub_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5120                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5121                         return Some(expr4_0);
5122                     }
5123                     _ => {}
5124                 }
5125             }
5126         }
5127         if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
5128             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5129             if let &InstructionData::Binary {
5130                 opcode: ref pattern5_0,
5131                 args: ref pattern5_1,
5132             } = &pattern4_0
5133             {
5134                 match pattern5_0 {
5135                     &Opcode::Rotl => {
5136                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5137                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5138                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5139                             if let &InstructionData::UnaryImm {
5140                                 opcode: ref pattern10_0,
5141                                 imm: pattern10_1,
5142                             } = &pattern9_0
5143                             {
5144                                 if let &Opcode::Iconst = pattern10_0 {
5145                                     let closure12 = || {
5146                                         return Some(pattern3_0);
5147                                     };
5148                                     if let Some(pattern12_0) = closure12() {
5149                                         if let Some(pattern13_0) =
5150                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5151                                         {
5152                                             // Rule at src/isa/aarch64/lower.isle line 843.
5153                                             let expr0_0 =
5154                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5155                                             let expr1_0 =
5156                                                 C::negate_imm_shift(ctx, pattern3_0, pattern13_0);
5157                                             let expr2_0 = constructor_small_rotr_imm(
5158                                                 ctx, pattern3_0, expr0_0, expr1_0,
5159                                             )?;
5160                                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5161                                             return Some(expr3_0);
5162                                         }
5163                                     }
5164                                 }
5165                             }
5166                         }
5167                         // Rule at src/isa/aarch64/lower.isle line 838.
5168                         let expr0_0: Type = I32;
5169                         let expr1_0 = C::zero_reg(ctx);
5170                         let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5171                         let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
5172                         let expr4_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5173                         let expr5_0 = constructor_small_rotr(ctx, pattern3_0, expr4_0, expr3_0)?;
5174                         let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
5175                         return Some(expr6_0);
5176                     }
5177                     &Opcode::Rotr => {
5178                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5179                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5180                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5181                             if let &InstructionData::UnaryImm {
5182                                 opcode: ref pattern10_0,
5183                                 imm: pattern10_1,
5184                             } = &pattern9_0
5185                             {
5186                                 if let &Opcode::Iconst = pattern10_0 {
5187                                     let closure12 = || {
5188                                         return Some(pattern3_0);
5189                                     };
5190                                     if let Some(pattern12_0) = closure12() {
5191                                         if let Some(pattern13_0) =
5192                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5193                                         {
5194                                             // Rule at src/isa/aarch64/lower.isle line 903.
5195                                             let expr0_0 =
5196                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5197                                             let expr1_0 = constructor_small_rotr_imm(
5198                                                 ctx,
5199                                                 pattern3_0,
5200                                                 expr0_0,
5201                                                 pattern13_0,
5202                                             )?;
5203                                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5204                                             return Some(expr2_0);
5205                                         }
5206                                     }
5207                                 }
5208                             }
5209                         }
5210                         // Rule at src/isa/aarch64/lower.isle line 891.
5211                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5212                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5213                         let expr2_0 = constructor_small_rotr(ctx, pattern3_0, expr0_0, expr1_0)?;
5214                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5215                         return Some(expr3_0);
5216                     }
5217                     _ => {}
5218                 }
5219             }
5220         }
5221         if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
5222             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5223             if let &InstructionData::Binary {
5224                 opcode: ref pattern5_0,
5225                 args: ref pattern5_1,
5226             } = &pattern4_0
5227             {
5228                 match pattern5_0 {
5229                     &Opcode::Umulhi => {
5230                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5231                         // Rule at src/isa/aarch64/lower.isle line 370.
5232                         let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5233                         let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?;
5234                         let expr2_0 = C::zero_reg(ctx);
5235                         let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
5236                         let expr4_0: Type = I64;
5237                         let expr5_0 = C::ty_bits(ctx, pattern3_0);
5238                         let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
5239                         let expr7_0 = constructor_lsr_imm(ctx, expr4_0, expr3_0, expr6_0)?;
5240                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
5241                         return Some(expr8_0);
5242                     }
5243                     &Opcode::Smulhi => {
5244                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5245                         // Rule at src/isa/aarch64/lower.isle line 358.
5246                         let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5247                         let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?;
5248                         let expr2_0 = C::zero_reg(ctx);
5249                         let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
5250                         let expr4_0: Type = I64;
5251                         let expr5_0 = C::ty_bits(ctx, pattern3_0);
5252                         let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
5253                         let expr7_0 = constructor_asr_imm(ctx, expr4_0, expr3_0, expr6_0)?;
5254                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
5255                         return Some(expr8_0);
5256                     }
5257                     &Opcode::Band => {
5258                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5259                         // Rule at src/isa/aarch64/lower.isle line 583.
5260                         let expr0_0 = ALUOp::And;
5261                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5262                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5263                         )?;
5264                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5265                         return Some(expr2_0);
5266                     }
5267                     &Opcode::Bor => {
5268                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5269                         // Rule at src/isa/aarch64/lower.isle line 596.
5270                         let expr0_0 = ALUOp::Orr;
5271                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5272                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5273                         )?;
5274                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5275                         return Some(expr2_0);
5276                     }
5277                     &Opcode::Bxor => {
5278                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5279                         // Rule at src/isa/aarch64/lower.isle line 609.
5280                         let expr0_0 = ALUOp::Eor;
5281                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5282                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5283                         )?;
5284                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5285                         return Some(expr2_0);
5286                     }
5287                     &Opcode::BandNot => {
5288                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5289                         // Rule at src/isa/aarch64/lower.isle line 622.
5290                         let expr0_0 = ALUOp::AndNot;
5291                         let expr1_0 = constructor_alu_rs_imm_logic(
5292                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5293                         )?;
5294                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5295                         return Some(expr2_0);
5296                     }
5297                     &Opcode::BorNot => {
5298                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5299                         // Rule at src/isa/aarch64/lower.isle line 635.
5300                         let expr0_0 = ALUOp::OrrNot;
5301                         let expr1_0 = constructor_alu_rs_imm_logic(
5302                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5303                         )?;
5304                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5305                         return Some(expr2_0);
5306                     }
5307                     &Opcode::BxorNot => {
5308                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5309                         // Rule at src/isa/aarch64/lower.isle line 645.
5310                         let expr0_0 = ALUOp::EorNot;
5311                         let expr1_0: Type = I32;
5312                         let expr2_0 = constructor_alu_rs_imm_logic(
5313                             ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
5314                         )?;
5315                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5316                         return Some(expr3_0);
5317                     }
5318                     &Opcode::Ishl => {
5319                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5320                         // Rule at src/isa/aarch64/lower.isle line 656.
5321                         let expr0_0 = ALUOp::Lsl;
5322                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
5323                         let expr2_0 =
5324                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5325                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5326                         return Some(expr3_0);
5327                     }
5328                     &Opcode::Ushr => {
5329                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5330                         // Rule at src/isa/aarch64/lower.isle line 740.
5331                         let expr0_0 = ALUOp::Lsr;
5332                         let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5333                         let expr2_0 =
5334                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5335                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5336                         return Some(expr3_0);
5337                     }
5338                     &Opcode::Sshr => {
5339                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5340                         // Rule at src/isa/aarch64/lower.isle line 787.
5341                         let expr0_0 = ALUOp::Asr;
5342                         let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
5343                         let expr2_0 =
5344                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5345                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5346                         return Some(expr3_0);
5347                     }
5348                     _ => {}
5349                 }
5350             }
5351         }
5352         if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
5353             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5354             match &pattern4_0 {
5355                 &InstructionData::Binary {
5356                     opcode: ref pattern5_0,
5357                     args: ref pattern5_1,
5358                 } => {
5359                     match pattern5_0 {
5360                         &Opcode::Iadd => {
5361                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5362                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5363                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5364                                 match &pattern9_0 {
5365                                     &InstructionData::UnaryImm {
5366                                         opcode: ref pattern10_0,
5367                                         imm: pattern10_1,
5368                                     } => {
5369                                         if let &Opcode::Iconst = pattern10_0 {
5370                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5371                                             if let Some(pattern13_0) =
5372                                                 C::imm12_from_u64(ctx, pattern12_0)
5373                                             {
5374                                                 // Rule at src/isa/aarch64/lower.isle line 37.
5375                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5376                                                 let expr1_0 = constructor_add_imm(
5377                                                     ctx,
5378                                                     pattern3_0,
5379                                                     expr0_0,
5380                                                     pattern13_0,
5381                                                 )?;
5382                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5383                                                 return Some(expr2_0);
5384                                             }
5385                                             if let Some(pattern13_0) =
5386                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5387                                             {
5388                                                 // Rule at src/isa/aarch64/lower.isle line 45.
5389                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5390                                                 let expr1_0 = constructor_sub_imm(
5391                                                     ctx,
5392                                                     pattern3_0,
5393                                                     expr0_0,
5394                                                     pattern13_0,
5395                                                 )?;
5396                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5397                                                 return Some(expr2_0);
5398                                             }
5399                                         }
5400                                     }
5401                                     &InstructionData::Binary {
5402                                         opcode: ref pattern10_0,
5403                                         args: ref pattern10_1,
5404                                     } => {
5405                                         match pattern10_0 {
5406                                             &Opcode::Imul => {
5407                                                 let (pattern12_0, pattern12_1) =
5408                                                     C::unpack_value_array_2(ctx, pattern10_1);
5409                                                 // Rule at src/isa/aarch64/lower.isle line 70.
5410                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5411                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5412                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5413                                                 let expr3_0 = constructor_madd(
5414                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5415                                                 )?;
5416                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5417                                                 return Some(expr4_0);
5418                                             }
5419                                             &Opcode::Ishl => {
5420                                                 let (pattern12_0, pattern12_1) =
5421                                                     C::unpack_value_array_2(ctx, pattern10_1);
5422                                                 if let Some(pattern13_0) =
5423                                                     C::def_inst(ctx, pattern12_1)
5424                                                 {
5425                                                     let pattern14_0 =
5426                                                         C::inst_data(ctx, pattern13_0);
5427                                                     if let &InstructionData::UnaryImm {
5428                                                         opcode: ref pattern15_0,
5429                                                         imm: pattern15_1,
5430                                                     } = &pattern14_0
5431                                                     {
5432                                                         if let &Opcode::Iconst = pattern15_0 {
5433                                                             let closure17 = || {
5434                                                                 return Some(pattern3_0);
5435                                                             };
5436                                                             if let Some(pattern17_0) = closure17() {
5437                                                                 if let Some(pattern18_0) =
5438                                                                     C::lshl_from_imm64(
5439                                                                         ctx,
5440                                                                         pattern15_1,
5441                                                                         pattern17_0,
5442                                                                     )
5443                                                                 {
5444                                                                     // Rule at src/isa/aarch64/lower.isle line 62.
5445                                                                     let expr0_0 = C::put_in_reg(
5446                                                                         ctx, pattern7_1,
5447                                                                     );
5448                                                                     let expr1_0 = C::put_in_reg(
5449                                                                         ctx,
5450                                                                         pattern12_0,
5451                                                                     );
5452                                                                     let expr2_0 =
5453                                                                         constructor_add_shift(
5454                                                                             ctx,
5455                                                                             pattern3_0,
5456                                                                             expr0_0,
5457                                                                             expr1_0,
5458                                                                             pattern18_0,
5459                                                                         )?;
5460                                                                     let expr3_0 =
5461                                                                         constructor_output_reg(
5462                                                                             ctx, expr2_0,
5463                                                                         )?;
5464                                                                     return Some(expr3_0);
5465                                                                 }
5466                                                             }
5467                                                         }
5468                                                     }
5469                                                 }
5470                                             }
5471                                             _ => {}
5472                                         }
5473                                     }
5474                                     _ => {}
5475                                 }
5476                             }
5477                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0)
5478                             {
5479                                 // Rule at src/isa/aarch64/lower.isle line 53.
5480                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5481                                 let expr1_0 =
5482                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5483                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5484                                 return Some(expr2_0);
5485                             }
5486                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5487                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5488                                 match &pattern9_0 {
5489                                     &InstructionData::UnaryImm {
5490                                         opcode: ref pattern10_0,
5491                                         imm: pattern10_1,
5492                                     } => {
5493                                         if let &Opcode::Iconst = pattern10_0 {
5494                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5495                                             if let Some(pattern13_0) =
5496                                                 C::imm12_from_u64(ctx, pattern12_0)
5497                                             {
5498                                                 // Rule at src/isa/aarch64/lower.isle line 34.
5499                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5500                                                 let expr1_0 = constructor_add_imm(
5501                                                     ctx,
5502                                                     pattern3_0,
5503                                                     expr0_0,
5504                                                     pattern13_0,
5505                                                 )?;
5506                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5507                                                 return Some(expr2_0);
5508                                             }
5509                                             if let Some(pattern13_0) =
5510                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5511                                             {
5512                                                 // Rule at src/isa/aarch64/lower.isle line 42.
5513                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5514                                                 let expr1_0 = constructor_sub_imm(
5515                                                     ctx,
5516                                                     pattern3_0,
5517                                                     expr0_0,
5518                                                     pattern13_0,
5519                                                 )?;
5520                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5521                                                 return Some(expr2_0);
5522                                             }
5523                                         }
5524                                     }
5525                                     &InstructionData::Binary {
5526                                         opcode: ref pattern10_0,
5527                                         args: ref pattern10_1,
5528                                     } => {
5529                                         match pattern10_0 {
5530                                             &Opcode::Imul => {
5531                                                 let (pattern12_0, pattern12_1) =
5532                                                     C::unpack_value_array_2(ctx, pattern10_1);
5533                                                 // Rule at src/isa/aarch64/lower.isle line 67.
5534                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5535                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5536                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
5537                                                 let expr3_0 = constructor_madd(
5538                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5539                                                 )?;
5540                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5541                                                 return Some(expr4_0);
5542                                             }
5543                                             &Opcode::Ishl => {
5544                                                 let (pattern12_0, pattern12_1) =
5545                                                     C::unpack_value_array_2(ctx, pattern10_1);
5546                                                 if let Some(pattern13_0) =
5547                                                     C::def_inst(ctx, pattern12_1)
5548                                                 {
5549                                                     let pattern14_0 =
5550                                                         C::inst_data(ctx, pattern13_0);
5551                                                     if let &InstructionData::UnaryImm {
5552                                                         opcode: ref pattern15_0,
5553                                                         imm: pattern15_1,
5554                                                     } = &pattern14_0
5555                                                     {
5556                                                         if let &Opcode::Iconst = pattern15_0 {
5557                                                             let closure17 = || {
5558                                                                 return Some(pattern3_0);
5559                                                             };
5560                                                             if let Some(pattern17_0) = closure17() {
5561                                                                 if let Some(pattern18_0) =
5562                                                                     C::lshl_from_imm64(
5563                                                                         ctx,
5564                                                                         pattern15_1,
5565                                                                         pattern17_0,
5566                                                                     )
5567                                                                 {
5568                                                                     // Rule at src/isa/aarch64/lower.isle line 58.
5569                                                                     let expr0_0 = C::put_in_reg(
5570                                                                         ctx, pattern7_0,
5571                                                                     );
5572                                                                     let expr1_0 = C::put_in_reg(
5573                                                                         ctx,
5574                                                                         pattern12_0,
5575                                                                     );
5576                                                                     let expr2_0 =
5577                                                                         constructor_add_shift(
5578                                                                             ctx,
5579                                                                             pattern3_0,
5580                                                                             expr0_0,
5581                                                                             expr1_0,
5582                                                                             pattern18_0,
5583                                                                         )?;
5584                                                                     let expr3_0 =
5585                                                                         constructor_output_reg(
5586                                                                             ctx, expr2_0,
5587                                                                         )?;
5588                                                                     return Some(expr3_0);
5589                                                                 }
5590                                                             }
5591                                                         }
5592                                                     }
5593                                                 }
5594                                             }
5595                                             _ => {}
5596                                         }
5597                                     }
5598                                     _ => {}
5599                                 }
5600                             }
5601                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
5602                             {
5603                                 // Rule at src/isa/aarch64/lower.isle line 50.
5604                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5605                                 let expr1_0 =
5606                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5607                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5608                                 return Some(expr2_0);
5609                             }
5610                             // Rule at src/isa/aarch64/lower.isle line 30.
5611                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5612                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5613                             let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, expr1_0)?;
5614                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5615                             return Some(expr3_0);
5616                         }
5617                         &Opcode::Isub => {
5618                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5619                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5620                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5621                                 match &pattern9_0 {
5622                                     &InstructionData::UnaryImm {
5623                                         opcode: ref pattern10_0,
5624                                         imm: pattern10_1,
5625                                     } => {
5626                                         if let &Opcode::Iconst = pattern10_0 {
5627                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5628                                             if let Some(pattern13_0) =
5629                                                 C::imm12_from_u64(ctx, pattern12_0)
5630                                             {
5631                                                 // Rule at src/isa/aarch64/lower.isle line 105.
5632                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5633                                                 let expr1_0 = constructor_sub_imm(
5634                                                     ctx,
5635                                                     pattern3_0,
5636                                                     expr0_0,
5637                                                     pattern13_0,
5638                                                 )?;
5639                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5640                                                 return Some(expr2_0);
5641                                             }
5642                                             if let Some(pattern13_0) =
5643                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5644                                             {
5645                                                 // Rule at src/isa/aarch64/lower.isle line 110.
5646                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5647                                                 let expr1_0 = constructor_add_imm(
5648                                                     ctx,
5649                                                     pattern3_0,
5650                                                     expr0_0,
5651                                                     pattern13_0,
5652                                                 )?;
5653                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5654                                                 return Some(expr2_0);
5655                                             }
5656                                         }
5657                                     }
5658                                     &InstructionData::Binary {
5659                                         opcode: ref pattern10_0,
5660                                         args: ref pattern10_1,
5661                                     } => {
5662                                         if let &Opcode::Ishl = pattern10_0 {
5663                                             let (pattern12_0, pattern12_1) =
5664                                                 C::unpack_value_array_2(ctx, pattern10_1);
5665                                             if let Some(pattern13_0) = C::def_inst(ctx, pattern12_1)
5666                                             {
5667                                                 let pattern14_0 = C::inst_data(ctx, pattern13_0);
5668                                                 if let &InstructionData::UnaryImm {
5669                                                     opcode: ref pattern15_0,
5670                                                     imm: pattern15_1,
5671                                                 } = &pattern14_0
5672                                                 {
5673                                                     if let &Opcode::Iconst = pattern15_0 {
5674                                                         let closure17 = || {
5675                                                             return Some(pattern3_0);
5676                                                         };
5677                                                         if let Some(pattern17_0) = closure17() {
5678                                                             if let Some(pattern18_0) =
5679                                                                 C::lshl_from_imm64(
5680                                                                     ctx,
5681                                                                     pattern15_1,
5682                                                                     pattern17_0,
5683                                                                 )
5684                                                             {
5685                                                                 // Rule at src/isa/aarch64/lower.isle line 120.
5686                                                                 let expr0_0 =
5687                                                                     C::put_in_reg(ctx, pattern7_0);
5688                                                                 let expr1_0 =
5689                                                                     C::put_in_reg(ctx, pattern12_0);
5690                                                                 let expr2_0 =
5691                                                                     constructor_sub_shift(
5692                                                                         ctx,
5693                                                                         pattern3_0,
5694                                                                         expr0_0,
5695                                                                         expr1_0,
5696                                                                         pattern18_0,
5697                                                                     )?;
5698                                                                 let expr3_0 =
5699                                                                     constructor_output_reg(
5700                                                                         ctx, expr2_0,
5701                                                                     )?;
5702                                                                 return Some(expr3_0);
5703                                                             }
5704                                                         }
5705                                                     }
5706                                                 }
5707                                             }
5708                                         }
5709                                     }
5710                                     _ => {}
5711                                 }
5712                             }
5713                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
5714                             {
5715                                 // Rule at src/isa/aarch64/lower.isle line 115.
5716                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5717                                 let expr1_0 =
5718                                     constructor_sub_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5719                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5720                                 return Some(expr2_0);
5721                             }
5722                             // Rule at src/isa/aarch64/lower.isle line 101.
5723                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5724                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5725                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
5726                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5727                             return Some(expr3_0);
5728                         }
5729                         &Opcode::Imul => {
5730                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5731                             // Rule at src/isa/aarch64/lower.isle line 179.
5732                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5733                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5734                             let expr2_0 = C::zero_reg(ctx);
5735                             let expr3_0 =
5736                                 constructor_madd(ctx, pattern3_0, expr0_0, expr1_0, expr2_0)?;
5737                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5738                             return Some(expr4_0);
5739                         }
5740                         &Opcode::Udiv => {
5741                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5742                             // Rule at src/isa/aarch64/lower.isle line 384.
5743                             let expr0_0: Type = I64;
5744                             let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5745                             let expr2_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
5746                             let expr3_0 = constructor_a64_udiv(ctx, expr0_0, expr1_0, expr2_0)?;
5747                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5748                             return Some(expr4_0);
5749                         }
5750                         &Opcode::Sdiv => {
5751                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5752                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5753                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5754                                 if let &InstructionData::UnaryImm {
5755                                     opcode: ref pattern10_0,
5756                                     imm: pattern10_1,
5757                                 } = &pattern9_0
5758                                 {
5759                                     if let &Opcode::Iconst = pattern10_0 {
5760                                         if let Some(pattern12_0) =
5761                                             C::safe_divisor_from_imm64(ctx, pattern10_1)
5762                                         {
5763                                             // Rule at src/isa/aarch64/lower.isle line 430.
5764                                             let expr0_0: Type = I64;
5765                                             let expr1_0 =
5766                                                 constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5767                                             let expr2_0 =
5768                                                 constructor_imm(ctx, pattern3_0, pattern12_0)?;
5769                                             let expr3_0 = constructor_a64_sdiv(
5770                                                 ctx, expr0_0, expr1_0, expr2_0,
5771                                             )?;
5772                                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5773                                             return Some(expr4_0);
5774                                         }
5775                                     }
5776                                 }
5777                             }
5778                             // Rule at src/isa/aarch64/lower.isle line 417.
5779                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5780                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
5781                             let expr2_0 = constructor_trap_if_div_overflow(
5782                                 ctx, pattern3_0, expr0_0, expr1_0,
5783                             )?;
5784                             let expr3_0: Type = I64;
5785                             let expr4_0 = constructor_a64_sdiv(ctx, expr3_0, expr2_0, expr1_0)?;
5786                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5787                             return Some(expr5_0);
5788                         }
5789                         &Opcode::Urem => {
5790                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5791                             // Rule at src/isa/aarch64/lower.isle line 458.
5792                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5793                             let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
5794                             let expr2_0: Type = I64;
5795                             let expr3_0 = constructor_a64_udiv(ctx, expr2_0, expr0_0, expr1_0)?;
5796                             let expr4_0 = constructor_msub64(ctx, expr3_0, expr1_0, expr0_0)?;
5797                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5798                             return Some(expr5_0);
5799                         }
5800                         &Opcode::Srem => {
5801                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5802                             // Rule at src/isa/aarch64/lower.isle line 465.
5803                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5804                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
5805                             let expr2_0: Type = I64;
5806                             let expr3_0 = constructor_a64_sdiv(ctx, expr2_0, expr0_0, expr1_0)?;
5807                             let expr4_0 = constructor_msub64(ctx, expr3_0, expr1_0, expr0_0)?;
5808                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5809                             return Some(expr5_0);
5810                         }
5811                         _ => {}
5812                     }
5813                 }
5814                 &InstructionData::Unary {
5815                     opcode: ref pattern5_0,
5816                     arg: pattern5_1,
5817                 } => {
5818                     match pattern5_0 {
5819                         &Opcode::Ineg => {
5820                             // Rule at src/isa/aarch64/lower.isle line 169.
5821                             let expr0_0 = C::zero_reg(ctx);
5822                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
5823                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
5824                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5825                             return Some(expr3_0);
5826                         }
5827                         &Opcode::Bnot => {
5828                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
5829                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
5830                                 if let &InstructionData::Binary {
5831                                     opcode: ref pattern9_0,
5832                                     args: ref pattern9_1,
5833                                 } = &pattern8_0
5834                                 {
5835                                     if let &Opcode::Ishl = pattern9_0 {
5836                                         let (pattern11_0, pattern11_1) =
5837                                             C::unpack_value_array_2(ctx, pattern9_1);
5838                                         if let Some(pattern12_0) = C::def_inst(ctx, pattern11_1) {
5839                                             let pattern13_0 = C::inst_data(ctx, pattern12_0);
5840                                             if let &InstructionData::UnaryImm {
5841                                                 opcode: ref pattern14_0,
5842                                                 imm: pattern14_1,
5843                                             } = &pattern13_0
5844                                             {
5845                                                 if let &Opcode::Iconst = pattern14_0 {
5846                                                     let closure16 = || {
5847                                                         return Some(pattern3_0);
5848                                                     };
5849                                                     if let Some(pattern16_0) = closure16() {
5850                                                         if let Some(pattern17_0) =
5851                                                             C::lshl_from_imm64(
5852                                                                 ctx,
5853                                                                 pattern14_1,
5854                                                                 pattern16_0,
5855                                                             )
5856                                                         {
5857                                                             // Rule at src/isa/aarch64/lower.isle line 564.
5858                                                             let expr0_0 = C::zero_reg(ctx);
5859                                                             let expr1_0 =
5860                                                                 C::put_in_reg(ctx, pattern11_0);
5861                                                             let expr2_0 =
5862                                                                 constructor_orr_not_shift(
5863                                                                     ctx,
5864                                                                     pattern3_0,
5865                                                                     expr0_0,
5866                                                                     expr1_0,
5867                                                                     pattern17_0,
5868                                                                 )?;
5869                                                             let expr3_0 = constructor_output_reg(
5870                                                                 ctx, expr2_0,
5871                                                             )?;
5872                                                             return Some(expr3_0);
5873                                                         }
5874                                                     }
5875                                                 }
5876                                             }
5877                                         }
5878                                     }
5879                                 }
5880                             }
5881                             // Rule at src/isa/aarch64/lower.isle line 559.
5882                             let expr0_0 = C::zero_reg(ctx);
5883                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
5884                             let expr2_0 = constructor_orr_not(ctx, pattern3_0, expr0_0, expr1_0)?;
5885                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5886                             return Some(expr3_0);
5887                         }
5888                         &Opcode::Uextend => {
5889                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
5890                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
5891                                 if let &InstructionData::BinaryImm8 {
5892                                     opcode: ref pattern9_0,
5893                                     arg: pattern9_1,
5894                                     imm: pattern9_2,
5895                                 } = &pattern8_0
5896                                 {
5897                                     if let &Opcode::Extractlane = pattern9_0 {
5898                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
5899                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
5900                                         // Rule at src/isa/aarch64/lower.isle line 481.
5901                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
5902                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
5903                                         let expr2_0 = constructor_mov_from_vec(
5904                                             ctx,
5905                                             expr0_0,
5906                                             pattern12_0,
5907                                             &expr1_0,
5908                                         )?;
5909                                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5910                                         return Some(expr3_0);
5911                                     }
5912                                 }
5913                             }
5914                             let pattern7_0 = C::value_type(ctx, pattern5_1);
5915                             if let Some(pattern8_0) = C::sinkable_atomic_load(ctx, pattern5_1) {
5916                                 // Rule at src/isa/aarch64/lower.isle line 488.
5917                                 let expr0_0 = C::sink_atomic_load(ctx, &pattern8_0);
5918                                 let expr1_0 = constructor_load_acquire(ctx, pattern7_0, expr0_0)?;
5919                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5920                                 return Some(expr2_0);
5921                             }
5922                             // Rule at src/isa/aarch64/lower.isle line 476.
5923                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
5924                             let expr1_0: bool = false;
5925                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
5926                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
5927                             let expr4_0 =
5928                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
5929                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5930                             return Some(expr5_0);
5931                         }
5932                         &Opcode::Sextend => {
5933                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
5934                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
5935                                 if let &InstructionData::BinaryImm8 {
5936                                     opcode: ref pattern9_0,
5937                                     arg: pattern9_1,
5938                                     imm: pattern9_2,
5939                                 } = &pattern8_0
5940                                 {
5941                                     if let &Opcode::Extractlane = pattern9_0 {
5942                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
5943                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
5944                                         // Rule at src/isa/aarch64/lower.isle line 513.
5945                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
5946                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
5947                                         let expr2_0 = constructor_size_from_ty(ctx, pattern3_0)?;
5948                                         let expr3_0 = constructor_mov_from_vec_signed(
5949                                             ctx,
5950                                             expr0_0,
5951                                             pattern12_0,
5952                                             &expr1_0,
5953                                             &expr2_0,
5954                                         )?;
5955                                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5956                                         return Some(expr4_0);
5957                                     }
5958                                 }
5959                             }
5960                             let pattern7_0 = C::value_type(ctx, pattern5_1);
5961                             // Rule at src/isa/aarch64/lower.isle line 508.
5962                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
5963                             let expr1_0: bool = true;
5964                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
5965                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
5966                             let expr4_0 =
5967                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
5968                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5969                             return Some(expr5_0);
5970                         }
5971                         _ => {}
5972                     }
5973                 }
5974                 _ => {}
5975             }
5976         }
5977         if let Some(pattern3_0) = C::vec128(ctx, pattern2_0) {
5978             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5979             match &pattern4_0 {
5980                 &InstructionData::Binary {
5981                     opcode: ref pattern5_0,
5982                     args: ref pattern5_1,
5983                 } => {
5984                     match pattern5_0 {
5985                         &Opcode::UaddSat => {
5986                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5987                             // Rule at src/isa/aarch64/lower.isle line 148.
5988                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5989                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5990                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5991                             let expr3_0 = constructor_uqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
5992                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5993                             return Some(expr4_0);
5994                         }
5995                         &Opcode::SaddSat => {
5996                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5997                             // Rule at src/isa/aarch64/lower.isle line 153.
5998                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5999                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6000                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6001                             let expr3_0 = constructor_sqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6002                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6003                             return Some(expr4_0);
6004                         }
6005                         &Opcode::UsubSat => {
6006                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6007                             // Rule at src/isa/aarch64/lower.isle line 158.
6008                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6009                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6010                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6011                             let expr3_0 = constructor_uqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6012                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6013                             return Some(expr4_0);
6014                         }
6015                         &Opcode::SsubSat => {
6016                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6017                             // Rule at src/isa/aarch64/lower.isle line 163.
6018                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6019                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6020                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6021                             let expr3_0 = constructor_sqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6022                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6023                             return Some(expr4_0);
6024                         }
6025                         &Opcode::Band => {
6026                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6027                             // Rule at src/isa/aarch64/lower.isle line 591.
6028                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6029                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6030                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6031                             let expr3_0 = constructor_and_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6032                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6033                             return Some(expr4_0);
6034                         }
6035                         &Opcode::Bor => {
6036                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6037                             // Rule at src/isa/aarch64/lower.isle line 604.
6038                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6039                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6040                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6041                             let expr3_0 = constructor_orr_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6042                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6043                             return Some(expr4_0);
6044                         }
6045                         &Opcode::Bxor => {
6046                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6047                             // Rule at src/isa/aarch64/lower.isle line 617.
6048                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6049                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6050                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6051                             let expr3_0 = constructor_eor_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6052                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6053                             return Some(expr4_0);
6054                         }
6055                         &Opcode::BandNot => {
6056                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6057                             // Rule at src/isa/aarch64/lower.isle line 630.
6058                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6059                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6060                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6061                             let expr3_0 = constructor_bic_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6062                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6063                             return Some(expr4_0);
6064                         }
6065                         &Opcode::Ishl => {
6066                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6067                             // Rule at src/isa/aarch64/lower.isle line 694.
6068                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6069                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6070                             let expr2_0 = constructor_vec_dup(ctx, expr1_0, &expr0_0)?;
6071                             let expr3_0 = C::put_in_reg(ctx, pattern7_0);
6072                             let expr4_0 = constructor_sshl(ctx, expr3_0, expr2_0, &expr0_0)?;
6073                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6074                             return Some(expr5_0);
6075                         }
6076                         &Opcode::Ushr => {
6077                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6078                             // Rule at src/isa/aarch64/lower.isle line 752.
6079                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6080                             let expr1_0: Type = I32;
6081                             let expr2_0 = C::zero_reg(ctx);
6082                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6083                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6084                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6085                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6086                             let expr7_0 = constructor_ushl(ctx, expr6_0, expr5_0, &expr0_0)?;
6087                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6088                             return Some(expr8_0);
6089                         }
6090                         &Opcode::Sshr => {
6091                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6092                             // Rule at src/isa/aarch64/lower.isle line 801.
6093                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6094                             let expr1_0: Type = I32;
6095                             let expr2_0 = C::zero_reg(ctx);
6096                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6097                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6098                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6099                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6100                             let expr7_0 = constructor_sshl(ctx, expr6_0, expr5_0, &expr0_0)?;
6101                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6102                             return Some(expr8_0);
6103                         }
6104                         _ => {}
6105                     }
6106                 }
6107                 &InstructionData::Unary {
6108                     opcode: ref pattern5_0,
6109                     arg: pattern5_1,
6110                 } => {
6111                     match pattern5_0 {
6112                         &Opcode::Ineg => {
6113                             // Rule at src/isa/aarch64/lower.isle line 173.
6114                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6115                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6116                             let expr2_0 = constructor_neg(ctx, expr0_0, &expr1_0)?;
6117                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6118                             return Some(expr3_0);
6119                         }
6120                         &Opcode::Bnot => {
6121                             // Rule at src/isa/aarch64/lower.isle line 578.
6122                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6123                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6124                             let expr2_0 = constructor_not(ctx, expr0_0, &expr1_0)?;
6125                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6126                             return Some(expr3_0);
6127                         }
6128                         _ => {}
6129                     }
6130                 }
6131                 _ => {}
6132             }
6133             if let Some(()) = C::not_i64x2(ctx, pattern3_0) {
6134                 let pattern5_0 = C::inst_data(ctx, pattern0_0);
6135                 if let &InstructionData::Binary {
6136                     opcode: ref pattern6_0,
6137                     args: ref pattern6_1,
6138                 } = &pattern5_0
6139                 {
6140                     if let &Opcode::Imul = pattern6_0 {
6141                         let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
6142                         // Rule at src/isa/aarch64/lower.isle line 211.
6143                         let expr0_0 = C::put_in_reg(ctx, pattern8_0);
6144                         let expr1_0 = C::put_in_reg(ctx, pattern8_1);
6145                         let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6146                         let expr3_0 = constructor_mul(ctx, expr0_0, expr1_0, &expr2_0)?;
6147                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6148                         return Some(expr4_0);
6149                     }
6150                 }
6151             }
6152         }
6153     }
6154     return None;
6155 }
6156 
6157 // Generated as internal constructor for term put_nonzero_in_reg_zext64.
6158 pub fn constructor_put_nonzero_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6159     let pattern0_0 = arg0;
6160     let pattern1_0 = C::value_type(ctx, pattern0_0);
6161     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6162         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6163         if let &InstructionData::UnaryImm {
6164             opcode: ref pattern4_0,
6165             imm: pattern4_1,
6166         } = &pattern3_0
6167         {
6168             if let &Opcode::Iconst = pattern4_0 {
6169                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6170                     // Rule at src/isa/aarch64/lower.isle line 394.
6171                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6172                     return Some(expr0_0);
6173                 }
6174             }
6175         }
6176     }
6177     // Rule at src/isa/aarch64/lower.isle line 389.
6178     let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern0_0)?;
6179     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6180     return Some(expr1_0);
6181 }
6182 
6183 // Generated as internal constructor for term put_nonzero_in_reg_sext64.
6184 pub fn constructor_put_nonzero_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6185     let pattern0_0 = arg0;
6186     let pattern1_0 = C::value_type(ctx, pattern0_0);
6187     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6188         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6189         if let &InstructionData::UnaryImm {
6190             opcode: ref pattern4_0,
6191             imm: pattern4_1,
6192         } = &pattern3_0
6193         {
6194             if let &Opcode::Iconst = pattern4_0 {
6195                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6196                     // Rule at src/isa/aarch64/lower.isle line 440.
6197                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6198                     return Some(expr0_0);
6199                 }
6200             }
6201         }
6202     }
6203     // Rule at src/isa/aarch64/lower.isle line 435.
6204     let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern0_0)?;
6205     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6206     return Some(expr1_0);
6207 }
6208 
6209 // Generated as internal constructor for term lower_shl128.
6210 pub fn constructor_lower_shl128<C: Context>(
6211     ctx: &mut C,
6212     arg0: ValueRegs,
6213     arg1: Reg,
6214 ) -> Option<ValueRegs> {
6215     let pattern0_0 = arg0;
6216     let pattern1_0 = arg1;
6217     // Rule at src/isa/aarch64/lower.isle line 677.
6218     let expr0_0: usize = 0;
6219     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6220     let expr2_0: usize = 1;
6221     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6222     let expr4_0: Type = I64;
6223     let expr5_0 = constructor_lsl(ctx, expr4_0, expr1_0, pattern1_0)?;
6224     let expr6_0: Type = I64;
6225     let expr7_0 = constructor_lsl(ctx, expr6_0, expr3_0, pattern1_0)?;
6226     let expr8_0: Type = I32;
6227     let expr9_0 = C::zero_reg(ctx);
6228     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6229     let expr11_0: Type = I64;
6230     let expr12_0: Type = I64;
6231     let expr13_0: u8 = 1;
6232     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6233     let expr15_0 = constructor_lsr_imm(ctx, expr12_0, expr1_0, expr14_0)?;
6234     let expr16_0 = constructor_lsr(ctx, expr11_0, expr15_0, expr10_0)?;
6235     let expr17_0: Type = I64;
6236     let expr18_0 = constructor_orr(ctx, expr17_0, expr7_0, expr16_0)?;
6237     let expr19_0: Type = I64;
6238     let expr20_0: Type = I64;
6239     let expr21_0: u64 = 64;
6240     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6241     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6242     let expr24_0 = Cond::Ne;
6243     let expr25_0 = C::zero_reg(ctx);
6244     let expr26_0 = constructor_csel(ctx, &expr24_0, expr25_0, expr5_0)?;
6245     let expr27_0 = Cond::Ne;
6246     let expr28_0 = constructor_csel(ctx, &expr27_0, expr5_0, expr18_0)?;
6247     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr26_0, &expr28_0)?;
6248     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6249     return Some(expr30_0);
6250 }
6251 
6252 // Generated as internal constructor for term do_shift.
6253 pub fn constructor_do_shift<C: Context>(
6254     ctx: &mut C,
6255     arg0: &ALUOp,
6256     arg1: Type,
6257     arg2: Reg,
6258     arg3: Value,
6259 ) -> Option<Reg> {
6260     let pattern0_0 = arg0;
6261     let pattern1_0 = arg1;
6262     let pattern2_0 = arg2;
6263     let pattern3_0 = arg3;
6264     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
6265         let pattern5_0 = C::inst_data(ctx, pattern4_0);
6266         if let &InstructionData::UnaryImm {
6267             opcode: ref pattern6_0,
6268             imm: pattern6_1,
6269         } = &pattern5_0
6270         {
6271             if let &Opcode::Iconst = pattern6_0 {
6272                 let closure8 = || {
6273                     return Some(pattern1_0);
6274                 };
6275                 if let Some(pattern8_0) = closure8() {
6276                     if let Some(pattern9_0) = C::imm_shift_from_imm64(ctx, pattern6_1, pattern8_0) {
6277                         // Rule at src/isa/aarch64/lower.isle line 734.
6278                         let expr0_0 = constructor_alu_rr_imm_shift(
6279                             ctx, pattern0_0, pattern1_0, pattern2_0, pattern9_0,
6280                         )?;
6281                         return Some(expr0_0);
6282                     }
6283                 }
6284             }
6285         }
6286     }
6287     let pattern0_0 = arg0;
6288     let pattern1_0 = arg1;
6289     if pattern1_0 == I32 {
6290         let pattern3_0 = arg2;
6291         let pattern4_0 = arg3;
6292         // Rule at src/isa/aarch64/lower.isle line 725.
6293         let expr0_0: Type = I32;
6294         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6295         let expr2_0: usize = 0;
6296         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6297         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6298         return Some(expr4_0);
6299     }
6300     if pattern1_0 == I64 {
6301         let pattern3_0 = arg2;
6302         let pattern4_0 = arg3;
6303         // Rule at src/isa/aarch64/lower.isle line 726.
6304         let expr0_0: Type = I64;
6305         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6306         let expr2_0: usize = 0;
6307         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6308         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6309         return Some(expr4_0);
6310     }
6311     if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
6312         let pattern3_0 = arg2;
6313         let pattern4_0 = arg3;
6314         // Rule at src/isa/aarch64/lower.isle line 716.
6315         let expr0_0 = C::put_in_regs(ctx, pattern4_0);
6316         let expr1_0: usize = 0;
6317         let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
6318         let expr3_0: Type = I32;
6319         let expr4_0 = C::shift_mask(ctx, pattern2_0);
6320         let expr5_0 = constructor_and_imm(ctx, expr3_0, expr2_0, expr4_0)?;
6321         let expr6_0: Type = I32;
6322         let expr7_0 = constructor_alu_rrr(ctx, pattern0_0, expr6_0, pattern3_0, expr5_0)?;
6323         return Some(expr7_0);
6324     }
6325     return None;
6326 }
6327 
6328 // Generated as internal constructor for term lower_ushr128.
6329 pub fn constructor_lower_ushr128<C: Context>(
6330     ctx: &mut C,
6331     arg0: ValueRegs,
6332     arg1: Reg,
6333 ) -> Option<ValueRegs> {
6334     let pattern0_0 = arg0;
6335     let pattern1_0 = arg1;
6336     // Rule at src/isa/aarch64/lower.isle line 767.
6337     let expr0_0: usize = 0;
6338     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6339     let expr2_0: usize = 1;
6340     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6341     let expr4_0: Type = I64;
6342     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6343     let expr6_0: Type = I64;
6344     let expr7_0 = constructor_lsr(ctx, expr6_0, expr3_0, pattern1_0)?;
6345     let expr8_0: Type = I32;
6346     let expr9_0 = C::zero_reg(ctx);
6347     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6348     let expr11_0: Type = I64;
6349     let expr12_0: Type = I64;
6350     let expr13_0: u8 = 1;
6351     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6352     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6353     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6354     let expr17_0: Type = I64;
6355     let expr18_0 = constructor_orr(ctx, expr17_0, expr5_0, expr16_0)?;
6356     let expr19_0: Type = I64;
6357     let expr20_0: Type = I64;
6358     let expr21_0: u64 = 64;
6359     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6360     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6361     let expr24_0 = Cond::Ne;
6362     let expr25_0 = constructor_csel(ctx, &expr24_0, expr7_0, expr18_0)?;
6363     let expr26_0 = Cond::Ne;
6364     let expr27_0 = C::zero_reg(ctx);
6365     let expr28_0 = constructor_csel(ctx, &expr26_0, expr27_0, expr7_0)?;
6366     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr25_0, &expr28_0)?;
6367     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6368     return Some(expr30_0);
6369 }
6370 
6371 // Generated as internal constructor for term lower_sshr128.
6372 pub fn constructor_lower_sshr128<C: Context>(
6373     ctx: &mut C,
6374     arg0: ValueRegs,
6375     arg1: Reg,
6376 ) -> Option<ValueRegs> {
6377     let pattern0_0 = arg0;
6378     let pattern1_0 = arg1;
6379     // Rule at src/isa/aarch64/lower.isle line 817.
6380     let expr0_0: usize = 0;
6381     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6382     let expr2_0: usize = 1;
6383     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6384     let expr4_0: Type = I64;
6385     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6386     let expr6_0: Type = I64;
6387     let expr7_0 = constructor_asr(ctx, expr6_0, expr3_0, pattern1_0)?;
6388     let expr8_0: Type = I32;
6389     let expr9_0 = C::zero_reg(ctx);
6390     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6391     let expr11_0: Type = I64;
6392     let expr12_0: Type = I64;
6393     let expr13_0: u8 = 1;
6394     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6395     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6396     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6397     let expr17_0: Type = I64;
6398     let expr18_0: u8 = 63;
6399     let expr19_0 = C::imm_shift_from_u8(ctx, expr18_0);
6400     let expr20_0 = constructor_asr_imm(ctx, expr17_0, expr3_0, expr19_0)?;
6401     let expr21_0: Type = I64;
6402     let expr22_0 = constructor_orr(ctx, expr21_0, expr5_0, expr16_0)?;
6403     let expr23_0: Type = I64;
6404     let expr24_0: Type = I64;
6405     let expr25_0: u64 = 64;
6406     let expr26_0 = C::u64_into_imm_logic(ctx, expr24_0, expr25_0);
6407     let expr27_0 = constructor_tst_imm(ctx, expr23_0, pattern1_0, expr26_0)?;
6408     let expr28_0 = Cond::Ne;
6409     let expr29_0 = constructor_csel(ctx, &expr28_0, expr7_0, expr22_0)?;
6410     let expr30_0 = Cond::Ne;
6411     let expr31_0 = constructor_csel(ctx, &expr30_0, expr20_0, expr7_0)?;
6412     let expr32_0 = constructor_consumes_flags_concat(ctx, &expr29_0, &expr31_0)?;
6413     let expr33_0 = constructor_with_flags(ctx, &expr27_0, &expr32_0)?;
6414     return Some(expr33_0);
6415 }
6416 
6417 // Generated as internal constructor for term small_rotr.
6418 pub fn constructor_small_rotr<C: Context>(
6419     ctx: &mut C,
6420     arg0: Type,
6421     arg1: Reg,
6422     arg2: Reg,
6423 ) -> Option<Reg> {
6424     let pattern0_0 = arg0;
6425     let pattern1_0 = arg1;
6426     let pattern2_0 = arg2;
6427     // Rule at src/isa/aarch64/lower.isle line 927.
6428     let expr0_0: Type = I32;
6429     let expr1_0 = C::rotr_mask(ctx, pattern0_0);
6430     let expr2_0 = constructor_and_imm(ctx, expr0_0, pattern2_0, expr1_0)?;
6431     let expr3_0: Type = I32;
6432     let expr4_0 = C::ty_bits(ctx, pattern0_0);
6433     let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
6434     let expr6_0 = constructor_sub_imm(ctx, expr3_0, expr2_0, expr5_0)?;
6435     let expr7_0: Type = I32;
6436     let expr8_0 = C::zero_reg(ctx);
6437     let expr9_0 = constructor_sub(ctx, expr7_0, expr8_0, expr6_0)?;
6438     let expr10_0: Type = I32;
6439     let expr11_0 = constructor_lsr(ctx, expr10_0, pattern1_0, expr2_0)?;
6440     let expr12_0: Type = I32;
6441     let expr13_0 = constructor_lsl(ctx, expr12_0, pattern1_0, expr9_0)?;
6442     let expr14_0: Type = I32;
6443     let expr15_0 = constructor_orr(ctx, expr14_0, expr13_0, expr11_0)?;
6444     return Some(expr15_0);
6445 }
6446 
6447 // Generated as internal constructor for term small_rotr_imm.
6448 pub fn constructor_small_rotr_imm<C: Context>(
6449     ctx: &mut C,
6450     arg0: Type,
6451     arg1: Reg,
6452     arg2: ImmShift,
6453 ) -> Option<Reg> {
6454     let pattern0_0 = arg0;
6455     let pattern1_0 = arg1;
6456     let pattern2_0 = arg2;
6457     // Rule at src/isa/aarch64/lower.isle line 948.
6458     let expr0_0: Type = I32;
6459     let expr1_0 = constructor_lsr_imm(ctx, expr0_0, pattern1_0, pattern2_0)?;
6460     let expr2_0: Type = I32;
6461     let expr3_0 = C::rotr_opposite_amount(ctx, pattern0_0, pattern2_0);
6462     let expr4_0 = constructor_lsl_imm(ctx, expr2_0, pattern1_0, expr3_0)?;
6463     let expr5_0: Type = I32;
6464     let expr6_0 = constructor_orr(ctx, expr5_0, expr4_0, expr1_0)?;
6465     return Some(expr6_0);
6466 }
6467 
6468 // Generated as internal constructor for term lower_clz128.
6469 pub fn constructor_lower_clz128<C: Context>(ctx: &mut C, arg0: ValueRegs) -> Option<ValueRegs> {
6470     let pattern0_0 = arg0;
6471     // Rule at src/isa/aarch64/lower.isle line 1013.
6472     let expr0_0: Type = I64;
6473     let expr1_0: usize = 1;
6474     let expr2_0 = C::value_regs_get(ctx, pattern0_0, expr1_0);
6475     let expr3_0 = constructor_a64_clz(ctx, expr0_0, expr2_0)?;
6476     let expr4_0: Type = I64;
6477     let expr5_0: usize = 0;
6478     let expr6_0 = C::value_regs_get(ctx, pattern0_0, expr5_0);
6479     let expr7_0 = constructor_a64_clz(ctx, expr4_0, expr6_0)?;
6480     let expr8_0: Type = I64;
6481     let expr9_0: u8 = 6;
6482     let expr10_0 = C::imm_shift_from_u8(ctx, expr9_0);
6483     let expr11_0 = constructor_lsr_imm(ctx, expr8_0, expr3_0, expr10_0)?;
6484     let expr12_0 = constructor_madd64(ctx, expr7_0, expr11_0, expr3_0)?;
6485     let expr13_0: Type = I64;
6486     let expr14_0: u64 = 0;
6487     let expr15_0 = constructor_imm(ctx, expr13_0, expr14_0)?;
6488     let expr16_0 = C::value_regs(ctx, expr12_0, expr15_0);
6489     return Some(expr16_0);
6490 }
6491