1 // GENERATED BY ISLE. DO NOT EDIT!
2 //
3 // Generated automatically from the instruction-selection DSL code in:
4 // - src/clif.isle
5 // - src/prelude.isle
6 // - src/isa/aarch64/inst.isle
7 // - src/isa/aarch64/lower.isle
8 
9 #![allow(dead_code, unreachable_code, unreachable_patterns)]
10 #![allow(unused_imports, unused_variables, non_snake_case)]
11 #![allow(irrefutable_let_patterns)]
12 
13 use super::*; // Pulls in all external types.
14 
15 /// Context during lowering: an implementation of this trait
16 /// must be provided with all external constructors and extractors.
17 /// A mutable borrow is passed along through all lowering logic.
18 pub trait Context {
19     fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
20     fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
21     fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
22     fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
23     fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
24     fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
25     fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
26     fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
27     fn value_regs_invalid(&mut self) -> ValueRegs;
28     fn output_none(&mut self) -> InstOutput;
29     fn output(&mut self, arg0: ValueRegs) -> InstOutput;
30     fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput;
31     fn output_builder_new(&mut self) -> InstOutputBuilder;
32     fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit;
33     fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput;
34     fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
35     fn invalid_reg(&mut self) -> Reg;
36     fn put_in_reg(&mut self, arg0: Value) -> Reg;
37     fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
38     fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
39     fn u8_as_u64(&mut self, arg0: u8) -> u64;
40     fn u16_as_u64(&mut self, arg0: u16) -> u64;
41     fn u32_as_u64(&mut self, arg0: u32) -> u64;
42     fn i64_as_u64(&mut self, arg0: i64) -> u64;
43     fn u64_add(&mut self, arg0: u64, arg1: u64) -> u64;
44     fn u64_sub(&mut self, arg0: u64, arg1: u64) -> u64;
45     fn u64_and(&mut self, arg0: u64, arg1: u64) -> u64;
46     fn ty_bits(&mut self, arg0: Type) -> u8;
47     fn ty_bits_u16(&mut self, arg0: Type) -> u16;
48     fn ty_bits_u64(&mut self, arg0: Type) -> u64;
49     fn ty_mask(&mut self, arg0: Type) -> u64;
50     fn ty_bytes(&mut self, arg0: Type) -> u16;
51     fn lane_type(&mut self, arg0: Type) -> Type;
52     fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
53     fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
54     fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
55     fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
56     fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
57     fn ty_int_bool_64(&mut self, arg0: Type) -> Option<Type>;
58     fn ty_int_bool_ref_64(&mut self, arg0: Type) -> Option<Type>;
59     fn ty_int_bool_128(&mut self, arg0: Type) -> Option<Type>;
60     fn ty_scalar_float(&mut self, arg0: Type) -> Option<Type>;
61     fn ty_vec128(&mut self, arg0: Type) -> Option<Type>;
62     fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
63     fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
64     fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>;
65     fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>;
66     fn value_slice_len(&mut self, arg0: ValueSlice) -> usize;
67     fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value;
68     fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
69     fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
70     fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
71     fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
72     fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
73     fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
74     fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
75     fn first_result(&mut self, arg0: Inst) -> Option<Value>;
76     fn inst_data(&mut self, arg0: Inst) -> InstructionData;
77     fn value_type(&mut self, arg0: Value) -> Type;
78     fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
79     fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
80     fn offset32_to_u32(&mut self, arg0: Offset32) -> u32;
81     fn emit(&mut self, arg0: &MInst) -> Unit;
82     fn trap_code_division_by_zero(&mut self) -> TrapCode;
83     fn trap_code_integer_overflow(&mut self) -> TrapCode;
84     fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
85     fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
86     fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
87     fn symbol_value_data(
88         &mut self,
89         arg0: GlobalValue,
90     ) -> Option<(ExternalName, RelocDistance, i64)>;
91     fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
92     fn move_wide_const_from_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
93     fn move_wide_const_from_negated_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
94     fn imm_logic_from_u64(&mut self, arg0: u64, arg1: Type) -> Option<ImmLogic>;
95     fn imm_logic_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmLogic>;
96     fn imm_shift_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmShift>;
97     fn imm_shift_from_u8(&mut self, arg0: u8) -> ImmShift;
98     fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12>;
99     fn u8_into_uimm5(&mut self, arg0: u8) -> UImm5;
100     fn u8_into_imm12(&mut self, arg0: u8) -> Imm12;
101     fn u64_into_imm_logic(&mut self, arg0: Type, arg1: u64) -> ImmLogic;
102     fn imm12_from_negated_u64(&mut self, arg0: u64) -> Option<Imm12>;
103     fn lshl_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ShiftOpAndAmt>;
104     fn integral_ty(&mut self, arg0: Type) -> Option<Type>;
105     fn extended_value_from_value(&mut self, arg0: Value) -> Option<ExtendedValue>;
106     fn put_extended_in_reg(&mut self, arg0: &ExtendedValue) -> Reg;
107     fn get_extended_op(&mut self, arg0: &ExtendedValue) -> ExtendOp;
108     fn nzcv(&mut self, arg0: bool, arg1: bool, arg2: bool, arg3: bool) -> NZCV;
109     fn cond_br_zero(&mut self, arg0: Reg) -> CondBrKind;
110     fn cond_br_cond(&mut self, arg0: &Cond) -> CondBrKind;
111     fn zero_reg(&mut self) -> Reg;
112     fn writable_zero_reg(&mut self) -> WritableReg;
113     fn load_constant64_full(&mut self, arg0: u64) -> Reg;
114     fn sinkable_atomic_load(&mut self, arg0: Value) -> Option<SinkableAtomicLoad>;
115     fn sink_atomic_load(&mut self, arg0: &SinkableAtomicLoad) -> Reg;
116     fn zero_value_f32(&mut self, arg0: Ieee32) -> Option<Ieee32>;
117     fn zero_value_f64(&mut self, arg0: Ieee64) -> Option<Ieee64>;
118     fn float_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &FloatCC) -> VecMisc2;
119     fn float_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &FloatCC) -> VecMisc2;
120     fn fcmp_zero_cond(&mut self, arg0: &FloatCC) -> Option<FloatCC>;
121     fn fcmp_zero_cond_not_eq(&mut self, arg0: &FloatCC) -> Option<FloatCC>;
122     fn zero_value(&mut self, arg0: Imm64) -> Option<Imm64>;
123     fn int_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &IntCC) -> VecMisc2;
124     fn int_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &IntCC) -> VecMisc2;
125     fn icmp_zero_cond(&mut self, arg0: &IntCC) -> Option<IntCC>;
126     fn icmp_zero_cond_not_eq(&mut self, arg0: &IntCC) -> Option<IntCC>;
127     fn safe_divisor_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
128     fn shift_mask(&mut self, arg0: Type) -> ImmLogic;
129     fn negate_imm_shift(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
130     fn rotr_mask(&mut self, arg0: Type) -> ImmLogic;
131     fn rotr_opposite_amount(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
132 }
133 
134 /// Internal type SideEffectNoResult: defined at src/prelude.isle line 402.
135 #[derive(Clone, Debug)]
136 pub enum SideEffectNoResult {
137     Inst { inst: MInst },
138 }
139 
140 /// Internal type ProducesFlags: defined at src/prelude.isle line 418.
141 #[derive(Clone, Debug)]
142 pub enum ProducesFlags {
143     ProducesFlagsSideEffect { inst: MInst },
144     ProducesFlagsReturnsReg { inst: MInst, result: Reg },
145     ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg },
146 }
147 
148 /// Internal type ConsumesFlags: defined at src/prelude.isle line 429.
149 #[derive(Clone, Debug)]
150 pub enum ConsumesFlags {
151     ConsumesFlagsReturnsResultWithProducer {
152         inst: MInst,
153         result: Reg,
154     },
155     ConsumesFlagsReturnsReg {
156         inst: MInst,
157         result: Reg,
158     },
159     ConsumesFlagsTwiceReturnsValueRegs {
160         inst1: MInst,
161         inst2: MInst,
162         result: ValueRegs,
163     },
164     ConsumesFlagsFourTimesReturnsValueRegs {
165         inst1: MInst,
166         inst2: MInst,
167         inst3: MInst,
168         inst4: MInst,
169         result: ValueRegs,
170     },
171 }
172 
173 /// Internal type MInst: defined at src/isa/aarch64/inst.isle line 2.
174 #[derive(Clone, Debug)]
175 pub enum MInst {
176     Nop0,
177     Nop4,
178     AluRRR {
179         alu_op: ALUOp,
180         size: OperandSize,
181         rd: WritableReg,
182         rn: Reg,
183         rm: Reg,
184     },
185     AluRRRR {
186         alu_op: ALUOp3,
187         size: OperandSize,
188         rd: WritableReg,
189         rn: Reg,
190         rm: Reg,
191         ra: Reg,
192     },
193     AluRRImm12 {
194         alu_op: ALUOp,
195         size: OperandSize,
196         rd: WritableReg,
197         rn: Reg,
198         imm12: Imm12,
199     },
200     AluRRImmLogic {
201         alu_op: ALUOp,
202         size: OperandSize,
203         rd: WritableReg,
204         rn: Reg,
205         imml: ImmLogic,
206     },
207     AluRRImmShift {
208         alu_op: ALUOp,
209         size: OperandSize,
210         rd: WritableReg,
211         rn: Reg,
212         immshift: ImmShift,
213     },
214     AluRRRShift {
215         alu_op: ALUOp,
216         size: OperandSize,
217         rd: WritableReg,
218         rn: Reg,
219         rm: Reg,
220         shiftop: ShiftOpAndAmt,
221     },
222     AluRRRExtend {
223         alu_op: ALUOp,
224         size: OperandSize,
225         rd: WritableReg,
226         rn: Reg,
227         rm: Reg,
228         extendop: ExtendOp,
229     },
230     BitRR {
231         op: BitOp,
232         size: OperandSize,
233         rd: WritableReg,
234         rn: Reg,
235     },
236     ULoad8 {
237         rd: WritableReg,
238         mem: AMode,
239         flags: MemFlags,
240     },
241     SLoad8 {
242         rd: WritableReg,
243         mem: AMode,
244         flags: MemFlags,
245     },
246     ULoad16 {
247         rd: WritableReg,
248         mem: AMode,
249         flags: MemFlags,
250     },
251     SLoad16 {
252         rd: WritableReg,
253         mem: AMode,
254         flags: MemFlags,
255     },
256     ULoad32 {
257         rd: WritableReg,
258         mem: AMode,
259         flags: MemFlags,
260     },
261     SLoad32 {
262         rd: WritableReg,
263         mem: AMode,
264         flags: MemFlags,
265     },
266     ULoad64 {
267         rd: WritableReg,
268         mem: AMode,
269         flags: MemFlags,
270     },
271     Store8 {
272         rd: Reg,
273         mem: AMode,
274         flags: MemFlags,
275     },
276     Store16 {
277         rd: Reg,
278         mem: AMode,
279         flags: MemFlags,
280     },
281     Store32 {
282         rd: Reg,
283         mem: AMode,
284         flags: MemFlags,
285     },
286     Store64 {
287         rd: Reg,
288         mem: AMode,
289         flags: MemFlags,
290     },
291     StoreP64 {
292         rt: Reg,
293         rt2: Reg,
294         mem: PairAMode,
295         flags: MemFlags,
296     },
297     LoadP64 {
298         rt: WritableReg,
299         rt2: WritableReg,
300         mem: PairAMode,
301         flags: MemFlags,
302     },
303     Mov64 {
304         rd: WritableReg,
305         rm: Reg,
306     },
307     Mov32 {
308         rd: WritableReg,
309         rm: Reg,
310     },
311     MovZ {
312         rd: WritableReg,
313         imm: MoveWideConst,
314         size: OperandSize,
315     },
316     MovN {
317         rd: WritableReg,
318         imm: MoveWideConst,
319         size: OperandSize,
320     },
321     MovK {
322         rd: WritableReg,
323         imm: MoveWideConst,
324         size: OperandSize,
325     },
326     Extend {
327         rd: WritableReg,
328         rn: Reg,
329         signed: bool,
330         from_bits: u8,
331         to_bits: u8,
332     },
333     CSel {
334         rd: WritableReg,
335         cond: Cond,
336         rn: Reg,
337         rm: Reg,
338     },
339     CSet {
340         rd: WritableReg,
341         cond: Cond,
342     },
343     CSetm {
344         rd: WritableReg,
345         cond: Cond,
346     },
347     CCmpImm {
348         size: OperandSize,
349         rn: Reg,
350         imm: UImm5,
351         nzcv: NZCV,
352         cond: Cond,
353     },
354     AtomicRMWLoop {
355         ty: Type,
356         op: AtomicRmwOp,
357     },
358     AtomicRMW {
359         op: AtomicRMWOp,
360         rs: Reg,
361         rt: WritableReg,
362         rn: Reg,
363         ty: Type,
364     },
365     AtomicCAS {
366         rs: WritableReg,
367         rt: Reg,
368         rn: Reg,
369         ty: Type,
370     },
371     AtomicCASLoop {
372         ty: Type,
373     },
374     LoadAcquire {
375         access_ty: Type,
376         rt: WritableReg,
377         rn: Reg,
378     },
379     StoreRelease {
380         access_ty: Type,
381         rt: Reg,
382         rn: Reg,
383     },
384     Fence,
385     FpuMove64 {
386         rd: WritableReg,
387         rn: Reg,
388     },
389     FpuMove128 {
390         rd: WritableReg,
391         rn: Reg,
392     },
393     FpuMoveFromVec {
394         rd: WritableReg,
395         rn: Reg,
396         idx: u8,
397         size: VectorSize,
398     },
399     FpuExtend {
400         rd: WritableReg,
401         rn: Reg,
402         size: ScalarSize,
403     },
404     FpuRR {
405         fpu_op: FPUOp1,
406         rd: WritableReg,
407         rn: Reg,
408     },
409     FpuRRR {
410         fpu_op: FPUOp2,
411         size: ScalarSize,
412         rd: WritableReg,
413         rn: Reg,
414         rm: Reg,
415     },
416     FpuRRI {
417         fpu_op: FPUOpRI,
418         rd: WritableReg,
419         rn: Reg,
420     },
421     FpuRRRR {
422         fpu_op: FPUOp3,
423         rd: WritableReg,
424         rn: Reg,
425         rm: Reg,
426         ra: Reg,
427     },
428     FpuCmp32 {
429         rn: Reg,
430         rm: Reg,
431     },
432     FpuCmp64 {
433         rn: Reg,
434         rm: Reg,
435     },
436     FpuLoad32 {
437         rd: WritableReg,
438         mem: AMode,
439         flags: MemFlags,
440     },
441     FpuStore32 {
442         rd: Reg,
443         mem: AMode,
444         flags: MemFlags,
445     },
446     FpuLoad64 {
447         rd: WritableReg,
448         mem: AMode,
449         flags: MemFlags,
450     },
451     FpuStore64 {
452         rd: Reg,
453         mem: AMode,
454         flags: MemFlags,
455     },
456     FpuLoad128 {
457         rd: WritableReg,
458         mem: AMode,
459         flags: MemFlags,
460     },
461     FpuStore128 {
462         rd: Reg,
463         mem: AMode,
464         flags: MemFlags,
465     },
466     FpuLoadP64 {
467         rt: WritableReg,
468         rt2: WritableReg,
469         mem: PairAMode,
470         flags: MemFlags,
471     },
472     FpuStoreP64 {
473         rt: Reg,
474         rt2: Reg,
475         mem: PairAMode,
476         flags: MemFlags,
477     },
478     FpuLoadP128 {
479         rt: WritableReg,
480         rt2: WritableReg,
481         mem: PairAMode,
482         flags: MemFlags,
483     },
484     FpuStoreP128 {
485         rt: Reg,
486         rt2: Reg,
487         mem: PairAMode,
488         flags: MemFlags,
489     },
490     LoadFpuConst64 {
491         rd: WritableReg,
492         const_data: u64,
493     },
494     LoadFpuConst128 {
495         rd: WritableReg,
496         const_data: u128,
497     },
498     FpuToInt {
499         op: FpuToIntOp,
500         rd: WritableReg,
501         rn: Reg,
502     },
503     IntToFpu {
504         op: IntToFpuOp,
505         rd: WritableReg,
506         rn: Reg,
507     },
508     FpuCSel32 {
509         rd: WritableReg,
510         rn: Reg,
511         rm: Reg,
512         cond: Cond,
513     },
514     FpuCSel64 {
515         rd: WritableReg,
516         rn: Reg,
517         rm: Reg,
518         cond: Cond,
519     },
520     FpuRound {
521         op: FpuRoundMode,
522         rd: WritableReg,
523         rn: Reg,
524     },
525     MovToFpu {
526         rd: WritableReg,
527         rn: Reg,
528         size: ScalarSize,
529     },
530     FpuMoveFPImm {
531         rd: WritableReg,
532         imm: ASIMDFPModImm,
533         size: ScalarSize,
534     },
535     MovToVec {
536         rd: WritableReg,
537         rn: Reg,
538         idx: u8,
539         size: VectorSize,
540     },
541     MovFromVec {
542         rd: WritableReg,
543         rn: Reg,
544         idx: u8,
545         size: VectorSize,
546     },
547     MovFromVecSigned {
548         rd: WritableReg,
549         rn: Reg,
550         idx: u8,
551         size: VectorSize,
552         scalar_size: OperandSize,
553     },
554     VecDup {
555         rd: WritableReg,
556         rn: Reg,
557         size: VectorSize,
558     },
559     VecDupFromFpu {
560         rd: WritableReg,
561         rn: Reg,
562         size: VectorSize,
563     },
564     VecDupFPImm {
565         rd: WritableReg,
566         imm: ASIMDFPModImm,
567         size: VectorSize,
568     },
569     VecDupImm {
570         rd: WritableReg,
571         imm: ASIMDMovModImm,
572         invert: bool,
573         size: VectorSize,
574     },
575     VecExtend {
576         t: VecExtendOp,
577         rd: WritableReg,
578         rn: Reg,
579         high_half: bool,
580     },
581     VecMovElement {
582         rd: WritableReg,
583         rn: Reg,
584         dest_idx: u8,
585         src_idx: u8,
586         size: VectorSize,
587     },
588     VecRRLong {
589         op: VecRRLongOp,
590         rd: WritableReg,
591         rn: Reg,
592         high_half: bool,
593     },
594     VecRRNarrow {
595         op: VecRRNarrowOp,
596         rd: WritableReg,
597         rn: Reg,
598         high_half: bool,
599     },
600     VecRRPair {
601         op: VecPairOp,
602         rd: WritableReg,
603         rn: Reg,
604     },
605     VecRRRLong {
606         alu_op: VecRRRLongOp,
607         rd: WritableReg,
608         rn: Reg,
609         rm: Reg,
610         high_half: bool,
611     },
612     VecRRPairLong {
613         op: VecRRPairLongOp,
614         rd: WritableReg,
615         rn: Reg,
616     },
617     VecRRR {
618         alu_op: VecALUOp,
619         rd: WritableReg,
620         rn: Reg,
621         rm: Reg,
622         size: VectorSize,
623     },
624     VecMisc {
625         op: VecMisc2,
626         rd: WritableReg,
627         rn: Reg,
628         size: VectorSize,
629     },
630     VecLanes {
631         op: VecLanesOp,
632         rd: WritableReg,
633         rn: Reg,
634         size: VectorSize,
635     },
636     VecShiftImm {
637         op: VecShiftImmOp,
638         rd: WritableReg,
639         rn: Reg,
640         size: VectorSize,
641         imm: u8,
642     },
643     VecExtract {
644         rd: WritableReg,
645         rn: Reg,
646         rm: Reg,
647         imm4: u8,
648     },
649     VecTbl {
650         rd: WritableReg,
651         rn: Reg,
652         rm: Reg,
653         is_extension: bool,
654     },
655     VecTbl2 {
656         rd: WritableReg,
657         rn: Reg,
658         rn2: Reg,
659         rm: Reg,
660         is_extension: bool,
661     },
662     VecLoadReplicate {
663         rd: WritableReg,
664         rn: Reg,
665         size: VectorSize,
666     },
667     VecCSel {
668         rd: WritableReg,
669         rn: Reg,
670         rm: Reg,
671         cond: Cond,
672     },
673     MovToNZCV {
674         rn: Reg,
675     },
676     MovFromNZCV {
677         rd: WritableReg,
678     },
679     Call {
680         info: BoxCallInfo,
681     },
682     CallInd {
683         info: BoxCallIndInfo,
684     },
685     Ret {
686         rets: VecReg,
687     },
688     EpiloguePlaceholder,
689     Jump {
690         dest: BranchTarget,
691     },
692     CondBr {
693         taken: BranchTarget,
694         not_taken: BranchTarget,
695         kind: CondBrKind,
696     },
697     TrapIf {
698         kind: CondBrKind,
699         trap_code: TrapCode,
700     },
701     IndirectBr {
702         rn: Reg,
703         targets: VecMachLabel,
704     },
705     Brk,
706     Udf {
707         trap_code: TrapCode,
708     },
709     Adr {
710         rd: WritableReg,
711         off: i32,
712     },
713     Word4 {
714         data: u32,
715     },
716     Word8 {
717         data: u64,
718     },
719     JTSequence {
720         info: BoxJTSequenceInfo,
721         ridx: Reg,
722         rtmp1: WritableReg,
723         rtmp2: WritableReg,
724     },
725     LoadExtName {
726         rd: WritableReg,
727         name: BoxExternalName,
728         offset: i64,
729     },
730     LoadAddr {
731         rd: WritableReg,
732         mem: AMode,
733     },
734     VirtualSPOffsetAdj {
735         offset: i64,
736     },
737     EmitIsland {
738         needed_space: CodeOffset,
739     },
740     ElfTlsGetAddr {
741         symbol: ExternalName,
742     },
743     Unwind {
744         inst: UnwindInst,
745     },
746     DummyUse {
747         reg: Reg,
748     },
749 }
750 
751 /// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 797.
752 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
753 pub enum ALUOp {
754     Add,
755     Sub,
756     Orr,
757     OrrNot,
758     And,
759     AndS,
760     AndNot,
761     Eor,
762     EorNot,
763     AddS,
764     SubS,
765     SMulH,
766     UMulH,
767     SDiv,
768     UDiv,
769     RotR,
770     Lsr,
771     Asr,
772     Lsl,
773     Adc,
774     AdcS,
775     Sbc,
776     SbcS,
777 }
778 
779 /// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 835.
780 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
781 pub enum ALUOp3 {
782     MAdd,
783     MSub,
784 }
785 
786 /// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 874.
787 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
788 pub enum BitOp {
789     RBit,
790     Clz,
791     Cls,
792 }
793 
794 /// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 941.
795 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
796 pub enum FPUOp1 {
797     Abs32,
798     Abs64,
799     Neg32,
800     Neg64,
801     Sqrt32,
802     Sqrt64,
803     Cvt32To64,
804     Cvt64To32,
805 }
806 
807 /// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 954.
808 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
809 pub enum FPUOp2 {
810     Add,
811     Sub,
812     Mul,
813     Div,
814     Max,
815     Min,
816 }
817 
818 /// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 965.
819 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
820 pub enum FPUOp3 {
821     MAdd32,
822     MAdd64,
823 }
824 
825 /// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 972.
826 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
827 pub enum FpuToIntOp {
828     F32ToU32,
829     F32ToI32,
830     F32ToU64,
831     F32ToI64,
832     F64ToU32,
833     F64ToI32,
834     F64ToU64,
835     F64ToI64,
836 }
837 
838 /// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 985.
839 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
840 pub enum IntToFpuOp {
841     U32ToF32,
842     I32ToF32,
843     U32ToF64,
844     I32ToF64,
845     U64ToF32,
846     I64ToF32,
847     U64ToF64,
848     I64ToF64,
849 }
850 
851 /// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 999.
852 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
853 pub enum FpuRoundMode {
854     Minus32,
855     Minus64,
856     Plus32,
857     Plus64,
858     Zero32,
859     Zero64,
860     Nearest32,
861     Nearest64,
862 }
863 
864 /// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 1012.
865 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
866 pub enum VecExtendOp {
867     Sxtl8,
868     Sxtl16,
869     Sxtl32,
870     Uxtl8,
871     Uxtl16,
872     Uxtl32,
873 }
874 
875 /// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1029.
876 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
877 pub enum VecALUOp {
878     Sqadd,
879     Uqadd,
880     Sqsub,
881     Uqsub,
882     Cmeq,
883     Cmge,
884     Cmgt,
885     Cmhs,
886     Cmhi,
887     Fcmeq,
888     Fcmgt,
889     Fcmge,
890     And,
891     Bic,
892     Orr,
893     Eor,
894     Bsl,
895     Umaxp,
896     Add,
897     Sub,
898     Mul,
899     Sshl,
900     Ushl,
901     Umin,
902     Smin,
903     Umax,
904     Smax,
905     Urhadd,
906     Fadd,
907     Fsub,
908     Fdiv,
909     Fmax,
910     Fmin,
911     Fmul,
912     Addp,
913     Zip1,
914     Sqrdmulh,
915 }
916 
917 /// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1108.
918 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
919 pub enum VecMisc2 {
920     Not,
921     Neg,
922     Abs,
923     Fabs,
924     Fneg,
925     Fsqrt,
926     Rev64,
927     Fcvtzs,
928     Fcvtzu,
929     Scvtf,
930     Ucvtf,
931     Frintn,
932     Frintz,
933     Frintm,
934     Frintp,
935     Cnt,
936     Cmeq0,
937     Cmge0,
938     Cmgt0,
939     Cmle0,
940     Cmlt0,
941     Fcmeq0,
942     Fcmge0,
943     Fcmgt0,
944     Fcmle0,
945     Fcmlt0,
946 }
947 
948 /// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1165.
949 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
950 pub enum VecRRLongOp {
951     Fcvtl16,
952     Fcvtl32,
953     Shll8,
954     Shll16,
955     Shll32,
956 }
957 
958 /// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1180.
959 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
960 pub enum VecRRNarrowOp {
961     Xtn16,
962     Xtn32,
963     Xtn64,
964     Sqxtn16,
965     Sqxtn32,
966     Sqxtn64,
967     Sqxtun16,
968     Sqxtun32,
969     Sqxtun64,
970     Uqxtn16,
971     Uqxtn32,
972     Uqxtn64,
973     Fcvtn32,
974     Fcvtn64,
975 }
976 
977 /// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1212.
978 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
979 pub enum VecRRRLongOp {
980     Smull8,
981     Smull16,
982     Smull32,
983     Umull8,
984     Umull16,
985     Umull32,
986     Umlal8,
987     Umlal16,
988     Umlal32,
989 }
990 
991 /// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1229.
992 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
993 pub enum VecPairOp {
994     Addp,
995 }
996 
997 /// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1237.
998 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
999 pub enum VecRRPairLongOp {
1000     Saddlp8,
1001     Saddlp16,
1002     Uaddlp8,
1003     Uaddlp16,
1004 }
1005 
1006 /// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1248.
1007 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1008 pub enum VecLanesOp {
1009     Addv,
1010     Uminv,
1011 }
1012 
1013 /// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1257.
1014 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1015 pub enum VecShiftImmOp {
1016     Shl,
1017     Ushr,
1018     Sshr,
1019 }
1020 
1021 /// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1268.
1022 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1023 pub enum AtomicRMWOp {
1024     Add,
1025     Clr,
1026     Eor,
1027     Set,
1028     Smax,
1029     Smin,
1030     Umax,
1031     Umin,
1032 }
1033 
1034 // Generated as internal constructor for term output_reg.
1035 pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
1036     let pattern0_0 = arg0;
1037     // Rule at src/prelude.isle line 86.
1038     let expr0_0 = C::value_reg(ctx, pattern0_0);
1039     let expr1_0 = C::output(ctx, expr0_0);
1040     return Some(expr1_0);
1041 }
1042 
1043 // Generated as internal constructor for term output_value.
1044 pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> {
1045     let pattern0_0 = arg0;
1046     // Rule at src/prelude.isle line 90.
1047     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1048     let expr1_0 = C::output(ctx, expr0_0);
1049     return Some(expr1_0);
1050 }
1051 
1052 // Generated as internal constructor for term temp_reg.
1053 pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
1054     let pattern0_0 = arg0;
1055     // Rule at src/prelude.isle line 110.
1056     let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
1057     let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
1058     return Some(expr1_0);
1059 }
1060 
1061 // Generated as internal constructor for term lo_reg.
1062 pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
1063     let pattern0_0 = arg0;
1064     // Rule at src/prelude.isle line 145.
1065     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1066     let expr1_0: usize = 0;
1067     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1068     return Some(expr2_0);
1069 }
1070 
1071 // Generated as internal constructor for term side_effect.
1072 pub fn constructor_side_effect<C: Context>(
1073     ctx: &mut C,
1074     arg0: &SideEffectNoResult,
1075 ) -> Option<InstOutput> {
1076     let pattern0_0 = arg0;
1077     if let &SideEffectNoResult::Inst {
1078         inst: ref pattern1_0,
1079     } = pattern0_0
1080     {
1081         // Rule at src/prelude.isle line 407.
1082         let expr0_0 = C::emit(ctx, pattern1_0);
1083         let expr1_0 = C::output_none(ctx);
1084         return Some(expr1_0);
1085     }
1086     return None;
1087 }
1088 
1089 // Generated as internal constructor for term produces_flags_get_reg.
1090 pub fn constructor_produces_flags_get_reg<C: Context>(
1091     ctx: &mut C,
1092     arg0: &ProducesFlags,
1093 ) -> Option<Reg> {
1094     let pattern0_0 = arg0;
1095     if let &ProducesFlags::ProducesFlagsReturnsReg {
1096         inst: ref pattern1_0,
1097         result: pattern1_1,
1098     } = pattern0_0
1099     {
1100         // Rule at src/prelude.isle line 445.
1101         return Some(pattern1_1);
1102     }
1103     return None;
1104 }
1105 
1106 // Generated as internal constructor for term produces_flags_ignore.
1107 pub fn constructor_produces_flags_ignore<C: Context>(
1108     ctx: &mut C,
1109     arg0: &ProducesFlags,
1110 ) -> Option<ProducesFlags> {
1111     let pattern0_0 = arg0;
1112     match pattern0_0 {
1113         &ProducesFlags::ProducesFlagsReturnsReg {
1114             inst: ref pattern1_0,
1115             result: pattern1_1,
1116         } => {
1117             // Rule at src/prelude.isle line 450.
1118             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1119                 inst: pattern1_0.clone(),
1120             };
1121             return Some(expr0_0);
1122         }
1123         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1124             inst: ref pattern1_0,
1125             result: pattern1_1,
1126         } => {
1127             // Rule at src/prelude.isle line 452.
1128             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1129                 inst: pattern1_0.clone(),
1130             };
1131             return Some(expr0_0);
1132         }
1133         _ => {}
1134     }
1135     return None;
1136 }
1137 
1138 // Generated as internal constructor for term consumes_flags_concat.
1139 pub fn constructor_consumes_flags_concat<C: Context>(
1140     ctx: &mut C,
1141     arg0: &ConsumesFlags,
1142     arg1: &ConsumesFlags,
1143 ) -> Option<ConsumesFlags> {
1144     let pattern0_0 = arg0;
1145     if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1146         inst: ref pattern1_0,
1147         result: pattern1_1,
1148     } = pattern0_0
1149     {
1150         let pattern2_0 = arg1;
1151         if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1152             inst: ref pattern3_0,
1153             result: pattern3_1,
1154         } = pattern2_0
1155         {
1156             // Rule at src/prelude.isle line 459.
1157             let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1158             let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1159                 inst1: pattern1_0.clone(),
1160                 inst2: pattern3_0.clone(),
1161                 result: expr0_0,
1162             };
1163             return Some(expr1_0);
1164         }
1165     }
1166     return None;
1167 }
1168 
1169 // Generated as internal constructor for term with_flags.
1170 pub fn constructor_with_flags<C: Context>(
1171     ctx: &mut C,
1172     arg0: &ProducesFlags,
1173     arg1: &ConsumesFlags,
1174 ) -> Option<ValueRegs> {
1175     let pattern0_0 = arg0;
1176     match pattern0_0 {
1177         &ProducesFlags::ProducesFlagsSideEffect {
1178             inst: ref pattern1_0,
1179         } => {
1180             let pattern2_0 = arg1;
1181             match pattern2_0 {
1182                 &ConsumesFlags::ConsumesFlagsReturnsReg {
1183                     inst: ref pattern3_0,
1184                     result: pattern3_1,
1185                 } => {
1186                     // Rule at src/prelude.isle line 484.
1187                     let expr0_0 = C::emit(ctx, pattern1_0);
1188                     let expr1_0 = C::emit(ctx, pattern3_0);
1189                     let expr2_0 = C::value_reg(ctx, pattern3_1);
1190                     return Some(expr2_0);
1191                 }
1192                 &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1193                     inst1: ref pattern3_0,
1194                     inst2: ref pattern3_1,
1195                     result: pattern3_2,
1196                 } => {
1197                     // Rule at src/prelude.isle line 490.
1198                     let expr0_0 = C::emit(ctx, pattern1_0);
1199                     let expr1_0 = C::emit(ctx, pattern3_0);
1200                     let expr2_0 = C::emit(ctx, pattern3_1);
1201                     return Some(pattern3_2);
1202                 }
1203                 &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs {
1204                     inst1: ref pattern3_0,
1205                     inst2: ref pattern3_1,
1206                     inst3: ref pattern3_2,
1207                     inst4: ref pattern3_3,
1208                     result: pattern3_4,
1209                 } => {
1210                     // Rule at src/prelude.isle line 502.
1211                     let expr0_0 = C::emit(ctx, pattern1_0);
1212                     let expr1_0 = C::emit(ctx, pattern3_0);
1213                     let expr2_0 = C::emit(ctx, pattern3_1);
1214                     let expr3_0 = C::emit(ctx, pattern3_2);
1215                     let expr4_0 = C::emit(ctx, pattern3_3);
1216                     return Some(pattern3_4);
1217                 }
1218                 _ => {}
1219             }
1220         }
1221         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1222             inst: ref pattern1_0,
1223             result: pattern1_1,
1224         } => {
1225             let pattern2_0 = arg1;
1226             if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1227                 inst: ref pattern3_0,
1228                 result: pattern3_1,
1229             } = pattern2_0
1230             {
1231                 // Rule at src/prelude.isle line 478.
1232                 let expr0_0 = C::emit(ctx, pattern1_0);
1233                 let expr1_0 = C::emit(ctx, pattern3_0);
1234                 let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1235                 return Some(expr2_0);
1236             }
1237         }
1238         _ => {}
1239     }
1240     return None;
1241 }
1242 
1243 // Generated as internal constructor for term with_flags_reg.
1244 pub fn constructor_with_flags_reg<C: Context>(
1245     ctx: &mut C,
1246     arg0: &ProducesFlags,
1247     arg1: &ConsumesFlags,
1248 ) -> Option<Reg> {
1249     let pattern0_0 = arg0;
1250     let pattern1_0 = arg1;
1251     // Rule at src/prelude.isle line 519.
1252     let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?;
1253     let expr1_0: usize = 0;
1254     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1255     return Some(expr2_0);
1256 }
1257 
1258 // Generated as internal constructor for term operand_size.
1259 pub fn constructor_operand_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
1260     let pattern0_0 = arg0;
1261     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
1262         // Rule at src/isa/aarch64/inst.isle line 892.
1263         let expr0_0 = OperandSize::Size32;
1264         return Some(expr0_0);
1265     }
1266     if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
1267         // Rule at src/isa/aarch64/inst.isle line 893.
1268         let expr0_0 = OperandSize::Size64;
1269         return Some(expr0_0);
1270     }
1271     return None;
1272 }
1273 
1274 // Generated as internal constructor for term vector_size.
1275 pub fn constructor_vector_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<VectorSize> {
1276     let pattern0_0 = arg0;
1277     if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
1278         if pattern1_0 == 8 {
1279             if pattern1_1 == 16 {
1280                 // Rule at src/isa/aarch64/inst.isle line 935.
1281                 let expr0_0 = VectorSize::Size8x16;
1282                 return Some(expr0_0);
1283             }
1284         }
1285         if pattern1_0 == 16 {
1286             if pattern1_1 == 8 {
1287                 // Rule at src/isa/aarch64/inst.isle line 936.
1288                 let expr0_0 = VectorSize::Size16x8;
1289                 return Some(expr0_0);
1290             }
1291         }
1292         if pattern1_0 == 32 {
1293             if pattern1_1 == 4 {
1294                 // Rule at src/isa/aarch64/inst.isle line 937.
1295                 let expr0_0 = VectorSize::Size32x4;
1296                 return Some(expr0_0);
1297             }
1298         }
1299         if pattern1_0 == 64 {
1300             if pattern1_1 == 2 {
1301                 // Rule at src/isa/aarch64/inst.isle line 938.
1302                 let expr0_0 = VectorSize::Size64x2;
1303                 return Some(expr0_0);
1304             }
1305         }
1306     }
1307     return None;
1308 }
1309 
1310 // Generated as internal constructor for term movz.
1311 pub fn constructor_movz<C: Context>(
1312     ctx: &mut C,
1313     arg0: MoveWideConst,
1314     arg1: &OperandSize,
1315 ) -> Option<Reg> {
1316     let pattern0_0 = arg0;
1317     let pattern1_0 = arg1;
1318     // Rule at src/isa/aarch64/inst.isle line 1364.
1319     let expr0_0: Type = I64;
1320     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1321     let expr2_0 = MInst::MovZ {
1322         rd: expr1_0,
1323         imm: pattern0_0,
1324         size: pattern1_0.clone(),
1325     };
1326     let expr3_0 = C::emit(ctx, &expr2_0);
1327     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1328     return Some(expr4_0);
1329 }
1330 
1331 // Generated as internal constructor for term movn.
1332 pub fn constructor_movn<C: Context>(
1333     ctx: &mut C,
1334     arg0: MoveWideConst,
1335     arg1: &OperandSize,
1336 ) -> Option<Reg> {
1337     let pattern0_0 = arg0;
1338     let pattern1_0 = arg1;
1339     // Rule at src/isa/aarch64/inst.isle line 1371.
1340     let expr0_0: Type = I64;
1341     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1342     let expr2_0 = MInst::MovN {
1343         rd: expr1_0,
1344         imm: pattern0_0,
1345         size: pattern1_0.clone(),
1346     };
1347     let expr3_0 = C::emit(ctx, &expr2_0);
1348     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1349     return Some(expr4_0);
1350 }
1351 
1352 // Generated as internal constructor for term alu_rr_imm_logic.
1353 pub fn constructor_alu_rr_imm_logic<C: Context>(
1354     ctx: &mut C,
1355     arg0: &ALUOp,
1356     arg1: Type,
1357     arg2: Reg,
1358     arg3: ImmLogic,
1359 ) -> Option<Reg> {
1360     let pattern0_0 = arg0;
1361     let pattern1_0 = arg1;
1362     let pattern2_0 = arg2;
1363     let pattern3_0 = arg3;
1364     // Rule at src/isa/aarch64/inst.isle line 1378.
1365     let expr0_0: Type = I64;
1366     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1367     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1368     let expr3_0 = MInst::AluRRImmLogic {
1369         alu_op: pattern0_0.clone(),
1370         size: expr2_0,
1371         rd: expr1_0,
1372         rn: pattern2_0,
1373         imml: pattern3_0,
1374     };
1375     let expr4_0 = C::emit(ctx, &expr3_0);
1376     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1377     return Some(expr5_0);
1378 }
1379 
1380 // Generated as internal constructor for term alu_rr_imm_shift.
1381 pub fn constructor_alu_rr_imm_shift<C: Context>(
1382     ctx: &mut C,
1383     arg0: &ALUOp,
1384     arg1: Type,
1385     arg2: Reg,
1386     arg3: ImmShift,
1387 ) -> Option<Reg> {
1388     let pattern0_0 = arg0;
1389     let pattern1_0 = arg1;
1390     let pattern2_0 = arg2;
1391     let pattern3_0 = arg3;
1392     // Rule at src/isa/aarch64/inst.isle line 1385.
1393     let expr0_0: Type = I64;
1394     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1395     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1396     let expr3_0 = MInst::AluRRImmShift {
1397         alu_op: pattern0_0.clone(),
1398         size: expr2_0,
1399         rd: expr1_0,
1400         rn: pattern2_0,
1401         immshift: pattern3_0,
1402     };
1403     let expr4_0 = C::emit(ctx, &expr3_0);
1404     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1405     return Some(expr5_0);
1406 }
1407 
1408 // Generated as internal constructor for term alu_rrr.
1409 pub fn constructor_alu_rrr<C: Context>(
1410     ctx: &mut C,
1411     arg0: &ALUOp,
1412     arg1: Type,
1413     arg2: Reg,
1414     arg3: Reg,
1415 ) -> Option<Reg> {
1416     let pattern0_0 = arg0;
1417     let pattern1_0 = arg1;
1418     let pattern2_0 = arg2;
1419     let pattern3_0 = arg3;
1420     // Rule at src/isa/aarch64/inst.isle line 1392.
1421     let expr0_0: Type = I64;
1422     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1423     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1424     let expr3_0 = MInst::AluRRR {
1425         alu_op: pattern0_0.clone(),
1426         size: expr2_0,
1427         rd: expr1_0,
1428         rn: pattern2_0,
1429         rm: pattern3_0,
1430     };
1431     let expr4_0 = C::emit(ctx, &expr3_0);
1432     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1433     return Some(expr5_0);
1434 }
1435 
1436 // Generated as internal constructor for term vec_rrr.
1437 pub fn constructor_vec_rrr<C: Context>(
1438     ctx: &mut C,
1439     arg0: &VecALUOp,
1440     arg1: Reg,
1441     arg2: Reg,
1442     arg3: &VectorSize,
1443 ) -> Option<Reg> {
1444     let pattern0_0 = arg0;
1445     let pattern1_0 = arg1;
1446     let pattern2_0 = arg2;
1447     let pattern3_0 = arg3;
1448     // Rule at src/isa/aarch64/inst.isle line 1399.
1449     let expr0_0: Type = I8X16;
1450     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1451     let expr2_0 = MInst::VecRRR {
1452         alu_op: pattern0_0.clone(),
1453         rd: expr1_0,
1454         rn: pattern1_0,
1455         rm: pattern2_0,
1456         size: pattern3_0.clone(),
1457     };
1458     let expr3_0 = C::emit(ctx, &expr2_0);
1459     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1460     return Some(expr4_0);
1461 }
1462 
1463 // Generated as internal constructor for term vec_lanes.
1464 pub fn constructor_vec_lanes<C: Context>(
1465     ctx: &mut C,
1466     arg0: &VecLanesOp,
1467     arg1: Reg,
1468     arg2: &VectorSize,
1469 ) -> Option<Reg> {
1470     let pattern0_0 = arg0;
1471     let pattern1_0 = arg1;
1472     let pattern2_0 = arg2;
1473     // Rule at src/isa/aarch64/inst.isle line 1406.
1474     let expr0_0: Type = I8X16;
1475     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1476     let expr2_0 = MInst::VecLanes {
1477         op: pattern0_0.clone(),
1478         rd: expr1_0,
1479         rn: pattern1_0,
1480         size: pattern2_0.clone(),
1481     };
1482     let expr3_0 = C::emit(ctx, &expr2_0);
1483     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1484     return Some(expr4_0);
1485 }
1486 
1487 // Generated as internal constructor for term vec_dup.
1488 pub fn constructor_vec_dup<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
1489     let pattern0_0 = arg0;
1490     let pattern1_0 = arg1;
1491     // Rule at src/isa/aarch64/inst.isle line 1413.
1492     let expr0_0: Type = I8X16;
1493     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1494     let expr2_0 = MInst::VecDup {
1495         rd: expr1_0,
1496         rn: pattern0_0,
1497         size: pattern1_0.clone(),
1498     };
1499     let expr3_0 = C::emit(ctx, &expr2_0);
1500     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1501     return Some(expr4_0);
1502 }
1503 
1504 // Generated as internal constructor for term alu_rr_imm12.
1505 pub fn constructor_alu_rr_imm12<C: Context>(
1506     ctx: &mut C,
1507     arg0: &ALUOp,
1508     arg1: Type,
1509     arg2: Reg,
1510     arg3: Imm12,
1511 ) -> Option<Reg> {
1512     let pattern0_0 = arg0;
1513     let pattern1_0 = arg1;
1514     let pattern2_0 = arg2;
1515     let pattern3_0 = arg3;
1516     // Rule at src/isa/aarch64/inst.isle line 1420.
1517     let expr0_0: Type = I64;
1518     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1519     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1520     let expr3_0 = MInst::AluRRImm12 {
1521         alu_op: pattern0_0.clone(),
1522         size: expr2_0,
1523         rd: expr1_0,
1524         rn: pattern2_0,
1525         imm12: pattern3_0,
1526     };
1527     let expr4_0 = C::emit(ctx, &expr3_0);
1528     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1529     return Some(expr5_0);
1530 }
1531 
1532 // Generated as internal constructor for term alu_rrr_shift.
1533 pub fn constructor_alu_rrr_shift<C: Context>(
1534     ctx: &mut C,
1535     arg0: &ALUOp,
1536     arg1: Type,
1537     arg2: Reg,
1538     arg3: Reg,
1539     arg4: ShiftOpAndAmt,
1540 ) -> Option<Reg> {
1541     let pattern0_0 = arg0;
1542     let pattern1_0 = arg1;
1543     let pattern2_0 = arg2;
1544     let pattern3_0 = arg3;
1545     let pattern4_0 = arg4;
1546     // Rule at src/isa/aarch64/inst.isle line 1427.
1547     let expr0_0: Type = I64;
1548     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1549     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1550     let expr3_0 = MInst::AluRRRShift {
1551         alu_op: pattern0_0.clone(),
1552         size: expr2_0,
1553         rd: expr1_0,
1554         rn: pattern2_0,
1555         rm: pattern3_0,
1556         shiftop: pattern4_0,
1557     };
1558     let expr4_0 = C::emit(ctx, &expr3_0);
1559     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1560     return Some(expr5_0);
1561 }
1562 
1563 // Generated as internal constructor for term alu_rrr_extend.
1564 pub fn constructor_alu_rrr_extend<C: Context>(
1565     ctx: &mut C,
1566     arg0: &ALUOp,
1567     arg1: Type,
1568     arg2: Reg,
1569     arg3: Reg,
1570     arg4: &ExtendOp,
1571 ) -> Option<Reg> {
1572     let pattern0_0 = arg0;
1573     let pattern1_0 = arg1;
1574     let pattern2_0 = arg2;
1575     let pattern3_0 = arg3;
1576     let pattern4_0 = arg4;
1577     // Rule at src/isa/aarch64/inst.isle line 1434.
1578     let expr0_0: Type = I64;
1579     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1580     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1581     let expr3_0 = MInst::AluRRRExtend {
1582         alu_op: pattern0_0.clone(),
1583         size: expr2_0,
1584         rd: expr1_0,
1585         rn: pattern2_0,
1586         rm: pattern3_0,
1587         extendop: pattern4_0.clone(),
1588     };
1589     let expr4_0 = C::emit(ctx, &expr3_0);
1590     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1591     return Some(expr5_0);
1592 }
1593 
1594 // Generated as internal constructor for term alu_rr_extend_reg.
1595 pub fn constructor_alu_rr_extend_reg<C: Context>(
1596     ctx: &mut C,
1597     arg0: &ALUOp,
1598     arg1: Type,
1599     arg2: Reg,
1600     arg3: &ExtendedValue,
1601 ) -> Option<Reg> {
1602     let pattern0_0 = arg0;
1603     let pattern1_0 = arg1;
1604     let pattern2_0 = arg2;
1605     let pattern3_0 = arg3;
1606     // Rule at src/isa/aarch64/inst.isle line 1442.
1607     let expr0_0 = C::put_extended_in_reg(ctx, pattern3_0);
1608     let expr1_0 = C::get_extended_op(ctx, pattern3_0);
1609     let expr2_0 =
1610         constructor_alu_rrr_extend(ctx, pattern0_0, pattern1_0, pattern2_0, expr0_0, &expr1_0)?;
1611     return Some(expr2_0);
1612 }
1613 
1614 // Generated as internal constructor for term alu_rrrr.
1615 pub fn constructor_alu_rrrr<C: Context>(
1616     ctx: &mut C,
1617     arg0: &ALUOp3,
1618     arg1: Type,
1619     arg2: Reg,
1620     arg3: Reg,
1621     arg4: Reg,
1622 ) -> Option<Reg> {
1623     let pattern0_0 = arg0;
1624     let pattern1_0 = arg1;
1625     let pattern2_0 = arg2;
1626     let pattern3_0 = arg3;
1627     let pattern4_0 = arg4;
1628     // Rule at src/isa/aarch64/inst.isle line 1449.
1629     let expr0_0: Type = I64;
1630     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1631     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1632     let expr3_0 = MInst::AluRRRR {
1633         alu_op: pattern0_0.clone(),
1634         size: expr2_0,
1635         rd: expr1_0,
1636         rn: pattern2_0,
1637         rm: pattern3_0,
1638         ra: pattern4_0,
1639     };
1640     let expr4_0 = C::emit(ctx, &expr3_0);
1641     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1642     return Some(expr5_0);
1643 }
1644 
1645 // Generated as internal constructor for term bit_rr.
1646 pub fn constructor_bit_rr<C: Context>(
1647     ctx: &mut C,
1648     arg0: &BitOp,
1649     arg1: Type,
1650     arg2: Reg,
1651 ) -> Option<Reg> {
1652     let pattern0_0 = arg0;
1653     let pattern1_0 = arg1;
1654     let pattern2_0 = arg2;
1655     // Rule at src/isa/aarch64/inst.isle line 1456.
1656     let expr0_0: Type = I64;
1657     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1658     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1659     let expr3_0 = MInst::BitRR {
1660         op: pattern0_0.clone(),
1661         size: expr2_0,
1662         rd: expr1_0,
1663         rn: pattern2_0,
1664     };
1665     let expr4_0 = C::emit(ctx, &expr3_0);
1666     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1667     return Some(expr5_0);
1668 }
1669 
1670 // Generated as internal constructor for term add_with_flags_paired.
1671 pub fn constructor_add_with_flags_paired<C: Context>(
1672     ctx: &mut C,
1673     arg0: Type,
1674     arg1: Reg,
1675     arg2: Reg,
1676 ) -> Option<ProducesFlags> {
1677     let pattern0_0 = arg0;
1678     let pattern1_0 = arg1;
1679     let pattern2_0 = arg2;
1680     // Rule at src/isa/aarch64/inst.isle line 1463.
1681     let expr0_0: Type = I64;
1682     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1683     let expr2_0 = ALUOp::AddS;
1684     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1685     let expr4_0 = MInst::AluRRR {
1686         alu_op: expr2_0,
1687         size: expr3_0,
1688         rd: expr1_0,
1689         rn: pattern1_0,
1690         rm: pattern2_0,
1691     };
1692     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1693     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1694         inst: expr4_0,
1695         result: expr5_0,
1696     };
1697     return Some(expr6_0);
1698 }
1699 
1700 // Generated as internal constructor for term adc_paired.
1701 pub fn constructor_adc_paired<C: Context>(
1702     ctx: &mut C,
1703     arg0: Type,
1704     arg1: Reg,
1705     arg2: Reg,
1706 ) -> Option<ConsumesFlags> {
1707     let pattern0_0 = arg0;
1708     let pattern1_0 = arg1;
1709     let pattern2_0 = arg2;
1710     // Rule at src/isa/aarch64/inst.isle line 1471.
1711     let expr0_0: Type = I64;
1712     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1713     let expr2_0 = ALUOp::Adc;
1714     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1715     let expr4_0 = MInst::AluRRR {
1716         alu_op: expr2_0,
1717         size: expr3_0,
1718         rd: expr1_0,
1719         rn: pattern1_0,
1720         rm: pattern2_0,
1721     };
1722     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1723     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1724         inst: expr4_0,
1725         result: expr5_0,
1726     };
1727     return Some(expr6_0);
1728 }
1729 
1730 // Generated as internal constructor for term sub_with_flags_paired.
1731 pub fn constructor_sub_with_flags_paired<C: Context>(
1732     ctx: &mut C,
1733     arg0: Type,
1734     arg1: Reg,
1735     arg2: Reg,
1736 ) -> Option<ProducesFlags> {
1737     let pattern0_0 = arg0;
1738     let pattern1_0 = arg1;
1739     let pattern2_0 = arg2;
1740     // Rule at src/isa/aarch64/inst.isle line 1479.
1741     let expr0_0: Type = I64;
1742     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1743     let expr2_0 = ALUOp::SubS;
1744     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1745     let expr4_0 = MInst::AluRRR {
1746         alu_op: expr2_0,
1747         size: expr3_0,
1748         rd: expr1_0,
1749         rn: pattern1_0,
1750         rm: pattern2_0,
1751     };
1752     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1753     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1754         inst: expr4_0,
1755         result: expr5_0,
1756     };
1757     return Some(expr6_0);
1758 }
1759 
1760 // Generated as internal constructor for term cmp64_imm.
1761 pub fn constructor_cmp64_imm<C: Context>(
1762     ctx: &mut C,
1763     arg0: Reg,
1764     arg1: Imm12,
1765 ) -> Option<ProducesFlags> {
1766     let pattern0_0 = arg0;
1767     let pattern1_0 = arg1;
1768     // Rule at src/isa/aarch64/inst.isle line 1486.
1769     let expr0_0 = ALUOp::SubS;
1770     let expr1_0 = OperandSize::Size64;
1771     let expr2_0 = C::writable_zero_reg(ctx);
1772     let expr3_0 = MInst::AluRRImm12 {
1773         alu_op: expr0_0,
1774         size: expr1_0,
1775         rd: expr2_0,
1776         rn: pattern0_0,
1777         imm12: pattern1_0,
1778     };
1779     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
1780     return Some(expr4_0);
1781 }
1782 
1783 // Generated as internal constructor for term sbc_paired.
1784 pub fn constructor_sbc_paired<C: Context>(
1785     ctx: &mut C,
1786     arg0: Type,
1787     arg1: Reg,
1788     arg2: Reg,
1789 ) -> Option<ConsumesFlags> {
1790     let pattern0_0 = arg0;
1791     let pattern1_0 = arg1;
1792     let pattern2_0 = arg2;
1793     // Rule at src/isa/aarch64/inst.isle line 1493.
1794     let expr0_0: Type = I64;
1795     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1796     let expr2_0 = ALUOp::Sbc;
1797     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1798     let expr4_0 = MInst::AluRRR {
1799         alu_op: expr2_0,
1800         size: expr3_0,
1801         rd: expr1_0,
1802         rn: pattern1_0,
1803         rm: pattern2_0,
1804     };
1805     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1806     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1807         inst: expr4_0,
1808         result: expr5_0,
1809     };
1810     return Some(expr6_0);
1811 }
1812 
1813 // Generated as internal constructor for term vec_misc.
1814 pub fn constructor_vec_misc<C: Context>(
1815     ctx: &mut C,
1816     arg0: &VecMisc2,
1817     arg1: Reg,
1818     arg2: &VectorSize,
1819 ) -> Option<Reg> {
1820     let pattern0_0 = arg0;
1821     let pattern1_0 = arg1;
1822     let pattern2_0 = arg2;
1823     // Rule at src/isa/aarch64/inst.isle line 1501.
1824     let expr0_0: Type = I8X16;
1825     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1826     let expr2_0 = MInst::VecMisc {
1827         op: pattern0_0.clone(),
1828         rd: expr1_0,
1829         rn: pattern1_0,
1830         size: pattern2_0.clone(),
1831     };
1832     let expr3_0 = C::emit(ctx, &expr2_0);
1833     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1834     return Some(expr4_0);
1835 }
1836 
1837 // Generated as internal constructor for term vec_rrr_long.
1838 pub fn constructor_vec_rrr_long<C: Context>(
1839     ctx: &mut C,
1840     arg0: &VecRRRLongOp,
1841     arg1: Reg,
1842     arg2: Reg,
1843     arg3: bool,
1844 ) -> Option<Reg> {
1845     let pattern0_0 = arg0;
1846     let pattern1_0 = arg1;
1847     let pattern2_0 = arg2;
1848     let pattern3_0 = arg3;
1849     // Rule at src/isa/aarch64/inst.isle line 1508.
1850     let expr0_0: Type = I8X16;
1851     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1852     let expr2_0 = MInst::VecRRRLong {
1853         alu_op: pattern0_0.clone(),
1854         rd: expr1_0,
1855         rn: pattern1_0,
1856         rm: pattern2_0,
1857         high_half: pattern3_0,
1858     };
1859     let expr3_0 = C::emit(ctx, &expr2_0);
1860     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1861     return Some(expr4_0);
1862 }
1863 
1864 // Generated as internal constructor for term vec_rrrr_long.
1865 pub fn constructor_vec_rrrr_long<C: Context>(
1866     ctx: &mut C,
1867     arg0: &VecRRRLongOp,
1868     arg1: Reg,
1869     arg2: Reg,
1870     arg3: Reg,
1871     arg4: bool,
1872 ) -> Option<Reg> {
1873     let pattern0_0 = arg0;
1874     let pattern1_0 = arg1;
1875     let pattern2_0 = arg2;
1876     let pattern3_0 = arg3;
1877     let pattern4_0 = arg4;
1878     // Rule at src/isa/aarch64/inst.isle line 1518.
1879     let expr0_0: Type = I8X16;
1880     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1881     let expr2_0 = MInst::FpuMove128 {
1882         rd: expr1_0,
1883         rn: pattern1_0,
1884     };
1885     let expr3_0 = C::emit(ctx, &expr2_0);
1886     let expr4_0 = MInst::VecRRRLong {
1887         alu_op: pattern0_0.clone(),
1888         rd: expr1_0,
1889         rn: pattern2_0,
1890         rm: pattern3_0,
1891         high_half: pattern4_0,
1892     };
1893     let expr5_0 = C::emit(ctx, &expr4_0);
1894     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1895     return Some(expr6_0);
1896 }
1897 
1898 // Generated as internal constructor for term vec_rr_narrow.
1899 pub fn constructor_vec_rr_narrow<C: Context>(
1900     ctx: &mut C,
1901     arg0: &VecRRNarrowOp,
1902     arg1: Reg,
1903     arg2: bool,
1904 ) -> Option<Reg> {
1905     let pattern0_0 = arg0;
1906     let pattern1_0 = arg1;
1907     let pattern2_0 = arg2;
1908     // Rule at src/isa/aarch64/inst.isle line 1526.
1909     let expr0_0: Type = I8X16;
1910     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1911     let expr2_0 = MInst::VecRRNarrow {
1912         op: pattern0_0.clone(),
1913         rd: expr1_0,
1914         rn: pattern1_0,
1915         high_half: pattern2_0,
1916     };
1917     let expr3_0 = C::emit(ctx, &expr2_0);
1918     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1919     return Some(expr4_0);
1920 }
1921 
1922 // Generated as internal constructor for term vec_rr_long.
1923 pub fn constructor_vec_rr_long<C: Context>(
1924     ctx: &mut C,
1925     arg0: &VecRRLongOp,
1926     arg1: Reg,
1927     arg2: bool,
1928 ) -> Option<Reg> {
1929     let pattern0_0 = arg0;
1930     let pattern1_0 = arg1;
1931     let pattern2_0 = arg2;
1932     // Rule at src/isa/aarch64/inst.isle line 1533.
1933     let expr0_0: Type = I8X16;
1934     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1935     let expr2_0 = MInst::VecRRLong {
1936         op: pattern0_0.clone(),
1937         rd: expr1_0,
1938         rn: pattern1_0,
1939         high_half: pattern2_0,
1940     };
1941     let expr3_0 = C::emit(ctx, &expr2_0);
1942     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1943     return Some(expr4_0);
1944 }
1945 
1946 // Generated as internal constructor for term mov_to_fpu.
1947 pub fn constructor_mov_to_fpu<C: Context>(
1948     ctx: &mut C,
1949     arg0: Reg,
1950     arg1: &ScalarSize,
1951 ) -> Option<Reg> {
1952     let pattern0_0 = arg0;
1953     let pattern1_0 = arg1;
1954     // Rule at src/isa/aarch64/inst.isle line 1540.
1955     let expr0_0: Type = I8X16;
1956     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1957     let expr2_0 = MInst::MovToFpu {
1958         rd: expr1_0,
1959         rn: pattern0_0,
1960         size: pattern1_0.clone(),
1961     };
1962     let expr3_0 = C::emit(ctx, &expr2_0);
1963     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1964     return Some(expr4_0);
1965 }
1966 
1967 // Generated as internal constructor for term mov_to_vec.
1968 pub fn constructor_mov_to_vec<C: Context>(
1969     ctx: &mut C,
1970     arg0: Reg,
1971     arg1: Reg,
1972     arg2: u8,
1973     arg3: &VectorSize,
1974 ) -> Option<Reg> {
1975     let pattern0_0 = arg0;
1976     let pattern1_0 = arg1;
1977     let pattern2_0 = arg2;
1978     let pattern3_0 = arg3;
1979     // Rule at src/isa/aarch64/inst.isle line 1547.
1980     let expr0_0: Type = I8X16;
1981     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1982     let expr2_0 = MInst::FpuMove128 {
1983         rd: expr1_0,
1984         rn: pattern0_0,
1985     };
1986     let expr3_0 = C::emit(ctx, &expr2_0);
1987     let expr4_0 = MInst::MovToVec {
1988         rd: expr1_0,
1989         rn: pattern1_0,
1990         idx: pattern2_0,
1991         size: pattern3_0.clone(),
1992     };
1993     let expr5_0 = C::emit(ctx, &expr4_0);
1994     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1995     return Some(expr6_0);
1996 }
1997 
1998 // Generated as internal constructor for term mov_from_vec.
1999 pub fn constructor_mov_from_vec<C: Context>(
2000     ctx: &mut C,
2001     arg0: Reg,
2002     arg1: u8,
2003     arg2: &VectorSize,
2004 ) -> Option<Reg> {
2005     let pattern0_0 = arg0;
2006     let pattern1_0 = arg1;
2007     let pattern2_0 = arg2;
2008     // Rule at src/isa/aarch64/inst.isle line 1555.
2009     let expr0_0: Type = I64;
2010     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2011     let expr2_0 = MInst::MovFromVec {
2012         rd: expr1_0,
2013         rn: pattern0_0,
2014         idx: pattern1_0,
2015         size: pattern2_0.clone(),
2016     };
2017     let expr3_0 = C::emit(ctx, &expr2_0);
2018     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2019     return Some(expr4_0);
2020 }
2021 
2022 // Generated as internal constructor for term mov_from_vec_signed.
2023 pub fn constructor_mov_from_vec_signed<C: Context>(
2024     ctx: &mut C,
2025     arg0: Reg,
2026     arg1: u8,
2027     arg2: &VectorSize,
2028     arg3: &OperandSize,
2029 ) -> Option<Reg> {
2030     let pattern0_0 = arg0;
2031     let pattern1_0 = arg1;
2032     let pattern2_0 = arg2;
2033     let pattern3_0 = arg3;
2034     // Rule at src/isa/aarch64/inst.isle line 1562.
2035     let expr0_0: Type = I64;
2036     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2037     let expr2_0 = MInst::MovFromVecSigned {
2038         rd: expr1_0,
2039         rn: pattern0_0,
2040         idx: pattern1_0,
2041         size: pattern2_0.clone(),
2042         scalar_size: pattern3_0.clone(),
2043     };
2044     let expr3_0 = C::emit(ctx, &expr2_0);
2045     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2046     return Some(expr4_0);
2047 }
2048 
2049 // Generated as internal constructor for term extend.
2050 pub fn constructor_extend<C: Context>(
2051     ctx: &mut C,
2052     arg0: Reg,
2053     arg1: bool,
2054     arg2: u8,
2055     arg3: u8,
2056 ) -> Option<Reg> {
2057     let pattern0_0 = arg0;
2058     let pattern1_0 = arg1;
2059     let pattern2_0 = arg2;
2060     let pattern3_0 = arg3;
2061     // Rule at src/isa/aarch64/inst.isle line 1569.
2062     let expr0_0: Type = I64;
2063     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2064     let expr2_0 = MInst::Extend {
2065         rd: expr1_0,
2066         rn: pattern0_0,
2067         signed: pattern1_0,
2068         from_bits: pattern2_0,
2069         to_bits: pattern3_0,
2070     };
2071     let expr3_0 = C::emit(ctx, &expr2_0);
2072     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2073     return Some(expr4_0);
2074 }
2075 
2076 // Generated as internal constructor for term load_acquire.
2077 pub fn constructor_load_acquire<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2078     let pattern0_0 = arg0;
2079     let pattern1_0 = arg1;
2080     // Rule at src/isa/aarch64/inst.isle line 1576.
2081     let expr0_0: Type = I64;
2082     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2083     let expr2_0 = MInst::LoadAcquire {
2084         access_ty: pattern0_0,
2085         rt: expr1_0,
2086         rn: pattern1_0,
2087     };
2088     let expr3_0 = C::emit(ctx, &expr2_0);
2089     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2090     return Some(expr4_0);
2091 }
2092 
2093 // Generated as internal constructor for term tst_imm.
2094 pub fn constructor_tst_imm<C: Context>(
2095     ctx: &mut C,
2096     arg0: Type,
2097     arg1: Reg,
2098     arg2: ImmLogic,
2099 ) -> Option<ProducesFlags> {
2100     let pattern0_0 = arg0;
2101     let pattern1_0 = arg1;
2102     let pattern2_0 = arg2;
2103     // Rule at src/isa/aarch64/inst.isle line 1586.
2104     let expr0_0 = ALUOp::AndS;
2105     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
2106     let expr2_0 = C::writable_zero_reg(ctx);
2107     let expr3_0 = MInst::AluRRImmLogic {
2108         alu_op: expr0_0,
2109         size: expr1_0,
2110         rd: expr2_0,
2111         rn: pattern1_0,
2112         imml: pattern2_0,
2113     };
2114     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
2115     return Some(expr4_0);
2116 }
2117 
2118 // Generated as internal constructor for term csel.
2119 pub fn constructor_csel<C: Context>(
2120     ctx: &mut C,
2121     arg0: &Cond,
2122     arg1: Reg,
2123     arg2: Reg,
2124 ) -> Option<ConsumesFlags> {
2125     let pattern0_0 = arg0;
2126     let pattern1_0 = arg1;
2127     let pattern2_0 = arg2;
2128     // Rule at src/isa/aarch64/inst.isle line 1600.
2129     let expr0_0: Type = I64;
2130     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2131     let expr2_0 = MInst::CSel {
2132         rd: expr1_0,
2133         cond: pattern0_0.clone(),
2134         rn: pattern1_0,
2135         rm: pattern2_0,
2136     };
2137     let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
2138     let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
2139         inst: expr2_0,
2140         result: expr3_0,
2141     };
2142     return Some(expr4_0);
2143 }
2144 
2145 // Generated as internal constructor for term add.
2146 pub fn constructor_add<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2147     let pattern0_0 = arg0;
2148     let pattern1_0 = arg1;
2149     let pattern2_0 = arg2;
2150     // Rule at src/isa/aarch64/inst.isle line 1609.
2151     let expr0_0 = ALUOp::Add;
2152     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2153     return Some(expr1_0);
2154 }
2155 
2156 // Generated as internal constructor for term add_imm.
2157 pub fn constructor_add_imm<C: Context>(
2158     ctx: &mut C,
2159     arg0: Type,
2160     arg1: Reg,
2161     arg2: Imm12,
2162 ) -> Option<Reg> {
2163     let pattern0_0 = arg0;
2164     let pattern1_0 = arg1;
2165     let pattern2_0 = arg2;
2166     // Rule at src/isa/aarch64/inst.isle line 1612.
2167     let expr0_0 = ALUOp::Add;
2168     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2169     return Some(expr1_0);
2170 }
2171 
2172 // Generated as internal constructor for term add_extend.
2173 pub fn constructor_add_extend<C: Context>(
2174     ctx: &mut C,
2175     arg0: Type,
2176     arg1: Reg,
2177     arg2: &ExtendedValue,
2178 ) -> Option<Reg> {
2179     let pattern0_0 = arg0;
2180     let pattern1_0 = arg1;
2181     let pattern2_0 = arg2;
2182     // Rule at src/isa/aarch64/inst.isle line 1615.
2183     let expr0_0 = ALUOp::Add;
2184     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2185     return Some(expr1_0);
2186 }
2187 
2188 // Generated as internal constructor for term add_shift.
2189 pub fn constructor_add_shift<C: Context>(
2190     ctx: &mut C,
2191     arg0: Type,
2192     arg1: Reg,
2193     arg2: Reg,
2194     arg3: ShiftOpAndAmt,
2195 ) -> Option<Reg> {
2196     let pattern0_0 = arg0;
2197     let pattern1_0 = arg1;
2198     let pattern2_0 = arg2;
2199     let pattern3_0 = arg3;
2200     // Rule at src/isa/aarch64/inst.isle line 1618.
2201     let expr0_0 = ALUOp::Add;
2202     let expr1_0 = constructor_alu_rrr_shift(
2203         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2204     )?;
2205     return Some(expr1_0);
2206 }
2207 
2208 // Generated as internal constructor for term add_vec.
2209 pub fn constructor_add_vec<C: Context>(
2210     ctx: &mut C,
2211     arg0: Reg,
2212     arg1: Reg,
2213     arg2: &VectorSize,
2214 ) -> Option<Reg> {
2215     let pattern0_0 = arg0;
2216     let pattern1_0 = arg1;
2217     let pattern2_0 = arg2;
2218     // Rule at src/isa/aarch64/inst.isle line 1621.
2219     let expr0_0 = VecALUOp::Add;
2220     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2221     return Some(expr1_0);
2222 }
2223 
2224 // Generated as internal constructor for term sub.
2225 pub fn constructor_sub<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2226     let pattern0_0 = arg0;
2227     let pattern1_0 = arg1;
2228     let pattern2_0 = arg2;
2229     // Rule at src/isa/aarch64/inst.isle line 1626.
2230     let expr0_0 = ALUOp::Sub;
2231     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2232     return Some(expr1_0);
2233 }
2234 
2235 // Generated as internal constructor for term sub_imm.
2236 pub fn constructor_sub_imm<C: Context>(
2237     ctx: &mut C,
2238     arg0: Type,
2239     arg1: Reg,
2240     arg2: Imm12,
2241 ) -> Option<Reg> {
2242     let pattern0_0 = arg0;
2243     let pattern1_0 = arg1;
2244     let pattern2_0 = arg2;
2245     // Rule at src/isa/aarch64/inst.isle line 1629.
2246     let expr0_0 = ALUOp::Sub;
2247     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2248     return Some(expr1_0);
2249 }
2250 
2251 // Generated as internal constructor for term sub_extend.
2252 pub fn constructor_sub_extend<C: Context>(
2253     ctx: &mut C,
2254     arg0: Type,
2255     arg1: Reg,
2256     arg2: &ExtendedValue,
2257 ) -> Option<Reg> {
2258     let pattern0_0 = arg0;
2259     let pattern1_0 = arg1;
2260     let pattern2_0 = arg2;
2261     // Rule at src/isa/aarch64/inst.isle line 1632.
2262     let expr0_0 = ALUOp::Sub;
2263     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2264     return Some(expr1_0);
2265 }
2266 
2267 // Generated as internal constructor for term sub_shift.
2268 pub fn constructor_sub_shift<C: Context>(
2269     ctx: &mut C,
2270     arg0: Type,
2271     arg1: Reg,
2272     arg2: Reg,
2273     arg3: ShiftOpAndAmt,
2274 ) -> Option<Reg> {
2275     let pattern0_0 = arg0;
2276     let pattern1_0 = arg1;
2277     let pattern2_0 = arg2;
2278     let pattern3_0 = arg3;
2279     // Rule at src/isa/aarch64/inst.isle line 1635.
2280     let expr0_0 = ALUOp::Sub;
2281     let expr1_0 = constructor_alu_rrr_shift(
2282         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2283     )?;
2284     return Some(expr1_0);
2285 }
2286 
2287 // Generated as internal constructor for term sub_vec.
2288 pub fn constructor_sub_vec<C: Context>(
2289     ctx: &mut C,
2290     arg0: Reg,
2291     arg1: Reg,
2292     arg2: &VectorSize,
2293 ) -> Option<Reg> {
2294     let pattern0_0 = arg0;
2295     let pattern1_0 = arg1;
2296     let pattern2_0 = arg2;
2297     // Rule at src/isa/aarch64/inst.isle line 1638.
2298     let expr0_0 = VecALUOp::Sub;
2299     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2300     return Some(expr1_0);
2301 }
2302 
2303 // Generated as internal constructor for term madd.
2304 pub fn constructor_madd<C: Context>(
2305     ctx: &mut C,
2306     arg0: Type,
2307     arg1: Reg,
2308     arg2: Reg,
2309     arg3: Reg,
2310 ) -> Option<Reg> {
2311     let pattern0_0 = arg0;
2312     let pattern1_0 = arg1;
2313     let pattern2_0 = arg2;
2314     let pattern3_0 = arg3;
2315     // Rule at src/isa/aarch64/inst.isle line 1643.
2316     let expr0_0 = ALUOp3::MAdd;
2317     let expr1_0 = constructor_alu_rrrr(
2318         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2319     )?;
2320     return Some(expr1_0);
2321 }
2322 
2323 // Generated as internal constructor for term msub.
2324 pub fn constructor_msub<C: Context>(
2325     ctx: &mut C,
2326     arg0: Type,
2327     arg1: Reg,
2328     arg2: Reg,
2329     arg3: Reg,
2330 ) -> Option<Reg> {
2331     let pattern0_0 = arg0;
2332     let pattern1_0 = arg1;
2333     let pattern2_0 = arg2;
2334     let pattern3_0 = arg3;
2335     // Rule at src/isa/aarch64/inst.isle line 1648.
2336     let expr0_0 = ALUOp3::MSub;
2337     let expr1_0 = constructor_alu_rrrr(
2338         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2339     )?;
2340     return Some(expr1_0);
2341 }
2342 
2343 // Generated as internal constructor for term uqadd.
2344 pub fn constructor_uqadd<C: Context>(
2345     ctx: &mut C,
2346     arg0: Reg,
2347     arg1: Reg,
2348     arg2: &VectorSize,
2349 ) -> Option<Reg> {
2350     let pattern0_0 = arg0;
2351     let pattern1_0 = arg1;
2352     let pattern2_0 = arg2;
2353     // Rule at src/isa/aarch64/inst.isle line 1652.
2354     let expr0_0 = VecALUOp::Uqadd;
2355     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2356     return Some(expr1_0);
2357 }
2358 
2359 // Generated as internal constructor for term sqadd.
2360 pub fn constructor_sqadd<C: Context>(
2361     ctx: &mut C,
2362     arg0: Reg,
2363     arg1: Reg,
2364     arg2: &VectorSize,
2365 ) -> Option<Reg> {
2366     let pattern0_0 = arg0;
2367     let pattern1_0 = arg1;
2368     let pattern2_0 = arg2;
2369     // Rule at src/isa/aarch64/inst.isle line 1656.
2370     let expr0_0 = VecALUOp::Sqadd;
2371     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2372     return Some(expr1_0);
2373 }
2374 
2375 // Generated as internal constructor for term uqsub.
2376 pub fn constructor_uqsub<C: Context>(
2377     ctx: &mut C,
2378     arg0: Reg,
2379     arg1: Reg,
2380     arg2: &VectorSize,
2381 ) -> Option<Reg> {
2382     let pattern0_0 = arg0;
2383     let pattern1_0 = arg1;
2384     let pattern2_0 = arg2;
2385     // Rule at src/isa/aarch64/inst.isle line 1660.
2386     let expr0_0 = VecALUOp::Uqsub;
2387     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2388     return Some(expr1_0);
2389 }
2390 
2391 // Generated as internal constructor for term sqsub.
2392 pub fn constructor_sqsub<C: Context>(
2393     ctx: &mut C,
2394     arg0: Reg,
2395     arg1: Reg,
2396     arg2: &VectorSize,
2397 ) -> Option<Reg> {
2398     let pattern0_0 = arg0;
2399     let pattern1_0 = arg1;
2400     let pattern2_0 = arg2;
2401     // Rule at src/isa/aarch64/inst.isle line 1664.
2402     let expr0_0 = VecALUOp::Sqsub;
2403     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2404     return Some(expr1_0);
2405 }
2406 
2407 // Generated as internal constructor for term umulh.
2408 pub fn constructor_umulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2409     let pattern0_0 = arg0;
2410     let pattern1_0 = arg1;
2411     let pattern2_0 = arg2;
2412     // Rule at src/isa/aarch64/inst.isle line 1668.
2413     let expr0_0 = ALUOp::UMulH;
2414     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2415     return Some(expr1_0);
2416 }
2417 
2418 // Generated as internal constructor for term smulh.
2419 pub fn constructor_smulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2420     let pattern0_0 = arg0;
2421     let pattern1_0 = arg1;
2422     let pattern2_0 = arg2;
2423     // Rule at src/isa/aarch64/inst.isle line 1672.
2424     let expr0_0 = ALUOp::SMulH;
2425     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2426     return Some(expr1_0);
2427 }
2428 
2429 // Generated as internal constructor for term mul.
2430 pub fn constructor_mul<C: Context>(
2431     ctx: &mut C,
2432     arg0: Reg,
2433     arg1: Reg,
2434     arg2: &VectorSize,
2435 ) -> Option<Reg> {
2436     let pattern0_0 = arg0;
2437     let pattern1_0 = arg1;
2438     let pattern2_0 = arg2;
2439     // Rule at src/isa/aarch64/inst.isle line 1676.
2440     let expr0_0 = VecALUOp::Mul;
2441     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2442     return Some(expr1_0);
2443 }
2444 
2445 // Generated as internal constructor for term neg.
2446 pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2447     let pattern0_0 = arg0;
2448     let pattern1_0 = arg1;
2449     // Rule at src/isa/aarch64/inst.isle line 1680.
2450     let expr0_0 = VecMisc2::Neg;
2451     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2452     return Some(expr1_0);
2453 }
2454 
2455 // Generated as internal constructor for term rev64.
2456 pub fn constructor_rev64<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2457     let pattern0_0 = arg0;
2458     let pattern1_0 = arg1;
2459     // Rule at src/isa/aarch64/inst.isle line 1684.
2460     let expr0_0 = VecMisc2::Rev64;
2461     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2462     return Some(expr1_0);
2463 }
2464 
2465 // Generated as internal constructor for term xtn64.
2466 pub fn constructor_xtn64<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2467     let pattern0_0 = arg0;
2468     let pattern1_0 = arg1;
2469     // Rule at src/isa/aarch64/inst.isle line 1688.
2470     let expr0_0 = VecRRNarrowOp::Xtn64;
2471     let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2472     return Some(expr1_0);
2473 }
2474 
2475 // Generated as internal constructor for term addp.
2476 pub fn constructor_addp<C: Context>(
2477     ctx: &mut C,
2478     arg0: Reg,
2479     arg1: Reg,
2480     arg2: &VectorSize,
2481 ) -> Option<Reg> {
2482     let pattern0_0 = arg0;
2483     let pattern1_0 = arg1;
2484     let pattern2_0 = arg2;
2485     // Rule at src/isa/aarch64/inst.isle line 1692.
2486     let expr0_0 = VecALUOp::Addp;
2487     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2488     return Some(expr1_0);
2489 }
2490 
2491 // Generated as internal constructor for term addv.
2492 pub fn constructor_addv<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2493     let pattern0_0 = arg0;
2494     let pattern1_0 = arg1;
2495     // Rule at src/isa/aarch64/inst.isle line 1696.
2496     let expr0_0 = VecLanesOp::Addv;
2497     let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2498     return Some(expr1_0);
2499 }
2500 
2501 // Generated as internal constructor for term shll32.
2502 pub fn constructor_shll32<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2503     let pattern0_0 = arg0;
2504     let pattern1_0 = arg1;
2505     // Rule at src/isa/aarch64/inst.isle line 1700.
2506     let expr0_0 = VecRRLongOp::Shll32;
2507     let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2508     return Some(expr1_0);
2509 }
2510 
2511 // Generated as internal constructor for term umlal32.
2512 pub fn constructor_umlal32<C: Context>(
2513     ctx: &mut C,
2514     arg0: Reg,
2515     arg1: Reg,
2516     arg2: Reg,
2517     arg3: bool,
2518 ) -> Option<Reg> {
2519     let pattern0_0 = arg0;
2520     let pattern1_0 = arg1;
2521     let pattern2_0 = arg2;
2522     let pattern3_0 = arg3;
2523     // Rule at src/isa/aarch64/inst.isle line 1704.
2524     let expr0_0 = VecRRRLongOp::Umlal32;
2525     let expr1_0 = constructor_vec_rrrr_long(
2526         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2527     )?;
2528     return Some(expr1_0);
2529 }
2530 
2531 // Generated as internal constructor for term smull8.
2532 pub fn constructor_smull8<C: Context>(
2533     ctx: &mut C,
2534     arg0: Reg,
2535     arg1: Reg,
2536     arg2: bool,
2537 ) -> Option<Reg> {
2538     let pattern0_0 = arg0;
2539     let pattern1_0 = arg1;
2540     let pattern2_0 = arg2;
2541     // Rule at src/isa/aarch64/inst.isle line 1708.
2542     let expr0_0 = VecRRRLongOp::Smull8;
2543     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2544     return Some(expr1_0);
2545 }
2546 
2547 // Generated as internal constructor for term umull8.
2548 pub fn constructor_umull8<C: Context>(
2549     ctx: &mut C,
2550     arg0: Reg,
2551     arg1: Reg,
2552     arg2: bool,
2553 ) -> Option<Reg> {
2554     let pattern0_0 = arg0;
2555     let pattern1_0 = arg1;
2556     let pattern2_0 = arg2;
2557     // Rule at src/isa/aarch64/inst.isle line 1712.
2558     let expr0_0 = VecRRRLongOp::Umull8;
2559     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2560     return Some(expr1_0);
2561 }
2562 
2563 // Generated as internal constructor for term smull16.
2564 pub fn constructor_smull16<C: Context>(
2565     ctx: &mut C,
2566     arg0: Reg,
2567     arg1: Reg,
2568     arg2: bool,
2569 ) -> Option<Reg> {
2570     let pattern0_0 = arg0;
2571     let pattern1_0 = arg1;
2572     let pattern2_0 = arg2;
2573     // Rule at src/isa/aarch64/inst.isle line 1716.
2574     let expr0_0 = VecRRRLongOp::Smull16;
2575     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2576     return Some(expr1_0);
2577 }
2578 
2579 // Generated as internal constructor for term umull16.
2580 pub fn constructor_umull16<C: Context>(
2581     ctx: &mut C,
2582     arg0: Reg,
2583     arg1: Reg,
2584     arg2: bool,
2585 ) -> Option<Reg> {
2586     let pattern0_0 = arg0;
2587     let pattern1_0 = arg1;
2588     let pattern2_0 = arg2;
2589     // Rule at src/isa/aarch64/inst.isle line 1720.
2590     let expr0_0 = VecRRRLongOp::Umull16;
2591     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2592     return Some(expr1_0);
2593 }
2594 
2595 // Generated as internal constructor for term smull32.
2596 pub fn constructor_smull32<C: Context>(
2597     ctx: &mut C,
2598     arg0: Reg,
2599     arg1: Reg,
2600     arg2: bool,
2601 ) -> Option<Reg> {
2602     let pattern0_0 = arg0;
2603     let pattern1_0 = arg1;
2604     let pattern2_0 = arg2;
2605     // Rule at src/isa/aarch64/inst.isle line 1724.
2606     let expr0_0 = VecRRRLongOp::Smull32;
2607     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2608     return Some(expr1_0);
2609 }
2610 
2611 // Generated as internal constructor for term umull32.
2612 pub fn constructor_umull32<C: Context>(
2613     ctx: &mut C,
2614     arg0: Reg,
2615     arg1: Reg,
2616     arg2: bool,
2617 ) -> Option<Reg> {
2618     let pattern0_0 = arg0;
2619     let pattern1_0 = arg1;
2620     let pattern2_0 = arg2;
2621     // Rule at src/isa/aarch64/inst.isle line 1728.
2622     let expr0_0 = VecRRRLongOp::Umull32;
2623     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2624     return Some(expr1_0);
2625 }
2626 
2627 // Generated as internal constructor for term asr.
2628 pub fn constructor_asr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2629     let pattern0_0 = arg0;
2630     let pattern1_0 = arg1;
2631     let pattern2_0 = arg2;
2632     // Rule at src/isa/aarch64/inst.isle line 1732.
2633     let expr0_0 = ALUOp::Asr;
2634     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2635     return Some(expr1_0);
2636 }
2637 
2638 // Generated as internal constructor for term asr_imm.
2639 pub fn constructor_asr_imm<C: Context>(
2640     ctx: &mut C,
2641     arg0: Type,
2642     arg1: Reg,
2643     arg2: ImmShift,
2644 ) -> Option<Reg> {
2645     let pattern0_0 = arg0;
2646     let pattern1_0 = arg1;
2647     let pattern2_0 = arg2;
2648     // Rule at src/isa/aarch64/inst.isle line 1735.
2649     let expr0_0 = ALUOp::Asr;
2650     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2651     return Some(expr1_0);
2652 }
2653 
2654 // Generated as internal constructor for term lsr.
2655 pub fn constructor_lsr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2656     let pattern0_0 = arg0;
2657     let pattern1_0 = arg1;
2658     let pattern2_0 = arg2;
2659     // Rule at src/isa/aarch64/inst.isle line 1739.
2660     let expr0_0 = ALUOp::Lsr;
2661     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2662     return Some(expr1_0);
2663 }
2664 
2665 // Generated as internal constructor for term lsr_imm.
2666 pub fn constructor_lsr_imm<C: Context>(
2667     ctx: &mut C,
2668     arg0: Type,
2669     arg1: Reg,
2670     arg2: ImmShift,
2671 ) -> Option<Reg> {
2672     let pattern0_0 = arg0;
2673     let pattern1_0 = arg1;
2674     let pattern2_0 = arg2;
2675     // Rule at src/isa/aarch64/inst.isle line 1742.
2676     let expr0_0 = ALUOp::Lsr;
2677     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2678     return Some(expr1_0);
2679 }
2680 
2681 // Generated as internal constructor for term lsl.
2682 pub fn constructor_lsl<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2683     let pattern0_0 = arg0;
2684     let pattern1_0 = arg1;
2685     let pattern2_0 = arg2;
2686     // Rule at src/isa/aarch64/inst.isle line 1746.
2687     let expr0_0 = ALUOp::Lsl;
2688     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2689     return Some(expr1_0);
2690 }
2691 
2692 // Generated as internal constructor for term lsl_imm.
2693 pub fn constructor_lsl_imm<C: Context>(
2694     ctx: &mut C,
2695     arg0: Type,
2696     arg1: Reg,
2697     arg2: ImmShift,
2698 ) -> Option<Reg> {
2699     let pattern0_0 = arg0;
2700     let pattern1_0 = arg1;
2701     let pattern2_0 = arg2;
2702     // Rule at src/isa/aarch64/inst.isle line 1749.
2703     let expr0_0 = ALUOp::Lsl;
2704     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2705     return Some(expr1_0);
2706 }
2707 
2708 // Generated as internal constructor for term a64_udiv.
2709 pub fn constructor_a64_udiv<C: Context>(
2710     ctx: &mut C,
2711     arg0: Type,
2712     arg1: Reg,
2713     arg2: Reg,
2714 ) -> Option<Reg> {
2715     let pattern0_0 = arg0;
2716     let pattern1_0 = arg1;
2717     let pattern2_0 = arg2;
2718     // Rule at src/isa/aarch64/inst.isle line 1753.
2719     let expr0_0 = ALUOp::UDiv;
2720     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2721     return Some(expr1_0);
2722 }
2723 
2724 // Generated as internal constructor for term a64_sdiv.
2725 pub fn constructor_a64_sdiv<C: Context>(
2726     ctx: &mut C,
2727     arg0: Type,
2728     arg1: Reg,
2729     arg2: Reg,
2730 ) -> Option<Reg> {
2731     let pattern0_0 = arg0;
2732     let pattern1_0 = arg1;
2733     let pattern2_0 = arg2;
2734     // Rule at src/isa/aarch64/inst.isle line 1757.
2735     let expr0_0 = ALUOp::SDiv;
2736     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2737     return Some(expr1_0);
2738 }
2739 
2740 // Generated as internal constructor for term not.
2741 pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2742     let pattern0_0 = arg0;
2743     let pattern1_0 = arg1;
2744     // Rule at src/isa/aarch64/inst.isle line 1761.
2745     let expr0_0 = VecMisc2::Not;
2746     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2747     return Some(expr1_0);
2748 }
2749 
2750 // Generated as internal constructor for term orr_not.
2751 pub fn constructor_orr_not<C: Context>(
2752     ctx: &mut C,
2753     arg0: Type,
2754     arg1: Reg,
2755     arg2: Reg,
2756 ) -> Option<Reg> {
2757     let pattern0_0 = arg0;
2758     let pattern1_0 = arg1;
2759     let pattern2_0 = arg2;
2760     // Rule at src/isa/aarch64/inst.isle line 1766.
2761     let expr0_0 = ALUOp::OrrNot;
2762     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2763     return Some(expr1_0);
2764 }
2765 
2766 // Generated as internal constructor for term orr_not_shift.
2767 pub fn constructor_orr_not_shift<C: Context>(
2768     ctx: &mut C,
2769     arg0: Type,
2770     arg1: Reg,
2771     arg2: Reg,
2772     arg3: ShiftOpAndAmt,
2773 ) -> Option<Reg> {
2774     let pattern0_0 = arg0;
2775     let pattern1_0 = arg1;
2776     let pattern2_0 = arg2;
2777     let pattern3_0 = arg3;
2778     // Rule at src/isa/aarch64/inst.isle line 1769.
2779     let expr0_0 = ALUOp::OrrNot;
2780     let expr1_0 = constructor_alu_rrr_shift(
2781         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2782     )?;
2783     return Some(expr1_0);
2784 }
2785 
2786 // Generated as internal constructor for term orr.
2787 pub fn constructor_orr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2788     let pattern0_0 = arg0;
2789     let pattern1_0 = arg1;
2790     let pattern2_0 = arg2;
2791     // Rule at src/isa/aarch64/inst.isle line 1774.
2792     let expr0_0 = ALUOp::Orr;
2793     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2794     return Some(expr1_0);
2795 }
2796 
2797 // Generated as internal constructor for term orr_imm.
2798 pub fn constructor_orr_imm<C: Context>(
2799     ctx: &mut C,
2800     arg0: Type,
2801     arg1: Reg,
2802     arg2: ImmLogic,
2803 ) -> Option<Reg> {
2804     let pattern0_0 = arg0;
2805     let pattern1_0 = arg1;
2806     let pattern2_0 = arg2;
2807     // Rule at src/isa/aarch64/inst.isle line 1777.
2808     let expr0_0 = ALUOp::Orr;
2809     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2810     return Some(expr1_0);
2811 }
2812 
2813 // Generated as internal constructor for term orr_vec.
2814 pub fn constructor_orr_vec<C: Context>(
2815     ctx: &mut C,
2816     arg0: Reg,
2817     arg1: Reg,
2818     arg2: &VectorSize,
2819 ) -> Option<Reg> {
2820     let pattern0_0 = arg0;
2821     let pattern1_0 = arg1;
2822     let pattern2_0 = arg2;
2823     // Rule at src/isa/aarch64/inst.isle line 1780.
2824     let expr0_0 = VecALUOp::Orr;
2825     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2826     return Some(expr1_0);
2827 }
2828 
2829 // Generated as internal constructor for term and_imm.
2830 pub fn constructor_and_imm<C: Context>(
2831     ctx: &mut C,
2832     arg0: Type,
2833     arg1: Reg,
2834     arg2: ImmLogic,
2835 ) -> Option<Reg> {
2836     let pattern0_0 = arg0;
2837     let pattern1_0 = arg1;
2838     let pattern2_0 = arg2;
2839     // Rule at src/isa/aarch64/inst.isle line 1785.
2840     let expr0_0 = ALUOp::And;
2841     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2842     return Some(expr1_0);
2843 }
2844 
2845 // Generated as internal constructor for term and_vec.
2846 pub fn constructor_and_vec<C: Context>(
2847     ctx: &mut C,
2848     arg0: Reg,
2849     arg1: Reg,
2850     arg2: &VectorSize,
2851 ) -> Option<Reg> {
2852     let pattern0_0 = arg0;
2853     let pattern1_0 = arg1;
2854     let pattern2_0 = arg2;
2855     // Rule at src/isa/aarch64/inst.isle line 1788.
2856     let expr0_0 = VecALUOp::And;
2857     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2858     return Some(expr1_0);
2859 }
2860 
2861 // Generated as internal constructor for term eor_vec.
2862 pub fn constructor_eor_vec<C: Context>(
2863     ctx: &mut C,
2864     arg0: Reg,
2865     arg1: Reg,
2866     arg2: &VectorSize,
2867 ) -> Option<Reg> {
2868     let pattern0_0 = arg0;
2869     let pattern1_0 = arg1;
2870     let pattern2_0 = arg2;
2871     // Rule at src/isa/aarch64/inst.isle line 1792.
2872     let expr0_0 = VecALUOp::Eor;
2873     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2874     return Some(expr1_0);
2875 }
2876 
2877 // Generated as internal constructor for term bic_vec.
2878 pub fn constructor_bic_vec<C: Context>(
2879     ctx: &mut C,
2880     arg0: Reg,
2881     arg1: Reg,
2882     arg2: &VectorSize,
2883 ) -> Option<Reg> {
2884     let pattern0_0 = arg0;
2885     let pattern1_0 = arg1;
2886     let pattern2_0 = arg2;
2887     // Rule at src/isa/aarch64/inst.isle line 1796.
2888     let expr0_0 = VecALUOp::Bic;
2889     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2890     return Some(expr1_0);
2891 }
2892 
2893 // Generated as internal constructor for term sshl.
2894 pub fn constructor_sshl<C: Context>(
2895     ctx: &mut C,
2896     arg0: Reg,
2897     arg1: Reg,
2898     arg2: &VectorSize,
2899 ) -> Option<Reg> {
2900     let pattern0_0 = arg0;
2901     let pattern1_0 = arg1;
2902     let pattern2_0 = arg2;
2903     // Rule at src/isa/aarch64/inst.isle line 1800.
2904     let expr0_0 = VecALUOp::Sshl;
2905     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2906     return Some(expr1_0);
2907 }
2908 
2909 // Generated as internal constructor for term ushl.
2910 pub fn constructor_ushl<C: Context>(
2911     ctx: &mut C,
2912     arg0: Reg,
2913     arg1: Reg,
2914     arg2: &VectorSize,
2915 ) -> Option<Reg> {
2916     let pattern0_0 = arg0;
2917     let pattern1_0 = arg1;
2918     let pattern2_0 = arg2;
2919     // Rule at src/isa/aarch64/inst.isle line 1804.
2920     let expr0_0 = VecALUOp::Ushl;
2921     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2922     return Some(expr1_0);
2923 }
2924 
2925 // Generated as internal constructor for term a64_rotr.
2926 pub fn constructor_a64_rotr<C: Context>(
2927     ctx: &mut C,
2928     arg0: Type,
2929     arg1: Reg,
2930     arg2: Reg,
2931 ) -> Option<Reg> {
2932     let pattern0_0 = arg0;
2933     let pattern1_0 = arg1;
2934     let pattern2_0 = arg2;
2935     // Rule at src/isa/aarch64/inst.isle line 1809.
2936     let expr0_0 = ALUOp::RotR;
2937     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2938     return Some(expr1_0);
2939 }
2940 
2941 // Generated as internal constructor for term a64_rotr_imm.
2942 pub fn constructor_a64_rotr_imm<C: Context>(
2943     ctx: &mut C,
2944     arg0: Type,
2945     arg1: Reg,
2946     arg2: ImmShift,
2947 ) -> Option<Reg> {
2948     let pattern0_0 = arg0;
2949     let pattern1_0 = arg1;
2950     let pattern2_0 = arg2;
2951     // Rule at src/isa/aarch64/inst.isle line 1812.
2952     let expr0_0 = ALUOp::RotR;
2953     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2954     return Some(expr1_0);
2955 }
2956 
2957 // Generated as internal constructor for term rbit.
2958 pub fn constructor_rbit<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2959     let pattern0_0 = arg0;
2960     let pattern1_0 = arg1;
2961     // Rule at src/isa/aarch64/inst.isle line 1817.
2962     let expr0_0 = BitOp::RBit;
2963     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2964     return Some(expr1_0);
2965 }
2966 
2967 // Generated as internal constructor for term a64_clz.
2968 pub fn constructor_a64_clz<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2969     let pattern0_0 = arg0;
2970     let pattern1_0 = arg1;
2971     // Rule at src/isa/aarch64/inst.isle line 1822.
2972     let expr0_0 = BitOp::Clz;
2973     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2974     return Some(expr1_0);
2975 }
2976 
2977 // Generated as internal constructor for term a64_cls.
2978 pub fn constructor_a64_cls<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2979     let pattern0_0 = arg0;
2980     let pattern1_0 = arg1;
2981     // Rule at src/isa/aarch64/inst.isle line 1827.
2982     let expr0_0 = BitOp::Cls;
2983     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2984     return Some(expr1_0);
2985 }
2986 
2987 // Generated as internal constructor for term eon.
2988 pub fn constructor_eon<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2989     let pattern0_0 = arg0;
2990     let pattern1_0 = arg1;
2991     let pattern2_0 = arg2;
2992     // Rule at src/isa/aarch64/inst.isle line 1832.
2993     let expr0_0 = ALUOp::EorNot;
2994     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2995     return Some(expr1_0);
2996 }
2997 
2998 // Generated as internal constructor for term vec_cnt.
2999 pub fn constructor_vec_cnt<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3000     let pattern0_0 = arg0;
3001     let pattern1_0 = arg1;
3002     // Rule at src/isa/aarch64/inst.isle line 1837.
3003     let expr0_0 = VecMisc2::Cnt;
3004     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3005     return Some(expr1_0);
3006 }
3007 
3008 // Generated as internal constructor for term imm.
3009 pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
3010     let pattern0_0 = arg0;
3011     if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) {
3012         let pattern2_0 = arg1;
3013         let closure3 = || {
3014             let expr0_0: Type = I64;
3015             return Some(expr0_0);
3016         };
3017         if let Some(pattern3_0) = closure3() {
3018             if let Some(pattern4_0) = C::imm_logic_from_u64(ctx, pattern2_0, pattern3_0) {
3019                 // Rule at src/isa/aarch64/inst.isle line 1852.
3020                 let expr0_0: Type = I64;
3021                 let expr1_0 = C::zero_reg(ctx);
3022                 let expr2_0 = constructor_orr_imm(ctx, expr0_0, expr1_0, pattern4_0)?;
3023                 return Some(expr2_0);
3024             }
3025         }
3026         if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) {
3027             // Rule at src/isa/aarch64/inst.isle line 1844.
3028             let expr0_0 = OperandSize::Size64;
3029             let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?;
3030             return Some(expr1_0);
3031         }
3032         if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) {
3033             // Rule at src/isa/aarch64/inst.isle line 1848.
3034             let expr0_0 = OperandSize::Size64;
3035             let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?;
3036             return Some(expr1_0);
3037         }
3038         // Rule at src/isa/aarch64/inst.isle line 1859.
3039         let expr0_0 = C::load_constant64_full(ctx, pattern2_0);
3040         return Some(expr0_0);
3041     }
3042     return None;
3043 }
3044 
3045 // Generated as internal constructor for term put_in_reg_sext32.
3046 pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3047     let pattern0_0 = arg0;
3048     let pattern1_0 = C::value_type(ctx, pattern0_0);
3049     if pattern1_0 == I32 {
3050         // Rule at src/isa/aarch64/inst.isle line 1870.
3051         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3052         return Some(expr0_0);
3053     }
3054     if pattern1_0 == I64 {
3055         // Rule at src/isa/aarch64/inst.isle line 1871.
3056         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3057         return Some(expr0_0);
3058     }
3059     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3060         // Rule at src/isa/aarch64/inst.isle line 1866.
3061         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3062         let expr1_0: bool = true;
3063         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3064         let expr3_0: u8 = 32;
3065         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3066         return Some(expr4_0);
3067     }
3068     return None;
3069 }
3070 
3071 // Generated as internal constructor for term put_in_reg_zext32.
3072 pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3073     let pattern0_0 = arg0;
3074     let pattern1_0 = C::value_type(ctx, pattern0_0);
3075     if pattern1_0 == I32 {
3076         // Rule at src/isa/aarch64/inst.isle line 1879.
3077         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3078         return Some(expr0_0);
3079     }
3080     if pattern1_0 == I64 {
3081         // Rule at src/isa/aarch64/inst.isle line 1880.
3082         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3083         return Some(expr0_0);
3084     }
3085     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3086         // Rule at src/isa/aarch64/inst.isle line 1875.
3087         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3088         let expr1_0: bool = false;
3089         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3090         let expr3_0: u8 = 32;
3091         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3092         return Some(expr4_0);
3093     }
3094     return None;
3095 }
3096 
3097 // Generated as internal constructor for term put_in_reg_sext64.
3098 pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3099     let pattern0_0 = arg0;
3100     let pattern1_0 = C::value_type(ctx, pattern0_0);
3101     if pattern1_0 == I64 {
3102         // Rule at src/isa/aarch64/inst.isle line 1888.
3103         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3104         return Some(expr0_0);
3105     }
3106     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3107         // Rule at src/isa/aarch64/inst.isle line 1884.
3108         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3109         let expr1_0: bool = true;
3110         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3111         let expr3_0: u8 = 64;
3112         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3113         return Some(expr4_0);
3114     }
3115     return None;
3116 }
3117 
3118 // Generated as internal constructor for term put_in_reg_zext64.
3119 pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3120     let pattern0_0 = arg0;
3121     let pattern1_0 = C::value_type(ctx, pattern0_0);
3122     if pattern1_0 == I64 {
3123         // Rule at src/isa/aarch64/inst.isle line 1896.
3124         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3125         return Some(expr0_0);
3126     }
3127     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3128         // Rule at src/isa/aarch64/inst.isle line 1892.
3129         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3130         let expr1_0: bool = false;
3131         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3132         let expr3_0: u8 = 64;
3133         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3134         return Some(expr4_0);
3135     }
3136     return None;
3137 }
3138 
3139 // Generated as internal constructor for term trap_if_zero_divisor.
3140 pub fn constructor_trap_if_zero_divisor<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3141     let pattern0_0 = arg0;
3142     // Rule at src/isa/aarch64/inst.isle line 1901.
3143     let expr0_0 = C::cond_br_zero(ctx, pattern0_0);
3144     let expr1_0 = C::trap_code_division_by_zero(ctx);
3145     let expr2_0 = MInst::TrapIf {
3146         kind: expr0_0,
3147         trap_code: expr1_0,
3148     };
3149     let expr3_0 = C::emit(ctx, &expr2_0);
3150     return Some(pattern0_0);
3151 }
3152 
3153 // Generated as internal constructor for term size_from_ty.
3154 pub fn constructor_size_from_ty<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
3155     let pattern0_0 = arg0;
3156     if pattern0_0 == I64 {
3157         // Rule at src/isa/aarch64/inst.isle line 1907.
3158         let expr0_0 = OperandSize::Size64;
3159         return Some(expr0_0);
3160     }
3161     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
3162         // Rule at src/isa/aarch64/inst.isle line 1906.
3163         let expr0_0 = OperandSize::Size32;
3164         return Some(expr0_0);
3165     }
3166     return None;
3167 }
3168 
3169 // Generated as internal constructor for term trap_if_div_overflow.
3170 pub fn constructor_trap_if_div_overflow<C: Context>(
3171     ctx: &mut C,
3172     arg0: Type,
3173     arg1: Reg,
3174     arg2: Reg,
3175 ) -> Option<Reg> {
3176     let pattern0_0 = arg0;
3177     let pattern1_0 = arg1;
3178     let pattern2_0 = arg2;
3179     // Rule at src/isa/aarch64/inst.isle line 1913.
3180     let expr0_0 = ALUOp::AddS;
3181     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
3182     let expr2_0 = C::writable_zero_reg(ctx);
3183     let expr3_0: u8 = 1;
3184     let expr4_0 = C::u8_into_imm12(ctx, expr3_0);
3185     let expr5_0 = MInst::AluRRImm12 {
3186         alu_op: expr0_0,
3187         size: expr1_0,
3188         rd: expr2_0,
3189         rn: pattern2_0,
3190         imm12: expr4_0,
3191     };
3192     let expr6_0 = C::emit(ctx, &expr5_0);
3193     let expr7_0 = constructor_size_from_ty(ctx, pattern0_0)?;
3194     let expr8_0: u8 = 1;
3195     let expr9_0 = C::u8_into_uimm5(ctx, expr8_0);
3196     let expr10_0: bool = false;
3197     let expr11_0: bool = false;
3198     let expr12_0: bool = false;
3199     let expr13_0: bool = false;
3200     let expr14_0 = C::nzcv(ctx, expr10_0, expr11_0, expr12_0, expr13_0);
3201     let expr15_0 = Cond::Eq;
3202     let expr16_0 = MInst::CCmpImm {
3203         size: expr7_0,
3204         rn: pattern1_0,
3205         imm: expr9_0,
3206         nzcv: expr14_0,
3207         cond: expr15_0,
3208     };
3209     let expr17_0 = C::emit(ctx, &expr16_0);
3210     let expr18_0 = Cond::Vs;
3211     let expr19_0 = C::cond_br_cond(ctx, &expr18_0);
3212     let expr20_0 = C::trap_code_integer_overflow(ctx);
3213     let expr21_0 = MInst::TrapIf {
3214         kind: expr19_0,
3215         trap_code: expr20_0,
3216     };
3217     let expr22_0 = C::emit(ctx, &expr21_0);
3218     return Some(pattern1_0);
3219 }
3220 
3221 // Generated as internal constructor for term alu_rs_imm_logic_commutative.
3222 pub fn constructor_alu_rs_imm_logic_commutative<C: Context>(
3223     ctx: &mut C,
3224     arg0: &ALUOp,
3225     arg1: Type,
3226     arg2: Value,
3227     arg3: Value,
3228 ) -> Option<Reg> {
3229     let pattern0_0 = arg0;
3230     let pattern1_0 = arg1;
3231     let pattern2_0 = arg2;
3232     if let Some(pattern3_0) = C::def_inst(ctx, pattern2_0) {
3233         let pattern4_0 = C::inst_data(ctx, pattern3_0);
3234         match &pattern4_0 {
3235             &InstructionData::UnaryImm {
3236                 opcode: ref pattern5_0,
3237                 imm: pattern5_1,
3238             } => {
3239                 if let &Opcode::Iconst = pattern5_0 {
3240                     let closure7 = || {
3241                         return Some(pattern1_0);
3242                     };
3243                     if let Some(pattern7_0) = closure7() {
3244                         if let Some(pattern8_0) =
3245                             C::imm_logic_from_imm64(ctx, pattern5_1, pattern7_0)
3246                         {
3247                             let pattern9_0 = arg3;
3248                             // Rule at src/isa/aarch64/inst.isle line 1958.
3249                             let expr0_0 = C::put_in_reg(ctx, pattern9_0);
3250                             let expr1_0 = constructor_alu_rr_imm_logic(
3251                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0,
3252                             )?;
3253                             return Some(expr1_0);
3254                         }
3255                     }
3256                 }
3257             }
3258             &InstructionData::Binary {
3259                 opcode: ref pattern5_0,
3260                 args: ref pattern5_1,
3261             } => {
3262                 if let &Opcode::Ishl = pattern5_0 {
3263                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3264                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3265                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
3266                         if let &InstructionData::UnaryImm {
3267                             opcode: ref pattern10_0,
3268                             imm: pattern10_1,
3269                         } = &pattern9_0
3270                         {
3271                             if let &Opcode::Iconst = pattern10_0 {
3272                                 let closure12 = || {
3273                                     return Some(pattern1_0);
3274                                 };
3275                                 if let Some(pattern12_0) = closure12() {
3276                                     if let Some(pattern13_0) =
3277                                         C::lshl_from_imm64(ctx, pattern10_1, pattern12_0)
3278                                     {
3279                                         let pattern14_0 = arg3;
3280                                         // Rule at src/isa/aarch64/inst.isle line 1964.
3281                                         let expr0_0 = C::put_in_reg(ctx, pattern14_0);
3282                                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3283                                         let expr2_0 = constructor_alu_rrr_shift(
3284                                             ctx,
3285                                             pattern0_0,
3286                                             pattern1_0,
3287                                             expr0_0,
3288                                             expr1_0,
3289                                             pattern13_0,
3290                                         )?;
3291                                         return Some(expr2_0);
3292                                     }
3293                                 }
3294                             }
3295                         }
3296                     }
3297                 }
3298             }
3299             _ => {}
3300         }
3301     }
3302     let pattern3_0 = arg3;
3303     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3304         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3305         match &pattern5_0 {
3306             &InstructionData::UnaryImm {
3307                 opcode: ref pattern6_0,
3308                 imm: pattern6_1,
3309             } => {
3310                 if let &Opcode::Iconst = pattern6_0 {
3311                     let closure8 = || {
3312                         return Some(pattern1_0);
3313                     };
3314                     if let Some(pattern8_0) = closure8() {
3315                         if let Some(pattern9_0) =
3316                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3317                         {
3318                             // Rule at src/isa/aarch64/inst.isle line 1956.
3319                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3320                             let expr1_0 = constructor_alu_rr_imm_logic(
3321                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3322                             )?;
3323                             return Some(expr1_0);
3324                         }
3325                     }
3326                 }
3327             }
3328             &InstructionData::Binary {
3329                 opcode: ref pattern6_0,
3330                 args: ref pattern6_1,
3331             } => {
3332                 if let &Opcode::Ishl = pattern6_0 {
3333                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3334                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3335                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3336                         if let &InstructionData::UnaryImm {
3337                             opcode: ref pattern11_0,
3338                             imm: pattern11_1,
3339                         } = &pattern10_0
3340                         {
3341                             if let &Opcode::Iconst = pattern11_0 {
3342                                 let closure13 = || {
3343                                     return Some(pattern1_0);
3344                                 };
3345                                 if let Some(pattern13_0) = closure13() {
3346                                     if let Some(pattern14_0) =
3347                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3348                                     {
3349                                         // Rule at src/isa/aarch64/inst.isle line 1962.
3350                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3351                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3352                                         let expr2_0 = constructor_alu_rrr_shift(
3353                                             ctx,
3354                                             pattern0_0,
3355                                             pattern1_0,
3356                                             expr0_0,
3357                                             expr1_0,
3358                                             pattern14_0,
3359                                         )?;
3360                                         return Some(expr2_0);
3361                                     }
3362                                 }
3363                             }
3364                         }
3365                     }
3366                 }
3367             }
3368             _ => {}
3369         }
3370     }
3371     // Rule at src/isa/aarch64/inst.isle line 1952.
3372     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3373     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3374     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3375     return Some(expr2_0);
3376 }
3377 
3378 // Generated as internal constructor for term alu_rs_imm_logic.
3379 pub fn constructor_alu_rs_imm_logic<C: Context>(
3380     ctx: &mut C,
3381     arg0: &ALUOp,
3382     arg1: Type,
3383     arg2: Value,
3384     arg3: Value,
3385 ) -> Option<Reg> {
3386     let pattern0_0 = arg0;
3387     let pattern1_0 = arg1;
3388     let pattern2_0 = arg2;
3389     let pattern3_0 = arg3;
3390     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3391         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3392         match &pattern5_0 {
3393             &InstructionData::UnaryImm {
3394                 opcode: ref pattern6_0,
3395                 imm: pattern6_1,
3396             } => {
3397                 if let &Opcode::Iconst = pattern6_0 {
3398                     let closure8 = || {
3399                         return Some(pattern1_0);
3400                     };
3401                     if let Some(pattern8_0) = closure8() {
3402                         if let Some(pattern9_0) =
3403                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3404                         {
3405                             // Rule at src/isa/aarch64/inst.isle line 1972.
3406                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3407                             let expr1_0 = constructor_alu_rr_imm_logic(
3408                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3409                             )?;
3410                             return Some(expr1_0);
3411                         }
3412                     }
3413                 }
3414             }
3415             &InstructionData::Binary {
3416                 opcode: ref pattern6_0,
3417                 args: ref pattern6_1,
3418             } => {
3419                 if let &Opcode::Ishl = pattern6_0 {
3420                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3421                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3422                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3423                         if let &InstructionData::UnaryImm {
3424                             opcode: ref pattern11_0,
3425                             imm: pattern11_1,
3426                         } = &pattern10_0
3427                         {
3428                             if let &Opcode::Iconst = pattern11_0 {
3429                                 let closure13 = || {
3430                                     return Some(pattern1_0);
3431                                 };
3432                                 if let Some(pattern13_0) = closure13() {
3433                                     if let Some(pattern14_0) =
3434                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3435                                     {
3436                                         // Rule at src/isa/aarch64/inst.isle line 1974.
3437                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3438                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3439                                         let expr2_0 = constructor_alu_rrr_shift(
3440                                             ctx,
3441                                             pattern0_0,
3442                                             pattern1_0,
3443                                             expr0_0,
3444                                             expr1_0,
3445                                             pattern14_0,
3446                                         )?;
3447                                         return Some(expr2_0);
3448                                     }
3449                                 }
3450                             }
3451                         }
3452                     }
3453                 }
3454             }
3455             _ => {}
3456         }
3457     }
3458     // Rule at src/isa/aarch64/inst.isle line 1970.
3459     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3460     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3461     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3462     return Some(expr2_0);
3463 }
3464 
3465 // Generated as internal constructor for term i128_alu_bitop.
3466 pub fn constructor_i128_alu_bitop<C: Context>(
3467     ctx: &mut C,
3468     arg0: &ALUOp,
3469     arg1: Type,
3470     arg2: Value,
3471     arg3: Value,
3472 ) -> Option<ValueRegs> {
3473     let pattern0_0 = arg0;
3474     let pattern1_0 = arg1;
3475     let pattern2_0 = arg2;
3476     let pattern3_0 = arg3;
3477     // Rule at src/isa/aarch64/inst.isle line 1982.
3478     let expr0_0 = C::put_in_regs(ctx, pattern2_0);
3479     let expr1_0: usize = 0;
3480     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3481     let expr3_0: usize = 1;
3482     let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
3483     let expr5_0 = C::put_in_regs(ctx, pattern3_0);
3484     let expr6_0: usize = 0;
3485     let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
3486     let expr8_0: usize = 1;
3487     let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
3488     let expr10_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr2_0, expr7_0)?;
3489     let expr11_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr4_0, expr9_0)?;
3490     let expr12_0 = C::value_regs(ctx, expr10_0, expr11_0);
3491     return Some(expr12_0);
3492 }
3493 
3494 // Generated as internal constructor for term float_cmp_zero.
3495 pub fn constructor_float_cmp_zero<C: Context>(
3496     ctx: &mut C,
3497     arg0: &FloatCC,
3498     arg1: Reg,
3499     arg2: &VectorSize,
3500 ) -> Option<Reg> {
3501     let pattern0_0 = arg0;
3502     let pattern1_0 = arg1;
3503     let pattern2_0 = arg2;
3504     // Rule at src/isa/aarch64/inst.isle line 2022.
3505     let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0);
3506     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3507     return Some(expr1_0);
3508 }
3509 
3510 // Generated as internal constructor for term float_cmp_zero_swap.
3511 pub fn constructor_float_cmp_zero_swap<C: Context>(
3512     ctx: &mut C,
3513     arg0: &FloatCC,
3514     arg1: Reg,
3515     arg2: &VectorSize,
3516 ) -> Option<Reg> {
3517     let pattern0_0 = arg0;
3518     let pattern1_0 = arg1;
3519     let pattern2_0 = arg2;
3520     // Rule at src/isa/aarch64/inst.isle line 2027.
3521     let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0);
3522     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3523     return Some(expr1_0);
3524 }
3525 
3526 // Generated as internal constructor for term fcmeq0.
3527 pub fn constructor_fcmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3528     let pattern0_0 = arg0;
3529     let pattern1_0 = arg1;
3530     // Rule at src/isa/aarch64/inst.isle line 2032.
3531     let expr0_0 = VecMisc2::Fcmeq0;
3532     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3533     return Some(expr1_0);
3534 }
3535 
3536 // Generated as internal constructor for term int_cmp_zero.
3537 pub fn constructor_int_cmp_zero<C: Context>(
3538     ctx: &mut C,
3539     arg0: &IntCC,
3540     arg1: Reg,
3541     arg2: &VectorSize,
3542 ) -> Option<Reg> {
3543     let pattern0_0 = arg0;
3544     let pattern1_0 = arg1;
3545     let pattern2_0 = arg2;
3546     // Rule at src/isa/aarch64/inst.isle line 2058.
3547     let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0);
3548     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3549     return Some(expr1_0);
3550 }
3551 
3552 // Generated as internal constructor for term int_cmp_zero_swap.
3553 pub fn constructor_int_cmp_zero_swap<C: Context>(
3554     ctx: &mut C,
3555     arg0: &IntCC,
3556     arg1: Reg,
3557     arg2: &VectorSize,
3558 ) -> Option<Reg> {
3559     let pattern0_0 = arg0;
3560     let pattern1_0 = arg1;
3561     let pattern2_0 = arg2;
3562     // Rule at src/isa/aarch64/inst.isle line 2063.
3563     let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0);
3564     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3565     return Some(expr1_0);
3566 }
3567 
3568 // Generated as internal constructor for term cmeq0.
3569 pub fn constructor_cmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3570     let pattern0_0 = arg0;
3571     let pattern1_0 = arg1;
3572     // Rule at src/isa/aarch64/inst.isle line 2068.
3573     let expr0_0 = VecMisc2::Cmeq0;
3574     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3575     return Some(expr1_0);
3576 }
3577 
3578 // Generated as internal constructor for term lower.
3579 pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> {
3580     let pattern0_0 = arg0;
3581     if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
3582         let pattern2_0 = C::value_type(ctx, pattern1_0);
3583         if pattern2_0 == I8 {
3584             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3585             if let &InstructionData::Unary {
3586                 opcode: ref pattern5_0,
3587                 arg: pattern5_1,
3588             } = &pattern4_0
3589             {
3590                 match pattern5_0 {
3591                     &Opcode::Bitrev => {
3592                         // Rule at src/isa/aarch64/lower.isle line 980.
3593                         let expr0_0: Type = I32;
3594                         let expr1_0: Type = I32;
3595                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3596                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3597                         let expr4_0: u8 = 24;
3598                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3599                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3600                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3601                         return Some(expr7_0);
3602                     }
3603                     &Opcode::Clz => {
3604                         // Rule at src/isa/aarch64/lower.isle line 1001.
3605                         let expr0_0: Type = I32;
3606                         let expr1_0: Type = I32;
3607                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3608                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3609                         let expr4_0: u8 = 24;
3610                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3611                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3612                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3613                         return Some(expr7_0);
3614                     }
3615                     &Opcode::Cls => {
3616                         // Rule at src/isa/aarch64/lower.isle line 1048.
3617                         let expr0_0: Type = I32;
3618                         let expr1_0: Type = I32;
3619                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3620                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3621                         let expr4_0: u8 = 24;
3622                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3623                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3624                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3625                         return Some(expr7_0);
3626                     }
3627                     &Opcode::Ctz => {
3628                         // Rule at src/isa/aarch64/lower.isle line 1031.
3629                         let expr0_0: Type = I32;
3630                         let expr1_0: Type = I32;
3631                         let expr2_0: Type = I32;
3632                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3633                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3634                         let expr5_0: Type = I32;
3635                         let expr6_0: u64 = 8388608;
3636                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3637                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3638                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3639                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3640                         return Some(expr10_0);
3641                     }
3642                     &Opcode::Popcnt => {
3643                         // Rule at src/isa/aarch64/lower.isle line 1099.
3644                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3645                         let expr1_0 = ScalarSize::Size32;
3646                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3647                         let expr3_0 = VectorSize::Size8x8;
3648                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3649                         let expr5_0: u8 = 0;
3650                         let expr6_0 = VectorSize::Size8x16;
3651                         let expr7_0 = constructor_mov_from_vec(ctx, expr4_0, expr5_0, &expr6_0)?;
3652                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
3653                         return Some(expr8_0);
3654                     }
3655                     _ => {}
3656                 }
3657             }
3658         }
3659         if pattern2_0 == I16 {
3660             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3661             if let &InstructionData::Unary {
3662                 opcode: ref pattern5_0,
3663                 arg: pattern5_1,
3664             } = &pattern4_0
3665             {
3666                 match pattern5_0 {
3667                     &Opcode::Bitrev => {
3668                         // Rule at src/isa/aarch64/lower.isle line 986.
3669                         let expr0_0: Type = I32;
3670                         let expr1_0: Type = I32;
3671                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3672                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3673                         let expr4_0: u8 = 16;
3674                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3675                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3676                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3677                         return Some(expr7_0);
3678                     }
3679                     &Opcode::Clz => {
3680                         // Rule at src/isa/aarch64/lower.isle line 1004.
3681                         let expr0_0: Type = I32;
3682                         let expr1_0: Type = I32;
3683                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3684                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3685                         let expr4_0: u8 = 16;
3686                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3687                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3688                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3689                         return Some(expr7_0);
3690                     }
3691                     &Opcode::Cls => {
3692                         // Rule at src/isa/aarch64/lower.isle line 1051.
3693                         let expr0_0: Type = I32;
3694                         let expr1_0: Type = I32;
3695                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3696                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3697                         let expr4_0: u8 = 16;
3698                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3699                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3700                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3701                         return Some(expr7_0);
3702                     }
3703                     &Opcode::Ctz => {
3704                         // Rule at src/isa/aarch64/lower.isle line 1034.
3705                         let expr0_0: Type = I32;
3706                         let expr1_0: Type = I32;
3707                         let expr2_0: Type = I32;
3708                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3709                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3710                         let expr5_0: Type = I32;
3711                         let expr6_0: u64 = 32768;
3712                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3713                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3714                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3715                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3716                         return Some(expr10_0);
3717                     }
3718                     &Opcode::Popcnt => {
3719                         // Rule at src/isa/aarch64/lower.isle line 1105.
3720                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3721                         let expr1_0 = ScalarSize::Size32;
3722                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3723                         let expr3_0 = VectorSize::Size8x8;
3724                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3725                         let expr5_0 = VectorSize::Size8x8;
3726                         let expr6_0 = constructor_addp(ctx, expr4_0, expr4_0, &expr5_0)?;
3727                         let expr7_0: u8 = 0;
3728                         let expr8_0 = VectorSize::Size8x16;
3729                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3730                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3731                         return Some(expr10_0);
3732                     }
3733                     _ => {}
3734                 }
3735             }
3736         }
3737         if pattern2_0 == I32 {
3738             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3739             match &pattern4_0 {
3740                 &InstructionData::Binary {
3741                     opcode: ref pattern5_0,
3742                     args: ref pattern5_1,
3743                 } => {
3744                     match pattern5_0 {
3745                         &Opcode::Rotl => {
3746                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3747                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3748                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3749                                 if let &InstructionData::UnaryImm {
3750                                     opcode: ref pattern10_0,
3751                                     imm: pattern10_1,
3752                                 } = &pattern9_0
3753                                 {
3754                                     if let &Opcode::Iconst = pattern10_0 {
3755                                         let closure12 = || {
3756                                             let expr0_0: Type = I32;
3757                                             return Some(expr0_0);
3758                                         };
3759                                         if let Some(pattern12_0) = closure12() {
3760                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3761                                                 ctx,
3762                                                 pattern10_1,
3763                                                 pattern12_0,
3764                                             ) {
3765                                                 // Rule at src/isa/aarch64/lower.isle line 871.
3766                                                 let expr0_0: Type = I32;
3767                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3768                                                 let expr2_0: Type = I32;
3769                                                 let expr3_0 =
3770                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3771                                                 let expr4_0 = constructor_a64_rotr_imm(
3772                                                     ctx, expr0_0, expr1_0, expr3_0,
3773                                                 )?;
3774                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3775                                                 return Some(expr5_0);
3776                                             }
3777                                         }
3778                                     }
3779                                 }
3780                             }
3781                             // Rule at src/isa/aarch64/lower.isle line 861.
3782                             let expr0_0: Type = I32;
3783                             let expr1_0 = C::zero_reg(ctx);
3784                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3785                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3786                             let expr4_0: Type = I32;
3787                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3788                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3789                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3790                             return Some(expr7_0);
3791                         }
3792                         &Opcode::Rotr => {
3793                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3794                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3795                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3796                                 if let &InstructionData::UnaryImm {
3797                                     opcode: ref pattern10_0,
3798                                     imm: pattern10_1,
3799                                 } = &pattern9_0
3800                                 {
3801                                     if let &Opcode::Iconst = pattern10_0 {
3802                                         let closure12 = || {
3803                                             let expr0_0: Type = I32;
3804                                             return Some(expr0_0);
3805                                         };
3806                                         if let Some(pattern12_0) = closure12() {
3807                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3808                                                 ctx,
3809                                                 pattern10_1,
3810                                                 pattern12_0,
3811                                             ) {
3812                                                 // Rule at src/isa/aarch64/lower.isle line 913.
3813                                                 let expr0_0: Type = I32;
3814                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3815                                                 let expr2_0 = constructor_a64_rotr_imm(
3816                                                     ctx,
3817                                                     expr0_0,
3818                                                     expr1_0,
3819                                                     pattern13_0,
3820                                                 )?;
3821                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3822                                                 return Some(expr3_0);
3823                                             }
3824                                         }
3825                                     }
3826                                 }
3827                             }
3828                             // Rule at src/isa/aarch64/lower.isle line 901.
3829                             let expr0_0: Type = I32;
3830                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3831                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3832                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
3833                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3834                             return Some(expr4_0);
3835                         }
3836                         _ => {}
3837                     }
3838                 }
3839                 &InstructionData::Unary {
3840                     opcode: ref pattern5_0,
3841                     arg: pattern5_1,
3842                 } => {
3843                     if let &Opcode::Popcnt = pattern5_0 {
3844                         // Rule at src/isa/aarch64/lower.isle line 1111.
3845                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3846                         let expr1_0 = ScalarSize::Size32;
3847                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3848                         let expr3_0 = VectorSize::Size8x8;
3849                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3850                         let expr5_0 = VectorSize::Size8x8;
3851                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
3852                         let expr7_0: u8 = 0;
3853                         let expr8_0 = VectorSize::Size8x16;
3854                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3855                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3856                         return Some(expr10_0);
3857                     }
3858                 }
3859                 _ => {}
3860             }
3861         }
3862         if pattern2_0 == I64 {
3863             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3864             match &pattern4_0 {
3865                 &InstructionData::Binary {
3866                     opcode: ref pattern5_0,
3867                     args: ref pattern5_1,
3868                 } => {
3869                     match pattern5_0 {
3870                         &Opcode::Umulhi => {
3871                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3872                             // Rule at src/isa/aarch64/lower.isle line 371.
3873                             let expr0_0: Type = I64;
3874                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3875                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3876                             let expr3_0 = constructor_umulh(ctx, expr0_0, expr1_0, expr2_0)?;
3877                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3878                             return Some(expr4_0);
3879                         }
3880                         &Opcode::Smulhi => {
3881                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3882                             // Rule at src/isa/aarch64/lower.isle line 359.
3883                             let expr0_0: Type = I64;
3884                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3885                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3886                             let expr3_0 = constructor_smulh(ctx, expr0_0, expr1_0, expr2_0)?;
3887                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3888                             return Some(expr4_0);
3889                         }
3890                         &Opcode::Band => {
3891                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3892                             // Rule at src/isa/aarch64/lower.isle line 592.
3893                             let expr0_0 = ALUOp::And;
3894                             let expr1_0: Type = I64;
3895                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3896                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3897                             )?;
3898                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3899                             return Some(expr3_0);
3900                         }
3901                         &Opcode::Bor => {
3902                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3903                             // Rule at src/isa/aarch64/lower.isle line 605.
3904                             let expr0_0 = ALUOp::Orr;
3905                             let expr1_0: Type = I64;
3906                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3907                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3908                             )?;
3909                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3910                             return Some(expr3_0);
3911                         }
3912                         &Opcode::Bxor => {
3913                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3914                             // Rule at src/isa/aarch64/lower.isle line 618.
3915                             let expr0_0 = ALUOp::Eor;
3916                             let expr1_0: Type = I64;
3917                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3918                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3919                             )?;
3920                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3921                             return Some(expr3_0);
3922                         }
3923                         &Opcode::BandNot => {
3924                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3925                             // Rule at src/isa/aarch64/lower.isle line 631.
3926                             let expr0_0 = ALUOp::AndNot;
3927                             let expr1_0: Type = I64;
3928                             let expr2_0 = constructor_alu_rs_imm_logic(
3929                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3930                             )?;
3931                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3932                             return Some(expr3_0);
3933                         }
3934                         &Opcode::BorNot => {
3935                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3936                             // Rule at src/isa/aarch64/lower.isle line 644.
3937                             let expr0_0 = ALUOp::OrrNot;
3938                             let expr1_0: Type = I64;
3939                             let expr2_0 = constructor_alu_rs_imm_logic(
3940                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3941                             )?;
3942                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3943                             return Some(expr3_0);
3944                         }
3945                         &Opcode::BxorNot => {
3946                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3947                             // Rule at src/isa/aarch64/lower.isle line 654.
3948                             let expr0_0 = ALUOp::EorNot;
3949                             let expr1_0: Type = I64;
3950                             let expr2_0 = constructor_alu_rs_imm_logic(
3951                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3952                             )?;
3953                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3954                             return Some(expr3_0);
3955                         }
3956                         &Opcode::Rotl => {
3957                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3958                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3959                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3960                                 if let &InstructionData::UnaryImm {
3961                                     opcode: ref pattern10_0,
3962                                     imm: pattern10_1,
3963                                 } = &pattern9_0
3964                                 {
3965                                     if let &Opcode::Iconst = pattern10_0 {
3966                                         let closure12 = || {
3967                                             let expr0_0: Type = I64;
3968                                             return Some(expr0_0);
3969                                         };
3970                                         if let Some(pattern12_0) = closure12() {
3971                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3972                                                 ctx,
3973                                                 pattern10_1,
3974                                                 pattern12_0,
3975                                             ) {
3976                                                 // Rule at src/isa/aarch64/lower.isle line 875.
3977                                                 let expr0_0: Type = I64;
3978                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3979                                                 let expr2_0: Type = I64;
3980                                                 let expr3_0 =
3981                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3982                                                 let expr4_0 = constructor_a64_rotr_imm(
3983                                                     ctx, expr0_0, expr1_0, expr3_0,
3984                                                 )?;
3985                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3986                                                 return Some(expr5_0);
3987                                             }
3988                                         }
3989                                     }
3990                                 }
3991                             }
3992                             // Rule at src/isa/aarch64/lower.isle line 866.
3993                             let expr0_0: Type = I64;
3994                             let expr1_0 = C::zero_reg(ctx);
3995                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3996                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3997                             let expr4_0: Type = I64;
3998                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3999                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
4000                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
4001                             return Some(expr7_0);
4002                         }
4003                         &Opcode::Rotr => {
4004                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4005                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
4006                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
4007                                 if let &InstructionData::UnaryImm {
4008                                     opcode: ref pattern10_0,
4009                                     imm: pattern10_1,
4010                                 } = &pattern9_0
4011                                 {
4012                                     if let &Opcode::Iconst = pattern10_0 {
4013                                         let closure12 = || {
4014                                             let expr0_0: Type = I64;
4015                                             return Some(expr0_0);
4016                                         };
4017                                         if let Some(pattern12_0) = closure12() {
4018                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4019                                                 ctx,
4020                                                 pattern10_1,
4021                                                 pattern12_0,
4022                                             ) {
4023                                                 // Rule at src/isa/aarch64/lower.isle line 917.
4024                                                 let expr0_0: Type = I64;
4025                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4026                                                 let expr2_0 = constructor_a64_rotr_imm(
4027                                                     ctx,
4028                                                     expr0_0,
4029                                                     expr1_0,
4030                                                     pattern13_0,
4031                                                 )?;
4032                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4033                                                 return Some(expr3_0);
4034                                             }
4035                                         }
4036                                     }
4037                                 }
4038                             }
4039                             // Rule at src/isa/aarch64/lower.isle line 905.
4040                             let expr0_0: Type = I64;
4041                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4042                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4043                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
4044                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4045                             return Some(expr4_0);
4046                         }
4047                         &Opcode::Ishl => {
4048                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4049                             // Rule at src/isa/aarch64/lower.isle line 666.
4050                             let expr0_0 = ALUOp::Lsl;
4051                             let expr1_0: Type = I64;
4052                             let expr2_0 = C::put_in_reg(ctx, pattern7_0);
4053                             let expr3_0 =
4054                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4055                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4056                             return Some(expr4_0);
4057                         }
4058                         &Opcode::Ushr => {
4059                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4060                             // Rule at src/isa/aarch64/lower.isle line 750.
4061                             let expr0_0 = ALUOp::Lsr;
4062                             let expr1_0: Type = I64;
4063                             let expr2_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
4064                             let expr3_0 =
4065                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4066                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4067                             return Some(expr4_0);
4068                         }
4069                         &Opcode::Sshr => {
4070                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4071                             // Rule at src/isa/aarch64/lower.isle line 797.
4072                             let expr0_0 = ALUOp::Asr;
4073                             let expr1_0: Type = I64;
4074                             let expr2_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
4075                             let expr3_0 =
4076                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4077                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4078                             return Some(expr4_0);
4079                         }
4080                         _ => {}
4081                     }
4082                 }
4083                 &InstructionData::Unary {
4084                     opcode: ref pattern5_0,
4085                     arg: pattern5_1,
4086                 } => {
4087                     if let &Opcode::Popcnt = pattern5_0 {
4088                         // Rule at src/isa/aarch64/lower.isle line 1117.
4089                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4090                         let expr1_0 = ScalarSize::Size64;
4091                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
4092                         let expr3_0 = VectorSize::Size8x8;
4093                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
4094                         let expr5_0 = VectorSize::Size8x8;
4095                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
4096                         let expr7_0: u8 = 0;
4097                         let expr8_0 = VectorSize::Size8x16;
4098                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
4099                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
4100                         return Some(expr10_0);
4101                     }
4102                 }
4103                 _ => {}
4104             }
4105         }
4106         if pattern2_0 == I128 {
4107             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4108             match &pattern4_0 {
4109                 &InstructionData::Binary {
4110                     opcode: ref pattern5_0,
4111                     args: ref pattern5_1,
4112                 } => {
4113                     match pattern5_0 {
4114                         &Opcode::Iadd => {
4115                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4116                             // Rule at src/isa/aarch64/lower.isle line 83.
4117                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4118                             let expr1_0: usize = 0;
4119                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4120                             let expr3_0: usize = 1;
4121                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4122                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4123                             let expr6_0: usize = 0;
4124                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4125                             let expr8_0: usize = 1;
4126                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4127                             let expr10_0: Type = I64;
4128                             let expr11_0 =
4129                                 constructor_add_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4130                             let expr12_0: Type = I64;
4131                             let expr13_0 = constructor_adc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4132                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4133                             let expr15_0 = C::output(ctx, expr14_0);
4134                             return Some(expr15_0);
4135                         }
4136                         &Opcode::Isub => {
4137                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4138                             // Rule at src/isa/aarch64/lower.isle line 133.
4139                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4140                             let expr1_0: usize = 0;
4141                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4142                             let expr3_0: usize = 1;
4143                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4144                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4145                             let expr6_0: usize = 0;
4146                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4147                             let expr8_0: usize = 1;
4148                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4149                             let expr10_0: Type = I64;
4150                             let expr11_0 =
4151                                 constructor_sub_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4152                             let expr12_0: Type = I64;
4153                             let expr13_0 = constructor_sbc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4154                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4155                             let expr15_0 = C::output(ctx, expr14_0);
4156                             return Some(expr15_0);
4157                         }
4158                         &Opcode::Imul => {
4159                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4160                             // Rule at src/isa/aarch64/lower.isle line 187.
4161                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4162                             let expr1_0: usize = 0;
4163                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4164                             let expr3_0: usize = 1;
4165                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4166                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4167                             let expr6_0: usize = 0;
4168                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4169                             let expr8_0: usize = 1;
4170                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4171                             let expr10_0: Type = I64;
4172                             let expr11_0 = constructor_umulh(ctx, expr10_0, expr2_0, expr7_0)?;
4173                             let expr12_0: Type = I64;
4174                             let expr13_0 =
4175                                 constructor_madd(ctx, expr12_0, expr2_0, expr9_0, expr11_0)?;
4176                             let expr14_0: Type = I64;
4177                             let expr15_0 =
4178                                 constructor_madd(ctx, expr14_0, expr4_0, expr7_0, expr13_0)?;
4179                             let expr16_0: Type = I64;
4180                             let expr17_0 = C::zero_reg(ctx);
4181                             let expr18_0 =
4182                                 constructor_madd(ctx, expr16_0, expr2_0, expr7_0, expr17_0)?;
4183                             let expr19_0 = C::value_regs(ctx, expr18_0, expr15_0);
4184                             let expr20_0 = C::output(ctx, expr19_0);
4185                             return Some(expr20_0);
4186                         }
4187                         &Opcode::Band => {
4188                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4189                             // Rule at src/isa/aarch64/lower.isle line 595.
4190                             let expr0_0 = ALUOp::And;
4191                             let expr1_0: Type = I64;
4192                             let expr2_0 = constructor_i128_alu_bitop(
4193                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4194                             )?;
4195                             let expr3_0 = C::output(ctx, expr2_0);
4196                             return Some(expr3_0);
4197                         }
4198                         &Opcode::Bor => {
4199                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4200                             // Rule at src/isa/aarch64/lower.isle line 608.
4201                             let expr0_0 = ALUOp::Orr;
4202                             let expr1_0: Type = I64;
4203                             let expr2_0 = constructor_i128_alu_bitop(
4204                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4205                             )?;
4206                             let expr3_0 = C::output(ctx, expr2_0);
4207                             return Some(expr3_0);
4208                         }
4209                         &Opcode::Bxor => {
4210                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4211                             // Rule at src/isa/aarch64/lower.isle line 621.
4212                             let expr0_0 = ALUOp::Eor;
4213                             let expr1_0: Type = I64;
4214                             let expr2_0 = constructor_i128_alu_bitop(
4215                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4216                             )?;
4217                             let expr3_0 = C::output(ctx, expr2_0);
4218                             return Some(expr3_0);
4219                         }
4220                         &Opcode::BandNot => {
4221                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4222                             // Rule at src/isa/aarch64/lower.isle line 634.
4223                             let expr0_0 = ALUOp::AndNot;
4224                             let expr1_0: Type = I64;
4225                             let expr2_0 = constructor_i128_alu_bitop(
4226                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4227                             )?;
4228                             let expr3_0 = C::output(ctx, expr2_0);
4229                             return Some(expr3_0);
4230                         }
4231                         &Opcode::BorNot => {
4232                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4233                             // Rule at src/isa/aarch64/lower.isle line 647.
4234                             let expr0_0 = ALUOp::OrrNot;
4235                             let expr1_0: Type = I64;
4236                             let expr2_0 = constructor_i128_alu_bitop(
4237                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4238                             )?;
4239                             let expr3_0 = C::output(ctx, expr2_0);
4240                             return Some(expr3_0);
4241                         }
4242                         &Opcode::BxorNot => {
4243                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4244                             // Rule at src/isa/aarch64/lower.isle line 657.
4245                             let expr0_0 = ALUOp::EorNot;
4246                             let expr1_0: Type = I64;
4247                             let expr2_0 = constructor_i128_alu_bitop(
4248                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4249                             )?;
4250                             let expr3_0 = C::output(ctx, expr2_0);
4251                             return Some(expr3_0);
4252                         }
4253                         &Opcode::Rotl => {
4254                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4255                             // Rule at src/isa/aarch64/lower.isle line 884.
4256                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4257                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4258                             let expr2_0: usize = 0;
4259                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4260                             let expr4_0: Type = I64;
4261                             let expr5_0: Type = I64;
4262                             let expr6_0: u64 = 128;
4263                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4264                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4265                             let expr9_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4266                             let expr10_0 = constructor_lower_ushr128(ctx, expr0_0, expr8_0)?;
4267                             let expr11_0: Type = I64;
4268                             let expr12_0: usize = 0;
4269                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4270                             let expr14_0: usize = 0;
4271                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4272                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4273                             let expr17_0: Type = I64;
4274                             let expr18_0: usize = 1;
4275                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4276                             let expr20_0: usize = 1;
4277                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4278                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4279                             let expr23_0 = C::value_regs(ctx, expr16_0, expr22_0);
4280                             let expr24_0 = C::output(ctx, expr23_0);
4281                             return Some(expr24_0);
4282                         }
4283                         &Opcode::Rotr => {
4284                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4285                             // Rule at src/isa/aarch64/lower.isle line 965.
4286                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4287                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4288                             let expr2_0: usize = 0;
4289                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4290                             let expr4_0: Type = I64;
4291                             let expr5_0: Type = I64;
4292                             let expr6_0: u64 = 128;
4293                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4294                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4295                             let expr9_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4296                             let expr10_0 = constructor_lower_shl128(ctx, expr0_0, expr8_0)?;
4297                             let expr11_0: Type = I64;
4298                             let expr12_0: usize = 1;
4299                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4300                             let expr14_0: usize = 1;
4301                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4302                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4303                             let expr17_0: Type = I64;
4304                             let expr18_0: usize = 0;
4305                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4306                             let expr20_0: usize = 0;
4307                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4308                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4309                             let expr23_0 = C::value_regs(ctx, expr22_0, expr16_0);
4310                             let expr24_0 = C::output(ctx, expr23_0);
4311                             return Some(expr24_0);
4312                         }
4313                         &Opcode::Ishl => {
4314                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4315                             // Rule at src/isa/aarch64/lower.isle line 670.
4316                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4317                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4318                             let expr2_0: usize = 0;
4319                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4320                             let expr4_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4321                             let expr5_0 = C::output(ctx, expr4_0);
4322                             return Some(expr5_0);
4323                         }
4324                         &Opcode::Ushr => {
4325                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4326                             // Rule at src/isa/aarch64/lower.isle line 754.
4327                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4328                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4329                             let expr2_0: usize = 0;
4330                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4331                             let expr4_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4332                             let expr5_0 = C::output(ctx, expr4_0);
4333                             return Some(expr5_0);
4334                         }
4335                         &Opcode::Sshr => {
4336                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4337                             // Rule at src/isa/aarch64/lower.isle line 801.
4338                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4339                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4340                             let expr2_0: usize = 0;
4341                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4342                             let expr4_0 = constructor_lower_sshr128(ctx, expr0_0, expr3_0)?;
4343                             let expr5_0 = C::output(ctx, expr4_0);
4344                             return Some(expr5_0);
4345                         }
4346                         _ => {}
4347                     }
4348                 }
4349                 &InstructionData::Unary {
4350                     opcode: ref pattern5_0,
4351                     arg: pattern5_1,
4352                 } => {
4353                     match pattern5_0 {
4354                         &Opcode::Bnot => {
4355                             // Rule at src/isa/aarch64/lower.isle line 575.
4356                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4357                             let expr1_0: usize = 0;
4358                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4359                             let expr3_0: usize = 1;
4360                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4361                             let expr5_0: Type = I64;
4362                             let expr6_0 = C::zero_reg(ctx);
4363                             let expr7_0 = constructor_orr_not(ctx, expr5_0, expr6_0, expr2_0)?;
4364                             let expr8_0: Type = I64;
4365                             let expr9_0 = C::zero_reg(ctx);
4366                             let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, expr4_0)?;
4367                             let expr11_0 = C::value_regs(ctx, expr7_0, expr10_0);
4368                             let expr12_0 = C::output(ctx, expr11_0);
4369                             return Some(expr12_0);
4370                         }
4371                         &Opcode::Bitrev => {
4372                             // Rule at src/isa/aarch64/lower.isle line 989.
4373                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4374                             let expr1_0: Type = I64;
4375                             let expr2_0: usize = 0;
4376                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4377                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4378                             let expr5_0: Type = I64;
4379                             let expr6_0: usize = 1;
4380                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4381                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4382                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4383                             let expr10_0 = C::output(ctx, expr9_0);
4384                             return Some(expr10_0);
4385                         }
4386                         &Opcode::Clz => {
4387                             // Rule at src/isa/aarch64/lower.isle line 1007.
4388                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4389                             let expr1_0 = constructor_lower_clz128(ctx, expr0_0)?;
4390                             let expr2_0 = C::output(ctx, expr1_0);
4391                             return Some(expr2_0);
4392                         }
4393                         &Opcode::Cls => {
4394                             // Rule at src/isa/aarch64/lower.isle line 1063.
4395                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4396                             let expr1_0: usize = 0;
4397                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4398                             let expr3_0: usize = 1;
4399                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4400                             let expr5_0: Type = I64;
4401                             let expr6_0 = constructor_a64_cls(ctx, expr5_0, expr2_0)?;
4402                             let expr7_0: Type = I64;
4403                             let expr8_0 = constructor_a64_cls(ctx, expr7_0, expr4_0)?;
4404                             let expr9_0: Type = I64;
4405                             let expr10_0 = constructor_eon(ctx, expr9_0, expr4_0, expr2_0)?;
4406                             let expr11_0: Type = I64;
4407                             let expr12_0: u8 = 63;
4408                             let expr13_0 = C::imm_shift_from_u8(ctx, expr12_0);
4409                             let expr14_0 = constructor_lsr_imm(ctx, expr11_0, expr10_0, expr13_0)?;
4410                             let expr15_0: Type = I64;
4411                             let expr16_0 =
4412                                 constructor_madd(ctx, expr15_0, expr6_0, expr14_0, expr14_0)?;
4413                             let expr17_0: u8 = 63;
4414                             let expr18_0 = C::u8_into_imm12(ctx, expr17_0);
4415                             let expr19_0 = constructor_cmp64_imm(ctx, expr8_0, expr18_0)?;
4416                             let expr20_0 = Cond::Eq;
4417                             let expr21_0 = C::zero_reg(ctx);
4418                             let expr22_0 = constructor_csel(ctx, &expr20_0, expr16_0, expr21_0)?;
4419                             let expr23_0 = constructor_with_flags_reg(ctx, &expr19_0, &expr22_0)?;
4420                             let expr24_0: Type = I64;
4421                             let expr25_0 = constructor_add(ctx, expr24_0, expr23_0, expr8_0)?;
4422                             let expr26_0: Type = I64;
4423                             let expr27_0: u64 = 0;
4424                             let expr28_0 = constructor_imm(ctx, expr26_0, expr27_0)?;
4425                             let expr29_0 = C::value_regs(ctx, expr25_0, expr28_0);
4426                             let expr30_0 = C::output(ctx, expr29_0);
4427                             return Some(expr30_0);
4428                         }
4429                         &Opcode::Ctz => {
4430                             // Rule at src/isa/aarch64/lower.isle line 1037.
4431                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4432                             let expr1_0: Type = I64;
4433                             let expr2_0: usize = 0;
4434                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4435                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4436                             let expr5_0: Type = I64;
4437                             let expr6_0: usize = 1;
4438                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4439                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4440                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4441                             let expr10_0 = constructor_lower_clz128(ctx, expr9_0)?;
4442                             let expr11_0 = C::output(ctx, expr10_0);
4443                             return Some(expr11_0);
4444                         }
4445                         &Opcode::Popcnt => {
4446                             // Rule at src/isa/aarch64/lower.isle line 1123.
4447                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4448                             let expr1_0: usize = 0;
4449                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4450                             let expr3_0 = ScalarSize::Size64;
4451                             let expr4_0 = constructor_mov_to_fpu(ctx, expr2_0, &expr3_0)?;
4452                             let expr5_0: usize = 1;
4453                             let expr6_0 = C::value_regs_get(ctx, expr0_0, expr5_0);
4454                             let expr7_0: u8 = 1;
4455                             let expr8_0 = VectorSize::Size64x2;
4456                             let expr9_0 =
4457                                 constructor_mov_to_vec(ctx, expr4_0, expr6_0, expr7_0, &expr8_0)?;
4458                             let expr10_0 = VectorSize::Size8x16;
4459                             let expr11_0 = constructor_vec_cnt(ctx, expr9_0, &expr10_0)?;
4460                             let expr12_0 = VectorSize::Size8x16;
4461                             let expr13_0 = constructor_addv(ctx, expr11_0, &expr12_0)?;
4462                             let expr14_0: u8 = 0;
4463                             let expr15_0 = VectorSize::Size8x16;
4464                             let expr16_0 =
4465                                 constructor_mov_from_vec(ctx, expr13_0, expr14_0, &expr15_0)?;
4466                             let expr17_0: Type = I64;
4467                             let expr18_0: u64 = 0;
4468                             let expr19_0 = constructor_imm(ctx, expr17_0, expr18_0)?;
4469                             let expr20_0 = C::value_regs(ctx, expr16_0, expr19_0);
4470                             let expr21_0 = C::output(ctx, expr20_0);
4471                             return Some(expr21_0);
4472                         }
4473                         &Opcode::Uextend => {
4474                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4475                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4476                                 if let &InstructionData::BinaryImm8 {
4477                                     opcode: ref pattern9_0,
4478                                     arg: pattern9_1,
4479                                     imm: pattern9_2,
4480                                 } = &pattern8_0
4481                                 {
4482                                     if let &Opcode::Extractlane = pattern9_0 {
4483                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4484                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
4485                                         // Rule at src/isa/aarch64/lower.isle line 505.
4486                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4487                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
4488                                         let expr2_0 = constructor_mov_from_vec(
4489                                             ctx,
4490                                             expr0_0,
4491                                             pattern12_0,
4492                                             &expr1_0,
4493                                         )?;
4494                                         let expr3_0: Type = I64;
4495                                         let expr4_0: u64 = 0;
4496                                         let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
4497                                         let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
4498                                         let expr7_0 = C::output(ctx, expr6_0);
4499                                         return Some(expr7_0);
4500                                     }
4501                                 }
4502                             }
4503                             // Rule at src/isa/aarch64/lower.isle line 500.
4504                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
4505                             let expr1_0: Type = I64;
4506                             let expr2_0: u64 = 0;
4507                             let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
4508                             let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
4509                             let expr5_0 = C::output(ctx, expr4_0);
4510                             return Some(expr5_0);
4511                         }
4512                         &Opcode::Sextend => {
4513                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4514                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4515                                 if let &InstructionData::BinaryImm8 {
4516                                     opcode: ref pattern9_0,
4517                                     arg: pattern9_1,
4518                                     imm: pattern9_2,
4519                                 } = &pattern8_0
4520                                 {
4521                                     if let &Opcode::Extractlane = pattern9_0 {
4522                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4523                                         if pattern11_0 == I64X2 {
4524                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4525                                             // Rule at src/isa/aarch64/lower.isle line 549.
4526                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4527                                             let expr1_0 = VectorSize::Size64x2;
4528                                             let expr2_0 = constructor_mov_from_vec(
4529                                                 ctx,
4530                                                 expr0_0,
4531                                                 pattern13_0,
4532                                                 &expr1_0,
4533                                             )?;
4534                                             let expr3_0: Type = I64;
4535                                             let expr4_0: u8 = 63;
4536                                             let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
4537                                             let expr6_0 = constructor_asr_imm(
4538                                                 ctx, expr3_0, expr2_0, expr5_0,
4539                                             )?;
4540                                             let expr7_0 = C::value_regs(ctx, expr2_0, expr6_0);
4541                                             let expr8_0 = C::output(ctx, expr7_0);
4542                                             return Some(expr8_0);
4543                                         }
4544                                         if let Some(()) = C::not_i64x2(ctx, pattern11_0) {
4545                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4546                                             // Rule at src/isa/aarch64/lower.isle line 538.
4547                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4548                                             let expr1_0 =
4549                                                 constructor_vector_size(ctx, pattern11_0)?;
4550                                             let expr2_0: Type = I64;
4551                                             let expr3_0 = constructor_size_from_ty(ctx, expr2_0)?;
4552                                             let expr4_0 = constructor_mov_from_vec_signed(
4553                                                 ctx,
4554                                                 expr0_0,
4555                                                 pattern13_0,
4556                                                 &expr1_0,
4557                                                 &expr3_0,
4558                                             )?;
4559                                             let expr5_0: Type = I64;
4560                                             let expr6_0: u8 = 63;
4561                                             let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
4562                                             let expr8_0 = constructor_asr_imm(
4563                                                 ctx, expr5_0, expr4_0, expr7_0,
4564                                             )?;
4565                                             let expr9_0 = C::value_regs(ctx, expr4_0, expr8_0);
4566                                             let expr10_0 = C::output(ctx, expr9_0);
4567                                             return Some(expr10_0);
4568                                         }
4569                                     }
4570                                 }
4571                             }
4572                             // Rule at src/isa/aarch64/lower.isle line 528.
4573                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
4574                             let expr1_0: Type = I64;
4575                             let expr2_0: u8 = 63;
4576                             let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0);
4577                             let expr4_0 = constructor_asr_imm(ctx, expr1_0, expr0_0, expr3_0)?;
4578                             let expr5_0 = C::value_regs(ctx, expr0_0, expr4_0);
4579                             let expr6_0 = C::output(ctx, expr5_0);
4580                             return Some(expr6_0);
4581                         }
4582                         _ => {}
4583                     }
4584                 }
4585                 _ => {}
4586             }
4587         }
4588         if pattern2_0 == I8X16 {
4589             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4590             if let &InstructionData::Unary {
4591                 opcode: ref pattern5_0,
4592                 arg: pattern5_1,
4593             } = &pattern4_0
4594             {
4595                 if let &Opcode::Popcnt = pattern5_0 {
4596                     // Rule at src/isa/aarch64/lower.isle line 1131.
4597                     let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4598                     let expr1_0 = VectorSize::Size8x16;
4599                     let expr2_0 = constructor_vec_cnt(ctx, expr0_0, &expr1_0)?;
4600                     let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4601                     return Some(expr3_0);
4602                 }
4603             }
4604         }
4605         if pattern2_0 == I16X8 {
4606             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4607             if let &InstructionData::Binary {
4608                 opcode: ref pattern5_0,
4609                 args: ref pattern5_1,
4610             } = &pattern4_0
4611             {
4612                 if let &Opcode::Imul = pattern5_0 {
4613                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4614                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4615                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4616                         if let &InstructionData::Unary {
4617                             opcode: ref pattern10_0,
4618                             arg: pattern10_1,
4619                         } = &pattern9_0
4620                         {
4621                             match pattern10_0 {
4622                                 &Opcode::SwidenLow => {
4623                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4624                                     if pattern12_0 == I8X16 {
4625                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4626                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4627                                             if let &InstructionData::Unary {
4628                                                 opcode: ref pattern16_0,
4629                                                 arg: pattern16_1,
4630                                             } = &pattern15_0
4631                                             {
4632                                                 if let &Opcode::SwidenLow = pattern16_0 {
4633                                                     let pattern18_0 =
4634                                                         C::value_type(ctx, pattern16_1);
4635                                                     if pattern18_0 == I8X16 {
4636                                                         // Rule at src/isa/aarch64/lower.isle line 286.
4637                                                         let expr0_0 =
4638                                                             C::put_in_reg(ctx, pattern10_1);
4639                                                         let expr1_0 =
4640                                                             C::put_in_reg(ctx, pattern16_1);
4641                                                         let expr2_0: bool = false;
4642                                                         let expr3_0 = constructor_smull8(
4643                                                             ctx, expr0_0, expr1_0, expr2_0,
4644                                                         )?;
4645                                                         let expr4_0 =
4646                                                             constructor_output_reg(ctx, expr3_0)?;
4647                                                         return Some(expr4_0);
4648                                                     }
4649                                                 }
4650                                             }
4651                                         }
4652                                     }
4653                                 }
4654                                 &Opcode::SwidenHigh => {
4655                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4656                                     if pattern12_0 == I8X16 {
4657                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4658                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4659                                             if let &InstructionData::Unary {
4660                                                 opcode: ref pattern16_0,
4661                                                 arg: pattern16_1,
4662                                             } = &pattern15_0
4663                                             {
4664                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4665                                                     let pattern18_0 =
4666                                                         C::value_type(ctx, pattern16_1);
4667                                                     if pattern18_0 == I8X16 {
4668                                                         // Rule at src/isa/aarch64/lower.isle line 292.
4669                                                         let expr0_0 =
4670                                                             C::put_in_reg(ctx, pattern10_1);
4671                                                         let expr1_0 =
4672                                                             C::put_in_reg(ctx, pattern16_1);
4673                                                         let expr2_0: bool = true;
4674                                                         let expr3_0 = constructor_smull8(
4675                                                             ctx, expr0_0, expr1_0, expr2_0,
4676                                                         )?;
4677                                                         let expr4_0 =
4678                                                             constructor_output_reg(ctx, expr3_0)?;
4679                                                         return Some(expr4_0);
4680                                                     }
4681                                                 }
4682                                             }
4683                                         }
4684                                     }
4685                                 }
4686                                 &Opcode::UwidenLow => {
4687                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4688                                     if pattern12_0 == I8X16 {
4689                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4690                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4691                                             if let &InstructionData::Unary {
4692                                                 opcode: ref pattern16_0,
4693                                                 arg: pattern16_1,
4694                                             } = &pattern15_0
4695                                             {
4696                                                 if let &Opcode::UwidenLow = pattern16_0 {
4697                                                     let pattern18_0 =
4698                                                         C::value_type(ctx, pattern16_1);
4699                                                     if pattern18_0 == I8X16 {
4700                                                         // Rule at src/isa/aarch64/lower.isle line 298.
4701                                                         let expr0_0 =
4702                                                             C::put_in_reg(ctx, pattern10_1);
4703                                                         let expr1_0 =
4704                                                             C::put_in_reg(ctx, pattern16_1);
4705                                                         let expr2_0: bool = false;
4706                                                         let expr3_0 = constructor_umull8(
4707                                                             ctx, expr0_0, expr1_0, expr2_0,
4708                                                         )?;
4709                                                         let expr4_0 =
4710                                                             constructor_output_reg(ctx, expr3_0)?;
4711                                                         return Some(expr4_0);
4712                                                     }
4713                                                 }
4714                                             }
4715                                         }
4716                                     }
4717                                 }
4718                                 &Opcode::UwidenHigh => {
4719                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4720                                     if pattern12_0 == I8X16 {
4721                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4722                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4723                                             if let &InstructionData::Unary {
4724                                                 opcode: ref pattern16_0,
4725                                                 arg: pattern16_1,
4726                                             } = &pattern15_0
4727                                             {
4728                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4729                                                     let pattern18_0 =
4730                                                         C::value_type(ctx, pattern16_1);
4731                                                     if pattern18_0 == I8X16 {
4732                                                         // Rule at src/isa/aarch64/lower.isle line 304.
4733                                                         let expr0_0 =
4734                                                             C::put_in_reg(ctx, pattern10_1);
4735                                                         let expr1_0 =
4736                                                             C::put_in_reg(ctx, pattern16_1);
4737                                                         let expr2_0: bool = true;
4738                                                         let expr3_0 = constructor_umull8(
4739                                                             ctx, expr0_0, expr1_0, expr2_0,
4740                                                         )?;
4741                                                         let expr4_0 =
4742                                                             constructor_output_reg(ctx, expr3_0)?;
4743                                                         return Some(expr4_0);
4744                                                     }
4745                                                 }
4746                                             }
4747                                         }
4748                                     }
4749                                 }
4750                                 _ => {}
4751                             }
4752                         }
4753                     }
4754                 }
4755             }
4756         }
4757         if pattern2_0 == I32X4 {
4758             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4759             if let &InstructionData::Binary {
4760                 opcode: ref pattern5_0,
4761                 args: ref pattern5_1,
4762             } = &pattern4_0
4763             {
4764                 if let &Opcode::Imul = pattern5_0 {
4765                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4766                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4767                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4768                         if let &InstructionData::Unary {
4769                             opcode: ref pattern10_0,
4770                             arg: pattern10_1,
4771                         } = &pattern9_0
4772                         {
4773                             match pattern10_0 {
4774                                 &Opcode::SwidenLow => {
4775                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4776                                     if pattern12_0 == I16X8 {
4777                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4778                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4779                                             if let &InstructionData::Unary {
4780                                                 opcode: ref pattern16_0,
4781                                                 arg: pattern16_1,
4782                                             } = &pattern15_0
4783                                             {
4784                                                 if let &Opcode::SwidenLow = pattern16_0 {
4785                                                     let pattern18_0 =
4786                                                         C::value_type(ctx, pattern16_1);
4787                                                     if pattern18_0 == I16X8 {
4788                                                         // Rule at src/isa/aarch64/lower.isle line 310.
4789                                                         let expr0_0 =
4790                                                             C::put_in_reg(ctx, pattern10_1);
4791                                                         let expr1_0 =
4792                                                             C::put_in_reg(ctx, pattern16_1);
4793                                                         let expr2_0: bool = false;
4794                                                         let expr3_0 = constructor_smull16(
4795                                                             ctx, expr0_0, expr1_0, expr2_0,
4796                                                         )?;
4797                                                         let expr4_0 =
4798                                                             constructor_output_reg(ctx, expr3_0)?;
4799                                                         return Some(expr4_0);
4800                                                     }
4801                                                 }
4802                                             }
4803                                         }
4804                                     }
4805                                 }
4806                                 &Opcode::SwidenHigh => {
4807                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4808                                     if pattern12_0 == I16X8 {
4809                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4810                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4811                                             if let &InstructionData::Unary {
4812                                                 opcode: ref pattern16_0,
4813                                                 arg: pattern16_1,
4814                                             } = &pattern15_0
4815                                             {
4816                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4817                                                     let pattern18_0 =
4818                                                         C::value_type(ctx, pattern16_1);
4819                                                     if pattern18_0 == I16X8 {
4820                                                         // Rule at src/isa/aarch64/lower.isle line 316.
4821                                                         let expr0_0 =
4822                                                             C::put_in_reg(ctx, pattern10_1);
4823                                                         let expr1_0 =
4824                                                             C::put_in_reg(ctx, pattern16_1);
4825                                                         let expr2_0: bool = true;
4826                                                         let expr3_0 = constructor_smull16(
4827                                                             ctx, expr0_0, expr1_0, expr2_0,
4828                                                         )?;
4829                                                         let expr4_0 =
4830                                                             constructor_output_reg(ctx, expr3_0)?;
4831                                                         return Some(expr4_0);
4832                                                     }
4833                                                 }
4834                                             }
4835                                         }
4836                                     }
4837                                 }
4838                                 &Opcode::UwidenLow => {
4839                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4840                                     if pattern12_0 == I16X8 {
4841                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4842                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4843                                             if let &InstructionData::Unary {
4844                                                 opcode: ref pattern16_0,
4845                                                 arg: pattern16_1,
4846                                             } = &pattern15_0
4847                                             {
4848                                                 if let &Opcode::UwidenLow = pattern16_0 {
4849                                                     let pattern18_0 =
4850                                                         C::value_type(ctx, pattern16_1);
4851                                                     if pattern18_0 == I16X8 {
4852                                                         // Rule at src/isa/aarch64/lower.isle line 322.
4853                                                         let expr0_0 =
4854                                                             C::put_in_reg(ctx, pattern10_1);
4855                                                         let expr1_0 =
4856                                                             C::put_in_reg(ctx, pattern16_1);
4857                                                         let expr2_0: bool = false;
4858                                                         let expr3_0 = constructor_umull16(
4859                                                             ctx, expr0_0, expr1_0, expr2_0,
4860                                                         )?;
4861                                                         let expr4_0 =
4862                                                             constructor_output_reg(ctx, expr3_0)?;
4863                                                         return Some(expr4_0);
4864                                                     }
4865                                                 }
4866                                             }
4867                                         }
4868                                     }
4869                                 }
4870                                 &Opcode::UwidenHigh => {
4871                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4872                                     if pattern12_0 == I16X8 {
4873                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4874                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4875                                             if let &InstructionData::Unary {
4876                                                 opcode: ref pattern16_0,
4877                                                 arg: pattern16_1,
4878                                             } = &pattern15_0
4879                                             {
4880                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4881                                                     let pattern18_0 =
4882                                                         C::value_type(ctx, pattern16_1);
4883                                                     if pattern18_0 == I16X8 {
4884                                                         // Rule at src/isa/aarch64/lower.isle line 328.
4885                                                         let expr0_0 =
4886                                                             C::put_in_reg(ctx, pattern10_1);
4887                                                         let expr1_0 =
4888                                                             C::put_in_reg(ctx, pattern16_1);
4889                                                         let expr2_0: bool = true;
4890                                                         let expr3_0 = constructor_umull16(
4891                                                             ctx, expr0_0, expr1_0, expr2_0,
4892                                                         )?;
4893                                                         let expr4_0 =
4894                                                             constructor_output_reg(ctx, expr3_0)?;
4895                                                         return Some(expr4_0);
4896                                                     }
4897                                                 }
4898                                             }
4899                                         }
4900                                     }
4901                                 }
4902                                 _ => {}
4903                             }
4904                         }
4905                     }
4906                 }
4907             }
4908         }
4909         if pattern2_0 == I64X2 {
4910             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4911             if let &InstructionData::Binary {
4912                 opcode: ref pattern5_0,
4913                 args: ref pattern5_1,
4914             } = &pattern4_0
4915             {
4916                 if let &Opcode::Imul = pattern5_0 {
4917                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4918                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4919                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4920                         if let &InstructionData::Unary {
4921                             opcode: ref pattern10_0,
4922                             arg: pattern10_1,
4923                         } = &pattern9_0
4924                         {
4925                             match pattern10_0 {
4926                                 &Opcode::SwidenLow => {
4927                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4928                                     if pattern12_0 == I32X4 {
4929                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4930                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4931                                             if let &InstructionData::Unary {
4932                                                 opcode: ref pattern16_0,
4933                                                 arg: pattern16_1,
4934                                             } = &pattern15_0
4935                                             {
4936                                                 if let &Opcode::SwidenLow = pattern16_0 {
4937                                                     let pattern18_0 =
4938                                                         C::value_type(ctx, pattern16_1);
4939                                                     if pattern18_0 == I32X4 {
4940                                                         // Rule at src/isa/aarch64/lower.isle line 334.
4941                                                         let expr0_0 =
4942                                                             C::put_in_reg(ctx, pattern10_1);
4943                                                         let expr1_0 =
4944                                                             C::put_in_reg(ctx, pattern16_1);
4945                                                         let expr2_0: bool = false;
4946                                                         let expr3_0 = constructor_smull32(
4947                                                             ctx, expr0_0, expr1_0, expr2_0,
4948                                                         )?;
4949                                                         let expr4_0 =
4950                                                             constructor_output_reg(ctx, expr3_0)?;
4951                                                         return Some(expr4_0);
4952                                                     }
4953                                                 }
4954                                             }
4955                                         }
4956                                     }
4957                                 }
4958                                 &Opcode::SwidenHigh => {
4959                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4960                                     if pattern12_0 == I32X4 {
4961                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4962                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4963                                             if let &InstructionData::Unary {
4964                                                 opcode: ref pattern16_0,
4965                                                 arg: pattern16_1,
4966                                             } = &pattern15_0
4967                                             {
4968                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4969                                                     let pattern18_0 =
4970                                                         C::value_type(ctx, pattern16_1);
4971                                                     if pattern18_0 == I32X4 {
4972                                                         // Rule at src/isa/aarch64/lower.isle line 340.
4973                                                         let expr0_0 =
4974                                                             C::put_in_reg(ctx, pattern10_1);
4975                                                         let expr1_0 =
4976                                                             C::put_in_reg(ctx, pattern16_1);
4977                                                         let expr2_0: bool = true;
4978                                                         let expr3_0 = constructor_smull32(
4979                                                             ctx, expr0_0, expr1_0, expr2_0,
4980                                                         )?;
4981                                                         let expr4_0 =
4982                                                             constructor_output_reg(ctx, expr3_0)?;
4983                                                         return Some(expr4_0);
4984                                                     }
4985                                                 }
4986                                             }
4987                                         }
4988                                     }
4989                                 }
4990                                 &Opcode::UwidenLow => {
4991                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4992                                     if pattern12_0 == I32X4 {
4993                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4994                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4995                                             if let &InstructionData::Unary {
4996                                                 opcode: ref pattern16_0,
4997                                                 arg: pattern16_1,
4998                                             } = &pattern15_0
4999                                             {
5000                                                 if let &Opcode::UwidenLow = pattern16_0 {
5001                                                     let pattern18_0 =
5002                                                         C::value_type(ctx, pattern16_1);
5003                                                     if pattern18_0 == I32X4 {
5004                                                         // Rule at src/isa/aarch64/lower.isle line 346.
5005                                                         let expr0_0 =
5006                                                             C::put_in_reg(ctx, pattern10_1);
5007                                                         let expr1_0 =
5008                                                             C::put_in_reg(ctx, pattern16_1);
5009                                                         let expr2_0: bool = false;
5010                                                         let expr3_0 = constructor_umull32(
5011                                                             ctx, expr0_0, expr1_0, expr2_0,
5012                                                         )?;
5013                                                         let expr4_0 =
5014                                                             constructor_output_reg(ctx, expr3_0)?;
5015                                                         return Some(expr4_0);
5016                                                     }
5017                                                 }
5018                                             }
5019                                         }
5020                                     }
5021                                 }
5022                                 &Opcode::UwidenHigh => {
5023                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5024                                     if pattern12_0 == I32X4 {
5025                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5026                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5027                                             if let &InstructionData::Unary {
5028                                                 opcode: ref pattern16_0,
5029                                                 arg: pattern16_1,
5030                                             } = &pattern15_0
5031                                             {
5032                                                 if let &Opcode::UwidenHigh = pattern16_0 {
5033                                                     let pattern18_0 =
5034                                                         C::value_type(ctx, pattern16_1);
5035                                                     if pattern18_0 == I32X4 {
5036                                                         // Rule at src/isa/aarch64/lower.isle line 352.
5037                                                         let expr0_0 =
5038                                                             C::put_in_reg(ctx, pattern10_1);
5039                                                         let expr1_0 =
5040                                                             C::put_in_reg(ctx, pattern16_1);
5041                                                         let expr2_0: bool = true;
5042                                                         let expr3_0 = constructor_umull32(
5043                                                             ctx, expr0_0, expr1_0, expr2_0,
5044                                                         )?;
5045                                                         let expr4_0 =
5046                                                             constructor_output_reg(ctx, expr3_0)?;
5047                                                         return Some(expr4_0);
5048                                                     }
5049                                                 }
5050                                             }
5051                                         }
5052                                     }
5053                                 }
5054                                 _ => {}
5055                             }
5056                         }
5057                     }
5058                     // Rule at src/isa/aarch64/lower.isle line 247.
5059                     let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5060                     let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5061                     let expr2_0 = VectorSize::Size32x4;
5062                     let expr3_0 = constructor_rev64(ctx, expr1_0, &expr2_0)?;
5063                     let expr4_0 = VectorSize::Size32x4;
5064                     let expr5_0 = constructor_mul(ctx, expr3_0, expr0_0, &expr4_0)?;
5065                     let expr6_0: bool = false;
5066                     let expr7_0 = constructor_xtn64(ctx, expr0_0, expr6_0)?;
5067                     let expr8_0 = VectorSize::Size32x4;
5068                     let expr9_0 = constructor_addp(ctx, expr5_0, expr5_0, &expr8_0)?;
5069                     let expr10_0: bool = false;
5070                     let expr11_0 = constructor_xtn64(ctx, expr1_0, expr10_0)?;
5071                     let expr12_0: bool = false;
5072                     let expr13_0 = constructor_shll32(ctx, expr9_0, expr12_0)?;
5073                     let expr14_0: bool = false;
5074                     let expr15_0 = constructor_umlal32(ctx, expr13_0, expr11_0, expr7_0, expr14_0)?;
5075                     let expr16_0 = constructor_output_reg(ctx, expr15_0)?;
5076                     return Some(expr16_0);
5077                 }
5078             }
5079         }
5080         let pattern3_0 = C::inst_data(ctx, pattern0_0);
5081         match &pattern3_0 {
5082             &InstructionData::NullAry {
5083                 opcode: ref pattern4_0,
5084             } => {
5085                 if let &Opcode::Null = pattern4_0 {
5086                     // Rule at src/isa/aarch64/lower.isle line 22.
5087                     let expr0_0: u64 = 0;
5088                     let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5089                     let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5090                     return Some(expr2_0);
5091                 }
5092             }
5093             &InstructionData::UnaryImm {
5094                 opcode: ref pattern4_0,
5095                 imm: pattern4_1,
5096             } => {
5097                 if let &Opcode::Iconst = pattern4_0 {
5098                     let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1);
5099                     // Rule at src/isa/aarch64/lower.isle line 9.
5100                     let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?;
5101                     let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
5102                     return Some(expr1_0);
5103                 }
5104             }
5105             &InstructionData::UnaryBool {
5106                 opcode: ref pattern4_0,
5107                 imm: pattern4_1,
5108             } => {
5109                 if let &Opcode::Bconst = pattern4_0 {
5110                     if pattern4_1 == true {
5111                         // Rule at src/isa/aarch64/lower.isle line 17.
5112                         let expr0_0: u64 = 1;
5113                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5114                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5115                         return Some(expr2_0);
5116                     }
5117                     if pattern4_1 == false {
5118                         // Rule at src/isa/aarch64/lower.isle line 14.
5119                         let expr0_0: u64 = 0;
5120                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5121                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5122                         return Some(expr2_0);
5123                     }
5124                 }
5125             }
5126             &InstructionData::Unary {
5127                 opcode: ref pattern4_0,
5128                 arg: pattern4_1,
5129             } => {
5130                 match pattern4_0 {
5131                     &Opcode::Bitrev => {
5132                         // Rule at src/isa/aarch64/lower.isle line 995.
5133                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5134                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5135                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5136                         return Some(expr2_0);
5137                     }
5138                     &Opcode::Clz => {
5139                         // Rule at src/isa/aarch64/lower.isle line 1010.
5140                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5141                         let expr1_0 = constructor_a64_clz(ctx, pattern2_0, expr0_0)?;
5142                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5143                         return Some(expr2_0);
5144                     }
5145                     &Opcode::Cls => {
5146                         // Rule at src/isa/aarch64/lower.isle line 1077.
5147                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5148                         let expr1_0 = constructor_a64_cls(ctx, pattern2_0, expr0_0)?;
5149                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5150                         return Some(expr2_0);
5151                     }
5152                     &Opcode::Ctz => {
5153                         // Rule at src/isa/aarch64/lower.isle line 1043.
5154                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5155                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5156                         let expr2_0 = constructor_a64_clz(ctx, pattern2_0, expr1_0)?;
5157                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5158                         return Some(expr3_0);
5159                     }
5160                     _ => {}
5161                 }
5162             }
5163             _ => {}
5164         }
5165         if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) {
5166             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5167             match &pattern4_0 {
5168                 &InstructionData::Binary {
5169                     opcode: ref pattern5_0,
5170                     args: ref pattern5_1,
5171                 } => {
5172                     match pattern5_0 {
5173                         &Opcode::Iadd => {
5174                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5175                             // Rule at src/isa/aarch64/lower.isle line 79.
5176                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5177                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5178                             let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5179                             let expr3_0 = constructor_add_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5180                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5181                             return Some(expr4_0);
5182                         }
5183                         &Opcode::Isub => {
5184                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5185                             // Rule at src/isa/aarch64/lower.isle line 129.
5186                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5187                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5188                             let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5189                             let expr3_0 = constructor_sub_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5190                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5191                             return Some(expr4_0);
5192                         }
5193                         _ => {}
5194                     }
5195                 }
5196                 &InstructionData::FloatCompare {
5197                     opcode: ref pattern5_0,
5198                     args: ref pattern5_1,
5199                     cond: ref pattern5_2,
5200                 } => {
5201                     if let &Opcode::Fcmp = pattern5_0 {
5202                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5203                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5204                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5205                             if let &InstructionData::Unary {
5206                                 opcode: ref pattern10_0,
5207                                 arg: pattern10_1,
5208                             } = &pattern9_0
5209                             {
5210                                 if let &Opcode::Splat = pattern10_0 {
5211                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5212                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5213                                         match &pattern13_0 {
5214                                             &InstructionData::UnaryIeee32 {
5215                                                 opcode: ref pattern14_0,
5216                                                 imm: pattern14_1,
5217                                             } => {
5218                                                 if let &Opcode::F32const = pattern14_0 {
5219                                                     if let Some(pattern16_0) =
5220                                                         C::zero_value_f32(ctx, pattern14_1)
5221                                                     {
5222                                                         if let Some(pattern17_0) =
5223                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5224                                                         {
5225                                                             // Rule at src/isa/aarch64/lower.isle line 1151.
5226                                                             let expr0_0 =
5227                                                                 C::put_in_reg(ctx, pattern7_1);
5228                                                             let expr1_0 = constructor_vector_size(
5229                                                                 ctx, pattern2_0,
5230                                                             )?;
5231                                                             let expr2_0 =
5232                                                                 constructor_float_cmp_zero_swap(
5233                                                                     ctx,
5234                                                                     &pattern17_0,
5235                                                                     expr0_0,
5236                                                                     &expr1_0,
5237                                                                 )?;
5238                                                             let expr3_0 =
5239                                                                 C::value_reg(ctx, expr2_0);
5240                                                             let expr4_0 = C::output(ctx, expr3_0);
5241                                                             return Some(expr4_0);
5242                                                         }
5243                                                         if let Some(pattern17_0) =
5244                                                             C::fcmp_zero_cond_not_eq(
5245                                                                 ctx, pattern5_2,
5246                                                             )
5247                                                         {
5248                                                             // Rule at src/isa/aarch64/lower.isle line 1146.
5249                                                             let expr0_0 =
5250                                                                 C::put_in_reg(ctx, pattern7_1);
5251                                                             let expr1_0 = constructor_vector_size(
5252                                                                 ctx, pattern2_0,
5253                                                             )?;
5254                                                             let expr2_0 = constructor_fcmeq0(
5255                                                                 ctx, expr0_0, &expr1_0,
5256                                                             )?;
5257                                                             let expr3_0 = constructor_not(
5258                                                                 ctx, expr2_0, &expr1_0,
5259                                                             )?;
5260                                                             let expr4_0 =
5261                                                                 C::value_reg(ctx, expr3_0);
5262                                                             let expr5_0 = C::output(ctx, expr4_0);
5263                                                             return Some(expr5_0);
5264                                                         }
5265                                                     }
5266                                                 }
5267                                             }
5268                                             &InstructionData::UnaryIeee64 {
5269                                                 opcode: ref pattern14_0,
5270                                                 imm: pattern14_1,
5271                                             } => {
5272                                                 if let &Opcode::F64const = pattern14_0 {
5273                                                     if let Some(pattern16_0) =
5274                                                         C::zero_value_f64(ctx, pattern14_1)
5275                                                     {
5276                                                         if let Some(pattern17_0) =
5277                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5278                                                         {
5279                                                             // Rule at src/isa/aarch64/lower.isle line 1173.
5280                                                             let expr0_0 =
5281                                                                 C::put_in_reg(ctx, pattern7_1);
5282                                                             let expr1_0 = constructor_vector_size(
5283                                                                 ctx, pattern2_0,
5284                                                             )?;
5285                                                             let expr2_0 =
5286                                                                 constructor_float_cmp_zero_swap(
5287                                                                     ctx,
5288                                                                     &pattern17_0,
5289                                                                     expr0_0,
5290                                                                     &expr1_0,
5291                                                                 )?;
5292                                                             let expr3_0 =
5293                                                                 C::value_reg(ctx, expr2_0);
5294                                                             let expr4_0 = C::output(ctx, expr3_0);
5295                                                             return Some(expr4_0);
5296                                                         }
5297                                                         if let Some(pattern17_0) =
5298                                                             C::fcmp_zero_cond_not_eq(
5299                                                                 ctx, pattern5_2,
5300                                                             )
5301                                                         {
5302                                                             // Rule at src/isa/aarch64/lower.isle line 1168.
5303                                                             let expr0_0 =
5304                                                                 C::put_in_reg(ctx, pattern7_1);
5305                                                             let expr1_0 = constructor_vector_size(
5306                                                                 ctx, pattern2_0,
5307                                                             )?;
5308                                                             let expr2_0 = constructor_fcmeq0(
5309                                                                 ctx, expr0_0, &expr1_0,
5310                                                             )?;
5311                                                             let expr3_0 = constructor_not(
5312                                                                 ctx, expr2_0, &expr1_0,
5313                                                             )?;
5314                                                             let expr4_0 =
5315                                                                 C::value_reg(ctx, expr3_0);
5316                                                             let expr5_0 = C::output(ctx, expr4_0);
5317                                                             return Some(expr5_0);
5318                                                         }
5319                                                     }
5320                                                 }
5321                                             }
5322                                             _ => {}
5323                                         }
5324                                     }
5325                                 }
5326                             }
5327                         }
5328                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5329                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5330                             if let &InstructionData::Unary {
5331                                 opcode: ref pattern10_0,
5332                                 arg: pattern10_1,
5333                             } = &pattern9_0
5334                             {
5335                                 if let &Opcode::Splat = pattern10_0 {
5336                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5337                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5338                                         match &pattern13_0 {
5339                                             &InstructionData::UnaryIeee32 {
5340                                                 opcode: ref pattern14_0,
5341                                                 imm: pattern14_1,
5342                                             } => {
5343                                                 if let &Opcode::F32const = pattern14_0 {
5344                                                     if let Some(pattern16_0) =
5345                                                         C::zero_value_f32(ctx, pattern14_1)
5346                                                     {
5347                                                         if let Some(pattern17_0) =
5348                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5349                                                         {
5350                                                             // Rule at src/isa/aarch64/lower.isle line 1141.
5351                                                             let expr0_0 =
5352                                                                 C::put_in_reg(ctx, pattern7_0);
5353                                                             let expr1_0 = constructor_vector_size(
5354                                                                 ctx, pattern2_0,
5355                                                             )?;
5356                                                             let expr2_0 =
5357                                                                 constructor_float_cmp_zero(
5358                                                                     ctx,
5359                                                                     &pattern17_0,
5360                                                                     expr0_0,
5361                                                                     &expr1_0,
5362                                                                 )?;
5363                                                             let expr3_0 =
5364                                                                 C::value_reg(ctx, expr2_0);
5365                                                             let expr4_0 = C::output(ctx, expr3_0);
5366                                                             return Some(expr4_0);
5367                                                         }
5368                                                         if let Some(pattern17_0) =
5369                                                             C::fcmp_zero_cond_not_eq(
5370                                                                 ctx, pattern5_2,
5371                                                             )
5372                                                         {
5373                                                             // Rule at src/isa/aarch64/lower.isle line 1136.
5374                                                             let expr0_0 =
5375                                                                 C::put_in_reg(ctx, pattern7_0);
5376                                                             let expr1_0 = constructor_vector_size(
5377                                                                 ctx, pattern2_0,
5378                                                             )?;
5379                                                             let expr2_0 = constructor_fcmeq0(
5380                                                                 ctx, expr0_0, &expr1_0,
5381                                                             )?;
5382                                                             let expr3_0 = constructor_not(
5383                                                                 ctx, expr2_0, &expr1_0,
5384                                                             )?;
5385                                                             let expr4_0 =
5386                                                                 C::value_reg(ctx, expr3_0);
5387                                                             let expr5_0 = C::output(ctx, expr4_0);
5388                                                             return Some(expr5_0);
5389                                                         }
5390                                                     }
5391                                                 }
5392                                             }
5393                                             &InstructionData::UnaryIeee64 {
5394                                                 opcode: ref pattern14_0,
5395                                                 imm: pattern14_1,
5396                                             } => {
5397                                                 if let &Opcode::F64const = pattern14_0 {
5398                                                     if let Some(pattern16_0) =
5399                                                         C::zero_value_f64(ctx, pattern14_1)
5400                                                     {
5401                                                         if let Some(pattern17_0) =
5402                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5403                                                         {
5404                                                             // Rule at src/isa/aarch64/lower.isle line 1163.
5405                                                             let expr0_0 =
5406                                                                 C::put_in_reg(ctx, pattern7_0);
5407                                                             let expr1_0 = constructor_vector_size(
5408                                                                 ctx, pattern2_0,
5409                                                             )?;
5410                                                             let expr2_0 =
5411                                                                 constructor_float_cmp_zero(
5412                                                                     ctx,
5413                                                                     &pattern17_0,
5414                                                                     expr0_0,
5415                                                                     &expr1_0,
5416                                                                 )?;
5417                                                             let expr3_0 =
5418                                                                 C::value_reg(ctx, expr2_0);
5419                                                             let expr4_0 = C::output(ctx, expr3_0);
5420                                                             return Some(expr4_0);
5421                                                         }
5422                                                         if let Some(pattern17_0) =
5423                                                             C::fcmp_zero_cond_not_eq(
5424                                                                 ctx, pattern5_2,
5425                                                             )
5426                                                         {
5427                                                             // Rule at src/isa/aarch64/lower.isle line 1158.
5428                                                             let expr0_0 =
5429                                                                 C::put_in_reg(ctx, pattern7_0);
5430                                                             let expr1_0 = constructor_vector_size(
5431                                                                 ctx, pattern2_0,
5432                                                             )?;
5433                                                             let expr2_0 = constructor_fcmeq0(
5434                                                                 ctx, expr0_0, &expr1_0,
5435                                                             )?;
5436                                                             let expr3_0 = constructor_not(
5437                                                                 ctx, expr2_0, &expr1_0,
5438                                                             )?;
5439                                                             let expr4_0 =
5440                                                                 C::value_reg(ctx, expr3_0);
5441                                                             let expr5_0 = C::output(ctx, expr4_0);
5442                                                             return Some(expr5_0);
5443                                                         }
5444                                                     }
5445                                                 }
5446                                             }
5447                                             _ => {}
5448                                         }
5449                                     }
5450                                 }
5451                             }
5452                         }
5453                     }
5454                 }
5455                 &InstructionData::IntCompare {
5456                     opcode: ref pattern5_0,
5457                     args: ref pattern5_1,
5458                     cond: ref pattern5_2,
5459                 } => {
5460                     if let &Opcode::Icmp = pattern5_0 {
5461                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5462                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5463                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5464                             if let &InstructionData::Unary {
5465                                 opcode: ref pattern10_0,
5466                                 arg: pattern10_1,
5467                             } = &pattern9_0
5468                             {
5469                                 if let &Opcode::Splat = pattern10_0 {
5470                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5471                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5472                                         if let &InstructionData::UnaryImm {
5473                                             opcode: ref pattern14_0,
5474                                             imm: pattern14_1,
5475                                         } = &pattern13_0
5476                                         {
5477                                             if let &Opcode::Iconst = pattern14_0 {
5478                                                 if let Some(pattern16_0) =
5479                                                     C::zero_value(ctx, pattern14_1)
5480                                                 {
5481                                                     if let Some(pattern17_0) =
5482                                                         C::icmp_zero_cond(ctx, pattern5_2)
5483                                                     {
5484                                                         // Rule at src/isa/aarch64/lower.isle line 1195.
5485                                                         let expr0_0 =
5486                                                             C::put_in_reg(ctx, pattern7_1);
5487                                                         let expr1_0 = constructor_vector_size(
5488                                                             ctx, pattern2_0,
5489                                                         )?;
5490                                                         let expr2_0 =
5491                                                             constructor_int_cmp_zero_swap(
5492                                                                 ctx,
5493                                                                 &pattern17_0,
5494                                                                 expr0_0,
5495                                                                 &expr1_0,
5496                                                             )?;
5497                                                         let expr3_0 = C::value_reg(ctx, expr2_0);
5498                                                         let expr4_0 = C::output(ctx, expr3_0);
5499                                                         return Some(expr4_0);
5500                                                     }
5501                                                     if let Some(pattern17_0) =
5502                                                         C::icmp_zero_cond_not_eq(ctx, pattern5_2)
5503                                                     {
5504                                                         // Rule at src/isa/aarch64/lower.isle line 1190.
5505                                                         let expr0_0 =
5506                                                             C::put_in_reg(ctx, pattern7_1);
5507                                                         let expr1_0 = constructor_vector_size(
5508                                                             ctx, pattern2_0,
5509                                                         )?;
5510                                                         let expr2_0 = constructor_cmeq0(
5511                                                             ctx, expr0_0, &expr1_0,
5512                                                         )?;
5513                                                         let expr3_0 = constructor_not(
5514                                                             ctx, expr2_0, &expr1_0,
5515                                                         )?;
5516                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5517                                                         let expr5_0 = C::output(ctx, expr4_0);
5518                                                         return Some(expr5_0);
5519                                                     }
5520                                                 }
5521                                             }
5522                                         }
5523                                     }
5524                                 }
5525                             }
5526                         }
5527                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5528                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5529                             if let &InstructionData::Unary {
5530                                 opcode: ref pattern10_0,
5531                                 arg: pattern10_1,
5532                             } = &pattern9_0
5533                             {
5534                                 if let &Opcode::Splat = pattern10_0 {
5535                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5536                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5537                                         if let &InstructionData::UnaryImm {
5538                                             opcode: ref pattern14_0,
5539                                             imm: pattern14_1,
5540                                         } = &pattern13_0
5541                                         {
5542                                             if let &Opcode::Iconst = pattern14_0 {
5543                                                 if let Some(pattern16_0) =
5544                                                     C::zero_value(ctx, pattern14_1)
5545                                                 {
5546                                                     if let Some(pattern17_0) =
5547                                                         C::icmp_zero_cond(ctx, pattern5_2)
5548                                                     {
5549                                                         // Rule at src/isa/aarch64/lower.isle line 1185.
5550                                                         let expr0_0 =
5551                                                             C::put_in_reg(ctx, pattern7_0);
5552                                                         let expr1_0 = constructor_vector_size(
5553                                                             ctx, pattern2_0,
5554                                                         )?;
5555                                                         let expr2_0 = constructor_int_cmp_zero(
5556                                                             ctx,
5557                                                             &pattern17_0,
5558                                                             expr0_0,
5559                                                             &expr1_0,
5560                                                         )?;
5561                                                         let expr3_0 = C::value_reg(ctx, expr2_0);
5562                                                         let expr4_0 = C::output(ctx, expr3_0);
5563                                                         return Some(expr4_0);
5564                                                     }
5565                                                     if let Some(pattern17_0) =
5566                                                         C::icmp_zero_cond_not_eq(ctx, pattern5_2)
5567                                                     {
5568                                                         // Rule at src/isa/aarch64/lower.isle line 1180.
5569                                                         let expr0_0 =
5570                                                             C::put_in_reg(ctx, pattern7_0);
5571                                                         let expr1_0 = constructor_vector_size(
5572                                                             ctx, pattern2_0,
5573                                                         )?;
5574                                                         let expr2_0 = constructor_cmeq0(
5575                                                             ctx, expr0_0, &expr1_0,
5576                                                         )?;
5577                                                         let expr3_0 = constructor_not(
5578                                                             ctx, expr2_0, &expr1_0,
5579                                                         )?;
5580                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5581                                                         let expr5_0 = C::output(ctx, expr4_0);
5582                                                         return Some(expr5_0);
5583                                                     }
5584                                                 }
5585                                             }
5586                                         }
5587                                     }
5588                                 }
5589                             }
5590                         }
5591                     }
5592                 }
5593                 _ => {}
5594             }
5595         }
5596         if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
5597             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5598             if let &InstructionData::Binary {
5599                 opcode: ref pattern5_0,
5600                 args: ref pattern5_1,
5601             } = &pattern4_0
5602             {
5603                 match pattern5_0 {
5604                     &Opcode::Rotl => {
5605                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5606                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5607                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5608                             if let &InstructionData::UnaryImm {
5609                                 opcode: ref pattern10_0,
5610                                 imm: pattern10_1,
5611                             } = &pattern9_0
5612                             {
5613                                 if let &Opcode::Iconst = pattern10_0 {
5614                                     let closure12 = || {
5615                                         return Some(pattern3_0);
5616                                     };
5617                                     if let Some(pattern12_0) = closure12() {
5618                                         if let Some(pattern13_0) =
5619                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5620                                         {
5621                                             // Rule at src/isa/aarch64/lower.isle line 849.
5622                                             let expr0_0 =
5623                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5624                                             let expr1_0 =
5625                                                 C::negate_imm_shift(ctx, pattern3_0, pattern13_0);
5626                                             let expr2_0 = constructor_small_rotr_imm(
5627                                                 ctx, pattern3_0, expr0_0, expr1_0,
5628                                             )?;
5629                                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5630                                             return Some(expr3_0);
5631                                         }
5632                                     }
5633                                 }
5634                             }
5635                         }
5636                         // Rule at src/isa/aarch64/lower.isle line 844.
5637                         let expr0_0: Type = I32;
5638                         let expr1_0 = C::zero_reg(ctx);
5639                         let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5640                         let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
5641                         let expr4_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5642                         let expr5_0 = constructor_small_rotr(ctx, pattern3_0, expr4_0, expr3_0)?;
5643                         let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
5644                         return Some(expr6_0);
5645                     }
5646                     &Opcode::Rotr => {
5647                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5648                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5649                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5650                             if let &InstructionData::UnaryImm {
5651                                 opcode: ref pattern10_0,
5652                                 imm: pattern10_1,
5653                             } = &pattern9_0
5654                             {
5655                                 if let &Opcode::Iconst = pattern10_0 {
5656                                     let closure12 = || {
5657                                         return Some(pattern3_0);
5658                                     };
5659                                     if let Some(pattern12_0) = closure12() {
5660                                         if let Some(pattern13_0) =
5661                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5662                                         {
5663                                             // Rule at src/isa/aarch64/lower.isle line 909.
5664                                             let expr0_0 =
5665                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5666                                             let expr1_0 = constructor_small_rotr_imm(
5667                                                 ctx,
5668                                                 pattern3_0,
5669                                                 expr0_0,
5670                                                 pattern13_0,
5671                                             )?;
5672                                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5673                                             return Some(expr2_0);
5674                                         }
5675                                     }
5676                                 }
5677                             }
5678                         }
5679                         // Rule at src/isa/aarch64/lower.isle line 897.
5680                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5681                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5682                         let expr2_0 = constructor_small_rotr(ctx, pattern3_0, expr0_0, expr1_0)?;
5683                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5684                         return Some(expr3_0);
5685                     }
5686                     _ => {}
5687                 }
5688             }
5689         }
5690         if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
5691             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5692             if let &InstructionData::Binary {
5693                 opcode: ref pattern5_0,
5694                 args: ref pattern5_1,
5695             } = &pattern4_0
5696             {
5697                 match pattern5_0 {
5698                     &Opcode::Umulhi => {
5699                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5700                         // Rule at src/isa/aarch64/lower.isle line 374.
5701                         let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5702                         let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?;
5703                         let expr2_0: Type = I64;
5704                         let expr3_0 = C::zero_reg(ctx);
5705                         let expr4_0 = constructor_madd(ctx, expr2_0, expr0_0, expr1_0, expr3_0)?;
5706                         let expr5_0: Type = I64;
5707                         let expr6_0 = C::ty_bits(ctx, pattern3_0);
5708                         let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
5709                         let expr8_0 = constructor_lsr_imm(ctx, expr5_0, expr4_0, expr7_0)?;
5710                         let expr9_0 = C::value_reg(ctx, expr8_0);
5711                         let expr10_0 = C::output(ctx, expr9_0);
5712                         return Some(expr10_0);
5713                     }
5714                     &Opcode::Smulhi => {
5715                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5716                         // Rule at src/isa/aarch64/lower.isle line 362.
5717                         let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5718                         let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?;
5719                         let expr2_0: Type = I64;
5720                         let expr3_0 = C::zero_reg(ctx);
5721                         let expr4_0 = constructor_madd(ctx, expr2_0, expr0_0, expr1_0, expr3_0)?;
5722                         let expr5_0: Type = I64;
5723                         let expr6_0 = C::ty_bits(ctx, pattern3_0);
5724                         let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
5725                         let expr8_0 = constructor_asr_imm(ctx, expr5_0, expr4_0, expr7_0)?;
5726                         let expr9_0 = constructor_output_reg(ctx, expr8_0)?;
5727                         return Some(expr9_0);
5728                     }
5729                     &Opcode::Band => {
5730                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5731                         // Rule at src/isa/aarch64/lower.isle line 589.
5732                         let expr0_0 = ALUOp::And;
5733                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5734                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5735                         )?;
5736                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5737                         return Some(expr2_0);
5738                     }
5739                     &Opcode::Bor => {
5740                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5741                         // Rule at src/isa/aarch64/lower.isle line 602.
5742                         let expr0_0 = ALUOp::Orr;
5743                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5744                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5745                         )?;
5746                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5747                         return Some(expr2_0);
5748                     }
5749                     &Opcode::Bxor => {
5750                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5751                         // Rule at src/isa/aarch64/lower.isle line 615.
5752                         let expr0_0 = ALUOp::Eor;
5753                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5754                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5755                         )?;
5756                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5757                         return Some(expr2_0);
5758                     }
5759                     &Opcode::BandNot => {
5760                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5761                         // Rule at src/isa/aarch64/lower.isle line 628.
5762                         let expr0_0 = ALUOp::AndNot;
5763                         let expr1_0 = constructor_alu_rs_imm_logic(
5764                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5765                         )?;
5766                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5767                         return Some(expr2_0);
5768                     }
5769                     &Opcode::BorNot => {
5770                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5771                         // Rule at src/isa/aarch64/lower.isle line 641.
5772                         let expr0_0 = ALUOp::OrrNot;
5773                         let expr1_0 = constructor_alu_rs_imm_logic(
5774                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5775                         )?;
5776                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5777                         return Some(expr2_0);
5778                     }
5779                     &Opcode::BxorNot => {
5780                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5781                         // Rule at src/isa/aarch64/lower.isle line 651.
5782                         let expr0_0 = ALUOp::EorNot;
5783                         let expr1_0: Type = I32;
5784                         let expr2_0 = constructor_alu_rs_imm_logic(
5785                             ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
5786                         )?;
5787                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5788                         return Some(expr3_0);
5789                     }
5790                     &Opcode::Ishl => {
5791                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5792                         // Rule at src/isa/aarch64/lower.isle line 662.
5793                         let expr0_0 = ALUOp::Lsl;
5794                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
5795                         let expr2_0 =
5796                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5797                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5798                         return Some(expr3_0);
5799                     }
5800                     &Opcode::Ushr => {
5801                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5802                         // Rule at src/isa/aarch64/lower.isle line 746.
5803                         let expr0_0 = ALUOp::Lsr;
5804                         let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5805                         let expr2_0 =
5806                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5807                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5808                         return Some(expr3_0);
5809                     }
5810                     &Opcode::Sshr => {
5811                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5812                         // Rule at src/isa/aarch64/lower.isle line 793.
5813                         let expr0_0 = ALUOp::Asr;
5814                         let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
5815                         let expr2_0 =
5816                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5817                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5818                         return Some(expr3_0);
5819                     }
5820                     _ => {}
5821                 }
5822             }
5823         }
5824         if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
5825             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5826             match &pattern4_0 {
5827                 &InstructionData::Binary {
5828                     opcode: ref pattern5_0,
5829                     args: ref pattern5_1,
5830                 } => {
5831                     match pattern5_0 {
5832                         &Opcode::Iadd => {
5833                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5834                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5835                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5836                                 match &pattern9_0 {
5837                                     &InstructionData::UnaryImm {
5838                                         opcode: ref pattern10_0,
5839                                         imm: pattern10_1,
5840                                     } => {
5841                                         if let &Opcode::Iconst = pattern10_0 {
5842                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5843                                             if let Some(pattern13_0) =
5844                                                 C::imm12_from_u64(ctx, pattern12_0)
5845                                             {
5846                                                 // Rule at src/isa/aarch64/lower.isle line 37.
5847                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5848                                                 let expr1_0 = constructor_add_imm(
5849                                                     ctx,
5850                                                     pattern3_0,
5851                                                     expr0_0,
5852                                                     pattern13_0,
5853                                                 )?;
5854                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5855                                                 return Some(expr2_0);
5856                                             }
5857                                             if let Some(pattern13_0) =
5858                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5859                                             {
5860                                                 // Rule at src/isa/aarch64/lower.isle line 45.
5861                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5862                                                 let expr1_0 = constructor_sub_imm(
5863                                                     ctx,
5864                                                     pattern3_0,
5865                                                     expr0_0,
5866                                                     pattern13_0,
5867                                                 )?;
5868                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5869                                                 return Some(expr2_0);
5870                                             }
5871                                         }
5872                                     }
5873                                     &InstructionData::Binary {
5874                                         opcode: ref pattern10_0,
5875                                         args: ref pattern10_1,
5876                                     } => {
5877                                         match pattern10_0 {
5878                                             &Opcode::Imul => {
5879                                                 let (pattern12_0, pattern12_1) =
5880                                                     C::unpack_value_array_2(ctx, pattern10_1);
5881                                                 // Rule at src/isa/aarch64/lower.isle line 70.
5882                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5883                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5884                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5885                                                 let expr3_0 = constructor_madd(
5886                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5887                                                 )?;
5888                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5889                                                 return Some(expr4_0);
5890                                             }
5891                                             &Opcode::Ishl => {
5892                                                 let (pattern12_0, pattern12_1) =
5893                                                     C::unpack_value_array_2(ctx, pattern10_1);
5894                                                 if let Some(pattern13_0) =
5895                                                     C::def_inst(ctx, pattern12_1)
5896                                                 {
5897                                                     let pattern14_0 =
5898                                                         C::inst_data(ctx, pattern13_0);
5899                                                     if let &InstructionData::UnaryImm {
5900                                                         opcode: ref pattern15_0,
5901                                                         imm: pattern15_1,
5902                                                     } = &pattern14_0
5903                                                     {
5904                                                         if let &Opcode::Iconst = pattern15_0 {
5905                                                             let closure17 = || {
5906                                                                 return Some(pattern3_0);
5907                                                             };
5908                                                             if let Some(pattern17_0) = closure17() {
5909                                                                 if let Some(pattern18_0) =
5910                                                                     C::lshl_from_imm64(
5911                                                                         ctx,
5912                                                                         pattern15_1,
5913                                                                         pattern17_0,
5914                                                                     )
5915                                                                 {
5916                                                                     // Rule at src/isa/aarch64/lower.isle line 62.
5917                                                                     let expr0_0 = C::put_in_reg(
5918                                                                         ctx, pattern7_1,
5919                                                                     );
5920                                                                     let expr1_0 = C::put_in_reg(
5921                                                                         ctx,
5922                                                                         pattern12_0,
5923                                                                     );
5924                                                                     let expr2_0 =
5925                                                                         constructor_add_shift(
5926                                                                             ctx,
5927                                                                             pattern3_0,
5928                                                                             expr0_0,
5929                                                                             expr1_0,
5930                                                                             pattern18_0,
5931                                                                         )?;
5932                                                                     let expr3_0 =
5933                                                                         constructor_output_reg(
5934                                                                             ctx, expr2_0,
5935                                                                         )?;
5936                                                                     return Some(expr3_0);
5937                                                                 }
5938                                                             }
5939                                                         }
5940                                                     }
5941                                                 }
5942                                             }
5943                                             _ => {}
5944                                         }
5945                                     }
5946                                     _ => {}
5947                                 }
5948                             }
5949                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0)
5950                             {
5951                                 // Rule at src/isa/aarch64/lower.isle line 53.
5952                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5953                                 let expr1_0 =
5954                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5955                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5956                                 return Some(expr2_0);
5957                             }
5958                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5959                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5960                                 match &pattern9_0 {
5961                                     &InstructionData::UnaryImm {
5962                                         opcode: ref pattern10_0,
5963                                         imm: pattern10_1,
5964                                     } => {
5965                                         if let &Opcode::Iconst = pattern10_0 {
5966                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5967                                             if let Some(pattern13_0) =
5968                                                 C::imm12_from_u64(ctx, pattern12_0)
5969                                             {
5970                                                 // Rule at src/isa/aarch64/lower.isle line 34.
5971                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5972                                                 let expr1_0 = constructor_add_imm(
5973                                                     ctx,
5974                                                     pattern3_0,
5975                                                     expr0_0,
5976                                                     pattern13_0,
5977                                                 )?;
5978                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5979                                                 return Some(expr2_0);
5980                                             }
5981                                             if let Some(pattern13_0) =
5982                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5983                                             {
5984                                                 // Rule at src/isa/aarch64/lower.isle line 42.
5985                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5986                                                 let expr1_0 = constructor_sub_imm(
5987                                                     ctx,
5988                                                     pattern3_0,
5989                                                     expr0_0,
5990                                                     pattern13_0,
5991                                                 )?;
5992                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5993                                                 return Some(expr2_0);
5994                                             }
5995                                         }
5996                                     }
5997                                     &InstructionData::Binary {
5998                                         opcode: ref pattern10_0,
5999                                         args: ref pattern10_1,
6000                                     } => {
6001                                         match pattern10_0 {
6002                                             &Opcode::Imul => {
6003                                                 let (pattern12_0, pattern12_1) =
6004                                                     C::unpack_value_array_2(ctx, pattern10_1);
6005                                                 // Rule at src/isa/aarch64/lower.isle line 67.
6006                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
6007                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
6008                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
6009                                                 let expr3_0 = constructor_madd(
6010                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
6011                                                 )?;
6012                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6013                                                 return Some(expr4_0);
6014                                             }
6015                                             &Opcode::Ishl => {
6016                                                 let (pattern12_0, pattern12_1) =
6017                                                     C::unpack_value_array_2(ctx, pattern10_1);
6018                                                 if let Some(pattern13_0) =
6019                                                     C::def_inst(ctx, pattern12_1)
6020                                                 {
6021                                                     let pattern14_0 =
6022                                                         C::inst_data(ctx, pattern13_0);
6023                                                     if let &InstructionData::UnaryImm {
6024                                                         opcode: ref pattern15_0,
6025                                                         imm: pattern15_1,
6026                                                     } = &pattern14_0
6027                                                     {
6028                                                         if let &Opcode::Iconst = pattern15_0 {
6029                                                             let closure17 = || {
6030                                                                 return Some(pattern3_0);
6031                                                             };
6032                                                             if let Some(pattern17_0) = closure17() {
6033                                                                 if let Some(pattern18_0) =
6034                                                                     C::lshl_from_imm64(
6035                                                                         ctx,
6036                                                                         pattern15_1,
6037                                                                         pattern17_0,
6038                                                                     )
6039                                                                 {
6040                                                                     // Rule at src/isa/aarch64/lower.isle line 58.
6041                                                                     let expr0_0 = C::put_in_reg(
6042                                                                         ctx, pattern7_0,
6043                                                                     );
6044                                                                     let expr1_0 = C::put_in_reg(
6045                                                                         ctx,
6046                                                                         pattern12_0,
6047                                                                     );
6048                                                                     let expr2_0 =
6049                                                                         constructor_add_shift(
6050                                                                             ctx,
6051                                                                             pattern3_0,
6052                                                                             expr0_0,
6053                                                                             expr1_0,
6054                                                                             pattern18_0,
6055                                                                         )?;
6056                                                                     let expr3_0 =
6057                                                                         constructor_output_reg(
6058                                                                             ctx, expr2_0,
6059                                                                         )?;
6060                                                                     return Some(expr3_0);
6061                                                                 }
6062                                                             }
6063                                                         }
6064                                                     }
6065                                                 }
6066                                             }
6067                                             _ => {}
6068                                         }
6069                                     }
6070                                     _ => {}
6071                                 }
6072                             }
6073                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
6074                             {
6075                                 // Rule at src/isa/aarch64/lower.isle line 50.
6076                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6077                                 let expr1_0 =
6078                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6079                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6080                                 return Some(expr2_0);
6081                             }
6082                             // Rule at src/isa/aarch64/lower.isle line 30.
6083                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6084                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6085                             let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, expr1_0)?;
6086                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6087                             return Some(expr3_0);
6088                         }
6089                         &Opcode::Isub => {
6090                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6091                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6092                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6093                                 match &pattern9_0 {
6094                                     &InstructionData::UnaryImm {
6095                                         opcode: ref pattern10_0,
6096                                         imm: pattern10_1,
6097                                     } => {
6098                                         if let &Opcode::Iconst = pattern10_0 {
6099                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
6100                                             if let Some(pattern13_0) =
6101                                                 C::imm12_from_u64(ctx, pattern12_0)
6102                                             {
6103                                                 // Rule at src/isa/aarch64/lower.isle line 109.
6104                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6105                                                 let expr1_0 = constructor_sub_imm(
6106                                                     ctx,
6107                                                     pattern3_0,
6108                                                     expr0_0,
6109                                                     pattern13_0,
6110                                                 )?;
6111                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6112                                                 return Some(expr2_0);
6113                                             }
6114                                             if let Some(pattern13_0) =
6115                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
6116                                             {
6117                                                 // Rule at src/isa/aarch64/lower.isle line 114.
6118                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6119                                                 let expr1_0 = constructor_add_imm(
6120                                                     ctx,
6121                                                     pattern3_0,
6122                                                     expr0_0,
6123                                                     pattern13_0,
6124                                                 )?;
6125                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6126                                                 return Some(expr2_0);
6127                                             }
6128                                         }
6129                                     }
6130                                     &InstructionData::Binary {
6131                                         opcode: ref pattern10_0,
6132                                         args: ref pattern10_1,
6133                                     } => {
6134                                         match pattern10_0 {
6135                                             &Opcode::Imul => {
6136                                                 let (pattern12_0, pattern12_1) =
6137                                                     C::unpack_value_array_2(ctx, pattern10_1);
6138                                                 // Rule at src/isa/aarch64/lower.isle line 74.
6139                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
6140                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
6141                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
6142                                                 let expr3_0 = constructor_msub(
6143                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
6144                                                 )?;
6145                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6146                                                 return Some(expr4_0);
6147                                             }
6148                                             &Opcode::Ishl => {
6149                                                 let (pattern12_0, pattern12_1) =
6150                                                     C::unpack_value_array_2(ctx, pattern10_1);
6151                                                 if let Some(pattern13_0) =
6152                                                     C::def_inst(ctx, pattern12_1)
6153                                                 {
6154                                                     let pattern14_0 =
6155                                                         C::inst_data(ctx, pattern13_0);
6156                                                     if let &InstructionData::UnaryImm {
6157                                                         opcode: ref pattern15_0,
6158                                                         imm: pattern15_1,
6159                                                     } = &pattern14_0
6160                                                     {
6161                                                         if let &Opcode::Iconst = pattern15_0 {
6162                                                             let closure17 = || {
6163                                                                 return Some(pattern3_0);
6164                                                             };
6165                                                             if let Some(pattern17_0) = closure17() {
6166                                                                 if let Some(pattern18_0) =
6167                                                                     C::lshl_from_imm64(
6168                                                                         ctx,
6169                                                                         pattern15_1,
6170                                                                         pattern17_0,
6171                                                                     )
6172                                                                 {
6173                                                                     // Rule at src/isa/aarch64/lower.isle line 124.
6174                                                                     let expr0_0 = C::put_in_reg(
6175                                                                         ctx, pattern7_0,
6176                                                                     );
6177                                                                     let expr1_0 = C::put_in_reg(
6178                                                                         ctx,
6179                                                                         pattern12_0,
6180                                                                     );
6181                                                                     let expr2_0 =
6182                                                                         constructor_sub_shift(
6183                                                                             ctx,
6184                                                                             pattern3_0,
6185                                                                             expr0_0,
6186                                                                             expr1_0,
6187                                                                             pattern18_0,
6188                                                                         )?;
6189                                                                     let expr3_0 =
6190                                                                         constructor_output_reg(
6191                                                                             ctx, expr2_0,
6192                                                                         )?;
6193                                                                     return Some(expr3_0);
6194                                                                 }
6195                                                             }
6196                                                         }
6197                                                     }
6198                                                 }
6199                                             }
6200                                             _ => {}
6201                                         }
6202                                     }
6203                                     _ => {}
6204                                 }
6205                             }
6206                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
6207                             {
6208                                 // Rule at src/isa/aarch64/lower.isle line 119.
6209                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6210                                 let expr1_0 =
6211                                     constructor_sub_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6212                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6213                                 return Some(expr2_0);
6214                             }
6215                             // Rule at src/isa/aarch64/lower.isle line 105.
6216                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6217                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6218                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
6219                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6220                             return Some(expr3_0);
6221                         }
6222                         &Opcode::Imul => {
6223                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6224                             // Rule at src/isa/aarch64/lower.isle line 183.
6225                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6226                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6227                             let expr2_0 = C::zero_reg(ctx);
6228                             let expr3_0 =
6229                                 constructor_madd(ctx, pattern3_0, expr0_0, expr1_0, expr2_0)?;
6230                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6231                             return Some(expr4_0);
6232                         }
6233                         &Opcode::Udiv => {
6234                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6235                             // Rule at src/isa/aarch64/lower.isle line 390.
6236                             let expr0_0: Type = I64;
6237                             let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
6238                             let expr2_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
6239                             let expr3_0 = constructor_a64_udiv(ctx, expr0_0, expr1_0, expr2_0)?;
6240                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6241                             return Some(expr4_0);
6242                         }
6243                         &Opcode::Sdiv => {
6244                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6245                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6246                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6247                                 if let &InstructionData::UnaryImm {
6248                                     opcode: ref pattern10_0,
6249                                     imm: pattern10_1,
6250                                 } = &pattern9_0
6251                                 {
6252                                     if let &Opcode::Iconst = pattern10_0 {
6253                                         if let Some(pattern12_0) =
6254                                             C::safe_divisor_from_imm64(ctx, pattern10_1)
6255                                         {
6256                                             // Rule at src/isa/aarch64/lower.isle line 436.
6257                                             let expr0_0: Type = I64;
6258                                             let expr1_0 =
6259                                                 constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6260                                             let expr2_0 =
6261                                                 constructor_imm(ctx, pattern3_0, pattern12_0)?;
6262                                             let expr3_0 = constructor_a64_sdiv(
6263                                                 ctx, expr0_0, expr1_0, expr2_0,
6264                                             )?;
6265                                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6266                                             return Some(expr4_0);
6267                                         }
6268                                     }
6269                                 }
6270                             }
6271                             // Rule at src/isa/aarch64/lower.isle line 423.
6272                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6273                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
6274                             let expr2_0 = constructor_trap_if_div_overflow(
6275                                 ctx, pattern3_0, expr0_0, expr1_0,
6276                             )?;
6277                             let expr3_0: Type = I64;
6278                             let expr4_0 = constructor_a64_sdiv(ctx, expr3_0, expr2_0, expr1_0)?;
6279                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6280                             return Some(expr5_0);
6281                         }
6282                         &Opcode::Urem => {
6283                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6284                             // Rule at src/isa/aarch64/lower.isle line 464.
6285                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
6286                             let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
6287                             let expr2_0: Type = I64;
6288                             let expr3_0 = constructor_a64_udiv(ctx, expr2_0, expr0_0, expr1_0)?;
6289                             let expr4_0: Type = I64;
6290                             let expr5_0 =
6291                                 constructor_msub(ctx, expr4_0, expr3_0, expr1_0, expr0_0)?;
6292                             let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
6293                             return Some(expr6_0);
6294                         }
6295                         &Opcode::Srem => {
6296                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6297                             // Rule at src/isa/aarch64/lower.isle line 471.
6298                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6299                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
6300                             let expr2_0: Type = I64;
6301                             let expr3_0 = constructor_a64_sdiv(ctx, expr2_0, expr0_0, expr1_0)?;
6302                             let expr4_0: Type = I64;
6303                             let expr5_0 =
6304                                 constructor_msub(ctx, expr4_0, expr3_0, expr1_0, expr0_0)?;
6305                             let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
6306                             return Some(expr6_0);
6307                         }
6308                         _ => {}
6309                     }
6310                 }
6311                 &InstructionData::Unary {
6312                     opcode: ref pattern5_0,
6313                     arg: pattern5_1,
6314                 } => {
6315                     match pattern5_0 {
6316                         &Opcode::Ineg => {
6317                             // Rule at src/isa/aarch64/lower.isle line 173.
6318                             let expr0_0 = C::zero_reg(ctx);
6319                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6320                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
6321                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6322                             return Some(expr3_0);
6323                         }
6324                         &Opcode::Bnot => {
6325                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6326                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6327                                 if let &InstructionData::Binary {
6328                                     opcode: ref pattern9_0,
6329                                     args: ref pattern9_1,
6330                                 } = &pattern8_0
6331                                 {
6332                                     if let &Opcode::Ishl = pattern9_0 {
6333                                         let (pattern11_0, pattern11_1) =
6334                                             C::unpack_value_array_2(ctx, pattern9_1);
6335                                         if let Some(pattern12_0) = C::def_inst(ctx, pattern11_1) {
6336                                             let pattern13_0 = C::inst_data(ctx, pattern12_0);
6337                                             if let &InstructionData::UnaryImm {
6338                                                 opcode: ref pattern14_0,
6339                                                 imm: pattern14_1,
6340                                             } = &pattern13_0
6341                                             {
6342                                                 if let &Opcode::Iconst = pattern14_0 {
6343                                                     let closure16 = || {
6344                                                         return Some(pattern3_0);
6345                                                     };
6346                                                     if let Some(pattern16_0) = closure16() {
6347                                                         if let Some(pattern17_0) =
6348                                                             C::lshl_from_imm64(
6349                                                                 ctx,
6350                                                                 pattern14_1,
6351                                                                 pattern16_0,
6352                                                             )
6353                                                         {
6354                                                             // Rule at src/isa/aarch64/lower.isle line 570.
6355                                                             let expr0_0 = C::zero_reg(ctx);
6356                                                             let expr1_0 =
6357                                                                 C::put_in_reg(ctx, pattern11_0);
6358                                                             let expr2_0 =
6359                                                                 constructor_orr_not_shift(
6360                                                                     ctx,
6361                                                                     pattern3_0,
6362                                                                     expr0_0,
6363                                                                     expr1_0,
6364                                                                     pattern17_0,
6365                                                                 )?;
6366                                                             let expr3_0 = constructor_output_reg(
6367                                                                 ctx, expr2_0,
6368                                                             )?;
6369                                                             return Some(expr3_0);
6370                                                         }
6371                                                     }
6372                                                 }
6373                                             }
6374                                         }
6375                                     }
6376                                 }
6377                             }
6378                             // Rule at src/isa/aarch64/lower.isle line 565.
6379                             let expr0_0 = C::zero_reg(ctx);
6380                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6381                             let expr2_0 = constructor_orr_not(ctx, pattern3_0, expr0_0, expr1_0)?;
6382                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6383                             return Some(expr3_0);
6384                         }
6385                         &Opcode::Uextend => {
6386                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6387                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6388                                 if let &InstructionData::BinaryImm8 {
6389                                     opcode: ref pattern9_0,
6390                                     arg: pattern9_1,
6391                                     imm: pattern9_2,
6392                                 } = &pattern8_0
6393                                 {
6394                                     if let &Opcode::Extractlane = pattern9_0 {
6395                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6396                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6397                                         // Rule at src/isa/aarch64/lower.isle line 487.
6398                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6399                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6400                                         let expr2_0 = constructor_mov_from_vec(
6401                                             ctx,
6402                                             expr0_0,
6403                                             pattern12_0,
6404                                             &expr1_0,
6405                                         )?;
6406                                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6407                                         return Some(expr3_0);
6408                                     }
6409                                 }
6410                             }
6411                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6412                             if let Some(pattern8_0) = C::sinkable_atomic_load(ctx, pattern5_1) {
6413                                 // Rule at src/isa/aarch64/lower.isle line 494.
6414                                 let expr0_0 = C::sink_atomic_load(ctx, &pattern8_0);
6415                                 let expr1_0 = constructor_load_acquire(ctx, pattern7_0, expr0_0)?;
6416                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6417                                 return Some(expr2_0);
6418                             }
6419                             // Rule at src/isa/aarch64/lower.isle line 482.
6420                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6421                             let expr1_0: bool = false;
6422                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6423                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6424                             let expr4_0 =
6425                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6426                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6427                             return Some(expr5_0);
6428                         }
6429                         &Opcode::Sextend => {
6430                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6431                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6432                                 if let &InstructionData::BinaryImm8 {
6433                                     opcode: ref pattern9_0,
6434                                     arg: pattern9_1,
6435                                     imm: pattern9_2,
6436                                 } = &pattern8_0
6437                                 {
6438                                     if let &Opcode::Extractlane = pattern9_0 {
6439                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6440                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6441                                         // Rule at src/isa/aarch64/lower.isle line 519.
6442                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6443                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6444                                         let expr2_0 = constructor_size_from_ty(ctx, pattern3_0)?;
6445                                         let expr3_0 = constructor_mov_from_vec_signed(
6446                                             ctx,
6447                                             expr0_0,
6448                                             pattern12_0,
6449                                             &expr1_0,
6450                                             &expr2_0,
6451                                         )?;
6452                                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6453                                         return Some(expr4_0);
6454                                     }
6455                                 }
6456                             }
6457                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6458                             // Rule at src/isa/aarch64/lower.isle line 514.
6459                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6460                             let expr1_0: bool = true;
6461                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6462                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6463                             let expr4_0 =
6464                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6465                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6466                             return Some(expr5_0);
6467                         }
6468                         _ => {}
6469                     }
6470                 }
6471                 _ => {}
6472             }
6473         }
6474         if let Some(pattern3_0) = C::ty_vec128(ctx, pattern2_0) {
6475             let pattern4_0 = C::inst_data(ctx, pattern0_0);
6476             match &pattern4_0 {
6477                 &InstructionData::Binary {
6478                     opcode: ref pattern5_0,
6479                     args: ref pattern5_1,
6480                 } => {
6481                     match pattern5_0 {
6482                         &Opcode::UaddSat => {
6483                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6484                             // Rule at src/isa/aarch64/lower.isle line 152.
6485                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6486                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6487                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6488                             let expr3_0 = constructor_uqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6489                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6490                             return Some(expr4_0);
6491                         }
6492                         &Opcode::SaddSat => {
6493                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6494                             // Rule at src/isa/aarch64/lower.isle line 157.
6495                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6496                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6497                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6498                             let expr3_0 = constructor_sqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6499                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6500                             return Some(expr4_0);
6501                         }
6502                         &Opcode::UsubSat => {
6503                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6504                             // Rule at src/isa/aarch64/lower.isle line 162.
6505                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6506                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6507                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6508                             let expr3_0 = constructor_uqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6509                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6510                             return Some(expr4_0);
6511                         }
6512                         &Opcode::SsubSat => {
6513                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6514                             // Rule at src/isa/aarch64/lower.isle line 167.
6515                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6516                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6517                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6518                             let expr3_0 = constructor_sqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6519                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6520                             return Some(expr4_0);
6521                         }
6522                         &Opcode::Band => {
6523                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6524                             // Rule at src/isa/aarch64/lower.isle line 597.
6525                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6526                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6527                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6528                             let expr3_0 = constructor_and_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6529                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6530                             return Some(expr4_0);
6531                         }
6532                         &Opcode::Bor => {
6533                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6534                             // Rule at src/isa/aarch64/lower.isle line 610.
6535                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6536                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6537                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6538                             let expr3_0 = constructor_orr_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6539                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6540                             return Some(expr4_0);
6541                         }
6542                         &Opcode::Bxor => {
6543                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6544                             // Rule at src/isa/aarch64/lower.isle line 623.
6545                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6546                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6547                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6548                             let expr3_0 = constructor_eor_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6549                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6550                             return Some(expr4_0);
6551                         }
6552                         &Opcode::BandNot => {
6553                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6554                             // Rule at src/isa/aarch64/lower.isle line 636.
6555                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6556                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6557                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6558                             let expr3_0 = constructor_bic_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6559                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6560                             return Some(expr4_0);
6561                         }
6562                         &Opcode::Ishl => {
6563                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6564                             // Rule at src/isa/aarch64/lower.isle line 700.
6565                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6566                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6567                             let expr2_0 = constructor_vec_dup(ctx, expr1_0, &expr0_0)?;
6568                             let expr3_0 = C::put_in_reg(ctx, pattern7_0);
6569                             let expr4_0 = constructor_sshl(ctx, expr3_0, expr2_0, &expr0_0)?;
6570                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6571                             return Some(expr5_0);
6572                         }
6573                         &Opcode::Ushr => {
6574                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6575                             // Rule at src/isa/aarch64/lower.isle line 758.
6576                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6577                             let expr1_0: Type = I32;
6578                             let expr2_0 = C::zero_reg(ctx);
6579                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6580                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6581                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6582                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6583                             let expr7_0 = constructor_ushl(ctx, expr6_0, expr5_0, &expr0_0)?;
6584                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6585                             return Some(expr8_0);
6586                         }
6587                         &Opcode::Sshr => {
6588                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6589                             // Rule at src/isa/aarch64/lower.isle line 807.
6590                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6591                             let expr1_0: Type = I32;
6592                             let expr2_0 = C::zero_reg(ctx);
6593                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6594                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6595                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6596                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6597                             let expr7_0 = constructor_sshl(ctx, expr6_0, expr5_0, &expr0_0)?;
6598                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6599                             return Some(expr8_0);
6600                         }
6601                         _ => {}
6602                     }
6603                 }
6604                 &InstructionData::Unary {
6605                     opcode: ref pattern5_0,
6606                     arg: pattern5_1,
6607                 } => {
6608                     match pattern5_0 {
6609                         &Opcode::Ineg => {
6610                             // Rule at src/isa/aarch64/lower.isle line 177.
6611                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6612                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6613                             let expr2_0 = constructor_neg(ctx, expr0_0, &expr1_0)?;
6614                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6615                             return Some(expr3_0);
6616                         }
6617                         &Opcode::Bnot => {
6618                             // Rule at src/isa/aarch64/lower.isle line 584.
6619                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6620                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6621                             let expr2_0 = constructor_not(ctx, expr0_0, &expr1_0)?;
6622                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6623                             return Some(expr3_0);
6624                         }
6625                         _ => {}
6626                     }
6627                 }
6628                 _ => {}
6629             }
6630             if let Some(()) = C::not_i64x2(ctx, pattern3_0) {
6631                 let pattern5_0 = C::inst_data(ctx, pattern0_0);
6632                 if let &InstructionData::Binary {
6633                     opcode: ref pattern6_0,
6634                     args: ref pattern6_1,
6635                 } = &pattern5_0
6636                 {
6637                     if let &Opcode::Imul = pattern6_0 {
6638                         let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
6639                         // Rule at src/isa/aarch64/lower.isle line 215.
6640                         let expr0_0 = C::put_in_reg(ctx, pattern8_0);
6641                         let expr1_0 = C::put_in_reg(ctx, pattern8_1);
6642                         let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6643                         let expr3_0 = constructor_mul(ctx, expr0_0, expr1_0, &expr2_0)?;
6644                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6645                         return Some(expr4_0);
6646                     }
6647                 }
6648             }
6649         }
6650     }
6651     return None;
6652 }
6653 
6654 // Generated as internal constructor for term put_nonzero_in_reg_zext64.
6655 pub fn constructor_put_nonzero_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6656     let pattern0_0 = arg0;
6657     let pattern1_0 = C::value_type(ctx, pattern0_0);
6658     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6659         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6660         if let &InstructionData::UnaryImm {
6661             opcode: ref pattern4_0,
6662             imm: pattern4_1,
6663         } = &pattern3_0
6664         {
6665             if let &Opcode::Iconst = pattern4_0 {
6666                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6667                     // Rule at src/isa/aarch64/lower.isle line 400.
6668                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6669                     return Some(expr0_0);
6670                 }
6671             }
6672         }
6673     }
6674     // Rule at src/isa/aarch64/lower.isle line 395.
6675     let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern0_0)?;
6676     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6677     return Some(expr1_0);
6678 }
6679 
6680 // Generated as internal constructor for term put_nonzero_in_reg_sext64.
6681 pub fn constructor_put_nonzero_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6682     let pattern0_0 = arg0;
6683     let pattern1_0 = C::value_type(ctx, pattern0_0);
6684     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6685         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6686         if let &InstructionData::UnaryImm {
6687             opcode: ref pattern4_0,
6688             imm: pattern4_1,
6689         } = &pattern3_0
6690         {
6691             if let &Opcode::Iconst = pattern4_0 {
6692                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6693                     // Rule at src/isa/aarch64/lower.isle line 446.
6694                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6695                     return Some(expr0_0);
6696                 }
6697             }
6698         }
6699     }
6700     // Rule at src/isa/aarch64/lower.isle line 441.
6701     let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern0_0)?;
6702     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6703     return Some(expr1_0);
6704 }
6705 
6706 // Generated as internal constructor for term lower_shl128.
6707 pub fn constructor_lower_shl128<C: Context>(
6708     ctx: &mut C,
6709     arg0: ValueRegs,
6710     arg1: Reg,
6711 ) -> Option<ValueRegs> {
6712     let pattern0_0 = arg0;
6713     let pattern1_0 = arg1;
6714     // Rule at src/isa/aarch64/lower.isle line 683.
6715     let expr0_0: usize = 0;
6716     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6717     let expr2_0: usize = 1;
6718     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6719     let expr4_0: Type = I64;
6720     let expr5_0 = constructor_lsl(ctx, expr4_0, expr1_0, pattern1_0)?;
6721     let expr6_0: Type = I64;
6722     let expr7_0 = constructor_lsl(ctx, expr6_0, expr3_0, pattern1_0)?;
6723     let expr8_0: Type = I32;
6724     let expr9_0 = C::zero_reg(ctx);
6725     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6726     let expr11_0: Type = I64;
6727     let expr12_0: Type = I64;
6728     let expr13_0: u8 = 1;
6729     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6730     let expr15_0 = constructor_lsr_imm(ctx, expr12_0, expr1_0, expr14_0)?;
6731     let expr16_0 = constructor_lsr(ctx, expr11_0, expr15_0, expr10_0)?;
6732     let expr17_0: Type = I64;
6733     let expr18_0 = constructor_orr(ctx, expr17_0, expr7_0, expr16_0)?;
6734     let expr19_0: Type = I64;
6735     let expr20_0: Type = I64;
6736     let expr21_0: u64 = 64;
6737     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6738     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6739     let expr24_0 = Cond::Ne;
6740     let expr25_0 = C::zero_reg(ctx);
6741     let expr26_0 = constructor_csel(ctx, &expr24_0, expr25_0, expr5_0)?;
6742     let expr27_0 = Cond::Ne;
6743     let expr28_0 = constructor_csel(ctx, &expr27_0, expr5_0, expr18_0)?;
6744     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr26_0, &expr28_0)?;
6745     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6746     return Some(expr30_0);
6747 }
6748 
6749 // Generated as internal constructor for term do_shift.
6750 pub fn constructor_do_shift<C: Context>(
6751     ctx: &mut C,
6752     arg0: &ALUOp,
6753     arg1: Type,
6754     arg2: Reg,
6755     arg3: Value,
6756 ) -> Option<Reg> {
6757     let pattern0_0 = arg0;
6758     let pattern1_0 = arg1;
6759     let pattern2_0 = arg2;
6760     let pattern3_0 = arg3;
6761     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
6762         let pattern5_0 = C::inst_data(ctx, pattern4_0);
6763         if let &InstructionData::UnaryImm {
6764             opcode: ref pattern6_0,
6765             imm: pattern6_1,
6766         } = &pattern5_0
6767         {
6768             if let &Opcode::Iconst = pattern6_0 {
6769                 let closure8 = || {
6770                     return Some(pattern1_0);
6771                 };
6772                 if let Some(pattern8_0) = closure8() {
6773                     if let Some(pattern9_0) = C::imm_shift_from_imm64(ctx, pattern6_1, pattern8_0) {
6774                         // Rule at src/isa/aarch64/lower.isle line 740.
6775                         let expr0_0 = constructor_alu_rr_imm_shift(
6776                             ctx, pattern0_0, pattern1_0, pattern2_0, pattern9_0,
6777                         )?;
6778                         return Some(expr0_0);
6779                     }
6780                 }
6781             }
6782         }
6783     }
6784     let pattern0_0 = arg0;
6785     let pattern1_0 = arg1;
6786     if pattern1_0 == I32 {
6787         let pattern3_0 = arg2;
6788         let pattern4_0 = arg3;
6789         // Rule at src/isa/aarch64/lower.isle line 731.
6790         let expr0_0: Type = I32;
6791         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6792         let expr2_0: usize = 0;
6793         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6794         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6795         return Some(expr4_0);
6796     }
6797     if pattern1_0 == I64 {
6798         let pattern3_0 = arg2;
6799         let pattern4_0 = arg3;
6800         // Rule at src/isa/aarch64/lower.isle line 732.
6801         let expr0_0: Type = I64;
6802         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6803         let expr2_0: usize = 0;
6804         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6805         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6806         return Some(expr4_0);
6807     }
6808     if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
6809         let pattern3_0 = arg2;
6810         let pattern4_0 = arg3;
6811         // Rule at src/isa/aarch64/lower.isle line 722.
6812         let expr0_0 = C::put_in_regs(ctx, pattern4_0);
6813         let expr1_0: usize = 0;
6814         let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
6815         let expr3_0: Type = I32;
6816         let expr4_0 = C::shift_mask(ctx, pattern2_0);
6817         let expr5_0 = constructor_and_imm(ctx, expr3_0, expr2_0, expr4_0)?;
6818         let expr6_0: Type = I32;
6819         let expr7_0 = constructor_alu_rrr(ctx, pattern0_0, expr6_0, pattern3_0, expr5_0)?;
6820         return Some(expr7_0);
6821     }
6822     return None;
6823 }
6824 
6825 // Generated as internal constructor for term lower_ushr128.
6826 pub fn constructor_lower_ushr128<C: Context>(
6827     ctx: &mut C,
6828     arg0: ValueRegs,
6829     arg1: Reg,
6830 ) -> Option<ValueRegs> {
6831     let pattern0_0 = arg0;
6832     let pattern1_0 = arg1;
6833     // Rule at src/isa/aarch64/lower.isle line 773.
6834     let expr0_0: usize = 0;
6835     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6836     let expr2_0: usize = 1;
6837     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6838     let expr4_0: Type = I64;
6839     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6840     let expr6_0: Type = I64;
6841     let expr7_0 = constructor_lsr(ctx, expr6_0, expr3_0, pattern1_0)?;
6842     let expr8_0: Type = I32;
6843     let expr9_0 = C::zero_reg(ctx);
6844     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6845     let expr11_0: Type = I64;
6846     let expr12_0: Type = I64;
6847     let expr13_0: u8 = 1;
6848     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6849     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6850     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6851     let expr17_0: Type = I64;
6852     let expr18_0 = constructor_orr(ctx, expr17_0, expr5_0, expr16_0)?;
6853     let expr19_0: Type = I64;
6854     let expr20_0: Type = I64;
6855     let expr21_0: u64 = 64;
6856     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6857     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6858     let expr24_0 = Cond::Ne;
6859     let expr25_0 = constructor_csel(ctx, &expr24_0, expr7_0, expr18_0)?;
6860     let expr26_0 = Cond::Ne;
6861     let expr27_0 = C::zero_reg(ctx);
6862     let expr28_0 = constructor_csel(ctx, &expr26_0, expr27_0, expr7_0)?;
6863     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr25_0, &expr28_0)?;
6864     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6865     return Some(expr30_0);
6866 }
6867 
6868 // Generated as internal constructor for term lower_sshr128.
6869 pub fn constructor_lower_sshr128<C: Context>(
6870     ctx: &mut C,
6871     arg0: ValueRegs,
6872     arg1: Reg,
6873 ) -> Option<ValueRegs> {
6874     let pattern0_0 = arg0;
6875     let pattern1_0 = arg1;
6876     // Rule at src/isa/aarch64/lower.isle line 823.
6877     let expr0_0: usize = 0;
6878     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6879     let expr2_0: usize = 1;
6880     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6881     let expr4_0: Type = I64;
6882     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6883     let expr6_0: Type = I64;
6884     let expr7_0 = constructor_asr(ctx, expr6_0, expr3_0, pattern1_0)?;
6885     let expr8_0: Type = I32;
6886     let expr9_0 = C::zero_reg(ctx);
6887     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6888     let expr11_0: Type = I64;
6889     let expr12_0: Type = I64;
6890     let expr13_0: u8 = 1;
6891     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6892     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6893     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6894     let expr17_0: Type = I64;
6895     let expr18_0: u8 = 63;
6896     let expr19_0 = C::imm_shift_from_u8(ctx, expr18_0);
6897     let expr20_0 = constructor_asr_imm(ctx, expr17_0, expr3_0, expr19_0)?;
6898     let expr21_0: Type = I64;
6899     let expr22_0 = constructor_orr(ctx, expr21_0, expr5_0, expr16_0)?;
6900     let expr23_0: Type = I64;
6901     let expr24_0: Type = I64;
6902     let expr25_0: u64 = 64;
6903     let expr26_0 = C::u64_into_imm_logic(ctx, expr24_0, expr25_0);
6904     let expr27_0 = constructor_tst_imm(ctx, expr23_0, pattern1_0, expr26_0)?;
6905     let expr28_0 = Cond::Ne;
6906     let expr29_0 = constructor_csel(ctx, &expr28_0, expr7_0, expr22_0)?;
6907     let expr30_0 = Cond::Ne;
6908     let expr31_0 = constructor_csel(ctx, &expr30_0, expr20_0, expr7_0)?;
6909     let expr32_0 = constructor_consumes_flags_concat(ctx, &expr29_0, &expr31_0)?;
6910     let expr33_0 = constructor_with_flags(ctx, &expr27_0, &expr32_0)?;
6911     return Some(expr33_0);
6912 }
6913 
6914 // Generated as internal constructor for term small_rotr.
6915 pub fn constructor_small_rotr<C: Context>(
6916     ctx: &mut C,
6917     arg0: Type,
6918     arg1: Reg,
6919     arg2: Reg,
6920 ) -> Option<Reg> {
6921     let pattern0_0 = arg0;
6922     let pattern1_0 = arg1;
6923     let pattern2_0 = arg2;
6924     // Rule at src/isa/aarch64/lower.isle line 933.
6925     let expr0_0: Type = I32;
6926     let expr1_0 = C::rotr_mask(ctx, pattern0_0);
6927     let expr2_0 = constructor_and_imm(ctx, expr0_0, pattern2_0, expr1_0)?;
6928     let expr3_0: Type = I32;
6929     let expr4_0 = C::ty_bits(ctx, pattern0_0);
6930     let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
6931     let expr6_0 = constructor_sub_imm(ctx, expr3_0, expr2_0, expr5_0)?;
6932     let expr7_0: Type = I32;
6933     let expr8_0 = C::zero_reg(ctx);
6934     let expr9_0 = constructor_sub(ctx, expr7_0, expr8_0, expr6_0)?;
6935     let expr10_0: Type = I32;
6936     let expr11_0 = constructor_lsr(ctx, expr10_0, pattern1_0, expr2_0)?;
6937     let expr12_0: Type = I32;
6938     let expr13_0 = constructor_lsl(ctx, expr12_0, pattern1_0, expr9_0)?;
6939     let expr14_0: Type = I32;
6940     let expr15_0 = constructor_orr(ctx, expr14_0, expr13_0, expr11_0)?;
6941     return Some(expr15_0);
6942 }
6943 
6944 // Generated as internal constructor for term small_rotr_imm.
6945 pub fn constructor_small_rotr_imm<C: Context>(
6946     ctx: &mut C,
6947     arg0: Type,
6948     arg1: Reg,
6949     arg2: ImmShift,
6950 ) -> Option<Reg> {
6951     let pattern0_0 = arg0;
6952     let pattern1_0 = arg1;
6953     let pattern2_0 = arg2;
6954     // Rule at src/isa/aarch64/lower.isle line 954.
6955     let expr0_0: Type = I32;
6956     let expr1_0 = constructor_lsr_imm(ctx, expr0_0, pattern1_0, pattern2_0)?;
6957     let expr2_0: Type = I32;
6958     let expr3_0 = C::rotr_opposite_amount(ctx, pattern0_0, pattern2_0);
6959     let expr4_0 = constructor_lsl_imm(ctx, expr2_0, pattern1_0, expr3_0)?;
6960     let expr5_0: Type = I32;
6961     let expr6_0 = constructor_orr(ctx, expr5_0, expr4_0, expr1_0)?;
6962     return Some(expr6_0);
6963 }
6964 
6965 // Generated as internal constructor for term lower_clz128.
6966 pub fn constructor_lower_clz128<C: Context>(ctx: &mut C, arg0: ValueRegs) -> Option<ValueRegs> {
6967     let pattern0_0 = arg0;
6968     // Rule at src/isa/aarch64/lower.isle line 1019.
6969     let expr0_0: Type = I64;
6970     let expr1_0: usize = 1;
6971     let expr2_0 = C::value_regs_get(ctx, pattern0_0, expr1_0);
6972     let expr3_0 = constructor_a64_clz(ctx, expr0_0, expr2_0)?;
6973     let expr4_0: Type = I64;
6974     let expr5_0: usize = 0;
6975     let expr6_0 = C::value_regs_get(ctx, pattern0_0, expr5_0);
6976     let expr7_0 = constructor_a64_clz(ctx, expr4_0, expr6_0)?;
6977     let expr8_0: Type = I64;
6978     let expr9_0: u8 = 6;
6979     let expr10_0 = C::imm_shift_from_u8(ctx, expr9_0);
6980     let expr11_0 = constructor_lsr_imm(ctx, expr8_0, expr3_0, expr10_0)?;
6981     let expr12_0: Type = I64;
6982     let expr13_0 = constructor_madd(ctx, expr12_0, expr7_0, expr11_0, expr3_0)?;
6983     let expr14_0: Type = I64;
6984     let expr15_0: u64 = 0;
6985     let expr16_0 = constructor_imm(ctx, expr14_0, expr15_0)?;
6986     let expr17_0 = C::value_regs(ctx, expr13_0, expr16_0);
6987     return Some(expr17_0);
6988 }
6989