1 // GENERATED BY ISLE. DO NOT EDIT!
2 //
3 // Generated automatically from the instruction-selection DSL code in:
4 // - src/clif.isle
5 // - src/prelude.isle
6 // - src/isa/aarch64/inst.isle
7 // - src/isa/aarch64/lower.isle
8 
9 #![allow(dead_code, unreachable_code, unreachable_patterns)]
10 #![allow(unused_imports, unused_variables, non_snake_case)]
11 #![allow(irrefutable_let_patterns)]
12 
13 use super::*; // Pulls in all external types.
14 
15 /// Context during lowering: an implementation of this trait
16 /// must be provided with all external constructors and extractors.
17 /// A mutable borrow is passed along through all lowering logic.
18 pub trait Context {
19     fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
20     fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
21     fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
22     fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
23     fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
24     fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
25     fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
26     fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
27     fn value_regs_invalid(&mut self) -> ValueRegs;
28     fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
29     fn invalid_reg(&mut self) -> Reg;
30     fn put_in_reg(&mut self, arg0: Value) -> Reg;
31     fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
32     fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
33     fn u8_as_u64(&mut self, arg0: u8) -> u64;
34     fn u16_as_u64(&mut self, arg0: u16) -> u64;
35     fn u32_as_u64(&mut self, arg0: u32) -> u64;
36     fn ty_bits(&mut self, arg0: Type) -> u8;
37     fn ty_bits_u16(&mut self, arg0: Type) -> u16;
38     fn ty_bytes(&mut self, arg0: Type) -> u16;
39     fn lane_type(&mut self, arg0: Type) -> Type;
40     fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
41     fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
42     fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
43     fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
44     fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
45     fn vec128(&mut self, arg0: Type) -> Option<Type>;
46     fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
47     fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
48     fn unwrap_head_value_list_1(&mut self, arg0: ValueList) -> (Value, ValueSlice);
49     fn unwrap_head_value_list_2(&mut self, arg0: ValueList) -> (Value, Value, ValueSlice);
50     fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
51     fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
52     fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
53     fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
54     fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
55     fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
56     fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
57     fn first_result(&mut self, arg0: Inst) -> Option<Value>;
58     fn inst_data(&mut self, arg0: Inst) -> InstructionData;
59     fn value_type(&mut self, arg0: Value) -> Type;
60     fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
61     fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
62     fn emit(&mut self, arg0: &MInst) -> Unit;
63     fn emit_safepoint(&mut self, arg0: &MInst) -> Unit;
64     fn trap_code_division_by_zero(&mut self) -> TrapCode;
65     fn trap_code_integer_overflow(&mut self) -> TrapCode;
66     fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
67     fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
68     fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
69     fn symbol_value_data(
70         &mut self,
71         arg0: GlobalValue,
72     ) -> Option<(ExternalName, RelocDistance, i64)>;
73     fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
74     fn move_wide_const_from_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
75     fn move_wide_const_from_negated_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
76     fn imm_logic_from_u64(&mut self, arg0: u64, arg1: Type) -> Option<ImmLogic>;
77     fn imm_logic_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmLogic>;
78     fn imm_shift_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmShift>;
79     fn imm_shift_from_u8(&mut self, arg0: u8) -> ImmShift;
80     fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12>;
81     fn u8_into_uimm5(&mut self, arg0: u8) -> UImm5;
82     fn u8_into_imm12(&mut self, arg0: u8) -> Imm12;
83     fn u64_into_imm_logic(&mut self, arg0: Type, arg1: u64) -> ImmLogic;
84     fn imm12_from_negated_u64(&mut self, arg0: u64) -> Option<Imm12>;
85     fn lshl_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ShiftOpAndAmt>;
86     fn integral_ty(&mut self, arg0: Type) -> Option<Type>;
87     fn extended_value_from_value(&mut self, arg0: Value) -> Option<ExtendedValue>;
88     fn put_extended_in_reg(&mut self, arg0: &ExtendedValue) -> Reg;
89     fn get_extended_op(&mut self, arg0: &ExtendedValue) -> ExtendOp;
90     fn nzcv(&mut self, arg0: bool, arg1: bool, arg2: bool, arg3: bool) -> NZCV;
91     fn cond_br_zero(&mut self, arg0: Reg) -> CondBrKind;
92     fn cond_br_cond(&mut self, arg0: &Cond) -> CondBrKind;
93     fn zero_reg(&mut self) -> Reg;
94     fn writable_zero_reg(&mut self) -> WritableReg;
95     fn load_constant64_full(&mut self, arg0: u64) -> Reg;
96     fn sinkable_atomic_load(&mut self, arg0: Value) -> Option<SinkableAtomicLoad>;
97     fn sink_atomic_load(&mut self, arg0: &SinkableAtomicLoad) -> Reg;
98     fn safe_divisor_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
99     fn shift_mask(&mut self, arg0: Type) -> ImmLogic;
100     fn negate_imm_shift(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
101     fn rotr_mask(&mut self, arg0: Type) -> ImmLogic;
102     fn rotr_opposite_amount(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
103 }
104 
105 /// Internal type SideEffectNoResult: defined at src/prelude.isle line 308.
106 #[derive(Clone, Debug)]
107 pub enum SideEffectNoResult {
108     Inst { inst: MInst },
109 }
110 
111 /// Internal type ProducesFlags: defined at src/prelude.isle line 327.
112 #[derive(Clone, Debug)]
113 pub enum ProducesFlags {
114     ProducesFlags { inst: MInst, result: Reg },
115 }
116 
117 /// Internal type ConsumesFlags: defined at src/prelude.isle line 330.
118 #[derive(Clone, Debug)]
119 pub enum ConsumesFlags {
120     ConsumesFlags { inst: MInst, result: Reg },
121 }
122 
123 /// Internal type MInst: defined at src/isa/aarch64/inst.isle line 2.
124 #[derive(Clone, Debug)]
125 pub enum MInst {
126     Nop0,
127     Nop4,
128     AluRRR {
129         alu_op: ALUOp,
130         rd: WritableReg,
131         rn: Reg,
132         rm: Reg,
133     },
134     AluRRRR {
135         alu_op: ALUOp3,
136         rd: WritableReg,
137         rn: Reg,
138         rm: Reg,
139         ra: Reg,
140     },
141     AluRRImm12 {
142         alu_op: ALUOp,
143         rd: WritableReg,
144         rn: Reg,
145         imm12: Imm12,
146     },
147     AluRRImmLogic {
148         alu_op: ALUOp,
149         rd: WritableReg,
150         rn: Reg,
151         imml: ImmLogic,
152     },
153     AluRRImmShift {
154         alu_op: ALUOp,
155         rd: WritableReg,
156         rn: Reg,
157         immshift: ImmShift,
158     },
159     AluRRRShift {
160         alu_op: ALUOp,
161         rd: WritableReg,
162         rn: Reg,
163         rm: Reg,
164         shiftop: ShiftOpAndAmt,
165     },
166     AluRRRExtend {
167         alu_op: ALUOp,
168         rd: WritableReg,
169         rn: Reg,
170         rm: Reg,
171         extendop: ExtendOp,
172     },
173     BitRR {
174         op: BitOp,
175         rd: WritableReg,
176         rn: Reg,
177     },
178     ULoad8 {
179         rd: WritableReg,
180         mem: AMode,
181         flags: MemFlags,
182     },
183     SLoad8 {
184         rd: WritableReg,
185         mem: AMode,
186         flags: MemFlags,
187     },
188     ULoad16 {
189         rd: WritableReg,
190         mem: AMode,
191         flags: MemFlags,
192     },
193     SLoad16 {
194         rd: WritableReg,
195         mem: AMode,
196         flags: MemFlags,
197     },
198     ULoad32 {
199         rd: WritableReg,
200         mem: AMode,
201         flags: MemFlags,
202     },
203     SLoad32 {
204         rd: WritableReg,
205         mem: AMode,
206         flags: MemFlags,
207     },
208     ULoad64 {
209         rd: WritableReg,
210         mem: AMode,
211         flags: MemFlags,
212     },
213     Store8 {
214         rd: Reg,
215         mem: AMode,
216         flags: MemFlags,
217     },
218     Store16 {
219         rd: Reg,
220         mem: AMode,
221         flags: MemFlags,
222     },
223     Store32 {
224         rd: Reg,
225         mem: AMode,
226         flags: MemFlags,
227     },
228     Store64 {
229         rd: Reg,
230         mem: AMode,
231         flags: MemFlags,
232     },
233     StoreP64 {
234         rt: Reg,
235         rt2: Reg,
236         mem: PairAMode,
237         flags: MemFlags,
238     },
239     LoadP64 {
240         rt: WritableReg,
241         rt2: WritableReg,
242         mem: PairAMode,
243         flags: MemFlags,
244     },
245     Mov64 {
246         rd: WritableReg,
247         rm: Reg,
248     },
249     Mov32 {
250         rd: WritableReg,
251         rm: Reg,
252     },
253     MovZ {
254         rd: WritableReg,
255         imm: MoveWideConst,
256         size: OperandSize,
257     },
258     MovN {
259         rd: WritableReg,
260         imm: MoveWideConst,
261         size: OperandSize,
262     },
263     MovK {
264         rd: WritableReg,
265         imm: MoveWideConst,
266         size: OperandSize,
267     },
268     Extend {
269         rd: WritableReg,
270         rn: Reg,
271         signed: bool,
272         from_bits: u8,
273         to_bits: u8,
274     },
275     CSel {
276         rd: WritableReg,
277         cond: Cond,
278         rn: Reg,
279         rm: Reg,
280     },
281     CSet {
282         rd: WritableReg,
283         cond: Cond,
284     },
285     CSetm {
286         rd: WritableReg,
287         cond: Cond,
288     },
289     CCmpImm {
290         size: OperandSize,
291         rn: Reg,
292         imm: UImm5,
293         nzcv: NZCV,
294         cond: Cond,
295     },
296     AtomicRMWLoop {
297         ty: Type,
298         op: AtomicRmwOp,
299     },
300     AtomicRMW {
301         op: AtomicRMWOp,
302         rs: Reg,
303         rt: WritableReg,
304         rn: Reg,
305         ty: Type,
306     },
307     AtomicCAS {
308         rs: WritableReg,
309         rt: Reg,
310         rn: Reg,
311         ty: Type,
312     },
313     AtomicCASLoop {
314         ty: Type,
315     },
316     LoadAcquire {
317         access_ty: Type,
318         rt: WritableReg,
319         rn: Reg,
320     },
321     StoreRelease {
322         access_ty: Type,
323         rt: Reg,
324         rn: Reg,
325     },
326     Fence,
327     FpuMove64 {
328         rd: WritableReg,
329         rn: Reg,
330     },
331     FpuMove128 {
332         rd: WritableReg,
333         rn: Reg,
334     },
335     FpuMoveFromVec {
336         rd: WritableReg,
337         rn: Reg,
338         idx: u8,
339         size: VectorSize,
340     },
341     FpuExtend {
342         rd: WritableReg,
343         rn: Reg,
344         size: ScalarSize,
345     },
346     FpuRR {
347         fpu_op: FPUOp1,
348         rd: WritableReg,
349         rn: Reg,
350     },
351     FpuRRR {
352         fpu_op: FPUOp2,
353         rd: WritableReg,
354         rn: Reg,
355         rm: Reg,
356     },
357     FpuRRI {
358         fpu_op: FPUOpRI,
359         rd: WritableReg,
360         rn: Reg,
361     },
362     FpuRRRR {
363         fpu_op: FPUOp3,
364         rd: WritableReg,
365         rn: Reg,
366         rm: Reg,
367         ra: Reg,
368     },
369     FpuCmp32 {
370         rn: Reg,
371         rm: Reg,
372     },
373     FpuCmp64 {
374         rn: Reg,
375         rm: Reg,
376     },
377     FpuLoad32 {
378         rd: WritableReg,
379         mem: AMode,
380         flags: MemFlags,
381     },
382     FpuStore32 {
383         rd: Reg,
384         mem: AMode,
385         flags: MemFlags,
386     },
387     FpuLoad64 {
388         rd: WritableReg,
389         mem: AMode,
390         flags: MemFlags,
391     },
392     FpuStore64 {
393         rd: Reg,
394         mem: AMode,
395         flags: MemFlags,
396     },
397     FpuLoad128 {
398         rd: WritableReg,
399         mem: AMode,
400         flags: MemFlags,
401     },
402     FpuStore128 {
403         rd: Reg,
404         mem: AMode,
405         flags: MemFlags,
406     },
407     FpuLoadP64 {
408         rt: WritableReg,
409         rt2: WritableReg,
410         mem: PairAMode,
411         flags: MemFlags,
412     },
413     FpuStoreP64 {
414         rt: Reg,
415         rt2: Reg,
416         mem: PairAMode,
417         flags: MemFlags,
418     },
419     FpuLoadP128 {
420         rt: WritableReg,
421         rt2: WritableReg,
422         mem: PairAMode,
423         flags: MemFlags,
424     },
425     FpuStoreP128 {
426         rt: Reg,
427         rt2: Reg,
428         mem: PairAMode,
429         flags: MemFlags,
430     },
431     LoadFpuConst64 {
432         rd: WritableReg,
433         const_data: u64,
434     },
435     LoadFpuConst128 {
436         rd: WritableReg,
437         const_data: u128,
438     },
439     FpuToInt {
440         op: FpuToIntOp,
441         rd: WritableReg,
442         rn: Reg,
443     },
444     IntToFpu {
445         op: IntToFpuOp,
446         rd: WritableReg,
447         rn: Reg,
448     },
449     FpuCSel32 {
450         rd: WritableReg,
451         rn: Reg,
452         rm: Reg,
453         cond: Cond,
454     },
455     FpuCSel64 {
456         rd: WritableReg,
457         rn: Reg,
458         rm: Reg,
459         cond: Cond,
460     },
461     FpuRound {
462         op: FpuRoundMode,
463         rd: WritableReg,
464         rn: Reg,
465     },
466     MovToFpu {
467         rd: WritableReg,
468         rn: Reg,
469         size: ScalarSize,
470     },
471     FpuMoveFPImm {
472         rd: WritableReg,
473         imm: ASIMDFPModImm,
474         size: ScalarSize,
475     },
476     MovToVec {
477         rd: WritableReg,
478         rn: Reg,
479         idx: u8,
480         size: VectorSize,
481     },
482     MovFromVec {
483         rd: WritableReg,
484         rn: Reg,
485         idx: u8,
486         size: VectorSize,
487     },
488     MovFromVecSigned {
489         rd: WritableReg,
490         rn: Reg,
491         idx: u8,
492         size: VectorSize,
493         scalar_size: OperandSize,
494     },
495     VecDup {
496         rd: WritableReg,
497         rn: Reg,
498         size: VectorSize,
499     },
500     VecDupFromFpu {
501         rd: WritableReg,
502         rn: Reg,
503         size: VectorSize,
504     },
505     VecDupFPImm {
506         rd: WritableReg,
507         imm: ASIMDFPModImm,
508         size: VectorSize,
509     },
510     VecDupImm {
511         rd: WritableReg,
512         imm: ASIMDMovModImm,
513         invert: bool,
514         size: VectorSize,
515     },
516     VecExtend {
517         t: VecExtendOp,
518         rd: WritableReg,
519         rn: Reg,
520         high_half: bool,
521     },
522     VecMovElement {
523         rd: WritableReg,
524         rn: Reg,
525         dest_idx: u8,
526         src_idx: u8,
527         size: VectorSize,
528     },
529     VecRRLong {
530         op: VecRRLongOp,
531         rd: WritableReg,
532         rn: Reg,
533         high_half: bool,
534     },
535     VecRRNarrow {
536         op: VecRRNarrowOp,
537         rd: WritableReg,
538         rn: Reg,
539         high_half: bool,
540     },
541     VecRRPair {
542         op: VecPairOp,
543         rd: WritableReg,
544         rn: Reg,
545     },
546     VecRRRLong {
547         alu_op: VecRRRLongOp,
548         rd: WritableReg,
549         rn: Reg,
550         rm: Reg,
551         high_half: bool,
552     },
553     VecRRPairLong {
554         op: VecRRPairLongOp,
555         rd: WritableReg,
556         rn: Reg,
557     },
558     VecRRR {
559         alu_op: VecALUOp,
560         rd: WritableReg,
561         rn: Reg,
562         rm: Reg,
563         size: VectorSize,
564     },
565     VecMisc {
566         op: VecMisc2,
567         rd: WritableReg,
568         rn: Reg,
569         size: VectorSize,
570     },
571     VecLanes {
572         op: VecLanesOp,
573         rd: WritableReg,
574         rn: Reg,
575         size: VectorSize,
576     },
577     VecShiftImm {
578         op: VecShiftImmOp,
579         rd: WritableReg,
580         rn: Reg,
581         size: VectorSize,
582         imm: u8,
583     },
584     VecExtract {
585         rd: WritableReg,
586         rn: Reg,
587         rm: Reg,
588         imm4: u8,
589     },
590     VecTbl {
591         rd: WritableReg,
592         rn: Reg,
593         rm: Reg,
594         is_extension: bool,
595     },
596     VecTbl2 {
597         rd: WritableReg,
598         rn: Reg,
599         rn2: Reg,
600         rm: Reg,
601         is_extension: bool,
602     },
603     VecLoadReplicate {
604         rd: WritableReg,
605         rn: Reg,
606         size: VectorSize,
607     },
608     VecCSel {
609         rd: WritableReg,
610         rn: Reg,
611         rm: Reg,
612         cond: Cond,
613     },
614     MovToNZCV {
615         rn: Reg,
616     },
617     MovFromNZCV {
618         rd: WritableReg,
619     },
620     Call {
621         info: BoxCallInfo,
622     },
623     CallInd {
624         info: BoxCallIndInfo,
625     },
626     Ret,
627     EpiloguePlaceholder,
628     Jump {
629         dest: BranchTarget,
630     },
631     CondBr {
632         taken: BranchTarget,
633         not_taken: BranchTarget,
634         kind: CondBrKind,
635     },
636     TrapIf {
637         kind: CondBrKind,
638         trap_code: TrapCode,
639     },
640     IndirectBr {
641         rn: Reg,
642         targets: VecMachLabel,
643     },
644     Brk,
645     Udf {
646         trap_code: TrapCode,
647     },
648     Adr {
649         rd: WritableReg,
650         off: i32,
651     },
652     Word4 {
653         data: u32,
654     },
655     Word8 {
656         data: u64,
657     },
658     JTSequence {
659         info: BoxJTSequenceInfo,
660         ridx: Reg,
661         rtmp1: WritableReg,
662         rtmp2: WritableReg,
663     },
664     LoadExtName {
665         rd: WritableReg,
666         name: BoxExternalName,
667         offset: i64,
668     },
669     LoadAddr {
670         rd: WritableReg,
671         mem: AMode,
672     },
673     VirtualSPOffsetAdj {
674         offset: i64,
675     },
676     EmitIsland {
677         needed_space: CodeOffset,
678     },
679     ElfTlsGetAddr {
680         symbol: ExternalName,
681     },
682     ValueLabelMarker {
683         reg: Reg,
684         label: ValueLabel,
685     },
686     Unwind {
687         inst: UnwindInst,
688     },
689 }
690 
691 /// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 789.
692 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
693 pub enum ALUOp {
694     Add32,
695     Add64,
696     Sub32,
697     Sub64,
698     Orr32,
699     Orr64,
700     OrrNot32,
701     OrrNot64,
702     And32,
703     And64,
704     AndS32,
705     AndS64,
706     AndNot32,
707     AndNot64,
708     Eor32,
709     Eor64,
710     EorNot32,
711     EorNot64,
712     AddS32,
713     AddS64,
714     SubS32,
715     SubS64,
716     SMulH,
717     UMulH,
718     SDiv64,
719     UDiv64,
720     RotR32,
721     RotR64,
722     Lsr32,
723     Lsr64,
724     Asr32,
725     Asr64,
726     Lsl32,
727     Lsl64,
728     Adc32,
729     Adc64,
730     AdcS32,
731     AdcS64,
732     Sbc32,
733     Sbc64,
734     SbcS32,
735     SbcS64,
736 }
737 
738 /// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 850.
739 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
740 pub enum ALUOp3 {
741     MAdd32,
742     MAdd64,
743     MSub32,
744     MSub64,
745 }
746 
747 /// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 893.
748 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
749 pub enum BitOp {
750     RBit32,
751     RBit64,
752     Clz32,
753     Clz64,
754     Cls32,
755     Cls64,
756 }
757 
758 /// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 959.
759 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
760 pub enum FPUOp1 {
761     Abs32,
762     Abs64,
763     Neg32,
764     Neg64,
765     Sqrt32,
766     Sqrt64,
767     Cvt32To64,
768     Cvt64To32,
769 }
770 
771 /// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 972.
772 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
773 pub enum FPUOp2 {
774     Add32,
775     Add64,
776     Sub32,
777     Sub64,
778     Mul32,
779     Mul64,
780     Div32,
781     Div64,
782     Max32,
783     Max64,
784     Min32,
785     Min64,
786     Sqadd64,
787     Uqadd64,
788     Sqsub64,
789     Uqsub64,
790 }
791 
792 /// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 997.
793 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
794 pub enum FPUOp3 {
795     MAdd32,
796     MAdd64,
797 }
798 
799 /// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 1004.
800 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
801 pub enum FpuToIntOp {
802     F32ToU32,
803     F32ToI32,
804     F32ToU64,
805     F32ToI64,
806     F64ToU32,
807     F64ToI32,
808     F64ToU64,
809     F64ToI64,
810 }
811 
812 /// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 1017.
813 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
814 pub enum IntToFpuOp {
815     U32ToF32,
816     I32ToF32,
817     U32ToF64,
818     I32ToF64,
819     U64ToF32,
820     I64ToF32,
821     U64ToF64,
822     I64ToF64,
823 }
824 
825 /// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 1031.
826 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
827 pub enum FpuRoundMode {
828     Minus32,
829     Minus64,
830     Plus32,
831     Plus64,
832     Zero32,
833     Zero64,
834     Nearest32,
835     Nearest64,
836 }
837 
838 /// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 1044.
839 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
840 pub enum VecExtendOp {
841     Sxtl8,
842     Sxtl16,
843     Sxtl32,
844     Uxtl8,
845     Uxtl16,
846     Uxtl32,
847 }
848 
849 /// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1061.
850 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
851 pub enum VecALUOp {
852     Sqadd,
853     Uqadd,
854     Sqsub,
855     Uqsub,
856     Cmeq,
857     Cmge,
858     Cmgt,
859     Cmhs,
860     Cmhi,
861     Fcmeq,
862     Fcmgt,
863     Fcmge,
864     And,
865     Bic,
866     Orr,
867     Eor,
868     Bsl,
869     Umaxp,
870     Add,
871     Sub,
872     Mul,
873     Sshl,
874     Ushl,
875     Umin,
876     Smin,
877     Umax,
878     Smax,
879     Urhadd,
880     Fadd,
881     Fsub,
882     Fdiv,
883     Fmax,
884     Fmin,
885     Fmul,
886     Addp,
887     Zip1,
888     Sqrdmulh,
889 }
890 
891 /// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1140.
892 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
893 pub enum VecMisc2 {
894     Not,
895     Neg,
896     Abs,
897     Fabs,
898     Fneg,
899     Fsqrt,
900     Rev64,
901     Fcvtzs,
902     Fcvtzu,
903     Scvtf,
904     Ucvtf,
905     Frintn,
906     Frintz,
907     Frintm,
908     Frintp,
909     Cnt,
910     Cmeq0,
911 }
912 
913 /// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1179.
914 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
915 pub enum VecRRLongOp {
916     Fcvtl16,
917     Fcvtl32,
918     Shll8,
919     Shll16,
920     Shll32,
921 }
922 
923 /// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1194.
924 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
925 pub enum VecRRNarrowOp {
926     Xtn16,
927     Xtn32,
928     Xtn64,
929     Sqxtn16,
930     Sqxtn32,
931     Sqxtn64,
932     Sqxtun16,
933     Sqxtun32,
934     Sqxtun64,
935     Uqxtn16,
936     Uqxtn32,
937     Uqxtn64,
938     Fcvtn32,
939     Fcvtn64,
940 }
941 
942 /// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1226.
943 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
944 pub enum VecRRRLongOp {
945     Smull8,
946     Smull16,
947     Smull32,
948     Umull8,
949     Umull16,
950     Umull32,
951     Umlal8,
952     Umlal16,
953     Umlal32,
954 }
955 
956 /// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1243.
957 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
958 pub enum VecPairOp {
959     Addp,
960 }
961 
962 /// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1251.
963 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
964 pub enum VecRRPairLongOp {
965     Saddlp8,
966     Saddlp16,
967     Uaddlp8,
968     Uaddlp16,
969 }
970 
971 /// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1262.
972 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
973 pub enum VecLanesOp {
974     Addv,
975     Uminv,
976 }
977 
978 /// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1271.
979 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
980 pub enum VecShiftImmOp {
981     Shl,
982     Ushr,
983     Sshr,
984 }
985 
986 /// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1282.
987 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
988 pub enum AtomicRMWOp {
989     Add,
990     Clr,
991     Eor,
992     Set,
993     Smax,
994     Smin,
995     Umax,
996     Umin,
997 }
998 
999 // Generated as internal constructor for term temp_reg.
1000 pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
1001     let pattern0_0 = arg0;
1002     // Rule at src/prelude.isle line 73.
1003     let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
1004     let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
1005     return Some(expr1_0);
1006 }
1007 
1008 // Generated as internal constructor for term lo_reg.
1009 pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
1010     let pattern0_0 = arg0;
1011     // Rule at src/prelude.isle line 108.
1012     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1013     let expr1_0: usize = 0;
1014     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1015     return Some(expr2_0);
1016 }
1017 
1018 // Generated as internal constructor for term value_regs_none.
1019 pub fn constructor_value_regs_none<C: Context>(
1020     ctx: &mut C,
1021     arg0: &SideEffectNoResult,
1022 ) -> Option<ValueRegs> {
1023     let pattern0_0 = arg0;
1024     if let &SideEffectNoResult::Inst {
1025         inst: ref pattern1_0,
1026     } = pattern0_0
1027     {
1028         // Rule at src/prelude.isle line 313.
1029         let expr0_0 = C::emit(ctx, &pattern1_0);
1030         let expr1_0 = C::value_regs_invalid(ctx);
1031         return Some(expr1_0);
1032     }
1033     return None;
1034 }
1035 
1036 // Generated as internal constructor for term safepoint.
1037 pub fn constructor_safepoint<C: Context>(
1038     ctx: &mut C,
1039     arg0: &SideEffectNoResult,
1040 ) -> Option<ValueRegs> {
1041     let pattern0_0 = arg0;
1042     if let &SideEffectNoResult::Inst {
1043         inst: ref pattern1_0,
1044     } = pattern0_0
1045     {
1046         // Rule at src/prelude.isle line 319.
1047         let expr0_0 = C::emit_safepoint(ctx, &pattern1_0);
1048         let expr1_0 = C::value_regs_invalid(ctx);
1049         return Some(expr1_0);
1050     }
1051     return None;
1052 }
1053 
1054 // Generated as internal constructor for term with_flags.
1055 pub fn constructor_with_flags<C: Context>(
1056     ctx: &mut C,
1057     arg0: &ProducesFlags,
1058     arg1: &ConsumesFlags,
1059 ) -> Option<ValueRegs> {
1060     let pattern0_0 = arg0;
1061     if let &ProducesFlags::ProducesFlags {
1062         inst: ref pattern1_0,
1063         result: pattern1_1,
1064     } = pattern0_0
1065     {
1066         let pattern2_0 = arg1;
1067         if let &ConsumesFlags::ConsumesFlags {
1068             inst: ref pattern3_0,
1069             result: pattern3_1,
1070         } = pattern2_0
1071         {
1072             // Rule at src/prelude.isle line 340.
1073             let expr0_0 = C::emit(ctx, &pattern1_0);
1074             let expr1_0 = C::emit(ctx, &pattern3_0);
1075             let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1076             return Some(expr2_0);
1077         }
1078     }
1079     return None;
1080 }
1081 
1082 // Generated as internal constructor for term with_flags_1.
1083 pub fn constructor_with_flags_1<C: Context>(
1084     ctx: &mut C,
1085     arg0: &ProducesFlags,
1086     arg1: &ConsumesFlags,
1087 ) -> Option<Reg> {
1088     let pattern0_0 = arg0;
1089     if let &ProducesFlags::ProducesFlags {
1090         inst: ref pattern1_0,
1091         result: pattern1_1,
1092     } = pattern0_0
1093     {
1094         let pattern2_0 = arg1;
1095         if let &ConsumesFlags::ConsumesFlags {
1096             inst: ref pattern3_0,
1097             result: pattern3_1,
1098         } = pattern2_0
1099         {
1100             // Rule at src/prelude.isle line 348.
1101             let expr0_0 = C::emit(ctx, &pattern1_0);
1102             let expr1_0 = C::emit(ctx, &pattern3_0);
1103             return Some(pattern3_1);
1104         }
1105     }
1106     return None;
1107 }
1108 
1109 // Generated as internal constructor for term with_flags_2.
1110 pub fn constructor_with_flags_2<C: Context>(
1111     ctx: &mut C,
1112     arg0: &ProducesFlags,
1113     arg1: &ConsumesFlags,
1114     arg2: &ConsumesFlags,
1115 ) -> Option<ValueRegs> {
1116     let pattern0_0 = arg0;
1117     if let &ProducesFlags::ProducesFlags {
1118         inst: ref pattern1_0,
1119         result: pattern1_1,
1120     } = pattern0_0
1121     {
1122         let pattern2_0 = arg1;
1123         if let &ConsumesFlags::ConsumesFlags {
1124             inst: ref pattern3_0,
1125             result: pattern3_1,
1126         } = pattern2_0
1127         {
1128             let pattern4_0 = arg2;
1129             if let &ConsumesFlags::ConsumesFlags {
1130                 inst: ref pattern5_0,
1131                 result: pattern5_1,
1132             } = pattern4_0
1133             {
1134                 // Rule at src/prelude.isle line 358.
1135                 let expr0_0 = C::emit(ctx, &pattern1_0);
1136                 let expr1_0 = C::emit(ctx, &pattern5_0);
1137                 let expr2_0 = C::emit(ctx, &pattern3_0);
1138                 let expr3_0 = C::value_regs(ctx, pattern3_1, pattern5_1);
1139                 return Some(expr3_0);
1140             }
1141         }
1142     }
1143     return None;
1144 }
1145 
1146 // Generated as internal constructor for term vector_size.
1147 pub fn constructor_vector_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<VectorSize> {
1148     let pattern0_0 = arg0;
1149     if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
1150         if pattern1_0 == 8 {
1151             if pattern1_1 == 16 {
1152                 // Rule at src/isa/aarch64/inst.isle line 953.
1153                 let expr0_0 = VectorSize::Size8x16;
1154                 return Some(expr0_0);
1155             }
1156         }
1157         if pattern1_0 == 16 {
1158             if pattern1_1 == 8 {
1159                 // Rule at src/isa/aarch64/inst.isle line 954.
1160                 let expr0_0 = VectorSize::Size16x8;
1161                 return Some(expr0_0);
1162             }
1163         }
1164         if pattern1_0 == 32 {
1165             if pattern1_1 == 4 {
1166                 // Rule at src/isa/aarch64/inst.isle line 955.
1167                 let expr0_0 = VectorSize::Size32x4;
1168                 return Some(expr0_0);
1169             }
1170         }
1171         if pattern1_0 == 64 {
1172             if pattern1_1 == 2 {
1173                 // Rule at src/isa/aarch64/inst.isle line 956.
1174                 let expr0_0 = VectorSize::Size64x2;
1175                 return Some(expr0_0);
1176             }
1177         }
1178     }
1179     return None;
1180 }
1181 
1182 // Generated as internal constructor for term movz.
1183 pub fn constructor_movz<C: Context>(
1184     ctx: &mut C,
1185     arg0: MoveWideConst,
1186     arg1: &OperandSize,
1187 ) -> Option<Reg> {
1188     let pattern0_0 = arg0;
1189     let pattern1_0 = arg1;
1190     // Rule at src/isa/aarch64/inst.isle line 1378.
1191     let expr0_0: Type = I64;
1192     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1193     let expr2_0 = MInst::MovZ {
1194         rd: expr1_0,
1195         imm: pattern0_0,
1196         size: pattern1_0.clone(),
1197     };
1198     let expr3_0 = C::emit(ctx, &expr2_0);
1199     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1200     return Some(expr4_0);
1201 }
1202 
1203 // Generated as internal constructor for term movn.
1204 pub fn constructor_movn<C: Context>(
1205     ctx: &mut C,
1206     arg0: MoveWideConst,
1207     arg1: &OperandSize,
1208 ) -> Option<Reg> {
1209     let pattern0_0 = arg0;
1210     let pattern1_0 = arg1;
1211     // Rule at src/isa/aarch64/inst.isle line 1385.
1212     let expr0_0: Type = I64;
1213     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1214     let expr2_0 = MInst::MovN {
1215         rd: expr1_0,
1216         imm: pattern0_0,
1217         size: pattern1_0.clone(),
1218     };
1219     let expr3_0 = C::emit(ctx, &expr2_0);
1220     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1221     return Some(expr4_0);
1222 }
1223 
1224 // Generated as internal constructor for term alu_rr_imm_logic.
1225 pub fn constructor_alu_rr_imm_logic<C: Context>(
1226     ctx: &mut C,
1227     arg0: &ALUOp,
1228     arg1: Reg,
1229     arg2: ImmLogic,
1230 ) -> Option<Reg> {
1231     let pattern0_0 = arg0;
1232     let pattern1_0 = arg1;
1233     let pattern2_0 = arg2;
1234     // Rule at src/isa/aarch64/inst.isle line 1392.
1235     let expr0_0: Type = I64;
1236     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1237     let expr2_0 = MInst::AluRRImmLogic {
1238         alu_op: pattern0_0.clone(),
1239         rd: expr1_0,
1240         rn: pattern1_0,
1241         imml: pattern2_0,
1242     };
1243     let expr3_0 = C::emit(ctx, &expr2_0);
1244     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1245     return Some(expr4_0);
1246 }
1247 
1248 // Generated as internal constructor for term alu_rr_imm_shift.
1249 pub fn constructor_alu_rr_imm_shift<C: Context>(
1250     ctx: &mut C,
1251     arg0: &ALUOp,
1252     arg1: Reg,
1253     arg2: ImmShift,
1254 ) -> Option<Reg> {
1255     let pattern0_0 = arg0;
1256     let pattern1_0 = arg1;
1257     let pattern2_0 = arg2;
1258     // Rule at src/isa/aarch64/inst.isle line 1399.
1259     let expr0_0: Type = I64;
1260     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1261     let expr2_0 = MInst::AluRRImmShift {
1262         alu_op: pattern0_0.clone(),
1263         rd: expr1_0,
1264         rn: pattern1_0,
1265         immshift: pattern2_0,
1266     };
1267     let expr3_0 = C::emit(ctx, &expr2_0);
1268     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1269     return Some(expr4_0);
1270 }
1271 
1272 // Generated as internal constructor for term alu_rrr.
1273 pub fn constructor_alu_rrr<C: Context>(
1274     ctx: &mut C,
1275     arg0: &ALUOp,
1276     arg1: Reg,
1277     arg2: Reg,
1278 ) -> Option<Reg> {
1279     let pattern0_0 = arg0;
1280     let pattern1_0 = arg1;
1281     let pattern2_0 = arg2;
1282     // Rule at src/isa/aarch64/inst.isle line 1406.
1283     let expr0_0: Type = I64;
1284     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1285     let expr2_0 = MInst::AluRRR {
1286         alu_op: pattern0_0.clone(),
1287         rd: expr1_0,
1288         rn: pattern1_0,
1289         rm: pattern2_0,
1290     };
1291     let expr3_0 = C::emit(ctx, &expr2_0);
1292     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1293     return Some(expr4_0);
1294 }
1295 
1296 // Generated as internal constructor for term vec_rrr.
1297 pub fn constructor_vec_rrr<C: Context>(
1298     ctx: &mut C,
1299     arg0: &VecALUOp,
1300     arg1: Reg,
1301     arg2: Reg,
1302     arg3: &VectorSize,
1303 ) -> Option<Reg> {
1304     let pattern0_0 = arg0;
1305     let pattern1_0 = arg1;
1306     let pattern2_0 = arg2;
1307     let pattern3_0 = arg3;
1308     // Rule at src/isa/aarch64/inst.isle line 1413.
1309     let expr0_0: Type = I8X16;
1310     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1311     let expr2_0 = MInst::VecRRR {
1312         alu_op: pattern0_0.clone(),
1313         rd: expr1_0,
1314         rn: pattern1_0,
1315         rm: pattern2_0,
1316         size: pattern3_0.clone(),
1317     };
1318     let expr3_0 = C::emit(ctx, &expr2_0);
1319     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1320     return Some(expr4_0);
1321 }
1322 
1323 // Generated as internal constructor for term vec_lanes.
1324 pub fn constructor_vec_lanes<C: Context>(
1325     ctx: &mut C,
1326     arg0: &VecLanesOp,
1327     arg1: Reg,
1328     arg2: &VectorSize,
1329 ) -> Option<Reg> {
1330     let pattern0_0 = arg0;
1331     let pattern1_0 = arg1;
1332     let pattern2_0 = arg2;
1333     // Rule at src/isa/aarch64/inst.isle line 1420.
1334     let expr0_0: Type = I8X16;
1335     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1336     let expr2_0 = MInst::VecLanes {
1337         op: pattern0_0.clone(),
1338         rd: expr1_0,
1339         rn: pattern1_0,
1340         size: pattern2_0.clone(),
1341     };
1342     let expr3_0 = C::emit(ctx, &expr2_0);
1343     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1344     return Some(expr4_0);
1345 }
1346 
1347 // Generated as internal constructor for term vec_dup.
1348 pub fn constructor_vec_dup<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
1349     let pattern0_0 = arg0;
1350     let pattern1_0 = arg1;
1351     // Rule at src/isa/aarch64/inst.isle line 1427.
1352     let expr0_0: Type = I8X16;
1353     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1354     let expr2_0 = MInst::VecDup {
1355         rd: expr1_0,
1356         rn: pattern0_0,
1357         size: pattern1_0.clone(),
1358     };
1359     let expr3_0 = C::emit(ctx, &expr2_0);
1360     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1361     return Some(expr4_0);
1362 }
1363 
1364 // Generated as internal constructor for term alu_rr_imm12.
1365 pub fn constructor_alu_rr_imm12<C: Context>(
1366     ctx: &mut C,
1367     arg0: &ALUOp,
1368     arg1: Reg,
1369     arg2: Imm12,
1370 ) -> Option<Reg> {
1371     let pattern0_0 = arg0;
1372     let pattern1_0 = arg1;
1373     let pattern2_0 = arg2;
1374     // Rule at src/isa/aarch64/inst.isle line 1434.
1375     let expr0_0: Type = I64;
1376     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1377     let expr2_0 = MInst::AluRRImm12 {
1378         alu_op: pattern0_0.clone(),
1379         rd: expr1_0,
1380         rn: pattern1_0,
1381         imm12: pattern2_0,
1382     };
1383     let expr3_0 = C::emit(ctx, &expr2_0);
1384     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1385     return Some(expr4_0);
1386 }
1387 
1388 // Generated as internal constructor for term alu_rrr_shift.
1389 pub fn constructor_alu_rrr_shift<C: Context>(
1390     ctx: &mut C,
1391     arg0: &ALUOp,
1392     arg1: Reg,
1393     arg2: Reg,
1394     arg3: ShiftOpAndAmt,
1395 ) -> Option<Reg> {
1396     let pattern0_0 = arg0;
1397     let pattern1_0 = arg1;
1398     let pattern2_0 = arg2;
1399     let pattern3_0 = arg3;
1400     // Rule at src/isa/aarch64/inst.isle line 1441.
1401     let expr0_0: Type = I64;
1402     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1403     let expr2_0 = MInst::AluRRRShift {
1404         alu_op: pattern0_0.clone(),
1405         rd: expr1_0,
1406         rn: pattern1_0,
1407         rm: pattern2_0,
1408         shiftop: pattern3_0,
1409     };
1410     let expr3_0 = C::emit(ctx, &expr2_0);
1411     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1412     return Some(expr4_0);
1413 }
1414 
1415 // Generated as internal constructor for term alu_rrr_extend.
1416 pub fn constructor_alu_rrr_extend<C: Context>(
1417     ctx: &mut C,
1418     arg0: &ALUOp,
1419     arg1: Reg,
1420     arg2: Reg,
1421     arg3: &ExtendOp,
1422 ) -> Option<Reg> {
1423     let pattern0_0 = arg0;
1424     let pattern1_0 = arg1;
1425     let pattern2_0 = arg2;
1426     let pattern3_0 = arg3;
1427     // Rule at src/isa/aarch64/inst.isle line 1448.
1428     let expr0_0: Type = I64;
1429     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1430     let expr2_0 = MInst::AluRRRExtend {
1431         alu_op: pattern0_0.clone(),
1432         rd: expr1_0,
1433         rn: pattern1_0,
1434         rm: pattern2_0,
1435         extendop: pattern3_0.clone(),
1436     };
1437     let expr3_0 = C::emit(ctx, &expr2_0);
1438     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1439     return Some(expr4_0);
1440 }
1441 
1442 // Generated as internal constructor for term alu_rr_extend_reg.
1443 pub fn constructor_alu_rr_extend_reg<C: Context>(
1444     ctx: &mut C,
1445     arg0: &ALUOp,
1446     arg1: Reg,
1447     arg2: &ExtendedValue,
1448 ) -> Option<Reg> {
1449     let pattern0_0 = arg0;
1450     let pattern1_0 = arg1;
1451     let pattern2_0 = arg2;
1452     // Rule at src/isa/aarch64/inst.isle line 1456.
1453     let expr0_0 = C::put_extended_in_reg(ctx, pattern2_0);
1454     let expr1_0 = C::get_extended_op(ctx, pattern2_0);
1455     let expr2_0 = constructor_alu_rrr_extend(ctx, pattern0_0, pattern1_0, expr0_0, &expr1_0)?;
1456     return Some(expr2_0);
1457 }
1458 
1459 // Generated as internal constructor for term alu_rrrr.
1460 pub fn constructor_alu_rrrr<C: Context>(
1461     ctx: &mut C,
1462     arg0: &ALUOp3,
1463     arg1: Reg,
1464     arg2: Reg,
1465     arg3: Reg,
1466 ) -> Option<Reg> {
1467     let pattern0_0 = arg0;
1468     let pattern1_0 = arg1;
1469     let pattern2_0 = arg2;
1470     let pattern3_0 = arg3;
1471     // Rule at src/isa/aarch64/inst.isle line 1463.
1472     let expr0_0: Type = I64;
1473     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1474     let expr2_0 = MInst::AluRRRR {
1475         alu_op: pattern0_0.clone(),
1476         rd: expr1_0,
1477         rn: pattern1_0,
1478         rm: pattern2_0,
1479         ra: pattern3_0,
1480     };
1481     let expr3_0 = C::emit(ctx, &expr2_0);
1482     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1483     return Some(expr4_0);
1484 }
1485 
1486 // Generated as internal constructor for term bit_rr.
1487 pub fn constructor_bit_rr<C: Context>(ctx: &mut C, arg0: &BitOp, arg1: Reg) -> Option<Reg> {
1488     let pattern0_0 = arg0;
1489     let pattern1_0 = arg1;
1490     // Rule at src/isa/aarch64/inst.isle line 1470.
1491     let expr0_0: Type = I64;
1492     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1493     let expr2_0 = MInst::BitRR {
1494         op: pattern0_0.clone(),
1495         rd: expr1_0,
1496         rn: pattern1_0,
1497     };
1498     let expr3_0 = C::emit(ctx, &expr2_0);
1499     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1500     return Some(expr4_0);
1501 }
1502 
1503 // Generated as internal constructor for term add64_with_flags.
1504 pub fn constructor_add64_with_flags<C: Context>(
1505     ctx: &mut C,
1506     arg0: Reg,
1507     arg1: Reg,
1508 ) -> Option<ProducesFlags> {
1509     let pattern0_0 = arg0;
1510     let pattern1_0 = arg1;
1511     // Rule at src/isa/aarch64/inst.isle line 1477.
1512     let expr0_0: Type = I64;
1513     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1514     let expr2_0 = ALUOp::AddS64;
1515     let expr3_0 = MInst::AluRRR {
1516         alu_op: expr2_0,
1517         rd: expr1_0,
1518         rn: pattern0_0,
1519         rm: pattern1_0,
1520     };
1521     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1522     let expr5_0 = ProducesFlags::ProducesFlags {
1523         inst: expr3_0,
1524         result: expr4_0,
1525     };
1526     return Some(expr5_0);
1527 }
1528 
1529 // Generated as internal constructor for term adc64.
1530 pub fn constructor_adc64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<ConsumesFlags> {
1531     let pattern0_0 = arg0;
1532     let pattern1_0 = arg1;
1533     // Rule at src/isa/aarch64/inst.isle line 1484.
1534     let expr0_0: Type = I64;
1535     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1536     let expr2_0 = ALUOp::Adc64;
1537     let expr3_0 = MInst::AluRRR {
1538         alu_op: expr2_0,
1539         rd: expr1_0,
1540         rn: pattern0_0,
1541         rm: pattern1_0,
1542     };
1543     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1544     let expr5_0 = ConsumesFlags::ConsumesFlags {
1545         inst: expr3_0,
1546         result: expr4_0,
1547     };
1548     return Some(expr5_0);
1549 }
1550 
1551 // Generated as internal constructor for term sub64_with_flags.
1552 pub fn constructor_sub64_with_flags<C: Context>(
1553     ctx: &mut C,
1554     arg0: Reg,
1555     arg1: Reg,
1556 ) -> Option<ProducesFlags> {
1557     let pattern0_0 = arg0;
1558     let pattern1_0 = arg1;
1559     // Rule at src/isa/aarch64/inst.isle line 1491.
1560     let expr0_0: Type = I64;
1561     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1562     let expr2_0 = ALUOp::SubS64;
1563     let expr3_0 = MInst::AluRRR {
1564         alu_op: expr2_0,
1565         rd: expr1_0,
1566         rn: pattern0_0,
1567         rm: pattern1_0,
1568     };
1569     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1570     let expr5_0 = ProducesFlags::ProducesFlags {
1571         inst: expr3_0,
1572         result: expr4_0,
1573     };
1574     return Some(expr5_0);
1575 }
1576 
1577 // Generated as internal constructor for term cmp64_imm.
1578 pub fn constructor_cmp64_imm<C: Context>(
1579     ctx: &mut C,
1580     arg0: Reg,
1581     arg1: Imm12,
1582 ) -> Option<ProducesFlags> {
1583     let pattern0_0 = arg0;
1584     let pattern1_0 = arg1;
1585     // Rule at src/isa/aarch64/inst.isle line 1497.
1586     let expr0_0 = ALUOp::SubS64;
1587     let expr1_0 = C::writable_zero_reg(ctx);
1588     let expr2_0 = MInst::AluRRImm12 {
1589         alu_op: expr0_0,
1590         rd: expr1_0,
1591         rn: pattern0_0,
1592         imm12: pattern1_0,
1593     };
1594     let expr3_0 = C::zero_reg(ctx);
1595     let expr4_0 = ProducesFlags::ProducesFlags {
1596         inst: expr2_0,
1597         result: expr3_0,
1598     };
1599     return Some(expr4_0);
1600 }
1601 
1602 // Generated as internal constructor for term sbc64.
1603 pub fn constructor_sbc64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<ConsumesFlags> {
1604     let pattern0_0 = arg0;
1605     let pattern1_0 = arg1;
1606     // Rule at src/isa/aarch64/inst.isle line 1503.
1607     let expr0_0: Type = I64;
1608     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1609     let expr2_0 = ALUOp::Sbc64;
1610     let expr3_0 = MInst::AluRRR {
1611         alu_op: expr2_0,
1612         rd: expr1_0,
1613         rn: pattern0_0,
1614         rm: pattern1_0,
1615     };
1616     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1617     let expr5_0 = ConsumesFlags::ConsumesFlags {
1618         inst: expr3_0,
1619         result: expr4_0,
1620     };
1621     return Some(expr5_0);
1622 }
1623 
1624 // Generated as internal constructor for term vec_misc.
1625 pub fn constructor_vec_misc<C: Context>(
1626     ctx: &mut C,
1627     arg0: &VecMisc2,
1628     arg1: Reg,
1629     arg2: &VectorSize,
1630 ) -> Option<Reg> {
1631     let pattern0_0 = arg0;
1632     let pattern1_0 = arg1;
1633     let pattern2_0 = arg2;
1634     // Rule at src/isa/aarch64/inst.isle line 1510.
1635     let expr0_0: Type = I8X16;
1636     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1637     let expr2_0 = MInst::VecMisc {
1638         op: pattern0_0.clone(),
1639         rd: expr1_0,
1640         rn: pattern1_0,
1641         size: pattern2_0.clone(),
1642     };
1643     let expr3_0 = C::emit(ctx, &expr2_0);
1644     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1645     return Some(expr4_0);
1646 }
1647 
1648 // Generated as internal constructor for term vec_rrr_long.
1649 pub fn constructor_vec_rrr_long<C: Context>(
1650     ctx: &mut C,
1651     arg0: &VecRRRLongOp,
1652     arg1: Reg,
1653     arg2: Reg,
1654     arg3: bool,
1655 ) -> Option<Reg> {
1656     let pattern0_0 = arg0;
1657     let pattern1_0 = arg1;
1658     let pattern2_0 = arg2;
1659     let pattern3_0 = arg3;
1660     // Rule at src/isa/aarch64/inst.isle line 1517.
1661     let expr0_0: Type = I8X16;
1662     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1663     let expr2_0 = MInst::VecRRRLong {
1664         alu_op: pattern0_0.clone(),
1665         rd: expr1_0,
1666         rn: pattern1_0,
1667         rm: pattern2_0,
1668         high_half: pattern3_0,
1669     };
1670     let expr3_0 = C::emit(ctx, &expr2_0);
1671     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1672     return Some(expr4_0);
1673 }
1674 
1675 // Generated as internal constructor for term vec_rrrr_long.
1676 pub fn constructor_vec_rrrr_long<C: Context>(
1677     ctx: &mut C,
1678     arg0: &VecRRRLongOp,
1679     arg1: Reg,
1680     arg2: Reg,
1681     arg3: Reg,
1682     arg4: bool,
1683 ) -> Option<Reg> {
1684     let pattern0_0 = arg0;
1685     let pattern1_0 = arg1;
1686     let pattern2_0 = arg2;
1687     let pattern3_0 = arg3;
1688     let pattern4_0 = arg4;
1689     // Rule at src/isa/aarch64/inst.isle line 1527.
1690     let expr0_0: Type = I8X16;
1691     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1692     let expr2_0 = MInst::FpuMove128 {
1693         rd: expr1_0,
1694         rn: pattern1_0,
1695     };
1696     let expr3_0 = C::emit(ctx, &expr2_0);
1697     let expr4_0 = MInst::VecRRRLong {
1698         alu_op: pattern0_0.clone(),
1699         rd: expr1_0,
1700         rn: pattern2_0,
1701         rm: pattern3_0,
1702         high_half: pattern4_0,
1703     };
1704     let expr5_0 = C::emit(ctx, &expr4_0);
1705     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1706     return Some(expr6_0);
1707 }
1708 
1709 // Generated as internal constructor for term vec_rr_narrow.
1710 pub fn constructor_vec_rr_narrow<C: Context>(
1711     ctx: &mut C,
1712     arg0: &VecRRNarrowOp,
1713     arg1: Reg,
1714     arg2: bool,
1715 ) -> Option<Reg> {
1716     let pattern0_0 = arg0;
1717     let pattern1_0 = arg1;
1718     let pattern2_0 = arg2;
1719     // Rule at src/isa/aarch64/inst.isle line 1535.
1720     let expr0_0: Type = I8X16;
1721     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1722     let expr2_0 = MInst::VecRRNarrow {
1723         op: pattern0_0.clone(),
1724         rd: expr1_0,
1725         rn: pattern1_0,
1726         high_half: pattern2_0,
1727     };
1728     let expr3_0 = C::emit(ctx, &expr2_0);
1729     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1730     return Some(expr4_0);
1731 }
1732 
1733 // Generated as internal constructor for term vec_rr_long.
1734 pub fn constructor_vec_rr_long<C: Context>(
1735     ctx: &mut C,
1736     arg0: &VecRRLongOp,
1737     arg1: Reg,
1738     arg2: bool,
1739 ) -> Option<Reg> {
1740     let pattern0_0 = arg0;
1741     let pattern1_0 = arg1;
1742     let pattern2_0 = arg2;
1743     // Rule at src/isa/aarch64/inst.isle line 1542.
1744     let expr0_0: Type = I8X16;
1745     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1746     let expr2_0 = MInst::VecRRLong {
1747         op: pattern0_0.clone(),
1748         rd: expr1_0,
1749         rn: pattern1_0,
1750         high_half: pattern2_0,
1751     };
1752     let expr3_0 = C::emit(ctx, &expr2_0);
1753     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1754     return Some(expr4_0);
1755 }
1756 
1757 // Generated as internal constructor for term mov_to_fpu.
1758 pub fn constructor_mov_to_fpu<C: Context>(
1759     ctx: &mut C,
1760     arg0: Reg,
1761     arg1: &ScalarSize,
1762 ) -> Option<Reg> {
1763     let pattern0_0 = arg0;
1764     let pattern1_0 = arg1;
1765     // Rule at src/isa/aarch64/inst.isle line 1549.
1766     let expr0_0: Type = I8X16;
1767     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1768     let expr2_0 = MInst::MovToFpu {
1769         rd: expr1_0,
1770         rn: pattern0_0,
1771         size: pattern1_0.clone(),
1772     };
1773     let expr3_0 = C::emit(ctx, &expr2_0);
1774     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1775     return Some(expr4_0);
1776 }
1777 
1778 // Generated as internal constructor for term mov_to_vec.
1779 pub fn constructor_mov_to_vec<C: Context>(
1780     ctx: &mut C,
1781     arg0: Reg,
1782     arg1: Reg,
1783     arg2: u8,
1784     arg3: &VectorSize,
1785 ) -> Option<Reg> {
1786     let pattern0_0 = arg0;
1787     let pattern1_0 = arg1;
1788     let pattern2_0 = arg2;
1789     let pattern3_0 = arg3;
1790     // Rule at src/isa/aarch64/inst.isle line 1556.
1791     let expr0_0: Type = I8X16;
1792     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1793     let expr2_0 = MInst::FpuMove128 {
1794         rd: expr1_0,
1795         rn: pattern0_0,
1796     };
1797     let expr3_0 = C::emit(ctx, &expr2_0);
1798     let expr4_0 = MInst::MovToVec {
1799         rd: expr1_0,
1800         rn: pattern1_0,
1801         idx: pattern2_0,
1802         size: pattern3_0.clone(),
1803     };
1804     let expr5_0 = C::emit(ctx, &expr4_0);
1805     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1806     return Some(expr6_0);
1807 }
1808 
1809 // Generated as internal constructor for term mov_from_vec.
1810 pub fn constructor_mov_from_vec<C: Context>(
1811     ctx: &mut C,
1812     arg0: Reg,
1813     arg1: u8,
1814     arg2: &VectorSize,
1815 ) -> Option<Reg> {
1816     let pattern0_0 = arg0;
1817     let pattern1_0 = arg1;
1818     let pattern2_0 = arg2;
1819     // Rule at src/isa/aarch64/inst.isle line 1564.
1820     let expr0_0: Type = I64;
1821     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1822     let expr2_0 = MInst::MovFromVec {
1823         rd: expr1_0,
1824         rn: pattern0_0,
1825         idx: pattern1_0,
1826         size: pattern2_0.clone(),
1827     };
1828     let expr3_0 = C::emit(ctx, &expr2_0);
1829     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1830     return Some(expr4_0);
1831 }
1832 
1833 // Generated as internal constructor for term mov_from_vec_signed.
1834 pub fn constructor_mov_from_vec_signed<C: Context>(
1835     ctx: &mut C,
1836     arg0: Reg,
1837     arg1: u8,
1838     arg2: &VectorSize,
1839     arg3: &OperandSize,
1840 ) -> Option<Reg> {
1841     let pattern0_0 = arg0;
1842     let pattern1_0 = arg1;
1843     let pattern2_0 = arg2;
1844     let pattern3_0 = arg3;
1845     // Rule at src/isa/aarch64/inst.isle line 1571.
1846     let expr0_0: Type = I64;
1847     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1848     let expr2_0 = MInst::MovFromVecSigned {
1849         rd: expr1_0,
1850         rn: pattern0_0,
1851         idx: pattern1_0,
1852         size: pattern2_0.clone(),
1853         scalar_size: pattern3_0.clone(),
1854     };
1855     let expr3_0 = C::emit(ctx, &expr2_0);
1856     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1857     return Some(expr4_0);
1858 }
1859 
1860 // Generated as internal constructor for term extend.
1861 pub fn constructor_extend<C: Context>(
1862     ctx: &mut C,
1863     arg0: Reg,
1864     arg1: bool,
1865     arg2: u8,
1866     arg3: u8,
1867 ) -> Option<Reg> {
1868     let pattern0_0 = arg0;
1869     let pattern1_0 = arg1;
1870     let pattern2_0 = arg2;
1871     let pattern3_0 = arg3;
1872     // Rule at src/isa/aarch64/inst.isle line 1578.
1873     let expr0_0: Type = I64;
1874     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1875     let expr2_0 = MInst::Extend {
1876         rd: expr1_0,
1877         rn: pattern0_0,
1878         signed: pattern1_0,
1879         from_bits: pattern2_0,
1880         to_bits: pattern3_0,
1881     };
1882     let expr3_0 = C::emit(ctx, &expr2_0);
1883     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1884     return Some(expr4_0);
1885 }
1886 
1887 // Generated as internal constructor for term load_acquire.
1888 pub fn constructor_load_acquire<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
1889     let pattern0_0 = arg0;
1890     let pattern1_0 = arg1;
1891     // Rule at src/isa/aarch64/inst.isle line 1585.
1892     let expr0_0: Type = I64;
1893     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1894     let expr2_0 = MInst::LoadAcquire {
1895         access_ty: pattern0_0,
1896         rt: expr1_0,
1897         rn: pattern1_0,
1898     };
1899     let expr3_0 = C::emit(ctx, &expr2_0);
1900     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1901     return Some(expr4_0);
1902 }
1903 
1904 // Generated as internal constructor for term tst64_imm.
1905 pub fn constructor_tst64_imm<C: Context>(
1906     ctx: &mut C,
1907     arg0: Reg,
1908     arg1: ImmLogic,
1909 ) -> Option<ProducesFlags> {
1910     let pattern0_0 = arg0;
1911     let pattern1_0 = arg1;
1912     // Rule at src/isa/aarch64/inst.isle line 1595.
1913     let expr0_0 = ALUOp::AndS64;
1914     let expr1_0 = C::writable_zero_reg(ctx);
1915     let expr2_0 = MInst::AluRRImmLogic {
1916         alu_op: expr0_0,
1917         rd: expr1_0,
1918         rn: pattern0_0,
1919         imml: pattern1_0,
1920     };
1921     let expr3_0 = C::invalid_reg(ctx);
1922     let expr4_0 = ProducesFlags::ProducesFlags {
1923         inst: expr2_0,
1924         result: expr3_0,
1925     };
1926     return Some(expr4_0);
1927 }
1928 
1929 // Generated as internal constructor for term csel.
1930 pub fn constructor_csel<C: Context>(
1931     ctx: &mut C,
1932     arg0: &Cond,
1933     arg1: Reg,
1934     arg2: Reg,
1935 ) -> Option<ConsumesFlags> {
1936     let pattern0_0 = arg0;
1937     let pattern1_0 = arg1;
1938     let pattern2_0 = arg2;
1939     // Rule at src/isa/aarch64/inst.isle line 1608.
1940     let expr0_0: Type = I64;
1941     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1942     let expr2_0 = MInst::CSel {
1943         rd: expr1_0,
1944         cond: pattern0_0.clone(),
1945         rn: pattern1_0,
1946         rm: pattern2_0,
1947     };
1948     let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
1949     let expr4_0 = ConsumesFlags::ConsumesFlags {
1950         inst: expr2_0,
1951         result: expr3_0,
1952     };
1953     return Some(expr4_0);
1954 }
1955 
1956 // Generated as internal constructor for term add.
1957 pub fn constructor_add<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
1958     let pattern0_0 = arg0;
1959     if pattern0_0 == I64 {
1960         let pattern2_0 = arg1;
1961         let pattern3_0 = arg2;
1962         // Rule at src/isa/aarch64/inst.isle line 1617.
1963         let expr0_0 = constructor_add64(ctx, pattern2_0, pattern3_0)?;
1964         return Some(expr0_0);
1965     }
1966     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
1967         let pattern2_0 = arg1;
1968         let pattern3_0 = arg2;
1969         // Rule at src/isa/aarch64/inst.isle line 1616.
1970         let expr0_0 = constructor_add32(ctx, pattern2_0, pattern3_0)?;
1971         return Some(expr0_0);
1972     }
1973     return None;
1974 }
1975 
1976 // Generated as internal constructor for term add32.
1977 pub fn constructor_add32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
1978     let pattern0_0 = arg0;
1979     let pattern1_0 = arg1;
1980     // Rule at src/isa/aarch64/inst.isle line 1620.
1981     let expr0_0 = ALUOp::Add32;
1982     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
1983     return Some(expr1_0);
1984 }
1985 
1986 // Generated as internal constructor for term add64.
1987 pub fn constructor_add64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
1988     let pattern0_0 = arg0;
1989     let pattern1_0 = arg1;
1990     // Rule at src/isa/aarch64/inst.isle line 1623.
1991     let expr0_0 = ALUOp::Add64;
1992     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
1993     return Some(expr1_0);
1994 }
1995 
1996 // Generated as internal constructor for term add_imm.
1997 pub fn constructor_add_imm<C: Context>(
1998     ctx: &mut C,
1999     arg0: Type,
2000     arg1: Reg,
2001     arg2: Imm12,
2002 ) -> Option<Reg> {
2003     let pattern0_0 = arg0;
2004     if pattern0_0 == I64 {
2005         let pattern2_0 = arg1;
2006         let pattern3_0 = arg2;
2007         // Rule at src/isa/aarch64/inst.isle line 1627.
2008         let expr0_0 = constructor_add64_imm(ctx, pattern2_0, pattern3_0)?;
2009         return Some(expr0_0);
2010     }
2011     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2012         let pattern2_0 = arg1;
2013         let pattern3_0 = arg2;
2014         // Rule at src/isa/aarch64/inst.isle line 1626.
2015         let expr0_0 = constructor_add32_imm(ctx, pattern2_0, pattern3_0)?;
2016         return Some(expr0_0);
2017     }
2018     return None;
2019 }
2020 
2021 // Generated as internal constructor for term add32_imm.
2022 pub fn constructor_add32_imm<C: Context>(ctx: &mut C, arg0: Reg, arg1: Imm12) -> Option<Reg> {
2023     let pattern0_0 = arg0;
2024     let pattern1_0 = arg1;
2025     // Rule at src/isa/aarch64/inst.isle line 1630.
2026     let expr0_0 = ALUOp::Add32;
2027     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2028     return Some(expr1_0);
2029 }
2030 
2031 // Generated as internal constructor for term add64_imm.
2032 pub fn constructor_add64_imm<C: Context>(ctx: &mut C, arg0: Reg, arg1: Imm12) -> Option<Reg> {
2033     let pattern0_0 = arg0;
2034     let pattern1_0 = arg1;
2035     // Rule at src/isa/aarch64/inst.isle line 1633.
2036     let expr0_0 = ALUOp::Add64;
2037     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2038     return Some(expr1_0);
2039 }
2040 
2041 // Generated as internal constructor for term add_extend.
2042 pub fn constructor_add_extend<C: Context>(
2043     ctx: &mut C,
2044     arg0: Type,
2045     arg1: Reg,
2046     arg2: &ExtendedValue,
2047 ) -> Option<Reg> {
2048     let pattern0_0 = arg0;
2049     if pattern0_0 == I64 {
2050         let pattern2_0 = arg1;
2051         let pattern3_0 = arg2;
2052         // Rule at src/isa/aarch64/inst.isle line 1637.
2053         let expr0_0 = constructor_add64_extend(ctx, pattern2_0, pattern3_0)?;
2054         return Some(expr0_0);
2055     }
2056     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2057         let pattern2_0 = arg1;
2058         let pattern3_0 = arg2;
2059         // Rule at src/isa/aarch64/inst.isle line 1636.
2060         let expr0_0 = constructor_add32_extend(ctx, pattern2_0, pattern3_0)?;
2061         return Some(expr0_0);
2062     }
2063     return None;
2064 }
2065 
2066 // Generated as internal constructor for term add32_extend.
2067 pub fn constructor_add32_extend<C: Context>(
2068     ctx: &mut C,
2069     arg0: Reg,
2070     arg1: &ExtendedValue,
2071 ) -> Option<Reg> {
2072     let pattern0_0 = arg0;
2073     let pattern1_0 = arg1;
2074     // Rule at src/isa/aarch64/inst.isle line 1640.
2075     let expr0_0 = ALUOp::Add32;
2076     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2077     return Some(expr1_0);
2078 }
2079 
2080 // Generated as internal constructor for term add64_extend.
2081 pub fn constructor_add64_extend<C: Context>(
2082     ctx: &mut C,
2083     arg0: Reg,
2084     arg1: &ExtendedValue,
2085 ) -> Option<Reg> {
2086     let pattern0_0 = arg0;
2087     let pattern1_0 = arg1;
2088     // Rule at src/isa/aarch64/inst.isle line 1643.
2089     let expr0_0 = ALUOp::Add64;
2090     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2091     return Some(expr1_0);
2092 }
2093 
2094 // Generated as internal constructor for term add_shift.
2095 pub fn constructor_add_shift<C: Context>(
2096     ctx: &mut C,
2097     arg0: Type,
2098     arg1: Reg,
2099     arg2: Reg,
2100     arg3: ShiftOpAndAmt,
2101 ) -> Option<Reg> {
2102     let pattern0_0 = arg0;
2103     if pattern0_0 == I64 {
2104         let pattern2_0 = arg1;
2105         let pattern3_0 = arg2;
2106         let pattern4_0 = arg3;
2107         // Rule at src/isa/aarch64/inst.isle line 1647.
2108         let expr0_0 = constructor_add64_shift(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2109         return Some(expr0_0);
2110     }
2111     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2112         let pattern2_0 = arg1;
2113         let pattern3_0 = arg2;
2114         let pattern4_0 = arg3;
2115         // Rule at src/isa/aarch64/inst.isle line 1646.
2116         let expr0_0 = constructor_add32_shift(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2117         return Some(expr0_0);
2118     }
2119     return None;
2120 }
2121 
2122 // Generated as internal constructor for term add32_shift.
2123 pub fn constructor_add32_shift<C: Context>(
2124     ctx: &mut C,
2125     arg0: Reg,
2126     arg1: Reg,
2127     arg2: ShiftOpAndAmt,
2128 ) -> Option<Reg> {
2129     let pattern0_0 = arg0;
2130     let pattern1_0 = arg1;
2131     let pattern2_0 = arg2;
2132     // Rule at src/isa/aarch64/inst.isle line 1650.
2133     let expr0_0 = ALUOp::Add32;
2134     let expr1_0 = constructor_alu_rrr_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2135     return Some(expr1_0);
2136 }
2137 
2138 // Generated as internal constructor for term add64_shift.
2139 pub fn constructor_add64_shift<C: Context>(
2140     ctx: &mut C,
2141     arg0: Reg,
2142     arg1: Reg,
2143     arg2: ShiftOpAndAmt,
2144 ) -> Option<Reg> {
2145     let pattern0_0 = arg0;
2146     let pattern1_0 = arg1;
2147     let pattern2_0 = arg2;
2148     // Rule at src/isa/aarch64/inst.isle line 1653.
2149     let expr0_0 = ALUOp::Add64;
2150     let expr1_0 = constructor_alu_rrr_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2151     return Some(expr1_0);
2152 }
2153 
2154 // Generated as internal constructor for term add_vec.
2155 pub fn constructor_add_vec<C: Context>(
2156     ctx: &mut C,
2157     arg0: Reg,
2158     arg1: Reg,
2159     arg2: &VectorSize,
2160 ) -> Option<Reg> {
2161     let pattern0_0 = arg0;
2162     let pattern1_0 = arg1;
2163     let pattern2_0 = arg2;
2164     // Rule at src/isa/aarch64/inst.isle line 1656.
2165     let expr0_0 = VecALUOp::Add;
2166     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2167     return Some(expr1_0);
2168 }
2169 
2170 // Generated as internal constructor for term sub.
2171 pub fn constructor_sub<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2172     let pattern0_0 = arg0;
2173     if pattern0_0 == I64 {
2174         let pattern2_0 = arg1;
2175         let pattern3_0 = arg2;
2176         // Rule at src/isa/aarch64/inst.isle line 1662.
2177         let expr0_0 = constructor_sub64(ctx, pattern2_0, pattern3_0)?;
2178         return Some(expr0_0);
2179     }
2180     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2181         let pattern2_0 = arg1;
2182         let pattern3_0 = arg2;
2183         // Rule at src/isa/aarch64/inst.isle line 1661.
2184         let expr0_0 = constructor_sub32(ctx, pattern2_0, pattern3_0)?;
2185         return Some(expr0_0);
2186     }
2187     return None;
2188 }
2189 
2190 // Generated as internal constructor for term sub32.
2191 pub fn constructor_sub32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2192     let pattern0_0 = arg0;
2193     let pattern1_0 = arg1;
2194     // Rule at src/isa/aarch64/inst.isle line 1665.
2195     let expr0_0 = ALUOp::Sub32;
2196     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2197     return Some(expr1_0);
2198 }
2199 
2200 // Generated as internal constructor for term sub64.
2201 pub fn constructor_sub64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2202     let pattern0_0 = arg0;
2203     let pattern1_0 = arg1;
2204     // Rule at src/isa/aarch64/inst.isle line 1668.
2205     let expr0_0 = ALUOp::Sub64;
2206     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2207     return Some(expr1_0);
2208 }
2209 
2210 // Generated as internal constructor for term sub_imm.
2211 pub fn constructor_sub_imm<C: Context>(
2212     ctx: &mut C,
2213     arg0: Type,
2214     arg1: Reg,
2215     arg2: Imm12,
2216 ) -> Option<Reg> {
2217     let pattern0_0 = arg0;
2218     if pattern0_0 == I64 {
2219         let pattern2_0 = arg1;
2220         let pattern3_0 = arg2;
2221         // Rule at src/isa/aarch64/inst.isle line 1672.
2222         let expr0_0 = constructor_sub64_imm(ctx, pattern2_0, pattern3_0)?;
2223         return Some(expr0_0);
2224     }
2225     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2226         let pattern2_0 = arg1;
2227         let pattern3_0 = arg2;
2228         // Rule at src/isa/aarch64/inst.isle line 1671.
2229         let expr0_0 = constructor_sub32_imm(ctx, pattern2_0, pattern3_0)?;
2230         return Some(expr0_0);
2231     }
2232     return None;
2233 }
2234 
2235 // Generated as internal constructor for term sub32_imm.
2236 pub fn constructor_sub32_imm<C: Context>(ctx: &mut C, arg0: Reg, arg1: Imm12) -> Option<Reg> {
2237     let pattern0_0 = arg0;
2238     let pattern1_0 = arg1;
2239     // Rule at src/isa/aarch64/inst.isle line 1675.
2240     let expr0_0 = ALUOp::Sub32;
2241     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2242     return Some(expr1_0);
2243 }
2244 
2245 // Generated as internal constructor for term sub64_imm.
2246 pub fn constructor_sub64_imm<C: Context>(ctx: &mut C, arg0: Reg, arg1: Imm12) -> Option<Reg> {
2247     let pattern0_0 = arg0;
2248     let pattern1_0 = arg1;
2249     // Rule at src/isa/aarch64/inst.isle line 1678.
2250     let expr0_0 = ALUOp::Sub64;
2251     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2252     return Some(expr1_0);
2253 }
2254 
2255 // Generated as internal constructor for term sub_extend.
2256 pub fn constructor_sub_extend<C: Context>(
2257     ctx: &mut C,
2258     arg0: Type,
2259     arg1: Reg,
2260     arg2: &ExtendedValue,
2261 ) -> Option<Reg> {
2262     let pattern0_0 = arg0;
2263     if pattern0_0 == I64 {
2264         let pattern2_0 = arg1;
2265         let pattern3_0 = arg2;
2266         // Rule at src/isa/aarch64/inst.isle line 1682.
2267         let expr0_0 = constructor_sub64_extend(ctx, pattern2_0, pattern3_0)?;
2268         return Some(expr0_0);
2269     }
2270     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2271         let pattern2_0 = arg1;
2272         let pattern3_0 = arg2;
2273         // Rule at src/isa/aarch64/inst.isle line 1681.
2274         let expr0_0 = constructor_sub32_extend(ctx, pattern2_0, pattern3_0)?;
2275         return Some(expr0_0);
2276     }
2277     return None;
2278 }
2279 
2280 // Generated as internal constructor for term sub32_extend.
2281 pub fn constructor_sub32_extend<C: Context>(
2282     ctx: &mut C,
2283     arg0: Reg,
2284     arg1: &ExtendedValue,
2285 ) -> Option<Reg> {
2286     let pattern0_0 = arg0;
2287     let pattern1_0 = arg1;
2288     // Rule at src/isa/aarch64/inst.isle line 1685.
2289     let expr0_0 = ALUOp::Sub32;
2290     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2291     return Some(expr1_0);
2292 }
2293 
2294 // Generated as internal constructor for term sub64_extend.
2295 pub fn constructor_sub64_extend<C: Context>(
2296     ctx: &mut C,
2297     arg0: Reg,
2298     arg1: &ExtendedValue,
2299 ) -> Option<Reg> {
2300     let pattern0_0 = arg0;
2301     let pattern1_0 = arg1;
2302     // Rule at src/isa/aarch64/inst.isle line 1688.
2303     let expr0_0 = ALUOp::Sub64;
2304     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2305     return Some(expr1_0);
2306 }
2307 
2308 // Generated as internal constructor for term sub_shift.
2309 pub fn constructor_sub_shift<C: Context>(
2310     ctx: &mut C,
2311     arg0: Type,
2312     arg1: Reg,
2313     arg2: Reg,
2314     arg3: ShiftOpAndAmt,
2315 ) -> Option<Reg> {
2316     let pattern0_0 = arg0;
2317     if pattern0_0 == I64 {
2318         let pattern2_0 = arg1;
2319         let pattern3_0 = arg2;
2320         let pattern4_0 = arg3;
2321         // Rule at src/isa/aarch64/inst.isle line 1692.
2322         let expr0_0 = constructor_sub64_shift(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2323         return Some(expr0_0);
2324     }
2325     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2326         let pattern2_0 = arg1;
2327         let pattern3_0 = arg2;
2328         let pattern4_0 = arg3;
2329         // Rule at src/isa/aarch64/inst.isle line 1691.
2330         let expr0_0 = constructor_sub32_shift(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2331         return Some(expr0_0);
2332     }
2333     return None;
2334 }
2335 
2336 // Generated as internal constructor for term sub32_shift.
2337 pub fn constructor_sub32_shift<C: Context>(
2338     ctx: &mut C,
2339     arg0: Reg,
2340     arg1: Reg,
2341     arg2: ShiftOpAndAmt,
2342 ) -> Option<Reg> {
2343     let pattern0_0 = arg0;
2344     let pattern1_0 = arg1;
2345     let pattern2_0 = arg2;
2346     // Rule at src/isa/aarch64/inst.isle line 1695.
2347     let expr0_0 = ALUOp::Sub32;
2348     let expr1_0 = constructor_alu_rrr_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2349     return Some(expr1_0);
2350 }
2351 
2352 // Generated as internal constructor for term sub64_shift.
2353 pub fn constructor_sub64_shift<C: Context>(
2354     ctx: &mut C,
2355     arg0: Reg,
2356     arg1: Reg,
2357     arg2: ShiftOpAndAmt,
2358 ) -> Option<Reg> {
2359     let pattern0_0 = arg0;
2360     let pattern1_0 = arg1;
2361     let pattern2_0 = arg2;
2362     // Rule at src/isa/aarch64/inst.isle line 1698.
2363     let expr0_0 = ALUOp::Sub64;
2364     let expr1_0 = constructor_alu_rrr_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2365     return Some(expr1_0);
2366 }
2367 
2368 // Generated as internal constructor for term sub_vec.
2369 pub fn constructor_sub_vec<C: Context>(
2370     ctx: &mut C,
2371     arg0: Reg,
2372     arg1: Reg,
2373     arg2: &VectorSize,
2374 ) -> Option<Reg> {
2375     let pattern0_0 = arg0;
2376     let pattern1_0 = arg1;
2377     let pattern2_0 = arg2;
2378     // Rule at src/isa/aarch64/inst.isle line 1701.
2379     let expr0_0 = VecALUOp::Sub;
2380     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2381     return Some(expr1_0);
2382 }
2383 
2384 // Generated as internal constructor for term madd.
2385 pub fn constructor_madd<C: Context>(
2386     ctx: &mut C,
2387     arg0: Type,
2388     arg1: Reg,
2389     arg2: Reg,
2390     arg3: Reg,
2391 ) -> Option<Reg> {
2392     let pattern0_0 = arg0;
2393     if pattern0_0 == I64 {
2394         let pattern2_0 = arg1;
2395         let pattern3_0 = arg2;
2396         let pattern4_0 = arg3;
2397         // Rule at src/isa/aarch64/inst.isle line 1707.
2398         let expr0_0 = constructor_madd64(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2399         return Some(expr0_0);
2400     }
2401     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2402         let pattern2_0 = arg1;
2403         let pattern3_0 = arg2;
2404         let pattern4_0 = arg3;
2405         // Rule at src/isa/aarch64/inst.isle line 1706.
2406         let expr0_0 = constructor_madd32(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2407         return Some(expr0_0);
2408     }
2409     return None;
2410 }
2411 
2412 // Generated as internal constructor for term madd32.
2413 pub fn constructor_madd32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2414     let pattern0_0 = arg0;
2415     let pattern1_0 = arg1;
2416     let pattern2_0 = arg2;
2417     // Rule at src/isa/aarch64/inst.isle line 1710.
2418     let expr0_0 = ALUOp3::MAdd32;
2419     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2420     return Some(expr1_0);
2421 }
2422 
2423 // Generated as internal constructor for term madd64.
2424 pub fn constructor_madd64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2425     let pattern0_0 = arg0;
2426     let pattern1_0 = arg1;
2427     let pattern2_0 = arg2;
2428     // Rule at src/isa/aarch64/inst.isle line 1713.
2429     let expr0_0 = ALUOp3::MAdd64;
2430     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2431     return Some(expr1_0);
2432 }
2433 
2434 // Generated as internal constructor for term msub64.
2435 pub fn constructor_msub64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2436     let pattern0_0 = arg0;
2437     let pattern1_0 = arg1;
2438     let pattern2_0 = arg2;
2439     // Rule at src/isa/aarch64/inst.isle line 1718.
2440     let expr0_0 = ALUOp3::MSub64;
2441     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2442     return Some(expr1_0);
2443 }
2444 
2445 // Generated as internal constructor for term uqadd.
2446 pub fn constructor_uqadd<C: Context>(
2447     ctx: &mut C,
2448     arg0: Reg,
2449     arg1: Reg,
2450     arg2: &VectorSize,
2451 ) -> Option<Reg> {
2452     let pattern0_0 = arg0;
2453     let pattern1_0 = arg1;
2454     let pattern2_0 = arg2;
2455     // Rule at src/isa/aarch64/inst.isle line 1722.
2456     let expr0_0 = VecALUOp::Uqadd;
2457     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2458     return Some(expr1_0);
2459 }
2460 
2461 // Generated as internal constructor for term sqadd.
2462 pub fn constructor_sqadd<C: Context>(
2463     ctx: &mut C,
2464     arg0: Reg,
2465     arg1: Reg,
2466     arg2: &VectorSize,
2467 ) -> Option<Reg> {
2468     let pattern0_0 = arg0;
2469     let pattern1_0 = arg1;
2470     let pattern2_0 = arg2;
2471     // Rule at src/isa/aarch64/inst.isle line 1726.
2472     let expr0_0 = VecALUOp::Sqadd;
2473     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2474     return Some(expr1_0);
2475 }
2476 
2477 // Generated as internal constructor for term uqsub.
2478 pub fn constructor_uqsub<C: Context>(
2479     ctx: &mut C,
2480     arg0: Reg,
2481     arg1: Reg,
2482     arg2: &VectorSize,
2483 ) -> Option<Reg> {
2484     let pattern0_0 = arg0;
2485     let pattern1_0 = arg1;
2486     let pattern2_0 = arg2;
2487     // Rule at src/isa/aarch64/inst.isle line 1730.
2488     let expr0_0 = VecALUOp::Uqsub;
2489     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2490     return Some(expr1_0);
2491 }
2492 
2493 // Generated as internal constructor for term sqsub.
2494 pub fn constructor_sqsub<C: Context>(
2495     ctx: &mut C,
2496     arg0: Reg,
2497     arg1: Reg,
2498     arg2: &VectorSize,
2499 ) -> Option<Reg> {
2500     let pattern0_0 = arg0;
2501     let pattern1_0 = arg1;
2502     let pattern2_0 = arg2;
2503     // Rule at src/isa/aarch64/inst.isle line 1734.
2504     let expr0_0 = VecALUOp::Sqsub;
2505     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2506     return Some(expr1_0);
2507 }
2508 
2509 // Generated as internal constructor for term umulh.
2510 pub fn constructor_umulh<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2511     let pattern0_0 = arg0;
2512     let pattern1_0 = arg1;
2513     // Rule at src/isa/aarch64/inst.isle line 1738.
2514     let expr0_0 = ALUOp::UMulH;
2515     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2516     return Some(expr1_0);
2517 }
2518 
2519 // Generated as internal constructor for term smulh.
2520 pub fn constructor_smulh<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2521     let pattern0_0 = arg0;
2522     let pattern1_0 = arg1;
2523     // Rule at src/isa/aarch64/inst.isle line 1742.
2524     let expr0_0 = ALUOp::SMulH;
2525     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2526     return Some(expr1_0);
2527 }
2528 
2529 // Generated as internal constructor for term mul.
2530 pub fn constructor_mul<C: Context>(
2531     ctx: &mut C,
2532     arg0: Reg,
2533     arg1: Reg,
2534     arg2: &VectorSize,
2535 ) -> Option<Reg> {
2536     let pattern0_0 = arg0;
2537     let pattern1_0 = arg1;
2538     let pattern2_0 = arg2;
2539     // Rule at src/isa/aarch64/inst.isle line 1746.
2540     let expr0_0 = VecALUOp::Mul;
2541     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2542     return Some(expr1_0);
2543 }
2544 
2545 // Generated as internal constructor for term neg.
2546 pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2547     let pattern0_0 = arg0;
2548     let pattern1_0 = arg1;
2549     // Rule at src/isa/aarch64/inst.isle line 1750.
2550     let expr0_0 = VecMisc2::Neg;
2551     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2552     return Some(expr1_0);
2553 }
2554 
2555 // Generated as internal constructor for term rev64.
2556 pub fn constructor_rev64<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2557     let pattern0_0 = arg0;
2558     let pattern1_0 = arg1;
2559     // Rule at src/isa/aarch64/inst.isle line 1754.
2560     let expr0_0 = VecMisc2::Rev64;
2561     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2562     return Some(expr1_0);
2563 }
2564 
2565 // Generated as internal constructor for term xtn64.
2566 pub fn constructor_xtn64<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2567     let pattern0_0 = arg0;
2568     let pattern1_0 = arg1;
2569     // Rule at src/isa/aarch64/inst.isle line 1758.
2570     let expr0_0 = VecRRNarrowOp::Xtn64;
2571     let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2572     return Some(expr1_0);
2573 }
2574 
2575 // Generated as internal constructor for term addp.
2576 pub fn constructor_addp<C: Context>(
2577     ctx: &mut C,
2578     arg0: Reg,
2579     arg1: Reg,
2580     arg2: &VectorSize,
2581 ) -> Option<Reg> {
2582     let pattern0_0 = arg0;
2583     let pattern1_0 = arg1;
2584     let pattern2_0 = arg2;
2585     // Rule at src/isa/aarch64/inst.isle line 1762.
2586     let expr0_0 = VecALUOp::Addp;
2587     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2588     return Some(expr1_0);
2589 }
2590 
2591 // Generated as internal constructor for term addv.
2592 pub fn constructor_addv<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2593     let pattern0_0 = arg0;
2594     let pattern1_0 = arg1;
2595     // Rule at src/isa/aarch64/inst.isle line 1766.
2596     let expr0_0 = VecLanesOp::Addv;
2597     let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2598     return Some(expr1_0);
2599 }
2600 
2601 // Generated as internal constructor for term shll32.
2602 pub fn constructor_shll32<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2603     let pattern0_0 = arg0;
2604     let pattern1_0 = arg1;
2605     // Rule at src/isa/aarch64/inst.isle line 1770.
2606     let expr0_0 = VecRRLongOp::Shll32;
2607     let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2608     return Some(expr1_0);
2609 }
2610 
2611 // Generated as internal constructor for term umlal32.
2612 pub fn constructor_umlal32<C: Context>(
2613     ctx: &mut C,
2614     arg0: Reg,
2615     arg1: Reg,
2616     arg2: Reg,
2617     arg3: bool,
2618 ) -> Option<Reg> {
2619     let pattern0_0 = arg0;
2620     let pattern1_0 = arg1;
2621     let pattern2_0 = arg2;
2622     let pattern3_0 = arg3;
2623     // Rule at src/isa/aarch64/inst.isle line 1774.
2624     let expr0_0 = VecRRRLongOp::Umlal32;
2625     let expr1_0 = constructor_vec_rrrr_long(
2626         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2627     )?;
2628     return Some(expr1_0);
2629 }
2630 
2631 // Generated as internal constructor for term smull8.
2632 pub fn constructor_smull8<C: Context>(
2633     ctx: &mut C,
2634     arg0: Reg,
2635     arg1: Reg,
2636     arg2: bool,
2637 ) -> Option<Reg> {
2638     let pattern0_0 = arg0;
2639     let pattern1_0 = arg1;
2640     let pattern2_0 = arg2;
2641     // Rule at src/isa/aarch64/inst.isle line 1778.
2642     let expr0_0 = VecRRRLongOp::Smull8;
2643     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2644     return Some(expr1_0);
2645 }
2646 
2647 // Generated as internal constructor for term umull8.
2648 pub fn constructor_umull8<C: Context>(
2649     ctx: &mut C,
2650     arg0: Reg,
2651     arg1: Reg,
2652     arg2: bool,
2653 ) -> Option<Reg> {
2654     let pattern0_0 = arg0;
2655     let pattern1_0 = arg1;
2656     let pattern2_0 = arg2;
2657     // Rule at src/isa/aarch64/inst.isle line 1782.
2658     let expr0_0 = VecRRRLongOp::Umull8;
2659     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2660     return Some(expr1_0);
2661 }
2662 
2663 // Generated as internal constructor for term smull16.
2664 pub fn constructor_smull16<C: Context>(
2665     ctx: &mut C,
2666     arg0: Reg,
2667     arg1: Reg,
2668     arg2: bool,
2669 ) -> Option<Reg> {
2670     let pattern0_0 = arg0;
2671     let pattern1_0 = arg1;
2672     let pattern2_0 = arg2;
2673     // Rule at src/isa/aarch64/inst.isle line 1786.
2674     let expr0_0 = VecRRRLongOp::Smull16;
2675     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2676     return Some(expr1_0);
2677 }
2678 
2679 // Generated as internal constructor for term umull16.
2680 pub fn constructor_umull16<C: Context>(
2681     ctx: &mut C,
2682     arg0: Reg,
2683     arg1: Reg,
2684     arg2: bool,
2685 ) -> Option<Reg> {
2686     let pattern0_0 = arg0;
2687     let pattern1_0 = arg1;
2688     let pattern2_0 = arg2;
2689     // Rule at src/isa/aarch64/inst.isle line 1790.
2690     let expr0_0 = VecRRRLongOp::Umull16;
2691     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2692     return Some(expr1_0);
2693 }
2694 
2695 // Generated as internal constructor for term smull32.
2696 pub fn constructor_smull32<C: Context>(
2697     ctx: &mut C,
2698     arg0: Reg,
2699     arg1: Reg,
2700     arg2: bool,
2701 ) -> Option<Reg> {
2702     let pattern0_0 = arg0;
2703     let pattern1_0 = arg1;
2704     let pattern2_0 = arg2;
2705     // Rule at src/isa/aarch64/inst.isle line 1794.
2706     let expr0_0 = VecRRRLongOp::Smull32;
2707     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2708     return Some(expr1_0);
2709 }
2710 
2711 // Generated as internal constructor for term umull32.
2712 pub fn constructor_umull32<C: Context>(
2713     ctx: &mut C,
2714     arg0: Reg,
2715     arg1: Reg,
2716     arg2: bool,
2717 ) -> Option<Reg> {
2718     let pattern0_0 = arg0;
2719     let pattern1_0 = arg1;
2720     let pattern2_0 = arg2;
2721     // Rule at src/isa/aarch64/inst.isle line 1798.
2722     let expr0_0 = VecRRRLongOp::Umull32;
2723     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2724     return Some(expr1_0);
2725 }
2726 
2727 // Generated as internal constructor for term asr64.
2728 pub fn constructor_asr64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2729     let pattern0_0 = arg0;
2730     let pattern1_0 = arg1;
2731     // Rule at src/isa/aarch64/inst.isle line 1802.
2732     let expr0_0 = ALUOp::Asr64;
2733     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2734     return Some(expr1_0);
2735 }
2736 
2737 // Generated as internal constructor for term asr64_imm.
2738 pub fn constructor_asr64_imm<C: Context>(ctx: &mut C, arg0: Reg, arg1: ImmShift) -> Option<Reg> {
2739     let pattern0_0 = arg0;
2740     let pattern1_0 = arg1;
2741     // Rule at src/isa/aarch64/inst.isle line 1805.
2742     let expr0_0 = ALUOp::Asr64;
2743     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2744     return Some(expr1_0);
2745 }
2746 
2747 // Generated as internal constructor for term lsr32.
2748 pub fn constructor_lsr32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2749     let pattern0_0 = arg0;
2750     let pattern1_0 = arg1;
2751     // Rule at src/isa/aarch64/inst.isle line 1809.
2752     let expr0_0 = ALUOp::Lsr32;
2753     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2754     return Some(expr1_0);
2755 }
2756 
2757 // Generated as internal constructor for term lsr32_imm.
2758 pub fn constructor_lsr32_imm<C: Context>(ctx: &mut C, arg0: Reg, arg1: ImmShift) -> Option<Reg> {
2759     let pattern0_0 = arg0;
2760     let pattern1_0 = arg1;
2761     // Rule at src/isa/aarch64/inst.isle line 1812.
2762     let expr0_0 = ALUOp::Lsr32;
2763     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2764     return Some(expr1_0);
2765 }
2766 
2767 // Generated as internal constructor for term lsr64.
2768 pub fn constructor_lsr64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2769     let pattern0_0 = arg0;
2770     let pattern1_0 = arg1;
2771     // Rule at src/isa/aarch64/inst.isle line 1815.
2772     let expr0_0 = ALUOp::Lsr64;
2773     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2774     return Some(expr1_0);
2775 }
2776 
2777 // Generated as internal constructor for term lsr64_imm.
2778 pub fn constructor_lsr64_imm<C: Context>(ctx: &mut C, arg0: Reg, arg1: ImmShift) -> Option<Reg> {
2779     let pattern0_0 = arg0;
2780     let pattern1_0 = arg1;
2781     // Rule at src/isa/aarch64/inst.isle line 1818.
2782     let expr0_0 = ALUOp::Lsr64;
2783     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2784     return Some(expr1_0);
2785 }
2786 
2787 // Generated as internal constructor for term lsl32.
2788 pub fn constructor_lsl32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2789     let pattern0_0 = arg0;
2790     let pattern1_0 = arg1;
2791     // Rule at src/isa/aarch64/inst.isle line 1822.
2792     let expr0_0 = ALUOp::Lsl32;
2793     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2794     return Some(expr1_0);
2795 }
2796 
2797 // Generated as internal constructor for term lsl32_imm.
2798 pub fn constructor_lsl32_imm<C: Context>(ctx: &mut C, arg0: Reg, arg1: ImmShift) -> Option<Reg> {
2799     let pattern0_0 = arg0;
2800     let pattern1_0 = arg1;
2801     // Rule at src/isa/aarch64/inst.isle line 1825.
2802     let expr0_0 = ALUOp::Lsl32;
2803     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2804     return Some(expr1_0);
2805 }
2806 
2807 // Generated as internal constructor for term lsl64.
2808 pub fn constructor_lsl64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2809     let pattern0_0 = arg0;
2810     let pattern1_0 = arg1;
2811     // Rule at src/isa/aarch64/inst.isle line 1828.
2812     let expr0_0 = ALUOp::Lsl64;
2813     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2814     return Some(expr1_0);
2815 }
2816 
2817 // Generated as internal constructor for term lsl64_imm.
2818 pub fn constructor_lsl64_imm<C: Context>(ctx: &mut C, arg0: Reg, arg1: ImmShift) -> Option<Reg> {
2819     let pattern0_0 = arg0;
2820     let pattern1_0 = arg1;
2821     // Rule at src/isa/aarch64/inst.isle line 1831.
2822     let expr0_0 = ALUOp::Lsl64;
2823     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2824     return Some(expr1_0);
2825 }
2826 
2827 // Generated as internal constructor for term udiv64.
2828 pub fn constructor_udiv64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2829     let pattern0_0 = arg0;
2830     let pattern1_0 = arg1;
2831     // Rule at src/isa/aarch64/inst.isle line 1835.
2832     let expr0_0 = ALUOp::UDiv64;
2833     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2834     return Some(expr1_0);
2835 }
2836 
2837 // Generated as internal constructor for term sdiv64.
2838 pub fn constructor_sdiv64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2839     let pattern0_0 = arg0;
2840     let pattern1_0 = arg1;
2841     // Rule at src/isa/aarch64/inst.isle line 1839.
2842     let expr0_0 = ALUOp::SDiv64;
2843     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2844     return Some(expr1_0);
2845 }
2846 
2847 // Generated as internal constructor for term not.
2848 pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2849     let pattern0_0 = arg0;
2850     let pattern1_0 = arg1;
2851     // Rule at src/isa/aarch64/inst.isle line 1843.
2852     let expr0_0 = VecMisc2::Not;
2853     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2854     return Some(expr1_0);
2855 }
2856 
2857 // Generated as internal constructor for term orr_not.
2858 pub fn constructor_orr_not<C: Context>(
2859     ctx: &mut C,
2860     arg0: Type,
2861     arg1: Reg,
2862     arg2: Reg,
2863 ) -> Option<Reg> {
2864     let pattern0_0 = arg0;
2865     if pattern0_0 == I64 {
2866         let pattern2_0 = arg1;
2867         let pattern3_0 = arg2;
2868         // Rule at src/isa/aarch64/inst.isle line 1849.
2869         let expr0_0 = constructor_orr_not64(ctx, pattern2_0, pattern3_0)?;
2870         return Some(expr0_0);
2871     }
2872     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2873         let pattern2_0 = arg1;
2874         let pattern3_0 = arg2;
2875         // Rule at src/isa/aarch64/inst.isle line 1848.
2876         let expr0_0 = constructor_orr_not32(ctx, pattern2_0, pattern3_0)?;
2877         return Some(expr0_0);
2878     }
2879     return None;
2880 }
2881 
2882 // Generated as internal constructor for term orr_not32.
2883 pub fn constructor_orr_not32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2884     let pattern0_0 = arg0;
2885     let pattern1_0 = arg1;
2886     // Rule at src/isa/aarch64/inst.isle line 1852.
2887     let expr0_0 = ALUOp::OrrNot32;
2888     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2889     return Some(expr1_0);
2890 }
2891 
2892 // Generated as internal constructor for term orr_not64.
2893 pub fn constructor_orr_not64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2894     let pattern0_0 = arg0;
2895     let pattern1_0 = arg1;
2896     // Rule at src/isa/aarch64/inst.isle line 1855.
2897     let expr0_0 = ALUOp::OrrNot64;
2898     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2899     return Some(expr1_0);
2900 }
2901 
2902 // Generated as internal constructor for term orr_not_shift.
2903 pub fn constructor_orr_not_shift<C: Context>(
2904     ctx: &mut C,
2905     arg0: Type,
2906     arg1: Reg,
2907     arg2: Reg,
2908     arg3: ShiftOpAndAmt,
2909 ) -> Option<Reg> {
2910     let pattern0_0 = arg0;
2911     if pattern0_0 == I64 {
2912         let pattern2_0 = arg1;
2913         let pattern3_0 = arg2;
2914         let pattern4_0 = arg3;
2915         // Rule at src/isa/aarch64/inst.isle line 1859.
2916         let expr0_0 = constructor_orr_not_shift64(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2917         return Some(expr0_0);
2918     }
2919     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2920         let pattern2_0 = arg1;
2921         let pattern3_0 = arg2;
2922         let pattern4_0 = arg3;
2923         // Rule at src/isa/aarch64/inst.isle line 1858.
2924         let expr0_0 = constructor_orr_not_shift32(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2925         return Some(expr0_0);
2926     }
2927     return None;
2928 }
2929 
2930 // Generated as internal constructor for term orr_not_shift32.
2931 pub fn constructor_orr_not_shift32<C: Context>(
2932     ctx: &mut C,
2933     arg0: Reg,
2934     arg1: Reg,
2935     arg2: ShiftOpAndAmt,
2936 ) -> Option<Reg> {
2937     let pattern0_0 = arg0;
2938     let pattern1_0 = arg1;
2939     let pattern2_0 = arg2;
2940     // Rule at src/isa/aarch64/inst.isle line 1862.
2941     let expr0_0 = ALUOp::OrrNot32;
2942     let expr1_0 = constructor_alu_rrr_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2943     return Some(expr1_0);
2944 }
2945 
2946 // Generated as internal constructor for term orr_not_shift64.
2947 pub fn constructor_orr_not_shift64<C: Context>(
2948     ctx: &mut C,
2949     arg0: Reg,
2950     arg1: Reg,
2951     arg2: ShiftOpAndAmt,
2952 ) -> Option<Reg> {
2953     let pattern0_0 = arg0;
2954     let pattern1_0 = arg1;
2955     let pattern2_0 = arg2;
2956     // Rule at src/isa/aarch64/inst.isle line 1865.
2957     let expr0_0 = ALUOp::OrrNot64;
2958     let expr1_0 = constructor_alu_rrr_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2959     return Some(expr1_0);
2960 }
2961 
2962 // Generated as internal constructor for term orr32.
2963 pub fn constructor_orr32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2964     let pattern0_0 = arg0;
2965     let pattern1_0 = arg1;
2966     // Rule at src/isa/aarch64/inst.isle line 1870.
2967     let expr0_0 = ALUOp::Orr32;
2968     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2969     return Some(expr1_0);
2970 }
2971 
2972 // Generated as internal constructor for term orr32_imm.
2973 pub fn constructor_orr32_imm<C: Context>(ctx: &mut C, arg0: Reg, arg1: ImmLogic) -> Option<Reg> {
2974     let pattern0_0 = arg0;
2975     let pattern1_0 = arg1;
2976     // Rule at src/isa/aarch64/inst.isle line 1873.
2977     let expr0_0 = ALUOp::Orr32;
2978     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2979     return Some(expr1_0);
2980 }
2981 
2982 // Generated as internal constructor for term orr64.
2983 pub fn constructor_orr64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
2984     let pattern0_0 = arg0;
2985     let pattern1_0 = arg1;
2986     // Rule at src/isa/aarch64/inst.isle line 1876.
2987     let expr0_0 = ALUOp::Orr64;
2988     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2989     return Some(expr1_0);
2990 }
2991 
2992 // Generated as internal constructor for term orr64_imm.
2993 pub fn constructor_orr64_imm<C: Context>(ctx: &mut C, arg0: Reg, arg1: ImmLogic) -> Option<Reg> {
2994     let pattern0_0 = arg0;
2995     let pattern1_0 = arg1;
2996     // Rule at src/isa/aarch64/inst.isle line 1879.
2997     let expr0_0 = ALUOp::Orr64;
2998     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2999     return Some(expr1_0);
3000 }
3001 
3002 // Generated as internal constructor for term orr_vec.
3003 pub fn constructor_orr_vec<C: Context>(
3004     ctx: &mut C,
3005     arg0: Reg,
3006     arg1: Reg,
3007     arg2: &VectorSize,
3008 ) -> Option<Reg> {
3009     let pattern0_0 = arg0;
3010     let pattern1_0 = arg1;
3011     let pattern2_0 = arg2;
3012     // Rule at src/isa/aarch64/inst.isle line 1882.
3013     let expr0_0 = VecALUOp::Orr;
3014     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3015     return Some(expr1_0);
3016 }
3017 
3018 // Generated as internal constructor for term and32_imm.
3019 pub fn constructor_and32_imm<C: Context>(ctx: &mut C, arg0: Reg, arg1: ImmLogic) -> Option<Reg> {
3020     let pattern0_0 = arg0;
3021     let pattern1_0 = arg1;
3022     // Rule at src/isa/aarch64/inst.isle line 1887.
3023     let expr0_0 = ALUOp::And32;
3024     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3025     return Some(expr1_0);
3026 }
3027 
3028 // Generated as internal constructor for term and_vec.
3029 pub fn constructor_and_vec<C: Context>(
3030     ctx: &mut C,
3031     arg0: Reg,
3032     arg1: Reg,
3033     arg2: &VectorSize,
3034 ) -> Option<Reg> {
3035     let pattern0_0 = arg0;
3036     let pattern1_0 = arg1;
3037     let pattern2_0 = arg2;
3038     // Rule at src/isa/aarch64/inst.isle line 1890.
3039     let expr0_0 = VecALUOp::And;
3040     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3041     return Some(expr1_0);
3042 }
3043 
3044 // Generated as internal constructor for term eor_vec.
3045 pub fn constructor_eor_vec<C: Context>(
3046     ctx: &mut C,
3047     arg0: Reg,
3048     arg1: Reg,
3049     arg2: &VectorSize,
3050 ) -> Option<Reg> {
3051     let pattern0_0 = arg0;
3052     let pattern1_0 = arg1;
3053     let pattern2_0 = arg2;
3054     // Rule at src/isa/aarch64/inst.isle line 1894.
3055     let expr0_0 = VecALUOp::Eor;
3056     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3057     return Some(expr1_0);
3058 }
3059 
3060 // Generated as internal constructor for term bic_vec.
3061 pub fn constructor_bic_vec<C: Context>(
3062     ctx: &mut C,
3063     arg0: Reg,
3064     arg1: Reg,
3065     arg2: &VectorSize,
3066 ) -> Option<Reg> {
3067     let pattern0_0 = arg0;
3068     let pattern1_0 = arg1;
3069     let pattern2_0 = arg2;
3070     // Rule at src/isa/aarch64/inst.isle line 1898.
3071     let expr0_0 = VecALUOp::Bic;
3072     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3073     return Some(expr1_0);
3074 }
3075 
3076 // Generated as internal constructor for term sshl.
3077 pub fn constructor_sshl<C: Context>(
3078     ctx: &mut C,
3079     arg0: Reg,
3080     arg1: Reg,
3081     arg2: &VectorSize,
3082 ) -> Option<Reg> {
3083     let pattern0_0 = arg0;
3084     let pattern1_0 = arg1;
3085     let pattern2_0 = arg2;
3086     // Rule at src/isa/aarch64/inst.isle line 1902.
3087     let expr0_0 = VecALUOp::Sshl;
3088     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3089     return Some(expr1_0);
3090 }
3091 
3092 // Generated as internal constructor for term ushl.
3093 pub fn constructor_ushl<C: Context>(
3094     ctx: &mut C,
3095     arg0: Reg,
3096     arg1: Reg,
3097     arg2: &VectorSize,
3098 ) -> Option<Reg> {
3099     let pattern0_0 = arg0;
3100     let pattern1_0 = arg1;
3101     let pattern2_0 = arg2;
3102     // Rule at src/isa/aarch64/inst.isle line 1906.
3103     let expr0_0 = VecALUOp::Ushl;
3104     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3105     return Some(expr1_0);
3106 }
3107 
3108 // Generated as internal constructor for term rotr32.
3109 pub fn constructor_rotr32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
3110     let pattern0_0 = arg0;
3111     let pattern1_0 = arg1;
3112     // Rule at src/isa/aarch64/inst.isle line 1911.
3113     let expr0_0 = ALUOp::RotR32;
3114     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3115     return Some(expr1_0);
3116 }
3117 
3118 // Generated as internal constructor for term rotr32_imm.
3119 pub fn constructor_rotr32_imm<C: Context>(ctx: &mut C, arg0: Reg, arg1: ImmShift) -> Option<Reg> {
3120     let pattern0_0 = arg0;
3121     let pattern1_0 = arg1;
3122     // Rule at src/isa/aarch64/inst.isle line 1914.
3123     let expr0_0 = ALUOp::RotR32;
3124     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3125     return Some(expr1_0);
3126 }
3127 
3128 // Generated as internal constructor for term rotr64.
3129 pub fn constructor_rotr64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
3130     let pattern0_0 = arg0;
3131     let pattern1_0 = arg1;
3132     // Rule at src/isa/aarch64/inst.isle line 1917.
3133     let expr0_0 = ALUOp::RotR64;
3134     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3135     return Some(expr1_0);
3136 }
3137 
3138 // Generated as internal constructor for term rotr64_imm.
3139 pub fn constructor_rotr64_imm<C: Context>(ctx: &mut C, arg0: Reg, arg1: ImmShift) -> Option<Reg> {
3140     let pattern0_0 = arg0;
3141     let pattern1_0 = arg1;
3142     // Rule at src/isa/aarch64/inst.isle line 1920.
3143     let expr0_0 = ALUOp::RotR64;
3144     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3145     return Some(expr1_0);
3146 }
3147 
3148 // Generated as internal constructor for term rbit32.
3149 pub fn constructor_rbit32<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3150     let pattern0_0 = arg0;
3151     // Rule at src/isa/aarch64/inst.isle line 1925.
3152     let expr0_0 = BitOp::RBit32;
3153     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0)?;
3154     return Some(expr1_0);
3155 }
3156 
3157 // Generated as internal constructor for term rbit64.
3158 pub fn constructor_rbit64<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3159     let pattern0_0 = arg0;
3160     // Rule at src/isa/aarch64/inst.isle line 1928.
3161     let expr0_0 = BitOp::RBit64;
3162     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0)?;
3163     return Some(expr1_0);
3164 }
3165 
3166 // Generated as internal constructor for term clz32.
3167 pub fn constructor_clz32<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3168     let pattern0_0 = arg0;
3169     // Rule at src/isa/aarch64/inst.isle line 1933.
3170     let expr0_0 = BitOp::Clz32;
3171     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0)?;
3172     return Some(expr1_0);
3173 }
3174 
3175 // Generated as internal constructor for term clz64.
3176 pub fn constructor_clz64<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3177     let pattern0_0 = arg0;
3178     // Rule at src/isa/aarch64/inst.isle line 1936.
3179     let expr0_0 = BitOp::Clz64;
3180     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0)?;
3181     return Some(expr1_0);
3182 }
3183 
3184 // Generated as internal constructor for term cls32.
3185 pub fn constructor_cls32<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3186     let pattern0_0 = arg0;
3187     // Rule at src/isa/aarch64/inst.isle line 1941.
3188     let expr0_0 = BitOp::Cls32;
3189     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0)?;
3190     return Some(expr1_0);
3191 }
3192 
3193 // Generated as internal constructor for term cls64.
3194 pub fn constructor_cls64<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3195     let pattern0_0 = arg0;
3196     // Rule at src/isa/aarch64/inst.isle line 1944.
3197     let expr0_0 = BitOp::Cls64;
3198     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0)?;
3199     return Some(expr1_0);
3200 }
3201 
3202 // Generated as internal constructor for term eon32.
3203 pub fn constructor_eon32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
3204     let pattern0_0 = arg0;
3205     let pattern1_0 = arg1;
3206     // Rule at src/isa/aarch64/inst.isle line 1949.
3207     let expr0_0 = ALUOp::EorNot32;
3208     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3209     return Some(expr1_0);
3210 }
3211 
3212 // Generated as internal constructor for term eon64.
3213 pub fn constructor_eon64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg) -> Option<Reg> {
3214     let pattern0_0 = arg0;
3215     let pattern1_0 = arg1;
3216     // Rule at src/isa/aarch64/inst.isle line 1952.
3217     let expr0_0 = ALUOp::EorNot64;
3218     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3219     return Some(expr1_0);
3220 }
3221 
3222 // Generated as internal constructor for term vec_cnt.
3223 pub fn constructor_vec_cnt<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3224     let pattern0_0 = arg0;
3225     let pattern1_0 = arg1;
3226     // Rule at src/isa/aarch64/inst.isle line 1957.
3227     let expr0_0 = VecMisc2::Cnt;
3228     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3229     return Some(expr1_0);
3230 }
3231 
3232 // Generated as internal constructor for term imm.
3233 pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
3234     let pattern0_0 = arg0;
3235     if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) {
3236         let pattern2_0 = arg1;
3237         let closure3 = || {
3238             let expr0_0: Type = I64;
3239             return Some(expr0_0);
3240         };
3241         if let Some(pattern3_0) = closure3() {
3242             if let Some(pattern4_0) = C::imm_logic_from_u64(ctx, pattern2_0, pattern3_0) {
3243                 // Rule at src/isa/aarch64/inst.isle line 1972.
3244                 let expr0_0 = C::zero_reg(ctx);
3245                 let expr1_0 = constructor_orr64_imm(ctx, expr0_0, pattern4_0)?;
3246                 return Some(expr1_0);
3247             }
3248         }
3249         if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) {
3250             // Rule at src/isa/aarch64/inst.isle line 1964.
3251             let expr0_0 = OperandSize::Size64;
3252             let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?;
3253             return Some(expr1_0);
3254         }
3255         if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) {
3256             // Rule at src/isa/aarch64/inst.isle line 1968.
3257             let expr0_0 = OperandSize::Size64;
3258             let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?;
3259             return Some(expr1_0);
3260         }
3261         // Rule at src/isa/aarch64/inst.isle line 1979.
3262         let expr0_0 = C::load_constant64_full(ctx, pattern2_0);
3263         return Some(expr0_0);
3264     }
3265     return None;
3266 }
3267 
3268 // Generated as internal constructor for term put_in_reg_sext32.
3269 pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3270     let pattern0_0 = arg0;
3271     let pattern1_0 = C::value_type(ctx, pattern0_0);
3272     if pattern1_0 == I32 {
3273         // Rule at src/isa/aarch64/inst.isle line 1990.
3274         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3275         return Some(expr0_0);
3276     }
3277     if pattern1_0 == I64 {
3278         // Rule at src/isa/aarch64/inst.isle line 1991.
3279         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3280         return Some(expr0_0);
3281     }
3282     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3283         // Rule at src/isa/aarch64/inst.isle line 1986.
3284         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3285         let expr1_0: bool = true;
3286         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3287         let expr3_0: u8 = 32;
3288         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3289         return Some(expr4_0);
3290     }
3291     return None;
3292 }
3293 
3294 // Generated as internal constructor for term put_in_reg_zext32.
3295 pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3296     let pattern0_0 = arg0;
3297     let pattern1_0 = C::value_type(ctx, pattern0_0);
3298     if pattern1_0 == I32 {
3299         // Rule at src/isa/aarch64/inst.isle line 1999.
3300         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3301         return Some(expr0_0);
3302     }
3303     if pattern1_0 == I64 {
3304         // Rule at src/isa/aarch64/inst.isle line 2000.
3305         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3306         return Some(expr0_0);
3307     }
3308     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3309         // Rule at src/isa/aarch64/inst.isle line 1995.
3310         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3311         let expr1_0: bool = false;
3312         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3313         let expr3_0: u8 = 32;
3314         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3315         return Some(expr4_0);
3316     }
3317     return None;
3318 }
3319 
3320 // Generated as internal constructor for term put_in_reg_sext64.
3321 pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3322     let pattern0_0 = arg0;
3323     let pattern1_0 = C::value_type(ctx, pattern0_0);
3324     if pattern1_0 == I64 {
3325         // Rule at src/isa/aarch64/inst.isle line 2008.
3326         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3327         return Some(expr0_0);
3328     }
3329     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3330         // Rule at src/isa/aarch64/inst.isle line 2004.
3331         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3332         let expr1_0: bool = true;
3333         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3334         let expr3_0: u8 = 64;
3335         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3336         return Some(expr4_0);
3337     }
3338     return None;
3339 }
3340 
3341 // Generated as internal constructor for term put_in_reg_zext64.
3342 pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3343     let pattern0_0 = arg0;
3344     let pattern1_0 = C::value_type(ctx, pattern0_0);
3345     if pattern1_0 == I64 {
3346         // Rule at src/isa/aarch64/inst.isle line 2016.
3347         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3348         return Some(expr0_0);
3349     }
3350     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3351         // Rule at src/isa/aarch64/inst.isle line 2012.
3352         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3353         let expr1_0: bool = false;
3354         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3355         let expr3_0: u8 = 64;
3356         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3357         return Some(expr4_0);
3358     }
3359     return None;
3360 }
3361 
3362 // Generated as internal constructor for term trap_if_zero_divisor.
3363 pub fn constructor_trap_if_zero_divisor<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3364     let pattern0_0 = arg0;
3365     // Rule at src/isa/aarch64/inst.isle line 2021.
3366     let expr0_0 = C::cond_br_zero(ctx, pattern0_0);
3367     let expr1_0 = C::trap_code_division_by_zero(ctx);
3368     let expr2_0 = MInst::TrapIf {
3369         kind: expr0_0,
3370         trap_code: expr1_0,
3371     };
3372     let expr3_0 = C::emit(ctx, &expr2_0);
3373     return Some(pattern0_0);
3374 }
3375 
3376 // Generated as internal constructor for term size_from_ty.
3377 pub fn constructor_size_from_ty<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
3378     let pattern0_0 = arg0;
3379     if pattern0_0 == I64 {
3380         // Rule at src/isa/aarch64/inst.isle line 2027.
3381         let expr0_0 = OperandSize::Size64;
3382         return Some(expr0_0);
3383     }
3384     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
3385         // Rule at src/isa/aarch64/inst.isle line 2026.
3386         let expr0_0 = OperandSize::Size32;
3387         return Some(expr0_0);
3388     }
3389     return None;
3390 }
3391 
3392 // Generated as internal constructor for term trap_if_div_overflow.
3393 pub fn constructor_trap_if_div_overflow<C: Context>(
3394     ctx: &mut C,
3395     arg0: Type,
3396     arg1: Reg,
3397     arg2: Reg,
3398 ) -> Option<Reg> {
3399     let pattern0_0 = arg0;
3400     let pattern1_0 = arg1;
3401     let pattern2_0 = arg2;
3402     // Rule at src/isa/aarch64/inst.isle line 2033.
3403     let expr0_0 = constructor_adds_op(ctx, pattern0_0)?;
3404     let expr1_0 = C::writable_zero_reg(ctx);
3405     let expr2_0: u8 = 1;
3406     let expr3_0 = C::u8_into_imm12(ctx, expr2_0);
3407     let expr4_0 = MInst::AluRRImm12 {
3408         alu_op: expr0_0,
3409         rd: expr1_0,
3410         rn: pattern2_0,
3411         imm12: expr3_0,
3412     };
3413     let expr5_0 = C::emit(ctx, &expr4_0);
3414     let expr6_0 = constructor_size_from_ty(ctx, pattern0_0)?;
3415     let expr7_0: u8 = 1;
3416     let expr8_0 = C::u8_into_uimm5(ctx, expr7_0);
3417     let expr9_0: bool = false;
3418     let expr10_0: bool = false;
3419     let expr11_0: bool = false;
3420     let expr12_0: bool = false;
3421     let expr13_0 = C::nzcv(ctx, expr9_0, expr10_0, expr11_0, expr12_0);
3422     let expr14_0 = Cond::Eq;
3423     let expr15_0 = MInst::CCmpImm {
3424         size: expr6_0,
3425         rn: pattern1_0,
3426         imm: expr8_0,
3427         nzcv: expr13_0,
3428         cond: expr14_0,
3429     };
3430     let expr16_0 = C::emit(ctx, &expr15_0);
3431     let expr17_0 = Cond::Vs;
3432     let expr18_0 = C::cond_br_cond(ctx, &expr17_0);
3433     let expr19_0 = C::trap_code_integer_overflow(ctx);
3434     let expr20_0 = MInst::TrapIf {
3435         kind: expr18_0,
3436         trap_code: expr19_0,
3437     };
3438     let expr21_0 = C::emit(ctx, &expr20_0);
3439     return Some(pattern1_0);
3440 }
3441 
3442 // Generated as internal constructor for term adds_op.
3443 pub fn constructor_adds_op<C: Context>(ctx: &mut C, arg0: Type) -> Option<ALUOp> {
3444     let pattern0_0 = arg0;
3445     if pattern0_0 == I64 {
3446         // Rule at src/isa/aarch64/inst.isle line 2053.
3447         let expr0_0 = ALUOp::AddS64;
3448         return Some(expr0_0);
3449     }
3450     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
3451         // Rule at src/isa/aarch64/inst.isle line 2052.
3452         let expr0_0 = ALUOp::AddS32;
3453         return Some(expr0_0);
3454     }
3455     return None;
3456 }
3457 
3458 // Generated as internal constructor for term alu_rs_imm_logic_commutative.
3459 pub fn constructor_alu_rs_imm_logic_commutative<C: Context>(
3460     ctx: &mut C,
3461     arg0: &ALUOp,
3462     arg1: Type,
3463     arg2: Value,
3464     arg3: Value,
3465 ) -> Option<Reg> {
3466     let pattern0_0 = arg0;
3467     let pattern1_0 = arg1;
3468     let pattern2_0 = arg2;
3469     if let Some(pattern3_0) = C::def_inst(ctx, pattern2_0) {
3470         let pattern4_0 = C::inst_data(ctx, pattern3_0);
3471         match &pattern4_0 {
3472             &InstructionData::UnaryImm {
3473                 opcode: ref pattern5_0,
3474                 imm: pattern5_1,
3475             } => {
3476                 if let &Opcode::Iconst = &pattern5_0 {
3477                     let closure7 = || {
3478                         return Some(pattern1_0);
3479                     };
3480                     if let Some(pattern7_0) = closure7() {
3481                         if let Some(pattern8_0) =
3482                             C::imm_logic_from_imm64(ctx, pattern5_1, pattern7_0)
3483                         {
3484                             let pattern9_0 = arg3;
3485                             // Rule at src/isa/aarch64/inst.isle line 2083.
3486                             let expr0_0 = C::put_in_reg(ctx, pattern9_0);
3487                             let expr1_0 =
3488                                 constructor_alu_rr_imm_logic(ctx, pattern0_0, expr0_0, pattern8_0)?;
3489                             return Some(expr1_0);
3490                         }
3491                     }
3492                 }
3493             }
3494             &InstructionData::Binary {
3495                 opcode: ref pattern5_0,
3496                 args: ref pattern5_1,
3497             } => {
3498                 if let &Opcode::Ishl = &pattern5_0 {
3499                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
3500                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3501                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
3502                         if let &InstructionData::UnaryImm {
3503                             opcode: ref pattern10_0,
3504                             imm: pattern10_1,
3505                         } = &pattern9_0
3506                         {
3507                             if let &Opcode::Iconst = &pattern10_0 {
3508                                 let closure12 = || {
3509                                     return Some(pattern1_0);
3510                                 };
3511                                 if let Some(pattern12_0) = closure12() {
3512                                     if let Some(pattern13_0) =
3513                                         C::lshl_from_imm64(ctx, pattern10_1, pattern12_0)
3514                                     {
3515                                         let pattern14_0 = arg3;
3516                                         // Rule at src/isa/aarch64/inst.isle line 2089.
3517                                         let expr0_0 = C::put_in_reg(ctx, pattern14_0);
3518                                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3519                                         let expr2_0 = constructor_alu_rrr_shift(
3520                                             ctx,
3521                                             pattern0_0,
3522                                             expr0_0,
3523                                             expr1_0,
3524                                             pattern13_0,
3525                                         )?;
3526                                         return Some(expr2_0);
3527                                     }
3528                                 }
3529                             }
3530                         }
3531                     }
3532                 }
3533             }
3534             _ => {}
3535         }
3536     }
3537     let pattern3_0 = arg3;
3538     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3539         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3540         match &pattern5_0 {
3541             &InstructionData::UnaryImm {
3542                 opcode: ref pattern6_0,
3543                 imm: pattern6_1,
3544             } => {
3545                 if let &Opcode::Iconst = &pattern6_0 {
3546                     let closure8 = || {
3547                         return Some(pattern1_0);
3548                     };
3549                     if let Some(pattern8_0) = closure8() {
3550                         if let Some(pattern9_0) =
3551                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3552                         {
3553                             // Rule at src/isa/aarch64/inst.isle line 2081.
3554                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3555                             let expr1_0 =
3556                                 constructor_alu_rr_imm_logic(ctx, pattern0_0, expr0_0, pattern9_0)?;
3557                             return Some(expr1_0);
3558                         }
3559                     }
3560                 }
3561             }
3562             &InstructionData::Binary {
3563                 opcode: ref pattern6_0,
3564                 args: ref pattern6_1,
3565             } => {
3566                 if let &Opcode::Ishl = &pattern6_0 {
3567                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, &pattern6_1);
3568                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3569                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3570                         if let &InstructionData::UnaryImm {
3571                             opcode: ref pattern11_0,
3572                             imm: pattern11_1,
3573                         } = &pattern10_0
3574                         {
3575                             if let &Opcode::Iconst = &pattern11_0 {
3576                                 let closure13 = || {
3577                                     return Some(pattern1_0);
3578                                 };
3579                                 if let Some(pattern13_0) = closure13() {
3580                                     if let Some(pattern14_0) =
3581                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3582                                     {
3583                                         // Rule at src/isa/aarch64/inst.isle line 2087.
3584                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3585                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3586                                         let expr2_0 = constructor_alu_rrr_shift(
3587                                             ctx,
3588                                             pattern0_0,
3589                                             expr0_0,
3590                                             expr1_0,
3591                                             pattern14_0,
3592                                         )?;
3593                                         return Some(expr2_0);
3594                                     }
3595                                 }
3596                             }
3597                         }
3598                     }
3599                 }
3600             }
3601             _ => {}
3602         }
3603     }
3604     // Rule at src/isa/aarch64/inst.isle line 2077.
3605     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3606     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3607     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, expr1_0)?;
3608     return Some(expr2_0);
3609 }
3610 
3611 // Generated as internal constructor for term alu_rs_imm_logic.
3612 pub fn constructor_alu_rs_imm_logic<C: Context>(
3613     ctx: &mut C,
3614     arg0: &ALUOp,
3615     arg1: Type,
3616     arg2: Value,
3617     arg3: Value,
3618 ) -> Option<Reg> {
3619     let pattern0_0 = arg0;
3620     let pattern1_0 = arg1;
3621     let pattern2_0 = arg2;
3622     let pattern3_0 = arg3;
3623     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3624         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3625         match &pattern5_0 {
3626             &InstructionData::UnaryImm {
3627                 opcode: ref pattern6_0,
3628                 imm: pattern6_1,
3629             } => {
3630                 if let &Opcode::Iconst = &pattern6_0 {
3631                     let closure8 = || {
3632                         return Some(pattern1_0);
3633                     };
3634                     if let Some(pattern8_0) = closure8() {
3635                         if let Some(pattern9_0) =
3636                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3637                         {
3638                             // Rule at src/isa/aarch64/inst.isle line 2097.
3639                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3640                             let expr1_0 =
3641                                 constructor_alu_rr_imm_logic(ctx, pattern0_0, expr0_0, pattern9_0)?;
3642                             return Some(expr1_0);
3643                         }
3644                     }
3645                 }
3646             }
3647             &InstructionData::Binary {
3648                 opcode: ref pattern6_0,
3649                 args: ref pattern6_1,
3650             } => {
3651                 if let &Opcode::Ishl = &pattern6_0 {
3652                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, &pattern6_1);
3653                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3654                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3655                         if let &InstructionData::UnaryImm {
3656                             opcode: ref pattern11_0,
3657                             imm: pattern11_1,
3658                         } = &pattern10_0
3659                         {
3660                             if let &Opcode::Iconst = &pattern11_0 {
3661                                 let closure13 = || {
3662                                     return Some(pattern1_0);
3663                                 };
3664                                 if let Some(pattern13_0) = closure13() {
3665                                     if let Some(pattern14_0) =
3666                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3667                                     {
3668                                         // Rule at src/isa/aarch64/inst.isle line 2099.
3669                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3670                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3671                                         let expr2_0 = constructor_alu_rrr_shift(
3672                                             ctx,
3673                                             pattern0_0,
3674                                             expr0_0,
3675                                             expr1_0,
3676                                             pattern14_0,
3677                                         )?;
3678                                         return Some(expr2_0);
3679                                     }
3680                                 }
3681                             }
3682                         }
3683                     }
3684                 }
3685             }
3686             _ => {}
3687         }
3688     }
3689     // Rule at src/isa/aarch64/inst.isle line 2095.
3690     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3691     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3692     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, expr1_0)?;
3693     return Some(expr2_0);
3694 }
3695 
3696 // Generated as internal constructor for term i128_alu_bitop.
3697 pub fn constructor_i128_alu_bitop<C: Context>(
3698     ctx: &mut C,
3699     arg0: &ALUOp,
3700     arg1: Value,
3701     arg2: Value,
3702 ) -> Option<ValueRegs> {
3703     let pattern0_0 = arg0;
3704     let pattern1_0 = arg1;
3705     let pattern2_0 = arg2;
3706     // Rule at src/isa/aarch64/inst.isle line 2107.
3707     let expr0_0 = C::put_in_regs(ctx, pattern1_0);
3708     let expr1_0: usize = 0;
3709     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3710     let expr3_0: usize = 1;
3711     let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
3712     let expr5_0 = C::put_in_regs(ctx, pattern2_0);
3713     let expr6_0: usize = 0;
3714     let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
3715     let expr8_0: usize = 1;
3716     let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
3717     let expr10_0 = constructor_alu_rrr(ctx, pattern0_0, expr2_0, expr7_0)?;
3718     let expr11_0 = constructor_alu_rrr(ctx, pattern0_0, expr4_0, expr9_0)?;
3719     let expr12_0 = C::value_regs(ctx, expr10_0, expr11_0);
3720     return Some(expr12_0);
3721 }
3722 
3723 // Generated as internal constructor for term lower.
3724 pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<ValueRegs> {
3725     let pattern0_0 = arg0;
3726     if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
3727         let pattern2_0 = C::value_type(ctx, pattern1_0);
3728         if pattern2_0 == I8 {
3729             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3730             if let &InstructionData::Unary {
3731                 opcode: ref pattern5_0,
3732                 arg: pattern5_1,
3733             } = &pattern4_0
3734             {
3735                 match &pattern5_0 {
3736                     &Opcode::Bitrev => {
3737                         // Rule at src/isa/aarch64/lower.isle line 1013.
3738                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3739                         let expr1_0 = constructor_rbit32(ctx, expr0_0)?;
3740                         let expr2_0: u8 = 24;
3741                         let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0);
3742                         let expr4_0 = constructor_lsr32_imm(ctx, expr1_0, expr3_0)?;
3743                         let expr5_0 = C::value_reg(ctx, expr4_0);
3744                         return Some(expr5_0);
3745                     }
3746                     &Opcode::Clz => {
3747                         // Rule at src/isa/aarch64/lower.isle line 1038.
3748                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3749                         let expr1_0 = constructor_clz32(ctx, expr0_0)?;
3750                         let expr2_0: u8 = 24;
3751                         let expr3_0 = C::u8_into_imm12(ctx, expr2_0);
3752                         let expr4_0 = constructor_sub32_imm(ctx, expr1_0, expr3_0)?;
3753                         let expr5_0 = C::value_reg(ctx, expr4_0);
3754                         return Some(expr5_0);
3755                     }
3756                     &Opcode::Cls => {
3757                         // Rule at src/isa/aarch64/lower.isle line 1095.
3758                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3759                         let expr1_0 = constructor_cls32(ctx, expr0_0)?;
3760                         let expr2_0: u8 = 24;
3761                         let expr3_0 = C::u8_into_imm12(ctx, expr2_0);
3762                         let expr4_0 = constructor_sub32_imm(ctx, expr1_0, expr3_0)?;
3763                         let expr5_0 = C::value_reg(ctx, expr4_0);
3764                         return Some(expr5_0);
3765                     }
3766                     &Opcode::Ctz => {
3767                         // Rule at src/isa/aarch64/lower.isle line 1073.
3768                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3769                         let expr1_0 = constructor_rbit32(ctx, expr0_0)?;
3770                         let expr2_0: Type = I32;
3771                         let expr3_0: u64 = 8388608;
3772                         let expr4_0 = C::u64_into_imm_logic(ctx, expr2_0, expr3_0);
3773                         let expr5_0 = constructor_orr32_imm(ctx, expr1_0, expr4_0)?;
3774                         let expr6_0 = constructor_clz32(ctx, expr5_0)?;
3775                         let expr7_0 = C::value_reg(ctx, expr6_0);
3776                         return Some(expr7_0);
3777                     }
3778                     &Opcode::Popcnt => {
3779                         // Rule at src/isa/aarch64/lower.isle line 1152.
3780                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3781                         let expr1_0 = ScalarSize::Size32;
3782                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3783                         let expr3_0 = VectorSize::Size8x8;
3784                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3785                         let expr5_0: u8 = 0;
3786                         let expr6_0 = VectorSize::Size8x16;
3787                         let expr7_0 = constructor_mov_from_vec(ctx, expr4_0, expr5_0, &expr6_0)?;
3788                         let expr8_0 = C::value_reg(ctx, expr7_0);
3789                         return Some(expr8_0);
3790                     }
3791                     _ => {}
3792                 }
3793             }
3794         }
3795         if pattern2_0 == I16 {
3796             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3797             if let &InstructionData::Unary {
3798                 opcode: ref pattern5_0,
3799                 arg: pattern5_1,
3800             } = &pattern4_0
3801             {
3802                 match &pattern5_0 {
3803                     &Opcode::Bitrev => {
3804                         // Rule at src/isa/aarch64/lower.isle line 1019.
3805                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3806                         let expr1_0 = constructor_rbit32(ctx, expr0_0)?;
3807                         let expr2_0: u8 = 16;
3808                         let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0);
3809                         let expr4_0 = constructor_lsr32_imm(ctx, expr1_0, expr3_0)?;
3810                         let expr5_0 = C::value_reg(ctx, expr4_0);
3811                         return Some(expr5_0);
3812                     }
3813                     &Opcode::Clz => {
3814                         // Rule at src/isa/aarch64/lower.isle line 1041.
3815                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3816                         let expr1_0 = constructor_clz32(ctx, expr0_0)?;
3817                         let expr2_0: u8 = 16;
3818                         let expr3_0 = C::u8_into_imm12(ctx, expr2_0);
3819                         let expr4_0 = constructor_sub32_imm(ctx, expr1_0, expr3_0)?;
3820                         let expr5_0 = C::value_reg(ctx, expr4_0);
3821                         return Some(expr5_0);
3822                     }
3823                     &Opcode::Cls => {
3824                         // Rule at src/isa/aarch64/lower.isle line 1098.
3825                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3826                         let expr1_0 = constructor_cls32(ctx, expr0_0)?;
3827                         let expr2_0: u8 = 16;
3828                         let expr3_0 = C::u8_into_imm12(ctx, expr2_0);
3829                         let expr4_0 = constructor_sub32_imm(ctx, expr1_0, expr3_0)?;
3830                         let expr5_0 = C::value_reg(ctx, expr4_0);
3831                         return Some(expr5_0);
3832                     }
3833                     &Opcode::Ctz => {
3834                         // Rule at src/isa/aarch64/lower.isle line 1076.
3835                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3836                         let expr1_0 = constructor_rbit32(ctx, expr0_0)?;
3837                         let expr2_0: Type = I32;
3838                         let expr3_0: u64 = 32768;
3839                         let expr4_0 = C::u64_into_imm_logic(ctx, expr2_0, expr3_0);
3840                         let expr5_0 = constructor_orr32_imm(ctx, expr1_0, expr4_0)?;
3841                         let expr6_0 = constructor_clz32(ctx, expr5_0)?;
3842                         let expr7_0 = C::value_reg(ctx, expr6_0);
3843                         return Some(expr7_0);
3844                     }
3845                     &Opcode::Popcnt => {
3846                         // Rule at src/isa/aarch64/lower.isle line 1160.
3847                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3848                         let expr1_0 = ScalarSize::Size32;
3849                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3850                         let expr3_0 = VectorSize::Size8x8;
3851                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3852                         let expr5_0 = VectorSize::Size8x8;
3853                         let expr6_0 = constructor_addp(ctx, expr4_0, expr4_0, &expr5_0)?;
3854                         let expr7_0: u8 = 0;
3855                         let expr8_0 = VectorSize::Size8x16;
3856                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3857                         let expr10_0 = C::value_reg(ctx, expr9_0);
3858                         return Some(expr10_0);
3859                     }
3860                     _ => {}
3861                 }
3862             }
3863         }
3864         if pattern2_0 == I32 {
3865             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3866             match &pattern4_0 {
3867                 &InstructionData::Binary {
3868                     opcode: ref pattern5_0,
3869                     args: ref pattern5_1,
3870                 } => {
3871                     match &pattern5_0 {
3872                         &Opcode::Rotl => {
3873                             let (pattern7_0, pattern7_1) =
3874                                 C::unpack_value_array_2(ctx, &pattern5_1);
3875                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3876                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3877                                 if let &InstructionData::UnaryImm {
3878                                     opcode: ref pattern10_0,
3879                                     imm: pattern10_1,
3880                                 } = &pattern9_0
3881                                 {
3882                                     if let &Opcode::Iconst = &pattern10_0 {
3883                                         let closure12 = || {
3884                                             let expr0_0: Type = I32;
3885                                             return Some(expr0_0);
3886                                         };
3887                                         if let Some(pattern12_0) = closure12() {
3888                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3889                                                 ctx,
3890                                                 pattern10_1,
3891                                                 pattern12_0,
3892                                             ) {
3893                                                 // Rule at src/isa/aarch64/lower.isle line 896.
3894                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
3895                                                 let expr1_0: Type = I32;
3896                                                 let expr2_0 =
3897                                                     C::negate_imm_shift(ctx, expr1_0, pattern13_0);
3898                                                 let expr3_0 =
3899                                                     constructor_rotr32_imm(ctx, expr0_0, expr2_0)?;
3900                                                 let expr4_0 = C::value_reg(ctx, expr3_0);
3901                                                 return Some(expr4_0);
3902                                             }
3903                                         }
3904                                     }
3905                                 }
3906                             }
3907                             // Rule at src/isa/aarch64/lower.isle line 886.
3908                             let expr0_0 = C::zero_reg(ctx);
3909                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
3910                             let expr2_0 = constructor_sub32(ctx, expr0_0, expr1_0)?;
3911                             let expr3_0 = C::put_in_reg(ctx, pattern7_0);
3912                             let expr4_0 = constructor_rotr32(ctx, expr3_0, expr2_0)?;
3913                             let expr5_0 = C::value_reg(ctx, expr4_0);
3914                             return Some(expr5_0);
3915                         }
3916                         &Opcode::Rotr => {
3917                             let (pattern7_0, pattern7_1) =
3918                                 C::unpack_value_array_2(ctx, &pattern5_1);
3919                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3920                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3921                                 if let &InstructionData::UnaryImm {
3922                                     opcode: ref pattern10_0,
3923                                     imm: pattern10_1,
3924                                 } = &pattern9_0
3925                                 {
3926                                     if let &Opcode::Iconst = &pattern10_0 {
3927                                         let closure12 = || {
3928                                             let expr0_0: Type = I32;
3929                                             return Some(expr0_0);
3930                                         };
3931                                         if let Some(pattern12_0) = closure12() {
3932                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3933                                                 ctx,
3934                                                 pattern10_1,
3935                                                 pattern12_0,
3936                                             ) {
3937                                                 // Rule at src/isa/aarch64/lower.isle line 940.
3938                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
3939                                                 let expr1_0 = constructor_rotr32_imm(
3940                                                     ctx,
3941                                                     expr0_0,
3942                                                     pattern13_0,
3943                                                 )?;
3944                                                 let expr2_0 = C::value_reg(ctx, expr1_0);
3945                                                 return Some(expr2_0);
3946                                             }
3947                                         }
3948                                     }
3949                                 }
3950                             }
3951                             // Rule at src/isa/aarch64/lower.isle line 928.
3952                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
3953                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
3954                             let expr2_0 = constructor_rotr32(ctx, expr0_0, expr1_0)?;
3955                             let expr3_0 = C::value_reg(ctx, expr2_0);
3956                             return Some(expr3_0);
3957                         }
3958                         _ => {}
3959                     }
3960                 }
3961                 &InstructionData::Unary {
3962                     opcode: ref pattern5_0,
3963                     arg: pattern5_1,
3964                 } => {
3965                     match &pattern5_0 {
3966                         &Opcode::Bitrev => {
3967                             // Rule at src/isa/aarch64/lower.isle line 1022.
3968                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3969                             let expr1_0 = constructor_rbit32(ctx, expr0_0)?;
3970                             let expr2_0 = C::value_reg(ctx, expr1_0);
3971                             return Some(expr2_0);
3972                         }
3973                         &Opcode::Clz => {
3974                             // Rule at src/isa/aarch64/lower.isle line 1044.
3975                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3976                             let expr1_0 = constructor_clz32(ctx, expr0_0)?;
3977                             let expr2_0 = C::value_reg(ctx, expr1_0);
3978                             return Some(expr2_0);
3979                         }
3980                         &Opcode::Cls => {
3981                             // Rule at src/isa/aarch64/lower.isle line 1101.
3982                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3983                             let expr1_0 = constructor_cls32(ctx, expr0_0)?;
3984                             let expr2_0 = C::value_reg(ctx, expr1_0);
3985                             return Some(expr2_0);
3986                         }
3987                         &Opcode::Ctz => {
3988                             // Rule at src/isa/aarch64/lower.isle line 1079.
3989                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3990                             let expr1_0 = constructor_rbit32(ctx, expr0_0)?;
3991                             let expr2_0 = constructor_clz32(ctx, expr1_0)?;
3992                             let expr3_0 = C::value_reg(ctx, expr2_0);
3993                             return Some(expr3_0);
3994                         }
3995                         &Opcode::Popcnt => {
3996                             // Rule at src/isa/aarch64/lower.isle line 1168.
3997                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3998                             let expr1_0 = ScalarSize::Size32;
3999                             let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
4000                             let expr3_0 = VectorSize::Size8x8;
4001                             let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
4002                             let expr5_0 = VectorSize::Size8x8;
4003                             let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
4004                             let expr7_0: u8 = 0;
4005                             let expr8_0 = VectorSize::Size8x16;
4006                             let expr9_0 =
4007                                 constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
4008                             let expr10_0 = C::value_reg(ctx, expr9_0);
4009                             return Some(expr10_0);
4010                         }
4011                         _ => {}
4012                     }
4013                 }
4014                 _ => {}
4015             }
4016         }
4017         if pattern2_0 == I64 {
4018             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4019             match &pattern4_0 {
4020                 &InstructionData::Binary {
4021                     opcode: ref pattern5_0,
4022                     args: ref pattern5_1,
4023                 } => {
4024                     match &pattern5_0 {
4025                         &Opcode::Umulhi => {
4026                             let (pattern7_0, pattern7_1) =
4027                                 C::unpack_value_array_2(ctx, &pattern5_1);
4028                             // Rule at src/isa/aarch64/lower.isle line 374.
4029                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
4030                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
4031                             let expr2_0 = constructor_umulh(ctx, expr0_0, expr1_0)?;
4032                             let expr3_0 = C::value_reg(ctx, expr2_0);
4033                             return Some(expr3_0);
4034                         }
4035                         &Opcode::Smulhi => {
4036                             let (pattern7_0, pattern7_1) =
4037                                 C::unpack_value_array_2(ctx, &pattern5_1);
4038                             // Rule at src/isa/aarch64/lower.isle line 360.
4039                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
4040                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
4041                             let expr2_0 = constructor_smulh(ctx, expr0_0, expr1_0)?;
4042                             let expr3_0 = C::value_reg(ctx, expr2_0);
4043                             return Some(expr3_0);
4044                         }
4045                         &Opcode::Band => {
4046                             let (pattern7_0, pattern7_1) =
4047                                 C::unpack_value_array_2(ctx, &pattern5_1);
4048                             // Rule at src/isa/aarch64/lower.isle line 609.
4049                             let expr0_0 = ALUOp::And64;
4050                             let expr1_0: Type = I64;
4051                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
4052                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4053                             )?;
4054                             let expr3_0 = C::value_reg(ctx, expr2_0);
4055                             return Some(expr3_0);
4056                         }
4057                         &Opcode::Bor => {
4058                             let (pattern7_0, pattern7_1) =
4059                                 C::unpack_value_array_2(ctx, &pattern5_1);
4060                             // Rule at src/isa/aarch64/lower.isle line 622.
4061                             let expr0_0 = ALUOp::Orr64;
4062                             let expr1_0: Type = I64;
4063                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
4064                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4065                             )?;
4066                             let expr3_0 = C::value_reg(ctx, expr2_0);
4067                             return Some(expr3_0);
4068                         }
4069                         &Opcode::Bxor => {
4070                             let (pattern7_0, pattern7_1) =
4071                                 C::unpack_value_array_2(ctx, &pattern5_1);
4072                             // Rule at src/isa/aarch64/lower.isle line 635.
4073                             let expr0_0 = ALUOp::Eor64;
4074                             let expr1_0: Type = I64;
4075                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
4076                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4077                             )?;
4078                             let expr3_0 = C::value_reg(ctx, expr2_0);
4079                             return Some(expr3_0);
4080                         }
4081                         &Opcode::BandNot => {
4082                             let (pattern7_0, pattern7_1) =
4083                                 C::unpack_value_array_2(ctx, &pattern5_1);
4084                             // Rule at src/isa/aarch64/lower.isle line 648.
4085                             let expr0_0 = ALUOp::AndNot64;
4086                             let expr1_0: Type = I64;
4087                             let expr2_0 = constructor_alu_rs_imm_logic(
4088                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4089                             )?;
4090                             let expr3_0 = C::value_reg(ctx, expr2_0);
4091                             return Some(expr3_0);
4092                         }
4093                         &Opcode::BorNot => {
4094                             let (pattern7_0, pattern7_1) =
4095                                 C::unpack_value_array_2(ctx, &pattern5_1);
4096                             // Rule at src/isa/aarch64/lower.isle line 661.
4097                             let expr0_0 = ALUOp::OrrNot64;
4098                             let expr1_0: Type = I64;
4099                             let expr2_0 = constructor_alu_rs_imm_logic(
4100                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4101                             )?;
4102                             let expr3_0 = C::value_reg(ctx, expr2_0);
4103                             return Some(expr3_0);
4104                         }
4105                         &Opcode::BxorNot => {
4106                             let (pattern7_0, pattern7_1) =
4107                                 C::unpack_value_array_2(ctx, &pattern5_1);
4108                             // Rule at src/isa/aarch64/lower.isle line 671.
4109                             let expr0_0 = ALUOp::EorNot64;
4110                             let expr1_0: Type = I64;
4111                             let expr2_0 = constructor_alu_rs_imm_logic(
4112                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4113                             )?;
4114                             let expr3_0 = C::value_reg(ctx, expr2_0);
4115                             return Some(expr3_0);
4116                         }
4117                         &Opcode::Rotl => {
4118                             let (pattern7_0, pattern7_1) =
4119                                 C::unpack_value_array_2(ctx, &pattern5_1);
4120                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
4121                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
4122                                 if let &InstructionData::UnaryImm {
4123                                     opcode: ref pattern10_0,
4124                                     imm: pattern10_1,
4125                                 } = &pattern9_0
4126                                 {
4127                                     if let &Opcode::Iconst = &pattern10_0 {
4128                                         let closure12 = || {
4129                                             let expr0_0: Type = I64;
4130                                             return Some(expr0_0);
4131                                         };
4132                                         if let Some(pattern12_0) = closure12() {
4133                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4134                                                 ctx,
4135                                                 pattern10_1,
4136                                                 pattern12_0,
4137                                             ) {
4138                                                 // Rule at src/isa/aarch64/lower.isle line 900.
4139                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
4140                                                 let expr1_0: Type = I64;
4141                                                 let expr2_0 =
4142                                                     C::negate_imm_shift(ctx, expr1_0, pattern13_0);
4143                                                 let expr3_0 =
4144                                                     constructor_rotr64_imm(ctx, expr0_0, expr2_0)?;
4145                                                 let expr4_0 = C::value_reg(ctx, expr3_0);
4146                                                 return Some(expr4_0);
4147                                             }
4148                                         }
4149                                     }
4150                                 }
4151                             }
4152                             // Rule at src/isa/aarch64/lower.isle line 891.
4153                             let expr0_0 = C::zero_reg(ctx);
4154                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
4155                             let expr2_0 = constructor_sub64(ctx, expr0_0, expr1_0)?;
4156                             let expr3_0 = C::put_in_reg(ctx, pattern7_0);
4157                             let expr4_0 = constructor_rotr64(ctx, expr3_0, expr2_0)?;
4158                             let expr5_0 = C::value_reg(ctx, expr4_0);
4159                             return Some(expr5_0);
4160                         }
4161                         &Opcode::Rotr => {
4162                             let (pattern7_0, pattern7_1) =
4163                                 C::unpack_value_array_2(ctx, &pattern5_1);
4164                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
4165                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
4166                                 if let &InstructionData::UnaryImm {
4167                                     opcode: ref pattern10_0,
4168                                     imm: pattern10_1,
4169                                 } = &pattern9_0
4170                                 {
4171                                     if let &Opcode::Iconst = &pattern10_0 {
4172                                         let closure12 = || {
4173                                             let expr0_0: Type = I64;
4174                                             return Some(expr0_0);
4175                                         };
4176                                         if let Some(pattern12_0) = closure12() {
4177                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4178                                                 ctx,
4179                                                 pattern10_1,
4180                                                 pattern12_0,
4181                                             ) {
4182                                                 // Rule at src/isa/aarch64/lower.isle line 944.
4183                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
4184                                                 let expr1_0 = constructor_rotr64_imm(
4185                                                     ctx,
4186                                                     expr0_0,
4187                                                     pattern13_0,
4188                                                 )?;
4189                                                 let expr2_0 = C::value_reg(ctx, expr1_0);
4190                                                 return Some(expr2_0);
4191                                             }
4192                                         }
4193                                     }
4194                                 }
4195                             }
4196                             // Rule at src/isa/aarch64/lower.isle line 932.
4197                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
4198                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
4199                             let expr2_0 = constructor_rotr64(ctx, expr0_0, expr1_0)?;
4200                             let expr3_0 = C::value_reg(ctx, expr2_0);
4201                             return Some(expr3_0);
4202                         }
4203                         &Opcode::Ishl => {
4204                             let (pattern7_0, pattern7_1) =
4205                                 C::unpack_value_array_2(ctx, &pattern5_1);
4206                             // Rule at src/isa/aarch64/lower.isle line 683.
4207                             let expr0_0 = ALUOp::Lsl64;
4208                             let expr1_0: Type = I64;
4209                             let expr2_0 = C::put_in_reg(ctx, pattern7_0);
4210                             let expr3_0 =
4211                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4212                             let expr4_0 = C::value_reg(ctx, expr3_0);
4213                             return Some(expr4_0);
4214                         }
4215                         &Opcode::Ushr => {
4216                             let (pattern7_0, pattern7_1) =
4217                                 C::unpack_value_array_2(ctx, &pattern5_1);
4218                             // Rule at src/isa/aarch64/lower.isle line 771.
4219                             let expr0_0 = ALUOp::Lsr64;
4220                             let expr1_0: Type = I64;
4221                             let expr2_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
4222                             let expr3_0 =
4223                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4224                             let expr4_0 = C::value_reg(ctx, expr3_0);
4225                             return Some(expr4_0);
4226                         }
4227                         &Opcode::Sshr => {
4228                             let (pattern7_0, pattern7_1) =
4229                                 C::unpack_value_array_2(ctx, &pattern5_1);
4230                             // Rule at src/isa/aarch64/lower.isle line 820.
4231                             let expr0_0 = ALUOp::Asr64;
4232                             let expr1_0: Type = I64;
4233                             let expr2_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
4234                             let expr3_0 =
4235                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4236                             let expr4_0 = C::value_reg(ctx, expr3_0);
4237                             return Some(expr4_0);
4238                         }
4239                         _ => {}
4240                     }
4241                 }
4242                 &InstructionData::Unary {
4243                     opcode: ref pattern5_0,
4244                     arg: pattern5_1,
4245                 } => {
4246                     match &pattern5_0 {
4247                         &Opcode::Bitrev => {
4248                             // Rule at src/isa/aarch64/lower.isle line 1025.
4249                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4250                             let expr1_0 = constructor_rbit64(ctx, expr0_0)?;
4251                             let expr2_0 = C::value_reg(ctx, expr1_0);
4252                             return Some(expr2_0);
4253                         }
4254                         &Opcode::Clz => {
4255                             // Rule at src/isa/aarch64/lower.isle line 1047.
4256                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4257                             let expr1_0 = constructor_clz64(ctx, expr0_0)?;
4258                             let expr2_0 = C::value_reg(ctx, expr1_0);
4259                             return Some(expr2_0);
4260                         }
4261                         &Opcode::Cls => {
4262                             // Rule at src/isa/aarch64/lower.isle line 1104.
4263                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4264                             let expr1_0 = constructor_cls64(ctx, expr0_0)?;
4265                             let expr2_0 = C::value_reg(ctx, expr1_0);
4266                             return Some(expr2_0);
4267                         }
4268                         &Opcode::Ctz => {
4269                             // Rule at src/isa/aarch64/lower.isle line 1082.
4270                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4271                             let expr1_0 = constructor_rbit64(ctx, expr0_0)?;
4272                             let expr2_0 = constructor_clz64(ctx, expr1_0)?;
4273                             let expr3_0 = C::value_reg(ctx, expr2_0);
4274                             return Some(expr3_0);
4275                         }
4276                         &Opcode::Popcnt => {
4277                             // Rule at src/isa/aarch64/lower.isle line 1176.
4278                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4279                             let expr1_0 = ScalarSize::Size64;
4280                             let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
4281                             let expr3_0 = VectorSize::Size8x8;
4282                             let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
4283                             let expr5_0 = VectorSize::Size8x8;
4284                             let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
4285                             let expr7_0: u8 = 0;
4286                             let expr8_0 = VectorSize::Size8x16;
4287                             let expr9_0 =
4288                                 constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
4289                             let expr10_0 = C::value_reg(ctx, expr9_0);
4290                             return Some(expr10_0);
4291                         }
4292                         _ => {}
4293                     }
4294                 }
4295                 _ => {}
4296             }
4297         }
4298         if pattern2_0 == I128 {
4299             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4300             match &pattern4_0 {
4301                 &InstructionData::Binary {
4302                     opcode: ref pattern5_0,
4303                     args: ref pattern5_1,
4304                 } => {
4305                     match &pattern5_0 {
4306                         &Opcode::Iadd => {
4307                             let (pattern7_0, pattern7_1) =
4308                                 C::unpack_value_array_2(ctx, &pattern5_1);
4309                             // Rule at src/isa/aarch64/lower.isle line 79.
4310                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4311                             let expr1_0: usize = 0;
4312                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4313                             let expr3_0: usize = 1;
4314                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4315                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4316                             let expr6_0: usize = 0;
4317                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4318                             let expr8_0: usize = 1;
4319                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4320                             let expr10_0 = constructor_add64_with_flags(ctx, expr2_0, expr7_0)?;
4321                             let expr11_0 = constructor_adc64(ctx, expr4_0, expr9_0)?;
4322                             let expr12_0 = constructor_with_flags(ctx, &expr10_0, &expr11_0)?;
4323                             return Some(expr12_0);
4324                         }
4325                         &Opcode::Isub => {
4326                             let (pattern7_0, pattern7_1) =
4327                                 C::unpack_value_array_2(ctx, &pattern5_1);
4328                             // Rule at src/isa/aarch64/lower.isle line 130.
4329                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4330                             let expr1_0: usize = 0;
4331                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4332                             let expr3_0: usize = 1;
4333                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4334                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4335                             let expr6_0: usize = 0;
4336                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4337                             let expr8_0: usize = 1;
4338                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4339                             let expr10_0 = constructor_sub64_with_flags(ctx, expr2_0, expr7_0)?;
4340                             let expr11_0 = constructor_sbc64(ctx, expr4_0, expr9_0)?;
4341                             let expr12_0 = constructor_with_flags(ctx, &expr10_0, &expr11_0)?;
4342                             return Some(expr12_0);
4343                         }
4344                         &Opcode::Imul => {
4345                             let (pattern7_0, pattern7_1) =
4346                                 C::unpack_value_array_2(ctx, &pattern5_1);
4347                             // Rule at src/isa/aarch64/lower.isle line 185.
4348                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4349                             let expr1_0: usize = 0;
4350                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4351                             let expr3_0: usize = 1;
4352                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4353                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4354                             let expr6_0: usize = 0;
4355                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4356                             let expr8_0: usize = 1;
4357                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4358                             let expr10_0 = constructor_umulh(ctx, expr2_0, expr7_0)?;
4359                             let expr11_0 = constructor_madd64(ctx, expr2_0, expr9_0, expr10_0)?;
4360                             let expr12_0 = constructor_madd64(ctx, expr4_0, expr7_0, expr11_0)?;
4361                             let expr13_0 = C::zero_reg(ctx);
4362                             let expr14_0 = constructor_madd64(ctx, expr2_0, expr7_0, expr13_0)?;
4363                             let expr15_0 = C::value_regs(ctx, expr14_0, expr12_0);
4364                             return Some(expr15_0);
4365                         }
4366                         &Opcode::Band => {
4367                             let (pattern7_0, pattern7_1) =
4368                                 C::unpack_value_array_2(ctx, &pattern5_1);
4369                             // Rule at src/isa/aarch64/lower.isle line 612.
4370                             let expr0_0 = ALUOp::And64;
4371                             let expr1_0 =
4372                                 constructor_i128_alu_bitop(ctx, &expr0_0, pattern7_0, pattern7_1)?;
4373                             return Some(expr1_0);
4374                         }
4375                         &Opcode::Bor => {
4376                             let (pattern7_0, pattern7_1) =
4377                                 C::unpack_value_array_2(ctx, &pattern5_1);
4378                             // Rule at src/isa/aarch64/lower.isle line 625.
4379                             let expr0_0 = ALUOp::Orr64;
4380                             let expr1_0 =
4381                                 constructor_i128_alu_bitop(ctx, &expr0_0, pattern7_0, pattern7_1)?;
4382                             return Some(expr1_0);
4383                         }
4384                         &Opcode::Bxor => {
4385                             let (pattern7_0, pattern7_1) =
4386                                 C::unpack_value_array_2(ctx, &pattern5_1);
4387                             // Rule at src/isa/aarch64/lower.isle line 638.
4388                             let expr0_0 = ALUOp::Eor64;
4389                             let expr1_0 =
4390                                 constructor_i128_alu_bitop(ctx, &expr0_0, pattern7_0, pattern7_1)?;
4391                             return Some(expr1_0);
4392                         }
4393                         &Opcode::BandNot => {
4394                             let (pattern7_0, pattern7_1) =
4395                                 C::unpack_value_array_2(ctx, &pattern5_1);
4396                             // Rule at src/isa/aarch64/lower.isle line 651.
4397                             let expr0_0 = ALUOp::AndNot64;
4398                             let expr1_0 =
4399                                 constructor_i128_alu_bitop(ctx, &expr0_0, pattern7_0, pattern7_1)?;
4400                             return Some(expr1_0);
4401                         }
4402                         &Opcode::BorNot => {
4403                             let (pattern7_0, pattern7_1) =
4404                                 C::unpack_value_array_2(ctx, &pattern5_1);
4405                             // Rule at src/isa/aarch64/lower.isle line 664.
4406                             let expr0_0 = ALUOp::OrrNot64;
4407                             let expr1_0 =
4408                                 constructor_i128_alu_bitop(ctx, &expr0_0, pattern7_0, pattern7_1)?;
4409                             return Some(expr1_0);
4410                         }
4411                         &Opcode::BxorNot => {
4412                             let (pattern7_0, pattern7_1) =
4413                                 C::unpack_value_array_2(ctx, &pattern5_1);
4414                             // Rule at src/isa/aarch64/lower.isle line 674.
4415                             let expr0_0 = ALUOp::EorNot64;
4416                             let expr1_0 =
4417                                 constructor_i128_alu_bitop(ctx, &expr0_0, pattern7_0, pattern7_1)?;
4418                             return Some(expr1_0);
4419                         }
4420                         &Opcode::Rotl => {
4421                             let (pattern7_0, pattern7_1) =
4422                                 C::unpack_value_array_2(ctx, &pattern5_1);
4423                             // Rule at src/isa/aarch64/lower.isle line 909.
4424                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4425                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4426                             let expr2_0: usize = 0;
4427                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4428                             let expr4_0: Type = I64;
4429                             let expr5_0: u64 = 128;
4430                             let expr6_0 = constructor_imm(ctx, expr4_0, expr5_0)?;
4431                             let expr7_0 = constructor_sub64(ctx, expr6_0, expr3_0)?;
4432                             let expr8_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4433                             let expr9_0 = constructor_lower_ushr128(ctx, expr0_0, expr7_0)?;
4434                             let expr10_0: usize = 0;
4435                             let expr11_0 = C::value_regs_get(ctx, expr8_0, expr10_0);
4436                             let expr12_0: usize = 0;
4437                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4438                             let expr14_0 = constructor_orr64(ctx, expr11_0, expr13_0)?;
4439                             let expr15_0: usize = 1;
4440                             let expr16_0 = C::value_regs_get(ctx, expr8_0, expr15_0);
4441                             let expr17_0: usize = 1;
4442                             let expr18_0 = C::value_regs_get(ctx, expr9_0, expr17_0);
4443                             let expr19_0 = constructor_orr64(ctx, expr16_0, expr18_0)?;
4444                             let expr20_0 = C::value_regs(ctx, expr14_0, expr19_0);
4445                             return Some(expr20_0);
4446                         }
4447                         &Opcode::Rotr => {
4448                             let (pattern7_0, pattern7_1) =
4449                                 C::unpack_value_array_2(ctx, &pattern5_1);
4450                             // Rule at src/isa/aarch64/lower.isle line 996.
4451                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4452                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4453                             let expr2_0: usize = 0;
4454                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4455                             let expr4_0: Type = I64;
4456                             let expr5_0: u64 = 128;
4457                             let expr6_0 = constructor_imm(ctx, expr4_0, expr5_0)?;
4458                             let expr7_0 = constructor_sub64(ctx, expr6_0, expr3_0)?;
4459                             let expr8_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4460                             let expr9_0 = constructor_lower_shl128(ctx, expr0_0, expr7_0)?;
4461                             let expr10_0: usize = 1;
4462                             let expr11_0 = C::value_regs_get(ctx, expr8_0, expr10_0);
4463                             let expr12_0: usize = 1;
4464                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4465                             let expr14_0 = constructor_orr64(ctx, expr11_0, expr13_0)?;
4466                             let expr15_0: usize = 0;
4467                             let expr16_0 = C::value_regs_get(ctx, expr8_0, expr15_0);
4468                             let expr17_0: usize = 0;
4469                             let expr18_0 = C::value_regs_get(ctx, expr9_0, expr17_0);
4470                             let expr19_0 = constructor_orr64(ctx, expr16_0, expr18_0)?;
4471                             let expr20_0 = C::value_regs(ctx, expr19_0, expr14_0);
4472                             return Some(expr20_0);
4473                         }
4474                         &Opcode::Ishl => {
4475                             let (pattern7_0, pattern7_1) =
4476                                 C::unpack_value_array_2(ctx, &pattern5_1);
4477                             // Rule at src/isa/aarch64/lower.isle line 687.
4478                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4479                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4480                             let expr2_0: usize = 0;
4481                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4482                             let expr4_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4483                             return Some(expr4_0);
4484                         }
4485                         &Opcode::Ushr => {
4486                             let (pattern7_0, pattern7_1) =
4487                                 C::unpack_value_array_2(ctx, &pattern5_1);
4488                             // Rule at src/isa/aarch64/lower.isle line 775.
4489                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4490                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4491                             let expr2_0: usize = 0;
4492                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4493                             let expr4_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4494                             return Some(expr4_0);
4495                         }
4496                         &Opcode::Sshr => {
4497                             let (pattern7_0, pattern7_1) =
4498                                 C::unpack_value_array_2(ctx, &pattern5_1);
4499                             // Rule at src/isa/aarch64/lower.isle line 824.
4500                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4501                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4502                             let expr2_0: usize = 0;
4503                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4504                             let expr4_0 = constructor_lower_sshr128(ctx, expr0_0, expr3_0)?;
4505                             return Some(expr4_0);
4506                         }
4507                         _ => {}
4508                     }
4509                 }
4510                 &InstructionData::Unary {
4511                     opcode: ref pattern5_0,
4512                     arg: pattern5_1,
4513                 } => {
4514                     match &pattern5_0 {
4515                         &Opcode::Bnot => {
4516                             // Rule at src/isa/aarch64/lower.isle line 590.
4517                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4518                             let expr1_0: usize = 0;
4519                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4520                             let expr3_0: usize = 1;
4521                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4522                             let expr5_0 = C::zero_reg(ctx);
4523                             let expr6_0 = constructor_orr_not64(ctx, expr5_0, expr2_0)?;
4524                             let expr7_0 = C::zero_reg(ctx);
4525                             let expr8_0 = constructor_orr_not64(ctx, expr7_0, expr4_0)?;
4526                             let expr9_0 = C::value_regs(ctx, expr6_0, expr8_0);
4527                             return Some(expr9_0);
4528                         }
4529                         &Opcode::Bitrev => {
4530                             // Rule at src/isa/aarch64/lower.isle line 1028.
4531                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4532                             let expr1_0: usize = 0;
4533                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4534                             let expr3_0 = constructor_rbit64(ctx, expr2_0)?;
4535                             let expr4_0: usize = 1;
4536                             let expr5_0 = C::value_regs_get(ctx, expr0_0, expr4_0);
4537                             let expr6_0 = constructor_rbit64(ctx, expr5_0)?;
4538                             let expr7_0 = C::value_regs(ctx, expr6_0, expr3_0);
4539                             return Some(expr7_0);
4540                         }
4541                         &Opcode::Clz => {
4542                             // Rule at src/isa/aarch64/lower.isle line 1050.
4543                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4544                             let expr1_0 = constructor_lower_clz128(ctx, expr0_0)?;
4545                             return Some(expr1_0);
4546                         }
4547                         &Opcode::Cls => {
4548                             // Rule at src/isa/aarch64/lower.isle line 1116.
4549                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4550                             let expr1_0: usize = 0;
4551                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4552                             let expr3_0: usize = 1;
4553                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4554                             let expr5_0 = constructor_cls64(ctx, expr2_0)?;
4555                             let expr6_0 = constructor_cls64(ctx, expr4_0)?;
4556                             let expr7_0 = constructor_eon64(ctx, expr4_0, expr2_0)?;
4557                             let expr8_0: u8 = 63;
4558                             let expr9_0 = C::imm_shift_from_u8(ctx, expr8_0);
4559                             let expr10_0 = constructor_lsr64_imm(ctx, expr7_0, expr9_0)?;
4560                             let expr11_0 = constructor_madd64(ctx, expr5_0, expr10_0, expr10_0)?;
4561                             let expr12_0: u8 = 63;
4562                             let expr13_0 = C::u8_into_imm12(ctx, expr12_0);
4563                             let expr14_0 = constructor_cmp64_imm(ctx, expr6_0, expr13_0)?;
4564                             let expr15_0 = Cond::Eq;
4565                             let expr16_0 = C::zero_reg(ctx);
4566                             let expr17_0 = constructor_csel(ctx, &expr15_0, expr11_0, expr16_0)?;
4567                             let expr18_0 = constructor_with_flags_1(ctx, &expr14_0, &expr17_0)?;
4568                             let expr19_0 = constructor_add64(ctx, expr18_0, expr6_0)?;
4569                             let expr20_0: Type = I64;
4570                             let expr21_0: u64 = 0;
4571                             let expr22_0 = constructor_imm(ctx, expr20_0, expr21_0)?;
4572                             let expr23_0 = C::value_regs(ctx, expr19_0, expr22_0);
4573                             return Some(expr23_0);
4574                         }
4575                         &Opcode::Ctz => {
4576                             // Rule at src/isa/aarch64/lower.isle line 1085.
4577                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4578                             let expr1_0: usize = 0;
4579                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4580                             let expr3_0 = constructor_rbit64(ctx, expr2_0)?;
4581                             let expr4_0: usize = 1;
4582                             let expr5_0 = C::value_regs_get(ctx, expr0_0, expr4_0);
4583                             let expr6_0 = constructor_rbit64(ctx, expr5_0)?;
4584                             let expr7_0 = C::value_regs(ctx, expr6_0, expr3_0);
4585                             let expr8_0 = constructor_lower_clz128(ctx, expr7_0)?;
4586                             return Some(expr8_0);
4587                         }
4588                         &Opcode::Popcnt => {
4589                             // Rule at src/isa/aarch64/lower.isle line 1184.
4590                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4591                             let expr1_0: usize = 0;
4592                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4593                             let expr3_0 = ScalarSize::Size64;
4594                             let expr4_0 = constructor_mov_to_fpu(ctx, expr2_0, &expr3_0)?;
4595                             let expr5_0: usize = 1;
4596                             let expr6_0 = C::value_regs_get(ctx, expr0_0, expr5_0);
4597                             let expr7_0: u8 = 1;
4598                             let expr8_0 = VectorSize::Size64x2;
4599                             let expr9_0 =
4600                                 constructor_mov_to_vec(ctx, expr4_0, expr6_0, expr7_0, &expr8_0)?;
4601                             let expr10_0 = VectorSize::Size8x16;
4602                             let expr11_0 = constructor_vec_cnt(ctx, expr9_0, &expr10_0)?;
4603                             let expr12_0 = VectorSize::Size8x16;
4604                             let expr13_0 = constructor_addv(ctx, expr11_0, &expr12_0)?;
4605                             let expr14_0: u8 = 0;
4606                             let expr15_0 = VectorSize::Size8x16;
4607                             let expr16_0 =
4608                                 constructor_mov_from_vec(ctx, expr13_0, expr14_0, &expr15_0)?;
4609                             let expr17_0: Type = I64;
4610                             let expr18_0: u64 = 0;
4611                             let expr19_0 = constructor_imm(ctx, expr17_0, expr18_0)?;
4612                             let expr20_0 = C::value_regs(ctx, expr16_0, expr19_0);
4613                             return Some(expr20_0);
4614                         }
4615                         &Opcode::Uextend => {
4616                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4617                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4618                                 if let &InstructionData::BinaryImm8 {
4619                                     opcode: ref pattern9_0,
4620                                     arg: pattern9_1,
4621                                     imm: pattern9_2,
4622                                 } = &pattern8_0
4623                                 {
4624                                     if let &Opcode::Extractlane = &pattern9_0 {
4625                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4626                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
4627                                         // Rule at src/isa/aarch64/lower.isle line 514.
4628                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4629                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
4630                                         let expr2_0 = constructor_mov_from_vec(
4631                                             ctx,
4632                                             expr0_0,
4633                                             pattern12_0,
4634                                             &expr1_0,
4635                                         )?;
4636                                         let expr3_0: Type = I64;
4637                                         let expr4_0: u64 = 0;
4638                                         let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
4639                                         let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
4640                                         return Some(expr6_0);
4641                                     }
4642                                 }
4643                             }
4644                             // Rule at src/isa/aarch64/lower.isle line 509.
4645                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
4646                             let expr1_0: Type = I64;
4647                             let expr2_0: u64 = 0;
4648                             let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
4649                             let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
4650                             return Some(expr4_0);
4651                         }
4652                         &Opcode::Sextend => {
4653                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4654                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4655                                 if let &InstructionData::BinaryImm8 {
4656                                     opcode: ref pattern9_0,
4657                                     arg: pattern9_1,
4658                                     imm: pattern9_2,
4659                                 } = &pattern8_0
4660                                 {
4661                                     if let &Opcode::Extractlane = &pattern9_0 {
4662                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4663                                         if pattern11_0 == I64X2 {
4664                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4665                                             // Rule at src/isa/aarch64/lower.isle line 562.
4666                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4667                                             let expr1_0 = VectorSize::Size64x2;
4668                                             let expr2_0 = constructor_mov_from_vec(
4669                                                 ctx,
4670                                                 expr0_0,
4671                                                 pattern13_0,
4672                                                 &expr1_0,
4673                                             )?;
4674                                             let expr3_0: u8 = 63;
4675                                             let expr4_0 = C::imm_shift_from_u8(ctx, expr3_0);
4676                                             let expr5_0 =
4677                                                 constructor_asr64_imm(ctx, expr2_0, expr4_0)?;
4678                                             let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
4679                                             return Some(expr6_0);
4680                                         }
4681                                         if let Some(()) = C::not_i64x2(ctx, pattern11_0) {
4682                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4683                                             // Rule at src/isa/aarch64/lower.isle line 549.
4684                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4685                                             let expr1_0 =
4686                                                 constructor_vector_size(ctx, pattern11_0)?;
4687                                             let expr2_0: Type = I64;
4688                                             let expr3_0 = constructor_size_from_ty(ctx, expr2_0)?;
4689                                             let expr4_0 = constructor_mov_from_vec_signed(
4690                                                 ctx,
4691                                                 expr0_0,
4692                                                 pattern13_0,
4693                                                 &expr1_0,
4694                                                 &expr3_0,
4695                                             )?;
4696                                             let expr5_0: u8 = 63;
4697                                             let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
4698                                             let expr7_0 =
4699                                                 constructor_asr64_imm(ctx, expr4_0, expr6_0)?;
4700                                             let expr8_0 = C::value_regs(ctx, expr4_0, expr7_0);
4701                                             return Some(expr8_0);
4702                                         }
4703                                     }
4704                                 }
4705                             }
4706                             // Rule at src/isa/aarch64/lower.isle line 537.
4707                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
4708                             let expr1_0: u8 = 63;
4709                             let expr2_0 = C::imm_shift_from_u8(ctx, expr1_0);
4710                             let expr3_0 = constructor_asr64_imm(ctx, expr0_0, expr2_0)?;
4711                             let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
4712                             return Some(expr4_0);
4713                         }
4714                         _ => {}
4715                     }
4716                 }
4717                 _ => {}
4718             }
4719         }
4720         if pattern2_0 == I8X16 {
4721             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4722             if let &InstructionData::Unary {
4723                 opcode: ref pattern5_0,
4724                 arg: pattern5_1,
4725             } = &pattern4_0
4726             {
4727                 if let &Opcode::Popcnt = &pattern5_0 {
4728                     // Rule at src/isa/aarch64/lower.isle line 1194.
4729                     let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4730                     let expr1_0 = VectorSize::Size8x16;
4731                     let expr2_0 = constructor_vec_cnt(ctx, expr0_0, &expr1_0)?;
4732                     let expr3_0 = C::value_reg(ctx, expr2_0);
4733                     return Some(expr3_0);
4734                 }
4735             }
4736         }
4737         if pattern2_0 == I16X8 {
4738             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4739             if let &InstructionData::Binary {
4740                 opcode: ref pattern5_0,
4741                 args: ref pattern5_1,
4742             } = &pattern4_0
4743             {
4744                 if let &Opcode::Imul = &pattern5_0 {
4745                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
4746                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4747                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4748                         if let &InstructionData::Unary {
4749                             opcode: ref pattern10_0,
4750                             arg: pattern10_1,
4751                         } = &pattern9_0
4752                         {
4753                             match &pattern10_0 {
4754                                 &Opcode::SwidenLow => {
4755                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4756                                     if pattern12_0 == I8X16 {
4757                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4758                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4759                                             if let &InstructionData::Unary {
4760                                                 opcode: ref pattern16_0,
4761                                                 arg: pattern16_1,
4762                                             } = &pattern15_0
4763                                             {
4764                                                 if let &Opcode::SwidenLow = &pattern16_0 {
4765                                                     let pattern18_0 =
4766                                                         C::value_type(ctx, pattern16_1);
4767                                                     if pattern18_0 == I8X16 {
4768                                                         // Rule at src/isa/aarch64/lower.isle line 287.
4769                                                         let expr0_0 =
4770                                                             C::put_in_reg(ctx, pattern10_1);
4771                                                         let expr1_0 =
4772                                                             C::put_in_reg(ctx, pattern16_1);
4773                                                         let expr2_0: bool = false;
4774                                                         let expr3_0 = constructor_smull8(
4775                                                             ctx, expr0_0, expr1_0, expr2_0,
4776                                                         )?;
4777                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
4778                                                         return Some(expr4_0);
4779                                                     }
4780                                                 }
4781                                             }
4782                                         }
4783                                     }
4784                                 }
4785                                 &Opcode::SwidenHigh => {
4786                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4787                                     if pattern12_0 == I8X16 {
4788                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4789                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4790                                             if let &InstructionData::Unary {
4791                                                 opcode: ref pattern16_0,
4792                                                 arg: pattern16_1,
4793                                             } = &pattern15_0
4794                                             {
4795                                                 if let &Opcode::SwidenHigh = &pattern16_0 {
4796                                                     let pattern18_0 =
4797                                                         C::value_type(ctx, pattern16_1);
4798                                                     if pattern18_0 == I8X16 {
4799                                                         // Rule at src/isa/aarch64/lower.isle line 293.
4800                                                         let expr0_0 =
4801                                                             C::put_in_reg(ctx, pattern10_1);
4802                                                         let expr1_0 =
4803                                                             C::put_in_reg(ctx, pattern16_1);
4804                                                         let expr2_0: bool = true;
4805                                                         let expr3_0 = constructor_smull8(
4806                                                             ctx, expr0_0, expr1_0, expr2_0,
4807                                                         )?;
4808                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
4809                                                         return Some(expr4_0);
4810                                                     }
4811                                                 }
4812                                             }
4813                                         }
4814                                     }
4815                                 }
4816                                 &Opcode::UwidenLow => {
4817                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4818                                     if pattern12_0 == I8X16 {
4819                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4820                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4821                                             if let &InstructionData::Unary {
4822                                                 opcode: ref pattern16_0,
4823                                                 arg: pattern16_1,
4824                                             } = &pattern15_0
4825                                             {
4826                                                 if let &Opcode::UwidenLow = &pattern16_0 {
4827                                                     let pattern18_0 =
4828                                                         C::value_type(ctx, pattern16_1);
4829                                                     if pattern18_0 == I8X16 {
4830                                                         // Rule at src/isa/aarch64/lower.isle line 299.
4831                                                         let expr0_0 =
4832                                                             C::put_in_reg(ctx, pattern10_1);
4833                                                         let expr1_0 =
4834                                                             C::put_in_reg(ctx, pattern16_1);
4835                                                         let expr2_0: bool = false;
4836                                                         let expr3_0 = constructor_umull8(
4837                                                             ctx, expr0_0, expr1_0, expr2_0,
4838                                                         )?;
4839                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
4840                                                         return Some(expr4_0);
4841                                                     }
4842                                                 }
4843                                             }
4844                                         }
4845                                     }
4846                                 }
4847                                 &Opcode::UwidenHigh => {
4848                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4849                                     if pattern12_0 == I8X16 {
4850                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4851                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4852                                             if let &InstructionData::Unary {
4853                                                 opcode: ref pattern16_0,
4854                                                 arg: pattern16_1,
4855                                             } = &pattern15_0
4856                                             {
4857                                                 if let &Opcode::UwidenHigh = &pattern16_0 {
4858                                                     let pattern18_0 =
4859                                                         C::value_type(ctx, pattern16_1);
4860                                                     if pattern18_0 == I8X16 {
4861                                                         // Rule at src/isa/aarch64/lower.isle line 305.
4862                                                         let expr0_0 =
4863                                                             C::put_in_reg(ctx, pattern10_1);
4864                                                         let expr1_0 =
4865                                                             C::put_in_reg(ctx, pattern16_1);
4866                                                         let expr2_0: bool = true;
4867                                                         let expr3_0 = constructor_umull8(
4868                                                             ctx, expr0_0, expr1_0, expr2_0,
4869                                                         )?;
4870                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
4871                                                         return Some(expr4_0);
4872                                                     }
4873                                                 }
4874                                             }
4875                                         }
4876                                     }
4877                                 }
4878                                 _ => {}
4879                             }
4880                         }
4881                     }
4882                 }
4883             }
4884         }
4885         if pattern2_0 == I32X4 {
4886             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4887             if let &InstructionData::Binary {
4888                 opcode: ref pattern5_0,
4889                 args: ref pattern5_1,
4890             } = &pattern4_0
4891             {
4892                 if let &Opcode::Imul = &pattern5_0 {
4893                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
4894                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4895                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4896                         if let &InstructionData::Unary {
4897                             opcode: ref pattern10_0,
4898                             arg: pattern10_1,
4899                         } = &pattern9_0
4900                         {
4901                             match &pattern10_0 {
4902                                 &Opcode::SwidenLow => {
4903                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4904                                     if pattern12_0 == I16X8 {
4905                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4906                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4907                                             if let &InstructionData::Unary {
4908                                                 opcode: ref pattern16_0,
4909                                                 arg: pattern16_1,
4910                                             } = &pattern15_0
4911                                             {
4912                                                 if let &Opcode::SwidenLow = &pattern16_0 {
4913                                                     let pattern18_0 =
4914                                                         C::value_type(ctx, pattern16_1);
4915                                                     if pattern18_0 == I16X8 {
4916                                                         // Rule at src/isa/aarch64/lower.isle line 311.
4917                                                         let expr0_0 =
4918                                                             C::put_in_reg(ctx, pattern10_1);
4919                                                         let expr1_0 =
4920                                                             C::put_in_reg(ctx, pattern16_1);
4921                                                         let expr2_0: bool = false;
4922                                                         let expr3_0 = constructor_smull16(
4923                                                             ctx, expr0_0, expr1_0, expr2_0,
4924                                                         )?;
4925                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
4926                                                         return Some(expr4_0);
4927                                                     }
4928                                                 }
4929                                             }
4930                                         }
4931                                     }
4932                                 }
4933                                 &Opcode::SwidenHigh => {
4934                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4935                                     if pattern12_0 == I16X8 {
4936                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4937                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4938                                             if let &InstructionData::Unary {
4939                                                 opcode: ref pattern16_0,
4940                                                 arg: pattern16_1,
4941                                             } = &pattern15_0
4942                                             {
4943                                                 if let &Opcode::SwidenHigh = &pattern16_0 {
4944                                                     let pattern18_0 =
4945                                                         C::value_type(ctx, pattern16_1);
4946                                                     if pattern18_0 == I16X8 {
4947                                                         // Rule at src/isa/aarch64/lower.isle line 317.
4948                                                         let expr0_0 =
4949                                                             C::put_in_reg(ctx, pattern10_1);
4950                                                         let expr1_0 =
4951                                                             C::put_in_reg(ctx, pattern16_1);
4952                                                         let expr2_0: bool = true;
4953                                                         let expr3_0 = constructor_smull16(
4954                                                             ctx, expr0_0, expr1_0, expr2_0,
4955                                                         )?;
4956                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
4957                                                         return Some(expr4_0);
4958                                                     }
4959                                                 }
4960                                             }
4961                                         }
4962                                     }
4963                                 }
4964                                 &Opcode::UwidenLow => {
4965                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4966                                     if pattern12_0 == I16X8 {
4967                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4968                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4969                                             if let &InstructionData::Unary {
4970                                                 opcode: ref pattern16_0,
4971                                                 arg: pattern16_1,
4972                                             } = &pattern15_0
4973                                             {
4974                                                 if let &Opcode::UwidenLow = &pattern16_0 {
4975                                                     let pattern18_0 =
4976                                                         C::value_type(ctx, pattern16_1);
4977                                                     if pattern18_0 == I16X8 {
4978                                                         // Rule at src/isa/aarch64/lower.isle line 323.
4979                                                         let expr0_0 =
4980                                                             C::put_in_reg(ctx, pattern10_1);
4981                                                         let expr1_0 =
4982                                                             C::put_in_reg(ctx, pattern16_1);
4983                                                         let expr2_0: bool = false;
4984                                                         let expr3_0 = constructor_umull16(
4985                                                             ctx, expr0_0, expr1_0, expr2_0,
4986                                                         )?;
4987                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
4988                                                         return Some(expr4_0);
4989                                                     }
4990                                                 }
4991                                             }
4992                                         }
4993                                     }
4994                                 }
4995                                 &Opcode::UwidenHigh => {
4996                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4997                                     if pattern12_0 == I16X8 {
4998                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4999                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5000                                             if let &InstructionData::Unary {
5001                                                 opcode: ref pattern16_0,
5002                                                 arg: pattern16_1,
5003                                             } = &pattern15_0
5004                                             {
5005                                                 if let &Opcode::UwidenHigh = &pattern16_0 {
5006                                                     let pattern18_0 =
5007                                                         C::value_type(ctx, pattern16_1);
5008                                                     if pattern18_0 == I16X8 {
5009                                                         // Rule at src/isa/aarch64/lower.isle line 329.
5010                                                         let expr0_0 =
5011                                                             C::put_in_reg(ctx, pattern10_1);
5012                                                         let expr1_0 =
5013                                                             C::put_in_reg(ctx, pattern16_1);
5014                                                         let expr2_0: bool = true;
5015                                                         let expr3_0 = constructor_umull16(
5016                                                             ctx, expr0_0, expr1_0, expr2_0,
5017                                                         )?;
5018                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5019                                                         return Some(expr4_0);
5020                                                     }
5021                                                 }
5022                                             }
5023                                         }
5024                                     }
5025                                 }
5026                                 _ => {}
5027                             }
5028                         }
5029                     }
5030                 }
5031             }
5032         }
5033         if pattern2_0 == I64X2 {
5034             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5035             if let &InstructionData::Binary {
5036                 opcode: ref pattern5_0,
5037                 args: ref pattern5_1,
5038             } = &pattern4_0
5039             {
5040                 if let &Opcode::Imul = &pattern5_0 {
5041                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5042                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5043                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
5044                         if let &InstructionData::Unary {
5045                             opcode: ref pattern10_0,
5046                             arg: pattern10_1,
5047                         } = &pattern9_0
5048                         {
5049                             match &pattern10_0 {
5050                                 &Opcode::SwidenLow => {
5051                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5052                                     if pattern12_0 == I32X4 {
5053                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5054                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5055                                             if let &InstructionData::Unary {
5056                                                 opcode: ref pattern16_0,
5057                                                 arg: pattern16_1,
5058                                             } = &pattern15_0
5059                                             {
5060                                                 if let &Opcode::SwidenLow = &pattern16_0 {
5061                                                     let pattern18_0 =
5062                                                         C::value_type(ctx, pattern16_1);
5063                                                     if pattern18_0 == I32X4 {
5064                                                         // Rule at src/isa/aarch64/lower.isle line 335.
5065                                                         let expr0_0 =
5066                                                             C::put_in_reg(ctx, pattern10_1);
5067                                                         let expr1_0 =
5068                                                             C::put_in_reg(ctx, pattern16_1);
5069                                                         let expr2_0: bool = false;
5070                                                         let expr3_0 = constructor_smull32(
5071                                                             ctx, expr0_0, expr1_0, expr2_0,
5072                                                         )?;
5073                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5074                                                         return Some(expr4_0);
5075                                                     }
5076                                                 }
5077                                             }
5078                                         }
5079                                     }
5080                                 }
5081                                 &Opcode::SwidenHigh => {
5082                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5083                                     if pattern12_0 == I32X4 {
5084                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5085                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5086                                             if let &InstructionData::Unary {
5087                                                 opcode: ref pattern16_0,
5088                                                 arg: pattern16_1,
5089                                             } = &pattern15_0
5090                                             {
5091                                                 if let &Opcode::SwidenHigh = &pattern16_0 {
5092                                                     let pattern18_0 =
5093                                                         C::value_type(ctx, pattern16_1);
5094                                                     if pattern18_0 == I32X4 {
5095                                                         // Rule at src/isa/aarch64/lower.isle line 341.
5096                                                         let expr0_0 =
5097                                                             C::put_in_reg(ctx, pattern10_1);
5098                                                         let expr1_0 =
5099                                                             C::put_in_reg(ctx, pattern16_1);
5100                                                         let expr2_0: bool = true;
5101                                                         let expr3_0 = constructor_smull32(
5102                                                             ctx, expr0_0, expr1_0, expr2_0,
5103                                                         )?;
5104                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5105                                                         return Some(expr4_0);
5106                                                     }
5107                                                 }
5108                                             }
5109                                         }
5110                                     }
5111                                 }
5112                                 &Opcode::UwidenLow => {
5113                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5114                                     if pattern12_0 == I32X4 {
5115                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5116                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5117                                             if let &InstructionData::Unary {
5118                                                 opcode: ref pattern16_0,
5119                                                 arg: pattern16_1,
5120                                             } = &pattern15_0
5121                                             {
5122                                                 if let &Opcode::UwidenLow = &pattern16_0 {
5123                                                     let pattern18_0 =
5124                                                         C::value_type(ctx, pattern16_1);
5125                                                     if pattern18_0 == I32X4 {
5126                                                         // Rule at src/isa/aarch64/lower.isle line 347.
5127                                                         let expr0_0 =
5128                                                             C::put_in_reg(ctx, pattern10_1);
5129                                                         let expr1_0 =
5130                                                             C::put_in_reg(ctx, pattern16_1);
5131                                                         let expr2_0: bool = false;
5132                                                         let expr3_0 = constructor_umull32(
5133                                                             ctx, expr0_0, expr1_0, expr2_0,
5134                                                         )?;
5135                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5136                                                         return Some(expr4_0);
5137                                                     }
5138                                                 }
5139                                             }
5140                                         }
5141                                     }
5142                                 }
5143                                 &Opcode::UwidenHigh => {
5144                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5145                                     if pattern12_0 == I32X4 {
5146                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5147                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5148                                             if let &InstructionData::Unary {
5149                                                 opcode: ref pattern16_0,
5150                                                 arg: pattern16_1,
5151                                             } = &pattern15_0
5152                                             {
5153                                                 if let &Opcode::UwidenHigh = &pattern16_0 {
5154                                                     let pattern18_0 =
5155                                                         C::value_type(ctx, pattern16_1);
5156                                                     if pattern18_0 == I32X4 {
5157                                                         // Rule at src/isa/aarch64/lower.isle line 353.
5158                                                         let expr0_0 =
5159                                                             C::put_in_reg(ctx, pattern10_1);
5160                                                         let expr1_0 =
5161                                                             C::put_in_reg(ctx, pattern16_1);
5162                                                         let expr2_0: bool = true;
5163                                                         let expr3_0 = constructor_umull32(
5164                                                             ctx, expr0_0, expr1_0, expr2_0,
5165                                                         )?;
5166                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5167                                                         return Some(expr4_0);
5168                                                     }
5169                                                 }
5170                                             }
5171                                         }
5172                                     }
5173                                 }
5174                                 _ => {}
5175                             }
5176                         }
5177                     }
5178                     // Rule at src/isa/aarch64/lower.isle line 246.
5179                     let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5180                     let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5181                     let expr2_0 = VectorSize::Size32x4;
5182                     let expr3_0 = constructor_rev64(ctx, expr1_0, &expr2_0)?;
5183                     let expr4_0 = VectorSize::Size32x4;
5184                     let expr5_0 = constructor_mul(ctx, expr3_0, expr0_0, &expr4_0)?;
5185                     let expr6_0: bool = false;
5186                     let expr7_0 = constructor_xtn64(ctx, expr0_0, expr6_0)?;
5187                     let expr8_0 = VectorSize::Size32x4;
5188                     let expr9_0 = constructor_addp(ctx, expr5_0, expr5_0, &expr8_0)?;
5189                     let expr10_0: bool = false;
5190                     let expr11_0 = constructor_xtn64(ctx, expr1_0, expr10_0)?;
5191                     let expr12_0: bool = false;
5192                     let expr13_0 = constructor_shll32(ctx, expr9_0, expr12_0)?;
5193                     let expr14_0: bool = false;
5194                     let expr15_0 = constructor_umlal32(ctx, expr13_0, expr11_0, expr7_0, expr14_0)?;
5195                     let expr16_0 = C::value_reg(ctx, expr15_0);
5196                     return Some(expr16_0);
5197                 }
5198             }
5199         }
5200         let pattern3_0 = C::inst_data(ctx, pattern0_0);
5201         match &pattern3_0 {
5202             &InstructionData::NullAry {
5203                 opcode: ref pattern4_0,
5204             } => {
5205                 if let &Opcode::Null = &pattern4_0 {
5206                     // Rule at src/isa/aarch64/lower.isle line 22.
5207                     let expr0_0: u64 = 0;
5208                     let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5209                     let expr2_0 = C::value_reg(ctx, expr1_0);
5210                     return Some(expr2_0);
5211                 }
5212             }
5213             &InstructionData::UnaryImm {
5214                 opcode: ref pattern4_0,
5215                 imm: pattern4_1,
5216             } => {
5217                 if let &Opcode::Iconst = &pattern4_0 {
5218                     let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1);
5219                     // Rule at src/isa/aarch64/lower.isle line 9.
5220                     let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?;
5221                     let expr1_0 = C::value_reg(ctx, expr0_0);
5222                     return Some(expr1_0);
5223                 }
5224             }
5225             &InstructionData::UnaryBool {
5226                 opcode: ref pattern4_0,
5227                 imm: pattern4_1,
5228             } => {
5229                 if let &Opcode::Bconst = &pattern4_0 {
5230                     if pattern4_1 == true {
5231                         // Rule at src/isa/aarch64/lower.isle line 17.
5232                         let expr0_0: u64 = 1;
5233                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5234                         let expr2_0 = C::value_reg(ctx, expr1_0);
5235                         return Some(expr2_0);
5236                     }
5237                     if pattern4_1 == false {
5238                         // Rule at src/isa/aarch64/lower.isle line 14.
5239                         let expr0_0: u64 = 0;
5240                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5241                         let expr2_0 = C::value_reg(ctx, expr1_0);
5242                         return Some(expr2_0);
5243                     }
5244                 }
5245             }
5246             _ => {}
5247         }
5248         if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) {
5249             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5250             if let &InstructionData::Binary {
5251                 opcode: ref pattern5_0,
5252                 args: ref pattern5_1,
5253             } = &pattern4_0
5254             {
5255                 match &pattern5_0 {
5256                     &Opcode::Iadd => {
5257                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5258                         // Rule at src/isa/aarch64/lower.isle line 75.
5259                         let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5260                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5261                         let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5262                         let expr3_0 = constructor_add_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5263                         let expr4_0 = C::value_reg(ctx, expr3_0);
5264                         return Some(expr4_0);
5265                     }
5266                     &Opcode::Isub => {
5267                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5268                         // Rule at src/isa/aarch64/lower.isle line 126.
5269                         let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5270                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5271                         let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5272                         let expr3_0 = constructor_sub_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5273                         let expr4_0 = C::value_reg(ctx, expr3_0);
5274                         return Some(expr4_0);
5275                     }
5276                     _ => {}
5277                 }
5278             }
5279         }
5280         if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
5281             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5282             if let &InstructionData::Binary {
5283                 opcode: ref pattern5_0,
5284                 args: ref pattern5_1,
5285             } = &pattern4_0
5286             {
5287                 match &pattern5_0 {
5288                     &Opcode::Rotl => {
5289                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5290                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5291                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5292                             if let &InstructionData::UnaryImm {
5293                                 opcode: ref pattern10_0,
5294                                 imm: pattern10_1,
5295                             } = &pattern9_0
5296                             {
5297                                 if let &Opcode::Iconst = &pattern10_0 {
5298                                     let closure12 = || {
5299                                         return Some(pattern3_0);
5300                                     };
5301                                     if let Some(pattern12_0) = closure12() {
5302                                         if let Some(pattern13_0) =
5303                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5304                                         {
5305                                             // Rule at src/isa/aarch64/lower.isle line 874.
5306                                             let expr0_0 =
5307                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5308                                             let expr1_0 =
5309                                                 C::negate_imm_shift(ctx, pattern3_0, pattern13_0);
5310                                             let expr2_0 = constructor_small_rotr_imm(
5311                                                 ctx, pattern3_0, expr0_0, expr1_0,
5312                                             )?;
5313                                             let expr3_0 = C::value_reg(ctx, expr2_0);
5314                                             return Some(expr3_0);
5315                                         }
5316                                     }
5317                                 }
5318                             }
5319                         }
5320                         // Rule at src/isa/aarch64/lower.isle line 869.
5321                         let expr0_0 = C::zero_reg(ctx);
5322                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5323                         let expr2_0 = constructor_sub32(ctx, expr0_0, expr1_0)?;
5324                         let expr3_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5325                         let expr4_0 = constructor_small_rotr(ctx, pattern3_0, expr3_0, expr2_0)?;
5326                         let expr5_0 = C::value_reg(ctx, expr4_0);
5327                         return Some(expr5_0);
5328                     }
5329                     &Opcode::Rotr => {
5330                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5331                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5332                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5333                             if let &InstructionData::UnaryImm {
5334                                 opcode: ref pattern10_0,
5335                                 imm: pattern10_1,
5336                             } = &pattern9_0
5337                             {
5338                                 if let &Opcode::Iconst = &pattern10_0 {
5339                                     let closure12 = || {
5340                                         return Some(pattern3_0);
5341                                     };
5342                                     if let Some(pattern12_0) = closure12() {
5343                                         if let Some(pattern13_0) =
5344                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5345                                         {
5346                                             // Rule at src/isa/aarch64/lower.isle line 936.
5347                                             let expr0_0 =
5348                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5349                                             let expr1_0 = constructor_small_rotr_imm(
5350                                                 ctx,
5351                                                 pattern3_0,
5352                                                 expr0_0,
5353                                                 pattern13_0,
5354                                             )?;
5355                                             let expr2_0 = C::value_reg(ctx, expr1_0);
5356                                             return Some(expr2_0);
5357                                         }
5358                                     }
5359                                 }
5360                             }
5361                         }
5362                         // Rule at src/isa/aarch64/lower.isle line 924.
5363                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5364                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5365                         let expr2_0 = constructor_small_rotr(ctx, pattern3_0, expr0_0, expr1_0)?;
5366                         let expr3_0 = C::value_reg(ctx, expr2_0);
5367                         return Some(expr3_0);
5368                     }
5369                     _ => {}
5370                 }
5371             }
5372         }
5373         if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
5374             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5375             if let &InstructionData::Binary {
5376                 opcode: ref pattern5_0,
5377                 args: ref pattern5_1,
5378             } = &pattern4_0
5379             {
5380                 match &pattern5_0 {
5381                     &Opcode::Umulhi => {
5382                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5383                         // Rule at src/isa/aarch64/lower.isle line 377.
5384                         let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5385                         let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?;
5386                         let expr2_0 = C::zero_reg(ctx);
5387                         let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
5388                         let expr4_0 = C::ty_bits(ctx, pattern3_0);
5389                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
5390                         let expr6_0 = constructor_lsr64_imm(ctx, expr3_0, expr5_0)?;
5391                         let expr7_0 = C::value_reg(ctx, expr6_0);
5392                         return Some(expr7_0);
5393                     }
5394                     &Opcode::Smulhi => {
5395                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5396                         // Rule at src/isa/aarch64/lower.isle line 363.
5397                         let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5398                         let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?;
5399                         let expr2_0 = C::zero_reg(ctx);
5400                         let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
5401                         let expr4_0 = C::ty_bits(ctx, pattern3_0);
5402                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
5403                         let expr6_0 = constructor_asr64_imm(ctx, expr3_0, expr5_0)?;
5404                         let expr7_0 = C::value_reg(ctx, expr6_0);
5405                         return Some(expr7_0);
5406                     }
5407                     &Opcode::Band => {
5408                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5409                         // Rule at src/isa/aarch64/lower.isle line 606.
5410                         let expr0_0 = ALUOp::And32;
5411                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5412                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5413                         )?;
5414                         let expr2_0 = C::value_reg(ctx, expr1_0);
5415                         return Some(expr2_0);
5416                     }
5417                     &Opcode::Bor => {
5418                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5419                         // Rule at src/isa/aarch64/lower.isle line 619.
5420                         let expr0_0 = ALUOp::Orr32;
5421                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5422                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5423                         )?;
5424                         let expr2_0 = C::value_reg(ctx, expr1_0);
5425                         return Some(expr2_0);
5426                     }
5427                     &Opcode::Bxor => {
5428                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5429                         // Rule at src/isa/aarch64/lower.isle line 632.
5430                         let expr0_0 = ALUOp::Eor32;
5431                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5432                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5433                         )?;
5434                         let expr2_0 = C::value_reg(ctx, expr1_0);
5435                         return Some(expr2_0);
5436                     }
5437                     &Opcode::BandNot => {
5438                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5439                         // Rule at src/isa/aarch64/lower.isle line 645.
5440                         let expr0_0 = ALUOp::AndNot32;
5441                         let expr1_0 = constructor_alu_rs_imm_logic(
5442                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5443                         )?;
5444                         let expr2_0 = C::value_reg(ctx, expr1_0);
5445                         return Some(expr2_0);
5446                     }
5447                     &Opcode::BorNot => {
5448                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5449                         // Rule at src/isa/aarch64/lower.isle line 658.
5450                         let expr0_0 = ALUOp::OrrNot32;
5451                         let expr1_0 = constructor_alu_rs_imm_logic(
5452                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5453                         )?;
5454                         let expr2_0 = C::value_reg(ctx, expr1_0);
5455                         return Some(expr2_0);
5456                     }
5457                     &Opcode::BxorNot => {
5458                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5459                         // Rule at src/isa/aarch64/lower.isle line 668.
5460                         let expr0_0 = ALUOp::EorNot32;
5461                         let expr1_0 = constructor_alu_rs_imm_logic(
5462                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5463                         )?;
5464                         let expr2_0 = C::value_reg(ctx, expr1_0);
5465                         return Some(expr2_0);
5466                     }
5467                     &Opcode::Ishl => {
5468                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5469                         // Rule at src/isa/aarch64/lower.isle line 679.
5470                         let expr0_0 = ALUOp::Lsl32;
5471                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
5472                         let expr2_0 =
5473                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5474                         let expr3_0 = C::value_reg(ctx, expr2_0);
5475                         return Some(expr3_0);
5476                     }
5477                     &Opcode::Ushr => {
5478                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5479                         // Rule at src/isa/aarch64/lower.isle line 767.
5480                         let expr0_0 = ALUOp::Lsr32;
5481                         let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5482                         let expr2_0 =
5483                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5484                         let expr3_0 = C::value_reg(ctx, expr2_0);
5485                         return Some(expr3_0);
5486                     }
5487                     &Opcode::Sshr => {
5488                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1);
5489                         // Rule at src/isa/aarch64/lower.isle line 816.
5490                         let expr0_0 = ALUOp::Asr32;
5491                         let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
5492                         let expr2_0 =
5493                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5494                         let expr3_0 = C::value_reg(ctx, expr2_0);
5495                         return Some(expr3_0);
5496                     }
5497                     _ => {}
5498                 }
5499             }
5500         }
5501         if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
5502             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5503             match &pattern4_0 {
5504                 &InstructionData::Binary {
5505                     opcode: ref pattern5_0,
5506                     args: ref pattern5_1,
5507                 } => {
5508                     match &pattern5_0 {
5509                         &Opcode::Iadd => {
5510                             let (pattern7_0, pattern7_1) =
5511                                 C::unpack_value_array_2(ctx, &pattern5_1);
5512                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5513                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5514                                 match &pattern9_0 {
5515                                     &InstructionData::UnaryImm {
5516                                         opcode: ref pattern10_0,
5517                                         imm: pattern10_1,
5518                                     } => {
5519                                         if let &Opcode::Iconst = &pattern10_0 {
5520                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5521                                             if let Some(pattern13_0) =
5522                                                 C::imm12_from_u64(ctx, pattern12_0)
5523                                             {
5524                                                 // Rule at src/isa/aarch64/lower.isle line 37.
5525                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5526                                                 let expr1_0 = constructor_add_imm(
5527                                                     ctx,
5528                                                     pattern3_0,
5529                                                     expr0_0,
5530                                                     pattern13_0,
5531                                                 )?;
5532                                                 let expr2_0 = C::value_reg(ctx, expr1_0);
5533                                                 return Some(expr2_0);
5534                                             }
5535                                             if let Some(pattern13_0) =
5536                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5537                                             {
5538                                                 // Rule at src/isa/aarch64/lower.isle line 45.
5539                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5540                                                 let expr1_0 = constructor_sub_imm(
5541                                                     ctx,
5542                                                     pattern3_0,
5543                                                     expr0_0,
5544                                                     pattern13_0,
5545                                                 )?;
5546                                                 let expr2_0 = C::value_reg(ctx, expr1_0);
5547                                                 return Some(expr2_0);
5548                                             }
5549                                         }
5550                                     }
5551                                     &InstructionData::Binary {
5552                                         opcode: ref pattern10_0,
5553                                         args: ref pattern10_1,
5554                                     } => {
5555                                         match &pattern10_0 {
5556                                             &Opcode::Imul => {
5557                                                 let (pattern12_0, pattern12_1) =
5558                                                     C::unpack_value_array_2(ctx, &pattern10_1);
5559                                                 // Rule at src/isa/aarch64/lower.isle line 70.
5560                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5561                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5562                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5563                                                 let expr3_0 = constructor_madd(
5564                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5565                                                 )?;
5566                                                 let expr4_0 = C::value_reg(ctx, expr3_0);
5567                                                 return Some(expr4_0);
5568                                             }
5569                                             &Opcode::Ishl => {
5570                                                 let (pattern12_0, pattern12_1) =
5571                                                     C::unpack_value_array_2(ctx, &pattern10_1);
5572                                                 if let Some(pattern13_0) =
5573                                                     C::def_inst(ctx, pattern12_1)
5574                                                 {
5575                                                     let pattern14_0 =
5576                                                         C::inst_data(ctx, pattern13_0);
5577                                                     if let &InstructionData::UnaryImm {
5578                                                         opcode: ref pattern15_0,
5579                                                         imm: pattern15_1,
5580                                                     } = &pattern14_0
5581                                                     {
5582                                                         if let &Opcode::Iconst = &pattern15_0 {
5583                                                             let closure17 = || {
5584                                                                 return Some(pattern3_0);
5585                                                             };
5586                                                             if let Some(pattern17_0) = closure17() {
5587                                                                 if let Some(pattern18_0) =
5588                                                                     C::lshl_from_imm64(
5589                                                                         ctx,
5590                                                                         pattern15_1,
5591                                                                         pattern17_0,
5592                                                                     )
5593                                                                 {
5594                                                                     // Rule at src/isa/aarch64/lower.isle line 62.
5595                                                                     let expr0_0 = C::put_in_reg(
5596                                                                         ctx, pattern7_1,
5597                                                                     );
5598                                                                     let expr1_0 = C::put_in_reg(
5599                                                                         ctx,
5600                                                                         pattern12_0,
5601                                                                     );
5602                                                                     let expr2_0 =
5603                                                                         constructor_add_shift(
5604                                                                             ctx,
5605                                                                             pattern3_0,
5606                                                                             expr0_0,
5607                                                                             expr1_0,
5608                                                                             pattern18_0,
5609                                                                         )?;
5610                                                                     let expr3_0 =
5611                                                                         C::value_reg(ctx, expr2_0);
5612                                                                     return Some(expr3_0);
5613                                                                 }
5614                                                             }
5615                                                         }
5616                                                     }
5617                                                 }
5618                                             }
5619                                             _ => {}
5620                                         }
5621                                     }
5622                                     _ => {}
5623                                 }
5624                             }
5625                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0)
5626                             {
5627                                 // Rule at src/isa/aarch64/lower.isle line 53.
5628                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5629                                 let expr1_0 =
5630                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5631                                 let expr2_0 = C::value_reg(ctx, expr1_0);
5632                                 return Some(expr2_0);
5633                             }
5634                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5635                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5636                                 match &pattern9_0 {
5637                                     &InstructionData::UnaryImm {
5638                                         opcode: ref pattern10_0,
5639                                         imm: pattern10_1,
5640                                     } => {
5641                                         if let &Opcode::Iconst = &pattern10_0 {
5642                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5643                                             if let Some(pattern13_0) =
5644                                                 C::imm12_from_u64(ctx, pattern12_0)
5645                                             {
5646                                                 // Rule at src/isa/aarch64/lower.isle line 34.
5647                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5648                                                 let expr1_0 = constructor_add_imm(
5649                                                     ctx,
5650                                                     pattern3_0,
5651                                                     expr0_0,
5652                                                     pattern13_0,
5653                                                 )?;
5654                                                 let expr2_0 = C::value_reg(ctx, expr1_0);
5655                                                 return Some(expr2_0);
5656                                             }
5657                                             if let Some(pattern13_0) =
5658                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5659                                             {
5660                                                 // Rule at src/isa/aarch64/lower.isle line 42.
5661                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5662                                                 let expr1_0 = constructor_sub_imm(
5663                                                     ctx,
5664                                                     pattern3_0,
5665                                                     expr0_0,
5666                                                     pattern13_0,
5667                                                 )?;
5668                                                 let expr2_0 = C::value_reg(ctx, expr1_0);
5669                                                 return Some(expr2_0);
5670                                             }
5671                                         }
5672                                     }
5673                                     &InstructionData::Binary {
5674                                         opcode: ref pattern10_0,
5675                                         args: ref pattern10_1,
5676                                     } => {
5677                                         match &pattern10_0 {
5678                                             &Opcode::Imul => {
5679                                                 let (pattern12_0, pattern12_1) =
5680                                                     C::unpack_value_array_2(ctx, &pattern10_1);
5681                                                 // Rule at src/isa/aarch64/lower.isle line 67.
5682                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5683                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5684                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
5685                                                 let expr3_0 = constructor_madd(
5686                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5687                                                 )?;
5688                                                 let expr4_0 = C::value_reg(ctx, expr3_0);
5689                                                 return Some(expr4_0);
5690                                             }
5691                                             &Opcode::Ishl => {
5692                                                 let (pattern12_0, pattern12_1) =
5693                                                     C::unpack_value_array_2(ctx, &pattern10_1);
5694                                                 if let Some(pattern13_0) =
5695                                                     C::def_inst(ctx, pattern12_1)
5696                                                 {
5697                                                     let pattern14_0 =
5698                                                         C::inst_data(ctx, pattern13_0);
5699                                                     if let &InstructionData::UnaryImm {
5700                                                         opcode: ref pattern15_0,
5701                                                         imm: pattern15_1,
5702                                                     } = &pattern14_0
5703                                                     {
5704                                                         if let &Opcode::Iconst = &pattern15_0 {
5705                                                             let closure17 = || {
5706                                                                 return Some(pattern3_0);
5707                                                             };
5708                                                             if let Some(pattern17_0) = closure17() {
5709                                                                 if let Some(pattern18_0) =
5710                                                                     C::lshl_from_imm64(
5711                                                                         ctx,
5712                                                                         pattern15_1,
5713                                                                         pattern17_0,
5714                                                                     )
5715                                                                 {
5716                                                                     // Rule at src/isa/aarch64/lower.isle line 58.
5717                                                                     let expr0_0 = C::put_in_reg(
5718                                                                         ctx, pattern7_0,
5719                                                                     );
5720                                                                     let expr1_0 = C::put_in_reg(
5721                                                                         ctx,
5722                                                                         pattern12_0,
5723                                                                     );
5724                                                                     let expr2_0 =
5725                                                                         constructor_add_shift(
5726                                                                             ctx,
5727                                                                             pattern3_0,
5728                                                                             expr0_0,
5729                                                                             expr1_0,
5730                                                                             pattern18_0,
5731                                                                         )?;
5732                                                                     let expr3_0 =
5733                                                                         C::value_reg(ctx, expr2_0);
5734                                                                     return Some(expr3_0);
5735                                                                 }
5736                                                             }
5737                                                         }
5738                                                     }
5739                                                 }
5740                                             }
5741                                             _ => {}
5742                                         }
5743                                     }
5744                                     _ => {}
5745                                 }
5746                             }
5747                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
5748                             {
5749                                 // Rule at src/isa/aarch64/lower.isle line 50.
5750                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5751                                 let expr1_0 =
5752                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5753                                 let expr2_0 = C::value_reg(ctx, expr1_0);
5754                                 return Some(expr2_0);
5755                             }
5756                             // Rule at src/isa/aarch64/lower.isle line 30.
5757                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5758                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5759                             let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, expr1_0)?;
5760                             let expr3_0 = C::value_reg(ctx, expr2_0);
5761                             return Some(expr3_0);
5762                         }
5763                         &Opcode::Isub => {
5764                             let (pattern7_0, pattern7_1) =
5765                                 C::unpack_value_array_2(ctx, &pattern5_1);
5766                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5767                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5768                                 match &pattern9_0 {
5769                                     &InstructionData::UnaryImm {
5770                                         opcode: ref pattern10_0,
5771                                         imm: pattern10_1,
5772                                     } => {
5773                                         if let &Opcode::Iconst = &pattern10_0 {
5774                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5775                                             if let Some(pattern13_0) =
5776                                                 C::imm12_from_u64(ctx, pattern12_0)
5777                                             {
5778                                                 // Rule at src/isa/aarch64/lower.isle line 106.
5779                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5780                                                 let expr1_0 = constructor_sub_imm(
5781                                                     ctx,
5782                                                     pattern3_0,
5783                                                     expr0_0,
5784                                                     pattern13_0,
5785                                                 )?;
5786                                                 let expr2_0 = C::value_reg(ctx, expr1_0);
5787                                                 return Some(expr2_0);
5788                                             }
5789                                             if let Some(pattern13_0) =
5790                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5791                                             {
5792                                                 // Rule at src/isa/aarch64/lower.isle line 111.
5793                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5794                                                 let expr1_0 = constructor_add_imm(
5795                                                     ctx,
5796                                                     pattern3_0,
5797                                                     expr0_0,
5798                                                     pattern13_0,
5799                                                 )?;
5800                                                 let expr2_0 = C::value_reg(ctx, expr1_0);
5801                                                 return Some(expr2_0);
5802                                             }
5803                                         }
5804                                     }
5805                                     &InstructionData::Binary {
5806                                         opcode: ref pattern10_0,
5807                                         args: ref pattern10_1,
5808                                     } => {
5809                                         if let &Opcode::Ishl = &pattern10_0 {
5810                                             let (pattern12_0, pattern12_1) =
5811                                                 C::unpack_value_array_2(ctx, &pattern10_1);
5812                                             if let Some(pattern13_0) = C::def_inst(ctx, pattern12_1)
5813                                             {
5814                                                 let pattern14_0 = C::inst_data(ctx, pattern13_0);
5815                                                 if let &InstructionData::UnaryImm {
5816                                                     opcode: ref pattern15_0,
5817                                                     imm: pattern15_1,
5818                                                 } = &pattern14_0
5819                                                 {
5820                                                     if let &Opcode::Iconst = &pattern15_0 {
5821                                                         let closure17 = || {
5822                                                             return Some(pattern3_0);
5823                                                         };
5824                                                         if let Some(pattern17_0) = closure17() {
5825                                                             if let Some(pattern18_0) =
5826                                                                 C::lshl_from_imm64(
5827                                                                     ctx,
5828                                                                     pattern15_1,
5829                                                                     pattern17_0,
5830                                                                 )
5831                                                             {
5832                                                                 // Rule at src/isa/aarch64/lower.isle line 121.
5833                                                                 let expr0_0 =
5834                                                                     C::put_in_reg(ctx, pattern7_0);
5835                                                                 let expr1_0 =
5836                                                                     C::put_in_reg(ctx, pattern12_0);
5837                                                                 let expr2_0 =
5838                                                                     constructor_sub_shift(
5839                                                                         ctx,
5840                                                                         pattern3_0,
5841                                                                         expr0_0,
5842                                                                         expr1_0,
5843                                                                         pattern18_0,
5844                                                                     )?;
5845                                                                 let expr3_0 =
5846                                                                     C::value_reg(ctx, expr2_0);
5847                                                                 return Some(expr3_0);
5848                                                             }
5849                                                         }
5850                                                     }
5851                                                 }
5852                                             }
5853                                         }
5854                                     }
5855                                     _ => {}
5856                                 }
5857                             }
5858                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
5859                             {
5860                                 // Rule at src/isa/aarch64/lower.isle line 116.
5861                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5862                                 let expr1_0 =
5863                                     constructor_sub_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5864                                 let expr2_0 = C::value_reg(ctx, expr1_0);
5865                                 return Some(expr2_0);
5866                             }
5867                             // Rule at src/isa/aarch64/lower.isle line 102.
5868                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5869                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5870                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
5871                             let expr3_0 = C::value_reg(ctx, expr2_0);
5872                             return Some(expr3_0);
5873                         }
5874                         &Opcode::Imul => {
5875                             let (pattern7_0, pattern7_1) =
5876                                 C::unpack_value_array_2(ctx, &pattern5_1);
5877                             // Rule at src/isa/aarch64/lower.isle line 181.
5878                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5879                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5880                             let expr2_0 = C::zero_reg(ctx);
5881                             let expr3_0 =
5882                                 constructor_madd(ctx, pattern3_0, expr0_0, expr1_0, expr2_0)?;
5883                             let expr4_0 = C::value_reg(ctx, expr3_0);
5884                             return Some(expr4_0);
5885                         }
5886                         &Opcode::Udiv => {
5887                             let (pattern7_0, pattern7_1) =
5888                                 C::unpack_value_array_2(ctx, &pattern5_1);
5889                             // Rule at src/isa/aarch64/lower.isle line 393.
5890                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5891                             let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
5892                             let expr2_0 = constructor_udiv64(ctx, expr0_0, expr1_0)?;
5893                             let expr3_0 = C::value_reg(ctx, expr2_0);
5894                             return Some(expr3_0);
5895                         }
5896                         &Opcode::Sdiv => {
5897                             let (pattern7_0, pattern7_1) =
5898                                 C::unpack_value_array_2(ctx, &pattern5_1);
5899                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5900                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5901                                 if let &InstructionData::UnaryImm {
5902                                     opcode: ref pattern10_0,
5903                                     imm: pattern10_1,
5904                                 } = &pattern9_0
5905                                 {
5906                                     if let &Opcode::Iconst = &pattern10_0 {
5907                                         if let Some(pattern12_0) =
5908                                             C::safe_divisor_from_imm64(ctx, pattern10_1)
5909                                         {
5910                                             // Rule at src/isa/aarch64/lower.isle line 441.
5911                                             let expr0_0 =
5912                                                 constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5913                                             let expr1_0 =
5914                                                 constructor_imm(ctx, pattern3_0, pattern12_0)?;
5915                                             let expr2_0 =
5916                                                 constructor_sdiv64(ctx, expr0_0, expr1_0)?;
5917                                             let expr3_0 = C::value_reg(ctx, expr2_0);
5918                                             return Some(expr3_0);
5919                                         }
5920                                     }
5921                                 }
5922                             }
5923                             // Rule at src/isa/aarch64/lower.isle line 426.
5924                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5925                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
5926                             let expr2_0 = constructor_trap_if_div_overflow(
5927                                 ctx, pattern3_0, expr0_0, expr1_0,
5928                             )?;
5929                             let expr3_0 = constructor_sdiv64(ctx, expr2_0, expr1_0)?;
5930                             let expr4_0 = C::value_reg(ctx, expr3_0);
5931                             return Some(expr4_0);
5932                         }
5933                         &Opcode::Urem => {
5934                             let (pattern7_0, pattern7_1) =
5935                                 C::unpack_value_array_2(ctx, &pattern5_1);
5936                             // Rule at src/isa/aarch64/lower.isle line 469.
5937                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5938                             let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
5939                             let expr2_0 = constructor_udiv64(ctx, expr0_0, expr1_0)?;
5940                             let expr3_0 = constructor_msub64(ctx, expr2_0, expr1_0, expr0_0)?;
5941                             let expr4_0 = C::value_reg(ctx, expr3_0);
5942                             return Some(expr4_0);
5943                         }
5944                         &Opcode::Srem => {
5945                             let (pattern7_0, pattern7_1) =
5946                                 C::unpack_value_array_2(ctx, &pattern5_1);
5947                             // Rule at src/isa/aarch64/lower.isle line 478.
5948                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5949                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
5950                             let expr2_0 = constructor_sdiv64(ctx, expr0_0, expr1_0)?;
5951                             let expr3_0 = constructor_msub64(ctx, expr2_0, expr1_0, expr0_0)?;
5952                             let expr4_0 = C::value_reg(ctx, expr3_0);
5953                             return Some(expr4_0);
5954                         }
5955                         _ => {}
5956                     }
5957                 }
5958                 &InstructionData::Unary {
5959                     opcode: ref pattern5_0,
5960                     arg: pattern5_1,
5961                 } => {
5962                     match &pattern5_0 {
5963                         &Opcode::Ineg => {
5964                             // Rule at src/isa/aarch64/lower.isle line 171.
5965                             let expr0_0 = C::zero_reg(ctx);
5966                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
5967                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
5968                             let expr3_0 = C::value_reg(ctx, expr2_0);
5969                             return Some(expr3_0);
5970                         }
5971                         &Opcode::Bnot => {
5972                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
5973                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
5974                                 if let &InstructionData::Binary {
5975                                     opcode: ref pattern9_0,
5976                                     args: ref pattern9_1,
5977                                 } = &pattern8_0
5978                                 {
5979                                     if let &Opcode::Ishl = &pattern9_0 {
5980                                         let (pattern11_0, pattern11_1) =
5981                                             C::unpack_value_array_2(ctx, &pattern9_1);
5982                                         if let Some(pattern12_0) = C::def_inst(ctx, pattern11_1) {
5983                                             let pattern13_0 = C::inst_data(ctx, pattern12_0);
5984                                             if let &InstructionData::UnaryImm {
5985                                                 opcode: ref pattern14_0,
5986                                                 imm: pattern14_1,
5987                                             } = &pattern13_0
5988                                             {
5989                                                 if let &Opcode::Iconst = &pattern14_0 {
5990                                                     let closure16 = || {
5991                                                         return Some(pattern3_0);
5992                                                     };
5993                                                     if let Some(pattern16_0) = closure16() {
5994                                                         if let Some(pattern17_0) =
5995                                                             C::lshl_from_imm64(
5996                                                                 ctx,
5997                                                                 pattern14_1,
5998                                                                 pattern16_0,
5999                                                             )
6000                                                         {
6001                                                             // Rule at src/isa/aarch64/lower.isle line 585.
6002                                                             let expr0_0 = C::zero_reg(ctx);
6003                                                             let expr1_0 =
6004                                                                 C::put_in_reg(ctx, pattern11_0);
6005                                                             let expr2_0 =
6006                                                                 constructor_orr_not_shift(
6007                                                                     ctx,
6008                                                                     pattern3_0,
6009                                                                     expr0_0,
6010                                                                     expr1_0,
6011                                                                     pattern17_0,
6012                                                                 )?;
6013                                                             let expr3_0 =
6014                                                                 C::value_reg(ctx, expr2_0);
6015                                                             return Some(expr3_0);
6016                                                         }
6017                                                     }
6018                                                 }
6019                                             }
6020                                         }
6021                                     }
6022                                 }
6023                             }
6024                             // Rule at src/isa/aarch64/lower.isle line 580.
6025                             let expr0_0 = C::zero_reg(ctx);
6026                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6027                             let expr2_0 = constructor_orr_not(ctx, pattern3_0, expr0_0, expr1_0)?;
6028                             let expr3_0 = C::value_reg(ctx, expr2_0);
6029                             return Some(expr3_0);
6030                         }
6031                         &Opcode::Uextend => {
6032                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6033                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6034                                 if let &InstructionData::BinaryImm8 {
6035                                     opcode: ref pattern9_0,
6036                                     arg: pattern9_1,
6037                                     imm: pattern9_2,
6038                                 } = &pattern8_0
6039                                 {
6040                                     if let &Opcode::Extractlane = &pattern9_0 {
6041                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6042                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6043                                         // Rule at src/isa/aarch64/lower.isle line 496.
6044                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6045                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6046                                         let expr2_0 = constructor_mov_from_vec(
6047                                             ctx,
6048                                             expr0_0,
6049                                             pattern12_0,
6050                                             &expr1_0,
6051                                         )?;
6052                                         let expr3_0 = C::value_reg(ctx, expr2_0);
6053                                         return Some(expr3_0);
6054                                     }
6055                                 }
6056                             }
6057                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6058                             if let Some(pattern8_0) = C::sinkable_atomic_load(ctx, pattern5_1) {
6059                                 // Rule at src/isa/aarch64/lower.isle line 503.
6060                                 let expr0_0 = C::sink_atomic_load(ctx, &pattern8_0);
6061                                 let expr1_0 = constructor_load_acquire(ctx, pattern7_0, expr0_0)?;
6062                                 let expr2_0 = C::value_reg(ctx, expr1_0);
6063                                 return Some(expr2_0);
6064                             }
6065                             // Rule at src/isa/aarch64/lower.isle line 491.
6066                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6067                             let expr1_0: bool = false;
6068                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6069                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6070                             let expr4_0 =
6071                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6072                             let expr5_0 = C::value_reg(ctx, expr4_0);
6073                             return Some(expr5_0);
6074                         }
6075                         &Opcode::Sextend => {
6076                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6077                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6078                                 if let &InstructionData::BinaryImm8 {
6079                                     opcode: ref pattern9_0,
6080                                     arg: pattern9_1,
6081                                     imm: pattern9_2,
6082                                 } = &pattern8_0
6083                                 {
6084                                     if let &Opcode::Extractlane = &pattern9_0 {
6085                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6086                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6087                                         // Rule at src/isa/aarch64/lower.isle line 528.
6088                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6089                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6090                                         let expr2_0 = constructor_size_from_ty(ctx, pattern3_0)?;
6091                                         let expr3_0 = constructor_mov_from_vec_signed(
6092                                             ctx,
6093                                             expr0_0,
6094                                             pattern12_0,
6095                                             &expr1_0,
6096                                             &expr2_0,
6097                                         )?;
6098                                         let expr4_0 = C::value_reg(ctx, expr3_0);
6099                                         return Some(expr4_0);
6100                                     }
6101                                 }
6102                             }
6103                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6104                             // Rule at src/isa/aarch64/lower.isle line 523.
6105                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6106                             let expr1_0: bool = true;
6107                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6108                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6109                             let expr4_0 =
6110                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6111                             let expr5_0 = C::value_reg(ctx, expr4_0);
6112                             return Some(expr5_0);
6113                         }
6114                         _ => {}
6115                     }
6116                 }
6117                 _ => {}
6118             }
6119         }
6120         if let Some(pattern3_0) = C::vec128(ctx, pattern2_0) {
6121             let pattern4_0 = C::inst_data(ctx, pattern0_0);
6122             match &pattern4_0 {
6123                 &InstructionData::Binary {
6124                     opcode: ref pattern5_0,
6125                     args: ref pattern5_1,
6126                 } => {
6127                     match &pattern5_0 {
6128                         &Opcode::UaddSat => {
6129                             let (pattern7_0, pattern7_1) =
6130                                 C::unpack_value_array_2(ctx, &pattern5_1);
6131                             // Rule at src/isa/aarch64/lower.isle line 150.
6132                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6133                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6134                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6135                             let expr3_0 = constructor_uqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6136                             let expr4_0 = C::value_reg(ctx, expr3_0);
6137                             return Some(expr4_0);
6138                         }
6139                         &Opcode::SaddSat => {
6140                             let (pattern7_0, pattern7_1) =
6141                                 C::unpack_value_array_2(ctx, &pattern5_1);
6142                             // Rule at src/isa/aarch64/lower.isle line 155.
6143                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6144                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6145                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6146                             let expr3_0 = constructor_sqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6147                             let expr4_0 = C::value_reg(ctx, expr3_0);
6148                             return Some(expr4_0);
6149                         }
6150                         &Opcode::UsubSat => {
6151                             let (pattern7_0, pattern7_1) =
6152                                 C::unpack_value_array_2(ctx, &pattern5_1);
6153                             // Rule at src/isa/aarch64/lower.isle line 160.
6154                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6155                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6156                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6157                             let expr3_0 = constructor_uqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6158                             let expr4_0 = C::value_reg(ctx, expr3_0);
6159                             return Some(expr4_0);
6160                         }
6161                         &Opcode::SsubSat => {
6162                             let (pattern7_0, pattern7_1) =
6163                                 C::unpack_value_array_2(ctx, &pattern5_1);
6164                             // Rule at src/isa/aarch64/lower.isle line 165.
6165                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6166                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6167                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6168                             let expr3_0 = constructor_sqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6169                             let expr4_0 = C::value_reg(ctx, expr3_0);
6170                             return Some(expr4_0);
6171                         }
6172                         &Opcode::Band => {
6173                             let (pattern7_0, pattern7_1) =
6174                                 C::unpack_value_array_2(ctx, &pattern5_1);
6175                             // Rule at src/isa/aarch64/lower.isle line 614.
6176                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6177                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6178                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6179                             let expr3_0 = constructor_and_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6180                             let expr4_0 = C::value_reg(ctx, expr3_0);
6181                             return Some(expr4_0);
6182                         }
6183                         &Opcode::Bor => {
6184                             let (pattern7_0, pattern7_1) =
6185                                 C::unpack_value_array_2(ctx, &pattern5_1);
6186                             // Rule at src/isa/aarch64/lower.isle line 627.
6187                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6188                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6189                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6190                             let expr3_0 = constructor_orr_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6191                             let expr4_0 = C::value_reg(ctx, expr3_0);
6192                             return Some(expr4_0);
6193                         }
6194                         &Opcode::Bxor => {
6195                             let (pattern7_0, pattern7_1) =
6196                                 C::unpack_value_array_2(ctx, &pattern5_1);
6197                             // Rule at src/isa/aarch64/lower.isle line 640.
6198                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6199                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6200                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6201                             let expr3_0 = constructor_eor_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6202                             let expr4_0 = C::value_reg(ctx, expr3_0);
6203                             return Some(expr4_0);
6204                         }
6205                         &Opcode::BandNot => {
6206                             let (pattern7_0, pattern7_1) =
6207                                 C::unpack_value_array_2(ctx, &pattern5_1);
6208                             // Rule at src/isa/aarch64/lower.isle line 653.
6209                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6210                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6211                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6212                             let expr3_0 = constructor_bic_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6213                             let expr4_0 = C::value_reg(ctx, expr3_0);
6214                             return Some(expr4_0);
6215                         }
6216                         &Opcode::Ishl => {
6217                             let (pattern7_0, pattern7_1) =
6218                                 C::unpack_value_array_2(ctx, &pattern5_1);
6219                             // Rule at src/isa/aarch64/lower.isle line 717.
6220                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6221                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6222                             let expr2_0 = constructor_vec_dup(ctx, expr1_0, &expr0_0)?;
6223                             let expr3_0 = C::put_in_reg(ctx, pattern7_0);
6224                             let expr4_0 = constructor_sshl(ctx, expr3_0, expr2_0, &expr0_0)?;
6225                             let expr5_0 = C::value_reg(ctx, expr4_0);
6226                             return Some(expr5_0);
6227                         }
6228                         &Opcode::Ushr => {
6229                             let (pattern7_0, pattern7_1) =
6230                                 C::unpack_value_array_2(ctx, &pattern5_1);
6231                             // Rule at src/isa/aarch64/lower.isle line 779.
6232                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6233                             let expr1_0 = C::zero_reg(ctx);
6234                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
6235                             let expr3_0 = constructor_sub32(ctx, expr1_0, expr2_0)?;
6236                             let expr4_0 = constructor_vec_dup(ctx, expr3_0, &expr0_0)?;
6237                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
6238                             let expr6_0 = constructor_ushl(ctx, expr5_0, expr4_0, &expr0_0)?;
6239                             let expr7_0 = C::value_reg(ctx, expr6_0);
6240                             return Some(expr7_0);
6241                         }
6242                         &Opcode::Sshr => {
6243                             let (pattern7_0, pattern7_1) =
6244                                 C::unpack_value_array_2(ctx, &pattern5_1);
6245                             // Rule at src/isa/aarch64/lower.isle line 830.
6246                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6247                             let expr1_0 = C::zero_reg(ctx);
6248                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
6249                             let expr3_0 = constructor_sub32(ctx, expr1_0, expr2_0)?;
6250                             let expr4_0 = constructor_vec_dup(ctx, expr3_0, &expr0_0)?;
6251                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
6252                             let expr6_0 = constructor_sshl(ctx, expr5_0, expr4_0, &expr0_0)?;
6253                             let expr7_0 = C::value_reg(ctx, expr6_0);
6254                             return Some(expr7_0);
6255                         }
6256                         _ => {}
6257                     }
6258                 }
6259                 &InstructionData::Unary {
6260                     opcode: ref pattern5_0,
6261                     arg: pattern5_1,
6262                 } => {
6263                     match &pattern5_0 {
6264                         &Opcode::Ineg => {
6265                             // Rule at src/isa/aarch64/lower.isle line 175.
6266                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6267                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6268                             let expr2_0 = constructor_neg(ctx, expr0_0, &expr1_0)?;
6269                             let expr3_0 = C::value_reg(ctx, expr2_0);
6270                             return Some(expr3_0);
6271                         }
6272                         &Opcode::Bnot => {
6273                             // Rule at src/isa/aarch64/lower.isle line 601.
6274                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6275                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6276                             let expr2_0 = constructor_not(ctx, expr0_0, &expr1_0)?;
6277                             let expr3_0 = C::value_reg(ctx, expr2_0);
6278                             return Some(expr3_0);
6279                         }
6280                         _ => {}
6281                     }
6282                 }
6283                 _ => {}
6284             }
6285             if let Some(()) = C::not_i64x2(ctx, pattern3_0) {
6286                 let pattern5_0 = C::inst_data(ctx, pattern0_0);
6287                 if let &InstructionData::Binary {
6288                     opcode: ref pattern6_0,
6289                     args: ref pattern6_1,
6290                 } = &pattern5_0
6291                 {
6292                     if let &Opcode::Imul = &pattern6_0 {
6293                         let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, &pattern6_1);
6294                         // Rule at src/isa/aarch64/lower.isle line 214.
6295                         let expr0_0 = C::put_in_reg(ctx, pattern8_0);
6296                         let expr1_0 = C::put_in_reg(ctx, pattern8_1);
6297                         let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6298                         let expr3_0 = constructor_mul(ctx, expr0_0, expr1_0, &expr2_0)?;
6299                         let expr4_0 = C::value_reg(ctx, expr3_0);
6300                         return Some(expr4_0);
6301                     }
6302                 }
6303             }
6304         }
6305     }
6306     return None;
6307 }
6308 
6309 // Generated as internal constructor for term put_nonzero_in_reg_zext64.
6310 pub fn constructor_put_nonzero_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6311     let pattern0_0 = arg0;
6312     let pattern1_0 = C::value_type(ctx, pattern0_0);
6313     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6314         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6315         if let &InstructionData::UnaryImm {
6316             opcode: ref pattern4_0,
6317             imm: pattern4_1,
6318         } = &pattern3_0
6319         {
6320             if let &Opcode::Iconst = &pattern4_0 {
6321                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6322                     // Rule at src/isa/aarch64/lower.isle line 403.
6323                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6324                     return Some(expr0_0);
6325                 }
6326             }
6327         }
6328     }
6329     // Rule at src/isa/aarch64/lower.isle line 398.
6330     let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern0_0)?;
6331     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6332     return Some(expr1_0);
6333 }
6334 
6335 // Generated as internal constructor for term put_nonzero_in_reg_sext64.
6336 pub fn constructor_put_nonzero_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6337     let pattern0_0 = arg0;
6338     let pattern1_0 = C::value_type(ctx, pattern0_0);
6339     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6340         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6341         if let &InstructionData::UnaryImm {
6342             opcode: ref pattern4_0,
6343             imm: pattern4_1,
6344         } = &pattern3_0
6345         {
6346             if let &Opcode::Iconst = &pattern4_0 {
6347                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6348                     // Rule at src/isa/aarch64/lower.isle line 451.
6349                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6350                     return Some(expr0_0);
6351                 }
6352             }
6353         }
6354     }
6355     // Rule at src/isa/aarch64/lower.isle line 446.
6356     let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern0_0)?;
6357     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6358     return Some(expr1_0);
6359 }
6360 
6361 // Generated as internal constructor for term lower_shl128.
6362 pub fn constructor_lower_shl128<C: Context>(
6363     ctx: &mut C,
6364     arg0: ValueRegs,
6365     arg1: Reg,
6366 ) -> Option<ValueRegs> {
6367     let pattern0_0 = arg0;
6368     let pattern1_0 = arg1;
6369     // Rule at src/isa/aarch64/lower.isle line 700.
6370     let expr0_0: usize = 0;
6371     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6372     let expr2_0: usize = 1;
6373     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6374     let expr4_0 = constructor_lsl64(ctx, expr1_0, pattern1_0)?;
6375     let expr5_0 = constructor_lsl64(ctx, expr3_0, pattern1_0)?;
6376     let expr6_0 = C::zero_reg(ctx);
6377     let expr7_0 = constructor_orr_not32(ctx, expr6_0, pattern1_0)?;
6378     let expr8_0: u8 = 1;
6379     let expr9_0 = C::imm_shift_from_u8(ctx, expr8_0);
6380     let expr10_0 = constructor_lsr64_imm(ctx, expr1_0, expr9_0)?;
6381     let expr11_0 = constructor_lsr64(ctx, expr10_0, expr7_0)?;
6382     let expr12_0 = constructor_orr64(ctx, expr5_0, expr11_0)?;
6383     let expr13_0: Type = I64;
6384     let expr14_0: u64 = 64;
6385     let expr15_0 = C::u64_into_imm_logic(ctx, expr13_0, expr14_0);
6386     let expr16_0 = constructor_tst64_imm(ctx, pattern1_0, expr15_0)?;
6387     let expr17_0 = Cond::Ne;
6388     let expr18_0 = C::zero_reg(ctx);
6389     let expr19_0 = constructor_csel(ctx, &expr17_0, expr18_0, expr4_0)?;
6390     let expr20_0 = Cond::Ne;
6391     let expr21_0 = constructor_csel(ctx, &expr20_0, expr4_0, expr12_0)?;
6392     let expr22_0 = constructor_with_flags_2(ctx, &expr16_0, &expr19_0, &expr21_0)?;
6393     return Some(expr22_0);
6394 }
6395 
6396 // Generated as internal constructor for term do_shift.
6397 pub fn constructor_do_shift<C: Context>(
6398     ctx: &mut C,
6399     arg0: &ALUOp,
6400     arg1: Type,
6401     arg2: Reg,
6402     arg3: Value,
6403 ) -> Option<Reg> {
6404     let pattern0_0 = arg0;
6405     let pattern1_0 = arg1;
6406     let pattern2_0 = arg2;
6407     let pattern3_0 = arg3;
6408     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
6409         let pattern5_0 = C::inst_data(ctx, pattern4_0);
6410         if let &InstructionData::UnaryImm {
6411             opcode: ref pattern6_0,
6412             imm: pattern6_1,
6413         } = &pattern5_0
6414         {
6415             if let &Opcode::Iconst = &pattern6_0 {
6416                 let closure8 = || {
6417                     return Some(pattern1_0);
6418                 };
6419                 if let Some(pattern8_0) = closure8() {
6420                     if let Some(pattern9_0) = C::imm_shift_from_imm64(ctx, pattern6_1, pattern8_0) {
6421                         // Rule at src/isa/aarch64/lower.isle line 761.
6422                         let expr0_0 =
6423                             constructor_alu_rr_imm_shift(ctx, pattern0_0, pattern2_0, pattern9_0)?;
6424                         return Some(expr0_0);
6425                     }
6426                 }
6427             }
6428         }
6429     }
6430     let pattern0_0 = arg0;
6431     let pattern1_0 = arg1;
6432     if pattern1_0 == I32 {
6433         let pattern3_0 = arg2;
6434         let pattern4_0 = arg3;
6435         // Rule at src/isa/aarch64/lower.isle line 752.
6436         let expr0_0 = C::put_in_regs(ctx, pattern4_0);
6437         let expr1_0: usize = 0;
6438         let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
6439         let expr3_0 = constructor_alu_rrr(ctx, pattern0_0, pattern3_0, expr2_0)?;
6440         return Some(expr3_0);
6441     }
6442     if pattern1_0 == I64 {
6443         let pattern3_0 = arg2;
6444         let pattern4_0 = arg3;
6445         // Rule at src/isa/aarch64/lower.isle line 753.
6446         let expr0_0 = C::put_in_regs(ctx, pattern4_0);
6447         let expr1_0: usize = 0;
6448         let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
6449         let expr3_0 = constructor_alu_rrr(ctx, pattern0_0, pattern3_0, expr2_0)?;
6450         return Some(expr3_0);
6451     }
6452     if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
6453         let pattern3_0 = arg2;
6454         let pattern4_0 = arg3;
6455         // Rule at src/isa/aarch64/lower.isle line 741.
6456         let expr0_0 = C::put_in_regs(ctx, pattern4_0);
6457         let expr1_0: usize = 0;
6458         let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
6459         let expr3_0 = C::shift_mask(ctx, pattern2_0);
6460         let expr4_0 = constructor_and32_imm(ctx, expr2_0, expr3_0)?;
6461         let expr5_0 = constructor_alu_rrr(ctx, pattern0_0, pattern3_0, expr4_0)?;
6462         return Some(expr5_0);
6463     }
6464     return None;
6465 }
6466 
6467 // Generated as internal constructor for term lower_ushr128.
6468 pub fn constructor_lower_ushr128<C: Context>(
6469     ctx: &mut C,
6470     arg0: ValueRegs,
6471     arg1: Reg,
6472 ) -> Option<ValueRegs> {
6473     let pattern0_0 = arg0;
6474     let pattern1_0 = arg1;
6475     // Rule at src/isa/aarch64/lower.isle line 796.
6476     let expr0_0: usize = 0;
6477     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6478     let expr2_0: usize = 1;
6479     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6480     let expr4_0 = constructor_lsr64(ctx, expr1_0, pattern1_0)?;
6481     let expr5_0 = constructor_lsr64(ctx, expr3_0, pattern1_0)?;
6482     let expr6_0 = C::zero_reg(ctx);
6483     let expr7_0 = constructor_orr_not32(ctx, expr6_0, pattern1_0)?;
6484     let expr8_0: u8 = 1;
6485     let expr9_0 = C::imm_shift_from_u8(ctx, expr8_0);
6486     let expr10_0 = constructor_lsl64_imm(ctx, expr3_0, expr9_0)?;
6487     let expr11_0 = constructor_lsl64(ctx, expr10_0, expr7_0)?;
6488     let expr12_0 = constructor_orr64(ctx, expr4_0, expr11_0)?;
6489     let expr13_0: Type = I64;
6490     let expr14_0: u64 = 64;
6491     let expr15_0 = C::u64_into_imm_logic(ctx, expr13_0, expr14_0);
6492     let expr16_0 = constructor_tst64_imm(ctx, pattern1_0, expr15_0)?;
6493     let expr17_0 = Cond::Ne;
6494     let expr18_0 = constructor_csel(ctx, &expr17_0, expr5_0, expr12_0)?;
6495     let expr19_0 = Cond::Ne;
6496     let expr20_0 = C::zero_reg(ctx);
6497     let expr21_0 = constructor_csel(ctx, &expr19_0, expr20_0, expr5_0)?;
6498     let expr22_0 = constructor_with_flags_2(ctx, &expr16_0, &expr18_0, &expr21_0)?;
6499     return Some(expr22_0);
6500 }
6501 
6502 // Generated as internal constructor for term lower_sshr128.
6503 pub fn constructor_lower_sshr128<C: Context>(
6504     ctx: &mut C,
6505     arg0: ValueRegs,
6506     arg1: Reg,
6507 ) -> Option<ValueRegs> {
6508     let pattern0_0 = arg0;
6509     let pattern1_0 = arg1;
6510     // Rule at src/isa/aarch64/lower.isle line 848.
6511     let expr0_0: usize = 0;
6512     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6513     let expr2_0: usize = 1;
6514     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6515     let expr4_0 = constructor_lsr64(ctx, expr1_0, pattern1_0)?;
6516     let expr5_0 = constructor_asr64(ctx, expr3_0, pattern1_0)?;
6517     let expr6_0 = C::zero_reg(ctx);
6518     let expr7_0 = constructor_orr_not32(ctx, expr6_0, pattern1_0)?;
6519     let expr8_0: u8 = 1;
6520     let expr9_0 = C::imm_shift_from_u8(ctx, expr8_0);
6521     let expr10_0 = constructor_lsl64_imm(ctx, expr3_0, expr9_0)?;
6522     let expr11_0 = constructor_lsl64(ctx, expr10_0, expr7_0)?;
6523     let expr12_0: u8 = 63;
6524     let expr13_0 = C::imm_shift_from_u8(ctx, expr12_0);
6525     let expr14_0 = constructor_asr64_imm(ctx, expr3_0, expr13_0)?;
6526     let expr15_0 = constructor_orr64(ctx, expr4_0, expr11_0)?;
6527     let expr16_0: Type = I64;
6528     let expr17_0: u64 = 64;
6529     let expr18_0 = C::u64_into_imm_logic(ctx, expr16_0, expr17_0);
6530     let expr19_0 = constructor_tst64_imm(ctx, pattern1_0, expr18_0)?;
6531     let expr20_0 = Cond::Ne;
6532     let expr21_0 = constructor_csel(ctx, &expr20_0, expr5_0, expr15_0)?;
6533     let expr22_0 = Cond::Ne;
6534     let expr23_0 = constructor_csel(ctx, &expr22_0, expr14_0, expr5_0)?;
6535     let expr24_0 = constructor_with_flags_2(ctx, &expr19_0, &expr21_0, &expr23_0)?;
6536     return Some(expr24_0);
6537 }
6538 
6539 // Generated as internal constructor for term small_rotr.
6540 pub fn constructor_small_rotr<C: Context>(
6541     ctx: &mut C,
6542     arg0: Type,
6543     arg1: Reg,
6544     arg2: Reg,
6545 ) -> Option<Reg> {
6546     let pattern0_0 = arg0;
6547     let pattern1_0 = arg1;
6548     let pattern2_0 = arg2;
6549     // Rule at src/isa/aarch64/lower.isle line 960.
6550     let expr0_0 = C::rotr_mask(ctx, pattern0_0);
6551     let expr1_0 = constructor_and32_imm(ctx, pattern2_0, expr0_0)?;
6552     let expr2_0 = C::ty_bits(ctx, pattern0_0);
6553     let expr3_0 = C::u8_into_imm12(ctx, expr2_0);
6554     let expr4_0 = constructor_sub32_imm(ctx, expr1_0, expr3_0)?;
6555     let expr5_0 = C::zero_reg(ctx);
6556     let expr6_0 = constructor_sub32(ctx, expr5_0, expr4_0)?;
6557     let expr7_0 = constructor_lsr32(ctx, pattern1_0, expr1_0)?;
6558     let expr8_0 = constructor_lsl32(ctx, pattern1_0, expr6_0)?;
6559     let expr9_0 = constructor_orr32(ctx, expr8_0, expr7_0)?;
6560     return Some(expr9_0);
6561 }
6562 
6563 // Generated as internal constructor for term small_rotr_imm.
6564 pub fn constructor_small_rotr_imm<C: Context>(
6565     ctx: &mut C,
6566     arg0: Type,
6567     arg1: Reg,
6568     arg2: ImmShift,
6569 ) -> Option<Reg> {
6570     let pattern0_0 = arg0;
6571     let pattern1_0 = arg1;
6572     let pattern2_0 = arg2;
6573     // Rule at src/isa/aarch64/lower.isle line 983.
6574     let expr0_0 = constructor_lsr32_imm(ctx, pattern1_0, pattern2_0)?;
6575     let expr1_0 = C::rotr_opposite_amount(ctx, pattern0_0, pattern2_0);
6576     let expr2_0 = constructor_lsl32_imm(ctx, pattern1_0, expr1_0)?;
6577     let expr3_0 = constructor_orr32(ctx, expr2_0, expr0_0)?;
6578     return Some(expr3_0);
6579 }
6580 
6581 // Generated as internal constructor for term lower_clz128.
6582 pub fn constructor_lower_clz128<C: Context>(ctx: &mut C, arg0: ValueRegs) -> Option<ValueRegs> {
6583     let pattern0_0 = arg0;
6584     // Rule at src/isa/aarch64/lower.isle line 1059.
6585     let expr0_0: usize = 1;
6586     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6587     let expr2_0 = constructor_clz64(ctx, expr1_0)?;
6588     let expr3_0: usize = 0;
6589     let expr4_0 = C::value_regs_get(ctx, pattern0_0, expr3_0);
6590     let expr5_0 = constructor_clz64(ctx, expr4_0)?;
6591     let expr6_0: u8 = 6;
6592     let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
6593     let expr8_0 = constructor_lsr64_imm(ctx, expr2_0, expr7_0)?;
6594     let expr9_0 = constructor_madd64(ctx, expr5_0, expr8_0, expr2_0)?;
6595     let expr10_0: Type = I64;
6596     let expr11_0: u64 = 0;
6597     let expr12_0 = constructor_imm(ctx, expr10_0, expr11_0)?;
6598     let expr13_0 = C::value_regs(ctx, expr9_0, expr12_0);
6599     return Some(expr13_0);
6600 }
6601