1 // GENERATED BY ISLE. DO NOT EDIT!
2 //
3 // Generated automatically from the instruction-selection DSL code in:
4 // - src/clif.isle
5 // - src/prelude.isle
6 // - src/isa/aarch64/inst.isle
7 // - src/isa/aarch64/lower.isle
8 
9 #![allow(dead_code, unreachable_code, unreachable_patterns)]
10 #![allow(unused_imports, unused_variables, non_snake_case)]
11 #![allow(irrefutable_let_patterns)]
12 
13 use super::*; // Pulls in all external types.
14 
15 /// Context during lowering: an implementation of this trait
16 /// must be provided with all external constructors and extractors.
17 /// A mutable borrow is passed along through all lowering logic.
18 pub trait Context {
19     fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
20     fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
21     fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
22     fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
23     fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
24     fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
25     fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
26     fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
27     fn value_regs_invalid(&mut self) -> ValueRegs;
28     fn output_none(&mut self) -> InstOutput;
29     fn output(&mut self, arg0: ValueRegs) -> InstOutput;
30     fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput;
31     fn output_builder_new(&mut self) -> InstOutputBuilder;
32     fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit;
33     fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput;
34     fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
35     fn invalid_reg(&mut self) -> Reg;
36     fn put_in_reg(&mut self, arg0: Value) -> Reg;
37     fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
38     fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
39     fn u8_as_u64(&mut self, arg0: u8) -> u64;
40     fn u16_as_u64(&mut self, arg0: u16) -> u64;
41     fn u32_as_u64(&mut self, arg0: u32) -> u64;
42     fn i64_as_u64(&mut self, arg0: i64) -> u64;
43     fn u64_add(&mut self, arg0: u64, arg1: u64) -> u64;
44     fn u64_sub(&mut self, arg0: u64, arg1: u64) -> u64;
45     fn u64_and(&mut self, arg0: u64, arg1: u64) -> u64;
46     fn ty_bits(&mut self, arg0: Type) -> u8;
47     fn ty_bits_u16(&mut self, arg0: Type) -> u16;
48     fn ty_bits_u64(&mut self, arg0: Type) -> u64;
49     fn ty_mask(&mut self, arg0: Type) -> u64;
50     fn ty_bytes(&mut self, arg0: Type) -> u16;
51     fn lane_type(&mut self, arg0: Type) -> Type;
52     fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
53     fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
54     fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
55     fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
56     fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
57     fn vec128(&mut self, arg0: Type) -> Option<Type>;
58     fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
59     fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
60     fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>;
61     fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>;
62     fn value_slice_len(&mut self, arg0: ValueSlice) -> usize;
63     fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value;
64     fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
65     fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
66     fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
67     fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
68     fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
69     fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
70     fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
71     fn first_result(&mut self, arg0: Inst) -> Option<Value>;
72     fn inst_data(&mut self, arg0: Inst) -> InstructionData;
73     fn value_type(&mut self, arg0: Value) -> Type;
74     fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
75     fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
76     fn emit(&mut self, arg0: &MInst) -> Unit;
77     fn emit_safepoint(&mut self, arg0: &MInst) -> Unit;
78     fn trap_code_division_by_zero(&mut self) -> TrapCode;
79     fn trap_code_integer_overflow(&mut self) -> TrapCode;
80     fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
81     fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
82     fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
83     fn symbol_value_data(
84         &mut self,
85         arg0: GlobalValue,
86     ) -> Option<(ExternalName, RelocDistance, i64)>;
87     fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
88     fn move_wide_const_from_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
89     fn move_wide_const_from_negated_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
90     fn imm_logic_from_u64(&mut self, arg0: u64, arg1: Type) -> Option<ImmLogic>;
91     fn imm_logic_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmLogic>;
92     fn imm_shift_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmShift>;
93     fn imm_shift_from_u8(&mut self, arg0: u8) -> ImmShift;
94     fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12>;
95     fn u8_into_uimm5(&mut self, arg0: u8) -> UImm5;
96     fn u8_into_imm12(&mut self, arg0: u8) -> Imm12;
97     fn u64_into_imm_logic(&mut self, arg0: Type, arg1: u64) -> ImmLogic;
98     fn imm12_from_negated_u64(&mut self, arg0: u64) -> Option<Imm12>;
99     fn lshl_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ShiftOpAndAmt>;
100     fn integral_ty(&mut self, arg0: Type) -> Option<Type>;
101     fn extended_value_from_value(&mut self, arg0: Value) -> Option<ExtendedValue>;
102     fn put_extended_in_reg(&mut self, arg0: &ExtendedValue) -> Reg;
103     fn get_extended_op(&mut self, arg0: &ExtendedValue) -> ExtendOp;
104     fn nzcv(&mut self, arg0: bool, arg1: bool, arg2: bool, arg3: bool) -> NZCV;
105     fn cond_br_zero(&mut self, arg0: Reg) -> CondBrKind;
106     fn cond_br_cond(&mut self, arg0: &Cond) -> CondBrKind;
107     fn zero_reg(&mut self) -> Reg;
108     fn writable_zero_reg(&mut self) -> WritableReg;
109     fn load_constant64_full(&mut self, arg0: u64) -> Reg;
110     fn sinkable_atomic_load(&mut self, arg0: Value) -> Option<SinkableAtomicLoad>;
111     fn sink_atomic_load(&mut self, arg0: &SinkableAtomicLoad) -> Reg;
112     fn safe_divisor_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
113     fn shift_mask(&mut self, arg0: Type) -> ImmLogic;
114     fn negate_imm_shift(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
115     fn rotr_mask(&mut self, arg0: Type) -> ImmLogic;
116     fn rotr_opposite_amount(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
117 }
118 
119 /// Internal type SideEffectNoResult: defined at src/prelude.isle line 385.
120 #[derive(Clone, Debug)]
121 pub enum SideEffectNoResult {
122     Inst { inst: MInst },
123 }
124 
125 /// Internal type ProducesFlags: defined at src/prelude.isle line 407.
126 #[derive(Clone, Debug)]
127 pub enum ProducesFlags {
128     ProducesFlagsSideEffect { inst: MInst },
129     ProducesFlagsReturnsReg { inst: MInst, result: Reg },
130     ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg },
131 }
132 
133 /// Internal type ConsumesFlags: defined at src/prelude.isle line 418.
134 #[derive(Clone, Debug)]
135 pub enum ConsumesFlags {
136     ConsumesFlagsReturnsResultWithProducer {
137         inst: MInst,
138         result: Reg,
139     },
140     ConsumesFlagsReturnsReg {
141         inst: MInst,
142         result: Reg,
143     },
144     ConsumesFlagsTwiceReturnsValueRegs {
145         inst1: MInst,
146         inst2: MInst,
147         result: ValueRegs,
148     },
149     ConsumesFlagsFourTimesReturnsValueRegs {
150         inst1: MInst,
151         inst2: MInst,
152         inst3: MInst,
153         inst4: MInst,
154         result: ValueRegs,
155     },
156 }
157 
158 /// Internal type MInst: defined at src/isa/aarch64/inst.isle line 2.
159 #[derive(Clone, Debug)]
160 pub enum MInst {
161     Nop0,
162     Nop4,
163     AluRRR {
164         alu_op: ALUOp,
165         size: OperandSize,
166         rd: WritableReg,
167         rn: Reg,
168         rm: Reg,
169     },
170     AluRRRR {
171         alu_op: ALUOp3,
172         rd: WritableReg,
173         rn: Reg,
174         rm: Reg,
175         ra: Reg,
176     },
177     AluRRImm12 {
178         alu_op: ALUOp,
179         size: OperandSize,
180         rd: WritableReg,
181         rn: Reg,
182         imm12: Imm12,
183     },
184     AluRRImmLogic {
185         alu_op: ALUOp,
186         size: OperandSize,
187         rd: WritableReg,
188         rn: Reg,
189         imml: ImmLogic,
190     },
191     AluRRImmShift {
192         alu_op: ALUOp,
193         size: OperandSize,
194         rd: WritableReg,
195         rn: Reg,
196         immshift: ImmShift,
197     },
198     AluRRRShift {
199         alu_op: ALUOp,
200         size: OperandSize,
201         rd: WritableReg,
202         rn: Reg,
203         rm: Reg,
204         shiftop: ShiftOpAndAmt,
205     },
206     AluRRRExtend {
207         alu_op: ALUOp,
208         size: OperandSize,
209         rd: WritableReg,
210         rn: Reg,
211         rm: Reg,
212         extendop: ExtendOp,
213     },
214     BitRR {
215         op: BitOp,
216         size: OperandSize,
217         rd: WritableReg,
218         rn: Reg,
219     },
220     ULoad8 {
221         rd: WritableReg,
222         mem: AMode,
223         flags: MemFlags,
224     },
225     SLoad8 {
226         rd: WritableReg,
227         mem: AMode,
228         flags: MemFlags,
229     },
230     ULoad16 {
231         rd: WritableReg,
232         mem: AMode,
233         flags: MemFlags,
234     },
235     SLoad16 {
236         rd: WritableReg,
237         mem: AMode,
238         flags: MemFlags,
239     },
240     ULoad32 {
241         rd: WritableReg,
242         mem: AMode,
243         flags: MemFlags,
244     },
245     SLoad32 {
246         rd: WritableReg,
247         mem: AMode,
248         flags: MemFlags,
249     },
250     ULoad64 {
251         rd: WritableReg,
252         mem: AMode,
253         flags: MemFlags,
254     },
255     Store8 {
256         rd: Reg,
257         mem: AMode,
258         flags: MemFlags,
259     },
260     Store16 {
261         rd: Reg,
262         mem: AMode,
263         flags: MemFlags,
264     },
265     Store32 {
266         rd: Reg,
267         mem: AMode,
268         flags: MemFlags,
269     },
270     Store64 {
271         rd: Reg,
272         mem: AMode,
273         flags: MemFlags,
274     },
275     StoreP64 {
276         rt: Reg,
277         rt2: Reg,
278         mem: PairAMode,
279         flags: MemFlags,
280     },
281     LoadP64 {
282         rt: WritableReg,
283         rt2: WritableReg,
284         mem: PairAMode,
285         flags: MemFlags,
286     },
287     Mov64 {
288         rd: WritableReg,
289         rm: Reg,
290     },
291     Mov32 {
292         rd: WritableReg,
293         rm: Reg,
294     },
295     MovZ {
296         rd: WritableReg,
297         imm: MoveWideConst,
298         size: OperandSize,
299     },
300     MovN {
301         rd: WritableReg,
302         imm: MoveWideConst,
303         size: OperandSize,
304     },
305     MovK {
306         rd: WritableReg,
307         imm: MoveWideConst,
308         size: OperandSize,
309     },
310     Extend {
311         rd: WritableReg,
312         rn: Reg,
313         signed: bool,
314         from_bits: u8,
315         to_bits: u8,
316     },
317     CSel {
318         rd: WritableReg,
319         cond: Cond,
320         rn: Reg,
321         rm: Reg,
322     },
323     CSet {
324         rd: WritableReg,
325         cond: Cond,
326     },
327     CSetm {
328         rd: WritableReg,
329         cond: Cond,
330     },
331     CCmpImm {
332         size: OperandSize,
333         rn: Reg,
334         imm: UImm5,
335         nzcv: NZCV,
336         cond: Cond,
337     },
338     AtomicRMWLoop {
339         ty: Type,
340         op: AtomicRmwOp,
341     },
342     AtomicRMW {
343         op: AtomicRMWOp,
344         rs: Reg,
345         rt: WritableReg,
346         rn: Reg,
347         ty: Type,
348     },
349     AtomicCAS {
350         rs: WritableReg,
351         rt: Reg,
352         rn: Reg,
353         ty: Type,
354     },
355     AtomicCASLoop {
356         ty: Type,
357     },
358     LoadAcquire {
359         access_ty: Type,
360         rt: WritableReg,
361         rn: Reg,
362     },
363     StoreRelease {
364         access_ty: Type,
365         rt: Reg,
366         rn: Reg,
367     },
368     Fence,
369     FpuMove64 {
370         rd: WritableReg,
371         rn: Reg,
372     },
373     FpuMove128 {
374         rd: WritableReg,
375         rn: Reg,
376     },
377     FpuMoveFromVec {
378         rd: WritableReg,
379         rn: Reg,
380         idx: u8,
381         size: VectorSize,
382     },
383     FpuExtend {
384         rd: WritableReg,
385         rn: Reg,
386         size: ScalarSize,
387     },
388     FpuRR {
389         fpu_op: FPUOp1,
390         rd: WritableReg,
391         rn: Reg,
392     },
393     FpuRRR {
394         fpu_op: FPUOp2,
395         rd: WritableReg,
396         rn: Reg,
397         rm: Reg,
398     },
399     FpuRRI {
400         fpu_op: FPUOpRI,
401         rd: WritableReg,
402         rn: Reg,
403     },
404     FpuRRRR {
405         fpu_op: FPUOp3,
406         rd: WritableReg,
407         rn: Reg,
408         rm: Reg,
409         ra: Reg,
410     },
411     FpuCmp32 {
412         rn: Reg,
413         rm: Reg,
414     },
415     FpuCmp64 {
416         rn: Reg,
417         rm: Reg,
418     },
419     FpuLoad32 {
420         rd: WritableReg,
421         mem: AMode,
422         flags: MemFlags,
423     },
424     FpuStore32 {
425         rd: Reg,
426         mem: AMode,
427         flags: MemFlags,
428     },
429     FpuLoad64 {
430         rd: WritableReg,
431         mem: AMode,
432         flags: MemFlags,
433     },
434     FpuStore64 {
435         rd: Reg,
436         mem: AMode,
437         flags: MemFlags,
438     },
439     FpuLoad128 {
440         rd: WritableReg,
441         mem: AMode,
442         flags: MemFlags,
443     },
444     FpuStore128 {
445         rd: Reg,
446         mem: AMode,
447         flags: MemFlags,
448     },
449     FpuLoadP64 {
450         rt: WritableReg,
451         rt2: WritableReg,
452         mem: PairAMode,
453         flags: MemFlags,
454     },
455     FpuStoreP64 {
456         rt: Reg,
457         rt2: Reg,
458         mem: PairAMode,
459         flags: MemFlags,
460     },
461     FpuLoadP128 {
462         rt: WritableReg,
463         rt2: WritableReg,
464         mem: PairAMode,
465         flags: MemFlags,
466     },
467     FpuStoreP128 {
468         rt: Reg,
469         rt2: Reg,
470         mem: PairAMode,
471         flags: MemFlags,
472     },
473     LoadFpuConst64 {
474         rd: WritableReg,
475         const_data: u64,
476     },
477     LoadFpuConst128 {
478         rd: WritableReg,
479         const_data: u128,
480     },
481     FpuToInt {
482         op: FpuToIntOp,
483         rd: WritableReg,
484         rn: Reg,
485     },
486     IntToFpu {
487         op: IntToFpuOp,
488         rd: WritableReg,
489         rn: Reg,
490     },
491     FpuCSel32 {
492         rd: WritableReg,
493         rn: Reg,
494         rm: Reg,
495         cond: Cond,
496     },
497     FpuCSel64 {
498         rd: WritableReg,
499         rn: Reg,
500         rm: Reg,
501         cond: Cond,
502     },
503     FpuRound {
504         op: FpuRoundMode,
505         rd: WritableReg,
506         rn: Reg,
507     },
508     MovToFpu {
509         rd: WritableReg,
510         rn: Reg,
511         size: ScalarSize,
512     },
513     FpuMoveFPImm {
514         rd: WritableReg,
515         imm: ASIMDFPModImm,
516         size: ScalarSize,
517     },
518     MovToVec {
519         rd: WritableReg,
520         rn: Reg,
521         idx: u8,
522         size: VectorSize,
523     },
524     MovFromVec {
525         rd: WritableReg,
526         rn: Reg,
527         idx: u8,
528         size: VectorSize,
529     },
530     MovFromVecSigned {
531         rd: WritableReg,
532         rn: Reg,
533         idx: u8,
534         size: VectorSize,
535         scalar_size: OperandSize,
536     },
537     VecDup {
538         rd: WritableReg,
539         rn: Reg,
540         size: VectorSize,
541     },
542     VecDupFromFpu {
543         rd: WritableReg,
544         rn: Reg,
545         size: VectorSize,
546     },
547     VecDupFPImm {
548         rd: WritableReg,
549         imm: ASIMDFPModImm,
550         size: VectorSize,
551     },
552     VecDupImm {
553         rd: WritableReg,
554         imm: ASIMDMovModImm,
555         invert: bool,
556         size: VectorSize,
557     },
558     VecExtend {
559         t: VecExtendOp,
560         rd: WritableReg,
561         rn: Reg,
562         high_half: bool,
563     },
564     VecMovElement {
565         rd: WritableReg,
566         rn: Reg,
567         dest_idx: u8,
568         src_idx: u8,
569         size: VectorSize,
570     },
571     VecRRLong {
572         op: VecRRLongOp,
573         rd: WritableReg,
574         rn: Reg,
575         high_half: bool,
576     },
577     VecRRNarrow {
578         op: VecRRNarrowOp,
579         rd: WritableReg,
580         rn: Reg,
581         high_half: bool,
582     },
583     VecRRPair {
584         op: VecPairOp,
585         rd: WritableReg,
586         rn: Reg,
587     },
588     VecRRRLong {
589         alu_op: VecRRRLongOp,
590         rd: WritableReg,
591         rn: Reg,
592         rm: Reg,
593         high_half: bool,
594     },
595     VecRRPairLong {
596         op: VecRRPairLongOp,
597         rd: WritableReg,
598         rn: Reg,
599     },
600     VecRRR {
601         alu_op: VecALUOp,
602         rd: WritableReg,
603         rn: Reg,
604         rm: Reg,
605         size: VectorSize,
606     },
607     VecMisc {
608         op: VecMisc2,
609         rd: WritableReg,
610         rn: Reg,
611         size: VectorSize,
612     },
613     VecLanes {
614         op: VecLanesOp,
615         rd: WritableReg,
616         rn: Reg,
617         size: VectorSize,
618     },
619     VecShiftImm {
620         op: VecShiftImmOp,
621         rd: WritableReg,
622         rn: Reg,
623         size: VectorSize,
624         imm: u8,
625     },
626     VecExtract {
627         rd: WritableReg,
628         rn: Reg,
629         rm: Reg,
630         imm4: u8,
631     },
632     VecTbl {
633         rd: WritableReg,
634         rn: Reg,
635         rm: Reg,
636         is_extension: bool,
637     },
638     VecTbl2 {
639         rd: WritableReg,
640         rn: Reg,
641         rn2: Reg,
642         rm: Reg,
643         is_extension: bool,
644     },
645     VecLoadReplicate {
646         rd: WritableReg,
647         rn: Reg,
648         size: VectorSize,
649     },
650     VecCSel {
651         rd: WritableReg,
652         rn: Reg,
653         rm: Reg,
654         cond: Cond,
655     },
656     MovToNZCV {
657         rn: Reg,
658     },
659     MovFromNZCV {
660         rd: WritableReg,
661     },
662     Call {
663         info: BoxCallInfo,
664     },
665     CallInd {
666         info: BoxCallIndInfo,
667     },
668     Ret,
669     EpiloguePlaceholder,
670     Jump {
671         dest: BranchTarget,
672     },
673     CondBr {
674         taken: BranchTarget,
675         not_taken: BranchTarget,
676         kind: CondBrKind,
677     },
678     TrapIf {
679         kind: CondBrKind,
680         trap_code: TrapCode,
681     },
682     IndirectBr {
683         rn: Reg,
684         targets: VecMachLabel,
685     },
686     Brk,
687     Udf {
688         trap_code: TrapCode,
689     },
690     Adr {
691         rd: WritableReg,
692         off: i32,
693     },
694     Word4 {
695         data: u32,
696     },
697     Word8 {
698         data: u64,
699     },
700     JTSequence {
701         info: BoxJTSequenceInfo,
702         ridx: Reg,
703         rtmp1: WritableReg,
704         rtmp2: WritableReg,
705     },
706     LoadExtName {
707         rd: WritableReg,
708         name: BoxExternalName,
709         offset: i64,
710     },
711     LoadAddr {
712         rd: WritableReg,
713         mem: AMode,
714     },
715     VirtualSPOffsetAdj {
716         offset: i64,
717     },
718     EmitIsland {
719         needed_space: CodeOffset,
720     },
721     ElfTlsGetAddr {
722         symbol: ExternalName,
723     },
724     ValueLabelMarker {
725         reg: Reg,
726         label: ValueLabel,
727     },
728     Unwind {
729         inst: UnwindInst,
730     },
731 }
732 
733 /// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 796.
734 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
735 pub enum ALUOp {
736     Add,
737     Sub,
738     Orr,
739     OrrNot,
740     And,
741     AndS,
742     AndNot,
743     Eor,
744     EorNot,
745     AddS,
746     SubS,
747     SMulH,
748     UMulH,
749     SDiv,
750     UDiv,
751     RotR,
752     Lsr,
753     Asr,
754     Lsl,
755     Adc,
756     AdcS,
757     Sbc,
758     SbcS,
759 }
760 
761 /// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 834.
762 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
763 pub enum ALUOp3 {
764     MAdd32,
765     MAdd64,
766     MSub32,
767     MSub64,
768 }
769 
770 /// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 877.
771 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
772 pub enum BitOp {
773     RBit,
774     Clz,
775     Cls,
776 }
777 
778 /// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 944.
779 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
780 pub enum FPUOp1 {
781     Abs32,
782     Abs64,
783     Neg32,
784     Neg64,
785     Sqrt32,
786     Sqrt64,
787     Cvt32To64,
788     Cvt64To32,
789 }
790 
791 /// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 957.
792 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
793 pub enum FPUOp2 {
794     Add32,
795     Add64,
796     Sub32,
797     Sub64,
798     Mul32,
799     Mul64,
800     Div32,
801     Div64,
802     Max32,
803     Max64,
804     Min32,
805     Min64,
806     Sqadd64,
807     Uqadd64,
808     Sqsub64,
809     Uqsub64,
810 }
811 
812 /// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 982.
813 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
814 pub enum FPUOp3 {
815     MAdd32,
816     MAdd64,
817 }
818 
819 /// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 989.
820 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
821 pub enum FpuToIntOp {
822     F32ToU32,
823     F32ToI32,
824     F32ToU64,
825     F32ToI64,
826     F64ToU32,
827     F64ToI32,
828     F64ToU64,
829     F64ToI64,
830 }
831 
832 /// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 1002.
833 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
834 pub enum IntToFpuOp {
835     U32ToF32,
836     I32ToF32,
837     U32ToF64,
838     I32ToF64,
839     U64ToF32,
840     I64ToF32,
841     U64ToF64,
842     I64ToF64,
843 }
844 
845 /// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 1016.
846 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
847 pub enum FpuRoundMode {
848     Minus32,
849     Minus64,
850     Plus32,
851     Plus64,
852     Zero32,
853     Zero64,
854     Nearest32,
855     Nearest64,
856 }
857 
858 /// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 1029.
859 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
860 pub enum VecExtendOp {
861     Sxtl8,
862     Sxtl16,
863     Sxtl32,
864     Uxtl8,
865     Uxtl16,
866     Uxtl32,
867 }
868 
869 /// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1046.
870 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
871 pub enum VecALUOp {
872     Sqadd,
873     Uqadd,
874     Sqsub,
875     Uqsub,
876     Cmeq,
877     Cmge,
878     Cmgt,
879     Cmhs,
880     Cmhi,
881     Fcmeq,
882     Fcmgt,
883     Fcmge,
884     And,
885     Bic,
886     Orr,
887     Eor,
888     Bsl,
889     Umaxp,
890     Add,
891     Sub,
892     Mul,
893     Sshl,
894     Ushl,
895     Umin,
896     Smin,
897     Umax,
898     Smax,
899     Urhadd,
900     Fadd,
901     Fsub,
902     Fdiv,
903     Fmax,
904     Fmin,
905     Fmul,
906     Addp,
907     Zip1,
908     Sqrdmulh,
909 }
910 
911 /// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1125.
912 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
913 pub enum VecMisc2 {
914     Not,
915     Neg,
916     Abs,
917     Fabs,
918     Fneg,
919     Fsqrt,
920     Rev64,
921     Fcvtzs,
922     Fcvtzu,
923     Scvtf,
924     Ucvtf,
925     Frintn,
926     Frintz,
927     Frintm,
928     Frintp,
929     Cnt,
930     Cmeq0,
931 }
932 
933 /// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1164.
934 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
935 pub enum VecRRLongOp {
936     Fcvtl16,
937     Fcvtl32,
938     Shll8,
939     Shll16,
940     Shll32,
941 }
942 
943 /// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1179.
944 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
945 pub enum VecRRNarrowOp {
946     Xtn16,
947     Xtn32,
948     Xtn64,
949     Sqxtn16,
950     Sqxtn32,
951     Sqxtn64,
952     Sqxtun16,
953     Sqxtun32,
954     Sqxtun64,
955     Uqxtn16,
956     Uqxtn32,
957     Uqxtn64,
958     Fcvtn32,
959     Fcvtn64,
960 }
961 
962 /// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1211.
963 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
964 pub enum VecRRRLongOp {
965     Smull8,
966     Smull16,
967     Smull32,
968     Umull8,
969     Umull16,
970     Umull32,
971     Umlal8,
972     Umlal16,
973     Umlal32,
974 }
975 
976 /// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1228.
977 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
978 pub enum VecPairOp {
979     Addp,
980 }
981 
982 /// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1236.
983 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
984 pub enum VecRRPairLongOp {
985     Saddlp8,
986     Saddlp16,
987     Uaddlp8,
988     Uaddlp16,
989 }
990 
991 /// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1247.
992 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
993 pub enum VecLanesOp {
994     Addv,
995     Uminv,
996 }
997 
998 /// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1256.
999 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1000 pub enum VecShiftImmOp {
1001     Shl,
1002     Ushr,
1003     Sshr,
1004 }
1005 
1006 /// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1267.
1007 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1008 pub enum AtomicRMWOp {
1009     Add,
1010     Clr,
1011     Eor,
1012     Set,
1013     Smax,
1014     Smin,
1015     Umax,
1016     Umin,
1017 }
1018 
1019 // Generated as internal constructor for term output_reg.
1020 pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
1021     let pattern0_0 = arg0;
1022     // Rule at src/prelude.isle line 86.
1023     let expr0_0 = C::value_reg(ctx, pattern0_0);
1024     let expr1_0 = C::output(ctx, expr0_0);
1025     return Some(expr1_0);
1026 }
1027 
1028 // Generated as internal constructor for term output_value.
1029 pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> {
1030     let pattern0_0 = arg0;
1031     // Rule at src/prelude.isle line 90.
1032     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1033     let expr1_0 = C::output(ctx, expr0_0);
1034     return Some(expr1_0);
1035 }
1036 
1037 // Generated as internal constructor for term temp_reg.
1038 pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
1039     let pattern0_0 = arg0;
1040     // Rule at src/prelude.isle line 110.
1041     let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
1042     let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
1043     return Some(expr1_0);
1044 }
1045 
1046 // Generated as internal constructor for term lo_reg.
1047 pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
1048     let pattern0_0 = arg0;
1049     // Rule at src/prelude.isle line 145.
1050     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1051     let expr1_0: usize = 0;
1052     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1053     return Some(expr2_0);
1054 }
1055 
1056 // Generated as internal constructor for term side_effect.
1057 pub fn constructor_side_effect<C: Context>(
1058     ctx: &mut C,
1059     arg0: &SideEffectNoResult,
1060 ) -> Option<InstOutput> {
1061     let pattern0_0 = arg0;
1062     if let &SideEffectNoResult::Inst {
1063         inst: ref pattern1_0,
1064     } = pattern0_0
1065     {
1066         // Rule at src/prelude.isle line 390.
1067         let expr0_0 = C::emit(ctx, pattern1_0);
1068         let expr1_0 = C::output_none(ctx);
1069         return Some(expr1_0);
1070     }
1071     return None;
1072 }
1073 
1074 // Generated as internal constructor for term safepoint.
1075 pub fn constructor_safepoint<C: Context>(
1076     ctx: &mut C,
1077     arg0: &SideEffectNoResult,
1078 ) -> Option<InstOutput> {
1079     let pattern0_0 = arg0;
1080     if let &SideEffectNoResult::Inst {
1081         inst: ref pattern1_0,
1082     } = pattern0_0
1083     {
1084         // Rule at src/prelude.isle line 396.
1085         let expr0_0 = C::emit_safepoint(ctx, pattern1_0);
1086         let expr1_0 = C::output_none(ctx);
1087         return Some(expr1_0);
1088     }
1089     return None;
1090 }
1091 
1092 // Generated as internal constructor for term produces_flags_get_reg.
1093 pub fn constructor_produces_flags_get_reg<C: Context>(
1094     ctx: &mut C,
1095     arg0: &ProducesFlags,
1096 ) -> Option<Reg> {
1097     let pattern0_0 = arg0;
1098     if let &ProducesFlags::ProducesFlagsReturnsReg {
1099         inst: ref pattern1_0,
1100         result: pattern1_1,
1101     } = pattern0_0
1102     {
1103         // Rule at src/prelude.isle line 434.
1104         return Some(pattern1_1);
1105     }
1106     return None;
1107 }
1108 
1109 // Generated as internal constructor for term produces_flags_ignore.
1110 pub fn constructor_produces_flags_ignore<C: Context>(
1111     ctx: &mut C,
1112     arg0: &ProducesFlags,
1113 ) -> Option<ProducesFlags> {
1114     let pattern0_0 = arg0;
1115     match pattern0_0 {
1116         &ProducesFlags::ProducesFlagsReturnsReg {
1117             inst: ref pattern1_0,
1118             result: pattern1_1,
1119         } => {
1120             // Rule at src/prelude.isle line 439.
1121             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1122                 inst: pattern1_0.clone(),
1123             };
1124             return Some(expr0_0);
1125         }
1126         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1127             inst: ref pattern1_0,
1128             result: pattern1_1,
1129         } => {
1130             // Rule at src/prelude.isle line 441.
1131             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1132                 inst: pattern1_0.clone(),
1133             };
1134             return Some(expr0_0);
1135         }
1136         _ => {}
1137     }
1138     return None;
1139 }
1140 
1141 // Generated as internal constructor for term consumes_flags_concat.
1142 pub fn constructor_consumes_flags_concat<C: Context>(
1143     ctx: &mut C,
1144     arg0: &ConsumesFlags,
1145     arg1: &ConsumesFlags,
1146 ) -> Option<ConsumesFlags> {
1147     let pattern0_0 = arg0;
1148     if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1149         inst: ref pattern1_0,
1150         result: pattern1_1,
1151     } = pattern0_0
1152     {
1153         let pattern2_0 = arg1;
1154         if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1155             inst: ref pattern3_0,
1156             result: pattern3_1,
1157         } = pattern2_0
1158         {
1159             // Rule at src/prelude.isle line 448.
1160             let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1161             let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1162                 inst1: pattern1_0.clone(),
1163                 inst2: pattern3_0.clone(),
1164                 result: expr0_0,
1165             };
1166             return Some(expr1_0);
1167         }
1168     }
1169     return None;
1170 }
1171 
1172 // Generated as internal constructor for term with_flags.
1173 pub fn constructor_with_flags<C: Context>(
1174     ctx: &mut C,
1175     arg0: &ProducesFlags,
1176     arg1: &ConsumesFlags,
1177 ) -> Option<ValueRegs> {
1178     let pattern0_0 = arg0;
1179     match pattern0_0 {
1180         &ProducesFlags::ProducesFlagsSideEffect {
1181             inst: ref pattern1_0,
1182         } => {
1183             let pattern2_0 = arg1;
1184             match pattern2_0 {
1185                 &ConsumesFlags::ConsumesFlagsReturnsReg {
1186                     inst: ref pattern3_0,
1187                     result: pattern3_1,
1188                 } => {
1189                     // Rule at src/prelude.isle line 473.
1190                     let expr0_0 = C::emit(ctx, pattern1_0);
1191                     let expr1_0 = C::emit(ctx, pattern3_0);
1192                     let expr2_0 = C::value_reg(ctx, pattern3_1);
1193                     return Some(expr2_0);
1194                 }
1195                 &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1196                     inst1: ref pattern3_0,
1197                     inst2: ref pattern3_1,
1198                     result: pattern3_2,
1199                 } => {
1200                     // Rule at src/prelude.isle line 479.
1201                     let expr0_0 = C::emit(ctx, pattern1_0);
1202                     let expr1_0 = C::emit(ctx, pattern3_0);
1203                     let expr2_0 = C::emit(ctx, pattern3_1);
1204                     return Some(pattern3_2);
1205                 }
1206                 &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs {
1207                     inst1: ref pattern3_0,
1208                     inst2: ref pattern3_1,
1209                     inst3: ref pattern3_2,
1210                     inst4: ref pattern3_3,
1211                     result: pattern3_4,
1212                 } => {
1213                     // Rule at src/prelude.isle line 491.
1214                     let expr0_0 = C::emit(ctx, pattern1_0);
1215                     let expr1_0 = C::emit(ctx, pattern3_0);
1216                     let expr2_0 = C::emit(ctx, pattern3_1);
1217                     let expr3_0 = C::emit(ctx, pattern3_2);
1218                     let expr4_0 = C::emit(ctx, pattern3_3);
1219                     return Some(pattern3_4);
1220                 }
1221                 _ => {}
1222             }
1223         }
1224         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1225             inst: ref pattern1_0,
1226             result: pattern1_1,
1227         } => {
1228             let pattern2_0 = arg1;
1229             if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1230                 inst: ref pattern3_0,
1231                 result: pattern3_1,
1232             } = pattern2_0
1233             {
1234                 // Rule at src/prelude.isle line 467.
1235                 let expr0_0 = C::emit(ctx, pattern1_0);
1236                 let expr1_0 = C::emit(ctx, pattern3_0);
1237                 let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1238                 return Some(expr2_0);
1239             }
1240         }
1241         _ => {}
1242     }
1243     return None;
1244 }
1245 
1246 // Generated as internal constructor for term with_flags_reg.
1247 pub fn constructor_with_flags_reg<C: Context>(
1248     ctx: &mut C,
1249     arg0: &ProducesFlags,
1250     arg1: &ConsumesFlags,
1251 ) -> Option<Reg> {
1252     let pattern0_0 = arg0;
1253     let pattern1_0 = arg1;
1254     // Rule at src/prelude.isle line 508.
1255     let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?;
1256     let expr1_0: usize = 0;
1257     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1258     return Some(expr2_0);
1259 }
1260 
1261 // Generated as internal constructor for term operand_size.
1262 pub fn constructor_operand_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
1263     let pattern0_0 = arg0;
1264     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
1265         // Rule at src/isa/aarch64/inst.isle line 895.
1266         let expr0_0 = OperandSize::Size32;
1267         return Some(expr0_0);
1268     }
1269     if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
1270         // Rule at src/isa/aarch64/inst.isle line 896.
1271         let expr0_0 = OperandSize::Size64;
1272         return Some(expr0_0);
1273     }
1274     return None;
1275 }
1276 
1277 // Generated as internal constructor for term vector_size.
1278 pub fn constructor_vector_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<VectorSize> {
1279     let pattern0_0 = arg0;
1280     if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
1281         if pattern1_0 == 8 {
1282             if pattern1_1 == 16 {
1283                 // Rule at src/isa/aarch64/inst.isle line 938.
1284                 let expr0_0 = VectorSize::Size8x16;
1285                 return Some(expr0_0);
1286             }
1287         }
1288         if pattern1_0 == 16 {
1289             if pattern1_1 == 8 {
1290                 // Rule at src/isa/aarch64/inst.isle line 939.
1291                 let expr0_0 = VectorSize::Size16x8;
1292                 return Some(expr0_0);
1293             }
1294         }
1295         if pattern1_0 == 32 {
1296             if pattern1_1 == 4 {
1297                 // Rule at src/isa/aarch64/inst.isle line 940.
1298                 let expr0_0 = VectorSize::Size32x4;
1299                 return Some(expr0_0);
1300             }
1301         }
1302         if pattern1_0 == 64 {
1303             if pattern1_1 == 2 {
1304                 // Rule at src/isa/aarch64/inst.isle line 941.
1305                 let expr0_0 = VectorSize::Size64x2;
1306                 return Some(expr0_0);
1307             }
1308         }
1309     }
1310     return None;
1311 }
1312 
1313 // Generated as internal constructor for term movz.
1314 pub fn constructor_movz<C: Context>(
1315     ctx: &mut C,
1316     arg0: MoveWideConst,
1317     arg1: &OperandSize,
1318 ) -> Option<Reg> {
1319     let pattern0_0 = arg0;
1320     let pattern1_0 = arg1;
1321     // Rule at src/isa/aarch64/inst.isle line 1363.
1322     let expr0_0: Type = I64;
1323     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1324     let expr2_0 = MInst::MovZ {
1325         rd: expr1_0,
1326         imm: pattern0_0,
1327         size: pattern1_0.clone(),
1328     };
1329     let expr3_0 = C::emit(ctx, &expr2_0);
1330     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1331     return Some(expr4_0);
1332 }
1333 
1334 // Generated as internal constructor for term movn.
1335 pub fn constructor_movn<C: Context>(
1336     ctx: &mut C,
1337     arg0: MoveWideConst,
1338     arg1: &OperandSize,
1339 ) -> Option<Reg> {
1340     let pattern0_0 = arg0;
1341     let pattern1_0 = arg1;
1342     // Rule at src/isa/aarch64/inst.isle line 1370.
1343     let expr0_0: Type = I64;
1344     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1345     let expr2_0 = MInst::MovN {
1346         rd: expr1_0,
1347         imm: pattern0_0,
1348         size: pattern1_0.clone(),
1349     };
1350     let expr3_0 = C::emit(ctx, &expr2_0);
1351     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1352     return Some(expr4_0);
1353 }
1354 
1355 // Generated as internal constructor for term alu_rr_imm_logic.
1356 pub fn constructor_alu_rr_imm_logic<C: Context>(
1357     ctx: &mut C,
1358     arg0: &ALUOp,
1359     arg1: Type,
1360     arg2: Reg,
1361     arg3: ImmLogic,
1362 ) -> Option<Reg> {
1363     let pattern0_0 = arg0;
1364     let pattern1_0 = arg1;
1365     let pattern2_0 = arg2;
1366     let pattern3_0 = arg3;
1367     // Rule at src/isa/aarch64/inst.isle line 1377.
1368     let expr0_0: Type = I64;
1369     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1370     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1371     let expr3_0 = MInst::AluRRImmLogic {
1372         alu_op: pattern0_0.clone(),
1373         size: expr2_0,
1374         rd: expr1_0,
1375         rn: pattern2_0,
1376         imml: pattern3_0,
1377     };
1378     let expr4_0 = C::emit(ctx, &expr3_0);
1379     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1380     return Some(expr5_0);
1381 }
1382 
1383 // Generated as internal constructor for term alu_rr_imm_shift.
1384 pub fn constructor_alu_rr_imm_shift<C: Context>(
1385     ctx: &mut C,
1386     arg0: &ALUOp,
1387     arg1: Type,
1388     arg2: Reg,
1389     arg3: ImmShift,
1390 ) -> Option<Reg> {
1391     let pattern0_0 = arg0;
1392     let pattern1_0 = arg1;
1393     let pattern2_0 = arg2;
1394     let pattern3_0 = arg3;
1395     // Rule at src/isa/aarch64/inst.isle line 1384.
1396     let expr0_0: Type = I64;
1397     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1398     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1399     let expr3_0 = MInst::AluRRImmShift {
1400         alu_op: pattern0_0.clone(),
1401         size: expr2_0,
1402         rd: expr1_0,
1403         rn: pattern2_0,
1404         immshift: pattern3_0,
1405     };
1406     let expr4_0 = C::emit(ctx, &expr3_0);
1407     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1408     return Some(expr5_0);
1409 }
1410 
1411 // Generated as internal constructor for term alu_rrr.
1412 pub fn constructor_alu_rrr<C: Context>(
1413     ctx: &mut C,
1414     arg0: &ALUOp,
1415     arg1: Type,
1416     arg2: Reg,
1417     arg3: Reg,
1418 ) -> Option<Reg> {
1419     let pattern0_0 = arg0;
1420     let pattern1_0 = arg1;
1421     let pattern2_0 = arg2;
1422     let pattern3_0 = arg3;
1423     // Rule at src/isa/aarch64/inst.isle line 1391.
1424     let expr0_0: Type = I64;
1425     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1426     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1427     let expr3_0 = MInst::AluRRR {
1428         alu_op: pattern0_0.clone(),
1429         size: expr2_0,
1430         rd: expr1_0,
1431         rn: pattern2_0,
1432         rm: pattern3_0,
1433     };
1434     let expr4_0 = C::emit(ctx, &expr3_0);
1435     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1436     return Some(expr5_0);
1437 }
1438 
1439 // Generated as internal constructor for term vec_rrr.
1440 pub fn constructor_vec_rrr<C: Context>(
1441     ctx: &mut C,
1442     arg0: &VecALUOp,
1443     arg1: Reg,
1444     arg2: Reg,
1445     arg3: &VectorSize,
1446 ) -> Option<Reg> {
1447     let pattern0_0 = arg0;
1448     let pattern1_0 = arg1;
1449     let pattern2_0 = arg2;
1450     let pattern3_0 = arg3;
1451     // Rule at src/isa/aarch64/inst.isle line 1398.
1452     let expr0_0: Type = I8X16;
1453     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1454     let expr2_0 = MInst::VecRRR {
1455         alu_op: pattern0_0.clone(),
1456         rd: expr1_0,
1457         rn: pattern1_0,
1458         rm: pattern2_0,
1459         size: pattern3_0.clone(),
1460     };
1461     let expr3_0 = C::emit(ctx, &expr2_0);
1462     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1463     return Some(expr4_0);
1464 }
1465 
1466 // Generated as internal constructor for term vec_lanes.
1467 pub fn constructor_vec_lanes<C: Context>(
1468     ctx: &mut C,
1469     arg0: &VecLanesOp,
1470     arg1: Reg,
1471     arg2: &VectorSize,
1472 ) -> Option<Reg> {
1473     let pattern0_0 = arg0;
1474     let pattern1_0 = arg1;
1475     let pattern2_0 = arg2;
1476     // Rule at src/isa/aarch64/inst.isle line 1405.
1477     let expr0_0: Type = I8X16;
1478     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1479     let expr2_0 = MInst::VecLanes {
1480         op: pattern0_0.clone(),
1481         rd: expr1_0,
1482         rn: pattern1_0,
1483         size: pattern2_0.clone(),
1484     };
1485     let expr3_0 = C::emit(ctx, &expr2_0);
1486     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1487     return Some(expr4_0);
1488 }
1489 
1490 // Generated as internal constructor for term vec_dup.
1491 pub fn constructor_vec_dup<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
1492     let pattern0_0 = arg0;
1493     let pattern1_0 = arg1;
1494     // Rule at src/isa/aarch64/inst.isle line 1412.
1495     let expr0_0: Type = I8X16;
1496     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1497     let expr2_0 = MInst::VecDup {
1498         rd: expr1_0,
1499         rn: pattern0_0,
1500         size: pattern1_0.clone(),
1501     };
1502     let expr3_0 = C::emit(ctx, &expr2_0);
1503     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1504     return Some(expr4_0);
1505 }
1506 
1507 // Generated as internal constructor for term alu_rr_imm12.
1508 pub fn constructor_alu_rr_imm12<C: Context>(
1509     ctx: &mut C,
1510     arg0: &ALUOp,
1511     arg1: Type,
1512     arg2: Reg,
1513     arg3: Imm12,
1514 ) -> Option<Reg> {
1515     let pattern0_0 = arg0;
1516     let pattern1_0 = arg1;
1517     let pattern2_0 = arg2;
1518     let pattern3_0 = arg3;
1519     // Rule at src/isa/aarch64/inst.isle line 1419.
1520     let expr0_0: Type = I64;
1521     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1522     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1523     let expr3_0 = MInst::AluRRImm12 {
1524         alu_op: pattern0_0.clone(),
1525         size: expr2_0,
1526         rd: expr1_0,
1527         rn: pattern2_0,
1528         imm12: pattern3_0,
1529     };
1530     let expr4_0 = C::emit(ctx, &expr3_0);
1531     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1532     return Some(expr5_0);
1533 }
1534 
1535 // Generated as internal constructor for term alu_rrr_shift.
1536 pub fn constructor_alu_rrr_shift<C: Context>(
1537     ctx: &mut C,
1538     arg0: &ALUOp,
1539     arg1: Type,
1540     arg2: Reg,
1541     arg3: Reg,
1542     arg4: ShiftOpAndAmt,
1543 ) -> Option<Reg> {
1544     let pattern0_0 = arg0;
1545     let pattern1_0 = arg1;
1546     let pattern2_0 = arg2;
1547     let pattern3_0 = arg3;
1548     let pattern4_0 = arg4;
1549     // Rule at src/isa/aarch64/inst.isle line 1426.
1550     let expr0_0: Type = I64;
1551     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1552     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1553     let expr3_0 = MInst::AluRRRShift {
1554         alu_op: pattern0_0.clone(),
1555         size: expr2_0,
1556         rd: expr1_0,
1557         rn: pattern2_0,
1558         rm: pattern3_0,
1559         shiftop: pattern4_0,
1560     };
1561     let expr4_0 = C::emit(ctx, &expr3_0);
1562     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1563     return Some(expr5_0);
1564 }
1565 
1566 // Generated as internal constructor for term alu_rrr_extend.
1567 pub fn constructor_alu_rrr_extend<C: Context>(
1568     ctx: &mut C,
1569     arg0: &ALUOp,
1570     arg1: Type,
1571     arg2: Reg,
1572     arg3: Reg,
1573     arg4: &ExtendOp,
1574 ) -> Option<Reg> {
1575     let pattern0_0 = arg0;
1576     let pattern1_0 = arg1;
1577     let pattern2_0 = arg2;
1578     let pattern3_0 = arg3;
1579     let pattern4_0 = arg4;
1580     // Rule at src/isa/aarch64/inst.isle line 1433.
1581     let expr0_0: Type = I64;
1582     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1583     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1584     let expr3_0 = MInst::AluRRRExtend {
1585         alu_op: pattern0_0.clone(),
1586         size: expr2_0,
1587         rd: expr1_0,
1588         rn: pattern2_0,
1589         rm: pattern3_0,
1590         extendop: pattern4_0.clone(),
1591     };
1592     let expr4_0 = C::emit(ctx, &expr3_0);
1593     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1594     return Some(expr5_0);
1595 }
1596 
1597 // Generated as internal constructor for term alu_rr_extend_reg.
1598 pub fn constructor_alu_rr_extend_reg<C: Context>(
1599     ctx: &mut C,
1600     arg0: &ALUOp,
1601     arg1: Type,
1602     arg2: Reg,
1603     arg3: &ExtendedValue,
1604 ) -> Option<Reg> {
1605     let pattern0_0 = arg0;
1606     let pattern1_0 = arg1;
1607     let pattern2_0 = arg2;
1608     let pattern3_0 = arg3;
1609     // Rule at src/isa/aarch64/inst.isle line 1441.
1610     let expr0_0 = C::put_extended_in_reg(ctx, pattern3_0);
1611     let expr1_0 = C::get_extended_op(ctx, pattern3_0);
1612     let expr2_0 =
1613         constructor_alu_rrr_extend(ctx, pattern0_0, pattern1_0, pattern2_0, expr0_0, &expr1_0)?;
1614     return Some(expr2_0);
1615 }
1616 
1617 // Generated as internal constructor for term alu_rrrr.
1618 pub fn constructor_alu_rrrr<C: Context>(
1619     ctx: &mut C,
1620     arg0: &ALUOp3,
1621     arg1: Reg,
1622     arg2: Reg,
1623     arg3: Reg,
1624 ) -> Option<Reg> {
1625     let pattern0_0 = arg0;
1626     let pattern1_0 = arg1;
1627     let pattern2_0 = arg2;
1628     let pattern3_0 = arg3;
1629     // Rule at src/isa/aarch64/inst.isle line 1448.
1630     let expr0_0: Type = I64;
1631     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1632     let expr2_0 = MInst::AluRRRR {
1633         alu_op: pattern0_0.clone(),
1634         rd: expr1_0,
1635         rn: pattern1_0,
1636         rm: pattern2_0,
1637         ra: pattern3_0,
1638     };
1639     let expr3_0 = C::emit(ctx, &expr2_0);
1640     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1641     return Some(expr4_0);
1642 }
1643 
1644 // Generated as internal constructor for term bit_rr.
1645 pub fn constructor_bit_rr<C: Context>(
1646     ctx: &mut C,
1647     arg0: &BitOp,
1648     arg1: Type,
1649     arg2: Reg,
1650 ) -> Option<Reg> {
1651     let pattern0_0 = arg0;
1652     let pattern1_0 = arg1;
1653     let pattern2_0 = arg2;
1654     // Rule at src/isa/aarch64/inst.isle line 1455.
1655     let expr0_0: Type = I64;
1656     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1657     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1658     let expr3_0 = MInst::BitRR {
1659         op: pattern0_0.clone(),
1660         size: expr2_0,
1661         rd: expr1_0,
1662         rn: pattern2_0,
1663     };
1664     let expr4_0 = C::emit(ctx, &expr3_0);
1665     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1666     return Some(expr5_0);
1667 }
1668 
1669 // Generated as internal constructor for term add_with_flags_paired.
1670 pub fn constructor_add_with_flags_paired<C: Context>(
1671     ctx: &mut C,
1672     arg0: Type,
1673     arg1: Reg,
1674     arg2: Reg,
1675 ) -> Option<ProducesFlags> {
1676     let pattern0_0 = arg0;
1677     let pattern1_0 = arg1;
1678     let pattern2_0 = arg2;
1679     // Rule at src/isa/aarch64/inst.isle line 1462.
1680     let expr0_0: Type = I64;
1681     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1682     let expr2_0 = ALUOp::AddS;
1683     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1684     let expr4_0 = MInst::AluRRR {
1685         alu_op: expr2_0,
1686         size: expr3_0,
1687         rd: expr1_0,
1688         rn: pattern1_0,
1689         rm: pattern2_0,
1690     };
1691     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1692     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1693         inst: expr4_0,
1694         result: expr5_0,
1695     };
1696     return Some(expr6_0);
1697 }
1698 
1699 // Generated as internal constructor for term adc_paired.
1700 pub fn constructor_adc_paired<C: Context>(
1701     ctx: &mut C,
1702     arg0: Type,
1703     arg1: Reg,
1704     arg2: Reg,
1705 ) -> Option<ConsumesFlags> {
1706     let pattern0_0 = arg0;
1707     let pattern1_0 = arg1;
1708     let pattern2_0 = arg2;
1709     // Rule at src/isa/aarch64/inst.isle line 1470.
1710     let expr0_0: Type = I64;
1711     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1712     let expr2_0 = ALUOp::Adc;
1713     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1714     let expr4_0 = MInst::AluRRR {
1715         alu_op: expr2_0,
1716         size: expr3_0,
1717         rd: expr1_0,
1718         rn: pattern1_0,
1719         rm: pattern2_0,
1720     };
1721     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1722     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1723         inst: expr4_0,
1724         result: expr5_0,
1725     };
1726     return Some(expr6_0);
1727 }
1728 
1729 // Generated as internal constructor for term sub_with_flags_paired.
1730 pub fn constructor_sub_with_flags_paired<C: Context>(
1731     ctx: &mut C,
1732     arg0: Type,
1733     arg1: Reg,
1734     arg2: Reg,
1735 ) -> Option<ProducesFlags> {
1736     let pattern0_0 = arg0;
1737     let pattern1_0 = arg1;
1738     let pattern2_0 = arg2;
1739     // Rule at src/isa/aarch64/inst.isle line 1478.
1740     let expr0_0: Type = I64;
1741     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1742     let expr2_0 = ALUOp::SubS;
1743     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1744     let expr4_0 = MInst::AluRRR {
1745         alu_op: expr2_0,
1746         size: expr3_0,
1747         rd: expr1_0,
1748         rn: pattern1_0,
1749         rm: pattern2_0,
1750     };
1751     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1752     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1753         inst: expr4_0,
1754         result: expr5_0,
1755     };
1756     return Some(expr6_0);
1757 }
1758 
1759 // Generated as internal constructor for term cmp64_imm.
1760 pub fn constructor_cmp64_imm<C: Context>(
1761     ctx: &mut C,
1762     arg0: Reg,
1763     arg1: Imm12,
1764 ) -> Option<ProducesFlags> {
1765     let pattern0_0 = arg0;
1766     let pattern1_0 = arg1;
1767     // Rule at src/isa/aarch64/inst.isle line 1485.
1768     let expr0_0 = ALUOp::SubS;
1769     let expr1_0 = OperandSize::Size64;
1770     let expr2_0 = C::writable_zero_reg(ctx);
1771     let expr3_0 = MInst::AluRRImm12 {
1772         alu_op: expr0_0,
1773         size: expr1_0,
1774         rd: expr2_0,
1775         rn: pattern0_0,
1776         imm12: pattern1_0,
1777     };
1778     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
1779     return Some(expr4_0);
1780 }
1781 
1782 // Generated as internal constructor for term sbc_paired.
1783 pub fn constructor_sbc_paired<C: Context>(
1784     ctx: &mut C,
1785     arg0: Type,
1786     arg1: Reg,
1787     arg2: Reg,
1788 ) -> Option<ConsumesFlags> {
1789     let pattern0_0 = arg0;
1790     let pattern1_0 = arg1;
1791     let pattern2_0 = arg2;
1792     // Rule at src/isa/aarch64/inst.isle line 1492.
1793     let expr0_0: Type = I64;
1794     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1795     let expr2_0 = ALUOp::Sbc;
1796     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1797     let expr4_0 = MInst::AluRRR {
1798         alu_op: expr2_0,
1799         size: expr3_0,
1800         rd: expr1_0,
1801         rn: pattern1_0,
1802         rm: pattern2_0,
1803     };
1804     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1805     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1806         inst: expr4_0,
1807         result: expr5_0,
1808     };
1809     return Some(expr6_0);
1810 }
1811 
1812 // Generated as internal constructor for term vec_misc.
1813 pub fn constructor_vec_misc<C: Context>(
1814     ctx: &mut C,
1815     arg0: &VecMisc2,
1816     arg1: Reg,
1817     arg2: &VectorSize,
1818 ) -> Option<Reg> {
1819     let pattern0_0 = arg0;
1820     let pattern1_0 = arg1;
1821     let pattern2_0 = arg2;
1822     // Rule at src/isa/aarch64/inst.isle line 1500.
1823     let expr0_0: Type = I8X16;
1824     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1825     let expr2_0 = MInst::VecMisc {
1826         op: pattern0_0.clone(),
1827         rd: expr1_0,
1828         rn: pattern1_0,
1829         size: pattern2_0.clone(),
1830     };
1831     let expr3_0 = C::emit(ctx, &expr2_0);
1832     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1833     return Some(expr4_0);
1834 }
1835 
1836 // Generated as internal constructor for term vec_rrr_long.
1837 pub fn constructor_vec_rrr_long<C: Context>(
1838     ctx: &mut C,
1839     arg0: &VecRRRLongOp,
1840     arg1: Reg,
1841     arg2: Reg,
1842     arg3: bool,
1843 ) -> Option<Reg> {
1844     let pattern0_0 = arg0;
1845     let pattern1_0 = arg1;
1846     let pattern2_0 = arg2;
1847     let pattern3_0 = arg3;
1848     // Rule at src/isa/aarch64/inst.isle line 1507.
1849     let expr0_0: Type = I8X16;
1850     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1851     let expr2_0 = MInst::VecRRRLong {
1852         alu_op: pattern0_0.clone(),
1853         rd: expr1_0,
1854         rn: pattern1_0,
1855         rm: pattern2_0,
1856         high_half: pattern3_0,
1857     };
1858     let expr3_0 = C::emit(ctx, &expr2_0);
1859     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1860     return Some(expr4_0);
1861 }
1862 
1863 // Generated as internal constructor for term vec_rrrr_long.
1864 pub fn constructor_vec_rrrr_long<C: Context>(
1865     ctx: &mut C,
1866     arg0: &VecRRRLongOp,
1867     arg1: Reg,
1868     arg2: Reg,
1869     arg3: Reg,
1870     arg4: bool,
1871 ) -> Option<Reg> {
1872     let pattern0_0 = arg0;
1873     let pattern1_0 = arg1;
1874     let pattern2_0 = arg2;
1875     let pattern3_0 = arg3;
1876     let pattern4_0 = arg4;
1877     // Rule at src/isa/aarch64/inst.isle line 1517.
1878     let expr0_0: Type = I8X16;
1879     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1880     let expr2_0 = MInst::FpuMove128 {
1881         rd: expr1_0,
1882         rn: pattern1_0,
1883     };
1884     let expr3_0 = C::emit(ctx, &expr2_0);
1885     let expr4_0 = MInst::VecRRRLong {
1886         alu_op: pattern0_0.clone(),
1887         rd: expr1_0,
1888         rn: pattern2_0,
1889         rm: pattern3_0,
1890         high_half: pattern4_0,
1891     };
1892     let expr5_0 = C::emit(ctx, &expr4_0);
1893     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1894     return Some(expr6_0);
1895 }
1896 
1897 // Generated as internal constructor for term vec_rr_narrow.
1898 pub fn constructor_vec_rr_narrow<C: Context>(
1899     ctx: &mut C,
1900     arg0: &VecRRNarrowOp,
1901     arg1: Reg,
1902     arg2: bool,
1903 ) -> Option<Reg> {
1904     let pattern0_0 = arg0;
1905     let pattern1_0 = arg1;
1906     let pattern2_0 = arg2;
1907     // Rule at src/isa/aarch64/inst.isle line 1525.
1908     let expr0_0: Type = I8X16;
1909     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1910     let expr2_0 = MInst::VecRRNarrow {
1911         op: pattern0_0.clone(),
1912         rd: expr1_0,
1913         rn: pattern1_0,
1914         high_half: pattern2_0,
1915     };
1916     let expr3_0 = C::emit(ctx, &expr2_0);
1917     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1918     return Some(expr4_0);
1919 }
1920 
1921 // Generated as internal constructor for term vec_rr_long.
1922 pub fn constructor_vec_rr_long<C: Context>(
1923     ctx: &mut C,
1924     arg0: &VecRRLongOp,
1925     arg1: Reg,
1926     arg2: bool,
1927 ) -> Option<Reg> {
1928     let pattern0_0 = arg0;
1929     let pattern1_0 = arg1;
1930     let pattern2_0 = arg2;
1931     // Rule at src/isa/aarch64/inst.isle line 1532.
1932     let expr0_0: Type = I8X16;
1933     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1934     let expr2_0 = MInst::VecRRLong {
1935         op: pattern0_0.clone(),
1936         rd: expr1_0,
1937         rn: pattern1_0,
1938         high_half: pattern2_0,
1939     };
1940     let expr3_0 = C::emit(ctx, &expr2_0);
1941     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1942     return Some(expr4_0);
1943 }
1944 
1945 // Generated as internal constructor for term mov_to_fpu.
1946 pub fn constructor_mov_to_fpu<C: Context>(
1947     ctx: &mut C,
1948     arg0: Reg,
1949     arg1: &ScalarSize,
1950 ) -> Option<Reg> {
1951     let pattern0_0 = arg0;
1952     let pattern1_0 = arg1;
1953     // Rule at src/isa/aarch64/inst.isle line 1539.
1954     let expr0_0: Type = I8X16;
1955     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1956     let expr2_0 = MInst::MovToFpu {
1957         rd: expr1_0,
1958         rn: pattern0_0,
1959         size: pattern1_0.clone(),
1960     };
1961     let expr3_0 = C::emit(ctx, &expr2_0);
1962     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1963     return Some(expr4_0);
1964 }
1965 
1966 // Generated as internal constructor for term mov_to_vec.
1967 pub fn constructor_mov_to_vec<C: Context>(
1968     ctx: &mut C,
1969     arg0: Reg,
1970     arg1: Reg,
1971     arg2: u8,
1972     arg3: &VectorSize,
1973 ) -> Option<Reg> {
1974     let pattern0_0 = arg0;
1975     let pattern1_0 = arg1;
1976     let pattern2_0 = arg2;
1977     let pattern3_0 = arg3;
1978     // Rule at src/isa/aarch64/inst.isle line 1546.
1979     let expr0_0: Type = I8X16;
1980     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1981     let expr2_0 = MInst::FpuMove128 {
1982         rd: expr1_0,
1983         rn: pattern0_0,
1984     };
1985     let expr3_0 = C::emit(ctx, &expr2_0);
1986     let expr4_0 = MInst::MovToVec {
1987         rd: expr1_0,
1988         rn: pattern1_0,
1989         idx: pattern2_0,
1990         size: pattern3_0.clone(),
1991     };
1992     let expr5_0 = C::emit(ctx, &expr4_0);
1993     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1994     return Some(expr6_0);
1995 }
1996 
1997 // Generated as internal constructor for term mov_from_vec.
1998 pub fn constructor_mov_from_vec<C: Context>(
1999     ctx: &mut C,
2000     arg0: Reg,
2001     arg1: u8,
2002     arg2: &VectorSize,
2003 ) -> Option<Reg> {
2004     let pattern0_0 = arg0;
2005     let pattern1_0 = arg1;
2006     let pattern2_0 = arg2;
2007     // Rule at src/isa/aarch64/inst.isle line 1554.
2008     let expr0_0: Type = I64;
2009     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2010     let expr2_0 = MInst::MovFromVec {
2011         rd: expr1_0,
2012         rn: pattern0_0,
2013         idx: pattern1_0,
2014         size: pattern2_0.clone(),
2015     };
2016     let expr3_0 = C::emit(ctx, &expr2_0);
2017     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2018     return Some(expr4_0);
2019 }
2020 
2021 // Generated as internal constructor for term mov_from_vec_signed.
2022 pub fn constructor_mov_from_vec_signed<C: Context>(
2023     ctx: &mut C,
2024     arg0: Reg,
2025     arg1: u8,
2026     arg2: &VectorSize,
2027     arg3: &OperandSize,
2028 ) -> Option<Reg> {
2029     let pattern0_0 = arg0;
2030     let pattern1_0 = arg1;
2031     let pattern2_0 = arg2;
2032     let pattern3_0 = arg3;
2033     // Rule at src/isa/aarch64/inst.isle line 1561.
2034     let expr0_0: Type = I64;
2035     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2036     let expr2_0 = MInst::MovFromVecSigned {
2037         rd: expr1_0,
2038         rn: pattern0_0,
2039         idx: pattern1_0,
2040         size: pattern2_0.clone(),
2041         scalar_size: pattern3_0.clone(),
2042     };
2043     let expr3_0 = C::emit(ctx, &expr2_0);
2044     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2045     return Some(expr4_0);
2046 }
2047 
2048 // Generated as internal constructor for term extend.
2049 pub fn constructor_extend<C: Context>(
2050     ctx: &mut C,
2051     arg0: Reg,
2052     arg1: bool,
2053     arg2: u8,
2054     arg3: u8,
2055 ) -> Option<Reg> {
2056     let pattern0_0 = arg0;
2057     let pattern1_0 = arg1;
2058     let pattern2_0 = arg2;
2059     let pattern3_0 = arg3;
2060     // Rule at src/isa/aarch64/inst.isle line 1568.
2061     let expr0_0: Type = I64;
2062     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2063     let expr2_0 = MInst::Extend {
2064         rd: expr1_0,
2065         rn: pattern0_0,
2066         signed: pattern1_0,
2067         from_bits: pattern2_0,
2068         to_bits: pattern3_0,
2069     };
2070     let expr3_0 = C::emit(ctx, &expr2_0);
2071     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2072     return Some(expr4_0);
2073 }
2074 
2075 // Generated as internal constructor for term load_acquire.
2076 pub fn constructor_load_acquire<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2077     let pattern0_0 = arg0;
2078     let pattern1_0 = arg1;
2079     // Rule at src/isa/aarch64/inst.isle line 1575.
2080     let expr0_0: Type = I64;
2081     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2082     let expr2_0 = MInst::LoadAcquire {
2083         access_ty: pattern0_0,
2084         rt: expr1_0,
2085         rn: pattern1_0,
2086     };
2087     let expr3_0 = C::emit(ctx, &expr2_0);
2088     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2089     return Some(expr4_0);
2090 }
2091 
2092 // Generated as internal constructor for term tst_imm.
2093 pub fn constructor_tst_imm<C: Context>(
2094     ctx: &mut C,
2095     arg0: Type,
2096     arg1: Reg,
2097     arg2: ImmLogic,
2098 ) -> Option<ProducesFlags> {
2099     let pattern0_0 = arg0;
2100     let pattern1_0 = arg1;
2101     let pattern2_0 = arg2;
2102     // Rule at src/isa/aarch64/inst.isle line 1585.
2103     let expr0_0 = ALUOp::AndS;
2104     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
2105     let expr2_0 = C::writable_zero_reg(ctx);
2106     let expr3_0 = MInst::AluRRImmLogic {
2107         alu_op: expr0_0,
2108         size: expr1_0,
2109         rd: expr2_0,
2110         rn: pattern1_0,
2111         imml: pattern2_0,
2112     };
2113     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
2114     return Some(expr4_0);
2115 }
2116 
2117 // Generated as internal constructor for term csel.
2118 pub fn constructor_csel<C: Context>(
2119     ctx: &mut C,
2120     arg0: &Cond,
2121     arg1: Reg,
2122     arg2: Reg,
2123 ) -> Option<ConsumesFlags> {
2124     let pattern0_0 = arg0;
2125     let pattern1_0 = arg1;
2126     let pattern2_0 = arg2;
2127     // Rule at src/isa/aarch64/inst.isle line 1599.
2128     let expr0_0: Type = I64;
2129     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2130     let expr2_0 = MInst::CSel {
2131         rd: expr1_0,
2132         cond: pattern0_0.clone(),
2133         rn: pattern1_0,
2134         rm: pattern2_0,
2135     };
2136     let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
2137     let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
2138         inst: expr2_0,
2139         result: expr3_0,
2140     };
2141     return Some(expr4_0);
2142 }
2143 
2144 // Generated as internal constructor for term add.
2145 pub fn constructor_add<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2146     let pattern0_0 = arg0;
2147     let pattern1_0 = arg1;
2148     let pattern2_0 = arg2;
2149     // Rule at src/isa/aarch64/inst.isle line 1608.
2150     let expr0_0 = ALUOp::Add;
2151     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2152     return Some(expr1_0);
2153 }
2154 
2155 // Generated as internal constructor for term add_imm.
2156 pub fn constructor_add_imm<C: Context>(
2157     ctx: &mut C,
2158     arg0: Type,
2159     arg1: Reg,
2160     arg2: Imm12,
2161 ) -> Option<Reg> {
2162     let pattern0_0 = arg0;
2163     let pattern1_0 = arg1;
2164     let pattern2_0 = arg2;
2165     // Rule at src/isa/aarch64/inst.isle line 1611.
2166     let expr0_0 = ALUOp::Add;
2167     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2168     return Some(expr1_0);
2169 }
2170 
2171 // Generated as internal constructor for term add_extend.
2172 pub fn constructor_add_extend<C: Context>(
2173     ctx: &mut C,
2174     arg0: Type,
2175     arg1: Reg,
2176     arg2: &ExtendedValue,
2177 ) -> Option<Reg> {
2178     let pattern0_0 = arg0;
2179     let pattern1_0 = arg1;
2180     let pattern2_0 = arg2;
2181     // Rule at src/isa/aarch64/inst.isle line 1614.
2182     let expr0_0 = ALUOp::Add;
2183     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2184     return Some(expr1_0);
2185 }
2186 
2187 // Generated as internal constructor for term add_shift.
2188 pub fn constructor_add_shift<C: Context>(
2189     ctx: &mut C,
2190     arg0: Type,
2191     arg1: Reg,
2192     arg2: Reg,
2193     arg3: ShiftOpAndAmt,
2194 ) -> Option<Reg> {
2195     let pattern0_0 = arg0;
2196     let pattern1_0 = arg1;
2197     let pattern2_0 = arg2;
2198     let pattern3_0 = arg3;
2199     // Rule at src/isa/aarch64/inst.isle line 1617.
2200     let expr0_0 = ALUOp::Add;
2201     let expr1_0 = constructor_alu_rrr_shift(
2202         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2203     )?;
2204     return Some(expr1_0);
2205 }
2206 
2207 // Generated as internal constructor for term add_vec.
2208 pub fn constructor_add_vec<C: Context>(
2209     ctx: &mut C,
2210     arg0: Reg,
2211     arg1: Reg,
2212     arg2: &VectorSize,
2213 ) -> Option<Reg> {
2214     let pattern0_0 = arg0;
2215     let pattern1_0 = arg1;
2216     let pattern2_0 = arg2;
2217     // Rule at src/isa/aarch64/inst.isle line 1620.
2218     let expr0_0 = VecALUOp::Add;
2219     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2220     return Some(expr1_0);
2221 }
2222 
2223 // Generated as internal constructor for term sub.
2224 pub fn constructor_sub<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2225     let pattern0_0 = arg0;
2226     let pattern1_0 = arg1;
2227     let pattern2_0 = arg2;
2228     // Rule at src/isa/aarch64/inst.isle line 1625.
2229     let expr0_0 = ALUOp::Sub;
2230     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2231     return Some(expr1_0);
2232 }
2233 
2234 // Generated as internal constructor for term sub_imm.
2235 pub fn constructor_sub_imm<C: Context>(
2236     ctx: &mut C,
2237     arg0: Type,
2238     arg1: Reg,
2239     arg2: Imm12,
2240 ) -> Option<Reg> {
2241     let pattern0_0 = arg0;
2242     let pattern1_0 = arg1;
2243     let pattern2_0 = arg2;
2244     // Rule at src/isa/aarch64/inst.isle line 1628.
2245     let expr0_0 = ALUOp::Sub;
2246     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2247     return Some(expr1_0);
2248 }
2249 
2250 // Generated as internal constructor for term sub_extend.
2251 pub fn constructor_sub_extend<C: Context>(
2252     ctx: &mut C,
2253     arg0: Type,
2254     arg1: Reg,
2255     arg2: &ExtendedValue,
2256 ) -> Option<Reg> {
2257     let pattern0_0 = arg0;
2258     let pattern1_0 = arg1;
2259     let pattern2_0 = arg2;
2260     // Rule at src/isa/aarch64/inst.isle line 1631.
2261     let expr0_0 = ALUOp::Sub;
2262     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2263     return Some(expr1_0);
2264 }
2265 
2266 // Generated as internal constructor for term sub_shift.
2267 pub fn constructor_sub_shift<C: Context>(
2268     ctx: &mut C,
2269     arg0: Type,
2270     arg1: Reg,
2271     arg2: Reg,
2272     arg3: ShiftOpAndAmt,
2273 ) -> Option<Reg> {
2274     let pattern0_0 = arg0;
2275     let pattern1_0 = arg1;
2276     let pattern2_0 = arg2;
2277     let pattern3_0 = arg3;
2278     // Rule at src/isa/aarch64/inst.isle line 1634.
2279     let expr0_0 = ALUOp::Sub;
2280     let expr1_0 = constructor_alu_rrr_shift(
2281         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2282     )?;
2283     return Some(expr1_0);
2284 }
2285 
2286 // Generated as internal constructor for term sub_vec.
2287 pub fn constructor_sub_vec<C: Context>(
2288     ctx: &mut C,
2289     arg0: Reg,
2290     arg1: Reg,
2291     arg2: &VectorSize,
2292 ) -> Option<Reg> {
2293     let pattern0_0 = arg0;
2294     let pattern1_0 = arg1;
2295     let pattern2_0 = arg2;
2296     // Rule at src/isa/aarch64/inst.isle line 1637.
2297     let expr0_0 = VecALUOp::Sub;
2298     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2299     return Some(expr1_0);
2300 }
2301 
2302 // Generated as internal constructor for term madd.
2303 pub fn constructor_madd<C: Context>(
2304     ctx: &mut C,
2305     arg0: Type,
2306     arg1: Reg,
2307     arg2: Reg,
2308     arg3: Reg,
2309 ) -> Option<Reg> {
2310     let pattern0_0 = arg0;
2311     if pattern0_0 == I64 {
2312         let pattern2_0 = arg1;
2313         let pattern3_0 = arg2;
2314         let pattern4_0 = arg3;
2315         // Rule at src/isa/aarch64/inst.isle line 1643.
2316         let expr0_0 = constructor_madd64(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2317         return Some(expr0_0);
2318     }
2319     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2320         let pattern2_0 = arg1;
2321         let pattern3_0 = arg2;
2322         let pattern4_0 = arg3;
2323         // Rule at src/isa/aarch64/inst.isle line 1642.
2324         let expr0_0 = constructor_madd32(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2325         return Some(expr0_0);
2326     }
2327     return None;
2328 }
2329 
2330 // Generated as internal constructor for term madd32.
2331 pub fn constructor_madd32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2332     let pattern0_0 = arg0;
2333     let pattern1_0 = arg1;
2334     let pattern2_0 = arg2;
2335     // Rule at src/isa/aarch64/inst.isle line 1646.
2336     let expr0_0 = ALUOp3::MAdd32;
2337     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2338     return Some(expr1_0);
2339 }
2340 
2341 // Generated as internal constructor for term madd64.
2342 pub fn constructor_madd64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2343     let pattern0_0 = arg0;
2344     let pattern1_0 = arg1;
2345     let pattern2_0 = arg2;
2346     // Rule at src/isa/aarch64/inst.isle line 1649.
2347     let expr0_0 = ALUOp3::MAdd64;
2348     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2349     return Some(expr1_0);
2350 }
2351 
2352 // Generated as internal constructor for term msub64.
2353 pub fn constructor_msub64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2354     let pattern0_0 = arg0;
2355     let pattern1_0 = arg1;
2356     let pattern2_0 = arg2;
2357     // Rule at src/isa/aarch64/inst.isle line 1654.
2358     let expr0_0 = ALUOp3::MSub64;
2359     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2360     return Some(expr1_0);
2361 }
2362 
2363 // Generated as internal constructor for term uqadd.
2364 pub fn constructor_uqadd<C: Context>(
2365     ctx: &mut C,
2366     arg0: Reg,
2367     arg1: Reg,
2368     arg2: &VectorSize,
2369 ) -> Option<Reg> {
2370     let pattern0_0 = arg0;
2371     let pattern1_0 = arg1;
2372     let pattern2_0 = arg2;
2373     // Rule at src/isa/aarch64/inst.isle line 1658.
2374     let expr0_0 = VecALUOp::Uqadd;
2375     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2376     return Some(expr1_0);
2377 }
2378 
2379 // Generated as internal constructor for term sqadd.
2380 pub fn constructor_sqadd<C: Context>(
2381     ctx: &mut C,
2382     arg0: Reg,
2383     arg1: Reg,
2384     arg2: &VectorSize,
2385 ) -> Option<Reg> {
2386     let pattern0_0 = arg0;
2387     let pattern1_0 = arg1;
2388     let pattern2_0 = arg2;
2389     // Rule at src/isa/aarch64/inst.isle line 1662.
2390     let expr0_0 = VecALUOp::Sqadd;
2391     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2392     return Some(expr1_0);
2393 }
2394 
2395 // Generated as internal constructor for term uqsub.
2396 pub fn constructor_uqsub<C: Context>(
2397     ctx: &mut C,
2398     arg0: Reg,
2399     arg1: Reg,
2400     arg2: &VectorSize,
2401 ) -> Option<Reg> {
2402     let pattern0_0 = arg0;
2403     let pattern1_0 = arg1;
2404     let pattern2_0 = arg2;
2405     // Rule at src/isa/aarch64/inst.isle line 1666.
2406     let expr0_0 = VecALUOp::Uqsub;
2407     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2408     return Some(expr1_0);
2409 }
2410 
2411 // Generated as internal constructor for term sqsub.
2412 pub fn constructor_sqsub<C: Context>(
2413     ctx: &mut C,
2414     arg0: Reg,
2415     arg1: Reg,
2416     arg2: &VectorSize,
2417 ) -> Option<Reg> {
2418     let pattern0_0 = arg0;
2419     let pattern1_0 = arg1;
2420     let pattern2_0 = arg2;
2421     // Rule at src/isa/aarch64/inst.isle line 1670.
2422     let expr0_0 = VecALUOp::Sqsub;
2423     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2424     return Some(expr1_0);
2425 }
2426 
2427 // Generated as internal constructor for term umulh.
2428 pub fn constructor_umulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2429     let pattern0_0 = arg0;
2430     let pattern1_0 = arg1;
2431     let pattern2_0 = arg2;
2432     // Rule at src/isa/aarch64/inst.isle line 1674.
2433     let expr0_0 = ALUOp::UMulH;
2434     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2435     return Some(expr1_0);
2436 }
2437 
2438 // Generated as internal constructor for term smulh.
2439 pub fn constructor_smulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2440     let pattern0_0 = arg0;
2441     let pattern1_0 = arg1;
2442     let pattern2_0 = arg2;
2443     // Rule at src/isa/aarch64/inst.isle line 1678.
2444     let expr0_0 = ALUOp::SMulH;
2445     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2446     return Some(expr1_0);
2447 }
2448 
2449 // Generated as internal constructor for term mul.
2450 pub fn constructor_mul<C: Context>(
2451     ctx: &mut C,
2452     arg0: Reg,
2453     arg1: Reg,
2454     arg2: &VectorSize,
2455 ) -> Option<Reg> {
2456     let pattern0_0 = arg0;
2457     let pattern1_0 = arg1;
2458     let pattern2_0 = arg2;
2459     // Rule at src/isa/aarch64/inst.isle line 1682.
2460     let expr0_0 = VecALUOp::Mul;
2461     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2462     return Some(expr1_0);
2463 }
2464 
2465 // Generated as internal constructor for term neg.
2466 pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2467     let pattern0_0 = arg0;
2468     let pattern1_0 = arg1;
2469     // Rule at src/isa/aarch64/inst.isle line 1686.
2470     let expr0_0 = VecMisc2::Neg;
2471     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2472     return Some(expr1_0);
2473 }
2474 
2475 // Generated as internal constructor for term rev64.
2476 pub fn constructor_rev64<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2477     let pattern0_0 = arg0;
2478     let pattern1_0 = arg1;
2479     // Rule at src/isa/aarch64/inst.isle line 1690.
2480     let expr0_0 = VecMisc2::Rev64;
2481     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2482     return Some(expr1_0);
2483 }
2484 
2485 // Generated as internal constructor for term xtn64.
2486 pub fn constructor_xtn64<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2487     let pattern0_0 = arg0;
2488     let pattern1_0 = arg1;
2489     // Rule at src/isa/aarch64/inst.isle line 1694.
2490     let expr0_0 = VecRRNarrowOp::Xtn64;
2491     let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2492     return Some(expr1_0);
2493 }
2494 
2495 // Generated as internal constructor for term addp.
2496 pub fn constructor_addp<C: Context>(
2497     ctx: &mut C,
2498     arg0: Reg,
2499     arg1: Reg,
2500     arg2: &VectorSize,
2501 ) -> Option<Reg> {
2502     let pattern0_0 = arg0;
2503     let pattern1_0 = arg1;
2504     let pattern2_0 = arg2;
2505     // Rule at src/isa/aarch64/inst.isle line 1698.
2506     let expr0_0 = VecALUOp::Addp;
2507     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2508     return Some(expr1_0);
2509 }
2510 
2511 // Generated as internal constructor for term addv.
2512 pub fn constructor_addv<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2513     let pattern0_0 = arg0;
2514     let pattern1_0 = arg1;
2515     // Rule at src/isa/aarch64/inst.isle line 1702.
2516     let expr0_0 = VecLanesOp::Addv;
2517     let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2518     return Some(expr1_0);
2519 }
2520 
2521 // Generated as internal constructor for term shll32.
2522 pub fn constructor_shll32<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2523     let pattern0_0 = arg0;
2524     let pattern1_0 = arg1;
2525     // Rule at src/isa/aarch64/inst.isle line 1706.
2526     let expr0_0 = VecRRLongOp::Shll32;
2527     let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2528     return Some(expr1_0);
2529 }
2530 
2531 // Generated as internal constructor for term umlal32.
2532 pub fn constructor_umlal32<C: Context>(
2533     ctx: &mut C,
2534     arg0: Reg,
2535     arg1: Reg,
2536     arg2: Reg,
2537     arg3: bool,
2538 ) -> Option<Reg> {
2539     let pattern0_0 = arg0;
2540     let pattern1_0 = arg1;
2541     let pattern2_0 = arg2;
2542     let pattern3_0 = arg3;
2543     // Rule at src/isa/aarch64/inst.isle line 1710.
2544     let expr0_0 = VecRRRLongOp::Umlal32;
2545     let expr1_0 = constructor_vec_rrrr_long(
2546         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2547     )?;
2548     return Some(expr1_0);
2549 }
2550 
2551 // Generated as internal constructor for term smull8.
2552 pub fn constructor_smull8<C: Context>(
2553     ctx: &mut C,
2554     arg0: Reg,
2555     arg1: Reg,
2556     arg2: bool,
2557 ) -> Option<Reg> {
2558     let pattern0_0 = arg0;
2559     let pattern1_0 = arg1;
2560     let pattern2_0 = arg2;
2561     // Rule at src/isa/aarch64/inst.isle line 1714.
2562     let expr0_0 = VecRRRLongOp::Smull8;
2563     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2564     return Some(expr1_0);
2565 }
2566 
2567 // Generated as internal constructor for term umull8.
2568 pub fn constructor_umull8<C: Context>(
2569     ctx: &mut C,
2570     arg0: Reg,
2571     arg1: Reg,
2572     arg2: bool,
2573 ) -> Option<Reg> {
2574     let pattern0_0 = arg0;
2575     let pattern1_0 = arg1;
2576     let pattern2_0 = arg2;
2577     // Rule at src/isa/aarch64/inst.isle line 1718.
2578     let expr0_0 = VecRRRLongOp::Umull8;
2579     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2580     return Some(expr1_0);
2581 }
2582 
2583 // Generated as internal constructor for term smull16.
2584 pub fn constructor_smull16<C: Context>(
2585     ctx: &mut C,
2586     arg0: Reg,
2587     arg1: Reg,
2588     arg2: bool,
2589 ) -> Option<Reg> {
2590     let pattern0_0 = arg0;
2591     let pattern1_0 = arg1;
2592     let pattern2_0 = arg2;
2593     // Rule at src/isa/aarch64/inst.isle line 1722.
2594     let expr0_0 = VecRRRLongOp::Smull16;
2595     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2596     return Some(expr1_0);
2597 }
2598 
2599 // Generated as internal constructor for term umull16.
2600 pub fn constructor_umull16<C: Context>(
2601     ctx: &mut C,
2602     arg0: Reg,
2603     arg1: Reg,
2604     arg2: bool,
2605 ) -> Option<Reg> {
2606     let pattern0_0 = arg0;
2607     let pattern1_0 = arg1;
2608     let pattern2_0 = arg2;
2609     // Rule at src/isa/aarch64/inst.isle line 1726.
2610     let expr0_0 = VecRRRLongOp::Umull16;
2611     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2612     return Some(expr1_0);
2613 }
2614 
2615 // Generated as internal constructor for term smull32.
2616 pub fn constructor_smull32<C: Context>(
2617     ctx: &mut C,
2618     arg0: Reg,
2619     arg1: Reg,
2620     arg2: bool,
2621 ) -> Option<Reg> {
2622     let pattern0_0 = arg0;
2623     let pattern1_0 = arg1;
2624     let pattern2_0 = arg2;
2625     // Rule at src/isa/aarch64/inst.isle line 1730.
2626     let expr0_0 = VecRRRLongOp::Smull32;
2627     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2628     return Some(expr1_0);
2629 }
2630 
2631 // Generated as internal constructor for term umull32.
2632 pub fn constructor_umull32<C: Context>(
2633     ctx: &mut C,
2634     arg0: Reg,
2635     arg1: Reg,
2636     arg2: bool,
2637 ) -> Option<Reg> {
2638     let pattern0_0 = arg0;
2639     let pattern1_0 = arg1;
2640     let pattern2_0 = arg2;
2641     // Rule at src/isa/aarch64/inst.isle line 1734.
2642     let expr0_0 = VecRRRLongOp::Umull32;
2643     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2644     return Some(expr1_0);
2645 }
2646 
2647 // Generated as internal constructor for term asr.
2648 pub fn constructor_asr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2649     let pattern0_0 = arg0;
2650     let pattern1_0 = arg1;
2651     let pattern2_0 = arg2;
2652     // Rule at src/isa/aarch64/inst.isle line 1738.
2653     let expr0_0 = ALUOp::Asr;
2654     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2655     return Some(expr1_0);
2656 }
2657 
2658 // Generated as internal constructor for term asr_imm.
2659 pub fn constructor_asr_imm<C: Context>(
2660     ctx: &mut C,
2661     arg0: Type,
2662     arg1: Reg,
2663     arg2: ImmShift,
2664 ) -> Option<Reg> {
2665     let pattern0_0 = arg0;
2666     let pattern1_0 = arg1;
2667     let pattern2_0 = arg2;
2668     // Rule at src/isa/aarch64/inst.isle line 1741.
2669     let expr0_0 = ALUOp::Asr;
2670     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2671     return Some(expr1_0);
2672 }
2673 
2674 // Generated as internal constructor for term lsr.
2675 pub fn constructor_lsr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2676     let pattern0_0 = arg0;
2677     let pattern1_0 = arg1;
2678     let pattern2_0 = arg2;
2679     // Rule at src/isa/aarch64/inst.isle line 1745.
2680     let expr0_0 = ALUOp::Lsr;
2681     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2682     return Some(expr1_0);
2683 }
2684 
2685 // Generated as internal constructor for term lsr_imm.
2686 pub fn constructor_lsr_imm<C: Context>(
2687     ctx: &mut C,
2688     arg0: Type,
2689     arg1: Reg,
2690     arg2: ImmShift,
2691 ) -> Option<Reg> {
2692     let pattern0_0 = arg0;
2693     let pattern1_0 = arg1;
2694     let pattern2_0 = arg2;
2695     // Rule at src/isa/aarch64/inst.isle line 1748.
2696     let expr0_0 = ALUOp::Lsr;
2697     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2698     return Some(expr1_0);
2699 }
2700 
2701 // Generated as internal constructor for term lsl.
2702 pub fn constructor_lsl<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2703     let pattern0_0 = arg0;
2704     let pattern1_0 = arg1;
2705     let pattern2_0 = arg2;
2706     // Rule at src/isa/aarch64/inst.isle line 1752.
2707     let expr0_0 = ALUOp::Lsl;
2708     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2709     return Some(expr1_0);
2710 }
2711 
2712 // Generated as internal constructor for term lsl_imm.
2713 pub fn constructor_lsl_imm<C: Context>(
2714     ctx: &mut C,
2715     arg0: Type,
2716     arg1: Reg,
2717     arg2: ImmShift,
2718 ) -> Option<Reg> {
2719     let pattern0_0 = arg0;
2720     let pattern1_0 = arg1;
2721     let pattern2_0 = arg2;
2722     // Rule at src/isa/aarch64/inst.isle line 1755.
2723     let expr0_0 = ALUOp::Lsl;
2724     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2725     return Some(expr1_0);
2726 }
2727 
2728 // Generated as internal constructor for term a64_udiv.
2729 pub fn constructor_a64_udiv<C: Context>(
2730     ctx: &mut C,
2731     arg0: Type,
2732     arg1: Reg,
2733     arg2: Reg,
2734 ) -> Option<Reg> {
2735     let pattern0_0 = arg0;
2736     let pattern1_0 = arg1;
2737     let pattern2_0 = arg2;
2738     // Rule at src/isa/aarch64/inst.isle line 1759.
2739     let expr0_0 = ALUOp::UDiv;
2740     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2741     return Some(expr1_0);
2742 }
2743 
2744 // Generated as internal constructor for term a64_sdiv.
2745 pub fn constructor_a64_sdiv<C: Context>(
2746     ctx: &mut C,
2747     arg0: Type,
2748     arg1: Reg,
2749     arg2: Reg,
2750 ) -> Option<Reg> {
2751     let pattern0_0 = arg0;
2752     let pattern1_0 = arg1;
2753     let pattern2_0 = arg2;
2754     // Rule at src/isa/aarch64/inst.isle line 1763.
2755     let expr0_0 = ALUOp::SDiv;
2756     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2757     return Some(expr1_0);
2758 }
2759 
2760 // Generated as internal constructor for term not.
2761 pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2762     let pattern0_0 = arg0;
2763     let pattern1_0 = arg1;
2764     // Rule at src/isa/aarch64/inst.isle line 1767.
2765     let expr0_0 = VecMisc2::Not;
2766     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2767     return Some(expr1_0);
2768 }
2769 
2770 // Generated as internal constructor for term orr_not.
2771 pub fn constructor_orr_not<C: Context>(
2772     ctx: &mut C,
2773     arg0: Type,
2774     arg1: Reg,
2775     arg2: Reg,
2776 ) -> Option<Reg> {
2777     let pattern0_0 = arg0;
2778     let pattern1_0 = arg1;
2779     let pattern2_0 = arg2;
2780     // Rule at src/isa/aarch64/inst.isle line 1772.
2781     let expr0_0 = ALUOp::OrrNot;
2782     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2783     return Some(expr1_0);
2784 }
2785 
2786 // Generated as internal constructor for term orr_not_shift.
2787 pub fn constructor_orr_not_shift<C: Context>(
2788     ctx: &mut C,
2789     arg0: Type,
2790     arg1: Reg,
2791     arg2: Reg,
2792     arg3: ShiftOpAndAmt,
2793 ) -> Option<Reg> {
2794     let pattern0_0 = arg0;
2795     let pattern1_0 = arg1;
2796     let pattern2_0 = arg2;
2797     let pattern3_0 = arg3;
2798     // Rule at src/isa/aarch64/inst.isle line 1775.
2799     let expr0_0 = ALUOp::OrrNot;
2800     let expr1_0 = constructor_alu_rrr_shift(
2801         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2802     )?;
2803     return Some(expr1_0);
2804 }
2805 
2806 // Generated as internal constructor for term orr.
2807 pub fn constructor_orr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2808     let pattern0_0 = arg0;
2809     let pattern1_0 = arg1;
2810     let pattern2_0 = arg2;
2811     // Rule at src/isa/aarch64/inst.isle line 1780.
2812     let expr0_0 = ALUOp::Orr;
2813     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2814     return Some(expr1_0);
2815 }
2816 
2817 // Generated as internal constructor for term orr_imm.
2818 pub fn constructor_orr_imm<C: Context>(
2819     ctx: &mut C,
2820     arg0: Type,
2821     arg1: Reg,
2822     arg2: ImmLogic,
2823 ) -> Option<Reg> {
2824     let pattern0_0 = arg0;
2825     let pattern1_0 = arg1;
2826     let pattern2_0 = arg2;
2827     // Rule at src/isa/aarch64/inst.isle line 1783.
2828     let expr0_0 = ALUOp::Orr;
2829     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2830     return Some(expr1_0);
2831 }
2832 
2833 // Generated as internal constructor for term orr_vec.
2834 pub fn constructor_orr_vec<C: Context>(
2835     ctx: &mut C,
2836     arg0: Reg,
2837     arg1: Reg,
2838     arg2: &VectorSize,
2839 ) -> Option<Reg> {
2840     let pattern0_0 = arg0;
2841     let pattern1_0 = arg1;
2842     let pattern2_0 = arg2;
2843     // Rule at src/isa/aarch64/inst.isle line 1786.
2844     let expr0_0 = VecALUOp::Orr;
2845     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2846     return Some(expr1_0);
2847 }
2848 
2849 // Generated as internal constructor for term and_imm.
2850 pub fn constructor_and_imm<C: Context>(
2851     ctx: &mut C,
2852     arg0: Type,
2853     arg1: Reg,
2854     arg2: ImmLogic,
2855 ) -> Option<Reg> {
2856     let pattern0_0 = arg0;
2857     let pattern1_0 = arg1;
2858     let pattern2_0 = arg2;
2859     // Rule at src/isa/aarch64/inst.isle line 1791.
2860     let expr0_0 = ALUOp::And;
2861     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2862     return Some(expr1_0);
2863 }
2864 
2865 // Generated as internal constructor for term and_vec.
2866 pub fn constructor_and_vec<C: Context>(
2867     ctx: &mut C,
2868     arg0: Reg,
2869     arg1: Reg,
2870     arg2: &VectorSize,
2871 ) -> Option<Reg> {
2872     let pattern0_0 = arg0;
2873     let pattern1_0 = arg1;
2874     let pattern2_0 = arg2;
2875     // Rule at src/isa/aarch64/inst.isle line 1794.
2876     let expr0_0 = VecALUOp::And;
2877     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2878     return Some(expr1_0);
2879 }
2880 
2881 // Generated as internal constructor for term eor_vec.
2882 pub fn constructor_eor_vec<C: Context>(
2883     ctx: &mut C,
2884     arg0: Reg,
2885     arg1: Reg,
2886     arg2: &VectorSize,
2887 ) -> Option<Reg> {
2888     let pattern0_0 = arg0;
2889     let pattern1_0 = arg1;
2890     let pattern2_0 = arg2;
2891     // Rule at src/isa/aarch64/inst.isle line 1798.
2892     let expr0_0 = VecALUOp::Eor;
2893     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2894     return Some(expr1_0);
2895 }
2896 
2897 // Generated as internal constructor for term bic_vec.
2898 pub fn constructor_bic_vec<C: Context>(
2899     ctx: &mut C,
2900     arg0: Reg,
2901     arg1: Reg,
2902     arg2: &VectorSize,
2903 ) -> Option<Reg> {
2904     let pattern0_0 = arg0;
2905     let pattern1_0 = arg1;
2906     let pattern2_0 = arg2;
2907     // Rule at src/isa/aarch64/inst.isle line 1802.
2908     let expr0_0 = VecALUOp::Bic;
2909     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2910     return Some(expr1_0);
2911 }
2912 
2913 // Generated as internal constructor for term sshl.
2914 pub fn constructor_sshl<C: Context>(
2915     ctx: &mut C,
2916     arg0: Reg,
2917     arg1: Reg,
2918     arg2: &VectorSize,
2919 ) -> Option<Reg> {
2920     let pattern0_0 = arg0;
2921     let pattern1_0 = arg1;
2922     let pattern2_0 = arg2;
2923     // Rule at src/isa/aarch64/inst.isle line 1806.
2924     let expr0_0 = VecALUOp::Sshl;
2925     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2926     return Some(expr1_0);
2927 }
2928 
2929 // Generated as internal constructor for term ushl.
2930 pub fn constructor_ushl<C: Context>(
2931     ctx: &mut C,
2932     arg0: Reg,
2933     arg1: Reg,
2934     arg2: &VectorSize,
2935 ) -> Option<Reg> {
2936     let pattern0_0 = arg0;
2937     let pattern1_0 = arg1;
2938     let pattern2_0 = arg2;
2939     // Rule at src/isa/aarch64/inst.isle line 1810.
2940     let expr0_0 = VecALUOp::Ushl;
2941     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2942     return Some(expr1_0);
2943 }
2944 
2945 // Generated as internal constructor for term a64_rotr.
2946 pub fn constructor_a64_rotr<C: Context>(
2947     ctx: &mut C,
2948     arg0: Type,
2949     arg1: Reg,
2950     arg2: Reg,
2951 ) -> Option<Reg> {
2952     let pattern0_0 = arg0;
2953     let pattern1_0 = arg1;
2954     let pattern2_0 = arg2;
2955     // Rule at src/isa/aarch64/inst.isle line 1815.
2956     let expr0_0 = ALUOp::RotR;
2957     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2958     return Some(expr1_0);
2959 }
2960 
2961 // Generated as internal constructor for term a64_rotr_imm.
2962 pub fn constructor_a64_rotr_imm<C: Context>(
2963     ctx: &mut C,
2964     arg0: Type,
2965     arg1: Reg,
2966     arg2: ImmShift,
2967 ) -> Option<Reg> {
2968     let pattern0_0 = arg0;
2969     let pattern1_0 = arg1;
2970     let pattern2_0 = arg2;
2971     // Rule at src/isa/aarch64/inst.isle line 1818.
2972     let expr0_0 = ALUOp::RotR;
2973     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2974     return Some(expr1_0);
2975 }
2976 
2977 // Generated as internal constructor for term rbit.
2978 pub fn constructor_rbit<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2979     let pattern0_0 = arg0;
2980     let pattern1_0 = arg1;
2981     // Rule at src/isa/aarch64/inst.isle line 1823.
2982     let expr0_0 = BitOp::RBit;
2983     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2984     return Some(expr1_0);
2985 }
2986 
2987 // Generated as internal constructor for term a64_clz.
2988 pub fn constructor_a64_clz<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2989     let pattern0_0 = arg0;
2990     let pattern1_0 = arg1;
2991     // Rule at src/isa/aarch64/inst.isle line 1828.
2992     let expr0_0 = BitOp::Clz;
2993     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2994     return Some(expr1_0);
2995 }
2996 
2997 // Generated as internal constructor for term a64_cls.
2998 pub fn constructor_a64_cls<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2999     let pattern0_0 = arg0;
3000     let pattern1_0 = arg1;
3001     // Rule at src/isa/aarch64/inst.isle line 1833.
3002     let expr0_0 = BitOp::Cls;
3003     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3004     return Some(expr1_0);
3005 }
3006 
3007 // Generated as internal constructor for term eon.
3008 pub fn constructor_eon<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
3009     let pattern0_0 = arg0;
3010     let pattern1_0 = arg1;
3011     let pattern2_0 = arg2;
3012     // Rule at src/isa/aarch64/inst.isle line 1838.
3013     let expr0_0 = ALUOp::EorNot;
3014     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3015     return Some(expr1_0);
3016 }
3017 
3018 // Generated as internal constructor for term vec_cnt.
3019 pub fn constructor_vec_cnt<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3020     let pattern0_0 = arg0;
3021     let pattern1_0 = arg1;
3022     // Rule at src/isa/aarch64/inst.isle line 1843.
3023     let expr0_0 = VecMisc2::Cnt;
3024     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3025     return Some(expr1_0);
3026 }
3027 
3028 // Generated as internal constructor for term imm.
3029 pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
3030     let pattern0_0 = arg0;
3031     if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) {
3032         let pattern2_0 = arg1;
3033         let closure3 = || {
3034             let expr0_0: Type = I64;
3035             return Some(expr0_0);
3036         };
3037         if let Some(pattern3_0) = closure3() {
3038             if let Some(pattern4_0) = C::imm_logic_from_u64(ctx, pattern2_0, pattern3_0) {
3039                 // Rule at src/isa/aarch64/inst.isle line 1858.
3040                 let expr0_0: Type = I64;
3041                 let expr1_0 = C::zero_reg(ctx);
3042                 let expr2_0 = constructor_orr_imm(ctx, expr0_0, expr1_0, pattern4_0)?;
3043                 return Some(expr2_0);
3044             }
3045         }
3046         if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) {
3047             // Rule at src/isa/aarch64/inst.isle line 1850.
3048             let expr0_0 = OperandSize::Size64;
3049             let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?;
3050             return Some(expr1_0);
3051         }
3052         if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) {
3053             // Rule at src/isa/aarch64/inst.isle line 1854.
3054             let expr0_0 = OperandSize::Size64;
3055             let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?;
3056             return Some(expr1_0);
3057         }
3058         // Rule at src/isa/aarch64/inst.isle line 1865.
3059         let expr0_0 = C::load_constant64_full(ctx, pattern2_0);
3060         return Some(expr0_0);
3061     }
3062     return None;
3063 }
3064 
3065 // Generated as internal constructor for term put_in_reg_sext32.
3066 pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3067     let pattern0_0 = arg0;
3068     let pattern1_0 = C::value_type(ctx, pattern0_0);
3069     if pattern1_0 == I32 {
3070         // Rule at src/isa/aarch64/inst.isle line 1876.
3071         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3072         return Some(expr0_0);
3073     }
3074     if pattern1_0 == I64 {
3075         // Rule at src/isa/aarch64/inst.isle line 1877.
3076         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3077         return Some(expr0_0);
3078     }
3079     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3080         // Rule at src/isa/aarch64/inst.isle line 1872.
3081         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3082         let expr1_0: bool = true;
3083         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3084         let expr3_0: u8 = 32;
3085         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3086         return Some(expr4_0);
3087     }
3088     return None;
3089 }
3090 
3091 // Generated as internal constructor for term put_in_reg_zext32.
3092 pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3093     let pattern0_0 = arg0;
3094     let pattern1_0 = C::value_type(ctx, pattern0_0);
3095     if pattern1_0 == I32 {
3096         // Rule at src/isa/aarch64/inst.isle line 1885.
3097         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3098         return Some(expr0_0);
3099     }
3100     if pattern1_0 == I64 {
3101         // Rule at src/isa/aarch64/inst.isle line 1886.
3102         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3103         return Some(expr0_0);
3104     }
3105     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3106         // Rule at src/isa/aarch64/inst.isle line 1881.
3107         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3108         let expr1_0: bool = false;
3109         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3110         let expr3_0: u8 = 32;
3111         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3112         return Some(expr4_0);
3113     }
3114     return None;
3115 }
3116 
3117 // Generated as internal constructor for term put_in_reg_sext64.
3118 pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3119     let pattern0_0 = arg0;
3120     let pattern1_0 = C::value_type(ctx, pattern0_0);
3121     if pattern1_0 == I64 {
3122         // Rule at src/isa/aarch64/inst.isle line 1894.
3123         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3124         return Some(expr0_0);
3125     }
3126     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3127         // Rule at src/isa/aarch64/inst.isle line 1890.
3128         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3129         let expr1_0: bool = true;
3130         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3131         let expr3_0: u8 = 64;
3132         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3133         return Some(expr4_0);
3134     }
3135     return None;
3136 }
3137 
3138 // Generated as internal constructor for term put_in_reg_zext64.
3139 pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3140     let pattern0_0 = arg0;
3141     let pattern1_0 = C::value_type(ctx, pattern0_0);
3142     if pattern1_0 == I64 {
3143         // Rule at src/isa/aarch64/inst.isle line 1902.
3144         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3145         return Some(expr0_0);
3146     }
3147     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3148         // Rule at src/isa/aarch64/inst.isle line 1898.
3149         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3150         let expr1_0: bool = false;
3151         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3152         let expr3_0: u8 = 64;
3153         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3154         return Some(expr4_0);
3155     }
3156     return None;
3157 }
3158 
3159 // Generated as internal constructor for term trap_if_zero_divisor.
3160 pub fn constructor_trap_if_zero_divisor<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3161     let pattern0_0 = arg0;
3162     // Rule at src/isa/aarch64/inst.isle line 1907.
3163     let expr0_0 = C::cond_br_zero(ctx, pattern0_0);
3164     let expr1_0 = C::trap_code_division_by_zero(ctx);
3165     let expr2_0 = MInst::TrapIf {
3166         kind: expr0_0,
3167         trap_code: expr1_0,
3168     };
3169     let expr3_0 = C::emit(ctx, &expr2_0);
3170     return Some(pattern0_0);
3171 }
3172 
3173 // Generated as internal constructor for term size_from_ty.
3174 pub fn constructor_size_from_ty<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
3175     let pattern0_0 = arg0;
3176     if pattern0_0 == I64 {
3177         // Rule at src/isa/aarch64/inst.isle line 1913.
3178         let expr0_0 = OperandSize::Size64;
3179         return Some(expr0_0);
3180     }
3181     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
3182         // Rule at src/isa/aarch64/inst.isle line 1912.
3183         let expr0_0 = OperandSize::Size32;
3184         return Some(expr0_0);
3185     }
3186     return None;
3187 }
3188 
3189 // Generated as internal constructor for term trap_if_div_overflow.
3190 pub fn constructor_trap_if_div_overflow<C: Context>(
3191     ctx: &mut C,
3192     arg0: Type,
3193     arg1: Reg,
3194     arg2: Reg,
3195 ) -> Option<Reg> {
3196     let pattern0_0 = arg0;
3197     let pattern1_0 = arg1;
3198     let pattern2_0 = arg2;
3199     // Rule at src/isa/aarch64/inst.isle line 1919.
3200     let expr0_0 = ALUOp::AddS;
3201     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
3202     let expr2_0 = C::writable_zero_reg(ctx);
3203     let expr3_0: u8 = 1;
3204     let expr4_0 = C::u8_into_imm12(ctx, expr3_0);
3205     let expr5_0 = MInst::AluRRImm12 {
3206         alu_op: expr0_0,
3207         size: expr1_0,
3208         rd: expr2_0,
3209         rn: pattern2_0,
3210         imm12: expr4_0,
3211     };
3212     let expr6_0 = C::emit(ctx, &expr5_0);
3213     let expr7_0 = constructor_size_from_ty(ctx, pattern0_0)?;
3214     let expr8_0: u8 = 1;
3215     let expr9_0 = C::u8_into_uimm5(ctx, expr8_0);
3216     let expr10_0: bool = false;
3217     let expr11_0: bool = false;
3218     let expr12_0: bool = false;
3219     let expr13_0: bool = false;
3220     let expr14_0 = C::nzcv(ctx, expr10_0, expr11_0, expr12_0, expr13_0);
3221     let expr15_0 = Cond::Eq;
3222     let expr16_0 = MInst::CCmpImm {
3223         size: expr7_0,
3224         rn: pattern1_0,
3225         imm: expr9_0,
3226         nzcv: expr14_0,
3227         cond: expr15_0,
3228     };
3229     let expr17_0 = C::emit(ctx, &expr16_0);
3230     let expr18_0 = Cond::Vs;
3231     let expr19_0 = C::cond_br_cond(ctx, &expr18_0);
3232     let expr20_0 = C::trap_code_integer_overflow(ctx);
3233     let expr21_0 = MInst::TrapIf {
3234         kind: expr19_0,
3235         trap_code: expr20_0,
3236     };
3237     let expr22_0 = C::emit(ctx, &expr21_0);
3238     return Some(pattern1_0);
3239 }
3240 
3241 // Generated as internal constructor for term alu_rs_imm_logic_commutative.
3242 pub fn constructor_alu_rs_imm_logic_commutative<C: Context>(
3243     ctx: &mut C,
3244     arg0: &ALUOp,
3245     arg1: Type,
3246     arg2: Value,
3247     arg3: Value,
3248 ) -> Option<Reg> {
3249     let pattern0_0 = arg0;
3250     let pattern1_0 = arg1;
3251     let pattern2_0 = arg2;
3252     if let Some(pattern3_0) = C::def_inst(ctx, pattern2_0) {
3253         let pattern4_0 = C::inst_data(ctx, pattern3_0);
3254         match &pattern4_0 {
3255             &InstructionData::UnaryImm {
3256                 opcode: ref pattern5_0,
3257                 imm: pattern5_1,
3258             } => {
3259                 if let &Opcode::Iconst = pattern5_0 {
3260                     let closure7 = || {
3261                         return Some(pattern1_0);
3262                     };
3263                     if let Some(pattern7_0) = closure7() {
3264                         if let Some(pattern8_0) =
3265                             C::imm_logic_from_imm64(ctx, pattern5_1, pattern7_0)
3266                         {
3267                             let pattern9_0 = arg3;
3268                             // Rule at src/isa/aarch64/inst.isle line 1964.
3269                             let expr0_0 = C::put_in_reg(ctx, pattern9_0);
3270                             let expr1_0 = constructor_alu_rr_imm_logic(
3271                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0,
3272                             )?;
3273                             return Some(expr1_0);
3274                         }
3275                     }
3276                 }
3277             }
3278             &InstructionData::Binary {
3279                 opcode: ref pattern5_0,
3280                 args: ref pattern5_1,
3281             } => {
3282                 if let &Opcode::Ishl = pattern5_0 {
3283                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3284                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3285                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
3286                         if let &InstructionData::UnaryImm {
3287                             opcode: ref pattern10_0,
3288                             imm: pattern10_1,
3289                         } = &pattern9_0
3290                         {
3291                             if let &Opcode::Iconst = pattern10_0 {
3292                                 let closure12 = || {
3293                                     return Some(pattern1_0);
3294                                 };
3295                                 if let Some(pattern12_0) = closure12() {
3296                                     if let Some(pattern13_0) =
3297                                         C::lshl_from_imm64(ctx, pattern10_1, pattern12_0)
3298                                     {
3299                                         let pattern14_0 = arg3;
3300                                         // Rule at src/isa/aarch64/inst.isle line 1970.
3301                                         let expr0_0 = C::put_in_reg(ctx, pattern14_0);
3302                                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3303                                         let expr2_0 = constructor_alu_rrr_shift(
3304                                             ctx,
3305                                             pattern0_0,
3306                                             pattern1_0,
3307                                             expr0_0,
3308                                             expr1_0,
3309                                             pattern13_0,
3310                                         )?;
3311                                         return Some(expr2_0);
3312                                     }
3313                                 }
3314                             }
3315                         }
3316                     }
3317                 }
3318             }
3319             _ => {}
3320         }
3321     }
3322     let pattern3_0 = arg3;
3323     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3324         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3325         match &pattern5_0 {
3326             &InstructionData::UnaryImm {
3327                 opcode: ref pattern6_0,
3328                 imm: pattern6_1,
3329             } => {
3330                 if let &Opcode::Iconst = pattern6_0 {
3331                     let closure8 = || {
3332                         return Some(pattern1_0);
3333                     };
3334                     if let Some(pattern8_0) = closure8() {
3335                         if let Some(pattern9_0) =
3336                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3337                         {
3338                             // Rule at src/isa/aarch64/inst.isle line 1962.
3339                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3340                             let expr1_0 = constructor_alu_rr_imm_logic(
3341                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3342                             )?;
3343                             return Some(expr1_0);
3344                         }
3345                     }
3346                 }
3347             }
3348             &InstructionData::Binary {
3349                 opcode: ref pattern6_0,
3350                 args: ref pattern6_1,
3351             } => {
3352                 if let &Opcode::Ishl = pattern6_0 {
3353                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3354                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3355                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3356                         if let &InstructionData::UnaryImm {
3357                             opcode: ref pattern11_0,
3358                             imm: pattern11_1,
3359                         } = &pattern10_0
3360                         {
3361                             if let &Opcode::Iconst = pattern11_0 {
3362                                 let closure13 = || {
3363                                     return Some(pattern1_0);
3364                                 };
3365                                 if let Some(pattern13_0) = closure13() {
3366                                     if let Some(pattern14_0) =
3367                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3368                                     {
3369                                         // Rule at src/isa/aarch64/inst.isle line 1968.
3370                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3371                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3372                                         let expr2_0 = constructor_alu_rrr_shift(
3373                                             ctx,
3374                                             pattern0_0,
3375                                             pattern1_0,
3376                                             expr0_0,
3377                                             expr1_0,
3378                                             pattern14_0,
3379                                         )?;
3380                                         return Some(expr2_0);
3381                                     }
3382                                 }
3383                             }
3384                         }
3385                     }
3386                 }
3387             }
3388             _ => {}
3389         }
3390     }
3391     // Rule at src/isa/aarch64/inst.isle line 1958.
3392     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3393     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3394     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3395     return Some(expr2_0);
3396 }
3397 
3398 // Generated as internal constructor for term alu_rs_imm_logic.
3399 pub fn constructor_alu_rs_imm_logic<C: Context>(
3400     ctx: &mut C,
3401     arg0: &ALUOp,
3402     arg1: Type,
3403     arg2: Value,
3404     arg3: Value,
3405 ) -> Option<Reg> {
3406     let pattern0_0 = arg0;
3407     let pattern1_0 = arg1;
3408     let pattern2_0 = arg2;
3409     let pattern3_0 = arg3;
3410     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3411         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3412         match &pattern5_0 {
3413             &InstructionData::UnaryImm {
3414                 opcode: ref pattern6_0,
3415                 imm: pattern6_1,
3416             } => {
3417                 if let &Opcode::Iconst = pattern6_0 {
3418                     let closure8 = || {
3419                         return Some(pattern1_0);
3420                     };
3421                     if let Some(pattern8_0) = closure8() {
3422                         if let Some(pattern9_0) =
3423                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3424                         {
3425                             // Rule at src/isa/aarch64/inst.isle line 1978.
3426                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3427                             let expr1_0 = constructor_alu_rr_imm_logic(
3428                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3429                             )?;
3430                             return Some(expr1_0);
3431                         }
3432                     }
3433                 }
3434             }
3435             &InstructionData::Binary {
3436                 opcode: ref pattern6_0,
3437                 args: ref pattern6_1,
3438             } => {
3439                 if let &Opcode::Ishl = pattern6_0 {
3440                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3441                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3442                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3443                         if let &InstructionData::UnaryImm {
3444                             opcode: ref pattern11_0,
3445                             imm: pattern11_1,
3446                         } = &pattern10_0
3447                         {
3448                             if let &Opcode::Iconst = pattern11_0 {
3449                                 let closure13 = || {
3450                                     return Some(pattern1_0);
3451                                 };
3452                                 if let Some(pattern13_0) = closure13() {
3453                                     if let Some(pattern14_0) =
3454                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3455                                     {
3456                                         // Rule at src/isa/aarch64/inst.isle line 1980.
3457                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3458                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3459                                         let expr2_0 = constructor_alu_rrr_shift(
3460                                             ctx,
3461                                             pattern0_0,
3462                                             pattern1_0,
3463                                             expr0_0,
3464                                             expr1_0,
3465                                             pattern14_0,
3466                                         )?;
3467                                         return Some(expr2_0);
3468                                     }
3469                                 }
3470                             }
3471                         }
3472                     }
3473                 }
3474             }
3475             _ => {}
3476         }
3477     }
3478     // Rule at src/isa/aarch64/inst.isle line 1976.
3479     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3480     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3481     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3482     return Some(expr2_0);
3483 }
3484 
3485 // Generated as internal constructor for term i128_alu_bitop.
3486 pub fn constructor_i128_alu_bitop<C: Context>(
3487     ctx: &mut C,
3488     arg0: &ALUOp,
3489     arg1: Type,
3490     arg2: Value,
3491     arg3: Value,
3492 ) -> Option<ValueRegs> {
3493     let pattern0_0 = arg0;
3494     let pattern1_0 = arg1;
3495     let pattern2_0 = arg2;
3496     let pattern3_0 = arg3;
3497     // Rule at src/isa/aarch64/inst.isle line 1988.
3498     let expr0_0 = C::put_in_regs(ctx, pattern2_0);
3499     let expr1_0: usize = 0;
3500     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3501     let expr3_0: usize = 1;
3502     let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
3503     let expr5_0 = C::put_in_regs(ctx, pattern3_0);
3504     let expr6_0: usize = 0;
3505     let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
3506     let expr8_0: usize = 1;
3507     let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
3508     let expr10_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr2_0, expr7_0)?;
3509     let expr11_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr4_0, expr9_0)?;
3510     let expr12_0 = C::value_regs(ctx, expr10_0, expr11_0);
3511     return Some(expr12_0);
3512 }
3513 
3514 // Generated as internal constructor for term lower.
3515 pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> {
3516     let pattern0_0 = arg0;
3517     if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
3518         let pattern2_0 = C::value_type(ctx, pattern1_0);
3519         if pattern2_0 == I8 {
3520             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3521             if let &InstructionData::Unary {
3522                 opcode: ref pattern5_0,
3523                 arg: pattern5_1,
3524             } = &pattern4_0
3525             {
3526                 match pattern5_0 {
3527                     &Opcode::Bitrev => {
3528                         // Rule at src/isa/aarch64/lower.isle line 974.
3529                         let expr0_0: Type = I32;
3530                         let expr1_0: Type = I32;
3531                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3532                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3533                         let expr4_0: u8 = 24;
3534                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3535                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3536                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3537                         return Some(expr7_0);
3538                     }
3539                     &Opcode::Clz => {
3540                         // Rule at src/isa/aarch64/lower.isle line 995.
3541                         let expr0_0: Type = I32;
3542                         let expr1_0: Type = I32;
3543                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3544                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3545                         let expr4_0: u8 = 24;
3546                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3547                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3548                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3549                         return Some(expr7_0);
3550                     }
3551                     &Opcode::Cls => {
3552                         // Rule at src/isa/aarch64/lower.isle line 1042.
3553                         let expr0_0: Type = I32;
3554                         let expr1_0: Type = I32;
3555                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3556                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3557                         let expr4_0: u8 = 24;
3558                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3559                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3560                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3561                         return Some(expr7_0);
3562                     }
3563                     &Opcode::Ctz => {
3564                         // Rule at src/isa/aarch64/lower.isle line 1025.
3565                         let expr0_0: Type = I32;
3566                         let expr1_0: Type = I32;
3567                         let expr2_0: Type = I32;
3568                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3569                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3570                         let expr5_0: Type = I32;
3571                         let expr6_0: u64 = 8388608;
3572                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3573                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3574                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3575                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3576                         return Some(expr10_0);
3577                     }
3578                     &Opcode::Popcnt => {
3579                         // Rule at src/isa/aarch64/lower.isle line 1093.
3580                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3581                         let expr1_0 = ScalarSize::Size32;
3582                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3583                         let expr3_0 = VectorSize::Size8x8;
3584                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3585                         let expr5_0: u8 = 0;
3586                         let expr6_0 = VectorSize::Size8x16;
3587                         let expr7_0 = constructor_mov_from_vec(ctx, expr4_0, expr5_0, &expr6_0)?;
3588                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
3589                         return Some(expr8_0);
3590                     }
3591                     _ => {}
3592                 }
3593             }
3594         }
3595         if pattern2_0 == I16 {
3596             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3597             if let &InstructionData::Unary {
3598                 opcode: ref pattern5_0,
3599                 arg: pattern5_1,
3600             } = &pattern4_0
3601             {
3602                 match pattern5_0 {
3603                     &Opcode::Bitrev => {
3604                         // Rule at src/isa/aarch64/lower.isle line 980.
3605                         let expr0_0: Type = I32;
3606                         let expr1_0: Type = I32;
3607                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3608                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3609                         let expr4_0: u8 = 16;
3610                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3611                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3612                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3613                         return Some(expr7_0);
3614                     }
3615                     &Opcode::Clz => {
3616                         // Rule at src/isa/aarch64/lower.isle line 998.
3617                         let expr0_0: Type = I32;
3618                         let expr1_0: Type = I32;
3619                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3620                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3621                         let expr4_0: u8 = 16;
3622                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3623                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3624                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3625                         return Some(expr7_0);
3626                     }
3627                     &Opcode::Cls => {
3628                         // Rule at src/isa/aarch64/lower.isle line 1045.
3629                         let expr0_0: Type = I32;
3630                         let expr1_0: Type = I32;
3631                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3632                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3633                         let expr4_0: u8 = 16;
3634                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3635                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3636                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3637                         return Some(expr7_0);
3638                     }
3639                     &Opcode::Ctz => {
3640                         // Rule at src/isa/aarch64/lower.isle line 1028.
3641                         let expr0_0: Type = I32;
3642                         let expr1_0: Type = I32;
3643                         let expr2_0: Type = I32;
3644                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3645                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3646                         let expr5_0: Type = I32;
3647                         let expr6_0: u64 = 32768;
3648                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3649                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3650                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3651                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3652                         return Some(expr10_0);
3653                     }
3654                     &Opcode::Popcnt => {
3655                         // Rule at src/isa/aarch64/lower.isle line 1099.
3656                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3657                         let expr1_0 = ScalarSize::Size32;
3658                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3659                         let expr3_0 = VectorSize::Size8x8;
3660                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3661                         let expr5_0 = VectorSize::Size8x8;
3662                         let expr6_0 = constructor_addp(ctx, expr4_0, expr4_0, &expr5_0)?;
3663                         let expr7_0: u8 = 0;
3664                         let expr8_0 = VectorSize::Size8x16;
3665                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3666                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3667                         return Some(expr10_0);
3668                     }
3669                     _ => {}
3670                 }
3671             }
3672         }
3673         if pattern2_0 == I32 {
3674             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3675             match &pattern4_0 {
3676                 &InstructionData::Binary {
3677                     opcode: ref pattern5_0,
3678                     args: ref pattern5_1,
3679                 } => {
3680                     match pattern5_0 {
3681                         &Opcode::Rotl => {
3682                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3683                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3684                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3685                                 if let &InstructionData::UnaryImm {
3686                                     opcode: ref pattern10_0,
3687                                     imm: pattern10_1,
3688                                 } = &pattern9_0
3689                                 {
3690                                     if let &Opcode::Iconst = pattern10_0 {
3691                                         let closure12 = || {
3692                                             let expr0_0: Type = I32;
3693                                             return Some(expr0_0);
3694                                         };
3695                                         if let Some(pattern12_0) = closure12() {
3696                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3697                                                 ctx,
3698                                                 pattern10_1,
3699                                                 pattern12_0,
3700                                             ) {
3701                                                 // Rule at src/isa/aarch64/lower.isle line 865.
3702                                                 let expr0_0: Type = I32;
3703                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3704                                                 let expr2_0: Type = I32;
3705                                                 let expr3_0 =
3706                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3707                                                 let expr4_0 = constructor_a64_rotr_imm(
3708                                                     ctx, expr0_0, expr1_0, expr3_0,
3709                                                 )?;
3710                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3711                                                 return Some(expr5_0);
3712                                             }
3713                                         }
3714                                     }
3715                                 }
3716                             }
3717                             // Rule at src/isa/aarch64/lower.isle line 855.
3718                             let expr0_0: Type = I32;
3719                             let expr1_0 = C::zero_reg(ctx);
3720                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3721                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3722                             let expr4_0: Type = I32;
3723                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3724                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3725                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3726                             return Some(expr7_0);
3727                         }
3728                         &Opcode::Rotr => {
3729                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3730                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3731                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3732                                 if let &InstructionData::UnaryImm {
3733                                     opcode: ref pattern10_0,
3734                                     imm: pattern10_1,
3735                                 } = &pattern9_0
3736                                 {
3737                                     if let &Opcode::Iconst = pattern10_0 {
3738                                         let closure12 = || {
3739                                             let expr0_0: Type = I32;
3740                                             return Some(expr0_0);
3741                                         };
3742                                         if let Some(pattern12_0) = closure12() {
3743                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3744                                                 ctx,
3745                                                 pattern10_1,
3746                                                 pattern12_0,
3747                                             ) {
3748                                                 // Rule at src/isa/aarch64/lower.isle line 907.
3749                                                 let expr0_0: Type = I32;
3750                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3751                                                 let expr2_0 = constructor_a64_rotr_imm(
3752                                                     ctx,
3753                                                     expr0_0,
3754                                                     expr1_0,
3755                                                     pattern13_0,
3756                                                 )?;
3757                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3758                                                 return Some(expr3_0);
3759                                             }
3760                                         }
3761                                     }
3762                                 }
3763                             }
3764                             // Rule at src/isa/aarch64/lower.isle line 895.
3765                             let expr0_0: Type = I32;
3766                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3767                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3768                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
3769                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3770                             return Some(expr4_0);
3771                         }
3772                         _ => {}
3773                     }
3774                 }
3775                 &InstructionData::Unary {
3776                     opcode: ref pattern5_0,
3777                     arg: pattern5_1,
3778                 } => {
3779                     if let &Opcode::Popcnt = pattern5_0 {
3780                         // Rule at src/isa/aarch64/lower.isle line 1105.
3781                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3782                         let expr1_0 = ScalarSize::Size32;
3783                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3784                         let expr3_0 = VectorSize::Size8x8;
3785                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3786                         let expr5_0 = VectorSize::Size8x8;
3787                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
3788                         let expr7_0: u8 = 0;
3789                         let expr8_0 = VectorSize::Size8x16;
3790                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3791                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3792                         return Some(expr10_0);
3793                     }
3794                 }
3795                 _ => {}
3796             }
3797         }
3798         if pattern2_0 == I64 {
3799             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3800             match &pattern4_0 {
3801                 &InstructionData::Binary {
3802                     opcode: ref pattern5_0,
3803                     args: ref pattern5_1,
3804                 } => {
3805                     match pattern5_0 {
3806                         &Opcode::Umulhi => {
3807                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3808                             // Rule at src/isa/aarch64/lower.isle line 367.
3809                             let expr0_0: Type = I64;
3810                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3811                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3812                             let expr3_0 = constructor_umulh(ctx, expr0_0, expr1_0, expr2_0)?;
3813                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3814                             return Some(expr4_0);
3815                         }
3816                         &Opcode::Smulhi => {
3817                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3818                             // Rule at src/isa/aarch64/lower.isle line 355.
3819                             let expr0_0: Type = I64;
3820                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3821                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3822                             let expr3_0 = constructor_smulh(ctx, expr0_0, expr1_0, expr2_0)?;
3823                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3824                             return Some(expr4_0);
3825                         }
3826                         &Opcode::Band => {
3827                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3828                             // Rule at src/isa/aarch64/lower.isle line 586.
3829                             let expr0_0 = ALUOp::And;
3830                             let expr1_0: Type = I64;
3831                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3832                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3833                             )?;
3834                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3835                             return Some(expr3_0);
3836                         }
3837                         &Opcode::Bor => {
3838                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3839                             // Rule at src/isa/aarch64/lower.isle line 599.
3840                             let expr0_0 = ALUOp::Orr;
3841                             let expr1_0: Type = I64;
3842                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3843                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3844                             )?;
3845                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3846                             return Some(expr3_0);
3847                         }
3848                         &Opcode::Bxor => {
3849                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3850                             // Rule at src/isa/aarch64/lower.isle line 612.
3851                             let expr0_0 = ALUOp::Eor;
3852                             let expr1_0: Type = I64;
3853                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3854                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3855                             )?;
3856                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3857                             return Some(expr3_0);
3858                         }
3859                         &Opcode::BandNot => {
3860                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3861                             // Rule at src/isa/aarch64/lower.isle line 625.
3862                             let expr0_0 = ALUOp::AndNot;
3863                             let expr1_0: Type = I64;
3864                             let expr2_0 = constructor_alu_rs_imm_logic(
3865                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3866                             )?;
3867                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3868                             return Some(expr3_0);
3869                         }
3870                         &Opcode::BorNot => {
3871                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3872                             // Rule at src/isa/aarch64/lower.isle line 638.
3873                             let expr0_0 = ALUOp::OrrNot;
3874                             let expr1_0: Type = I64;
3875                             let expr2_0 = constructor_alu_rs_imm_logic(
3876                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3877                             )?;
3878                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3879                             return Some(expr3_0);
3880                         }
3881                         &Opcode::BxorNot => {
3882                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3883                             // Rule at src/isa/aarch64/lower.isle line 648.
3884                             let expr0_0 = ALUOp::EorNot;
3885                             let expr1_0: Type = I64;
3886                             let expr2_0 = constructor_alu_rs_imm_logic(
3887                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3888                             )?;
3889                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3890                             return Some(expr3_0);
3891                         }
3892                         &Opcode::Rotl => {
3893                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3894                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3895                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3896                                 if let &InstructionData::UnaryImm {
3897                                     opcode: ref pattern10_0,
3898                                     imm: pattern10_1,
3899                                 } = &pattern9_0
3900                                 {
3901                                     if let &Opcode::Iconst = pattern10_0 {
3902                                         let closure12 = || {
3903                                             let expr0_0: Type = I64;
3904                                             return Some(expr0_0);
3905                                         };
3906                                         if let Some(pattern12_0) = closure12() {
3907                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3908                                                 ctx,
3909                                                 pattern10_1,
3910                                                 pattern12_0,
3911                                             ) {
3912                                                 // Rule at src/isa/aarch64/lower.isle line 869.
3913                                                 let expr0_0: Type = I64;
3914                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3915                                                 let expr2_0: Type = I64;
3916                                                 let expr3_0 =
3917                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3918                                                 let expr4_0 = constructor_a64_rotr_imm(
3919                                                     ctx, expr0_0, expr1_0, expr3_0,
3920                                                 )?;
3921                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3922                                                 return Some(expr5_0);
3923                                             }
3924                                         }
3925                                     }
3926                                 }
3927                             }
3928                             // Rule at src/isa/aarch64/lower.isle line 860.
3929                             let expr0_0: Type = I64;
3930                             let expr1_0 = C::zero_reg(ctx);
3931                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3932                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3933                             let expr4_0: Type = I64;
3934                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3935                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3936                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3937                             return Some(expr7_0);
3938                         }
3939                         &Opcode::Rotr => {
3940                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3941                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3942                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3943                                 if let &InstructionData::UnaryImm {
3944                                     opcode: ref pattern10_0,
3945                                     imm: pattern10_1,
3946                                 } = &pattern9_0
3947                                 {
3948                                     if let &Opcode::Iconst = pattern10_0 {
3949                                         let closure12 = || {
3950                                             let expr0_0: Type = I64;
3951                                             return Some(expr0_0);
3952                                         };
3953                                         if let Some(pattern12_0) = closure12() {
3954                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3955                                                 ctx,
3956                                                 pattern10_1,
3957                                                 pattern12_0,
3958                                             ) {
3959                                                 // Rule at src/isa/aarch64/lower.isle line 911.
3960                                                 let expr0_0: Type = I64;
3961                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3962                                                 let expr2_0 = constructor_a64_rotr_imm(
3963                                                     ctx,
3964                                                     expr0_0,
3965                                                     expr1_0,
3966                                                     pattern13_0,
3967                                                 )?;
3968                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3969                                                 return Some(expr3_0);
3970                                             }
3971                                         }
3972                                     }
3973                                 }
3974                             }
3975                             // Rule at src/isa/aarch64/lower.isle line 899.
3976                             let expr0_0: Type = I64;
3977                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3978                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3979                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
3980                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3981                             return Some(expr4_0);
3982                         }
3983                         &Opcode::Ishl => {
3984                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3985                             // Rule at src/isa/aarch64/lower.isle line 660.
3986                             let expr0_0 = ALUOp::Lsl;
3987                             let expr1_0: Type = I64;
3988                             let expr2_0 = C::put_in_reg(ctx, pattern7_0);
3989                             let expr3_0 =
3990                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
3991                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3992                             return Some(expr4_0);
3993                         }
3994                         &Opcode::Ushr => {
3995                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3996                             // Rule at src/isa/aarch64/lower.isle line 744.
3997                             let expr0_0 = ALUOp::Lsr;
3998                             let expr1_0: Type = I64;
3999                             let expr2_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
4000                             let expr3_0 =
4001                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4002                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4003                             return Some(expr4_0);
4004                         }
4005                         &Opcode::Sshr => {
4006                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4007                             // Rule at src/isa/aarch64/lower.isle line 791.
4008                             let expr0_0 = ALUOp::Asr;
4009                             let expr1_0: Type = I64;
4010                             let expr2_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
4011                             let expr3_0 =
4012                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4013                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4014                             return Some(expr4_0);
4015                         }
4016                         _ => {}
4017                     }
4018                 }
4019                 &InstructionData::Unary {
4020                     opcode: ref pattern5_0,
4021                     arg: pattern5_1,
4022                 } => {
4023                     if let &Opcode::Popcnt = pattern5_0 {
4024                         // Rule at src/isa/aarch64/lower.isle line 1111.
4025                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4026                         let expr1_0 = ScalarSize::Size64;
4027                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
4028                         let expr3_0 = VectorSize::Size8x8;
4029                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
4030                         let expr5_0 = VectorSize::Size8x8;
4031                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
4032                         let expr7_0: u8 = 0;
4033                         let expr8_0 = VectorSize::Size8x16;
4034                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
4035                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
4036                         return Some(expr10_0);
4037                     }
4038                 }
4039                 _ => {}
4040             }
4041         }
4042         if pattern2_0 == I128 {
4043             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4044             match &pattern4_0 {
4045                 &InstructionData::Binary {
4046                     opcode: ref pattern5_0,
4047                     args: ref pattern5_1,
4048                 } => {
4049                     match pattern5_0 {
4050                         &Opcode::Iadd => {
4051                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4052                             // Rule at src/isa/aarch64/lower.isle line 79.
4053                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4054                             let expr1_0: usize = 0;
4055                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4056                             let expr3_0: usize = 1;
4057                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4058                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4059                             let expr6_0: usize = 0;
4060                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4061                             let expr8_0: usize = 1;
4062                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4063                             let expr10_0: Type = I64;
4064                             let expr11_0 =
4065                                 constructor_add_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4066                             let expr12_0: Type = I64;
4067                             let expr13_0 = constructor_adc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4068                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4069                             let expr15_0 = C::output(ctx, expr14_0);
4070                             return Some(expr15_0);
4071                         }
4072                         &Opcode::Isub => {
4073                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4074                             // Rule at src/isa/aarch64/lower.isle line 129.
4075                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4076                             let expr1_0: usize = 0;
4077                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4078                             let expr3_0: usize = 1;
4079                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4080                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4081                             let expr6_0: usize = 0;
4082                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4083                             let expr8_0: usize = 1;
4084                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4085                             let expr10_0: Type = I64;
4086                             let expr11_0 =
4087                                 constructor_sub_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4088                             let expr12_0: Type = I64;
4089                             let expr13_0 = constructor_sbc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4090                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4091                             let expr15_0 = C::output(ctx, expr14_0);
4092                             return Some(expr15_0);
4093                         }
4094                         &Opcode::Imul => {
4095                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4096                             // Rule at src/isa/aarch64/lower.isle line 183.
4097                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4098                             let expr1_0: usize = 0;
4099                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4100                             let expr3_0: usize = 1;
4101                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4102                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4103                             let expr6_0: usize = 0;
4104                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4105                             let expr8_0: usize = 1;
4106                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4107                             let expr10_0: Type = I64;
4108                             let expr11_0 = constructor_umulh(ctx, expr10_0, expr2_0, expr7_0)?;
4109                             let expr12_0 = constructor_madd64(ctx, expr2_0, expr9_0, expr11_0)?;
4110                             let expr13_0 = constructor_madd64(ctx, expr4_0, expr7_0, expr12_0)?;
4111                             let expr14_0 = C::zero_reg(ctx);
4112                             let expr15_0 = constructor_madd64(ctx, expr2_0, expr7_0, expr14_0)?;
4113                             let expr16_0 = C::value_regs(ctx, expr15_0, expr13_0);
4114                             let expr17_0 = C::output(ctx, expr16_0);
4115                             return Some(expr17_0);
4116                         }
4117                         &Opcode::Band => {
4118                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4119                             // Rule at src/isa/aarch64/lower.isle line 589.
4120                             let expr0_0 = ALUOp::And;
4121                             let expr1_0: Type = I64;
4122                             let expr2_0 = constructor_i128_alu_bitop(
4123                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4124                             )?;
4125                             let expr3_0 = C::output(ctx, expr2_0);
4126                             return Some(expr3_0);
4127                         }
4128                         &Opcode::Bor => {
4129                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4130                             // Rule at src/isa/aarch64/lower.isle line 602.
4131                             let expr0_0 = ALUOp::Orr;
4132                             let expr1_0: Type = I64;
4133                             let expr2_0 = constructor_i128_alu_bitop(
4134                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4135                             )?;
4136                             let expr3_0 = C::output(ctx, expr2_0);
4137                             return Some(expr3_0);
4138                         }
4139                         &Opcode::Bxor => {
4140                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4141                             // Rule at src/isa/aarch64/lower.isle line 615.
4142                             let expr0_0 = ALUOp::Eor;
4143                             let expr1_0: Type = I64;
4144                             let expr2_0 = constructor_i128_alu_bitop(
4145                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4146                             )?;
4147                             let expr3_0 = C::output(ctx, expr2_0);
4148                             return Some(expr3_0);
4149                         }
4150                         &Opcode::BandNot => {
4151                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4152                             // Rule at src/isa/aarch64/lower.isle line 628.
4153                             let expr0_0 = ALUOp::AndNot;
4154                             let expr1_0: Type = I64;
4155                             let expr2_0 = constructor_i128_alu_bitop(
4156                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4157                             )?;
4158                             let expr3_0 = C::output(ctx, expr2_0);
4159                             return Some(expr3_0);
4160                         }
4161                         &Opcode::BorNot => {
4162                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4163                             // Rule at src/isa/aarch64/lower.isle line 641.
4164                             let expr0_0 = ALUOp::OrrNot;
4165                             let expr1_0: Type = I64;
4166                             let expr2_0 = constructor_i128_alu_bitop(
4167                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4168                             )?;
4169                             let expr3_0 = C::output(ctx, expr2_0);
4170                             return Some(expr3_0);
4171                         }
4172                         &Opcode::BxorNot => {
4173                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4174                             // Rule at src/isa/aarch64/lower.isle line 651.
4175                             let expr0_0 = ALUOp::EorNot;
4176                             let expr1_0: Type = I64;
4177                             let expr2_0 = constructor_i128_alu_bitop(
4178                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4179                             )?;
4180                             let expr3_0 = C::output(ctx, expr2_0);
4181                             return Some(expr3_0);
4182                         }
4183                         &Opcode::Rotl => {
4184                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4185                             // Rule at src/isa/aarch64/lower.isle line 878.
4186                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4187                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4188                             let expr2_0: usize = 0;
4189                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4190                             let expr4_0: Type = I64;
4191                             let expr5_0: Type = I64;
4192                             let expr6_0: u64 = 128;
4193                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4194                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4195                             let expr9_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4196                             let expr10_0 = constructor_lower_ushr128(ctx, expr0_0, expr8_0)?;
4197                             let expr11_0: Type = I64;
4198                             let expr12_0: usize = 0;
4199                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4200                             let expr14_0: usize = 0;
4201                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4202                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4203                             let expr17_0: Type = I64;
4204                             let expr18_0: usize = 1;
4205                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4206                             let expr20_0: usize = 1;
4207                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4208                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4209                             let expr23_0 = C::value_regs(ctx, expr16_0, expr22_0);
4210                             let expr24_0 = C::output(ctx, expr23_0);
4211                             return Some(expr24_0);
4212                         }
4213                         &Opcode::Rotr => {
4214                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4215                             // Rule at src/isa/aarch64/lower.isle line 959.
4216                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4217                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4218                             let expr2_0: usize = 0;
4219                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4220                             let expr4_0: Type = I64;
4221                             let expr5_0: Type = I64;
4222                             let expr6_0: u64 = 128;
4223                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4224                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4225                             let expr9_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4226                             let expr10_0 = constructor_lower_shl128(ctx, expr0_0, expr8_0)?;
4227                             let expr11_0: Type = I64;
4228                             let expr12_0: usize = 1;
4229                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4230                             let expr14_0: usize = 1;
4231                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4232                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4233                             let expr17_0: Type = I64;
4234                             let expr18_0: usize = 0;
4235                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4236                             let expr20_0: usize = 0;
4237                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4238                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4239                             let expr23_0 = C::value_regs(ctx, expr22_0, expr16_0);
4240                             let expr24_0 = C::output(ctx, expr23_0);
4241                             return Some(expr24_0);
4242                         }
4243                         &Opcode::Ishl => {
4244                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4245                             // Rule at src/isa/aarch64/lower.isle line 664.
4246                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4247                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4248                             let expr2_0: usize = 0;
4249                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4250                             let expr4_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4251                             let expr5_0 = C::output(ctx, expr4_0);
4252                             return Some(expr5_0);
4253                         }
4254                         &Opcode::Ushr => {
4255                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4256                             // Rule at src/isa/aarch64/lower.isle line 748.
4257                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4258                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4259                             let expr2_0: usize = 0;
4260                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4261                             let expr4_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4262                             let expr5_0 = C::output(ctx, expr4_0);
4263                             return Some(expr5_0);
4264                         }
4265                         &Opcode::Sshr => {
4266                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4267                             // Rule at src/isa/aarch64/lower.isle line 795.
4268                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4269                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4270                             let expr2_0: usize = 0;
4271                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4272                             let expr4_0 = constructor_lower_sshr128(ctx, expr0_0, expr3_0)?;
4273                             let expr5_0 = C::output(ctx, expr4_0);
4274                             return Some(expr5_0);
4275                         }
4276                         _ => {}
4277                     }
4278                 }
4279                 &InstructionData::Unary {
4280                     opcode: ref pattern5_0,
4281                     arg: pattern5_1,
4282                 } => {
4283                     match pattern5_0 {
4284                         &Opcode::Bnot => {
4285                             // Rule at src/isa/aarch64/lower.isle line 569.
4286                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4287                             let expr1_0: usize = 0;
4288                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4289                             let expr3_0: usize = 1;
4290                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4291                             let expr5_0: Type = I64;
4292                             let expr6_0 = C::zero_reg(ctx);
4293                             let expr7_0 = constructor_orr_not(ctx, expr5_0, expr6_0, expr2_0)?;
4294                             let expr8_0: Type = I64;
4295                             let expr9_0 = C::zero_reg(ctx);
4296                             let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, expr4_0)?;
4297                             let expr11_0 = C::value_regs(ctx, expr7_0, expr10_0);
4298                             let expr12_0 = C::output(ctx, expr11_0);
4299                             return Some(expr12_0);
4300                         }
4301                         &Opcode::Bitrev => {
4302                             // Rule at src/isa/aarch64/lower.isle line 983.
4303                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4304                             let expr1_0: Type = I64;
4305                             let expr2_0: usize = 0;
4306                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4307                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4308                             let expr5_0: Type = I64;
4309                             let expr6_0: usize = 1;
4310                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4311                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4312                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4313                             let expr10_0 = C::output(ctx, expr9_0);
4314                             return Some(expr10_0);
4315                         }
4316                         &Opcode::Clz => {
4317                             // Rule at src/isa/aarch64/lower.isle line 1001.
4318                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4319                             let expr1_0 = constructor_lower_clz128(ctx, expr0_0)?;
4320                             let expr2_0 = C::output(ctx, expr1_0);
4321                             return Some(expr2_0);
4322                         }
4323                         &Opcode::Cls => {
4324                             // Rule at src/isa/aarch64/lower.isle line 1057.
4325                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4326                             let expr1_0: usize = 0;
4327                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4328                             let expr3_0: usize = 1;
4329                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4330                             let expr5_0: Type = I64;
4331                             let expr6_0 = constructor_a64_cls(ctx, expr5_0, expr2_0)?;
4332                             let expr7_0: Type = I64;
4333                             let expr8_0 = constructor_a64_cls(ctx, expr7_0, expr4_0)?;
4334                             let expr9_0: Type = I64;
4335                             let expr10_0 = constructor_eon(ctx, expr9_0, expr4_0, expr2_0)?;
4336                             let expr11_0: Type = I64;
4337                             let expr12_0: u8 = 63;
4338                             let expr13_0 = C::imm_shift_from_u8(ctx, expr12_0);
4339                             let expr14_0 = constructor_lsr_imm(ctx, expr11_0, expr10_0, expr13_0)?;
4340                             let expr15_0 = constructor_madd64(ctx, expr6_0, expr14_0, expr14_0)?;
4341                             let expr16_0: u8 = 63;
4342                             let expr17_0 = C::u8_into_imm12(ctx, expr16_0);
4343                             let expr18_0 = constructor_cmp64_imm(ctx, expr8_0, expr17_0)?;
4344                             let expr19_0 = Cond::Eq;
4345                             let expr20_0 = C::zero_reg(ctx);
4346                             let expr21_0 = constructor_csel(ctx, &expr19_0, expr15_0, expr20_0)?;
4347                             let expr22_0 = constructor_with_flags_reg(ctx, &expr18_0, &expr21_0)?;
4348                             let expr23_0: Type = I64;
4349                             let expr24_0 = constructor_add(ctx, expr23_0, expr22_0, expr8_0)?;
4350                             let expr25_0: Type = I64;
4351                             let expr26_0: u64 = 0;
4352                             let expr27_0 = constructor_imm(ctx, expr25_0, expr26_0)?;
4353                             let expr28_0 = C::value_regs(ctx, expr24_0, expr27_0);
4354                             let expr29_0 = C::output(ctx, expr28_0);
4355                             return Some(expr29_0);
4356                         }
4357                         &Opcode::Ctz => {
4358                             // Rule at src/isa/aarch64/lower.isle line 1031.
4359                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4360                             let expr1_0: Type = I64;
4361                             let expr2_0: usize = 0;
4362                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4363                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4364                             let expr5_0: Type = I64;
4365                             let expr6_0: usize = 1;
4366                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4367                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4368                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4369                             let expr10_0 = constructor_lower_clz128(ctx, expr9_0)?;
4370                             let expr11_0 = C::output(ctx, expr10_0);
4371                             return Some(expr11_0);
4372                         }
4373                         &Opcode::Popcnt => {
4374                             // Rule at src/isa/aarch64/lower.isle line 1117.
4375                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4376                             let expr1_0: usize = 0;
4377                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4378                             let expr3_0 = ScalarSize::Size64;
4379                             let expr4_0 = constructor_mov_to_fpu(ctx, expr2_0, &expr3_0)?;
4380                             let expr5_0: usize = 1;
4381                             let expr6_0 = C::value_regs_get(ctx, expr0_0, expr5_0);
4382                             let expr7_0: u8 = 1;
4383                             let expr8_0 = VectorSize::Size64x2;
4384                             let expr9_0 =
4385                                 constructor_mov_to_vec(ctx, expr4_0, expr6_0, expr7_0, &expr8_0)?;
4386                             let expr10_0 = VectorSize::Size8x16;
4387                             let expr11_0 = constructor_vec_cnt(ctx, expr9_0, &expr10_0)?;
4388                             let expr12_0 = VectorSize::Size8x16;
4389                             let expr13_0 = constructor_addv(ctx, expr11_0, &expr12_0)?;
4390                             let expr14_0: u8 = 0;
4391                             let expr15_0 = VectorSize::Size8x16;
4392                             let expr16_0 =
4393                                 constructor_mov_from_vec(ctx, expr13_0, expr14_0, &expr15_0)?;
4394                             let expr17_0: Type = I64;
4395                             let expr18_0: u64 = 0;
4396                             let expr19_0 = constructor_imm(ctx, expr17_0, expr18_0)?;
4397                             let expr20_0 = C::value_regs(ctx, expr16_0, expr19_0);
4398                             let expr21_0 = C::output(ctx, expr20_0);
4399                             return Some(expr21_0);
4400                         }
4401                         &Opcode::Uextend => {
4402                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4403                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4404                                 if let &InstructionData::BinaryImm8 {
4405                                     opcode: ref pattern9_0,
4406                                     arg: pattern9_1,
4407                                     imm: pattern9_2,
4408                                 } = &pattern8_0
4409                                 {
4410                                     if let &Opcode::Extractlane = pattern9_0 {
4411                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4412                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
4413                                         // Rule at src/isa/aarch64/lower.isle line 499.
4414                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4415                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
4416                                         let expr2_0 = constructor_mov_from_vec(
4417                                             ctx,
4418                                             expr0_0,
4419                                             pattern12_0,
4420                                             &expr1_0,
4421                                         )?;
4422                                         let expr3_0: Type = I64;
4423                                         let expr4_0: u64 = 0;
4424                                         let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
4425                                         let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
4426                                         let expr7_0 = C::output(ctx, expr6_0);
4427                                         return Some(expr7_0);
4428                                     }
4429                                 }
4430                             }
4431                             // Rule at src/isa/aarch64/lower.isle line 494.
4432                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
4433                             let expr1_0: Type = I64;
4434                             let expr2_0: u64 = 0;
4435                             let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
4436                             let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
4437                             let expr5_0 = C::output(ctx, expr4_0);
4438                             return Some(expr5_0);
4439                         }
4440                         &Opcode::Sextend => {
4441                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4442                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4443                                 if let &InstructionData::BinaryImm8 {
4444                                     opcode: ref pattern9_0,
4445                                     arg: pattern9_1,
4446                                     imm: pattern9_2,
4447                                 } = &pattern8_0
4448                                 {
4449                                     if let &Opcode::Extractlane = pattern9_0 {
4450                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4451                                         if pattern11_0 == I64X2 {
4452                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4453                                             // Rule at src/isa/aarch64/lower.isle line 543.
4454                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4455                                             let expr1_0 = VectorSize::Size64x2;
4456                                             let expr2_0 = constructor_mov_from_vec(
4457                                                 ctx,
4458                                                 expr0_0,
4459                                                 pattern13_0,
4460                                                 &expr1_0,
4461                                             )?;
4462                                             let expr3_0: Type = I64;
4463                                             let expr4_0: u8 = 63;
4464                                             let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
4465                                             let expr6_0 = constructor_asr_imm(
4466                                                 ctx, expr3_0, expr2_0, expr5_0,
4467                                             )?;
4468                                             let expr7_0 = C::value_regs(ctx, expr2_0, expr6_0);
4469                                             let expr8_0 = C::output(ctx, expr7_0);
4470                                             return Some(expr8_0);
4471                                         }
4472                                         if let Some(()) = C::not_i64x2(ctx, pattern11_0) {
4473                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4474                                             // Rule at src/isa/aarch64/lower.isle line 532.
4475                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4476                                             let expr1_0 =
4477                                                 constructor_vector_size(ctx, pattern11_0)?;
4478                                             let expr2_0: Type = I64;
4479                                             let expr3_0 = constructor_size_from_ty(ctx, expr2_0)?;
4480                                             let expr4_0 = constructor_mov_from_vec_signed(
4481                                                 ctx,
4482                                                 expr0_0,
4483                                                 pattern13_0,
4484                                                 &expr1_0,
4485                                                 &expr3_0,
4486                                             )?;
4487                                             let expr5_0: Type = I64;
4488                                             let expr6_0: u8 = 63;
4489                                             let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
4490                                             let expr8_0 = constructor_asr_imm(
4491                                                 ctx, expr5_0, expr4_0, expr7_0,
4492                                             )?;
4493                                             let expr9_0 = C::value_regs(ctx, expr4_0, expr8_0);
4494                                             let expr10_0 = C::output(ctx, expr9_0);
4495                                             return Some(expr10_0);
4496                                         }
4497                                     }
4498                                 }
4499                             }
4500                             // Rule at src/isa/aarch64/lower.isle line 522.
4501                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
4502                             let expr1_0: Type = I64;
4503                             let expr2_0: u8 = 63;
4504                             let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0);
4505                             let expr4_0 = constructor_asr_imm(ctx, expr1_0, expr0_0, expr3_0)?;
4506                             let expr5_0 = C::value_regs(ctx, expr0_0, expr4_0);
4507                             let expr6_0 = C::output(ctx, expr5_0);
4508                             return Some(expr6_0);
4509                         }
4510                         _ => {}
4511                     }
4512                 }
4513                 _ => {}
4514             }
4515         }
4516         if pattern2_0 == I8X16 {
4517             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4518             if let &InstructionData::Unary {
4519                 opcode: ref pattern5_0,
4520                 arg: pattern5_1,
4521             } = &pattern4_0
4522             {
4523                 if let &Opcode::Popcnt = pattern5_0 {
4524                     // Rule at src/isa/aarch64/lower.isle line 1125.
4525                     let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4526                     let expr1_0 = VectorSize::Size8x16;
4527                     let expr2_0 = constructor_vec_cnt(ctx, expr0_0, &expr1_0)?;
4528                     let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4529                     return Some(expr3_0);
4530                 }
4531             }
4532         }
4533         if pattern2_0 == I16X8 {
4534             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4535             if let &InstructionData::Binary {
4536                 opcode: ref pattern5_0,
4537                 args: ref pattern5_1,
4538             } = &pattern4_0
4539             {
4540                 if let &Opcode::Imul = pattern5_0 {
4541                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4542                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4543                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4544                         if let &InstructionData::Unary {
4545                             opcode: ref pattern10_0,
4546                             arg: pattern10_1,
4547                         } = &pattern9_0
4548                         {
4549                             match pattern10_0 {
4550                                 &Opcode::SwidenLow => {
4551                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4552                                     if pattern12_0 == I8X16 {
4553                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4554                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4555                                             if let &InstructionData::Unary {
4556                                                 opcode: ref pattern16_0,
4557                                                 arg: pattern16_1,
4558                                             } = &pattern15_0
4559                                             {
4560                                                 if let &Opcode::SwidenLow = pattern16_0 {
4561                                                     let pattern18_0 =
4562                                                         C::value_type(ctx, pattern16_1);
4563                                                     if pattern18_0 == I8X16 {
4564                                                         // Rule at src/isa/aarch64/lower.isle line 282.
4565                                                         let expr0_0 =
4566                                                             C::put_in_reg(ctx, pattern10_1);
4567                                                         let expr1_0 =
4568                                                             C::put_in_reg(ctx, pattern16_1);
4569                                                         let expr2_0: bool = false;
4570                                                         let expr3_0 = constructor_smull8(
4571                                                             ctx, expr0_0, expr1_0, expr2_0,
4572                                                         )?;
4573                                                         let expr4_0 =
4574                                                             constructor_output_reg(ctx, expr3_0)?;
4575                                                         return Some(expr4_0);
4576                                                     }
4577                                                 }
4578                                             }
4579                                         }
4580                                     }
4581                                 }
4582                                 &Opcode::SwidenHigh => {
4583                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4584                                     if pattern12_0 == I8X16 {
4585                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4586                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4587                                             if let &InstructionData::Unary {
4588                                                 opcode: ref pattern16_0,
4589                                                 arg: pattern16_1,
4590                                             } = &pattern15_0
4591                                             {
4592                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4593                                                     let pattern18_0 =
4594                                                         C::value_type(ctx, pattern16_1);
4595                                                     if pattern18_0 == I8X16 {
4596                                                         // Rule at src/isa/aarch64/lower.isle line 288.
4597                                                         let expr0_0 =
4598                                                             C::put_in_reg(ctx, pattern10_1);
4599                                                         let expr1_0 =
4600                                                             C::put_in_reg(ctx, pattern16_1);
4601                                                         let expr2_0: bool = true;
4602                                                         let expr3_0 = constructor_smull8(
4603                                                             ctx, expr0_0, expr1_0, expr2_0,
4604                                                         )?;
4605                                                         let expr4_0 =
4606                                                             constructor_output_reg(ctx, expr3_0)?;
4607                                                         return Some(expr4_0);
4608                                                     }
4609                                                 }
4610                                             }
4611                                         }
4612                                     }
4613                                 }
4614                                 &Opcode::UwidenLow => {
4615                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4616                                     if pattern12_0 == I8X16 {
4617                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4618                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4619                                             if let &InstructionData::Unary {
4620                                                 opcode: ref pattern16_0,
4621                                                 arg: pattern16_1,
4622                                             } = &pattern15_0
4623                                             {
4624                                                 if let &Opcode::UwidenLow = pattern16_0 {
4625                                                     let pattern18_0 =
4626                                                         C::value_type(ctx, pattern16_1);
4627                                                     if pattern18_0 == I8X16 {
4628                                                         // Rule at src/isa/aarch64/lower.isle line 294.
4629                                                         let expr0_0 =
4630                                                             C::put_in_reg(ctx, pattern10_1);
4631                                                         let expr1_0 =
4632                                                             C::put_in_reg(ctx, pattern16_1);
4633                                                         let expr2_0: bool = false;
4634                                                         let expr3_0 = constructor_umull8(
4635                                                             ctx, expr0_0, expr1_0, expr2_0,
4636                                                         )?;
4637                                                         let expr4_0 =
4638                                                             constructor_output_reg(ctx, expr3_0)?;
4639                                                         return Some(expr4_0);
4640                                                     }
4641                                                 }
4642                                             }
4643                                         }
4644                                     }
4645                                 }
4646                                 &Opcode::UwidenHigh => {
4647                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4648                                     if pattern12_0 == I8X16 {
4649                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4650                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4651                                             if let &InstructionData::Unary {
4652                                                 opcode: ref pattern16_0,
4653                                                 arg: pattern16_1,
4654                                             } = &pattern15_0
4655                                             {
4656                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4657                                                     let pattern18_0 =
4658                                                         C::value_type(ctx, pattern16_1);
4659                                                     if pattern18_0 == I8X16 {
4660                                                         // Rule at src/isa/aarch64/lower.isle line 300.
4661                                                         let expr0_0 =
4662                                                             C::put_in_reg(ctx, pattern10_1);
4663                                                         let expr1_0 =
4664                                                             C::put_in_reg(ctx, pattern16_1);
4665                                                         let expr2_0: bool = true;
4666                                                         let expr3_0 = constructor_umull8(
4667                                                             ctx, expr0_0, expr1_0, expr2_0,
4668                                                         )?;
4669                                                         let expr4_0 =
4670                                                             constructor_output_reg(ctx, expr3_0)?;
4671                                                         return Some(expr4_0);
4672                                                     }
4673                                                 }
4674                                             }
4675                                         }
4676                                     }
4677                                 }
4678                                 _ => {}
4679                             }
4680                         }
4681                     }
4682                 }
4683             }
4684         }
4685         if pattern2_0 == I32X4 {
4686             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4687             if let &InstructionData::Binary {
4688                 opcode: ref pattern5_0,
4689                 args: ref pattern5_1,
4690             } = &pattern4_0
4691             {
4692                 if let &Opcode::Imul = pattern5_0 {
4693                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4694                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4695                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4696                         if let &InstructionData::Unary {
4697                             opcode: ref pattern10_0,
4698                             arg: pattern10_1,
4699                         } = &pattern9_0
4700                         {
4701                             match pattern10_0 {
4702                                 &Opcode::SwidenLow => {
4703                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4704                                     if pattern12_0 == I16X8 {
4705                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4706                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4707                                             if let &InstructionData::Unary {
4708                                                 opcode: ref pattern16_0,
4709                                                 arg: pattern16_1,
4710                                             } = &pattern15_0
4711                                             {
4712                                                 if let &Opcode::SwidenLow = pattern16_0 {
4713                                                     let pattern18_0 =
4714                                                         C::value_type(ctx, pattern16_1);
4715                                                     if pattern18_0 == I16X8 {
4716                                                         // Rule at src/isa/aarch64/lower.isle line 306.
4717                                                         let expr0_0 =
4718                                                             C::put_in_reg(ctx, pattern10_1);
4719                                                         let expr1_0 =
4720                                                             C::put_in_reg(ctx, pattern16_1);
4721                                                         let expr2_0: bool = false;
4722                                                         let expr3_0 = constructor_smull16(
4723                                                             ctx, expr0_0, expr1_0, expr2_0,
4724                                                         )?;
4725                                                         let expr4_0 =
4726                                                             constructor_output_reg(ctx, expr3_0)?;
4727                                                         return Some(expr4_0);
4728                                                     }
4729                                                 }
4730                                             }
4731                                         }
4732                                     }
4733                                 }
4734                                 &Opcode::SwidenHigh => {
4735                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4736                                     if pattern12_0 == I16X8 {
4737                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4738                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4739                                             if let &InstructionData::Unary {
4740                                                 opcode: ref pattern16_0,
4741                                                 arg: pattern16_1,
4742                                             } = &pattern15_0
4743                                             {
4744                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4745                                                     let pattern18_0 =
4746                                                         C::value_type(ctx, pattern16_1);
4747                                                     if pattern18_0 == I16X8 {
4748                                                         // Rule at src/isa/aarch64/lower.isle line 312.
4749                                                         let expr0_0 =
4750                                                             C::put_in_reg(ctx, pattern10_1);
4751                                                         let expr1_0 =
4752                                                             C::put_in_reg(ctx, pattern16_1);
4753                                                         let expr2_0: bool = true;
4754                                                         let expr3_0 = constructor_smull16(
4755                                                             ctx, expr0_0, expr1_0, expr2_0,
4756                                                         )?;
4757                                                         let expr4_0 =
4758                                                             constructor_output_reg(ctx, expr3_0)?;
4759                                                         return Some(expr4_0);
4760                                                     }
4761                                                 }
4762                                             }
4763                                         }
4764                                     }
4765                                 }
4766                                 &Opcode::UwidenLow => {
4767                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4768                                     if pattern12_0 == I16X8 {
4769                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4770                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4771                                             if let &InstructionData::Unary {
4772                                                 opcode: ref pattern16_0,
4773                                                 arg: pattern16_1,
4774                                             } = &pattern15_0
4775                                             {
4776                                                 if let &Opcode::UwidenLow = pattern16_0 {
4777                                                     let pattern18_0 =
4778                                                         C::value_type(ctx, pattern16_1);
4779                                                     if pattern18_0 == I16X8 {
4780                                                         // Rule at src/isa/aarch64/lower.isle line 318.
4781                                                         let expr0_0 =
4782                                                             C::put_in_reg(ctx, pattern10_1);
4783                                                         let expr1_0 =
4784                                                             C::put_in_reg(ctx, pattern16_1);
4785                                                         let expr2_0: bool = false;
4786                                                         let expr3_0 = constructor_umull16(
4787                                                             ctx, expr0_0, expr1_0, expr2_0,
4788                                                         )?;
4789                                                         let expr4_0 =
4790                                                             constructor_output_reg(ctx, expr3_0)?;
4791                                                         return Some(expr4_0);
4792                                                     }
4793                                                 }
4794                                             }
4795                                         }
4796                                     }
4797                                 }
4798                                 &Opcode::UwidenHigh => {
4799                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4800                                     if pattern12_0 == I16X8 {
4801                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4802                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4803                                             if let &InstructionData::Unary {
4804                                                 opcode: ref pattern16_0,
4805                                                 arg: pattern16_1,
4806                                             } = &pattern15_0
4807                                             {
4808                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4809                                                     let pattern18_0 =
4810                                                         C::value_type(ctx, pattern16_1);
4811                                                     if pattern18_0 == I16X8 {
4812                                                         // Rule at src/isa/aarch64/lower.isle line 324.
4813                                                         let expr0_0 =
4814                                                             C::put_in_reg(ctx, pattern10_1);
4815                                                         let expr1_0 =
4816                                                             C::put_in_reg(ctx, pattern16_1);
4817                                                         let expr2_0: bool = true;
4818                                                         let expr3_0 = constructor_umull16(
4819                                                             ctx, expr0_0, expr1_0, expr2_0,
4820                                                         )?;
4821                                                         let expr4_0 =
4822                                                             constructor_output_reg(ctx, expr3_0)?;
4823                                                         return Some(expr4_0);
4824                                                     }
4825                                                 }
4826                                             }
4827                                         }
4828                                     }
4829                                 }
4830                                 _ => {}
4831                             }
4832                         }
4833                     }
4834                 }
4835             }
4836         }
4837         if pattern2_0 == I64X2 {
4838             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4839             if let &InstructionData::Binary {
4840                 opcode: ref pattern5_0,
4841                 args: ref pattern5_1,
4842             } = &pattern4_0
4843             {
4844                 if let &Opcode::Imul = pattern5_0 {
4845                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4846                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4847                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4848                         if let &InstructionData::Unary {
4849                             opcode: ref pattern10_0,
4850                             arg: pattern10_1,
4851                         } = &pattern9_0
4852                         {
4853                             match pattern10_0 {
4854                                 &Opcode::SwidenLow => {
4855                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4856                                     if pattern12_0 == I32X4 {
4857                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4858                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4859                                             if let &InstructionData::Unary {
4860                                                 opcode: ref pattern16_0,
4861                                                 arg: pattern16_1,
4862                                             } = &pattern15_0
4863                                             {
4864                                                 if let &Opcode::SwidenLow = pattern16_0 {
4865                                                     let pattern18_0 =
4866                                                         C::value_type(ctx, pattern16_1);
4867                                                     if pattern18_0 == I32X4 {
4868                                                         // Rule at src/isa/aarch64/lower.isle line 330.
4869                                                         let expr0_0 =
4870                                                             C::put_in_reg(ctx, pattern10_1);
4871                                                         let expr1_0 =
4872                                                             C::put_in_reg(ctx, pattern16_1);
4873                                                         let expr2_0: bool = false;
4874                                                         let expr3_0 = constructor_smull32(
4875                                                             ctx, expr0_0, expr1_0, expr2_0,
4876                                                         )?;
4877                                                         let expr4_0 =
4878                                                             constructor_output_reg(ctx, expr3_0)?;
4879                                                         return Some(expr4_0);
4880                                                     }
4881                                                 }
4882                                             }
4883                                         }
4884                                     }
4885                                 }
4886                                 &Opcode::SwidenHigh => {
4887                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4888                                     if pattern12_0 == I32X4 {
4889                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4890                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4891                                             if let &InstructionData::Unary {
4892                                                 opcode: ref pattern16_0,
4893                                                 arg: pattern16_1,
4894                                             } = &pattern15_0
4895                                             {
4896                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4897                                                     let pattern18_0 =
4898                                                         C::value_type(ctx, pattern16_1);
4899                                                     if pattern18_0 == I32X4 {
4900                                                         // Rule at src/isa/aarch64/lower.isle line 336.
4901                                                         let expr0_0 =
4902                                                             C::put_in_reg(ctx, pattern10_1);
4903                                                         let expr1_0 =
4904                                                             C::put_in_reg(ctx, pattern16_1);
4905                                                         let expr2_0: bool = true;
4906                                                         let expr3_0 = constructor_smull32(
4907                                                             ctx, expr0_0, expr1_0, expr2_0,
4908                                                         )?;
4909                                                         let expr4_0 =
4910                                                             constructor_output_reg(ctx, expr3_0)?;
4911                                                         return Some(expr4_0);
4912                                                     }
4913                                                 }
4914                                             }
4915                                         }
4916                                     }
4917                                 }
4918                                 &Opcode::UwidenLow => {
4919                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4920                                     if pattern12_0 == I32X4 {
4921                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4922                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4923                                             if let &InstructionData::Unary {
4924                                                 opcode: ref pattern16_0,
4925                                                 arg: pattern16_1,
4926                                             } = &pattern15_0
4927                                             {
4928                                                 if let &Opcode::UwidenLow = pattern16_0 {
4929                                                     let pattern18_0 =
4930                                                         C::value_type(ctx, pattern16_1);
4931                                                     if pattern18_0 == I32X4 {
4932                                                         // Rule at src/isa/aarch64/lower.isle line 342.
4933                                                         let expr0_0 =
4934                                                             C::put_in_reg(ctx, pattern10_1);
4935                                                         let expr1_0 =
4936                                                             C::put_in_reg(ctx, pattern16_1);
4937                                                         let expr2_0: bool = false;
4938                                                         let expr3_0 = constructor_umull32(
4939                                                             ctx, expr0_0, expr1_0, expr2_0,
4940                                                         )?;
4941                                                         let expr4_0 =
4942                                                             constructor_output_reg(ctx, expr3_0)?;
4943                                                         return Some(expr4_0);
4944                                                     }
4945                                                 }
4946                                             }
4947                                         }
4948                                     }
4949                                 }
4950                                 &Opcode::UwidenHigh => {
4951                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4952                                     if pattern12_0 == I32X4 {
4953                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4954                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4955                                             if let &InstructionData::Unary {
4956                                                 opcode: ref pattern16_0,
4957                                                 arg: pattern16_1,
4958                                             } = &pattern15_0
4959                                             {
4960                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4961                                                     let pattern18_0 =
4962                                                         C::value_type(ctx, pattern16_1);
4963                                                     if pattern18_0 == I32X4 {
4964                                                         // Rule at src/isa/aarch64/lower.isle line 348.
4965                                                         let expr0_0 =
4966                                                             C::put_in_reg(ctx, pattern10_1);
4967                                                         let expr1_0 =
4968                                                             C::put_in_reg(ctx, pattern16_1);
4969                                                         let expr2_0: bool = true;
4970                                                         let expr3_0 = constructor_umull32(
4971                                                             ctx, expr0_0, expr1_0, expr2_0,
4972                                                         )?;
4973                                                         let expr4_0 =
4974                                                             constructor_output_reg(ctx, expr3_0)?;
4975                                                         return Some(expr4_0);
4976                                                     }
4977                                                 }
4978                                             }
4979                                         }
4980                                     }
4981                                 }
4982                                 _ => {}
4983                             }
4984                         }
4985                     }
4986                     // Rule at src/isa/aarch64/lower.isle line 243.
4987                     let expr0_0 = C::put_in_reg(ctx, pattern7_0);
4988                     let expr1_0 = C::put_in_reg(ctx, pattern7_1);
4989                     let expr2_0 = VectorSize::Size32x4;
4990                     let expr3_0 = constructor_rev64(ctx, expr1_0, &expr2_0)?;
4991                     let expr4_0 = VectorSize::Size32x4;
4992                     let expr5_0 = constructor_mul(ctx, expr3_0, expr0_0, &expr4_0)?;
4993                     let expr6_0: bool = false;
4994                     let expr7_0 = constructor_xtn64(ctx, expr0_0, expr6_0)?;
4995                     let expr8_0 = VectorSize::Size32x4;
4996                     let expr9_0 = constructor_addp(ctx, expr5_0, expr5_0, &expr8_0)?;
4997                     let expr10_0: bool = false;
4998                     let expr11_0 = constructor_xtn64(ctx, expr1_0, expr10_0)?;
4999                     let expr12_0: bool = false;
5000                     let expr13_0 = constructor_shll32(ctx, expr9_0, expr12_0)?;
5001                     let expr14_0: bool = false;
5002                     let expr15_0 = constructor_umlal32(ctx, expr13_0, expr11_0, expr7_0, expr14_0)?;
5003                     let expr16_0 = constructor_output_reg(ctx, expr15_0)?;
5004                     return Some(expr16_0);
5005                 }
5006             }
5007         }
5008         let pattern3_0 = C::inst_data(ctx, pattern0_0);
5009         match &pattern3_0 {
5010             &InstructionData::NullAry {
5011                 opcode: ref pattern4_0,
5012             } => {
5013                 if let &Opcode::Null = pattern4_0 {
5014                     // Rule at src/isa/aarch64/lower.isle line 22.
5015                     let expr0_0: u64 = 0;
5016                     let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5017                     let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5018                     return Some(expr2_0);
5019                 }
5020             }
5021             &InstructionData::UnaryImm {
5022                 opcode: ref pattern4_0,
5023                 imm: pattern4_1,
5024             } => {
5025                 if let &Opcode::Iconst = pattern4_0 {
5026                     let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1);
5027                     // Rule at src/isa/aarch64/lower.isle line 9.
5028                     let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?;
5029                     let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
5030                     return Some(expr1_0);
5031                 }
5032             }
5033             &InstructionData::UnaryBool {
5034                 opcode: ref pattern4_0,
5035                 imm: pattern4_1,
5036             } => {
5037                 if let &Opcode::Bconst = pattern4_0 {
5038                     if pattern4_1 == true {
5039                         // Rule at src/isa/aarch64/lower.isle line 17.
5040                         let expr0_0: u64 = 1;
5041                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5042                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5043                         return Some(expr2_0);
5044                     }
5045                     if pattern4_1 == false {
5046                         // Rule at src/isa/aarch64/lower.isle line 14.
5047                         let expr0_0: u64 = 0;
5048                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5049                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5050                         return Some(expr2_0);
5051                     }
5052                 }
5053             }
5054             &InstructionData::Unary {
5055                 opcode: ref pattern4_0,
5056                 arg: pattern4_1,
5057             } => {
5058                 match pattern4_0 {
5059                     &Opcode::Bitrev => {
5060                         // Rule at src/isa/aarch64/lower.isle line 989.
5061                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5062                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5063                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5064                         return Some(expr2_0);
5065                     }
5066                     &Opcode::Clz => {
5067                         // Rule at src/isa/aarch64/lower.isle line 1004.
5068                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5069                         let expr1_0 = constructor_a64_clz(ctx, pattern2_0, expr0_0)?;
5070                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5071                         return Some(expr2_0);
5072                     }
5073                     &Opcode::Cls => {
5074                         // Rule at src/isa/aarch64/lower.isle line 1071.
5075                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5076                         let expr1_0 = constructor_a64_cls(ctx, pattern2_0, expr0_0)?;
5077                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5078                         return Some(expr2_0);
5079                     }
5080                     &Opcode::Ctz => {
5081                         // Rule at src/isa/aarch64/lower.isle line 1037.
5082                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5083                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5084                         let expr2_0 = constructor_a64_clz(ctx, pattern2_0, expr1_0)?;
5085                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5086                         return Some(expr3_0);
5087                     }
5088                     _ => {}
5089                 }
5090             }
5091             _ => {}
5092         }
5093         if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) {
5094             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5095             if let &InstructionData::Binary {
5096                 opcode: ref pattern5_0,
5097                 args: ref pattern5_1,
5098             } = &pattern4_0
5099             {
5100                 match pattern5_0 {
5101                     &Opcode::Iadd => {
5102                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5103                         // Rule at src/isa/aarch64/lower.isle line 75.
5104                         let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5105                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5106                         let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5107                         let expr3_0 = constructor_add_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5108                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5109                         return Some(expr4_0);
5110                     }
5111                     &Opcode::Isub => {
5112                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5113                         // Rule at src/isa/aarch64/lower.isle line 125.
5114                         let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5115                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5116                         let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5117                         let expr3_0 = constructor_sub_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5118                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5119                         return Some(expr4_0);
5120                     }
5121                     _ => {}
5122                 }
5123             }
5124         }
5125         if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
5126             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5127             if let &InstructionData::Binary {
5128                 opcode: ref pattern5_0,
5129                 args: ref pattern5_1,
5130             } = &pattern4_0
5131             {
5132                 match pattern5_0 {
5133                     &Opcode::Rotl => {
5134                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5135                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5136                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5137                             if let &InstructionData::UnaryImm {
5138                                 opcode: ref pattern10_0,
5139                                 imm: pattern10_1,
5140                             } = &pattern9_0
5141                             {
5142                                 if let &Opcode::Iconst = pattern10_0 {
5143                                     let closure12 = || {
5144                                         return Some(pattern3_0);
5145                                     };
5146                                     if let Some(pattern12_0) = closure12() {
5147                                         if let Some(pattern13_0) =
5148                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5149                                         {
5150                                             // Rule at src/isa/aarch64/lower.isle line 843.
5151                                             let expr0_0 =
5152                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5153                                             let expr1_0 =
5154                                                 C::negate_imm_shift(ctx, pattern3_0, pattern13_0);
5155                                             let expr2_0 = constructor_small_rotr_imm(
5156                                                 ctx, pattern3_0, expr0_0, expr1_0,
5157                                             )?;
5158                                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5159                                             return Some(expr3_0);
5160                                         }
5161                                     }
5162                                 }
5163                             }
5164                         }
5165                         // Rule at src/isa/aarch64/lower.isle line 838.
5166                         let expr0_0: Type = I32;
5167                         let expr1_0 = C::zero_reg(ctx);
5168                         let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5169                         let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
5170                         let expr4_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5171                         let expr5_0 = constructor_small_rotr(ctx, pattern3_0, expr4_0, expr3_0)?;
5172                         let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
5173                         return Some(expr6_0);
5174                     }
5175                     &Opcode::Rotr => {
5176                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5177                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5178                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5179                             if let &InstructionData::UnaryImm {
5180                                 opcode: ref pattern10_0,
5181                                 imm: pattern10_1,
5182                             } = &pattern9_0
5183                             {
5184                                 if let &Opcode::Iconst = pattern10_0 {
5185                                     let closure12 = || {
5186                                         return Some(pattern3_0);
5187                                     };
5188                                     if let Some(pattern12_0) = closure12() {
5189                                         if let Some(pattern13_0) =
5190                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5191                                         {
5192                                             // Rule at src/isa/aarch64/lower.isle line 903.
5193                                             let expr0_0 =
5194                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5195                                             let expr1_0 = constructor_small_rotr_imm(
5196                                                 ctx,
5197                                                 pattern3_0,
5198                                                 expr0_0,
5199                                                 pattern13_0,
5200                                             )?;
5201                                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5202                                             return Some(expr2_0);
5203                                         }
5204                                     }
5205                                 }
5206                             }
5207                         }
5208                         // Rule at src/isa/aarch64/lower.isle line 891.
5209                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5210                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5211                         let expr2_0 = constructor_small_rotr(ctx, pattern3_0, expr0_0, expr1_0)?;
5212                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5213                         return Some(expr3_0);
5214                     }
5215                     _ => {}
5216                 }
5217             }
5218         }
5219         if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
5220             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5221             if let &InstructionData::Binary {
5222                 opcode: ref pattern5_0,
5223                 args: ref pattern5_1,
5224             } = &pattern4_0
5225             {
5226                 match pattern5_0 {
5227                     &Opcode::Umulhi => {
5228                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5229                         // Rule at src/isa/aarch64/lower.isle line 370.
5230                         let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5231                         let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?;
5232                         let expr2_0 = C::zero_reg(ctx);
5233                         let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
5234                         let expr4_0: Type = I64;
5235                         let expr5_0 = C::ty_bits(ctx, pattern3_0);
5236                         let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
5237                         let expr7_0 = constructor_lsr_imm(ctx, expr4_0, expr3_0, expr6_0)?;
5238                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
5239                         return Some(expr8_0);
5240                     }
5241                     &Opcode::Smulhi => {
5242                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5243                         // Rule at src/isa/aarch64/lower.isle line 358.
5244                         let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5245                         let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?;
5246                         let expr2_0 = C::zero_reg(ctx);
5247                         let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
5248                         let expr4_0: Type = I64;
5249                         let expr5_0 = C::ty_bits(ctx, pattern3_0);
5250                         let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
5251                         let expr7_0 = constructor_asr_imm(ctx, expr4_0, expr3_0, expr6_0)?;
5252                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
5253                         return Some(expr8_0);
5254                     }
5255                     &Opcode::Band => {
5256                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5257                         // Rule at src/isa/aarch64/lower.isle line 583.
5258                         let expr0_0 = ALUOp::And;
5259                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5260                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5261                         )?;
5262                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5263                         return Some(expr2_0);
5264                     }
5265                     &Opcode::Bor => {
5266                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5267                         // Rule at src/isa/aarch64/lower.isle line 596.
5268                         let expr0_0 = ALUOp::Orr;
5269                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5270                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5271                         )?;
5272                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5273                         return Some(expr2_0);
5274                     }
5275                     &Opcode::Bxor => {
5276                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5277                         // Rule at src/isa/aarch64/lower.isle line 609.
5278                         let expr0_0 = ALUOp::Eor;
5279                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5280                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5281                         )?;
5282                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5283                         return Some(expr2_0);
5284                     }
5285                     &Opcode::BandNot => {
5286                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5287                         // Rule at src/isa/aarch64/lower.isle line 622.
5288                         let expr0_0 = ALUOp::AndNot;
5289                         let expr1_0 = constructor_alu_rs_imm_logic(
5290                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5291                         )?;
5292                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5293                         return Some(expr2_0);
5294                     }
5295                     &Opcode::BorNot => {
5296                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5297                         // Rule at src/isa/aarch64/lower.isle line 635.
5298                         let expr0_0 = ALUOp::OrrNot;
5299                         let expr1_0 = constructor_alu_rs_imm_logic(
5300                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5301                         )?;
5302                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5303                         return Some(expr2_0);
5304                     }
5305                     &Opcode::BxorNot => {
5306                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5307                         // Rule at src/isa/aarch64/lower.isle line 645.
5308                         let expr0_0 = ALUOp::EorNot;
5309                         let expr1_0: Type = I32;
5310                         let expr2_0 = constructor_alu_rs_imm_logic(
5311                             ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
5312                         )?;
5313                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5314                         return Some(expr3_0);
5315                     }
5316                     &Opcode::Ishl => {
5317                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5318                         // Rule at src/isa/aarch64/lower.isle line 656.
5319                         let expr0_0 = ALUOp::Lsl;
5320                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
5321                         let expr2_0 =
5322                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5323                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5324                         return Some(expr3_0);
5325                     }
5326                     &Opcode::Ushr => {
5327                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5328                         // Rule at src/isa/aarch64/lower.isle line 740.
5329                         let expr0_0 = ALUOp::Lsr;
5330                         let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5331                         let expr2_0 =
5332                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5333                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5334                         return Some(expr3_0);
5335                     }
5336                     &Opcode::Sshr => {
5337                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5338                         // Rule at src/isa/aarch64/lower.isle line 787.
5339                         let expr0_0 = ALUOp::Asr;
5340                         let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
5341                         let expr2_0 =
5342                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5343                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5344                         return Some(expr3_0);
5345                     }
5346                     _ => {}
5347                 }
5348             }
5349         }
5350         if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
5351             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5352             match &pattern4_0 {
5353                 &InstructionData::Binary {
5354                     opcode: ref pattern5_0,
5355                     args: ref pattern5_1,
5356                 } => {
5357                     match pattern5_0 {
5358                         &Opcode::Iadd => {
5359                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5360                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5361                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5362                                 match &pattern9_0 {
5363                                     &InstructionData::UnaryImm {
5364                                         opcode: ref pattern10_0,
5365                                         imm: pattern10_1,
5366                                     } => {
5367                                         if let &Opcode::Iconst = pattern10_0 {
5368                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5369                                             if let Some(pattern13_0) =
5370                                                 C::imm12_from_u64(ctx, pattern12_0)
5371                                             {
5372                                                 // Rule at src/isa/aarch64/lower.isle line 37.
5373                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5374                                                 let expr1_0 = constructor_add_imm(
5375                                                     ctx,
5376                                                     pattern3_0,
5377                                                     expr0_0,
5378                                                     pattern13_0,
5379                                                 )?;
5380                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5381                                                 return Some(expr2_0);
5382                                             }
5383                                             if let Some(pattern13_0) =
5384                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5385                                             {
5386                                                 // Rule at src/isa/aarch64/lower.isle line 45.
5387                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5388                                                 let expr1_0 = constructor_sub_imm(
5389                                                     ctx,
5390                                                     pattern3_0,
5391                                                     expr0_0,
5392                                                     pattern13_0,
5393                                                 )?;
5394                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5395                                                 return Some(expr2_0);
5396                                             }
5397                                         }
5398                                     }
5399                                     &InstructionData::Binary {
5400                                         opcode: ref pattern10_0,
5401                                         args: ref pattern10_1,
5402                                     } => {
5403                                         match pattern10_0 {
5404                                             &Opcode::Imul => {
5405                                                 let (pattern12_0, pattern12_1) =
5406                                                     C::unpack_value_array_2(ctx, pattern10_1);
5407                                                 // Rule at src/isa/aarch64/lower.isle line 70.
5408                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5409                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5410                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5411                                                 let expr3_0 = constructor_madd(
5412                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5413                                                 )?;
5414                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5415                                                 return Some(expr4_0);
5416                                             }
5417                                             &Opcode::Ishl => {
5418                                                 let (pattern12_0, pattern12_1) =
5419                                                     C::unpack_value_array_2(ctx, pattern10_1);
5420                                                 if let Some(pattern13_0) =
5421                                                     C::def_inst(ctx, pattern12_1)
5422                                                 {
5423                                                     let pattern14_0 =
5424                                                         C::inst_data(ctx, pattern13_0);
5425                                                     if let &InstructionData::UnaryImm {
5426                                                         opcode: ref pattern15_0,
5427                                                         imm: pattern15_1,
5428                                                     } = &pattern14_0
5429                                                     {
5430                                                         if let &Opcode::Iconst = pattern15_0 {
5431                                                             let closure17 = || {
5432                                                                 return Some(pattern3_0);
5433                                                             };
5434                                                             if let Some(pattern17_0) = closure17() {
5435                                                                 if let Some(pattern18_0) =
5436                                                                     C::lshl_from_imm64(
5437                                                                         ctx,
5438                                                                         pattern15_1,
5439                                                                         pattern17_0,
5440                                                                     )
5441                                                                 {
5442                                                                     // Rule at src/isa/aarch64/lower.isle line 62.
5443                                                                     let expr0_0 = C::put_in_reg(
5444                                                                         ctx, pattern7_1,
5445                                                                     );
5446                                                                     let expr1_0 = C::put_in_reg(
5447                                                                         ctx,
5448                                                                         pattern12_0,
5449                                                                     );
5450                                                                     let expr2_0 =
5451                                                                         constructor_add_shift(
5452                                                                             ctx,
5453                                                                             pattern3_0,
5454                                                                             expr0_0,
5455                                                                             expr1_0,
5456                                                                             pattern18_0,
5457                                                                         )?;
5458                                                                     let expr3_0 =
5459                                                                         constructor_output_reg(
5460                                                                             ctx, expr2_0,
5461                                                                         )?;
5462                                                                     return Some(expr3_0);
5463                                                                 }
5464                                                             }
5465                                                         }
5466                                                     }
5467                                                 }
5468                                             }
5469                                             _ => {}
5470                                         }
5471                                     }
5472                                     _ => {}
5473                                 }
5474                             }
5475                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0)
5476                             {
5477                                 // Rule at src/isa/aarch64/lower.isle line 53.
5478                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5479                                 let expr1_0 =
5480                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5481                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5482                                 return Some(expr2_0);
5483                             }
5484                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5485                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5486                                 match &pattern9_0 {
5487                                     &InstructionData::UnaryImm {
5488                                         opcode: ref pattern10_0,
5489                                         imm: pattern10_1,
5490                                     } => {
5491                                         if let &Opcode::Iconst = pattern10_0 {
5492                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5493                                             if let Some(pattern13_0) =
5494                                                 C::imm12_from_u64(ctx, pattern12_0)
5495                                             {
5496                                                 // Rule at src/isa/aarch64/lower.isle line 34.
5497                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5498                                                 let expr1_0 = constructor_add_imm(
5499                                                     ctx,
5500                                                     pattern3_0,
5501                                                     expr0_0,
5502                                                     pattern13_0,
5503                                                 )?;
5504                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5505                                                 return Some(expr2_0);
5506                                             }
5507                                             if let Some(pattern13_0) =
5508                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5509                                             {
5510                                                 // Rule at src/isa/aarch64/lower.isle line 42.
5511                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5512                                                 let expr1_0 = constructor_sub_imm(
5513                                                     ctx,
5514                                                     pattern3_0,
5515                                                     expr0_0,
5516                                                     pattern13_0,
5517                                                 )?;
5518                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5519                                                 return Some(expr2_0);
5520                                             }
5521                                         }
5522                                     }
5523                                     &InstructionData::Binary {
5524                                         opcode: ref pattern10_0,
5525                                         args: ref pattern10_1,
5526                                     } => {
5527                                         match pattern10_0 {
5528                                             &Opcode::Imul => {
5529                                                 let (pattern12_0, pattern12_1) =
5530                                                     C::unpack_value_array_2(ctx, pattern10_1);
5531                                                 // Rule at src/isa/aarch64/lower.isle line 67.
5532                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5533                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5534                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
5535                                                 let expr3_0 = constructor_madd(
5536                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5537                                                 )?;
5538                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5539                                                 return Some(expr4_0);
5540                                             }
5541                                             &Opcode::Ishl => {
5542                                                 let (pattern12_0, pattern12_1) =
5543                                                     C::unpack_value_array_2(ctx, pattern10_1);
5544                                                 if let Some(pattern13_0) =
5545                                                     C::def_inst(ctx, pattern12_1)
5546                                                 {
5547                                                     let pattern14_0 =
5548                                                         C::inst_data(ctx, pattern13_0);
5549                                                     if let &InstructionData::UnaryImm {
5550                                                         opcode: ref pattern15_0,
5551                                                         imm: pattern15_1,
5552                                                     } = &pattern14_0
5553                                                     {
5554                                                         if let &Opcode::Iconst = pattern15_0 {
5555                                                             let closure17 = || {
5556                                                                 return Some(pattern3_0);
5557                                                             };
5558                                                             if let Some(pattern17_0) = closure17() {
5559                                                                 if let Some(pattern18_0) =
5560                                                                     C::lshl_from_imm64(
5561                                                                         ctx,
5562                                                                         pattern15_1,
5563                                                                         pattern17_0,
5564                                                                     )
5565                                                                 {
5566                                                                     // Rule at src/isa/aarch64/lower.isle line 58.
5567                                                                     let expr0_0 = C::put_in_reg(
5568                                                                         ctx, pattern7_0,
5569                                                                     );
5570                                                                     let expr1_0 = C::put_in_reg(
5571                                                                         ctx,
5572                                                                         pattern12_0,
5573                                                                     );
5574                                                                     let expr2_0 =
5575                                                                         constructor_add_shift(
5576                                                                             ctx,
5577                                                                             pattern3_0,
5578                                                                             expr0_0,
5579                                                                             expr1_0,
5580                                                                             pattern18_0,
5581                                                                         )?;
5582                                                                     let expr3_0 =
5583                                                                         constructor_output_reg(
5584                                                                             ctx, expr2_0,
5585                                                                         )?;
5586                                                                     return Some(expr3_0);
5587                                                                 }
5588                                                             }
5589                                                         }
5590                                                     }
5591                                                 }
5592                                             }
5593                                             _ => {}
5594                                         }
5595                                     }
5596                                     _ => {}
5597                                 }
5598                             }
5599                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
5600                             {
5601                                 // Rule at src/isa/aarch64/lower.isle line 50.
5602                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5603                                 let expr1_0 =
5604                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5605                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5606                                 return Some(expr2_0);
5607                             }
5608                             // Rule at src/isa/aarch64/lower.isle line 30.
5609                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5610                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5611                             let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, expr1_0)?;
5612                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5613                             return Some(expr3_0);
5614                         }
5615                         &Opcode::Isub => {
5616                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5617                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5618                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5619                                 match &pattern9_0 {
5620                                     &InstructionData::UnaryImm {
5621                                         opcode: ref pattern10_0,
5622                                         imm: pattern10_1,
5623                                     } => {
5624                                         if let &Opcode::Iconst = pattern10_0 {
5625                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5626                                             if let Some(pattern13_0) =
5627                                                 C::imm12_from_u64(ctx, pattern12_0)
5628                                             {
5629                                                 // Rule at src/isa/aarch64/lower.isle line 105.
5630                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5631                                                 let expr1_0 = constructor_sub_imm(
5632                                                     ctx,
5633                                                     pattern3_0,
5634                                                     expr0_0,
5635                                                     pattern13_0,
5636                                                 )?;
5637                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5638                                                 return Some(expr2_0);
5639                                             }
5640                                             if let Some(pattern13_0) =
5641                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5642                                             {
5643                                                 // Rule at src/isa/aarch64/lower.isle line 110.
5644                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5645                                                 let expr1_0 = constructor_add_imm(
5646                                                     ctx,
5647                                                     pattern3_0,
5648                                                     expr0_0,
5649                                                     pattern13_0,
5650                                                 )?;
5651                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5652                                                 return Some(expr2_0);
5653                                             }
5654                                         }
5655                                     }
5656                                     &InstructionData::Binary {
5657                                         opcode: ref pattern10_0,
5658                                         args: ref pattern10_1,
5659                                     } => {
5660                                         if let &Opcode::Ishl = pattern10_0 {
5661                                             let (pattern12_0, pattern12_1) =
5662                                                 C::unpack_value_array_2(ctx, pattern10_1);
5663                                             if let Some(pattern13_0) = C::def_inst(ctx, pattern12_1)
5664                                             {
5665                                                 let pattern14_0 = C::inst_data(ctx, pattern13_0);
5666                                                 if let &InstructionData::UnaryImm {
5667                                                     opcode: ref pattern15_0,
5668                                                     imm: pattern15_1,
5669                                                 } = &pattern14_0
5670                                                 {
5671                                                     if let &Opcode::Iconst = pattern15_0 {
5672                                                         let closure17 = || {
5673                                                             return Some(pattern3_0);
5674                                                         };
5675                                                         if let Some(pattern17_0) = closure17() {
5676                                                             if let Some(pattern18_0) =
5677                                                                 C::lshl_from_imm64(
5678                                                                     ctx,
5679                                                                     pattern15_1,
5680                                                                     pattern17_0,
5681                                                                 )
5682                                                             {
5683                                                                 // Rule at src/isa/aarch64/lower.isle line 120.
5684                                                                 let expr0_0 =
5685                                                                     C::put_in_reg(ctx, pattern7_0);
5686                                                                 let expr1_0 =
5687                                                                     C::put_in_reg(ctx, pattern12_0);
5688                                                                 let expr2_0 =
5689                                                                     constructor_sub_shift(
5690                                                                         ctx,
5691                                                                         pattern3_0,
5692                                                                         expr0_0,
5693                                                                         expr1_0,
5694                                                                         pattern18_0,
5695                                                                     )?;
5696                                                                 let expr3_0 =
5697                                                                     constructor_output_reg(
5698                                                                         ctx, expr2_0,
5699                                                                     )?;
5700                                                                 return Some(expr3_0);
5701                                                             }
5702                                                         }
5703                                                     }
5704                                                 }
5705                                             }
5706                                         }
5707                                     }
5708                                     _ => {}
5709                                 }
5710                             }
5711                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
5712                             {
5713                                 // Rule at src/isa/aarch64/lower.isle line 115.
5714                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5715                                 let expr1_0 =
5716                                     constructor_sub_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5717                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5718                                 return Some(expr2_0);
5719                             }
5720                             // Rule at src/isa/aarch64/lower.isle line 101.
5721                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5722                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5723                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
5724                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5725                             return Some(expr3_0);
5726                         }
5727                         &Opcode::Imul => {
5728                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5729                             // Rule at src/isa/aarch64/lower.isle line 179.
5730                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5731                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5732                             let expr2_0 = C::zero_reg(ctx);
5733                             let expr3_0 =
5734                                 constructor_madd(ctx, pattern3_0, expr0_0, expr1_0, expr2_0)?;
5735                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5736                             return Some(expr4_0);
5737                         }
5738                         &Opcode::Udiv => {
5739                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5740                             // Rule at src/isa/aarch64/lower.isle line 384.
5741                             let expr0_0: Type = I64;
5742                             let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5743                             let expr2_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
5744                             let expr3_0 = constructor_a64_udiv(ctx, expr0_0, expr1_0, expr2_0)?;
5745                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5746                             return Some(expr4_0);
5747                         }
5748                         &Opcode::Sdiv => {
5749                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5750                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5751                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5752                                 if let &InstructionData::UnaryImm {
5753                                     opcode: ref pattern10_0,
5754                                     imm: pattern10_1,
5755                                 } = &pattern9_0
5756                                 {
5757                                     if let &Opcode::Iconst = pattern10_0 {
5758                                         if let Some(pattern12_0) =
5759                                             C::safe_divisor_from_imm64(ctx, pattern10_1)
5760                                         {
5761                                             // Rule at src/isa/aarch64/lower.isle line 430.
5762                                             let expr0_0: Type = I64;
5763                                             let expr1_0 =
5764                                                 constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5765                                             let expr2_0 =
5766                                                 constructor_imm(ctx, pattern3_0, pattern12_0)?;
5767                                             let expr3_0 = constructor_a64_sdiv(
5768                                                 ctx, expr0_0, expr1_0, expr2_0,
5769                                             )?;
5770                                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5771                                             return Some(expr4_0);
5772                                         }
5773                                     }
5774                                 }
5775                             }
5776                             // Rule at src/isa/aarch64/lower.isle line 417.
5777                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5778                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
5779                             let expr2_0 = constructor_trap_if_div_overflow(
5780                                 ctx, pattern3_0, expr0_0, expr1_0,
5781                             )?;
5782                             let expr3_0: Type = I64;
5783                             let expr4_0 = constructor_a64_sdiv(ctx, expr3_0, expr2_0, expr1_0)?;
5784                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5785                             return Some(expr5_0);
5786                         }
5787                         &Opcode::Urem => {
5788                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5789                             // Rule at src/isa/aarch64/lower.isle line 458.
5790                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5791                             let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
5792                             let expr2_0: Type = I64;
5793                             let expr3_0 = constructor_a64_udiv(ctx, expr2_0, expr0_0, expr1_0)?;
5794                             let expr4_0 = constructor_msub64(ctx, expr3_0, expr1_0, expr0_0)?;
5795                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5796                             return Some(expr5_0);
5797                         }
5798                         &Opcode::Srem => {
5799                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5800                             // Rule at src/isa/aarch64/lower.isle line 465.
5801                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5802                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
5803                             let expr2_0: Type = I64;
5804                             let expr3_0 = constructor_a64_sdiv(ctx, expr2_0, expr0_0, expr1_0)?;
5805                             let expr4_0 = constructor_msub64(ctx, expr3_0, expr1_0, expr0_0)?;
5806                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5807                             return Some(expr5_0);
5808                         }
5809                         _ => {}
5810                     }
5811                 }
5812                 &InstructionData::Unary {
5813                     opcode: ref pattern5_0,
5814                     arg: pattern5_1,
5815                 } => {
5816                     match pattern5_0 {
5817                         &Opcode::Ineg => {
5818                             // Rule at src/isa/aarch64/lower.isle line 169.
5819                             let expr0_0 = C::zero_reg(ctx);
5820                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
5821                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
5822                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5823                             return Some(expr3_0);
5824                         }
5825                         &Opcode::Bnot => {
5826                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
5827                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
5828                                 if let &InstructionData::Binary {
5829                                     opcode: ref pattern9_0,
5830                                     args: ref pattern9_1,
5831                                 } = &pattern8_0
5832                                 {
5833                                     if let &Opcode::Ishl = pattern9_0 {
5834                                         let (pattern11_0, pattern11_1) =
5835                                             C::unpack_value_array_2(ctx, pattern9_1);
5836                                         if let Some(pattern12_0) = C::def_inst(ctx, pattern11_1) {
5837                                             let pattern13_0 = C::inst_data(ctx, pattern12_0);
5838                                             if let &InstructionData::UnaryImm {
5839                                                 opcode: ref pattern14_0,
5840                                                 imm: pattern14_1,
5841                                             } = &pattern13_0
5842                                             {
5843                                                 if let &Opcode::Iconst = pattern14_0 {
5844                                                     let closure16 = || {
5845                                                         return Some(pattern3_0);
5846                                                     };
5847                                                     if let Some(pattern16_0) = closure16() {
5848                                                         if let Some(pattern17_0) =
5849                                                             C::lshl_from_imm64(
5850                                                                 ctx,
5851                                                                 pattern14_1,
5852                                                                 pattern16_0,
5853                                                             )
5854                                                         {
5855                                                             // Rule at src/isa/aarch64/lower.isle line 564.
5856                                                             let expr0_0 = C::zero_reg(ctx);
5857                                                             let expr1_0 =
5858                                                                 C::put_in_reg(ctx, pattern11_0);
5859                                                             let expr2_0 =
5860                                                                 constructor_orr_not_shift(
5861                                                                     ctx,
5862                                                                     pattern3_0,
5863                                                                     expr0_0,
5864                                                                     expr1_0,
5865                                                                     pattern17_0,
5866                                                                 )?;
5867                                                             let expr3_0 = constructor_output_reg(
5868                                                                 ctx, expr2_0,
5869                                                             )?;
5870                                                             return Some(expr3_0);
5871                                                         }
5872                                                     }
5873                                                 }
5874                                             }
5875                                         }
5876                                     }
5877                                 }
5878                             }
5879                             // Rule at src/isa/aarch64/lower.isle line 559.
5880                             let expr0_0 = C::zero_reg(ctx);
5881                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
5882                             let expr2_0 = constructor_orr_not(ctx, pattern3_0, expr0_0, expr1_0)?;
5883                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5884                             return Some(expr3_0);
5885                         }
5886                         &Opcode::Uextend => {
5887                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
5888                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
5889                                 if let &InstructionData::BinaryImm8 {
5890                                     opcode: ref pattern9_0,
5891                                     arg: pattern9_1,
5892                                     imm: pattern9_2,
5893                                 } = &pattern8_0
5894                                 {
5895                                     if let &Opcode::Extractlane = pattern9_0 {
5896                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
5897                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
5898                                         // Rule at src/isa/aarch64/lower.isle line 481.
5899                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
5900                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
5901                                         let expr2_0 = constructor_mov_from_vec(
5902                                             ctx,
5903                                             expr0_0,
5904                                             pattern12_0,
5905                                             &expr1_0,
5906                                         )?;
5907                                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5908                                         return Some(expr3_0);
5909                                     }
5910                                 }
5911                             }
5912                             let pattern7_0 = C::value_type(ctx, pattern5_1);
5913                             if let Some(pattern8_0) = C::sinkable_atomic_load(ctx, pattern5_1) {
5914                                 // Rule at src/isa/aarch64/lower.isle line 488.
5915                                 let expr0_0 = C::sink_atomic_load(ctx, &pattern8_0);
5916                                 let expr1_0 = constructor_load_acquire(ctx, pattern7_0, expr0_0)?;
5917                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5918                                 return Some(expr2_0);
5919                             }
5920                             // Rule at src/isa/aarch64/lower.isle line 476.
5921                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
5922                             let expr1_0: bool = false;
5923                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
5924                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
5925                             let expr4_0 =
5926                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
5927                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5928                             return Some(expr5_0);
5929                         }
5930                         &Opcode::Sextend => {
5931                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
5932                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
5933                                 if let &InstructionData::BinaryImm8 {
5934                                     opcode: ref pattern9_0,
5935                                     arg: pattern9_1,
5936                                     imm: pattern9_2,
5937                                 } = &pattern8_0
5938                                 {
5939                                     if let &Opcode::Extractlane = pattern9_0 {
5940                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
5941                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
5942                                         // Rule at src/isa/aarch64/lower.isle line 513.
5943                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
5944                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
5945                                         let expr2_0 = constructor_size_from_ty(ctx, pattern3_0)?;
5946                                         let expr3_0 = constructor_mov_from_vec_signed(
5947                                             ctx,
5948                                             expr0_0,
5949                                             pattern12_0,
5950                                             &expr1_0,
5951                                             &expr2_0,
5952                                         )?;
5953                                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5954                                         return Some(expr4_0);
5955                                     }
5956                                 }
5957                             }
5958                             let pattern7_0 = C::value_type(ctx, pattern5_1);
5959                             // Rule at src/isa/aarch64/lower.isle line 508.
5960                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
5961                             let expr1_0: bool = true;
5962                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
5963                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
5964                             let expr4_0 =
5965                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
5966                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5967                             return Some(expr5_0);
5968                         }
5969                         _ => {}
5970                     }
5971                 }
5972                 _ => {}
5973             }
5974         }
5975         if let Some(pattern3_0) = C::vec128(ctx, pattern2_0) {
5976             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5977             match &pattern4_0 {
5978                 &InstructionData::Binary {
5979                     opcode: ref pattern5_0,
5980                     args: ref pattern5_1,
5981                 } => {
5982                     match pattern5_0 {
5983                         &Opcode::UaddSat => {
5984                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5985                             // Rule at src/isa/aarch64/lower.isle line 148.
5986                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5987                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5988                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5989                             let expr3_0 = constructor_uqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
5990                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5991                             return Some(expr4_0);
5992                         }
5993                         &Opcode::SaddSat => {
5994                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5995                             // Rule at src/isa/aarch64/lower.isle line 153.
5996                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5997                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5998                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5999                             let expr3_0 = constructor_sqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6000                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6001                             return Some(expr4_0);
6002                         }
6003                         &Opcode::UsubSat => {
6004                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6005                             // Rule at src/isa/aarch64/lower.isle line 158.
6006                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6007                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6008                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6009                             let expr3_0 = constructor_uqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6010                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6011                             return Some(expr4_0);
6012                         }
6013                         &Opcode::SsubSat => {
6014                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6015                             // Rule at src/isa/aarch64/lower.isle line 163.
6016                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6017                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6018                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6019                             let expr3_0 = constructor_sqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6020                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6021                             return Some(expr4_0);
6022                         }
6023                         &Opcode::Band => {
6024                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6025                             // Rule at src/isa/aarch64/lower.isle line 591.
6026                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6027                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6028                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6029                             let expr3_0 = constructor_and_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6030                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6031                             return Some(expr4_0);
6032                         }
6033                         &Opcode::Bor => {
6034                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6035                             // Rule at src/isa/aarch64/lower.isle line 604.
6036                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6037                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6038                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6039                             let expr3_0 = constructor_orr_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6040                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6041                             return Some(expr4_0);
6042                         }
6043                         &Opcode::Bxor => {
6044                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6045                             // Rule at src/isa/aarch64/lower.isle line 617.
6046                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6047                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6048                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6049                             let expr3_0 = constructor_eor_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6050                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6051                             return Some(expr4_0);
6052                         }
6053                         &Opcode::BandNot => {
6054                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6055                             // Rule at src/isa/aarch64/lower.isle line 630.
6056                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6057                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6058                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6059                             let expr3_0 = constructor_bic_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6060                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6061                             return Some(expr4_0);
6062                         }
6063                         &Opcode::Ishl => {
6064                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6065                             // Rule at src/isa/aarch64/lower.isle line 694.
6066                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6067                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6068                             let expr2_0 = constructor_vec_dup(ctx, expr1_0, &expr0_0)?;
6069                             let expr3_0 = C::put_in_reg(ctx, pattern7_0);
6070                             let expr4_0 = constructor_sshl(ctx, expr3_0, expr2_0, &expr0_0)?;
6071                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6072                             return Some(expr5_0);
6073                         }
6074                         &Opcode::Ushr => {
6075                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6076                             // Rule at src/isa/aarch64/lower.isle line 752.
6077                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6078                             let expr1_0: Type = I32;
6079                             let expr2_0 = C::zero_reg(ctx);
6080                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6081                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6082                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6083                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6084                             let expr7_0 = constructor_ushl(ctx, expr6_0, expr5_0, &expr0_0)?;
6085                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6086                             return Some(expr8_0);
6087                         }
6088                         &Opcode::Sshr => {
6089                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6090                             // Rule at src/isa/aarch64/lower.isle line 801.
6091                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6092                             let expr1_0: Type = I32;
6093                             let expr2_0 = C::zero_reg(ctx);
6094                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6095                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6096                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6097                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6098                             let expr7_0 = constructor_sshl(ctx, expr6_0, expr5_0, &expr0_0)?;
6099                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6100                             return Some(expr8_0);
6101                         }
6102                         _ => {}
6103                     }
6104                 }
6105                 &InstructionData::Unary {
6106                     opcode: ref pattern5_0,
6107                     arg: pattern5_1,
6108                 } => {
6109                     match pattern5_0 {
6110                         &Opcode::Ineg => {
6111                             // Rule at src/isa/aarch64/lower.isle line 173.
6112                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6113                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6114                             let expr2_0 = constructor_neg(ctx, expr0_0, &expr1_0)?;
6115                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6116                             return Some(expr3_0);
6117                         }
6118                         &Opcode::Bnot => {
6119                             // Rule at src/isa/aarch64/lower.isle line 578.
6120                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6121                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6122                             let expr2_0 = constructor_not(ctx, expr0_0, &expr1_0)?;
6123                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6124                             return Some(expr3_0);
6125                         }
6126                         _ => {}
6127                     }
6128                 }
6129                 _ => {}
6130             }
6131             if let Some(()) = C::not_i64x2(ctx, pattern3_0) {
6132                 let pattern5_0 = C::inst_data(ctx, pattern0_0);
6133                 if let &InstructionData::Binary {
6134                     opcode: ref pattern6_0,
6135                     args: ref pattern6_1,
6136                 } = &pattern5_0
6137                 {
6138                     if let &Opcode::Imul = pattern6_0 {
6139                         let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
6140                         // Rule at src/isa/aarch64/lower.isle line 211.
6141                         let expr0_0 = C::put_in_reg(ctx, pattern8_0);
6142                         let expr1_0 = C::put_in_reg(ctx, pattern8_1);
6143                         let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6144                         let expr3_0 = constructor_mul(ctx, expr0_0, expr1_0, &expr2_0)?;
6145                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6146                         return Some(expr4_0);
6147                     }
6148                 }
6149             }
6150         }
6151     }
6152     return None;
6153 }
6154 
6155 // Generated as internal constructor for term put_nonzero_in_reg_zext64.
6156 pub fn constructor_put_nonzero_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6157     let pattern0_0 = arg0;
6158     let pattern1_0 = C::value_type(ctx, pattern0_0);
6159     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6160         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6161         if let &InstructionData::UnaryImm {
6162             opcode: ref pattern4_0,
6163             imm: pattern4_1,
6164         } = &pattern3_0
6165         {
6166             if let &Opcode::Iconst = pattern4_0 {
6167                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6168                     // Rule at src/isa/aarch64/lower.isle line 394.
6169                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6170                     return Some(expr0_0);
6171                 }
6172             }
6173         }
6174     }
6175     // Rule at src/isa/aarch64/lower.isle line 389.
6176     let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern0_0)?;
6177     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6178     return Some(expr1_0);
6179 }
6180 
6181 // Generated as internal constructor for term put_nonzero_in_reg_sext64.
6182 pub fn constructor_put_nonzero_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6183     let pattern0_0 = arg0;
6184     let pattern1_0 = C::value_type(ctx, pattern0_0);
6185     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6186         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6187         if let &InstructionData::UnaryImm {
6188             opcode: ref pattern4_0,
6189             imm: pattern4_1,
6190         } = &pattern3_0
6191         {
6192             if let &Opcode::Iconst = pattern4_0 {
6193                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6194                     // Rule at src/isa/aarch64/lower.isle line 440.
6195                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6196                     return Some(expr0_0);
6197                 }
6198             }
6199         }
6200     }
6201     // Rule at src/isa/aarch64/lower.isle line 435.
6202     let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern0_0)?;
6203     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6204     return Some(expr1_0);
6205 }
6206 
6207 // Generated as internal constructor for term lower_shl128.
6208 pub fn constructor_lower_shl128<C: Context>(
6209     ctx: &mut C,
6210     arg0: ValueRegs,
6211     arg1: Reg,
6212 ) -> Option<ValueRegs> {
6213     let pattern0_0 = arg0;
6214     let pattern1_0 = arg1;
6215     // Rule at src/isa/aarch64/lower.isle line 677.
6216     let expr0_0: usize = 0;
6217     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6218     let expr2_0: usize = 1;
6219     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6220     let expr4_0: Type = I64;
6221     let expr5_0 = constructor_lsl(ctx, expr4_0, expr1_0, pattern1_0)?;
6222     let expr6_0: Type = I64;
6223     let expr7_0 = constructor_lsl(ctx, expr6_0, expr3_0, pattern1_0)?;
6224     let expr8_0: Type = I32;
6225     let expr9_0 = C::zero_reg(ctx);
6226     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6227     let expr11_0: Type = I64;
6228     let expr12_0: Type = I64;
6229     let expr13_0: u8 = 1;
6230     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6231     let expr15_0 = constructor_lsr_imm(ctx, expr12_0, expr1_0, expr14_0)?;
6232     let expr16_0 = constructor_lsr(ctx, expr11_0, expr15_0, expr10_0)?;
6233     let expr17_0: Type = I64;
6234     let expr18_0 = constructor_orr(ctx, expr17_0, expr7_0, expr16_0)?;
6235     let expr19_0: Type = I64;
6236     let expr20_0: Type = I64;
6237     let expr21_0: u64 = 64;
6238     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6239     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6240     let expr24_0 = Cond::Ne;
6241     let expr25_0 = C::zero_reg(ctx);
6242     let expr26_0 = constructor_csel(ctx, &expr24_0, expr25_0, expr5_0)?;
6243     let expr27_0 = Cond::Ne;
6244     let expr28_0 = constructor_csel(ctx, &expr27_0, expr5_0, expr18_0)?;
6245     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr26_0, &expr28_0)?;
6246     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6247     return Some(expr30_0);
6248 }
6249 
6250 // Generated as internal constructor for term do_shift.
6251 pub fn constructor_do_shift<C: Context>(
6252     ctx: &mut C,
6253     arg0: &ALUOp,
6254     arg1: Type,
6255     arg2: Reg,
6256     arg3: Value,
6257 ) -> Option<Reg> {
6258     let pattern0_0 = arg0;
6259     let pattern1_0 = arg1;
6260     let pattern2_0 = arg2;
6261     let pattern3_0 = arg3;
6262     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
6263         let pattern5_0 = C::inst_data(ctx, pattern4_0);
6264         if let &InstructionData::UnaryImm {
6265             opcode: ref pattern6_0,
6266             imm: pattern6_1,
6267         } = &pattern5_0
6268         {
6269             if let &Opcode::Iconst = pattern6_0 {
6270                 let closure8 = || {
6271                     return Some(pattern1_0);
6272                 };
6273                 if let Some(pattern8_0) = closure8() {
6274                     if let Some(pattern9_0) = C::imm_shift_from_imm64(ctx, pattern6_1, pattern8_0) {
6275                         // Rule at src/isa/aarch64/lower.isle line 734.
6276                         let expr0_0 = constructor_alu_rr_imm_shift(
6277                             ctx, pattern0_0, pattern1_0, pattern2_0, pattern9_0,
6278                         )?;
6279                         return Some(expr0_0);
6280                     }
6281                 }
6282             }
6283         }
6284     }
6285     let pattern0_0 = arg0;
6286     let pattern1_0 = arg1;
6287     if pattern1_0 == I32 {
6288         let pattern3_0 = arg2;
6289         let pattern4_0 = arg3;
6290         // Rule at src/isa/aarch64/lower.isle line 725.
6291         let expr0_0: Type = I32;
6292         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6293         let expr2_0: usize = 0;
6294         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6295         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6296         return Some(expr4_0);
6297     }
6298     if pattern1_0 == I64 {
6299         let pattern3_0 = arg2;
6300         let pattern4_0 = arg3;
6301         // Rule at src/isa/aarch64/lower.isle line 726.
6302         let expr0_0: Type = I64;
6303         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6304         let expr2_0: usize = 0;
6305         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6306         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6307         return Some(expr4_0);
6308     }
6309     if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
6310         let pattern3_0 = arg2;
6311         let pattern4_0 = arg3;
6312         // Rule at src/isa/aarch64/lower.isle line 716.
6313         let expr0_0 = C::put_in_regs(ctx, pattern4_0);
6314         let expr1_0: usize = 0;
6315         let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
6316         let expr3_0: Type = I32;
6317         let expr4_0 = C::shift_mask(ctx, pattern2_0);
6318         let expr5_0 = constructor_and_imm(ctx, expr3_0, expr2_0, expr4_0)?;
6319         let expr6_0: Type = I32;
6320         let expr7_0 = constructor_alu_rrr(ctx, pattern0_0, expr6_0, pattern3_0, expr5_0)?;
6321         return Some(expr7_0);
6322     }
6323     return None;
6324 }
6325 
6326 // Generated as internal constructor for term lower_ushr128.
6327 pub fn constructor_lower_ushr128<C: Context>(
6328     ctx: &mut C,
6329     arg0: ValueRegs,
6330     arg1: Reg,
6331 ) -> Option<ValueRegs> {
6332     let pattern0_0 = arg0;
6333     let pattern1_0 = arg1;
6334     // Rule at src/isa/aarch64/lower.isle line 767.
6335     let expr0_0: usize = 0;
6336     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6337     let expr2_0: usize = 1;
6338     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6339     let expr4_0: Type = I64;
6340     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6341     let expr6_0: Type = I64;
6342     let expr7_0 = constructor_lsr(ctx, expr6_0, expr3_0, pattern1_0)?;
6343     let expr8_0: Type = I32;
6344     let expr9_0 = C::zero_reg(ctx);
6345     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6346     let expr11_0: Type = I64;
6347     let expr12_0: Type = I64;
6348     let expr13_0: u8 = 1;
6349     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6350     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6351     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6352     let expr17_0: Type = I64;
6353     let expr18_0 = constructor_orr(ctx, expr17_0, expr5_0, expr16_0)?;
6354     let expr19_0: Type = I64;
6355     let expr20_0: Type = I64;
6356     let expr21_0: u64 = 64;
6357     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6358     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6359     let expr24_0 = Cond::Ne;
6360     let expr25_0 = constructor_csel(ctx, &expr24_0, expr7_0, expr18_0)?;
6361     let expr26_0 = Cond::Ne;
6362     let expr27_0 = C::zero_reg(ctx);
6363     let expr28_0 = constructor_csel(ctx, &expr26_0, expr27_0, expr7_0)?;
6364     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr25_0, &expr28_0)?;
6365     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6366     return Some(expr30_0);
6367 }
6368 
6369 // Generated as internal constructor for term lower_sshr128.
6370 pub fn constructor_lower_sshr128<C: Context>(
6371     ctx: &mut C,
6372     arg0: ValueRegs,
6373     arg1: Reg,
6374 ) -> Option<ValueRegs> {
6375     let pattern0_0 = arg0;
6376     let pattern1_0 = arg1;
6377     // Rule at src/isa/aarch64/lower.isle line 817.
6378     let expr0_0: usize = 0;
6379     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6380     let expr2_0: usize = 1;
6381     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6382     let expr4_0: Type = I64;
6383     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6384     let expr6_0: Type = I64;
6385     let expr7_0 = constructor_asr(ctx, expr6_0, expr3_0, pattern1_0)?;
6386     let expr8_0: Type = I32;
6387     let expr9_0 = C::zero_reg(ctx);
6388     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6389     let expr11_0: Type = I64;
6390     let expr12_0: Type = I64;
6391     let expr13_0: u8 = 1;
6392     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6393     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6394     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6395     let expr17_0: Type = I64;
6396     let expr18_0: u8 = 63;
6397     let expr19_0 = C::imm_shift_from_u8(ctx, expr18_0);
6398     let expr20_0 = constructor_asr_imm(ctx, expr17_0, expr3_0, expr19_0)?;
6399     let expr21_0: Type = I64;
6400     let expr22_0 = constructor_orr(ctx, expr21_0, expr5_0, expr16_0)?;
6401     let expr23_0: Type = I64;
6402     let expr24_0: Type = I64;
6403     let expr25_0: u64 = 64;
6404     let expr26_0 = C::u64_into_imm_logic(ctx, expr24_0, expr25_0);
6405     let expr27_0 = constructor_tst_imm(ctx, expr23_0, pattern1_0, expr26_0)?;
6406     let expr28_0 = Cond::Ne;
6407     let expr29_0 = constructor_csel(ctx, &expr28_0, expr7_0, expr22_0)?;
6408     let expr30_0 = Cond::Ne;
6409     let expr31_0 = constructor_csel(ctx, &expr30_0, expr20_0, expr7_0)?;
6410     let expr32_0 = constructor_consumes_flags_concat(ctx, &expr29_0, &expr31_0)?;
6411     let expr33_0 = constructor_with_flags(ctx, &expr27_0, &expr32_0)?;
6412     return Some(expr33_0);
6413 }
6414 
6415 // Generated as internal constructor for term small_rotr.
6416 pub fn constructor_small_rotr<C: Context>(
6417     ctx: &mut C,
6418     arg0: Type,
6419     arg1: Reg,
6420     arg2: Reg,
6421 ) -> Option<Reg> {
6422     let pattern0_0 = arg0;
6423     let pattern1_0 = arg1;
6424     let pattern2_0 = arg2;
6425     // Rule at src/isa/aarch64/lower.isle line 927.
6426     let expr0_0: Type = I32;
6427     let expr1_0 = C::rotr_mask(ctx, pattern0_0);
6428     let expr2_0 = constructor_and_imm(ctx, expr0_0, pattern2_0, expr1_0)?;
6429     let expr3_0: Type = I32;
6430     let expr4_0 = C::ty_bits(ctx, pattern0_0);
6431     let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
6432     let expr6_0 = constructor_sub_imm(ctx, expr3_0, expr2_0, expr5_0)?;
6433     let expr7_0: Type = I32;
6434     let expr8_0 = C::zero_reg(ctx);
6435     let expr9_0 = constructor_sub(ctx, expr7_0, expr8_0, expr6_0)?;
6436     let expr10_0: Type = I32;
6437     let expr11_0 = constructor_lsr(ctx, expr10_0, pattern1_0, expr2_0)?;
6438     let expr12_0: Type = I32;
6439     let expr13_0 = constructor_lsl(ctx, expr12_0, pattern1_0, expr9_0)?;
6440     let expr14_0: Type = I32;
6441     let expr15_0 = constructor_orr(ctx, expr14_0, expr13_0, expr11_0)?;
6442     return Some(expr15_0);
6443 }
6444 
6445 // Generated as internal constructor for term small_rotr_imm.
6446 pub fn constructor_small_rotr_imm<C: Context>(
6447     ctx: &mut C,
6448     arg0: Type,
6449     arg1: Reg,
6450     arg2: ImmShift,
6451 ) -> Option<Reg> {
6452     let pattern0_0 = arg0;
6453     let pattern1_0 = arg1;
6454     let pattern2_0 = arg2;
6455     // Rule at src/isa/aarch64/lower.isle line 948.
6456     let expr0_0: Type = I32;
6457     let expr1_0 = constructor_lsr_imm(ctx, expr0_0, pattern1_0, pattern2_0)?;
6458     let expr2_0: Type = I32;
6459     let expr3_0 = C::rotr_opposite_amount(ctx, pattern0_0, pattern2_0);
6460     let expr4_0 = constructor_lsl_imm(ctx, expr2_0, pattern1_0, expr3_0)?;
6461     let expr5_0: Type = I32;
6462     let expr6_0 = constructor_orr(ctx, expr5_0, expr4_0, expr1_0)?;
6463     return Some(expr6_0);
6464 }
6465 
6466 // Generated as internal constructor for term lower_clz128.
6467 pub fn constructor_lower_clz128<C: Context>(ctx: &mut C, arg0: ValueRegs) -> Option<ValueRegs> {
6468     let pattern0_0 = arg0;
6469     // Rule at src/isa/aarch64/lower.isle line 1013.
6470     let expr0_0: Type = I64;
6471     let expr1_0: usize = 1;
6472     let expr2_0 = C::value_regs_get(ctx, pattern0_0, expr1_0);
6473     let expr3_0 = constructor_a64_clz(ctx, expr0_0, expr2_0)?;
6474     let expr4_0: Type = I64;
6475     let expr5_0: usize = 0;
6476     let expr6_0 = C::value_regs_get(ctx, pattern0_0, expr5_0);
6477     let expr7_0 = constructor_a64_clz(ctx, expr4_0, expr6_0)?;
6478     let expr8_0: Type = I64;
6479     let expr9_0: u8 = 6;
6480     let expr10_0 = C::imm_shift_from_u8(ctx, expr9_0);
6481     let expr11_0 = constructor_lsr_imm(ctx, expr8_0, expr3_0, expr10_0)?;
6482     let expr12_0 = constructor_madd64(ctx, expr7_0, expr11_0, expr3_0)?;
6483     let expr13_0: Type = I64;
6484     let expr14_0: u64 = 0;
6485     let expr15_0 = constructor_imm(ctx, expr13_0, expr14_0)?;
6486     let expr16_0 = C::value_regs(ctx, expr12_0, expr15_0);
6487     return Some(expr16_0);
6488 }
6489