1 // GENERATED BY ISLE. DO NOT EDIT!
2 //
3 // Generated automatically from the instruction-selection DSL code in:
4 // - src/clif.isle
5 // - src/prelude.isle
6 // - src/isa/aarch64/inst.isle
7 // - src/isa/aarch64/lower.isle
8 
9 #![allow(dead_code, unreachable_code, unreachable_patterns)]
10 #![allow(unused_imports, unused_variables, non_snake_case)]
11 #![allow(irrefutable_let_patterns)]
12 
13 use super::*; // Pulls in all external types.
14 
15 /// Context during lowering: an implementation of this trait
16 /// must be provided with all external constructors and extractors.
17 /// A mutable borrow is passed along through all lowering logic.
18 pub trait Context {
19     fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
20     fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
21     fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
22     fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
23     fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
24     fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
25     fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
26     fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
27     fn value_regs_invalid(&mut self) -> ValueRegs;
28     fn output_none(&mut self) -> InstOutput;
29     fn output(&mut self, arg0: ValueRegs) -> InstOutput;
30     fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput;
31     fn output_builder_new(&mut self) -> InstOutputBuilder;
32     fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit;
33     fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput;
34     fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
35     fn invalid_reg(&mut self) -> Reg;
36     fn put_in_reg(&mut self, arg0: Value) -> Reg;
37     fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
38     fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
39     fn u8_as_u64(&mut self, arg0: u8) -> u64;
40     fn u16_as_u64(&mut self, arg0: u16) -> u64;
41     fn u32_as_u64(&mut self, arg0: u32) -> u64;
42     fn i64_as_u64(&mut self, arg0: i64) -> u64;
43     fn u64_add(&mut self, arg0: u64, arg1: u64) -> u64;
44     fn u64_sub(&mut self, arg0: u64, arg1: u64) -> u64;
45     fn u64_and(&mut self, arg0: u64, arg1: u64) -> u64;
46     fn ty_bits(&mut self, arg0: Type) -> u8;
47     fn ty_bits_u16(&mut self, arg0: Type) -> u16;
48     fn ty_bits_u64(&mut self, arg0: Type) -> u64;
49     fn ty_mask(&mut self, arg0: Type) -> u64;
50     fn ty_bytes(&mut self, arg0: Type) -> u16;
51     fn lane_type(&mut self, arg0: Type) -> Type;
52     fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
53     fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
54     fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
55     fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
56     fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
57     fn ty_int_bool_64(&mut self, arg0: Type) -> Option<Type>;
58     fn ty_int_bool_ref_64(&mut self, arg0: Type) -> Option<Type>;
59     fn ty_int_bool_128(&mut self, arg0: Type) -> Option<Type>;
60     fn ty_scalar_float(&mut self, arg0: Type) -> Option<Type>;
61     fn ty_vec128(&mut self, arg0: Type) -> Option<Type>;
62     fn ty_vec128_int(&mut self, arg0: Type) -> Option<Type>;
63     fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
64     fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
65     fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>;
66     fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>;
67     fn value_slice_len(&mut self, arg0: ValueSlice) -> usize;
68     fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value;
69     fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
70     fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
71     fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
72     fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
73     fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
74     fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
75     fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
76     fn first_result(&mut self, arg0: Inst) -> Option<Value>;
77     fn inst_data(&mut self, arg0: Inst) -> InstructionData;
78     fn value_type(&mut self, arg0: Value) -> Type;
79     fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
80     fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
81     fn offset32_to_u32(&mut self, arg0: Offset32) -> u32;
82     fn emit(&mut self, arg0: &MInst) -> Unit;
83     fn trap_code_division_by_zero(&mut self) -> TrapCode;
84     fn trap_code_integer_overflow(&mut self) -> TrapCode;
85     fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
86     fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
87     fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
88     fn symbol_value_data(
89         &mut self,
90         arg0: GlobalValue,
91     ) -> Option<(ExternalName, RelocDistance, i64)>;
92     fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
93     fn move_wide_const_from_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
94     fn move_wide_const_from_negated_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
95     fn imm_logic_from_u64(&mut self, arg0: u64, arg1: Type) -> Option<ImmLogic>;
96     fn imm_logic_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmLogic>;
97     fn imm_shift_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmShift>;
98     fn imm_shift_from_u8(&mut self, arg0: u8) -> ImmShift;
99     fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12>;
100     fn u8_into_uimm5(&mut self, arg0: u8) -> UImm5;
101     fn u8_into_imm12(&mut self, arg0: u8) -> Imm12;
102     fn u64_into_imm_logic(&mut self, arg0: Type, arg1: u64) -> ImmLogic;
103     fn imm12_from_negated_u64(&mut self, arg0: u64) -> Option<Imm12>;
104     fn lshl_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ShiftOpAndAmt>;
105     fn integral_ty(&mut self, arg0: Type) -> Option<Type>;
106     fn extended_value_from_value(&mut self, arg0: Value) -> Option<ExtendedValue>;
107     fn put_extended_in_reg(&mut self, arg0: &ExtendedValue) -> Reg;
108     fn get_extended_op(&mut self, arg0: &ExtendedValue) -> ExtendOp;
109     fn nzcv(&mut self, arg0: bool, arg1: bool, arg2: bool, arg3: bool) -> NZCV;
110     fn cond_br_zero(&mut self, arg0: Reg) -> CondBrKind;
111     fn cond_br_cond(&mut self, arg0: &Cond) -> CondBrKind;
112     fn zero_reg(&mut self) -> Reg;
113     fn writable_zero_reg(&mut self) -> WritableReg;
114     fn load_constant64_full(&mut self, arg0: u64) -> Reg;
115     fn sinkable_atomic_load(&mut self, arg0: Value) -> Option<SinkableAtomicLoad>;
116     fn sink_atomic_load(&mut self, arg0: &SinkableAtomicLoad) -> Reg;
117     fn zero_value_f32(&mut self, arg0: Ieee32) -> Option<Ieee32>;
118     fn zero_value_f64(&mut self, arg0: Ieee64) -> Option<Ieee64>;
119     fn float_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &FloatCC) -> VecMisc2;
120     fn float_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &FloatCC) -> VecMisc2;
121     fn fcmp_zero_cond(&mut self, arg0: &FloatCC) -> Option<FloatCC>;
122     fn fcmp_zero_cond_not_eq(&mut self, arg0: &FloatCC) -> Option<FloatCC>;
123     fn zero_value(&mut self, arg0: Imm64) -> Option<Imm64>;
124     fn int_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &IntCC) -> VecMisc2;
125     fn int_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &IntCC) -> VecMisc2;
126     fn icmp_zero_cond(&mut self, arg0: &IntCC) -> Option<IntCC>;
127     fn icmp_zero_cond_not_eq(&mut self, arg0: &IntCC) -> Option<IntCC>;
128     fn safe_divisor_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
129     fn shift_mask(&mut self, arg0: Type) -> ImmLogic;
130     fn negate_imm_shift(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
131     fn rotr_mask(&mut self, arg0: Type) -> ImmLogic;
132     fn rotr_opposite_amount(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
133 }
134 
135 /// Internal type SideEffectNoResult: defined at src/prelude.isle line 407.
136 #[derive(Clone, Debug)]
137 pub enum SideEffectNoResult {
138     Inst { inst: MInst },
139     Inst2 { inst1: MInst, inst2: MInst },
140 }
141 
142 /// Internal type ProducesFlags: defined at src/prelude.isle line 434.
143 #[derive(Clone, Debug)]
144 pub enum ProducesFlags {
145     ProducesFlagsSideEffect { inst: MInst },
146     ProducesFlagsReturnsReg { inst: MInst, result: Reg },
147     ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg },
148 }
149 
150 /// Internal type ConsumesFlags: defined at src/prelude.isle line 445.
151 #[derive(Clone, Debug)]
152 pub enum ConsumesFlags {
153     ConsumesFlagsReturnsResultWithProducer {
154         inst: MInst,
155         result: Reg,
156     },
157     ConsumesFlagsReturnsReg {
158         inst: MInst,
159         result: Reg,
160     },
161     ConsumesFlagsTwiceReturnsValueRegs {
162         inst1: MInst,
163         inst2: MInst,
164         result: ValueRegs,
165     },
166     ConsumesFlagsFourTimesReturnsValueRegs {
167         inst1: MInst,
168         inst2: MInst,
169         inst3: MInst,
170         inst4: MInst,
171         result: ValueRegs,
172     },
173 }
174 
175 /// Internal type MInst: defined at src/isa/aarch64/inst.isle line 2.
176 #[derive(Clone, Debug)]
177 pub enum MInst {
178     Nop0,
179     Nop4,
180     AluRRR {
181         alu_op: ALUOp,
182         size: OperandSize,
183         rd: WritableReg,
184         rn: Reg,
185         rm: Reg,
186     },
187     AluRRRR {
188         alu_op: ALUOp3,
189         size: OperandSize,
190         rd: WritableReg,
191         rn: Reg,
192         rm: Reg,
193         ra: Reg,
194     },
195     AluRRImm12 {
196         alu_op: ALUOp,
197         size: OperandSize,
198         rd: WritableReg,
199         rn: Reg,
200         imm12: Imm12,
201     },
202     AluRRImmLogic {
203         alu_op: ALUOp,
204         size: OperandSize,
205         rd: WritableReg,
206         rn: Reg,
207         imml: ImmLogic,
208     },
209     AluRRImmShift {
210         alu_op: ALUOp,
211         size: OperandSize,
212         rd: WritableReg,
213         rn: Reg,
214         immshift: ImmShift,
215     },
216     AluRRRShift {
217         alu_op: ALUOp,
218         size: OperandSize,
219         rd: WritableReg,
220         rn: Reg,
221         rm: Reg,
222         shiftop: ShiftOpAndAmt,
223     },
224     AluRRRExtend {
225         alu_op: ALUOp,
226         size: OperandSize,
227         rd: WritableReg,
228         rn: Reg,
229         rm: Reg,
230         extendop: ExtendOp,
231     },
232     BitRR {
233         op: BitOp,
234         size: OperandSize,
235         rd: WritableReg,
236         rn: Reg,
237     },
238     ULoad8 {
239         rd: WritableReg,
240         mem: AMode,
241         flags: MemFlags,
242     },
243     SLoad8 {
244         rd: WritableReg,
245         mem: AMode,
246         flags: MemFlags,
247     },
248     ULoad16 {
249         rd: WritableReg,
250         mem: AMode,
251         flags: MemFlags,
252     },
253     SLoad16 {
254         rd: WritableReg,
255         mem: AMode,
256         flags: MemFlags,
257     },
258     ULoad32 {
259         rd: WritableReg,
260         mem: AMode,
261         flags: MemFlags,
262     },
263     SLoad32 {
264         rd: WritableReg,
265         mem: AMode,
266         flags: MemFlags,
267     },
268     ULoad64 {
269         rd: WritableReg,
270         mem: AMode,
271         flags: MemFlags,
272     },
273     Store8 {
274         rd: Reg,
275         mem: AMode,
276         flags: MemFlags,
277     },
278     Store16 {
279         rd: Reg,
280         mem: AMode,
281         flags: MemFlags,
282     },
283     Store32 {
284         rd: Reg,
285         mem: AMode,
286         flags: MemFlags,
287     },
288     Store64 {
289         rd: Reg,
290         mem: AMode,
291         flags: MemFlags,
292     },
293     StoreP64 {
294         rt: Reg,
295         rt2: Reg,
296         mem: PairAMode,
297         flags: MemFlags,
298     },
299     LoadP64 {
300         rt: WritableReg,
301         rt2: WritableReg,
302         mem: PairAMode,
303         flags: MemFlags,
304     },
305     Mov {
306         size: OperandSize,
307         rd: WritableReg,
308         rm: Reg,
309     },
310     MovWide {
311         op: MoveWideOp,
312         rd: WritableReg,
313         imm: MoveWideConst,
314         size: OperandSize,
315     },
316     Extend {
317         rd: WritableReg,
318         rn: Reg,
319         signed: bool,
320         from_bits: u8,
321         to_bits: u8,
322     },
323     CSel {
324         rd: WritableReg,
325         cond: Cond,
326         rn: Reg,
327         rm: Reg,
328     },
329     CSet {
330         rd: WritableReg,
331         cond: Cond,
332     },
333     CSetm {
334         rd: WritableReg,
335         cond: Cond,
336     },
337     CCmpImm {
338         size: OperandSize,
339         rn: Reg,
340         imm: UImm5,
341         nzcv: NZCV,
342         cond: Cond,
343     },
344     AtomicRMWLoop {
345         ty: Type,
346         op: AtomicRmwOp,
347     },
348     AtomicRMW {
349         op: AtomicRMWOp,
350         rs: Reg,
351         rt: WritableReg,
352         rn: Reg,
353         ty: Type,
354     },
355     AtomicCAS {
356         rs: WritableReg,
357         rt: Reg,
358         rn: Reg,
359         ty: Type,
360     },
361     AtomicCASLoop {
362         ty: Type,
363     },
364     LoadAcquire {
365         access_ty: Type,
366         rt: WritableReg,
367         rn: Reg,
368     },
369     StoreRelease {
370         access_ty: Type,
371         rt: Reg,
372         rn: Reg,
373     },
374     Fence,
375     FpuMove64 {
376         rd: WritableReg,
377         rn: Reg,
378     },
379     FpuMove128 {
380         rd: WritableReg,
381         rn: Reg,
382     },
383     FpuMoveFromVec {
384         rd: WritableReg,
385         rn: Reg,
386         idx: u8,
387         size: VectorSize,
388     },
389     FpuExtend {
390         rd: WritableReg,
391         rn: Reg,
392         size: ScalarSize,
393     },
394     FpuRR {
395         fpu_op: FPUOp1,
396         size: ScalarSize,
397         rd: WritableReg,
398         rn: Reg,
399     },
400     FpuRRR {
401         fpu_op: FPUOp2,
402         size: ScalarSize,
403         rd: WritableReg,
404         rn: Reg,
405         rm: Reg,
406     },
407     FpuRRI {
408         fpu_op: FPUOpRI,
409         rd: WritableReg,
410         rn: Reg,
411     },
412     FpuRRRR {
413         fpu_op: FPUOp3,
414         rd: WritableReg,
415         rn: Reg,
416         rm: Reg,
417         ra: Reg,
418     },
419     FpuCmp {
420         size: ScalarSize,
421         rn: Reg,
422         rm: Reg,
423     },
424     FpuLoad32 {
425         rd: WritableReg,
426         mem: AMode,
427         flags: MemFlags,
428     },
429     FpuStore32 {
430         rd: Reg,
431         mem: AMode,
432         flags: MemFlags,
433     },
434     FpuLoad64 {
435         rd: WritableReg,
436         mem: AMode,
437         flags: MemFlags,
438     },
439     FpuStore64 {
440         rd: Reg,
441         mem: AMode,
442         flags: MemFlags,
443     },
444     FpuLoad128 {
445         rd: WritableReg,
446         mem: AMode,
447         flags: MemFlags,
448     },
449     FpuStore128 {
450         rd: Reg,
451         mem: AMode,
452         flags: MemFlags,
453     },
454     FpuLoadP64 {
455         rt: WritableReg,
456         rt2: WritableReg,
457         mem: PairAMode,
458         flags: MemFlags,
459     },
460     FpuStoreP64 {
461         rt: Reg,
462         rt2: Reg,
463         mem: PairAMode,
464         flags: MemFlags,
465     },
466     FpuLoadP128 {
467         rt: WritableReg,
468         rt2: WritableReg,
469         mem: PairAMode,
470         flags: MemFlags,
471     },
472     FpuStoreP128 {
473         rt: Reg,
474         rt2: Reg,
475         mem: PairAMode,
476         flags: MemFlags,
477     },
478     LoadFpuConst64 {
479         rd: WritableReg,
480         const_data: u64,
481     },
482     LoadFpuConst128 {
483         rd: WritableReg,
484         const_data: u128,
485     },
486     FpuToInt {
487         op: FpuToIntOp,
488         rd: WritableReg,
489         rn: Reg,
490     },
491     IntToFpu {
492         op: IntToFpuOp,
493         rd: WritableReg,
494         rn: Reg,
495     },
496     FpuCSel32 {
497         rd: WritableReg,
498         rn: Reg,
499         rm: Reg,
500         cond: Cond,
501     },
502     FpuCSel64 {
503         rd: WritableReg,
504         rn: Reg,
505         rm: Reg,
506         cond: Cond,
507     },
508     FpuRound {
509         op: FpuRoundMode,
510         rd: WritableReg,
511         rn: Reg,
512     },
513     MovToFpu {
514         rd: WritableReg,
515         rn: Reg,
516         size: ScalarSize,
517     },
518     FpuMoveFPImm {
519         rd: WritableReg,
520         imm: ASIMDFPModImm,
521         size: ScalarSize,
522     },
523     MovToVec {
524         rd: WritableReg,
525         rn: Reg,
526         idx: u8,
527         size: VectorSize,
528     },
529     MovFromVec {
530         rd: WritableReg,
531         rn: Reg,
532         idx: u8,
533         size: VectorSize,
534     },
535     MovFromVecSigned {
536         rd: WritableReg,
537         rn: Reg,
538         idx: u8,
539         size: VectorSize,
540         scalar_size: OperandSize,
541     },
542     VecDup {
543         rd: WritableReg,
544         rn: Reg,
545         size: VectorSize,
546     },
547     VecDupFromFpu {
548         rd: WritableReg,
549         rn: Reg,
550         size: VectorSize,
551     },
552     VecDupFPImm {
553         rd: WritableReg,
554         imm: ASIMDFPModImm,
555         size: VectorSize,
556     },
557     VecDupImm {
558         rd: WritableReg,
559         imm: ASIMDMovModImm,
560         invert: bool,
561         size: VectorSize,
562     },
563     VecExtend {
564         t: VecExtendOp,
565         rd: WritableReg,
566         rn: Reg,
567         high_half: bool,
568     },
569     VecMovElement {
570         rd: WritableReg,
571         rn: Reg,
572         dest_idx: u8,
573         src_idx: u8,
574         size: VectorSize,
575     },
576     VecRRLong {
577         op: VecRRLongOp,
578         rd: WritableReg,
579         rn: Reg,
580         high_half: bool,
581     },
582     VecRRNarrow {
583         op: VecRRNarrowOp,
584         rd: WritableReg,
585         rn: Reg,
586         high_half: bool,
587     },
588     VecRRPair {
589         op: VecPairOp,
590         rd: WritableReg,
591         rn: Reg,
592     },
593     VecRRRLong {
594         alu_op: VecRRRLongOp,
595         rd: WritableReg,
596         rn: Reg,
597         rm: Reg,
598         high_half: bool,
599     },
600     VecRRPairLong {
601         op: VecRRPairLongOp,
602         rd: WritableReg,
603         rn: Reg,
604     },
605     VecRRR {
606         alu_op: VecALUOp,
607         rd: WritableReg,
608         rn: Reg,
609         rm: Reg,
610         size: VectorSize,
611     },
612     VecMisc {
613         op: VecMisc2,
614         rd: WritableReg,
615         rn: Reg,
616         size: VectorSize,
617     },
618     VecLanes {
619         op: VecLanesOp,
620         rd: WritableReg,
621         rn: Reg,
622         size: VectorSize,
623     },
624     VecShiftImm {
625         op: VecShiftImmOp,
626         rd: WritableReg,
627         rn: Reg,
628         size: VectorSize,
629         imm: u8,
630     },
631     VecExtract {
632         rd: WritableReg,
633         rn: Reg,
634         rm: Reg,
635         imm4: u8,
636     },
637     VecTbl {
638         rd: WritableReg,
639         rn: Reg,
640         rm: Reg,
641         is_extension: bool,
642     },
643     VecTbl2 {
644         rd: WritableReg,
645         rn: Reg,
646         rn2: Reg,
647         rm: Reg,
648         is_extension: bool,
649     },
650     VecLoadReplicate {
651         rd: WritableReg,
652         rn: Reg,
653         size: VectorSize,
654     },
655     VecCSel {
656         rd: WritableReg,
657         rn: Reg,
658         rm: Reg,
659         cond: Cond,
660     },
661     MovToNZCV {
662         rn: Reg,
663     },
664     MovFromNZCV {
665         rd: WritableReg,
666     },
667     Call {
668         info: BoxCallInfo,
669     },
670     CallInd {
671         info: BoxCallIndInfo,
672     },
673     Ret {
674         rets: VecReg,
675     },
676     EpiloguePlaceholder,
677     Jump {
678         dest: BranchTarget,
679     },
680     CondBr {
681         taken: BranchTarget,
682         not_taken: BranchTarget,
683         kind: CondBrKind,
684     },
685     TrapIf {
686         kind: CondBrKind,
687         trap_code: TrapCode,
688     },
689     IndirectBr {
690         rn: Reg,
691         targets: VecMachLabel,
692     },
693     Brk,
694     Udf {
695         trap_code: TrapCode,
696     },
697     Adr {
698         rd: WritableReg,
699         off: i32,
700     },
701     Word4 {
702         data: u32,
703     },
704     Word8 {
705         data: u64,
706     },
707     JTSequence {
708         info: BoxJTSequenceInfo,
709         ridx: Reg,
710         rtmp1: WritableReg,
711         rtmp2: WritableReg,
712     },
713     LoadExtName {
714         rd: WritableReg,
715         name: BoxExternalName,
716         offset: i64,
717     },
718     LoadAddr {
719         rd: WritableReg,
720         mem: AMode,
721     },
722     VirtualSPOffsetAdj {
723         offset: i64,
724     },
725     EmitIsland {
726         needed_space: CodeOffset,
727     },
728     ElfTlsGetAddr {
729         symbol: ExternalName,
730     },
731     Unwind {
732         inst: UnwindInst,
733     },
734     DummyUse {
735         reg: Reg,
736     },
737 }
738 
739 /// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 779.
740 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
741 pub enum ALUOp {
742     Add,
743     Sub,
744     Orr,
745     OrrNot,
746     And,
747     AndS,
748     AndNot,
749     Eor,
750     EorNot,
751     AddS,
752     SubS,
753     SMulH,
754     UMulH,
755     SDiv,
756     UDiv,
757     RotR,
758     Lsr,
759     Asr,
760     Lsl,
761     Adc,
762     AdcS,
763     Sbc,
764     SbcS,
765 }
766 
767 /// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 817.
768 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
769 pub enum ALUOp3 {
770     MAdd,
771     MSub,
772 }
773 
774 /// Internal type MoveWideOp: defined at src/isa/aarch64/inst.isle line 825.
775 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
776 pub enum MoveWideOp {
777     MovZ,
778     MovN,
779     MovK,
780 }
781 
782 /// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 863.
783 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
784 pub enum BitOp {
785     RBit,
786     Clz,
787     Cls,
788 }
789 
790 /// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 930.
791 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
792 pub enum FPUOp1 {
793     Abs,
794     Neg,
795     Sqrt,
796     Cvt32To64,
797     Cvt64To32,
798 }
799 
800 /// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 940.
801 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
802 pub enum FPUOp2 {
803     Add,
804     Sub,
805     Mul,
806     Div,
807     Max,
808     Min,
809 }
810 
811 /// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 951.
812 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
813 pub enum FPUOp3 {
814     MAdd32,
815     MAdd64,
816 }
817 
818 /// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 958.
819 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
820 pub enum FpuToIntOp {
821     F32ToU32,
822     F32ToI32,
823     F32ToU64,
824     F32ToI64,
825     F64ToU32,
826     F64ToI32,
827     F64ToU64,
828     F64ToI64,
829 }
830 
831 /// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 971.
832 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
833 pub enum IntToFpuOp {
834     U32ToF32,
835     I32ToF32,
836     U32ToF64,
837     I32ToF64,
838     U64ToF32,
839     I64ToF32,
840     U64ToF64,
841     I64ToF64,
842 }
843 
844 /// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 985.
845 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
846 pub enum FpuRoundMode {
847     Minus32,
848     Minus64,
849     Plus32,
850     Plus64,
851     Zero32,
852     Zero64,
853     Nearest32,
854     Nearest64,
855 }
856 
857 /// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 998.
858 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
859 pub enum VecExtendOp {
860     Sxtl8,
861     Sxtl16,
862     Sxtl32,
863     Uxtl8,
864     Uxtl16,
865     Uxtl32,
866 }
867 
868 /// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1015.
869 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
870 pub enum VecALUOp {
871     Sqadd,
872     Uqadd,
873     Sqsub,
874     Uqsub,
875     Cmeq,
876     Cmge,
877     Cmgt,
878     Cmhs,
879     Cmhi,
880     Fcmeq,
881     Fcmgt,
882     Fcmge,
883     And,
884     Bic,
885     Orr,
886     Eor,
887     Bsl,
888     Umaxp,
889     Add,
890     Sub,
891     Mul,
892     Sshl,
893     Ushl,
894     Umin,
895     Smin,
896     Umax,
897     Smax,
898     Urhadd,
899     Fadd,
900     Fsub,
901     Fdiv,
902     Fmax,
903     Fmin,
904     Fmul,
905     Addp,
906     Zip1,
907     Sqrdmulh,
908 }
909 
910 /// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1094.
911 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
912 pub enum VecMisc2 {
913     Not,
914     Neg,
915     Abs,
916     Fabs,
917     Fneg,
918     Fsqrt,
919     Rev64,
920     Fcvtzs,
921     Fcvtzu,
922     Scvtf,
923     Ucvtf,
924     Frintn,
925     Frintz,
926     Frintm,
927     Frintp,
928     Cnt,
929     Cmeq0,
930     Cmge0,
931     Cmgt0,
932     Cmle0,
933     Cmlt0,
934     Fcmeq0,
935     Fcmge0,
936     Fcmgt0,
937     Fcmle0,
938     Fcmlt0,
939 }
940 
941 /// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1151.
942 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
943 pub enum VecRRLongOp {
944     Fcvtl16,
945     Fcvtl32,
946     Shll8,
947     Shll16,
948     Shll32,
949 }
950 
951 /// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1166.
952 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
953 pub enum VecRRNarrowOp {
954     Xtn16,
955     Xtn32,
956     Xtn64,
957     Sqxtn16,
958     Sqxtn32,
959     Sqxtn64,
960     Sqxtun16,
961     Sqxtun32,
962     Sqxtun64,
963     Uqxtn16,
964     Uqxtn32,
965     Uqxtn64,
966     Fcvtn32,
967     Fcvtn64,
968 }
969 
970 /// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1198.
971 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
972 pub enum VecRRRLongOp {
973     Smull8,
974     Smull16,
975     Smull32,
976     Umull8,
977     Umull16,
978     Umull32,
979     Umlal8,
980     Umlal16,
981     Umlal32,
982 }
983 
984 /// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1215.
985 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
986 pub enum VecPairOp {
987     Addp,
988 }
989 
990 /// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1223.
991 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
992 pub enum VecRRPairLongOp {
993     Saddlp8,
994     Saddlp16,
995     Uaddlp8,
996     Uaddlp16,
997 }
998 
999 /// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1234.
1000 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1001 pub enum VecLanesOp {
1002     Addv,
1003     Uminv,
1004 }
1005 
1006 /// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1243.
1007 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1008 pub enum VecShiftImmOp {
1009     Shl,
1010     Ushr,
1011     Sshr,
1012 }
1013 
1014 /// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1254.
1015 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1016 pub enum AtomicRMWOp {
1017     Add,
1018     Clr,
1019     Eor,
1020     Set,
1021     Smax,
1022     Smin,
1023     Umax,
1024     Umin,
1025 }
1026 
1027 // Generated as internal constructor for term output_reg.
1028 pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
1029     let pattern0_0 = arg0;
1030     // Rule at src/prelude.isle line 86.
1031     let expr0_0 = C::value_reg(ctx, pattern0_0);
1032     let expr1_0 = C::output(ctx, expr0_0);
1033     return Some(expr1_0);
1034 }
1035 
1036 // Generated as internal constructor for term output_value.
1037 pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> {
1038     let pattern0_0 = arg0;
1039     // Rule at src/prelude.isle line 90.
1040     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1041     let expr1_0 = C::output(ctx, expr0_0);
1042     return Some(expr1_0);
1043 }
1044 
1045 // Generated as internal constructor for term temp_reg.
1046 pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
1047     let pattern0_0 = arg0;
1048     // Rule at src/prelude.isle line 110.
1049     let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
1050     let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
1051     return Some(expr1_0);
1052 }
1053 
1054 // Generated as internal constructor for term lo_reg.
1055 pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
1056     let pattern0_0 = arg0;
1057     // Rule at src/prelude.isle line 145.
1058     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1059     let expr1_0: usize = 0;
1060     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1061     return Some(expr2_0);
1062 }
1063 
1064 // Generated as internal constructor for term side_effect.
1065 pub fn constructor_side_effect<C: Context>(
1066     ctx: &mut C,
1067     arg0: &SideEffectNoResult,
1068 ) -> Option<InstOutput> {
1069     let pattern0_0 = arg0;
1070     match pattern0_0 {
1071         &SideEffectNoResult::Inst {
1072             inst: ref pattern1_0,
1073         } => {
1074             // Rule at src/prelude.isle line 415.
1075             let expr0_0 = C::emit(ctx, pattern1_0);
1076             let expr1_0 = C::output_none(ctx);
1077             return Some(expr1_0);
1078         }
1079         &SideEffectNoResult::Inst2 {
1080             inst1: ref pattern1_0,
1081             inst2: ref pattern1_1,
1082         } => {
1083             // Rule at src/prelude.isle line 418.
1084             let expr0_0 = C::emit(ctx, pattern1_0);
1085             let expr1_0 = C::emit(ctx, pattern1_1);
1086             let expr2_0 = C::output_none(ctx);
1087             return Some(expr2_0);
1088         }
1089         _ => {}
1090     }
1091     return None;
1092 }
1093 
1094 // Generated as internal constructor for term side_effect_concat.
1095 pub fn constructor_side_effect_concat<C: Context>(
1096     ctx: &mut C,
1097     arg0: &SideEffectNoResult,
1098     arg1: &SideEffectNoResult,
1099 ) -> Option<SideEffectNoResult> {
1100     let pattern0_0 = arg0;
1101     if let &SideEffectNoResult::Inst {
1102         inst: ref pattern1_0,
1103     } = pattern0_0
1104     {
1105         let pattern2_0 = arg1;
1106         if let &SideEffectNoResult::Inst {
1107             inst: ref pattern3_0,
1108         } = pattern2_0
1109         {
1110             // Rule at src/prelude.isle line 424.
1111             let expr0_0 = SideEffectNoResult::Inst2 {
1112                 inst1: pattern1_0.clone(),
1113                 inst2: pattern3_0.clone(),
1114             };
1115             return Some(expr0_0);
1116         }
1117     }
1118     return None;
1119 }
1120 
1121 // Generated as internal constructor for term produces_flags_get_reg.
1122 pub fn constructor_produces_flags_get_reg<C: Context>(
1123     ctx: &mut C,
1124     arg0: &ProducesFlags,
1125 ) -> Option<Reg> {
1126     let pattern0_0 = arg0;
1127     if let &ProducesFlags::ProducesFlagsReturnsReg {
1128         inst: ref pattern1_0,
1129         result: pattern1_1,
1130     } = pattern0_0
1131     {
1132         // Rule at src/prelude.isle line 461.
1133         return Some(pattern1_1);
1134     }
1135     return None;
1136 }
1137 
1138 // Generated as internal constructor for term produces_flags_ignore.
1139 pub fn constructor_produces_flags_ignore<C: Context>(
1140     ctx: &mut C,
1141     arg0: &ProducesFlags,
1142 ) -> Option<ProducesFlags> {
1143     let pattern0_0 = arg0;
1144     match pattern0_0 {
1145         &ProducesFlags::ProducesFlagsReturnsReg {
1146             inst: ref pattern1_0,
1147             result: pattern1_1,
1148         } => {
1149             // Rule at src/prelude.isle line 466.
1150             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1151                 inst: pattern1_0.clone(),
1152             };
1153             return Some(expr0_0);
1154         }
1155         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1156             inst: ref pattern1_0,
1157             result: pattern1_1,
1158         } => {
1159             // Rule at src/prelude.isle line 468.
1160             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1161                 inst: pattern1_0.clone(),
1162             };
1163             return Some(expr0_0);
1164         }
1165         _ => {}
1166     }
1167     return None;
1168 }
1169 
1170 // Generated as internal constructor for term consumes_flags_concat.
1171 pub fn constructor_consumes_flags_concat<C: Context>(
1172     ctx: &mut C,
1173     arg0: &ConsumesFlags,
1174     arg1: &ConsumesFlags,
1175 ) -> Option<ConsumesFlags> {
1176     let pattern0_0 = arg0;
1177     if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1178         inst: ref pattern1_0,
1179         result: pattern1_1,
1180     } = pattern0_0
1181     {
1182         let pattern2_0 = arg1;
1183         if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1184             inst: ref pattern3_0,
1185             result: pattern3_1,
1186         } = pattern2_0
1187         {
1188             // Rule at src/prelude.isle line 475.
1189             let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1190             let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1191                 inst1: pattern1_0.clone(),
1192                 inst2: pattern3_0.clone(),
1193                 result: expr0_0,
1194             };
1195             return Some(expr1_0);
1196         }
1197     }
1198     return None;
1199 }
1200 
1201 // Generated as internal constructor for term with_flags.
1202 pub fn constructor_with_flags<C: Context>(
1203     ctx: &mut C,
1204     arg0: &ProducesFlags,
1205     arg1: &ConsumesFlags,
1206 ) -> Option<ValueRegs> {
1207     let pattern0_0 = arg0;
1208     match pattern0_0 {
1209         &ProducesFlags::ProducesFlagsSideEffect {
1210             inst: ref pattern1_0,
1211         } => {
1212             let pattern2_0 = arg1;
1213             match pattern2_0 {
1214                 &ConsumesFlags::ConsumesFlagsReturnsReg {
1215                     inst: ref pattern3_0,
1216                     result: pattern3_1,
1217                 } => {
1218                     // Rule at src/prelude.isle line 500.
1219                     let expr0_0 = C::emit(ctx, pattern1_0);
1220                     let expr1_0 = C::emit(ctx, pattern3_0);
1221                     let expr2_0 = C::value_reg(ctx, pattern3_1);
1222                     return Some(expr2_0);
1223                 }
1224                 &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1225                     inst1: ref pattern3_0,
1226                     inst2: ref pattern3_1,
1227                     result: pattern3_2,
1228                 } => {
1229                     // Rule at src/prelude.isle line 506.
1230                     let expr0_0 = C::emit(ctx, pattern1_0);
1231                     let expr1_0 = C::emit(ctx, pattern3_0);
1232                     let expr2_0 = C::emit(ctx, pattern3_1);
1233                     return Some(pattern3_2);
1234                 }
1235                 &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs {
1236                     inst1: ref pattern3_0,
1237                     inst2: ref pattern3_1,
1238                     inst3: ref pattern3_2,
1239                     inst4: ref pattern3_3,
1240                     result: pattern3_4,
1241                 } => {
1242                     // Rule at src/prelude.isle line 518.
1243                     let expr0_0 = C::emit(ctx, pattern1_0);
1244                     let expr1_0 = C::emit(ctx, pattern3_0);
1245                     let expr2_0 = C::emit(ctx, pattern3_1);
1246                     let expr3_0 = C::emit(ctx, pattern3_2);
1247                     let expr4_0 = C::emit(ctx, pattern3_3);
1248                     return Some(pattern3_4);
1249                 }
1250                 _ => {}
1251             }
1252         }
1253         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1254             inst: ref pattern1_0,
1255             result: pattern1_1,
1256         } => {
1257             let pattern2_0 = arg1;
1258             if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1259                 inst: ref pattern3_0,
1260                 result: pattern3_1,
1261             } = pattern2_0
1262             {
1263                 // Rule at src/prelude.isle line 494.
1264                 let expr0_0 = C::emit(ctx, pattern1_0);
1265                 let expr1_0 = C::emit(ctx, pattern3_0);
1266                 let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1267                 return Some(expr2_0);
1268             }
1269         }
1270         _ => {}
1271     }
1272     return None;
1273 }
1274 
1275 // Generated as internal constructor for term with_flags_reg.
1276 pub fn constructor_with_flags_reg<C: Context>(
1277     ctx: &mut C,
1278     arg0: &ProducesFlags,
1279     arg1: &ConsumesFlags,
1280 ) -> Option<Reg> {
1281     let pattern0_0 = arg0;
1282     let pattern1_0 = arg1;
1283     // Rule at src/prelude.isle line 535.
1284     let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?;
1285     let expr1_0: usize = 0;
1286     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1287     return Some(expr2_0);
1288 }
1289 
1290 // Generated as internal constructor for term operand_size.
1291 pub fn constructor_operand_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
1292     let pattern0_0 = arg0;
1293     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
1294         // Rule at src/isa/aarch64/inst.isle line 881.
1295         let expr0_0 = OperandSize::Size32;
1296         return Some(expr0_0);
1297     }
1298     if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
1299         // Rule at src/isa/aarch64/inst.isle line 882.
1300         let expr0_0 = OperandSize::Size64;
1301         return Some(expr0_0);
1302     }
1303     return None;
1304 }
1305 
1306 // Generated as internal constructor for term vector_size.
1307 pub fn constructor_vector_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<VectorSize> {
1308     let pattern0_0 = arg0;
1309     if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
1310         if pattern1_0 == 8 {
1311             if pattern1_1 == 16 {
1312                 // Rule at src/isa/aarch64/inst.isle line 924.
1313                 let expr0_0 = VectorSize::Size8x16;
1314                 return Some(expr0_0);
1315             }
1316         }
1317         if pattern1_0 == 16 {
1318             if pattern1_1 == 8 {
1319                 // Rule at src/isa/aarch64/inst.isle line 925.
1320                 let expr0_0 = VectorSize::Size16x8;
1321                 return Some(expr0_0);
1322             }
1323         }
1324         if pattern1_0 == 32 {
1325             if pattern1_1 == 4 {
1326                 // Rule at src/isa/aarch64/inst.isle line 926.
1327                 let expr0_0 = VectorSize::Size32x4;
1328                 return Some(expr0_0);
1329             }
1330         }
1331         if pattern1_0 == 64 {
1332             if pattern1_1 == 2 {
1333                 // Rule at src/isa/aarch64/inst.isle line 927.
1334                 let expr0_0 = VectorSize::Size64x2;
1335                 return Some(expr0_0);
1336             }
1337         }
1338     }
1339     return None;
1340 }
1341 
1342 // Generated as internal constructor for term movz.
1343 pub fn constructor_movz<C: Context>(
1344     ctx: &mut C,
1345     arg0: MoveWideConst,
1346     arg1: &OperandSize,
1347 ) -> Option<Reg> {
1348     let pattern0_0 = arg0;
1349     let pattern1_0 = arg1;
1350     // Rule at src/isa/aarch64/inst.isle line 1350.
1351     let expr0_0: Type = I64;
1352     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1353     let expr2_0 = MoveWideOp::MovZ;
1354     let expr3_0 = MInst::MovWide {
1355         op: expr2_0,
1356         rd: expr1_0,
1357         imm: pattern0_0,
1358         size: pattern1_0.clone(),
1359     };
1360     let expr4_0 = C::emit(ctx, &expr3_0);
1361     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1362     return Some(expr5_0);
1363 }
1364 
1365 // Generated as internal constructor for term movn.
1366 pub fn constructor_movn<C: Context>(
1367     ctx: &mut C,
1368     arg0: MoveWideConst,
1369     arg1: &OperandSize,
1370 ) -> Option<Reg> {
1371     let pattern0_0 = arg0;
1372     let pattern1_0 = arg1;
1373     // Rule at src/isa/aarch64/inst.isle line 1357.
1374     let expr0_0: Type = I64;
1375     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1376     let expr2_0 = MoveWideOp::MovN;
1377     let expr3_0 = MInst::MovWide {
1378         op: expr2_0,
1379         rd: expr1_0,
1380         imm: pattern0_0,
1381         size: pattern1_0.clone(),
1382     };
1383     let expr4_0 = C::emit(ctx, &expr3_0);
1384     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1385     return Some(expr5_0);
1386 }
1387 
1388 // Generated as internal constructor for term alu_rr_imm_logic.
1389 pub fn constructor_alu_rr_imm_logic<C: Context>(
1390     ctx: &mut C,
1391     arg0: &ALUOp,
1392     arg1: Type,
1393     arg2: Reg,
1394     arg3: ImmLogic,
1395 ) -> Option<Reg> {
1396     let pattern0_0 = arg0;
1397     let pattern1_0 = arg1;
1398     let pattern2_0 = arg2;
1399     let pattern3_0 = arg3;
1400     // Rule at src/isa/aarch64/inst.isle line 1364.
1401     let expr0_0: Type = I64;
1402     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1403     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1404     let expr3_0 = MInst::AluRRImmLogic {
1405         alu_op: pattern0_0.clone(),
1406         size: expr2_0,
1407         rd: expr1_0,
1408         rn: pattern2_0,
1409         imml: pattern3_0,
1410     };
1411     let expr4_0 = C::emit(ctx, &expr3_0);
1412     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1413     return Some(expr5_0);
1414 }
1415 
1416 // Generated as internal constructor for term alu_rr_imm_shift.
1417 pub fn constructor_alu_rr_imm_shift<C: Context>(
1418     ctx: &mut C,
1419     arg0: &ALUOp,
1420     arg1: Type,
1421     arg2: Reg,
1422     arg3: ImmShift,
1423 ) -> Option<Reg> {
1424     let pattern0_0 = arg0;
1425     let pattern1_0 = arg1;
1426     let pattern2_0 = arg2;
1427     let pattern3_0 = arg3;
1428     // Rule at src/isa/aarch64/inst.isle line 1371.
1429     let expr0_0: Type = I64;
1430     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1431     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1432     let expr3_0 = MInst::AluRRImmShift {
1433         alu_op: pattern0_0.clone(),
1434         size: expr2_0,
1435         rd: expr1_0,
1436         rn: pattern2_0,
1437         immshift: pattern3_0,
1438     };
1439     let expr4_0 = C::emit(ctx, &expr3_0);
1440     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1441     return Some(expr5_0);
1442 }
1443 
1444 // Generated as internal constructor for term alu_rrr.
1445 pub fn constructor_alu_rrr<C: Context>(
1446     ctx: &mut C,
1447     arg0: &ALUOp,
1448     arg1: Type,
1449     arg2: Reg,
1450     arg3: Reg,
1451 ) -> Option<Reg> {
1452     let pattern0_0 = arg0;
1453     let pattern1_0 = arg1;
1454     let pattern2_0 = arg2;
1455     let pattern3_0 = arg3;
1456     // Rule at src/isa/aarch64/inst.isle line 1378.
1457     let expr0_0: Type = I64;
1458     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1459     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1460     let expr3_0 = MInst::AluRRR {
1461         alu_op: pattern0_0.clone(),
1462         size: expr2_0,
1463         rd: expr1_0,
1464         rn: pattern2_0,
1465         rm: pattern3_0,
1466     };
1467     let expr4_0 = C::emit(ctx, &expr3_0);
1468     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1469     return Some(expr5_0);
1470 }
1471 
1472 // Generated as internal constructor for term vec_rrr.
1473 pub fn constructor_vec_rrr<C: Context>(
1474     ctx: &mut C,
1475     arg0: &VecALUOp,
1476     arg1: Reg,
1477     arg2: Reg,
1478     arg3: &VectorSize,
1479 ) -> Option<Reg> {
1480     let pattern0_0 = arg0;
1481     let pattern1_0 = arg1;
1482     let pattern2_0 = arg2;
1483     let pattern3_0 = arg3;
1484     // Rule at src/isa/aarch64/inst.isle line 1385.
1485     let expr0_0: Type = I8X16;
1486     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1487     let expr2_0 = MInst::VecRRR {
1488         alu_op: pattern0_0.clone(),
1489         rd: expr1_0,
1490         rn: pattern1_0,
1491         rm: pattern2_0,
1492         size: pattern3_0.clone(),
1493     };
1494     let expr3_0 = C::emit(ctx, &expr2_0);
1495     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1496     return Some(expr4_0);
1497 }
1498 
1499 // Generated as internal constructor for term vec_lanes.
1500 pub fn constructor_vec_lanes<C: Context>(
1501     ctx: &mut C,
1502     arg0: &VecLanesOp,
1503     arg1: Reg,
1504     arg2: &VectorSize,
1505 ) -> Option<Reg> {
1506     let pattern0_0 = arg0;
1507     let pattern1_0 = arg1;
1508     let pattern2_0 = arg2;
1509     // Rule at src/isa/aarch64/inst.isle line 1392.
1510     let expr0_0: Type = I8X16;
1511     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1512     let expr2_0 = MInst::VecLanes {
1513         op: pattern0_0.clone(),
1514         rd: expr1_0,
1515         rn: pattern1_0,
1516         size: pattern2_0.clone(),
1517     };
1518     let expr3_0 = C::emit(ctx, &expr2_0);
1519     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1520     return Some(expr4_0);
1521 }
1522 
1523 // Generated as internal constructor for term vec_dup.
1524 pub fn constructor_vec_dup<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
1525     let pattern0_0 = arg0;
1526     let pattern1_0 = arg1;
1527     // Rule at src/isa/aarch64/inst.isle line 1399.
1528     let expr0_0: Type = I8X16;
1529     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1530     let expr2_0 = MInst::VecDup {
1531         rd: expr1_0,
1532         rn: pattern0_0,
1533         size: pattern1_0.clone(),
1534     };
1535     let expr3_0 = C::emit(ctx, &expr2_0);
1536     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1537     return Some(expr4_0);
1538 }
1539 
1540 // Generated as internal constructor for term alu_rr_imm12.
1541 pub fn constructor_alu_rr_imm12<C: Context>(
1542     ctx: &mut C,
1543     arg0: &ALUOp,
1544     arg1: Type,
1545     arg2: Reg,
1546     arg3: Imm12,
1547 ) -> Option<Reg> {
1548     let pattern0_0 = arg0;
1549     let pattern1_0 = arg1;
1550     let pattern2_0 = arg2;
1551     let pattern3_0 = arg3;
1552     // Rule at src/isa/aarch64/inst.isle line 1406.
1553     let expr0_0: Type = I64;
1554     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1555     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1556     let expr3_0 = MInst::AluRRImm12 {
1557         alu_op: pattern0_0.clone(),
1558         size: expr2_0,
1559         rd: expr1_0,
1560         rn: pattern2_0,
1561         imm12: pattern3_0,
1562     };
1563     let expr4_0 = C::emit(ctx, &expr3_0);
1564     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1565     return Some(expr5_0);
1566 }
1567 
1568 // Generated as internal constructor for term alu_rrr_shift.
1569 pub fn constructor_alu_rrr_shift<C: Context>(
1570     ctx: &mut C,
1571     arg0: &ALUOp,
1572     arg1: Type,
1573     arg2: Reg,
1574     arg3: Reg,
1575     arg4: ShiftOpAndAmt,
1576 ) -> Option<Reg> {
1577     let pattern0_0 = arg0;
1578     let pattern1_0 = arg1;
1579     let pattern2_0 = arg2;
1580     let pattern3_0 = arg3;
1581     let pattern4_0 = arg4;
1582     // Rule at src/isa/aarch64/inst.isle line 1413.
1583     let expr0_0: Type = I64;
1584     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1585     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1586     let expr3_0 = MInst::AluRRRShift {
1587         alu_op: pattern0_0.clone(),
1588         size: expr2_0,
1589         rd: expr1_0,
1590         rn: pattern2_0,
1591         rm: pattern3_0,
1592         shiftop: pattern4_0,
1593     };
1594     let expr4_0 = C::emit(ctx, &expr3_0);
1595     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1596     return Some(expr5_0);
1597 }
1598 
1599 // Generated as internal constructor for term alu_rrr_extend.
1600 pub fn constructor_alu_rrr_extend<C: Context>(
1601     ctx: &mut C,
1602     arg0: &ALUOp,
1603     arg1: Type,
1604     arg2: Reg,
1605     arg3: Reg,
1606     arg4: &ExtendOp,
1607 ) -> Option<Reg> {
1608     let pattern0_0 = arg0;
1609     let pattern1_0 = arg1;
1610     let pattern2_0 = arg2;
1611     let pattern3_0 = arg3;
1612     let pattern4_0 = arg4;
1613     // Rule at src/isa/aarch64/inst.isle line 1420.
1614     let expr0_0: Type = I64;
1615     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1616     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1617     let expr3_0 = MInst::AluRRRExtend {
1618         alu_op: pattern0_0.clone(),
1619         size: expr2_0,
1620         rd: expr1_0,
1621         rn: pattern2_0,
1622         rm: pattern3_0,
1623         extendop: pattern4_0.clone(),
1624     };
1625     let expr4_0 = C::emit(ctx, &expr3_0);
1626     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1627     return Some(expr5_0);
1628 }
1629 
1630 // Generated as internal constructor for term alu_rr_extend_reg.
1631 pub fn constructor_alu_rr_extend_reg<C: Context>(
1632     ctx: &mut C,
1633     arg0: &ALUOp,
1634     arg1: Type,
1635     arg2: Reg,
1636     arg3: &ExtendedValue,
1637 ) -> Option<Reg> {
1638     let pattern0_0 = arg0;
1639     let pattern1_0 = arg1;
1640     let pattern2_0 = arg2;
1641     let pattern3_0 = arg3;
1642     // Rule at src/isa/aarch64/inst.isle line 1428.
1643     let expr0_0 = C::put_extended_in_reg(ctx, pattern3_0);
1644     let expr1_0 = C::get_extended_op(ctx, pattern3_0);
1645     let expr2_0 =
1646         constructor_alu_rrr_extend(ctx, pattern0_0, pattern1_0, pattern2_0, expr0_0, &expr1_0)?;
1647     return Some(expr2_0);
1648 }
1649 
1650 // Generated as internal constructor for term alu_rrrr.
1651 pub fn constructor_alu_rrrr<C: Context>(
1652     ctx: &mut C,
1653     arg0: &ALUOp3,
1654     arg1: Type,
1655     arg2: Reg,
1656     arg3: Reg,
1657     arg4: Reg,
1658 ) -> Option<Reg> {
1659     let pattern0_0 = arg0;
1660     let pattern1_0 = arg1;
1661     let pattern2_0 = arg2;
1662     let pattern3_0 = arg3;
1663     let pattern4_0 = arg4;
1664     // Rule at src/isa/aarch64/inst.isle line 1435.
1665     let expr0_0: Type = I64;
1666     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1667     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1668     let expr3_0 = MInst::AluRRRR {
1669         alu_op: pattern0_0.clone(),
1670         size: expr2_0,
1671         rd: expr1_0,
1672         rn: pattern2_0,
1673         rm: pattern3_0,
1674         ra: pattern4_0,
1675     };
1676     let expr4_0 = C::emit(ctx, &expr3_0);
1677     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1678     return Some(expr5_0);
1679 }
1680 
1681 // Generated as internal constructor for term bit_rr.
1682 pub fn constructor_bit_rr<C: Context>(
1683     ctx: &mut C,
1684     arg0: &BitOp,
1685     arg1: Type,
1686     arg2: Reg,
1687 ) -> Option<Reg> {
1688     let pattern0_0 = arg0;
1689     let pattern1_0 = arg1;
1690     let pattern2_0 = arg2;
1691     // Rule at src/isa/aarch64/inst.isle line 1442.
1692     let expr0_0: Type = I64;
1693     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1694     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1695     let expr3_0 = MInst::BitRR {
1696         op: pattern0_0.clone(),
1697         size: expr2_0,
1698         rd: expr1_0,
1699         rn: pattern2_0,
1700     };
1701     let expr4_0 = C::emit(ctx, &expr3_0);
1702     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1703     return Some(expr5_0);
1704 }
1705 
1706 // Generated as internal constructor for term add_with_flags_paired.
1707 pub fn constructor_add_with_flags_paired<C: Context>(
1708     ctx: &mut C,
1709     arg0: Type,
1710     arg1: Reg,
1711     arg2: Reg,
1712 ) -> Option<ProducesFlags> {
1713     let pattern0_0 = arg0;
1714     let pattern1_0 = arg1;
1715     let pattern2_0 = arg2;
1716     // Rule at src/isa/aarch64/inst.isle line 1449.
1717     let expr0_0: Type = I64;
1718     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1719     let expr2_0 = ALUOp::AddS;
1720     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1721     let expr4_0 = MInst::AluRRR {
1722         alu_op: expr2_0,
1723         size: expr3_0,
1724         rd: expr1_0,
1725         rn: pattern1_0,
1726         rm: pattern2_0,
1727     };
1728     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1729     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1730         inst: expr4_0,
1731         result: expr5_0,
1732     };
1733     return Some(expr6_0);
1734 }
1735 
1736 // Generated as internal constructor for term adc_paired.
1737 pub fn constructor_adc_paired<C: Context>(
1738     ctx: &mut C,
1739     arg0: Type,
1740     arg1: Reg,
1741     arg2: Reg,
1742 ) -> Option<ConsumesFlags> {
1743     let pattern0_0 = arg0;
1744     let pattern1_0 = arg1;
1745     let pattern2_0 = arg2;
1746     // Rule at src/isa/aarch64/inst.isle line 1457.
1747     let expr0_0: Type = I64;
1748     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1749     let expr2_0 = ALUOp::Adc;
1750     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1751     let expr4_0 = MInst::AluRRR {
1752         alu_op: expr2_0,
1753         size: expr3_0,
1754         rd: expr1_0,
1755         rn: pattern1_0,
1756         rm: pattern2_0,
1757     };
1758     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1759     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1760         inst: expr4_0,
1761         result: expr5_0,
1762     };
1763     return Some(expr6_0);
1764 }
1765 
1766 // Generated as internal constructor for term sub_with_flags_paired.
1767 pub fn constructor_sub_with_flags_paired<C: Context>(
1768     ctx: &mut C,
1769     arg0: Type,
1770     arg1: Reg,
1771     arg2: Reg,
1772 ) -> Option<ProducesFlags> {
1773     let pattern0_0 = arg0;
1774     let pattern1_0 = arg1;
1775     let pattern2_0 = arg2;
1776     // Rule at src/isa/aarch64/inst.isle line 1465.
1777     let expr0_0: Type = I64;
1778     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1779     let expr2_0 = ALUOp::SubS;
1780     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1781     let expr4_0 = MInst::AluRRR {
1782         alu_op: expr2_0,
1783         size: expr3_0,
1784         rd: expr1_0,
1785         rn: pattern1_0,
1786         rm: pattern2_0,
1787     };
1788     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1789     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1790         inst: expr4_0,
1791         result: expr5_0,
1792     };
1793     return Some(expr6_0);
1794 }
1795 
1796 // Generated as internal constructor for term cmp64_imm.
1797 pub fn constructor_cmp64_imm<C: Context>(
1798     ctx: &mut C,
1799     arg0: Reg,
1800     arg1: Imm12,
1801 ) -> Option<ProducesFlags> {
1802     let pattern0_0 = arg0;
1803     let pattern1_0 = arg1;
1804     // Rule at src/isa/aarch64/inst.isle line 1472.
1805     let expr0_0 = ALUOp::SubS;
1806     let expr1_0 = OperandSize::Size64;
1807     let expr2_0 = C::writable_zero_reg(ctx);
1808     let expr3_0 = MInst::AluRRImm12 {
1809         alu_op: expr0_0,
1810         size: expr1_0,
1811         rd: expr2_0,
1812         rn: pattern0_0,
1813         imm12: pattern1_0,
1814     };
1815     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
1816     return Some(expr4_0);
1817 }
1818 
1819 // Generated as internal constructor for term sbc_paired.
1820 pub fn constructor_sbc_paired<C: Context>(
1821     ctx: &mut C,
1822     arg0: Type,
1823     arg1: Reg,
1824     arg2: Reg,
1825 ) -> Option<ConsumesFlags> {
1826     let pattern0_0 = arg0;
1827     let pattern1_0 = arg1;
1828     let pattern2_0 = arg2;
1829     // Rule at src/isa/aarch64/inst.isle line 1479.
1830     let expr0_0: Type = I64;
1831     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1832     let expr2_0 = ALUOp::Sbc;
1833     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1834     let expr4_0 = MInst::AluRRR {
1835         alu_op: expr2_0,
1836         size: expr3_0,
1837         rd: expr1_0,
1838         rn: pattern1_0,
1839         rm: pattern2_0,
1840     };
1841     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1842     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1843         inst: expr4_0,
1844         result: expr5_0,
1845     };
1846     return Some(expr6_0);
1847 }
1848 
1849 // Generated as internal constructor for term vec_misc.
1850 pub fn constructor_vec_misc<C: Context>(
1851     ctx: &mut C,
1852     arg0: &VecMisc2,
1853     arg1: Reg,
1854     arg2: &VectorSize,
1855 ) -> Option<Reg> {
1856     let pattern0_0 = arg0;
1857     let pattern1_0 = arg1;
1858     let pattern2_0 = arg2;
1859     // Rule at src/isa/aarch64/inst.isle line 1487.
1860     let expr0_0: Type = I8X16;
1861     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1862     let expr2_0 = MInst::VecMisc {
1863         op: pattern0_0.clone(),
1864         rd: expr1_0,
1865         rn: pattern1_0,
1866         size: pattern2_0.clone(),
1867     };
1868     let expr3_0 = C::emit(ctx, &expr2_0);
1869     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1870     return Some(expr4_0);
1871 }
1872 
1873 // Generated as internal constructor for term vec_rrr_long.
1874 pub fn constructor_vec_rrr_long<C: Context>(
1875     ctx: &mut C,
1876     arg0: &VecRRRLongOp,
1877     arg1: Reg,
1878     arg2: Reg,
1879     arg3: bool,
1880 ) -> Option<Reg> {
1881     let pattern0_0 = arg0;
1882     let pattern1_0 = arg1;
1883     let pattern2_0 = arg2;
1884     let pattern3_0 = arg3;
1885     // Rule at src/isa/aarch64/inst.isle line 1494.
1886     let expr0_0: Type = I8X16;
1887     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1888     let expr2_0 = MInst::VecRRRLong {
1889         alu_op: pattern0_0.clone(),
1890         rd: expr1_0,
1891         rn: pattern1_0,
1892         rm: pattern2_0,
1893         high_half: pattern3_0,
1894     };
1895     let expr3_0 = C::emit(ctx, &expr2_0);
1896     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1897     return Some(expr4_0);
1898 }
1899 
1900 // Generated as internal constructor for term vec_rrrr_long.
1901 pub fn constructor_vec_rrrr_long<C: Context>(
1902     ctx: &mut C,
1903     arg0: &VecRRRLongOp,
1904     arg1: Reg,
1905     arg2: Reg,
1906     arg3: Reg,
1907     arg4: bool,
1908 ) -> Option<Reg> {
1909     let pattern0_0 = arg0;
1910     let pattern1_0 = arg1;
1911     let pattern2_0 = arg2;
1912     let pattern3_0 = arg3;
1913     let pattern4_0 = arg4;
1914     // Rule at src/isa/aarch64/inst.isle line 1504.
1915     let expr0_0: Type = I8X16;
1916     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1917     let expr2_0 = MInst::FpuMove128 {
1918         rd: expr1_0,
1919         rn: pattern1_0,
1920     };
1921     let expr3_0 = C::emit(ctx, &expr2_0);
1922     let expr4_0 = MInst::VecRRRLong {
1923         alu_op: pattern0_0.clone(),
1924         rd: expr1_0,
1925         rn: pattern2_0,
1926         rm: pattern3_0,
1927         high_half: pattern4_0,
1928     };
1929     let expr5_0 = C::emit(ctx, &expr4_0);
1930     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1931     return Some(expr6_0);
1932 }
1933 
1934 // Generated as internal constructor for term vec_rr_narrow.
1935 pub fn constructor_vec_rr_narrow<C: Context>(
1936     ctx: &mut C,
1937     arg0: &VecRRNarrowOp,
1938     arg1: Reg,
1939     arg2: bool,
1940 ) -> Option<Reg> {
1941     let pattern0_0 = arg0;
1942     let pattern1_0 = arg1;
1943     let pattern2_0 = arg2;
1944     // Rule at src/isa/aarch64/inst.isle line 1512.
1945     let expr0_0: Type = I8X16;
1946     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1947     let expr2_0 = MInst::VecRRNarrow {
1948         op: pattern0_0.clone(),
1949         rd: expr1_0,
1950         rn: pattern1_0,
1951         high_half: pattern2_0,
1952     };
1953     let expr3_0 = C::emit(ctx, &expr2_0);
1954     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1955     return Some(expr4_0);
1956 }
1957 
1958 // Generated as internal constructor for term vec_rr_long.
1959 pub fn constructor_vec_rr_long<C: Context>(
1960     ctx: &mut C,
1961     arg0: &VecRRLongOp,
1962     arg1: Reg,
1963     arg2: bool,
1964 ) -> Option<Reg> {
1965     let pattern0_0 = arg0;
1966     let pattern1_0 = arg1;
1967     let pattern2_0 = arg2;
1968     // Rule at src/isa/aarch64/inst.isle line 1519.
1969     let expr0_0: Type = I8X16;
1970     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1971     let expr2_0 = MInst::VecRRLong {
1972         op: pattern0_0.clone(),
1973         rd: expr1_0,
1974         rn: pattern1_0,
1975         high_half: pattern2_0,
1976     };
1977     let expr3_0 = C::emit(ctx, &expr2_0);
1978     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1979     return Some(expr4_0);
1980 }
1981 
1982 // Generated as internal constructor for term mov_to_fpu.
1983 pub fn constructor_mov_to_fpu<C: Context>(
1984     ctx: &mut C,
1985     arg0: Reg,
1986     arg1: &ScalarSize,
1987 ) -> Option<Reg> {
1988     let pattern0_0 = arg0;
1989     let pattern1_0 = arg1;
1990     // Rule at src/isa/aarch64/inst.isle line 1526.
1991     let expr0_0: Type = I8X16;
1992     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1993     let expr2_0 = MInst::MovToFpu {
1994         rd: expr1_0,
1995         rn: pattern0_0,
1996         size: pattern1_0.clone(),
1997     };
1998     let expr3_0 = C::emit(ctx, &expr2_0);
1999     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2000     return Some(expr4_0);
2001 }
2002 
2003 // Generated as internal constructor for term mov_to_vec.
2004 pub fn constructor_mov_to_vec<C: Context>(
2005     ctx: &mut C,
2006     arg0: Reg,
2007     arg1: Reg,
2008     arg2: u8,
2009     arg3: &VectorSize,
2010 ) -> Option<Reg> {
2011     let pattern0_0 = arg0;
2012     let pattern1_0 = arg1;
2013     let pattern2_0 = arg2;
2014     let pattern3_0 = arg3;
2015     // Rule at src/isa/aarch64/inst.isle line 1533.
2016     let expr0_0: Type = I8X16;
2017     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2018     let expr2_0 = MInst::FpuMove128 {
2019         rd: expr1_0,
2020         rn: pattern0_0,
2021     };
2022     let expr3_0 = C::emit(ctx, &expr2_0);
2023     let expr4_0 = MInst::MovToVec {
2024         rd: expr1_0,
2025         rn: pattern1_0,
2026         idx: pattern2_0,
2027         size: pattern3_0.clone(),
2028     };
2029     let expr5_0 = C::emit(ctx, &expr4_0);
2030     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
2031     return Some(expr6_0);
2032 }
2033 
2034 // Generated as internal constructor for term mov_from_vec.
2035 pub fn constructor_mov_from_vec<C: Context>(
2036     ctx: &mut C,
2037     arg0: Reg,
2038     arg1: u8,
2039     arg2: &VectorSize,
2040 ) -> Option<Reg> {
2041     let pattern0_0 = arg0;
2042     let pattern1_0 = arg1;
2043     let pattern2_0 = arg2;
2044     // Rule at src/isa/aarch64/inst.isle line 1541.
2045     let expr0_0: Type = I64;
2046     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2047     let expr2_0 = MInst::MovFromVec {
2048         rd: expr1_0,
2049         rn: pattern0_0,
2050         idx: pattern1_0,
2051         size: pattern2_0.clone(),
2052     };
2053     let expr3_0 = C::emit(ctx, &expr2_0);
2054     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2055     return Some(expr4_0);
2056 }
2057 
2058 // Generated as internal constructor for term mov_from_vec_signed.
2059 pub fn constructor_mov_from_vec_signed<C: Context>(
2060     ctx: &mut C,
2061     arg0: Reg,
2062     arg1: u8,
2063     arg2: &VectorSize,
2064     arg3: &OperandSize,
2065 ) -> Option<Reg> {
2066     let pattern0_0 = arg0;
2067     let pattern1_0 = arg1;
2068     let pattern2_0 = arg2;
2069     let pattern3_0 = arg3;
2070     // Rule at src/isa/aarch64/inst.isle line 1548.
2071     let expr0_0: Type = I64;
2072     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2073     let expr2_0 = MInst::MovFromVecSigned {
2074         rd: expr1_0,
2075         rn: pattern0_0,
2076         idx: pattern1_0,
2077         size: pattern2_0.clone(),
2078         scalar_size: pattern3_0.clone(),
2079     };
2080     let expr3_0 = C::emit(ctx, &expr2_0);
2081     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2082     return Some(expr4_0);
2083 }
2084 
2085 // Generated as internal constructor for term extend.
2086 pub fn constructor_extend<C: Context>(
2087     ctx: &mut C,
2088     arg0: Reg,
2089     arg1: bool,
2090     arg2: u8,
2091     arg3: u8,
2092 ) -> Option<Reg> {
2093     let pattern0_0 = arg0;
2094     let pattern1_0 = arg1;
2095     let pattern2_0 = arg2;
2096     let pattern3_0 = arg3;
2097     // Rule at src/isa/aarch64/inst.isle line 1555.
2098     let expr0_0: Type = I64;
2099     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2100     let expr2_0 = MInst::Extend {
2101         rd: expr1_0,
2102         rn: pattern0_0,
2103         signed: pattern1_0,
2104         from_bits: pattern2_0,
2105         to_bits: pattern3_0,
2106     };
2107     let expr3_0 = C::emit(ctx, &expr2_0);
2108     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2109     return Some(expr4_0);
2110 }
2111 
2112 // Generated as internal constructor for term load_acquire.
2113 pub fn constructor_load_acquire<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2114     let pattern0_0 = arg0;
2115     let pattern1_0 = arg1;
2116     // Rule at src/isa/aarch64/inst.isle line 1562.
2117     let expr0_0: Type = I64;
2118     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2119     let expr2_0 = MInst::LoadAcquire {
2120         access_ty: pattern0_0,
2121         rt: expr1_0,
2122         rn: pattern1_0,
2123     };
2124     let expr3_0 = C::emit(ctx, &expr2_0);
2125     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2126     return Some(expr4_0);
2127 }
2128 
2129 // Generated as internal constructor for term tst_imm.
2130 pub fn constructor_tst_imm<C: Context>(
2131     ctx: &mut C,
2132     arg0: Type,
2133     arg1: Reg,
2134     arg2: ImmLogic,
2135 ) -> Option<ProducesFlags> {
2136     let pattern0_0 = arg0;
2137     let pattern1_0 = arg1;
2138     let pattern2_0 = arg2;
2139     // Rule at src/isa/aarch64/inst.isle line 1572.
2140     let expr0_0 = ALUOp::AndS;
2141     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
2142     let expr2_0 = C::writable_zero_reg(ctx);
2143     let expr3_0 = MInst::AluRRImmLogic {
2144         alu_op: expr0_0,
2145         size: expr1_0,
2146         rd: expr2_0,
2147         rn: pattern1_0,
2148         imml: pattern2_0,
2149     };
2150     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
2151     return Some(expr4_0);
2152 }
2153 
2154 // Generated as internal constructor for term csel.
2155 pub fn constructor_csel<C: Context>(
2156     ctx: &mut C,
2157     arg0: &Cond,
2158     arg1: Reg,
2159     arg2: Reg,
2160 ) -> Option<ConsumesFlags> {
2161     let pattern0_0 = arg0;
2162     let pattern1_0 = arg1;
2163     let pattern2_0 = arg2;
2164     // Rule at src/isa/aarch64/inst.isle line 1586.
2165     let expr0_0: Type = I64;
2166     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2167     let expr2_0 = MInst::CSel {
2168         rd: expr1_0,
2169         cond: pattern0_0.clone(),
2170         rn: pattern1_0,
2171         rm: pattern2_0,
2172     };
2173     let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
2174     let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
2175         inst: expr2_0,
2176         result: expr3_0,
2177     };
2178     return Some(expr4_0);
2179 }
2180 
2181 // Generated as internal constructor for term add.
2182 pub fn constructor_add<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2183     let pattern0_0 = arg0;
2184     let pattern1_0 = arg1;
2185     let pattern2_0 = arg2;
2186     // Rule at src/isa/aarch64/inst.isle line 1595.
2187     let expr0_0 = ALUOp::Add;
2188     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2189     return Some(expr1_0);
2190 }
2191 
2192 // Generated as internal constructor for term add_imm.
2193 pub fn constructor_add_imm<C: Context>(
2194     ctx: &mut C,
2195     arg0: Type,
2196     arg1: Reg,
2197     arg2: Imm12,
2198 ) -> Option<Reg> {
2199     let pattern0_0 = arg0;
2200     let pattern1_0 = arg1;
2201     let pattern2_0 = arg2;
2202     // Rule at src/isa/aarch64/inst.isle line 1598.
2203     let expr0_0 = ALUOp::Add;
2204     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2205     return Some(expr1_0);
2206 }
2207 
2208 // Generated as internal constructor for term add_extend.
2209 pub fn constructor_add_extend<C: Context>(
2210     ctx: &mut C,
2211     arg0: Type,
2212     arg1: Reg,
2213     arg2: &ExtendedValue,
2214 ) -> Option<Reg> {
2215     let pattern0_0 = arg0;
2216     let pattern1_0 = arg1;
2217     let pattern2_0 = arg2;
2218     // Rule at src/isa/aarch64/inst.isle line 1601.
2219     let expr0_0 = ALUOp::Add;
2220     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2221     return Some(expr1_0);
2222 }
2223 
2224 // Generated as internal constructor for term add_shift.
2225 pub fn constructor_add_shift<C: Context>(
2226     ctx: &mut C,
2227     arg0: Type,
2228     arg1: Reg,
2229     arg2: Reg,
2230     arg3: ShiftOpAndAmt,
2231 ) -> Option<Reg> {
2232     let pattern0_0 = arg0;
2233     let pattern1_0 = arg1;
2234     let pattern2_0 = arg2;
2235     let pattern3_0 = arg3;
2236     // Rule at src/isa/aarch64/inst.isle line 1604.
2237     let expr0_0 = ALUOp::Add;
2238     let expr1_0 = constructor_alu_rrr_shift(
2239         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2240     )?;
2241     return Some(expr1_0);
2242 }
2243 
2244 // Generated as internal constructor for term add_vec.
2245 pub fn constructor_add_vec<C: Context>(
2246     ctx: &mut C,
2247     arg0: Reg,
2248     arg1: Reg,
2249     arg2: &VectorSize,
2250 ) -> Option<Reg> {
2251     let pattern0_0 = arg0;
2252     let pattern1_0 = arg1;
2253     let pattern2_0 = arg2;
2254     // Rule at src/isa/aarch64/inst.isle line 1607.
2255     let expr0_0 = VecALUOp::Add;
2256     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2257     return Some(expr1_0);
2258 }
2259 
2260 // Generated as internal constructor for term sub.
2261 pub fn constructor_sub<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2262     let pattern0_0 = arg0;
2263     let pattern1_0 = arg1;
2264     let pattern2_0 = arg2;
2265     // Rule at src/isa/aarch64/inst.isle line 1612.
2266     let expr0_0 = ALUOp::Sub;
2267     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2268     return Some(expr1_0);
2269 }
2270 
2271 // Generated as internal constructor for term sub_imm.
2272 pub fn constructor_sub_imm<C: Context>(
2273     ctx: &mut C,
2274     arg0: Type,
2275     arg1: Reg,
2276     arg2: Imm12,
2277 ) -> Option<Reg> {
2278     let pattern0_0 = arg0;
2279     let pattern1_0 = arg1;
2280     let pattern2_0 = arg2;
2281     // Rule at src/isa/aarch64/inst.isle line 1615.
2282     let expr0_0 = ALUOp::Sub;
2283     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2284     return Some(expr1_0);
2285 }
2286 
2287 // Generated as internal constructor for term sub_extend.
2288 pub fn constructor_sub_extend<C: Context>(
2289     ctx: &mut C,
2290     arg0: Type,
2291     arg1: Reg,
2292     arg2: &ExtendedValue,
2293 ) -> Option<Reg> {
2294     let pattern0_0 = arg0;
2295     let pattern1_0 = arg1;
2296     let pattern2_0 = arg2;
2297     // Rule at src/isa/aarch64/inst.isle line 1618.
2298     let expr0_0 = ALUOp::Sub;
2299     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2300     return Some(expr1_0);
2301 }
2302 
2303 // Generated as internal constructor for term sub_shift.
2304 pub fn constructor_sub_shift<C: Context>(
2305     ctx: &mut C,
2306     arg0: Type,
2307     arg1: Reg,
2308     arg2: Reg,
2309     arg3: ShiftOpAndAmt,
2310 ) -> Option<Reg> {
2311     let pattern0_0 = arg0;
2312     let pattern1_0 = arg1;
2313     let pattern2_0 = arg2;
2314     let pattern3_0 = arg3;
2315     // Rule at src/isa/aarch64/inst.isle line 1621.
2316     let expr0_0 = ALUOp::Sub;
2317     let expr1_0 = constructor_alu_rrr_shift(
2318         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2319     )?;
2320     return Some(expr1_0);
2321 }
2322 
2323 // Generated as internal constructor for term sub_vec.
2324 pub fn constructor_sub_vec<C: Context>(
2325     ctx: &mut C,
2326     arg0: Reg,
2327     arg1: Reg,
2328     arg2: &VectorSize,
2329 ) -> Option<Reg> {
2330     let pattern0_0 = arg0;
2331     let pattern1_0 = arg1;
2332     let pattern2_0 = arg2;
2333     // Rule at src/isa/aarch64/inst.isle line 1624.
2334     let expr0_0 = VecALUOp::Sub;
2335     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2336     return Some(expr1_0);
2337 }
2338 
2339 // Generated as internal constructor for term madd.
2340 pub fn constructor_madd<C: Context>(
2341     ctx: &mut C,
2342     arg0: Type,
2343     arg1: Reg,
2344     arg2: Reg,
2345     arg3: Reg,
2346 ) -> Option<Reg> {
2347     let pattern0_0 = arg0;
2348     let pattern1_0 = arg1;
2349     let pattern2_0 = arg2;
2350     let pattern3_0 = arg3;
2351     // Rule at src/isa/aarch64/inst.isle line 1629.
2352     let expr0_0 = ALUOp3::MAdd;
2353     let expr1_0 = constructor_alu_rrrr(
2354         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2355     )?;
2356     return Some(expr1_0);
2357 }
2358 
2359 // Generated as internal constructor for term msub.
2360 pub fn constructor_msub<C: Context>(
2361     ctx: &mut C,
2362     arg0: Type,
2363     arg1: Reg,
2364     arg2: Reg,
2365     arg3: Reg,
2366 ) -> Option<Reg> {
2367     let pattern0_0 = arg0;
2368     let pattern1_0 = arg1;
2369     let pattern2_0 = arg2;
2370     let pattern3_0 = arg3;
2371     // Rule at src/isa/aarch64/inst.isle line 1634.
2372     let expr0_0 = ALUOp3::MSub;
2373     let expr1_0 = constructor_alu_rrrr(
2374         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2375     )?;
2376     return Some(expr1_0);
2377 }
2378 
2379 // Generated as internal constructor for term uqadd.
2380 pub fn constructor_uqadd<C: Context>(
2381     ctx: &mut C,
2382     arg0: Reg,
2383     arg1: Reg,
2384     arg2: &VectorSize,
2385 ) -> Option<Reg> {
2386     let pattern0_0 = arg0;
2387     let pattern1_0 = arg1;
2388     let pattern2_0 = arg2;
2389     // Rule at src/isa/aarch64/inst.isle line 1638.
2390     let expr0_0 = VecALUOp::Uqadd;
2391     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2392     return Some(expr1_0);
2393 }
2394 
2395 // Generated as internal constructor for term sqadd.
2396 pub fn constructor_sqadd<C: Context>(
2397     ctx: &mut C,
2398     arg0: Reg,
2399     arg1: Reg,
2400     arg2: &VectorSize,
2401 ) -> Option<Reg> {
2402     let pattern0_0 = arg0;
2403     let pattern1_0 = arg1;
2404     let pattern2_0 = arg2;
2405     // Rule at src/isa/aarch64/inst.isle line 1642.
2406     let expr0_0 = VecALUOp::Sqadd;
2407     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2408     return Some(expr1_0);
2409 }
2410 
2411 // Generated as internal constructor for term uqsub.
2412 pub fn constructor_uqsub<C: Context>(
2413     ctx: &mut C,
2414     arg0: Reg,
2415     arg1: Reg,
2416     arg2: &VectorSize,
2417 ) -> Option<Reg> {
2418     let pattern0_0 = arg0;
2419     let pattern1_0 = arg1;
2420     let pattern2_0 = arg2;
2421     // Rule at src/isa/aarch64/inst.isle line 1646.
2422     let expr0_0 = VecALUOp::Uqsub;
2423     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2424     return Some(expr1_0);
2425 }
2426 
2427 // Generated as internal constructor for term sqsub.
2428 pub fn constructor_sqsub<C: Context>(
2429     ctx: &mut C,
2430     arg0: Reg,
2431     arg1: Reg,
2432     arg2: &VectorSize,
2433 ) -> Option<Reg> {
2434     let pattern0_0 = arg0;
2435     let pattern1_0 = arg1;
2436     let pattern2_0 = arg2;
2437     // Rule at src/isa/aarch64/inst.isle line 1650.
2438     let expr0_0 = VecALUOp::Sqsub;
2439     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2440     return Some(expr1_0);
2441 }
2442 
2443 // Generated as internal constructor for term umulh.
2444 pub fn constructor_umulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2445     let pattern0_0 = arg0;
2446     let pattern1_0 = arg1;
2447     let pattern2_0 = arg2;
2448     // Rule at src/isa/aarch64/inst.isle line 1654.
2449     let expr0_0 = ALUOp::UMulH;
2450     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2451     return Some(expr1_0);
2452 }
2453 
2454 // Generated as internal constructor for term smulh.
2455 pub fn constructor_smulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2456     let pattern0_0 = arg0;
2457     let pattern1_0 = arg1;
2458     let pattern2_0 = arg2;
2459     // Rule at src/isa/aarch64/inst.isle line 1658.
2460     let expr0_0 = ALUOp::SMulH;
2461     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2462     return Some(expr1_0);
2463 }
2464 
2465 // Generated as internal constructor for term mul.
2466 pub fn constructor_mul<C: Context>(
2467     ctx: &mut C,
2468     arg0: Reg,
2469     arg1: Reg,
2470     arg2: &VectorSize,
2471 ) -> Option<Reg> {
2472     let pattern0_0 = arg0;
2473     let pattern1_0 = arg1;
2474     let pattern2_0 = arg2;
2475     // Rule at src/isa/aarch64/inst.isle line 1662.
2476     let expr0_0 = VecALUOp::Mul;
2477     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2478     return Some(expr1_0);
2479 }
2480 
2481 // Generated as internal constructor for term neg.
2482 pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2483     let pattern0_0 = arg0;
2484     let pattern1_0 = arg1;
2485     // Rule at src/isa/aarch64/inst.isle line 1666.
2486     let expr0_0 = VecMisc2::Neg;
2487     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2488     return Some(expr1_0);
2489 }
2490 
2491 // Generated as internal constructor for term rev64.
2492 pub fn constructor_rev64<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2493     let pattern0_0 = arg0;
2494     let pattern1_0 = arg1;
2495     // Rule at src/isa/aarch64/inst.isle line 1670.
2496     let expr0_0 = VecMisc2::Rev64;
2497     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2498     return Some(expr1_0);
2499 }
2500 
2501 // Generated as internal constructor for term xtn64.
2502 pub fn constructor_xtn64<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2503     let pattern0_0 = arg0;
2504     let pattern1_0 = arg1;
2505     // Rule at src/isa/aarch64/inst.isle line 1674.
2506     let expr0_0 = VecRRNarrowOp::Xtn64;
2507     let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2508     return Some(expr1_0);
2509 }
2510 
2511 // Generated as internal constructor for term addp.
2512 pub fn constructor_addp<C: Context>(
2513     ctx: &mut C,
2514     arg0: Reg,
2515     arg1: Reg,
2516     arg2: &VectorSize,
2517 ) -> Option<Reg> {
2518     let pattern0_0 = arg0;
2519     let pattern1_0 = arg1;
2520     let pattern2_0 = arg2;
2521     // Rule at src/isa/aarch64/inst.isle line 1678.
2522     let expr0_0 = VecALUOp::Addp;
2523     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2524     return Some(expr1_0);
2525 }
2526 
2527 // Generated as internal constructor for term addv.
2528 pub fn constructor_addv<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2529     let pattern0_0 = arg0;
2530     let pattern1_0 = arg1;
2531     // Rule at src/isa/aarch64/inst.isle line 1682.
2532     let expr0_0 = VecLanesOp::Addv;
2533     let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2534     return Some(expr1_0);
2535 }
2536 
2537 // Generated as internal constructor for term shll32.
2538 pub fn constructor_shll32<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2539     let pattern0_0 = arg0;
2540     let pattern1_0 = arg1;
2541     // Rule at src/isa/aarch64/inst.isle line 1686.
2542     let expr0_0 = VecRRLongOp::Shll32;
2543     let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2544     return Some(expr1_0);
2545 }
2546 
2547 // Generated as internal constructor for term umlal32.
2548 pub fn constructor_umlal32<C: Context>(
2549     ctx: &mut C,
2550     arg0: Reg,
2551     arg1: Reg,
2552     arg2: Reg,
2553     arg3: bool,
2554 ) -> Option<Reg> {
2555     let pattern0_0 = arg0;
2556     let pattern1_0 = arg1;
2557     let pattern2_0 = arg2;
2558     let pattern3_0 = arg3;
2559     // Rule at src/isa/aarch64/inst.isle line 1690.
2560     let expr0_0 = VecRRRLongOp::Umlal32;
2561     let expr1_0 = constructor_vec_rrrr_long(
2562         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2563     )?;
2564     return Some(expr1_0);
2565 }
2566 
2567 // Generated as internal constructor for term smull8.
2568 pub fn constructor_smull8<C: Context>(
2569     ctx: &mut C,
2570     arg0: Reg,
2571     arg1: Reg,
2572     arg2: bool,
2573 ) -> Option<Reg> {
2574     let pattern0_0 = arg0;
2575     let pattern1_0 = arg1;
2576     let pattern2_0 = arg2;
2577     // Rule at src/isa/aarch64/inst.isle line 1694.
2578     let expr0_0 = VecRRRLongOp::Smull8;
2579     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2580     return Some(expr1_0);
2581 }
2582 
2583 // Generated as internal constructor for term umull8.
2584 pub fn constructor_umull8<C: Context>(
2585     ctx: &mut C,
2586     arg0: Reg,
2587     arg1: Reg,
2588     arg2: bool,
2589 ) -> Option<Reg> {
2590     let pattern0_0 = arg0;
2591     let pattern1_0 = arg1;
2592     let pattern2_0 = arg2;
2593     // Rule at src/isa/aarch64/inst.isle line 1698.
2594     let expr0_0 = VecRRRLongOp::Umull8;
2595     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2596     return Some(expr1_0);
2597 }
2598 
2599 // Generated as internal constructor for term smull16.
2600 pub fn constructor_smull16<C: Context>(
2601     ctx: &mut C,
2602     arg0: Reg,
2603     arg1: Reg,
2604     arg2: bool,
2605 ) -> Option<Reg> {
2606     let pattern0_0 = arg0;
2607     let pattern1_0 = arg1;
2608     let pattern2_0 = arg2;
2609     // Rule at src/isa/aarch64/inst.isle line 1702.
2610     let expr0_0 = VecRRRLongOp::Smull16;
2611     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2612     return Some(expr1_0);
2613 }
2614 
2615 // Generated as internal constructor for term umull16.
2616 pub fn constructor_umull16<C: Context>(
2617     ctx: &mut C,
2618     arg0: Reg,
2619     arg1: Reg,
2620     arg2: bool,
2621 ) -> Option<Reg> {
2622     let pattern0_0 = arg0;
2623     let pattern1_0 = arg1;
2624     let pattern2_0 = arg2;
2625     // Rule at src/isa/aarch64/inst.isle line 1706.
2626     let expr0_0 = VecRRRLongOp::Umull16;
2627     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2628     return Some(expr1_0);
2629 }
2630 
2631 // Generated as internal constructor for term smull32.
2632 pub fn constructor_smull32<C: Context>(
2633     ctx: &mut C,
2634     arg0: Reg,
2635     arg1: Reg,
2636     arg2: bool,
2637 ) -> Option<Reg> {
2638     let pattern0_0 = arg0;
2639     let pattern1_0 = arg1;
2640     let pattern2_0 = arg2;
2641     // Rule at src/isa/aarch64/inst.isle line 1710.
2642     let expr0_0 = VecRRRLongOp::Smull32;
2643     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2644     return Some(expr1_0);
2645 }
2646 
2647 // Generated as internal constructor for term umull32.
2648 pub fn constructor_umull32<C: Context>(
2649     ctx: &mut C,
2650     arg0: Reg,
2651     arg1: Reg,
2652     arg2: bool,
2653 ) -> Option<Reg> {
2654     let pattern0_0 = arg0;
2655     let pattern1_0 = arg1;
2656     let pattern2_0 = arg2;
2657     // Rule at src/isa/aarch64/inst.isle line 1714.
2658     let expr0_0 = VecRRRLongOp::Umull32;
2659     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2660     return Some(expr1_0);
2661 }
2662 
2663 // Generated as internal constructor for term asr.
2664 pub fn constructor_asr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2665     let pattern0_0 = arg0;
2666     let pattern1_0 = arg1;
2667     let pattern2_0 = arg2;
2668     // Rule at src/isa/aarch64/inst.isle line 1718.
2669     let expr0_0 = ALUOp::Asr;
2670     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2671     return Some(expr1_0);
2672 }
2673 
2674 // Generated as internal constructor for term asr_imm.
2675 pub fn constructor_asr_imm<C: Context>(
2676     ctx: &mut C,
2677     arg0: Type,
2678     arg1: Reg,
2679     arg2: ImmShift,
2680 ) -> Option<Reg> {
2681     let pattern0_0 = arg0;
2682     let pattern1_0 = arg1;
2683     let pattern2_0 = arg2;
2684     // Rule at src/isa/aarch64/inst.isle line 1721.
2685     let expr0_0 = ALUOp::Asr;
2686     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2687     return Some(expr1_0);
2688 }
2689 
2690 // Generated as internal constructor for term lsr.
2691 pub fn constructor_lsr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2692     let pattern0_0 = arg0;
2693     let pattern1_0 = arg1;
2694     let pattern2_0 = arg2;
2695     // Rule at src/isa/aarch64/inst.isle line 1725.
2696     let expr0_0 = ALUOp::Lsr;
2697     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2698     return Some(expr1_0);
2699 }
2700 
2701 // Generated as internal constructor for term lsr_imm.
2702 pub fn constructor_lsr_imm<C: Context>(
2703     ctx: &mut C,
2704     arg0: Type,
2705     arg1: Reg,
2706     arg2: ImmShift,
2707 ) -> Option<Reg> {
2708     let pattern0_0 = arg0;
2709     let pattern1_0 = arg1;
2710     let pattern2_0 = arg2;
2711     // Rule at src/isa/aarch64/inst.isle line 1728.
2712     let expr0_0 = ALUOp::Lsr;
2713     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2714     return Some(expr1_0);
2715 }
2716 
2717 // Generated as internal constructor for term lsl.
2718 pub fn constructor_lsl<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2719     let pattern0_0 = arg0;
2720     let pattern1_0 = arg1;
2721     let pattern2_0 = arg2;
2722     // Rule at src/isa/aarch64/inst.isle line 1732.
2723     let expr0_0 = ALUOp::Lsl;
2724     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2725     return Some(expr1_0);
2726 }
2727 
2728 // Generated as internal constructor for term lsl_imm.
2729 pub fn constructor_lsl_imm<C: Context>(
2730     ctx: &mut C,
2731     arg0: Type,
2732     arg1: Reg,
2733     arg2: ImmShift,
2734 ) -> Option<Reg> {
2735     let pattern0_0 = arg0;
2736     let pattern1_0 = arg1;
2737     let pattern2_0 = arg2;
2738     // Rule at src/isa/aarch64/inst.isle line 1735.
2739     let expr0_0 = ALUOp::Lsl;
2740     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2741     return Some(expr1_0);
2742 }
2743 
2744 // Generated as internal constructor for term a64_udiv.
2745 pub fn constructor_a64_udiv<C: Context>(
2746     ctx: &mut C,
2747     arg0: Type,
2748     arg1: Reg,
2749     arg2: Reg,
2750 ) -> Option<Reg> {
2751     let pattern0_0 = arg0;
2752     let pattern1_0 = arg1;
2753     let pattern2_0 = arg2;
2754     // Rule at src/isa/aarch64/inst.isle line 1739.
2755     let expr0_0 = ALUOp::UDiv;
2756     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2757     return Some(expr1_0);
2758 }
2759 
2760 // Generated as internal constructor for term a64_sdiv.
2761 pub fn constructor_a64_sdiv<C: Context>(
2762     ctx: &mut C,
2763     arg0: Type,
2764     arg1: Reg,
2765     arg2: Reg,
2766 ) -> Option<Reg> {
2767     let pattern0_0 = arg0;
2768     let pattern1_0 = arg1;
2769     let pattern2_0 = arg2;
2770     // Rule at src/isa/aarch64/inst.isle line 1743.
2771     let expr0_0 = ALUOp::SDiv;
2772     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2773     return Some(expr1_0);
2774 }
2775 
2776 // Generated as internal constructor for term not.
2777 pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2778     let pattern0_0 = arg0;
2779     let pattern1_0 = arg1;
2780     // Rule at src/isa/aarch64/inst.isle line 1747.
2781     let expr0_0 = VecMisc2::Not;
2782     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2783     return Some(expr1_0);
2784 }
2785 
2786 // Generated as internal constructor for term orr_not.
2787 pub fn constructor_orr_not<C: Context>(
2788     ctx: &mut C,
2789     arg0: Type,
2790     arg1: Reg,
2791     arg2: Reg,
2792 ) -> Option<Reg> {
2793     let pattern0_0 = arg0;
2794     let pattern1_0 = arg1;
2795     let pattern2_0 = arg2;
2796     // Rule at src/isa/aarch64/inst.isle line 1752.
2797     let expr0_0 = ALUOp::OrrNot;
2798     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2799     return Some(expr1_0);
2800 }
2801 
2802 // Generated as internal constructor for term orr_not_shift.
2803 pub fn constructor_orr_not_shift<C: Context>(
2804     ctx: &mut C,
2805     arg0: Type,
2806     arg1: Reg,
2807     arg2: Reg,
2808     arg3: ShiftOpAndAmt,
2809 ) -> Option<Reg> {
2810     let pattern0_0 = arg0;
2811     let pattern1_0 = arg1;
2812     let pattern2_0 = arg2;
2813     let pattern3_0 = arg3;
2814     // Rule at src/isa/aarch64/inst.isle line 1755.
2815     let expr0_0 = ALUOp::OrrNot;
2816     let expr1_0 = constructor_alu_rrr_shift(
2817         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2818     )?;
2819     return Some(expr1_0);
2820 }
2821 
2822 // Generated as internal constructor for term orr.
2823 pub fn constructor_orr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2824     let pattern0_0 = arg0;
2825     let pattern1_0 = arg1;
2826     let pattern2_0 = arg2;
2827     // Rule at src/isa/aarch64/inst.isle line 1760.
2828     let expr0_0 = ALUOp::Orr;
2829     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2830     return Some(expr1_0);
2831 }
2832 
2833 // Generated as internal constructor for term orr_imm.
2834 pub fn constructor_orr_imm<C: Context>(
2835     ctx: &mut C,
2836     arg0: Type,
2837     arg1: Reg,
2838     arg2: ImmLogic,
2839 ) -> Option<Reg> {
2840     let pattern0_0 = arg0;
2841     let pattern1_0 = arg1;
2842     let pattern2_0 = arg2;
2843     // Rule at src/isa/aarch64/inst.isle line 1763.
2844     let expr0_0 = ALUOp::Orr;
2845     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2846     return Some(expr1_0);
2847 }
2848 
2849 // Generated as internal constructor for term orr_vec.
2850 pub fn constructor_orr_vec<C: Context>(
2851     ctx: &mut C,
2852     arg0: Reg,
2853     arg1: Reg,
2854     arg2: &VectorSize,
2855 ) -> Option<Reg> {
2856     let pattern0_0 = arg0;
2857     let pattern1_0 = arg1;
2858     let pattern2_0 = arg2;
2859     // Rule at src/isa/aarch64/inst.isle line 1766.
2860     let expr0_0 = VecALUOp::Orr;
2861     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2862     return Some(expr1_0);
2863 }
2864 
2865 // Generated as internal constructor for term and_imm.
2866 pub fn constructor_and_imm<C: Context>(
2867     ctx: &mut C,
2868     arg0: Type,
2869     arg1: Reg,
2870     arg2: ImmLogic,
2871 ) -> Option<Reg> {
2872     let pattern0_0 = arg0;
2873     let pattern1_0 = arg1;
2874     let pattern2_0 = arg2;
2875     // Rule at src/isa/aarch64/inst.isle line 1771.
2876     let expr0_0 = ALUOp::And;
2877     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2878     return Some(expr1_0);
2879 }
2880 
2881 // Generated as internal constructor for term and_vec.
2882 pub fn constructor_and_vec<C: Context>(
2883     ctx: &mut C,
2884     arg0: Reg,
2885     arg1: Reg,
2886     arg2: &VectorSize,
2887 ) -> Option<Reg> {
2888     let pattern0_0 = arg0;
2889     let pattern1_0 = arg1;
2890     let pattern2_0 = arg2;
2891     // Rule at src/isa/aarch64/inst.isle line 1774.
2892     let expr0_0 = VecALUOp::And;
2893     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2894     return Some(expr1_0);
2895 }
2896 
2897 // Generated as internal constructor for term eor_vec.
2898 pub fn constructor_eor_vec<C: Context>(
2899     ctx: &mut C,
2900     arg0: Reg,
2901     arg1: Reg,
2902     arg2: &VectorSize,
2903 ) -> Option<Reg> {
2904     let pattern0_0 = arg0;
2905     let pattern1_0 = arg1;
2906     let pattern2_0 = arg2;
2907     // Rule at src/isa/aarch64/inst.isle line 1778.
2908     let expr0_0 = VecALUOp::Eor;
2909     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2910     return Some(expr1_0);
2911 }
2912 
2913 // Generated as internal constructor for term bic_vec.
2914 pub fn constructor_bic_vec<C: Context>(
2915     ctx: &mut C,
2916     arg0: Reg,
2917     arg1: Reg,
2918     arg2: &VectorSize,
2919 ) -> Option<Reg> {
2920     let pattern0_0 = arg0;
2921     let pattern1_0 = arg1;
2922     let pattern2_0 = arg2;
2923     // Rule at src/isa/aarch64/inst.isle line 1782.
2924     let expr0_0 = VecALUOp::Bic;
2925     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2926     return Some(expr1_0);
2927 }
2928 
2929 // Generated as internal constructor for term sshl.
2930 pub fn constructor_sshl<C: Context>(
2931     ctx: &mut C,
2932     arg0: Reg,
2933     arg1: Reg,
2934     arg2: &VectorSize,
2935 ) -> Option<Reg> {
2936     let pattern0_0 = arg0;
2937     let pattern1_0 = arg1;
2938     let pattern2_0 = arg2;
2939     // Rule at src/isa/aarch64/inst.isle line 1786.
2940     let expr0_0 = VecALUOp::Sshl;
2941     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2942     return Some(expr1_0);
2943 }
2944 
2945 // Generated as internal constructor for term ushl.
2946 pub fn constructor_ushl<C: Context>(
2947     ctx: &mut C,
2948     arg0: Reg,
2949     arg1: Reg,
2950     arg2: &VectorSize,
2951 ) -> Option<Reg> {
2952     let pattern0_0 = arg0;
2953     let pattern1_0 = arg1;
2954     let pattern2_0 = arg2;
2955     // Rule at src/isa/aarch64/inst.isle line 1790.
2956     let expr0_0 = VecALUOp::Ushl;
2957     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2958     return Some(expr1_0);
2959 }
2960 
2961 // Generated as internal constructor for term a64_rotr.
2962 pub fn constructor_a64_rotr<C: Context>(
2963     ctx: &mut C,
2964     arg0: Type,
2965     arg1: Reg,
2966     arg2: Reg,
2967 ) -> Option<Reg> {
2968     let pattern0_0 = arg0;
2969     let pattern1_0 = arg1;
2970     let pattern2_0 = arg2;
2971     // Rule at src/isa/aarch64/inst.isle line 1795.
2972     let expr0_0 = ALUOp::RotR;
2973     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2974     return Some(expr1_0);
2975 }
2976 
2977 // Generated as internal constructor for term a64_rotr_imm.
2978 pub fn constructor_a64_rotr_imm<C: Context>(
2979     ctx: &mut C,
2980     arg0: Type,
2981     arg1: Reg,
2982     arg2: ImmShift,
2983 ) -> Option<Reg> {
2984     let pattern0_0 = arg0;
2985     let pattern1_0 = arg1;
2986     let pattern2_0 = arg2;
2987     // Rule at src/isa/aarch64/inst.isle line 1798.
2988     let expr0_0 = ALUOp::RotR;
2989     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2990     return Some(expr1_0);
2991 }
2992 
2993 // Generated as internal constructor for term rbit.
2994 pub fn constructor_rbit<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2995     let pattern0_0 = arg0;
2996     let pattern1_0 = arg1;
2997     // Rule at src/isa/aarch64/inst.isle line 1803.
2998     let expr0_0 = BitOp::RBit;
2999     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3000     return Some(expr1_0);
3001 }
3002 
3003 // Generated as internal constructor for term a64_clz.
3004 pub fn constructor_a64_clz<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
3005     let pattern0_0 = arg0;
3006     let pattern1_0 = arg1;
3007     // Rule at src/isa/aarch64/inst.isle line 1808.
3008     let expr0_0 = BitOp::Clz;
3009     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3010     return Some(expr1_0);
3011 }
3012 
3013 // Generated as internal constructor for term a64_cls.
3014 pub fn constructor_a64_cls<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
3015     let pattern0_0 = arg0;
3016     let pattern1_0 = arg1;
3017     // Rule at src/isa/aarch64/inst.isle line 1813.
3018     let expr0_0 = BitOp::Cls;
3019     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3020     return Some(expr1_0);
3021 }
3022 
3023 // Generated as internal constructor for term eon.
3024 pub fn constructor_eon<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
3025     let pattern0_0 = arg0;
3026     let pattern1_0 = arg1;
3027     let pattern2_0 = arg2;
3028     // Rule at src/isa/aarch64/inst.isle line 1818.
3029     let expr0_0 = ALUOp::EorNot;
3030     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3031     return Some(expr1_0);
3032 }
3033 
3034 // Generated as internal constructor for term vec_cnt.
3035 pub fn constructor_vec_cnt<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3036     let pattern0_0 = arg0;
3037     let pattern1_0 = arg1;
3038     // Rule at src/isa/aarch64/inst.isle line 1823.
3039     let expr0_0 = VecMisc2::Cnt;
3040     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3041     return Some(expr1_0);
3042 }
3043 
3044 // Generated as internal constructor for term imm.
3045 pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
3046     let pattern0_0 = arg0;
3047     if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) {
3048         let pattern2_0 = arg1;
3049         let closure3 = || {
3050             let expr0_0: Type = I64;
3051             return Some(expr0_0);
3052         };
3053         if let Some(pattern3_0) = closure3() {
3054             if let Some(pattern4_0) = C::imm_logic_from_u64(ctx, pattern2_0, pattern3_0) {
3055                 // Rule at src/isa/aarch64/inst.isle line 1838.
3056                 let expr0_0: Type = I64;
3057                 let expr1_0 = C::zero_reg(ctx);
3058                 let expr2_0 = constructor_orr_imm(ctx, expr0_0, expr1_0, pattern4_0)?;
3059                 return Some(expr2_0);
3060             }
3061         }
3062         if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) {
3063             // Rule at src/isa/aarch64/inst.isle line 1830.
3064             let expr0_0 = OperandSize::Size64;
3065             let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?;
3066             return Some(expr1_0);
3067         }
3068         if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) {
3069             // Rule at src/isa/aarch64/inst.isle line 1834.
3070             let expr0_0 = OperandSize::Size64;
3071             let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?;
3072             return Some(expr1_0);
3073         }
3074         // Rule at src/isa/aarch64/inst.isle line 1845.
3075         let expr0_0 = C::load_constant64_full(ctx, pattern2_0);
3076         return Some(expr0_0);
3077     }
3078     return None;
3079 }
3080 
3081 // Generated as internal constructor for term put_in_reg_sext32.
3082 pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3083     let pattern0_0 = arg0;
3084     let pattern1_0 = C::value_type(ctx, pattern0_0);
3085     if pattern1_0 == I32 {
3086         // Rule at src/isa/aarch64/inst.isle line 1856.
3087         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3088         return Some(expr0_0);
3089     }
3090     if pattern1_0 == I64 {
3091         // Rule at src/isa/aarch64/inst.isle line 1857.
3092         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3093         return Some(expr0_0);
3094     }
3095     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3096         // Rule at src/isa/aarch64/inst.isle line 1852.
3097         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3098         let expr1_0: bool = true;
3099         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3100         let expr3_0: u8 = 32;
3101         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3102         return Some(expr4_0);
3103     }
3104     return None;
3105 }
3106 
3107 // Generated as internal constructor for term put_in_reg_zext32.
3108 pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3109     let pattern0_0 = arg0;
3110     let pattern1_0 = C::value_type(ctx, pattern0_0);
3111     if pattern1_0 == I32 {
3112         // Rule at src/isa/aarch64/inst.isle line 1865.
3113         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3114         return Some(expr0_0);
3115     }
3116     if pattern1_0 == I64 {
3117         // Rule at src/isa/aarch64/inst.isle line 1866.
3118         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3119         return Some(expr0_0);
3120     }
3121     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3122         // Rule at src/isa/aarch64/inst.isle line 1861.
3123         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3124         let expr1_0: bool = false;
3125         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3126         let expr3_0: u8 = 32;
3127         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3128         return Some(expr4_0);
3129     }
3130     return None;
3131 }
3132 
3133 // Generated as internal constructor for term put_in_reg_sext64.
3134 pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3135     let pattern0_0 = arg0;
3136     let pattern1_0 = C::value_type(ctx, pattern0_0);
3137     if pattern1_0 == I64 {
3138         // Rule at src/isa/aarch64/inst.isle line 1874.
3139         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3140         return Some(expr0_0);
3141     }
3142     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3143         // Rule at src/isa/aarch64/inst.isle line 1870.
3144         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3145         let expr1_0: bool = true;
3146         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3147         let expr3_0: u8 = 64;
3148         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3149         return Some(expr4_0);
3150     }
3151     return None;
3152 }
3153 
3154 // Generated as internal constructor for term put_in_reg_zext64.
3155 pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3156     let pattern0_0 = arg0;
3157     let pattern1_0 = C::value_type(ctx, pattern0_0);
3158     if pattern1_0 == I64 {
3159         // Rule at src/isa/aarch64/inst.isle line 1882.
3160         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3161         return Some(expr0_0);
3162     }
3163     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3164         // Rule at src/isa/aarch64/inst.isle line 1878.
3165         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3166         let expr1_0: bool = false;
3167         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3168         let expr3_0: u8 = 64;
3169         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3170         return Some(expr4_0);
3171     }
3172     return None;
3173 }
3174 
3175 // Generated as internal constructor for term trap_if_zero_divisor.
3176 pub fn constructor_trap_if_zero_divisor<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3177     let pattern0_0 = arg0;
3178     // Rule at src/isa/aarch64/inst.isle line 1887.
3179     let expr0_0 = C::cond_br_zero(ctx, pattern0_0);
3180     let expr1_0 = C::trap_code_division_by_zero(ctx);
3181     let expr2_0 = MInst::TrapIf {
3182         kind: expr0_0,
3183         trap_code: expr1_0,
3184     };
3185     let expr3_0 = C::emit(ctx, &expr2_0);
3186     return Some(pattern0_0);
3187 }
3188 
3189 // Generated as internal constructor for term size_from_ty.
3190 pub fn constructor_size_from_ty<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
3191     let pattern0_0 = arg0;
3192     if pattern0_0 == I64 {
3193         // Rule at src/isa/aarch64/inst.isle line 1893.
3194         let expr0_0 = OperandSize::Size64;
3195         return Some(expr0_0);
3196     }
3197     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
3198         // Rule at src/isa/aarch64/inst.isle line 1892.
3199         let expr0_0 = OperandSize::Size32;
3200         return Some(expr0_0);
3201     }
3202     return None;
3203 }
3204 
3205 // Generated as internal constructor for term trap_if_div_overflow.
3206 pub fn constructor_trap_if_div_overflow<C: Context>(
3207     ctx: &mut C,
3208     arg0: Type,
3209     arg1: Reg,
3210     arg2: Reg,
3211 ) -> Option<Reg> {
3212     let pattern0_0 = arg0;
3213     let pattern1_0 = arg1;
3214     let pattern2_0 = arg2;
3215     // Rule at src/isa/aarch64/inst.isle line 1899.
3216     let expr0_0 = ALUOp::AddS;
3217     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
3218     let expr2_0 = C::writable_zero_reg(ctx);
3219     let expr3_0: u8 = 1;
3220     let expr4_0 = C::u8_into_imm12(ctx, expr3_0);
3221     let expr5_0 = MInst::AluRRImm12 {
3222         alu_op: expr0_0,
3223         size: expr1_0,
3224         rd: expr2_0,
3225         rn: pattern2_0,
3226         imm12: expr4_0,
3227     };
3228     let expr6_0 = C::emit(ctx, &expr5_0);
3229     let expr7_0 = constructor_size_from_ty(ctx, pattern0_0)?;
3230     let expr8_0: u8 = 1;
3231     let expr9_0 = C::u8_into_uimm5(ctx, expr8_0);
3232     let expr10_0: bool = false;
3233     let expr11_0: bool = false;
3234     let expr12_0: bool = false;
3235     let expr13_0: bool = false;
3236     let expr14_0 = C::nzcv(ctx, expr10_0, expr11_0, expr12_0, expr13_0);
3237     let expr15_0 = Cond::Eq;
3238     let expr16_0 = MInst::CCmpImm {
3239         size: expr7_0,
3240         rn: pattern1_0,
3241         imm: expr9_0,
3242         nzcv: expr14_0,
3243         cond: expr15_0,
3244     };
3245     let expr17_0 = C::emit(ctx, &expr16_0);
3246     let expr18_0 = Cond::Vs;
3247     let expr19_0 = C::cond_br_cond(ctx, &expr18_0);
3248     let expr20_0 = C::trap_code_integer_overflow(ctx);
3249     let expr21_0 = MInst::TrapIf {
3250         kind: expr19_0,
3251         trap_code: expr20_0,
3252     };
3253     let expr22_0 = C::emit(ctx, &expr21_0);
3254     return Some(pattern1_0);
3255 }
3256 
3257 // Generated as internal constructor for term alu_rs_imm_logic_commutative.
3258 pub fn constructor_alu_rs_imm_logic_commutative<C: Context>(
3259     ctx: &mut C,
3260     arg0: &ALUOp,
3261     arg1: Type,
3262     arg2: Value,
3263     arg3: Value,
3264 ) -> Option<Reg> {
3265     let pattern0_0 = arg0;
3266     let pattern1_0 = arg1;
3267     let pattern2_0 = arg2;
3268     if let Some(pattern3_0) = C::def_inst(ctx, pattern2_0) {
3269         let pattern4_0 = C::inst_data(ctx, pattern3_0);
3270         match &pattern4_0 {
3271             &InstructionData::UnaryImm {
3272                 opcode: ref pattern5_0,
3273                 imm: pattern5_1,
3274             } => {
3275                 if let &Opcode::Iconst = pattern5_0 {
3276                     let closure7 = || {
3277                         return Some(pattern1_0);
3278                     };
3279                     if let Some(pattern7_0) = closure7() {
3280                         if let Some(pattern8_0) =
3281                             C::imm_logic_from_imm64(ctx, pattern5_1, pattern7_0)
3282                         {
3283                             let pattern9_0 = arg3;
3284                             // Rule at src/isa/aarch64/inst.isle line 1944.
3285                             let expr0_0 = C::put_in_reg(ctx, pattern9_0);
3286                             let expr1_0 = constructor_alu_rr_imm_logic(
3287                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0,
3288                             )?;
3289                             return Some(expr1_0);
3290                         }
3291                     }
3292                 }
3293             }
3294             &InstructionData::Binary {
3295                 opcode: ref pattern5_0,
3296                 args: ref pattern5_1,
3297             } => {
3298                 if let &Opcode::Ishl = pattern5_0 {
3299                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3300                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3301                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
3302                         if let &InstructionData::UnaryImm {
3303                             opcode: ref pattern10_0,
3304                             imm: pattern10_1,
3305                         } = &pattern9_0
3306                         {
3307                             if let &Opcode::Iconst = pattern10_0 {
3308                                 let closure12 = || {
3309                                     return Some(pattern1_0);
3310                                 };
3311                                 if let Some(pattern12_0) = closure12() {
3312                                     if let Some(pattern13_0) =
3313                                         C::lshl_from_imm64(ctx, pattern10_1, pattern12_0)
3314                                     {
3315                                         let pattern14_0 = arg3;
3316                                         // Rule at src/isa/aarch64/inst.isle line 1950.
3317                                         let expr0_0 = C::put_in_reg(ctx, pattern14_0);
3318                                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3319                                         let expr2_0 = constructor_alu_rrr_shift(
3320                                             ctx,
3321                                             pattern0_0,
3322                                             pattern1_0,
3323                                             expr0_0,
3324                                             expr1_0,
3325                                             pattern13_0,
3326                                         )?;
3327                                         return Some(expr2_0);
3328                                     }
3329                                 }
3330                             }
3331                         }
3332                     }
3333                 }
3334             }
3335             _ => {}
3336         }
3337     }
3338     let pattern3_0 = arg3;
3339     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3340         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3341         match &pattern5_0 {
3342             &InstructionData::UnaryImm {
3343                 opcode: ref pattern6_0,
3344                 imm: pattern6_1,
3345             } => {
3346                 if let &Opcode::Iconst = pattern6_0 {
3347                     let closure8 = || {
3348                         return Some(pattern1_0);
3349                     };
3350                     if let Some(pattern8_0) = closure8() {
3351                         if let Some(pattern9_0) =
3352                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3353                         {
3354                             // Rule at src/isa/aarch64/inst.isle line 1942.
3355                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3356                             let expr1_0 = constructor_alu_rr_imm_logic(
3357                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3358                             )?;
3359                             return Some(expr1_0);
3360                         }
3361                     }
3362                 }
3363             }
3364             &InstructionData::Binary {
3365                 opcode: ref pattern6_0,
3366                 args: ref pattern6_1,
3367             } => {
3368                 if let &Opcode::Ishl = pattern6_0 {
3369                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3370                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3371                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3372                         if let &InstructionData::UnaryImm {
3373                             opcode: ref pattern11_0,
3374                             imm: pattern11_1,
3375                         } = &pattern10_0
3376                         {
3377                             if let &Opcode::Iconst = pattern11_0 {
3378                                 let closure13 = || {
3379                                     return Some(pattern1_0);
3380                                 };
3381                                 if let Some(pattern13_0) = closure13() {
3382                                     if let Some(pattern14_0) =
3383                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3384                                     {
3385                                         // Rule at src/isa/aarch64/inst.isle line 1948.
3386                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3387                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3388                                         let expr2_0 = constructor_alu_rrr_shift(
3389                                             ctx,
3390                                             pattern0_0,
3391                                             pattern1_0,
3392                                             expr0_0,
3393                                             expr1_0,
3394                                             pattern14_0,
3395                                         )?;
3396                                         return Some(expr2_0);
3397                                     }
3398                                 }
3399                             }
3400                         }
3401                     }
3402                 }
3403             }
3404             _ => {}
3405         }
3406     }
3407     // Rule at src/isa/aarch64/inst.isle line 1938.
3408     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3409     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3410     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3411     return Some(expr2_0);
3412 }
3413 
3414 // Generated as internal constructor for term alu_rs_imm_logic.
3415 pub fn constructor_alu_rs_imm_logic<C: Context>(
3416     ctx: &mut C,
3417     arg0: &ALUOp,
3418     arg1: Type,
3419     arg2: Value,
3420     arg3: Value,
3421 ) -> Option<Reg> {
3422     let pattern0_0 = arg0;
3423     let pattern1_0 = arg1;
3424     let pattern2_0 = arg2;
3425     let pattern3_0 = arg3;
3426     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3427         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3428         match &pattern5_0 {
3429             &InstructionData::UnaryImm {
3430                 opcode: ref pattern6_0,
3431                 imm: pattern6_1,
3432             } => {
3433                 if let &Opcode::Iconst = pattern6_0 {
3434                     let closure8 = || {
3435                         return Some(pattern1_0);
3436                     };
3437                     if let Some(pattern8_0) = closure8() {
3438                         if let Some(pattern9_0) =
3439                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3440                         {
3441                             // Rule at src/isa/aarch64/inst.isle line 1958.
3442                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3443                             let expr1_0 = constructor_alu_rr_imm_logic(
3444                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3445                             )?;
3446                             return Some(expr1_0);
3447                         }
3448                     }
3449                 }
3450             }
3451             &InstructionData::Binary {
3452                 opcode: ref pattern6_0,
3453                 args: ref pattern6_1,
3454             } => {
3455                 if let &Opcode::Ishl = pattern6_0 {
3456                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3457                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3458                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3459                         if let &InstructionData::UnaryImm {
3460                             opcode: ref pattern11_0,
3461                             imm: pattern11_1,
3462                         } = &pattern10_0
3463                         {
3464                             if let &Opcode::Iconst = pattern11_0 {
3465                                 let closure13 = || {
3466                                     return Some(pattern1_0);
3467                                 };
3468                                 if let Some(pattern13_0) = closure13() {
3469                                     if let Some(pattern14_0) =
3470                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3471                                     {
3472                                         // Rule at src/isa/aarch64/inst.isle line 1960.
3473                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3474                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3475                                         let expr2_0 = constructor_alu_rrr_shift(
3476                                             ctx,
3477                                             pattern0_0,
3478                                             pattern1_0,
3479                                             expr0_0,
3480                                             expr1_0,
3481                                             pattern14_0,
3482                                         )?;
3483                                         return Some(expr2_0);
3484                                     }
3485                                 }
3486                             }
3487                         }
3488                     }
3489                 }
3490             }
3491             _ => {}
3492         }
3493     }
3494     // Rule at src/isa/aarch64/inst.isle line 1956.
3495     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3496     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3497     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3498     return Some(expr2_0);
3499 }
3500 
3501 // Generated as internal constructor for term i128_alu_bitop.
3502 pub fn constructor_i128_alu_bitop<C: Context>(
3503     ctx: &mut C,
3504     arg0: &ALUOp,
3505     arg1: Type,
3506     arg2: Value,
3507     arg3: Value,
3508 ) -> Option<ValueRegs> {
3509     let pattern0_0 = arg0;
3510     let pattern1_0 = arg1;
3511     let pattern2_0 = arg2;
3512     let pattern3_0 = arg3;
3513     // Rule at src/isa/aarch64/inst.isle line 1968.
3514     let expr0_0 = C::put_in_regs(ctx, pattern2_0);
3515     let expr1_0: usize = 0;
3516     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3517     let expr3_0: usize = 1;
3518     let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
3519     let expr5_0 = C::put_in_regs(ctx, pattern3_0);
3520     let expr6_0: usize = 0;
3521     let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
3522     let expr8_0: usize = 1;
3523     let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
3524     let expr10_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr2_0, expr7_0)?;
3525     let expr11_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr4_0, expr9_0)?;
3526     let expr12_0 = C::value_regs(ctx, expr10_0, expr11_0);
3527     return Some(expr12_0);
3528 }
3529 
3530 // Generated as internal constructor for term float_cmp_zero.
3531 pub fn constructor_float_cmp_zero<C: Context>(
3532     ctx: &mut C,
3533     arg0: &FloatCC,
3534     arg1: Reg,
3535     arg2: &VectorSize,
3536 ) -> Option<Reg> {
3537     let pattern0_0 = arg0;
3538     let pattern1_0 = arg1;
3539     let pattern2_0 = arg2;
3540     // Rule at src/isa/aarch64/inst.isle line 2008.
3541     let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0);
3542     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3543     return Some(expr1_0);
3544 }
3545 
3546 // Generated as internal constructor for term float_cmp_zero_swap.
3547 pub fn constructor_float_cmp_zero_swap<C: Context>(
3548     ctx: &mut C,
3549     arg0: &FloatCC,
3550     arg1: Reg,
3551     arg2: &VectorSize,
3552 ) -> Option<Reg> {
3553     let pattern0_0 = arg0;
3554     let pattern1_0 = arg1;
3555     let pattern2_0 = arg2;
3556     // Rule at src/isa/aarch64/inst.isle line 2013.
3557     let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0);
3558     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3559     return Some(expr1_0);
3560 }
3561 
3562 // Generated as internal constructor for term fcmeq0.
3563 pub fn constructor_fcmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3564     let pattern0_0 = arg0;
3565     let pattern1_0 = arg1;
3566     // Rule at src/isa/aarch64/inst.isle line 2018.
3567     let expr0_0 = VecMisc2::Fcmeq0;
3568     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3569     return Some(expr1_0);
3570 }
3571 
3572 // Generated as internal constructor for term int_cmp_zero.
3573 pub fn constructor_int_cmp_zero<C: Context>(
3574     ctx: &mut C,
3575     arg0: &IntCC,
3576     arg1: Reg,
3577     arg2: &VectorSize,
3578 ) -> Option<Reg> {
3579     let pattern0_0 = arg0;
3580     let pattern1_0 = arg1;
3581     let pattern2_0 = arg2;
3582     // Rule at src/isa/aarch64/inst.isle line 2044.
3583     let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0);
3584     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3585     return Some(expr1_0);
3586 }
3587 
3588 // Generated as internal constructor for term int_cmp_zero_swap.
3589 pub fn constructor_int_cmp_zero_swap<C: Context>(
3590     ctx: &mut C,
3591     arg0: &IntCC,
3592     arg1: Reg,
3593     arg2: &VectorSize,
3594 ) -> Option<Reg> {
3595     let pattern0_0 = arg0;
3596     let pattern1_0 = arg1;
3597     let pattern2_0 = arg2;
3598     // Rule at src/isa/aarch64/inst.isle line 2049.
3599     let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0);
3600     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3601     return Some(expr1_0);
3602 }
3603 
3604 // Generated as internal constructor for term cmeq0.
3605 pub fn constructor_cmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3606     let pattern0_0 = arg0;
3607     let pattern1_0 = arg1;
3608     // Rule at src/isa/aarch64/inst.isle line 2054.
3609     let expr0_0 = VecMisc2::Cmeq0;
3610     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3611     return Some(expr1_0);
3612 }
3613 
3614 // Generated as internal constructor for term lower.
3615 pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> {
3616     let pattern0_0 = arg0;
3617     if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
3618         let pattern2_0 = C::value_type(ctx, pattern1_0);
3619         if pattern2_0 == I8 {
3620             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3621             if let &InstructionData::Unary {
3622                 opcode: ref pattern5_0,
3623                 arg: pattern5_1,
3624             } = &pattern4_0
3625             {
3626                 match pattern5_0 {
3627                     &Opcode::Bitrev => {
3628                         // Rule at src/isa/aarch64/lower.isle line 980.
3629                         let expr0_0: Type = I32;
3630                         let expr1_0: Type = I32;
3631                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3632                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3633                         let expr4_0: u8 = 24;
3634                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3635                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3636                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3637                         return Some(expr7_0);
3638                     }
3639                     &Opcode::Clz => {
3640                         // Rule at src/isa/aarch64/lower.isle line 1001.
3641                         let expr0_0: Type = I32;
3642                         let expr1_0: Type = I32;
3643                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3644                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3645                         let expr4_0: u8 = 24;
3646                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3647                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3648                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3649                         return Some(expr7_0);
3650                     }
3651                     &Opcode::Cls => {
3652                         // Rule at src/isa/aarch64/lower.isle line 1048.
3653                         let expr0_0: Type = I32;
3654                         let expr1_0: Type = I32;
3655                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3656                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3657                         let expr4_0: u8 = 24;
3658                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3659                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3660                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3661                         return Some(expr7_0);
3662                     }
3663                     &Opcode::Ctz => {
3664                         // Rule at src/isa/aarch64/lower.isle line 1031.
3665                         let expr0_0: Type = I32;
3666                         let expr1_0: Type = I32;
3667                         let expr2_0: Type = I32;
3668                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3669                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3670                         let expr5_0: Type = I32;
3671                         let expr6_0: u64 = 8388608;
3672                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3673                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3674                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3675                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3676                         return Some(expr10_0);
3677                     }
3678                     &Opcode::Popcnt => {
3679                         // Rule at src/isa/aarch64/lower.isle line 1099.
3680                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3681                         let expr1_0 = ScalarSize::Size32;
3682                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3683                         let expr3_0 = VectorSize::Size8x8;
3684                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3685                         let expr5_0: u8 = 0;
3686                         let expr6_0 = VectorSize::Size8x16;
3687                         let expr7_0 = constructor_mov_from_vec(ctx, expr4_0, expr5_0, &expr6_0)?;
3688                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
3689                         return Some(expr8_0);
3690                     }
3691                     _ => {}
3692                 }
3693             }
3694         }
3695         if pattern2_0 == I16 {
3696             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3697             if let &InstructionData::Unary {
3698                 opcode: ref pattern5_0,
3699                 arg: pattern5_1,
3700             } = &pattern4_0
3701             {
3702                 match pattern5_0 {
3703                     &Opcode::Bitrev => {
3704                         // Rule at src/isa/aarch64/lower.isle line 986.
3705                         let expr0_0: Type = I32;
3706                         let expr1_0: Type = I32;
3707                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3708                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3709                         let expr4_0: u8 = 16;
3710                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3711                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3712                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3713                         return Some(expr7_0);
3714                     }
3715                     &Opcode::Clz => {
3716                         // Rule at src/isa/aarch64/lower.isle line 1004.
3717                         let expr0_0: Type = I32;
3718                         let expr1_0: Type = I32;
3719                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3720                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3721                         let expr4_0: u8 = 16;
3722                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3723                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3724                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3725                         return Some(expr7_0);
3726                     }
3727                     &Opcode::Cls => {
3728                         // Rule at src/isa/aarch64/lower.isle line 1051.
3729                         let expr0_0: Type = I32;
3730                         let expr1_0: Type = I32;
3731                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3732                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3733                         let expr4_0: u8 = 16;
3734                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3735                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3736                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3737                         return Some(expr7_0);
3738                     }
3739                     &Opcode::Ctz => {
3740                         // Rule at src/isa/aarch64/lower.isle line 1034.
3741                         let expr0_0: Type = I32;
3742                         let expr1_0: Type = I32;
3743                         let expr2_0: Type = I32;
3744                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3745                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3746                         let expr5_0: Type = I32;
3747                         let expr6_0: u64 = 32768;
3748                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3749                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3750                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3751                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3752                         return Some(expr10_0);
3753                     }
3754                     &Opcode::Popcnt => {
3755                         // Rule at src/isa/aarch64/lower.isle line 1105.
3756                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3757                         let expr1_0 = ScalarSize::Size32;
3758                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3759                         let expr3_0 = VectorSize::Size8x8;
3760                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3761                         let expr5_0 = VectorSize::Size8x8;
3762                         let expr6_0 = constructor_addp(ctx, expr4_0, expr4_0, &expr5_0)?;
3763                         let expr7_0: u8 = 0;
3764                         let expr8_0 = VectorSize::Size8x16;
3765                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3766                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3767                         return Some(expr10_0);
3768                     }
3769                     _ => {}
3770                 }
3771             }
3772         }
3773         if pattern2_0 == I32 {
3774             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3775             match &pattern4_0 {
3776                 &InstructionData::Binary {
3777                     opcode: ref pattern5_0,
3778                     args: ref pattern5_1,
3779                 } => {
3780                     match pattern5_0 {
3781                         &Opcode::Rotl => {
3782                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3783                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3784                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3785                                 if let &InstructionData::UnaryImm {
3786                                     opcode: ref pattern10_0,
3787                                     imm: pattern10_1,
3788                                 } = &pattern9_0
3789                                 {
3790                                     if let &Opcode::Iconst = pattern10_0 {
3791                                         let closure12 = || {
3792                                             let expr0_0: Type = I32;
3793                                             return Some(expr0_0);
3794                                         };
3795                                         if let Some(pattern12_0) = closure12() {
3796                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3797                                                 ctx,
3798                                                 pattern10_1,
3799                                                 pattern12_0,
3800                                             ) {
3801                                                 // Rule at src/isa/aarch64/lower.isle line 871.
3802                                                 let expr0_0: Type = I32;
3803                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3804                                                 let expr2_0: Type = I32;
3805                                                 let expr3_0 =
3806                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3807                                                 let expr4_0 = constructor_a64_rotr_imm(
3808                                                     ctx, expr0_0, expr1_0, expr3_0,
3809                                                 )?;
3810                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3811                                                 return Some(expr5_0);
3812                                             }
3813                                         }
3814                                     }
3815                                 }
3816                             }
3817                             // Rule at src/isa/aarch64/lower.isle line 861.
3818                             let expr0_0: Type = I32;
3819                             let expr1_0 = C::zero_reg(ctx);
3820                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3821                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3822                             let expr4_0: Type = I32;
3823                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3824                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3825                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3826                             return Some(expr7_0);
3827                         }
3828                         &Opcode::Rotr => {
3829                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3830                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3831                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3832                                 if let &InstructionData::UnaryImm {
3833                                     opcode: ref pattern10_0,
3834                                     imm: pattern10_1,
3835                                 } = &pattern9_0
3836                                 {
3837                                     if let &Opcode::Iconst = pattern10_0 {
3838                                         let closure12 = || {
3839                                             let expr0_0: Type = I32;
3840                                             return Some(expr0_0);
3841                                         };
3842                                         if let Some(pattern12_0) = closure12() {
3843                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3844                                                 ctx,
3845                                                 pattern10_1,
3846                                                 pattern12_0,
3847                                             ) {
3848                                                 // Rule at src/isa/aarch64/lower.isle line 913.
3849                                                 let expr0_0: Type = I32;
3850                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3851                                                 let expr2_0 = constructor_a64_rotr_imm(
3852                                                     ctx,
3853                                                     expr0_0,
3854                                                     expr1_0,
3855                                                     pattern13_0,
3856                                                 )?;
3857                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3858                                                 return Some(expr3_0);
3859                                             }
3860                                         }
3861                                     }
3862                                 }
3863                             }
3864                             // Rule at src/isa/aarch64/lower.isle line 901.
3865                             let expr0_0: Type = I32;
3866                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3867                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3868                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
3869                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3870                             return Some(expr4_0);
3871                         }
3872                         _ => {}
3873                     }
3874                 }
3875                 &InstructionData::Unary {
3876                     opcode: ref pattern5_0,
3877                     arg: pattern5_1,
3878                 } => {
3879                     if let &Opcode::Popcnt = pattern5_0 {
3880                         // Rule at src/isa/aarch64/lower.isle line 1111.
3881                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3882                         let expr1_0 = ScalarSize::Size32;
3883                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3884                         let expr3_0 = VectorSize::Size8x8;
3885                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3886                         let expr5_0 = VectorSize::Size8x8;
3887                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
3888                         let expr7_0: u8 = 0;
3889                         let expr8_0 = VectorSize::Size8x16;
3890                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3891                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3892                         return Some(expr10_0);
3893                     }
3894                 }
3895                 _ => {}
3896             }
3897         }
3898         if pattern2_0 == I64 {
3899             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3900             match &pattern4_0 {
3901                 &InstructionData::Binary {
3902                     opcode: ref pattern5_0,
3903                     args: ref pattern5_1,
3904                 } => {
3905                     match pattern5_0 {
3906                         &Opcode::Umulhi => {
3907                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3908                             // Rule at src/isa/aarch64/lower.isle line 371.
3909                             let expr0_0: Type = I64;
3910                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3911                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3912                             let expr3_0 = constructor_umulh(ctx, expr0_0, expr1_0, expr2_0)?;
3913                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3914                             return Some(expr4_0);
3915                         }
3916                         &Opcode::Smulhi => {
3917                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3918                             // Rule at src/isa/aarch64/lower.isle line 359.
3919                             let expr0_0: Type = I64;
3920                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3921                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3922                             let expr3_0 = constructor_smulh(ctx, expr0_0, expr1_0, expr2_0)?;
3923                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3924                             return Some(expr4_0);
3925                         }
3926                         &Opcode::Band => {
3927                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3928                             // Rule at src/isa/aarch64/lower.isle line 592.
3929                             let expr0_0 = ALUOp::And;
3930                             let expr1_0: Type = I64;
3931                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3932                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3933                             )?;
3934                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3935                             return Some(expr3_0);
3936                         }
3937                         &Opcode::Bor => {
3938                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3939                             // Rule at src/isa/aarch64/lower.isle line 605.
3940                             let expr0_0 = ALUOp::Orr;
3941                             let expr1_0: Type = I64;
3942                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3943                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3944                             )?;
3945                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3946                             return Some(expr3_0);
3947                         }
3948                         &Opcode::Bxor => {
3949                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3950                             // Rule at src/isa/aarch64/lower.isle line 618.
3951                             let expr0_0 = ALUOp::Eor;
3952                             let expr1_0: Type = I64;
3953                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3954                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3955                             )?;
3956                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3957                             return Some(expr3_0);
3958                         }
3959                         &Opcode::BandNot => {
3960                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3961                             // Rule at src/isa/aarch64/lower.isle line 631.
3962                             let expr0_0 = ALUOp::AndNot;
3963                             let expr1_0: Type = I64;
3964                             let expr2_0 = constructor_alu_rs_imm_logic(
3965                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3966                             )?;
3967                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3968                             return Some(expr3_0);
3969                         }
3970                         &Opcode::BorNot => {
3971                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3972                             // Rule at src/isa/aarch64/lower.isle line 644.
3973                             let expr0_0 = ALUOp::OrrNot;
3974                             let expr1_0: Type = I64;
3975                             let expr2_0 = constructor_alu_rs_imm_logic(
3976                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3977                             )?;
3978                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3979                             return Some(expr3_0);
3980                         }
3981                         &Opcode::BxorNot => {
3982                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3983                             // Rule at src/isa/aarch64/lower.isle line 654.
3984                             let expr0_0 = ALUOp::EorNot;
3985                             let expr1_0: Type = I64;
3986                             let expr2_0 = constructor_alu_rs_imm_logic(
3987                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3988                             )?;
3989                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3990                             return Some(expr3_0);
3991                         }
3992                         &Opcode::Rotl => {
3993                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3994                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3995                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3996                                 if let &InstructionData::UnaryImm {
3997                                     opcode: ref pattern10_0,
3998                                     imm: pattern10_1,
3999                                 } = &pattern9_0
4000                                 {
4001                                     if let &Opcode::Iconst = pattern10_0 {
4002                                         let closure12 = || {
4003                                             let expr0_0: Type = I64;
4004                                             return Some(expr0_0);
4005                                         };
4006                                         if let Some(pattern12_0) = closure12() {
4007                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4008                                                 ctx,
4009                                                 pattern10_1,
4010                                                 pattern12_0,
4011                                             ) {
4012                                                 // Rule at src/isa/aarch64/lower.isle line 875.
4013                                                 let expr0_0: Type = I64;
4014                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4015                                                 let expr2_0: Type = I64;
4016                                                 let expr3_0 =
4017                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
4018                                                 let expr4_0 = constructor_a64_rotr_imm(
4019                                                     ctx, expr0_0, expr1_0, expr3_0,
4020                                                 )?;
4021                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
4022                                                 return Some(expr5_0);
4023                                             }
4024                                         }
4025                                     }
4026                                 }
4027                             }
4028                             // Rule at src/isa/aarch64/lower.isle line 866.
4029                             let expr0_0: Type = I64;
4030                             let expr1_0 = C::zero_reg(ctx);
4031                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4032                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
4033                             let expr4_0: Type = I64;
4034                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
4035                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
4036                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
4037                             return Some(expr7_0);
4038                         }
4039                         &Opcode::Rotr => {
4040                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4041                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
4042                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
4043                                 if let &InstructionData::UnaryImm {
4044                                     opcode: ref pattern10_0,
4045                                     imm: pattern10_1,
4046                                 } = &pattern9_0
4047                                 {
4048                                     if let &Opcode::Iconst = pattern10_0 {
4049                                         let closure12 = || {
4050                                             let expr0_0: Type = I64;
4051                                             return Some(expr0_0);
4052                                         };
4053                                         if let Some(pattern12_0) = closure12() {
4054                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4055                                                 ctx,
4056                                                 pattern10_1,
4057                                                 pattern12_0,
4058                                             ) {
4059                                                 // Rule at src/isa/aarch64/lower.isle line 917.
4060                                                 let expr0_0: Type = I64;
4061                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4062                                                 let expr2_0 = constructor_a64_rotr_imm(
4063                                                     ctx,
4064                                                     expr0_0,
4065                                                     expr1_0,
4066                                                     pattern13_0,
4067                                                 )?;
4068                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4069                                                 return Some(expr3_0);
4070                                             }
4071                                         }
4072                                     }
4073                                 }
4074                             }
4075                             // Rule at src/isa/aarch64/lower.isle line 905.
4076                             let expr0_0: Type = I64;
4077                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4078                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4079                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
4080                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4081                             return Some(expr4_0);
4082                         }
4083                         &Opcode::Ishl => {
4084                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4085                             // Rule at src/isa/aarch64/lower.isle line 666.
4086                             let expr0_0 = ALUOp::Lsl;
4087                             let expr1_0: Type = I64;
4088                             let expr2_0 = C::put_in_reg(ctx, pattern7_0);
4089                             let expr3_0 =
4090                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4091                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4092                             return Some(expr4_0);
4093                         }
4094                         &Opcode::Ushr => {
4095                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4096                             // Rule at src/isa/aarch64/lower.isle line 750.
4097                             let expr0_0 = ALUOp::Lsr;
4098                             let expr1_0: Type = I64;
4099                             let expr2_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
4100                             let expr3_0 =
4101                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4102                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4103                             return Some(expr4_0);
4104                         }
4105                         &Opcode::Sshr => {
4106                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4107                             // Rule at src/isa/aarch64/lower.isle line 797.
4108                             let expr0_0 = ALUOp::Asr;
4109                             let expr1_0: Type = I64;
4110                             let expr2_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
4111                             let expr3_0 =
4112                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4113                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4114                             return Some(expr4_0);
4115                         }
4116                         _ => {}
4117                     }
4118                 }
4119                 &InstructionData::Unary {
4120                     opcode: ref pattern5_0,
4121                     arg: pattern5_1,
4122                 } => {
4123                     if let &Opcode::Popcnt = pattern5_0 {
4124                         // Rule at src/isa/aarch64/lower.isle line 1117.
4125                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4126                         let expr1_0 = ScalarSize::Size64;
4127                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
4128                         let expr3_0 = VectorSize::Size8x8;
4129                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
4130                         let expr5_0 = VectorSize::Size8x8;
4131                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
4132                         let expr7_0: u8 = 0;
4133                         let expr8_0 = VectorSize::Size8x16;
4134                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
4135                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
4136                         return Some(expr10_0);
4137                     }
4138                 }
4139                 _ => {}
4140             }
4141         }
4142         if pattern2_0 == I128 {
4143             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4144             match &pattern4_0 {
4145                 &InstructionData::Binary {
4146                     opcode: ref pattern5_0,
4147                     args: ref pattern5_1,
4148                 } => {
4149                     match pattern5_0 {
4150                         &Opcode::Iadd => {
4151                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4152                             // Rule at src/isa/aarch64/lower.isle line 83.
4153                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4154                             let expr1_0: usize = 0;
4155                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4156                             let expr3_0: usize = 1;
4157                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4158                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4159                             let expr6_0: usize = 0;
4160                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4161                             let expr8_0: usize = 1;
4162                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4163                             let expr10_0: Type = I64;
4164                             let expr11_0 =
4165                                 constructor_add_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4166                             let expr12_0: Type = I64;
4167                             let expr13_0 = constructor_adc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4168                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4169                             let expr15_0 = C::output(ctx, expr14_0);
4170                             return Some(expr15_0);
4171                         }
4172                         &Opcode::Isub => {
4173                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4174                             // Rule at src/isa/aarch64/lower.isle line 133.
4175                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4176                             let expr1_0: usize = 0;
4177                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4178                             let expr3_0: usize = 1;
4179                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4180                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4181                             let expr6_0: usize = 0;
4182                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4183                             let expr8_0: usize = 1;
4184                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4185                             let expr10_0: Type = I64;
4186                             let expr11_0 =
4187                                 constructor_sub_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4188                             let expr12_0: Type = I64;
4189                             let expr13_0 = constructor_sbc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4190                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4191                             let expr15_0 = C::output(ctx, expr14_0);
4192                             return Some(expr15_0);
4193                         }
4194                         &Opcode::Imul => {
4195                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4196                             // Rule at src/isa/aarch64/lower.isle line 187.
4197                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4198                             let expr1_0: usize = 0;
4199                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4200                             let expr3_0: usize = 1;
4201                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4202                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4203                             let expr6_0: usize = 0;
4204                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4205                             let expr8_0: usize = 1;
4206                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4207                             let expr10_0: Type = I64;
4208                             let expr11_0 = constructor_umulh(ctx, expr10_0, expr2_0, expr7_0)?;
4209                             let expr12_0: Type = I64;
4210                             let expr13_0 =
4211                                 constructor_madd(ctx, expr12_0, expr2_0, expr9_0, expr11_0)?;
4212                             let expr14_0: Type = I64;
4213                             let expr15_0 =
4214                                 constructor_madd(ctx, expr14_0, expr4_0, expr7_0, expr13_0)?;
4215                             let expr16_0: Type = I64;
4216                             let expr17_0 = C::zero_reg(ctx);
4217                             let expr18_0 =
4218                                 constructor_madd(ctx, expr16_0, expr2_0, expr7_0, expr17_0)?;
4219                             let expr19_0 = C::value_regs(ctx, expr18_0, expr15_0);
4220                             let expr20_0 = C::output(ctx, expr19_0);
4221                             return Some(expr20_0);
4222                         }
4223                         &Opcode::Band => {
4224                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4225                             // Rule at src/isa/aarch64/lower.isle line 595.
4226                             let expr0_0 = ALUOp::And;
4227                             let expr1_0: Type = I64;
4228                             let expr2_0 = constructor_i128_alu_bitop(
4229                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4230                             )?;
4231                             let expr3_0 = C::output(ctx, expr2_0);
4232                             return Some(expr3_0);
4233                         }
4234                         &Opcode::Bor => {
4235                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4236                             // Rule at src/isa/aarch64/lower.isle line 608.
4237                             let expr0_0 = ALUOp::Orr;
4238                             let expr1_0: Type = I64;
4239                             let expr2_0 = constructor_i128_alu_bitop(
4240                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4241                             )?;
4242                             let expr3_0 = C::output(ctx, expr2_0);
4243                             return Some(expr3_0);
4244                         }
4245                         &Opcode::Bxor => {
4246                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4247                             // Rule at src/isa/aarch64/lower.isle line 621.
4248                             let expr0_0 = ALUOp::Eor;
4249                             let expr1_0: Type = I64;
4250                             let expr2_0 = constructor_i128_alu_bitop(
4251                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4252                             )?;
4253                             let expr3_0 = C::output(ctx, expr2_0);
4254                             return Some(expr3_0);
4255                         }
4256                         &Opcode::BandNot => {
4257                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4258                             // Rule at src/isa/aarch64/lower.isle line 634.
4259                             let expr0_0 = ALUOp::AndNot;
4260                             let expr1_0: Type = I64;
4261                             let expr2_0 = constructor_i128_alu_bitop(
4262                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4263                             )?;
4264                             let expr3_0 = C::output(ctx, expr2_0);
4265                             return Some(expr3_0);
4266                         }
4267                         &Opcode::BorNot => {
4268                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4269                             // Rule at src/isa/aarch64/lower.isle line 647.
4270                             let expr0_0 = ALUOp::OrrNot;
4271                             let expr1_0: Type = I64;
4272                             let expr2_0 = constructor_i128_alu_bitop(
4273                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4274                             )?;
4275                             let expr3_0 = C::output(ctx, expr2_0);
4276                             return Some(expr3_0);
4277                         }
4278                         &Opcode::BxorNot => {
4279                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4280                             // Rule at src/isa/aarch64/lower.isle line 657.
4281                             let expr0_0 = ALUOp::EorNot;
4282                             let expr1_0: Type = I64;
4283                             let expr2_0 = constructor_i128_alu_bitop(
4284                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4285                             )?;
4286                             let expr3_0 = C::output(ctx, expr2_0);
4287                             return Some(expr3_0);
4288                         }
4289                         &Opcode::Rotl => {
4290                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4291                             // Rule at src/isa/aarch64/lower.isle line 884.
4292                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4293                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4294                             let expr2_0: usize = 0;
4295                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4296                             let expr4_0: Type = I64;
4297                             let expr5_0: Type = I64;
4298                             let expr6_0: u64 = 128;
4299                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4300                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4301                             let expr9_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4302                             let expr10_0 = constructor_lower_ushr128(ctx, expr0_0, expr8_0)?;
4303                             let expr11_0: Type = I64;
4304                             let expr12_0: usize = 0;
4305                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4306                             let expr14_0: usize = 0;
4307                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4308                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4309                             let expr17_0: Type = I64;
4310                             let expr18_0: usize = 1;
4311                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4312                             let expr20_0: usize = 1;
4313                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4314                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4315                             let expr23_0 = C::value_regs(ctx, expr16_0, expr22_0);
4316                             let expr24_0 = C::output(ctx, expr23_0);
4317                             return Some(expr24_0);
4318                         }
4319                         &Opcode::Rotr => {
4320                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4321                             // Rule at src/isa/aarch64/lower.isle line 965.
4322                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4323                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4324                             let expr2_0: usize = 0;
4325                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4326                             let expr4_0: Type = I64;
4327                             let expr5_0: Type = I64;
4328                             let expr6_0: u64 = 128;
4329                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4330                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4331                             let expr9_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4332                             let expr10_0 = constructor_lower_shl128(ctx, expr0_0, expr8_0)?;
4333                             let expr11_0: Type = I64;
4334                             let expr12_0: usize = 1;
4335                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4336                             let expr14_0: usize = 1;
4337                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4338                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4339                             let expr17_0: Type = I64;
4340                             let expr18_0: usize = 0;
4341                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4342                             let expr20_0: usize = 0;
4343                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4344                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4345                             let expr23_0 = C::value_regs(ctx, expr22_0, expr16_0);
4346                             let expr24_0 = C::output(ctx, expr23_0);
4347                             return Some(expr24_0);
4348                         }
4349                         &Opcode::Ishl => {
4350                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4351                             // Rule at src/isa/aarch64/lower.isle line 670.
4352                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4353                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4354                             let expr2_0: usize = 0;
4355                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4356                             let expr4_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4357                             let expr5_0 = C::output(ctx, expr4_0);
4358                             return Some(expr5_0);
4359                         }
4360                         &Opcode::Ushr => {
4361                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4362                             // Rule at src/isa/aarch64/lower.isle line 754.
4363                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4364                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4365                             let expr2_0: usize = 0;
4366                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4367                             let expr4_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4368                             let expr5_0 = C::output(ctx, expr4_0);
4369                             return Some(expr5_0);
4370                         }
4371                         &Opcode::Sshr => {
4372                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4373                             // Rule at src/isa/aarch64/lower.isle line 801.
4374                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4375                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4376                             let expr2_0: usize = 0;
4377                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4378                             let expr4_0 = constructor_lower_sshr128(ctx, expr0_0, expr3_0)?;
4379                             let expr5_0 = C::output(ctx, expr4_0);
4380                             return Some(expr5_0);
4381                         }
4382                         _ => {}
4383                     }
4384                 }
4385                 &InstructionData::Unary {
4386                     opcode: ref pattern5_0,
4387                     arg: pattern5_1,
4388                 } => {
4389                     match pattern5_0 {
4390                         &Opcode::Bnot => {
4391                             // Rule at src/isa/aarch64/lower.isle line 575.
4392                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4393                             let expr1_0: usize = 0;
4394                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4395                             let expr3_0: usize = 1;
4396                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4397                             let expr5_0: Type = I64;
4398                             let expr6_0 = C::zero_reg(ctx);
4399                             let expr7_0 = constructor_orr_not(ctx, expr5_0, expr6_0, expr2_0)?;
4400                             let expr8_0: Type = I64;
4401                             let expr9_0 = C::zero_reg(ctx);
4402                             let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, expr4_0)?;
4403                             let expr11_0 = C::value_regs(ctx, expr7_0, expr10_0);
4404                             let expr12_0 = C::output(ctx, expr11_0);
4405                             return Some(expr12_0);
4406                         }
4407                         &Opcode::Bitrev => {
4408                             // Rule at src/isa/aarch64/lower.isle line 989.
4409                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4410                             let expr1_0: Type = I64;
4411                             let expr2_0: usize = 0;
4412                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4413                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4414                             let expr5_0: Type = I64;
4415                             let expr6_0: usize = 1;
4416                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4417                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4418                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4419                             let expr10_0 = C::output(ctx, expr9_0);
4420                             return Some(expr10_0);
4421                         }
4422                         &Opcode::Clz => {
4423                             // Rule at src/isa/aarch64/lower.isle line 1007.
4424                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4425                             let expr1_0 = constructor_lower_clz128(ctx, expr0_0)?;
4426                             let expr2_0 = C::output(ctx, expr1_0);
4427                             return Some(expr2_0);
4428                         }
4429                         &Opcode::Cls => {
4430                             // Rule at src/isa/aarch64/lower.isle line 1063.
4431                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4432                             let expr1_0: usize = 0;
4433                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4434                             let expr3_0: usize = 1;
4435                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4436                             let expr5_0: Type = I64;
4437                             let expr6_0 = constructor_a64_cls(ctx, expr5_0, expr2_0)?;
4438                             let expr7_0: Type = I64;
4439                             let expr8_0 = constructor_a64_cls(ctx, expr7_0, expr4_0)?;
4440                             let expr9_0: Type = I64;
4441                             let expr10_0 = constructor_eon(ctx, expr9_0, expr4_0, expr2_0)?;
4442                             let expr11_0: Type = I64;
4443                             let expr12_0: u8 = 63;
4444                             let expr13_0 = C::imm_shift_from_u8(ctx, expr12_0);
4445                             let expr14_0 = constructor_lsr_imm(ctx, expr11_0, expr10_0, expr13_0)?;
4446                             let expr15_0: Type = I64;
4447                             let expr16_0 =
4448                                 constructor_madd(ctx, expr15_0, expr6_0, expr14_0, expr14_0)?;
4449                             let expr17_0: u8 = 63;
4450                             let expr18_0 = C::u8_into_imm12(ctx, expr17_0);
4451                             let expr19_0 = constructor_cmp64_imm(ctx, expr8_0, expr18_0)?;
4452                             let expr20_0 = Cond::Eq;
4453                             let expr21_0 = C::zero_reg(ctx);
4454                             let expr22_0 = constructor_csel(ctx, &expr20_0, expr16_0, expr21_0)?;
4455                             let expr23_0 = constructor_with_flags_reg(ctx, &expr19_0, &expr22_0)?;
4456                             let expr24_0: Type = I64;
4457                             let expr25_0 = constructor_add(ctx, expr24_0, expr23_0, expr8_0)?;
4458                             let expr26_0: Type = I64;
4459                             let expr27_0: u64 = 0;
4460                             let expr28_0 = constructor_imm(ctx, expr26_0, expr27_0)?;
4461                             let expr29_0 = C::value_regs(ctx, expr25_0, expr28_0);
4462                             let expr30_0 = C::output(ctx, expr29_0);
4463                             return Some(expr30_0);
4464                         }
4465                         &Opcode::Ctz => {
4466                             // Rule at src/isa/aarch64/lower.isle line 1037.
4467                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4468                             let expr1_0: Type = I64;
4469                             let expr2_0: usize = 0;
4470                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4471                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4472                             let expr5_0: Type = I64;
4473                             let expr6_0: usize = 1;
4474                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4475                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4476                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4477                             let expr10_0 = constructor_lower_clz128(ctx, expr9_0)?;
4478                             let expr11_0 = C::output(ctx, expr10_0);
4479                             return Some(expr11_0);
4480                         }
4481                         &Opcode::Popcnt => {
4482                             // Rule at src/isa/aarch64/lower.isle line 1123.
4483                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4484                             let expr1_0: usize = 0;
4485                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4486                             let expr3_0 = ScalarSize::Size64;
4487                             let expr4_0 = constructor_mov_to_fpu(ctx, expr2_0, &expr3_0)?;
4488                             let expr5_0: usize = 1;
4489                             let expr6_0 = C::value_regs_get(ctx, expr0_0, expr5_0);
4490                             let expr7_0: u8 = 1;
4491                             let expr8_0 = VectorSize::Size64x2;
4492                             let expr9_0 =
4493                                 constructor_mov_to_vec(ctx, expr4_0, expr6_0, expr7_0, &expr8_0)?;
4494                             let expr10_0 = VectorSize::Size8x16;
4495                             let expr11_0 = constructor_vec_cnt(ctx, expr9_0, &expr10_0)?;
4496                             let expr12_0 = VectorSize::Size8x16;
4497                             let expr13_0 = constructor_addv(ctx, expr11_0, &expr12_0)?;
4498                             let expr14_0: u8 = 0;
4499                             let expr15_0 = VectorSize::Size8x16;
4500                             let expr16_0 =
4501                                 constructor_mov_from_vec(ctx, expr13_0, expr14_0, &expr15_0)?;
4502                             let expr17_0: Type = I64;
4503                             let expr18_0: u64 = 0;
4504                             let expr19_0 = constructor_imm(ctx, expr17_0, expr18_0)?;
4505                             let expr20_0 = C::value_regs(ctx, expr16_0, expr19_0);
4506                             let expr21_0 = C::output(ctx, expr20_0);
4507                             return Some(expr21_0);
4508                         }
4509                         &Opcode::Uextend => {
4510                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4511                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4512                                 if let &InstructionData::BinaryImm8 {
4513                                     opcode: ref pattern9_0,
4514                                     arg: pattern9_1,
4515                                     imm: pattern9_2,
4516                                 } = &pattern8_0
4517                                 {
4518                                     if let &Opcode::Extractlane = pattern9_0 {
4519                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4520                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
4521                                         // Rule at src/isa/aarch64/lower.isle line 505.
4522                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4523                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
4524                                         let expr2_0 = constructor_mov_from_vec(
4525                                             ctx,
4526                                             expr0_0,
4527                                             pattern12_0,
4528                                             &expr1_0,
4529                                         )?;
4530                                         let expr3_0: Type = I64;
4531                                         let expr4_0: u64 = 0;
4532                                         let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
4533                                         let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
4534                                         let expr7_0 = C::output(ctx, expr6_0);
4535                                         return Some(expr7_0);
4536                                     }
4537                                 }
4538                             }
4539                             // Rule at src/isa/aarch64/lower.isle line 500.
4540                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
4541                             let expr1_0: Type = I64;
4542                             let expr2_0: u64 = 0;
4543                             let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
4544                             let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
4545                             let expr5_0 = C::output(ctx, expr4_0);
4546                             return Some(expr5_0);
4547                         }
4548                         &Opcode::Sextend => {
4549                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4550                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4551                                 if let &InstructionData::BinaryImm8 {
4552                                     opcode: ref pattern9_0,
4553                                     arg: pattern9_1,
4554                                     imm: pattern9_2,
4555                                 } = &pattern8_0
4556                                 {
4557                                     if let &Opcode::Extractlane = pattern9_0 {
4558                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4559                                         if pattern11_0 == I64X2 {
4560                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4561                                             // Rule at src/isa/aarch64/lower.isle line 549.
4562                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4563                                             let expr1_0 = VectorSize::Size64x2;
4564                                             let expr2_0 = constructor_mov_from_vec(
4565                                                 ctx,
4566                                                 expr0_0,
4567                                                 pattern13_0,
4568                                                 &expr1_0,
4569                                             )?;
4570                                             let expr3_0: Type = I64;
4571                                             let expr4_0: u8 = 63;
4572                                             let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
4573                                             let expr6_0 = constructor_asr_imm(
4574                                                 ctx, expr3_0, expr2_0, expr5_0,
4575                                             )?;
4576                                             let expr7_0 = C::value_regs(ctx, expr2_0, expr6_0);
4577                                             let expr8_0 = C::output(ctx, expr7_0);
4578                                             return Some(expr8_0);
4579                                         }
4580                                         if let Some(()) = C::not_i64x2(ctx, pattern11_0) {
4581                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4582                                             // Rule at src/isa/aarch64/lower.isle line 538.
4583                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4584                                             let expr1_0 =
4585                                                 constructor_vector_size(ctx, pattern11_0)?;
4586                                             let expr2_0: Type = I64;
4587                                             let expr3_0 = constructor_size_from_ty(ctx, expr2_0)?;
4588                                             let expr4_0 = constructor_mov_from_vec_signed(
4589                                                 ctx,
4590                                                 expr0_0,
4591                                                 pattern13_0,
4592                                                 &expr1_0,
4593                                                 &expr3_0,
4594                                             )?;
4595                                             let expr5_0: Type = I64;
4596                                             let expr6_0: u8 = 63;
4597                                             let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
4598                                             let expr8_0 = constructor_asr_imm(
4599                                                 ctx, expr5_0, expr4_0, expr7_0,
4600                                             )?;
4601                                             let expr9_0 = C::value_regs(ctx, expr4_0, expr8_0);
4602                                             let expr10_0 = C::output(ctx, expr9_0);
4603                                             return Some(expr10_0);
4604                                         }
4605                                     }
4606                                 }
4607                             }
4608                             // Rule at src/isa/aarch64/lower.isle line 528.
4609                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
4610                             let expr1_0: Type = I64;
4611                             let expr2_0: u8 = 63;
4612                             let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0);
4613                             let expr4_0 = constructor_asr_imm(ctx, expr1_0, expr0_0, expr3_0)?;
4614                             let expr5_0 = C::value_regs(ctx, expr0_0, expr4_0);
4615                             let expr6_0 = C::output(ctx, expr5_0);
4616                             return Some(expr6_0);
4617                         }
4618                         _ => {}
4619                     }
4620                 }
4621                 _ => {}
4622             }
4623         }
4624         if pattern2_0 == I8X16 {
4625             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4626             if let &InstructionData::Unary {
4627                 opcode: ref pattern5_0,
4628                 arg: pattern5_1,
4629             } = &pattern4_0
4630             {
4631                 if let &Opcode::Popcnt = pattern5_0 {
4632                     // Rule at src/isa/aarch64/lower.isle line 1131.
4633                     let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4634                     let expr1_0 = VectorSize::Size8x16;
4635                     let expr2_0 = constructor_vec_cnt(ctx, expr0_0, &expr1_0)?;
4636                     let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4637                     return Some(expr3_0);
4638                 }
4639             }
4640         }
4641         if pattern2_0 == I16X8 {
4642             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4643             if let &InstructionData::Binary {
4644                 opcode: ref pattern5_0,
4645                 args: ref pattern5_1,
4646             } = &pattern4_0
4647             {
4648                 if let &Opcode::Imul = pattern5_0 {
4649                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4650                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4651                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4652                         if let &InstructionData::Unary {
4653                             opcode: ref pattern10_0,
4654                             arg: pattern10_1,
4655                         } = &pattern9_0
4656                         {
4657                             match pattern10_0 {
4658                                 &Opcode::SwidenLow => {
4659                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4660                                     if pattern12_0 == I8X16 {
4661                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4662                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4663                                             if let &InstructionData::Unary {
4664                                                 opcode: ref pattern16_0,
4665                                                 arg: pattern16_1,
4666                                             } = &pattern15_0
4667                                             {
4668                                                 if let &Opcode::SwidenLow = pattern16_0 {
4669                                                     let pattern18_0 =
4670                                                         C::value_type(ctx, pattern16_1);
4671                                                     if pattern18_0 == I8X16 {
4672                                                         // Rule at src/isa/aarch64/lower.isle line 286.
4673                                                         let expr0_0 =
4674                                                             C::put_in_reg(ctx, pattern10_1);
4675                                                         let expr1_0 =
4676                                                             C::put_in_reg(ctx, pattern16_1);
4677                                                         let expr2_0: bool = false;
4678                                                         let expr3_0 = constructor_smull8(
4679                                                             ctx, expr0_0, expr1_0, expr2_0,
4680                                                         )?;
4681                                                         let expr4_0 =
4682                                                             constructor_output_reg(ctx, expr3_0)?;
4683                                                         return Some(expr4_0);
4684                                                     }
4685                                                 }
4686                                             }
4687                                         }
4688                                     }
4689                                 }
4690                                 &Opcode::SwidenHigh => {
4691                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4692                                     if pattern12_0 == I8X16 {
4693                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4694                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4695                                             if let &InstructionData::Unary {
4696                                                 opcode: ref pattern16_0,
4697                                                 arg: pattern16_1,
4698                                             } = &pattern15_0
4699                                             {
4700                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4701                                                     let pattern18_0 =
4702                                                         C::value_type(ctx, pattern16_1);
4703                                                     if pattern18_0 == I8X16 {
4704                                                         // Rule at src/isa/aarch64/lower.isle line 292.
4705                                                         let expr0_0 =
4706                                                             C::put_in_reg(ctx, pattern10_1);
4707                                                         let expr1_0 =
4708                                                             C::put_in_reg(ctx, pattern16_1);
4709                                                         let expr2_0: bool = true;
4710                                                         let expr3_0 = constructor_smull8(
4711                                                             ctx, expr0_0, expr1_0, expr2_0,
4712                                                         )?;
4713                                                         let expr4_0 =
4714                                                             constructor_output_reg(ctx, expr3_0)?;
4715                                                         return Some(expr4_0);
4716                                                     }
4717                                                 }
4718                                             }
4719                                         }
4720                                     }
4721                                 }
4722                                 &Opcode::UwidenLow => {
4723                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4724                                     if pattern12_0 == I8X16 {
4725                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4726                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4727                                             if let &InstructionData::Unary {
4728                                                 opcode: ref pattern16_0,
4729                                                 arg: pattern16_1,
4730                                             } = &pattern15_0
4731                                             {
4732                                                 if let &Opcode::UwidenLow = pattern16_0 {
4733                                                     let pattern18_0 =
4734                                                         C::value_type(ctx, pattern16_1);
4735                                                     if pattern18_0 == I8X16 {
4736                                                         // Rule at src/isa/aarch64/lower.isle line 298.
4737                                                         let expr0_0 =
4738                                                             C::put_in_reg(ctx, pattern10_1);
4739                                                         let expr1_0 =
4740                                                             C::put_in_reg(ctx, pattern16_1);
4741                                                         let expr2_0: bool = false;
4742                                                         let expr3_0 = constructor_umull8(
4743                                                             ctx, expr0_0, expr1_0, expr2_0,
4744                                                         )?;
4745                                                         let expr4_0 =
4746                                                             constructor_output_reg(ctx, expr3_0)?;
4747                                                         return Some(expr4_0);
4748                                                     }
4749                                                 }
4750                                             }
4751                                         }
4752                                     }
4753                                 }
4754                                 &Opcode::UwidenHigh => {
4755                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4756                                     if pattern12_0 == I8X16 {
4757                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4758                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4759                                             if let &InstructionData::Unary {
4760                                                 opcode: ref pattern16_0,
4761                                                 arg: pattern16_1,
4762                                             } = &pattern15_0
4763                                             {
4764                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4765                                                     let pattern18_0 =
4766                                                         C::value_type(ctx, pattern16_1);
4767                                                     if pattern18_0 == I8X16 {
4768                                                         // Rule at src/isa/aarch64/lower.isle line 304.
4769                                                         let expr0_0 =
4770                                                             C::put_in_reg(ctx, pattern10_1);
4771                                                         let expr1_0 =
4772                                                             C::put_in_reg(ctx, pattern16_1);
4773                                                         let expr2_0: bool = true;
4774                                                         let expr3_0 = constructor_umull8(
4775                                                             ctx, expr0_0, expr1_0, expr2_0,
4776                                                         )?;
4777                                                         let expr4_0 =
4778                                                             constructor_output_reg(ctx, expr3_0)?;
4779                                                         return Some(expr4_0);
4780                                                     }
4781                                                 }
4782                                             }
4783                                         }
4784                                     }
4785                                 }
4786                                 _ => {}
4787                             }
4788                         }
4789                     }
4790                 }
4791             }
4792         }
4793         if pattern2_0 == I32X4 {
4794             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4795             if let &InstructionData::Binary {
4796                 opcode: ref pattern5_0,
4797                 args: ref pattern5_1,
4798             } = &pattern4_0
4799             {
4800                 if let &Opcode::Imul = pattern5_0 {
4801                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4802                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4803                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4804                         if let &InstructionData::Unary {
4805                             opcode: ref pattern10_0,
4806                             arg: pattern10_1,
4807                         } = &pattern9_0
4808                         {
4809                             match pattern10_0 {
4810                                 &Opcode::SwidenLow => {
4811                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4812                                     if pattern12_0 == I16X8 {
4813                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4814                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4815                                             if let &InstructionData::Unary {
4816                                                 opcode: ref pattern16_0,
4817                                                 arg: pattern16_1,
4818                                             } = &pattern15_0
4819                                             {
4820                                                 if let &Opcode::SwidenLow = pattern16_0 {
4821                                                     let pattern18_0 =
4822                                                         C::value_type(ctx, pattern16_1);
4823                                                     if pattern18_0 == I16X8 {
4824                                                         // Rule at src/isa/aarch64/lower.isle line 310.
4825                                                         let expr0_0 =
4826                                                             C::put_in_reg(ctx, pattern10_1);
4827                                                         let expr1_0 =
4828                                                             C::put_in_reg(ctx, pattern16_1);
4829                                                         let expr2_0: bool = false;
4830                                                         let expr3_0 = constructor_smull16(
4831                                                             ctx, expr0_0, expr1_0, expr2_0,
4832                                                         )?;
4833                                                         let expr4_0 =
4834                                                             constructor_output_reg(ctx, expr3_0)?;
4835                                                         return Some(expr4_0);
4836                                                     }
4837                                                 }
4838                                             }
4839                                         }
4840                                     }
4841                                 }
4842                                 &Opcode::SwidenHigh => {
4843                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4844                                     if pattern12_0 == I16X8 {
4845                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4846                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4847                                             if let &InstructionData::Unary {
4848                                                 opcode: ref pattern16_0,
4849                                                 arg: pattern16_1,
4850                                             } = &pattern15_0
4851                                             {
4852                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4853                                                     let pattern18_0 =
4854                                                         C::value_type(ctx, pattern16_1);
4855                                                     if pattern18_0 == I16X8 {
4856                                                         // Rule at src/isa/aarch64/lower.isle line 316.
4857                                                         let expr0_0 =
4858                                                             C::put_in_reg(ctx, pattern10_1);
4859                                                         let expr1_0 =
4860                                                             C::put_in_reg(ctx, pattern16_1);
4861                                                         let expr2_0: bool = true;
4862                                                         let expr3_0 = constructor_smull16(
4863                                                             ctx, expr0_0, expr1_0, expr2_0,
4864                                                         )?;
4865                                                         let expr4_0 =
4866                                                             constructor_output_reg(ctx, expr3_0)?;
4867                                                         return Some(expr4_0);
4868                                                     }
4869                                                 }
4870                                             }
4871                                         }
4872                                     }
4873                                 }
4874                                 &Opcode::UwidenLow => {
4875                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4876                                     if pattern12_0 == I16X8 {
4877                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4878                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4879                                             if let &InstructionData::Unary {
4880                                                 opcode: ref pattern16_0,
4881                                                 arg: pattern16_1,
4882                                             } = &pattern15_0
4883                                             {
4884                                                 if let &Opcode::UwidenLow = pattern16_0 {
4885                                                     let pattern18_0 =
4886                                                         C::value_type(ctx, pattern16_1);
4887                                                     if pattern18_0 == I16X8 {
4888                                                         // Rule at src/isa/aarch64/lower.isle line 322.
4889                                                         let expr0_0 =
4890                                                             C::put_in_reg(ctx, pattern10_1);
4891                                                         let expr1_0 =
4892                                                             C::put_in_reg(ctx, pattern16_1);
4893                                                         let expr2_0: bool = false;
4894                                                         let expr3_0 = constructor_umull16(
4895                                                             ctx, expr0_0, expr1_0, expr2_0,
4896                                                         )?;
4897                                                         let expr4_0 =
4898                                                             constructor_output_reg(ctx, expr3_0)?;
4899                                                         return Some(expr4_0);
4900                                                     }
4901                                                 }
4902                                             }
4903                                         }
4904                                     }
4905                                 }
4906                                 &Opcode::UwidenHigh => {
4907                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4908                                     if pattern12_0 == I16X8 {
4909                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4910                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4911                                             if let &InstructionData::Unary {
4912                                                 opcode: ref pattern16_0,
4913                                                 arg: pattern16_1,
4914                                             } = &pattern15_0
4915                                             {
4916                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4917                                                     let pattern18_0 =
4918                                                         C::value_type(ctx, pattern16_1);
4919                                                     if pattern18_0 == I16X8 {
4920                                                         // Rule at src/isa/aarch64/lower.isle line 328.
4921                                                         let expr0_0 =
4922                                                             C::put_in_reg(ctx, pattern10_1);
4923                                                         let expr1_0 =
4924                                                             C::put_in_reg(ctx, pattern16_1);
4925                                                         let expr2_0: bool = true;
4926                                                         let expr3_0 = constructor_umull16(
4927                                                             ctx, expr0_0, expr1_0, expr2_0,
4928                                                         )?;
4929                                                         let expr4_0 =
4930                                                             constructor_output_reg(ctx, expr3_0)?;
4931                                                         return Some(expr4_0);
4932                                                     }
4933                                                 }
4934                                             }
4935                                         }
4936                                     }
4937                                 }
4938                                 _ => {}
4939                             }
4940                         }
4941                     }
4942                 }
4943             }
4944         }
4945         if pattern2_0 == I64X2 {
4946             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4947             if let &InstructionData::Binary {
4948                 opcode: ref pattern5_0,
4949                 args: ref pattern5_1,
4950             } = &pattern4_0
4951             {
4952                 if let &Opcode::Imul = pattern5_0 {
4953                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4954                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4955                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4956                         if let &InstructionData::Unary {
4957                             opcode: ref pattern10_0,
4958                             arg: pattern10_1,
4959                         } = &pattern9_0
4960                         {
4961                             match pattern10_0 {
4962                                 &Opcode::SwidenLow => {
4963                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4964                                     if pattern12_0 == I32X4 {
4965                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4966                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4967                                             if let &InstructionData::Unary {
4968                                                 opcode: ref pattern16_0,
4969                                                 arg: pattern16_1,
4970                                             } = &pattern15_0
4971                                             {
4972                                                 if let &Opcode::SwidenLow = pattern16_0 {
4973                                                     let pattern18_0 =
4974                                                         C::value_type(ctx, pattern16_1);
4975                                                     if pattern18_0 == I32X4 {
4976                                                         // Rule at src/isa/aarch64/lower.isle line 334.
4977                                                         let expr0_0 =
4978                                                             C::put_in_reg(ctx, pattern10_1);
4979                                                         let expr1_0 =
4980                                                             C::put_in_reg(ctx, pattern16_1);
4981                                                         let expr2_0: bool = false;
4982                                                         let expr3_0 = constructor_smull32(
4983                                                             ctx, expr0_0, expr1_0, expr2_0,
4984                                                         )?;
4985                                                         let expr4_0 =
4986                                                             constructor_output_reg(ctx, expr3_0)?;
4987                                                         return Some(expr4_0);
4988                                                     }
4989                                                 }
4990                                             }
4991                                         }
4992                                     }
4993                                 }
4994                                 &Opcode::SwidenHigh => {
4995                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4996                                     if pattern12_0 == I32X4 {
4997                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4998                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4999                                             if let &InstructionData::Unary {
5000                                                 opcode: ref pattern16_0,
5001                                                 arg: pattern16_1,
5002                                             } = &pattern15_0
5003                                             {
5004                                                 if let &Opcode::SwidenHigh = pattern16_0 {
5005                                                     let pattern18_0 =
5006                                                         C::value_type(ctx, pattern16_1);
5007                                                     if pattern18_0 == I32X4 {
5008                                                         // Rule at src/isa/aarch64/lower.isle line 340.
5009                                                         let expr0_0 =
5010                                                             C::put_in_reg(ctx, pattern10_1);
5011                                                         let expr1_0 =
5012                                                             C::put_in_reg(ctx, pattern16_1);
5013                                                         let expr2_0: bool = true;
5014                                                         let expr3_0 = constructor_smull32(
5015                                                             ctx, expr0_0, expr1_0, expr2_0,
5016                                                         )?;
5017                                                         let expr4_0 =
5018                                                             constructor_output_reg(ctx, expr3_0)?;
5019                                                         return Some(expr4_0);
5020                                                     }
5021                                                 }
5022                                             }
5023                                         }
5024                                     }
5025                                 }
5026                                 &Opcode::UwidenLow => {
5027                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5028                                     if pattern12_0 == I32X4 {
5029                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5030                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5031                                             if let &InstructionData::Unary {
5032                                                 opcode: ref pattern16_0,
5033                                                 arg: pattern16_1,
5034                                             } = &pattern15_0
5035                                             {
5036                                                 if let &Opcode::UwidenLow = pattern16_0 {
5037                                                     let pattern18_0 =
5038                                                         C::value_type(ctx, pattern16_1);
5039                                                     if pattern18_0 == I32X4 {
5040                                                         // Rule at src/isa/aarch64/lower.isle line 346.
5041                                                         let expr0_0 =
5042                                                             C::put_in_reg(ctx, pattern10_1);
5043                                                         let expr1_0 =
5044                                                             C::put_in_reg(ctx, pattern16_1);
5045                                                         let expr2_0: bool = false;
5046                                                         let expr3_0 = constructor_umull32(
5047                                                             ctx, expr0_0, expr1_0, expr2_0,
5048                                                         )?;
5049                                                         let expr4_0 =
5050                                                             constructor_output_reg(ctx, expr3_0)?;
5051                                                         return Some(expr4_0);
5052                                                     }
5053                                                 }
5054                                             }
5055                                         }
5056                                     }
5057                                 }
5058                                 &Opcode::UwidenHigh => {
5059                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5060                                     if pattern12_0 == I32X4 {
5061                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5062                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5063                                             if let &InstructionData::Unary {
5064                                                 opcode: ref pattern16_0,
5065                                                 arg: pattern16_1,
5066                                             } = &pattern15_0
5067                                             {
5068                                                 if let &Opcode::UwidenHigh = pattern16_0 {
5069                                                     let pattern18_0 =
5070                                                         C::value_type(ctx, pattern16_1);
5071                                                     if pattern18_0 == I32X4 {
5072                                                         // Rule at src/isa/aarch64/lower.isle line 352.
5073                                                         let expr0_0 =
5074                                                             C::put_in_reg(ctx, pattern10_1);
5075                                                         let expr1_0 =
5076                                                             C::put_in_reg(ctx, pattern16_1);
5077                                                         let expr2_0: bool = true;
5078                                                         let expr3_0 = constructor_umull32(
5079                                                             ctx, expr0_0, expr1_0, expr2_0,
5080                                                         )?;
5081                                                         let expr4_0 =
5082                                                             constructor_output_reg(ctx, expr3_0)?;
5083                                                         return Some(expr4_0);
5084                                                     }
5085                                                 }
5086                                             }
5087                                         }
5088                                     }
5089                                 }
5090                                 _ => {}
5091                             }
5092                         }
5093                     }
5094                     // Rule at src/isa/aarch64/lower.isle line 247.
5095                     let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5096                     let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5097                     let expr2_0 = VectorSize::Size32x4;
5098                     let expr3_0 = constructor_rev64(ctx, expr1_0, &expr2_0)?;
5099                     let expr4_0 = VectorSize::Size32x4;
5100                     let expr5_0 = constructor_mul(ctx, expr3_0, expr0_0, &expr4_0)?;
5101                     let expr6_0: bool = false;
5102                     let expr7_0 = constructor_xtn64(ctx, expr0_0, expr6_0)?;
5103                     let expr8_0 = VectorSize::Size32x4;
5104                     let expr9_0 = constructor_addp(ctx, expr5_0, expr5_0, &expr8_0)?;
5105                     let expr10_0: bool = false;
5106                     let expr11_0 = constructor_xtn64(ctx, expr1_0, expr10_0)?;
5107                     let expr12_0: bool = false;
5108                     let expr13_0 = constructor_shll32(ctx, expr9_0, expr12_0)?;
5109                     let expr14_0: bool = false;
5110                     let expr15_0 = constructor_umlal32(ctx, expr13_0, expr11_0, expr7_0, expr14_0)?;
5111                     let expr16_0 = constructor_output_reg(ctx, expr15_0)?;
5112                     return Some(expr16_0);
5113                 }
5114             }
5115         }
5116         let pattern3_0 = C::inst_data(ctx, pattern0_0);
5117         match &pattern3_0 {
5118             &InstructionData::NullAry {
5119                 opcode: ref pattern4_0,
5120             } => {
5121                 if let &Opcode::Null = pattern4_0 {
5122                     // Rule at src/isa/aarch64/lower.isle line 22.
5123                     let expr0_0: u64 = 0;
5124                     let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5125                     let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5126                     return Some(expr2_0);
5127                 }
5128             }
5129             &InstructionData::UnaryImm {
5130                 opcode: ref pattern4_0,
5131                 imm: pattern4_1,
5132             } => {
5133                 if let &Opcode::Iconst = pattern4_0 {
5134                     let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1);
5135                     // Rule at src/isa/aarch64/lower.isle line 9.
5136                     let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?;
5137                     let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
5138                     return Some(expr1_0);
5139                 }
5140             }
5141             &InstructionData::UnaryBool {
5142                 opcode: ref pattern4_0,
5143                 imm: pattern4_1,
5144             } => {
5145                 if let &Opcode::Bconst = pattern4_0 {
5146                     if pattern4_1 == true {
5147                         // Rule at src/isa/aarch64/lower.isle line 17.
5148                         let expr0_0: u64 = 1;
5149                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5150                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5151                         return Some(expr2_0);
5152                     }
5153                     if pattern4_1 == false {
5154                         // Rule at src/isa/aarch64/lower.isle line 14.
5155                         let expr0_0: u64 = 0;
5156                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5157                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5158                         return Some(expr2_0);
5159                     }
5160                 }
5161             }
5162             &InstructionData::Unary {
5163                 opcode: ref pattern4_0,
5164                 arg: pattern4_1,
5165             } => {
5166                 match pattern4_0 {
5167                     &Opcode::Bitrev => {
5168                         // Rule at src/isa/aarch64/lower.isle line 995.
5169                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5170                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5171                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5172                         return Some(expr2_0);
5173                     }
5174                     &Opcode::Clz => {
5175                         // Rule at src/isa/aarch64/lower.isle line 1010.
5176                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5177                         let expr1_0 = constructor_a64_clz(ctx, pattern2_0, expr0_0)?;
5178                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5179                         return Some(expr2_0);
5180                     }
5181                     &Opcode::Cls => {
5182                         // Rule at src/isa/aarch64/lower.isle line 1077.
5183                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5184                         let expr1_0 = constructor_a64_cls(ctx, pattern2_0, expr0_0)?;
5185                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5186                         return Some(expr2_0);
5187                     }
5188                     &Opcode::Ctz => {
5189                         // Rule at src/isa/aarch64/lower.isle line 1043.
5190                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5191                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5192                         let expr2_0 = constructor_a64_clz(ctx, pattern2_0, expr1_0)?;
5193                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5194                         return Some(expr3_0);
5195                     }
5196                     _ => {}
5197                 }
5198             }
5199             _ => {}
5200         }
5201         if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) {
5202             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5203             match &pattern4_0 {
5204                 &InstructionData::Binary {
5205                     opcode: ref pattern5_0,
5206                     args: ref pattern5_1,
5207                 } => {
5208                     match pattern5_0 {
5209                         &Opcode::Iadd => {
5210                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5211                             // Rule at src/isa/aarch64/lower.isle line 79.
5212                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5213                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5214                             let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5215                             let expr3_0 = constructor_add_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5216                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5217                             return Some(expr4_0);
5218                         }
5219                         &Opcode::Isub => {
5220                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5221                             // Rule at src/isa/aarch64/lower.isle line 129.
5222                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5223                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5224                             let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5225                             let expr3_0 = constructor_sub_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5226                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5227                             return Some(expr4_0);
5228                         }
5229                         _ => {}
5230                     }
5231                 }
5232                 &InstructionData::FloatCompare {
5233                     opcode: ref pattern5_0,
5234                     args: ref pattern5_1,
5235                     cond: ref pattern5_2,
5236                 } => {
5237                     if let &Opcode::Fcmp = pattern5_0 {
5238                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5239                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5240                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5241                             if let &InstructionData::Unary {
5242                                 opcode: ref pattern10_0,
5243                                 arg: pattern10_1,
5244                             } = &pattern9_0
5245                             {
5246                                 if let &Opcode::Splat = pattern10_0 {
5247                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5248                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5249                                         match &pattern13_0 {
5250                                             &InstructionData::UnaryIeee32 {
5251                                                 opcode: ref pattern14_0,
5252                                                 imm: pattern14_1,
5253                                             } => {
5254                                                 if let &Opcode::F32const = pattern14_0 {
5255                                                     if let Some(pattern16_0) =
5256                                                         C::zero_value_f32(ctx, pattern14_1)
5257                                                     {
5258                                                         if let Some(pattern17_0) =
5259                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5260                                                         {
5261                                                             // Rule at src/isa/aarch64/lower.isle line 1151.
5262                                                             let expr0_0 =
5263                                                                 C::put_in_reg(ctx, pattern7_1);
5264                                                             let expr1_0 = constructor_vector_size(
5265                                                                 ctx, pattern2_0,
5266                                                             )?;
5267                                                             let expr2_0 =
5268                                                                 constructor_float_cmp_zero_swap(
5269                                                                     ctx,
5270                                                                     &pattern17_0,
5271                                                                     expr0_0,
5272                                                                     &expr1_0,
5273                                                                 )?;
5274                                                             let expr3_0 =
5275                                                                 C::value_reg(ctx, expr2_0);
5276                                                             let expr4_0 = C::output(ctx, expr3_0);
5277                                                             return Some(expr4_0);
5278                                                         }
5279                                                         if let Some(pattern17_0) =
5280                                                             C::fcmp_zero_cond_not_eq(
5281                                                                 ctx, pattern5_2,
5282                                                             )
5283                                                         {
5284                                                             // Rule at src/isa/aarch64/lower.isle line 1146.
5285                                                             let expr0_0 =
5286                                                                 C::put_in_reg(ctx, pattern7_1);
5287                                                             let expr1_0 = constructor_vector_size(
5288                                                                 ctx, pattern2_0,
5289                                                             )?;
5290                                                             let expr2_0 = constructor_fcmeq0(
5291                                                                 ctx, expr0_0, &expr1_0,
5292                                                             )?;
5293                                                             let expr3_0 = constructor_not(
5294                                                                 ctx, expr2_0, &expr1_0,
5295                                                             )?;
5296                                                             let expr4_0 =
5297                                                                 C::value_reg(ctx, expr3_0);
5298                                                             let expr5_0 = C::output(ctx, expr4_0);
5299                                                             return Some(expr5_0);
5300                                                         }
5301                                                     }
5302                                                 }
5303                                             }
5304                                             &InstructionData::UnaryIeee64 {
5305                                                 opcode: ref pattern14_0,
5306                                                 imm: pattern14_1,
5307                                             } => {
5308                                                 if let &Opcode::F64const = pattern14_0 {
5309                                                     if let Some(pattern16_0) =
5310                                                         C::zero_value_f64(ctx, pattern14_1)
5311                                                     {
5312                                                         if let Some(pattern17_0) =
5313                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5314                                                         {
5315                                                             // Rule at src/isa/aarch64/lower.isle line 1173.
5316                                                             let expr0_0 =
5317                                                                 C::put_in_reg(ctx, pattern7_1);
5318                                                             let expr1_0 = constructor_vector_size(
5319                                                                 ctx, pattern2_0,
5320                                                             )?;
5321                                                             let expr2_0 =
5322                                                                 constructor_float_cmp_zero_swap(
5323                                                                     ctx,
5324                                                                     &pattern17_0,
5325                                                                     expr0_0,
5326                                                                     &expr1_0,
5327                                                                 )?;
5328                                                             let expr3_0 =
5329                                                                 C::value_reg(ctx, expr2_0);
5330                                                             let expr4_0 = C::output(ctx, expr3_0);
5331                                                             return Some(expr4_0);
5332                                                         }
5333                                                         if let Some(pattern17_0) =
5334                                                             C::fcmp_zero_cond_not_eq(
5335                                                                 ctx, pattern5_2,
5336                                                             )
5337                                                         {
5338                                                             // Rule at src/isa/aarch64/lower.isle line 1168.
5339                                                             let expr0_0 =
5340                                                                 C::put_in_reg(ctx, pattern7_1);
5341                                                             let expr1_0 = constructor_vector_size(
5342                                                                 ctx, pattern2_0,
5343                                                             )?;
5344                                                             let expr2_0 = constructor_fcmeq0(
5345                                                                 ctx, expr0_0, &expr1_0,
5346                                                             )?;
5347                                                             let expr3_0 = constructor_not(
5348                                                                 ctx, expr2_0, &expr1_0,
5349                                                             )?;
5350                                                             let expr4_0 =
5351                                                                 C::value_reg(ctx, expr3_0);
5352                                                             let expr5_0 = C::output(ctx, expr4_0);
5353                                                             return Some(expr5_0);
5354                                                         }
5355                                                     }
5356                                                 }
5357                                             }
5358                                             _ => {}
5359                                         }
5360                                     }
5361                                 }
5362                             }
5363                         }
5364                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5365                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5366                             if let &InstructionData::Unary {
5367                                 opcode: ref pattern10_0,
5368                                 arg: pattern10_1,
5369                             } = &pattern9_0
5370                             {
5371                                 if let &Opcode::Splat = pattern10_0 {
5372                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5373                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5374                                         match &pattern13_0 {
5375                                             &InstructionData::UnaryIeee32 {
5376                                                 opcode: ref pattern14_0,
5377                                                 imm: pattern14_1,
5378                                             } => {
5379                                                 if let &Opcode::F32const = pattern14_0 {
5380                                                     if let Some(pattern16_0) =
5381                                                         C::zero_value_f32(ctx, pattern14_1)
5382                                                     {
5383                                                         if let Some(pattern17_0) =
5384                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5385                                                         {
5386                                                             // Rule at src/isa/aarch64/lower.isle line 1141.
5387                                                             let expr0_0 =
5388                                                                 C::put_in_reg(ctx, pattern7_0);
5389                                                             let expr1_0 = constructor_vector_size(
5390                                                                 ctx, pattern2_0,
5391                                                             )?;
5392                                                             let expr2_0 =
5393                                                                 constructor_float_cmp_zero(
5394                                                                     ctx,
5395                                                                     &pattern17_0,
5396                                                                     expr0_0,
5397                                                                     &expr1_0,
5398                                                                 )?;
5399                                                             let expr3_0 =
5400                                                                 C::value_reg(ctx, expr2_0);
5401                                                             let expr4_0 = C::output(ctx, expr3_0);
5402                                                             return Some(expr4_0);
5403                                                         }
5404                                                         if let Some(pattern17_0) =
5405                                                             C::fcmp_zero_cond_not_eq(
5406                                                                 ctx, pattern5_2,
5407                                                             )
5408                                                         {
5409                                                             // Rule at src/isa/aarch64/lower.isle line 1136.
5410                                                             let expr0_0 =
5411                                                                 C::put_in_reg(ctx, pattern7_0);
5412                                                             let expr1_0 = constructor_vector_size(
5413                                                                 ctx, pattern2_0,
5414                                                             )?;
5415                                                             let expr2_0 = constructor_fcmeq0(
5416                                                                 ctx, expr0_0, &expr1_0,
5417                                                             )?;
5418                                                             let expr3_0 = constructor_not(
5419                                                                 ctx, expr2_0, &expr1_0,
5420                                                             )?;
5421                                                             let expr4_0 =
5422                                                                 C::value_reg(ctx, expr3_0);
5423                                                             let expr5_0 = C::output(ctx, expr4_0);
5424                                                             return Some(expr5_0);
5425                                                         }
5426                                                     }
5427                                                 }
5428                                             }
5429                                             &InstructionData::UnaryIeee64 {
5430                                                 opcode: ref pattern14_0,
5431                                                 imm: pattern14_1,
5432                                             } => {
5433                                                 if let &Opcode::F64const = pattern14_0 {
5434                                                     if let Some(pattern16_0) =
5435                                                         C::zero_value_f64(ctx, pattern14_1)
5436                                                     {
5437                                                         if let Some(pattern17_0) =
5438                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5439                                                         {
5440                                                             // Rule at src/isa/aarch64/lower.isle line 1163.
5441                                                             let expr0_0 =
5442                                                                 C::put_in_reg(ctx, pattern7_0);
5443                                                             let expr1_0 = constructor_vector_size(
5444                                                                 ctx, pattern2_0,
5445                                                             )?;
5446                                                             let expr2_0 =
5447                                                                 constructor_float_cmp_zero(
5448                                                                     ctx,
5449                                                                     &pattern17_0,
5450                                                                     expr0_0,
5451                                                                     &expr1_0,
5452                                                                 )?;
5453                                                             let expr3_0 =
5454                                                                 C::value_reg(ctx, expr2_0);
5455                                                             let expr4_0 = C::output(ctx, expr3_0);
5456                                                             return Some(expr4_0);
5457                                                         }
5458                                                         if let Some(pattern17_0) =
5459                                                             C::fcmp_zero_cond_not_eq(
5460                                                                 ctx, pattern5_2,
5461                                                             )
5462                                                         {
5463                                                             // Rule at src/isa/aarch64/lower.isle line 1158.
5464                                                             let expr0_0 =
5465                                                                 C::put_in_reg(ctx, pattern7_0);
5466                                                             let expr1_0 = constructor_vector_size(
5467                                                                 ctx, pattern2_0,
5468                                                             )?;
5469                                                             let expr2_0 = constructor_fcmeq0(
5470                                                                 ctx, expr0_0, &expr1_0,
5471                                                             )?;
5472                                                             let expr3_0 = constructor_not(
5473                                                                 ctx, expr2_0, &expr1_0,
5474                                                             )?;
5475                                                             let expr4_0 =
5476                                                                 C::value_reg(ctx, expr3_0);
5477                                                             let expr5_0 = C::output(ctx, expr4_0);
5478                                                             return Some(expr5_0);
5479                                                         }
5480                                                     }
5481                                                 }
5482                                             }
5483                                             _ => {}
5484                                         }
5485                                     }
5486                                 }
5487                             }
5488                         }
5489                     }
5490                 }
5491                 &InstructionData::IntCompare {
5492                     opcode: ref pattern5_0,
5493                     args: ref pattern5_1,
5494                     cond: ref pattern5_2,
5495                 } => {
5496                     if let &Opcode::Icmp = pattern5_0 {
5497                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5498                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5499                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5500                             if let &InstructionData::Unary {
5501                                 opcode: ref pattern10_0,
5502                                 arg: pattern10_1,
5503                             } = &pattern9_0
5504                             {
5505                                 if let &Opcode::Splat = pattern10_0 {
5506                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5507                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5508                                         if let &InstructionData::UnaryImm {
5509                                             opcode: ref pattern14_0,
5510                                             imm: pattern14_1,
5511                                         } = &pattern13_0
5512                                         {
5513                                             if let &Opcode::Iconst = pattern14_0 {
5514                                                 if let Some(pattern16_0) =
5515                                                     C::zero_value(ctx, pattern14_1)
5516                                                 {
5517                                                     if let Some(pattern17_0) =
5518                                                         C::icmp_zero_cond(ctx, pattern5_2)
5519                                                     {
5520                                                         // Rule at src/isa/aarch64/lower.isle line 1195.
5521                                                         let expr0_0 =
5522                                                             C::put_in_reg(ctx, pattern7_1);
5523                                                         let expr1_0 = constructor_vector_size(
5524                                                             ctx, pattern2_0,
5525                                                         )?;
5526                                                         let expr2_0 =
5527                                                             constructor_int_cmp_zero_swap(
5528                                                                 ctx,
5529                                                                 &pattern17_0,
5530                                                                 expr0_0,
5531                                                                 &expr1_0,
5532                                                             )?;
5533                                                         let expr3_0 = C::value_reg(ctx, expr2_0);
5534                                                         let expr4_0 = C::output(ctx, expr3_0);
5535                                                         return Some(expr4_0);
5536                                                     }
5537                                                     if let Some(pattern17_0) =
5538                                                         C::icmp_zero_cond_not_eq(ctx, pattern5_2)
5539                                                     {
5540                                                         // Rule at src/isa/aarch64/lower.isle line 1190.
5541                                                         let expr0_0 =
5542                                                             C::put_in_reg(ctx, pattern7_1);
5543                                                         let expr1_0 = constructor_vector_size(
5544                                                             ctx, pattern2_0,
5545                                                         )?;
5546                                                         let expr2_0 = constructor_cmeq0(
5547                                                             ctx, expr0_0, &expr1_0,
5548                                                         )?;
5549                                                         let expr3_0 = constructor_not(
5550                                                             ctx, expr2_0, &expr1_0,
5551                                                         )?;
5552                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5553                                                         let expr5_0 = C::output(ctx, expr4_0);
5554                                                         return Some(expr5_0);
5555                                                     }
5556                                                 }
5557                                             }
5558                                         }
5559                                     }
5560                                 }
5561                             }
5562                         }
5563                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5564                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5565                             if let &InstructionData::Unary {
5566                                 opcode: ref pattern10_0,
5567                                 arg: pattern10_1,
5568                             } = &pattern9_0
5569                             {
5570                                 if let &Opcode::Splat = pattern10_0 {
5571                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5572                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5573                                         if let &InstructionData::UnaryImm {
5574                                             opcode: ref pattern14_0,
5575                                             imm: pattern14_1,
5576                                         } = &pattern13_0
5577                                         {
5578                                             if let &Opcode::Iconst = pattern14_0 {
5579                                                 if let Some(pattern16_0) =
5580                                                     C::zero_value(ctx, pattern14_1)
5581                                                 {
5582                                                     if let Some(pattern17_0) =
5583                                                         C::icmp_zero_cond(ctx, pattern5_2)
5584                                                     {
5585                                                         // Rule at src/isa/aarch64/lower.isle line 1185.
5586                                                         let expr0_0 =
5587                                                             C::put_in_reg(ctx, pattern7_0);
5588                                                         let expr1_0 = constructor_vector_size(
5589                                                             ctx, pattern2_0,
5590                                                         )?;
5591                                                         let expr2_0 = constructor_int_cmp_zero(
5592                                                             ctx,
5593                                                             &pattern17_0,
5594                                                             expr0_0,
5595                                                             &expr1_0,
5596                                                         )?;
5597                                                         let expr3_0 = C::value_reg(ctx, expr2_0);
5598                                                         let expr4_0 = C::output(ctx, expr3_0);
5599                                                         return Some(expr4_0);
5600                                                     }
5601                                                     if let Some(pattern17_0) =
5602                                                         C::icmp_zero_cond_not_eq(ctx, pattern5_2)
5603                                                     {
5604                                                         // Rule at src/isa/aarch64/lower.isle line 1180.
5605                                                         let expr0_0 =
5606                                                             C::put_in_reg(ctx, pattern7_0);
5607                                                         let expr1_0 = constructor_vector_size(
5608                                                             ctx, pattern2_0,
5609                                                         )?;
5610                                                         let expr2_0 = constructor_cmeq0(
5611                                                             ctx, expr0_0, &expr1_0,
5612                                                         )?;
5613                                                         let expr3_0 = constructor_not(
5614                                                             ctx, expr2_0, &expr1_0,
5615                                                         )?;
5616                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5617                                                         let expr5_0 = C::output(ctx, expr4_0);
5618                                                         return Some(expr5_0);
5619                                                     }
5620                                                 }
5621                                             }
5622                                         }
5623                                     }
5624                                 }
5625                             }
5626                         }
5627                     }
5628                 }
5629                 _ => {}
5630             }
5631         }
5632         if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
5633             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5634             if let &InstructionData::Binary {
5635                 opcode: ref pattern5_0,
5636                 args: ref pattern5_1,
5637             } = &pattern4_0
5638             {
5639                 match pattern5_0 {
5640                     &Opcode::Rotl => {
5641                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5642                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5643                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5644                             if let &InstructionData::UnaryImm {
5645                                 opcode: ref pattern10_0,
5646                                 imm: pattern10_1,
5647                             } = &pattern9_0
5648                             {
5649                                 if let &Opcode::Iconst = pattern10_0 {
5650                                     let closure12 = || {
5651                                         return Some(pattern3_0);
5652                                     };
5653                                     if let Some(pattern12_0) = closure12() {
5654                                         if let Some(pattern13_0) =
5655                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5656                                         {
5657                                             // Rule at src/isa/aarch64/lower.isle line 849.
5658                                             let expr0_0 =
5659                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5660                                             let expr1_0 =
5661                                                 C::negate_imm_shift(ctx, pattern3_0, pattern13_0);
5662                                             let expr2_0 = constructor_small_rotr_imm(
5663                                                 ctx, pattern3_0, expr0_0, expr1_0,
5664                                             )?;
5665                                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5666                                             return Some(expr3_0);
5667                                         }
5668                                     }
5669                                 }
5670                             }
5671                         }
5672                         // Rule at src/isa/aarch64/lower.isle line 844.
5673                         let expr0_0: Type = I32;
5674                         let expr1_0 = C::zero_reg(ctx);
5675                         let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5676                         let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
5677                         let expr4_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5678                         let expr5_0 = constructor_small_rotr(ctx, pattern3_0, expr4_0, expr3_0)?;
5679                         let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
5680                         return Some(expr6_0);
5681                     }
5682                     &Opcode::Rotr => {
5683                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5684                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5685                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5686                             if let &InstructionData::UnaryImm {
5687                                 opcode: ref pattern10_0,
5688                                 imm: pattern10_1,
5689                             } = &pattern9_0
5690                             {
5691                                 if let &Opcode::Iconst = pattern10_0 {
5692                                     let closure12 = || {
5693                                         return Some(pattern3_0);
5694                                     };
5695                                     if let Some(pattern12_0) = closure12() {
5696                                         if let Some(pattern13_0) =
5697                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5698                                         {
5699                                             // Rule at src/isa/aarch64/lower.isle line 909.
5700                                             let expr0_0 =
5701                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5702                                             let expr1_0 = constructor_small_rotr_imm(
5703                                                 ctx,
5704                                                 pattern3_0,
5705                                                 expr0_0,
5706                                                 pattern13_0,
5707                                             )?;
5708                                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5709                                             return Some(expr2_0);
5710                                         }
5711                                     }
5712                                 }
5713                             }
5714                         }
5715                         // Rule at src/isa/aarch64/lower.isle line 897.
5716                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5717                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5718                         let expr2_0 = constructor_small_rotr(ctx, pattern3_0, expr0_0, expr1_0)?;
5719                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5720                         return Some(expr3_0);
5721                     }
5722                     _ => {}
5723                 }
5724             }
5725         }
5726         if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
5727             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5728             if let &InstructionData::Binary {
5729                 opcode: ref pattern5_0,
5730                 args: ref pattern5_1,
5731             } = &pattern4_0
5732             {
5733                 match pattern5_0 {
5734                     &Opcode::Umulhi => {
5735                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5736                         // Rule at src/isa/aarch64/lower.isle line 374.
5737                         let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5738                         let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?;
5739                         let expr2_0: Type = I64;
5740                         let expr3_0 = C::zero_reg(ctx);
5741                         let expr4_0 = constructor_madd(ctx, expr2_0, expr0_0, expr1_0, expr3_0)?;
5742                         let expr5_0: Type = I64;
5743                         let expr6_0 = C::ty_bits(ctx, pattern3_0);
5744                         let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
5745                         let expr8_0 = constructor_lsr_imm(ctx, expr5_0, expr4_0, expr7_0)?;
5746                         let expr9_0 = C::value_reg(ctx, expr8_0);
5747                         let expr10_0 = C::output(ctx, expr9_0);
5748                         return Some(expr10_0);
5749                     }
5750                     &Opcode::Smulhi => {
5751                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5752                         // Rule at src/isa/aarch64/lower.isle line 362.
5753                         let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5754                         let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?;
5755                         let expr2_0: Type = I64;
5756                         let expr3_0 = C::zero_reg(ctx);
5757                         let expr4_0 = constructor_madd(ctx, expr2_0, expr0_0, expr1_0, expr3_0)?;
5758                         let expr5_0: Type = I64;
5759                         let expr6_0 = C::ty_bits(ctx, pattern3_0);
5760                         let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
5761                         let expr8_0 = constructor_asr_imm(ctx, expr5_0, expr4_0, expr7_0)?;
5762                         let expr9_0 = constructor_output_reg(ctx, expr8_0)?;
5763                         return Some(expr9_0);
5764                     }
5765                     &Opcode::Band => {
5766                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5767                         // Rule at src/isa/aarch64/lower.isle line 589.
5768                         let expr0_0 = ALUOp::And;
5769                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5770                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5771                         )?;
5772                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5773                         return Some(expr2_0);
5774                     }
5775                     &Opcode::Bor => {
5776                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5777                         // Rule at src/isa/aarch64/lower.isle line 602.
5778                         let expr0_0 = ALUOp::Orr;
5779                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5780                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5781                         )?;
5782                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5783                         return Some(expr2_0);
5784                     }
5785                     &Opcode::Bxor => {
5786                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5787                         // Rule at src/isa/aarch64/lower.isle line 615.
5788                         let expr0_0 = ALUOp::Eor;
5789                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5790                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5791                         )?;
5792                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5793                         return Some(expr2_0);
5794                     }
5795                     &Opcode::BandNot => {
5796                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5797                         // Rule at src/isa/aarch64/lower.isle line 628.
5798                         let expr0_0 = ALUOp::AndNot;
5799                         let expr1_0 = constructor_alu_rs_imm_logic(
5800                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5801                         )?;
5802                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5803                         return Some(expr2_0);
5804                     }
5805                     &Opcode::BorNot => {
5806                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5807                         // Rule at src/isa/aarch64/lower.isle line 641.
5808                         let expr0_0 = ALUOp::OrrNot;
5809                         let expr1_0 = constructor_alu_rs_imm_logic(
5810                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5811                         )?;
5812                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5813                         return Some(expr2_0);
5814                     }
5815                     &Opcode::BxorNot => {
5816                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5817                         // Rule at src/isa/aarch64/lower.isle line 651.
5818                         let expr0_0 = ALUOp::EorNot;
5819                         let expr1_0: Type = I32;
5820                         let expr2_0 = constructor_alu_rs_imm_logic(
5821                             ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
5822                         )?;
5823                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5824                         return Some(expr3_0);
5825                     }
5826                     &Opcode::Ishl => {
5827                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5828                         // Rule at src/isa/aarch64/lower.isle line 662.
5829                         let expr0_0 = ALUOp::Lsl;
5830                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
5831                         let expr2_0 =
5832                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5833                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5834                         return Some(expr3_0);
5835                     }
5836                     &Opcode::Ushr => {
5837                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5838                         // Rule at src/isa/aarch64/lower.isle line 746.
5839                         let expr0_0 = ALUOp::Lsr;
5840                         let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5841                         let expr2_0 =
5842                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5843                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5844                         return Some(expr3_0);
5845                     }
5846                     &Opcode::Sshr => {
5847                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5848                         // Rule at src/isa/aarch64/lower.isle line 793.
5849                         let expr0_0 = ALUOp::Asr;
5850                         let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
5851                         let expr2_0 =
5852                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5853                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5854                         return Some(expr3_0);
5855                     }
5856                     _ => {}
5857                 }
5858             }
5859         }
5860         if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
5861             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5862             match &pattern4_0 {
5863                 &InstructionData::Binary {
5864                     opcode: ref pattern5_0,
5865                     args: ref pattern5_1,
5866                 } => {
5867                     match pattern5_0 {
5868                         &Opcode::Iadd => {
5869                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5870                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5871                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5872                                 match &pattern9_0 {
5873                                     &InstructionData::UnaryImm {
5874                                         opcode: ref pattern10_0,
5875                                         imm: pattern10_1,
5876                                     } => {
5877                                         if let &Opcode::Iconst = pattern10_0 {
5878                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5879                                             if let Some(pattern13_0) =
5880                                                 C::imm12_from_u64(ctx, pattern12_0)
5881                                             {
5882                                                 // Rule at src/isa/aarch64/lower.isle line 37.
5883                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5884                                                 let expr1_0 = constructor_add_imm(
5885                                                     ctx,
5886                                                     pattern3_0,
5887                                                     expr0_0,
5888                                                     pattern13_0,
5889                                                 )?;
5890                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5891                                                 return Some(expr2_0);
5892                                             }
5893                                             if let Some(pattern13_0) =
5894                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5895                                             {
5896                                                 // Rule at src/isa/aarch64/lower.isle line 45.
5897                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5898                                                 let expr1_0 = constructor_sub_imm(
5899                                                     ctx,
5900                                                     pattern3_0,
5901                                                     expr0_0,
5902                                                     pattern13_0,
5903                                                 )?;
5904                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5905                                                 return Some(expr2_0);
5906                                             }
5907                                         }
5908                                     }
5909                                     &InstructionData::Binary {
5910                                         opcode: ref pattern10_0,
5911                                         args: ref pattern10_1,
5912                                     } => {
5913                                         match pattern10_0 {
5914                                             &Opcode::Imul => {
5915                                                 let (pattern12_0, pattern12_1) =
5916                                                     C::unpack_value_array_2(ctx, pattern10_1);
5917                                                 // Rule at src/isa/aarch64/lower.isle line 70.
5918                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5919                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5920                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5921                                                 let expr3_0 = constructor_madd(
5922                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5923                                                 )?;
5924                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5925                                                 return Some(expr4_0);
5926                                             }
5927                                             &Opcode::Ishl => {
5928                                                 let (pattern12_0, pattern12_1) =
5929                                                     C::unpack_value_array_2(ctx, pattern10_1);
5930                                                 if let Some(pattern13_0) =
5931                                                     C::def_inst(ctx, pattern12_1)
5932                                                 {
5933                                                     let pattern14_0 =
5934                                                         C::inst_data(ctx, pattern13_0);
5935                                                     if let &InstructionData::UnaryImm {
5936                                                         opcode: ref pattern15_0,
5937                                                         imm: pattern15_1,
5938                                                     } = &pattern14_0
5939                                                     {
5940                                                         if let &Opcode::Iconst = pattern15_0 {
5941                                                             let closure17 = || {
5942                                                                 return Some(pattern3_0);
5943                                                             };
5944                                                             if let Some(pattern17_0) = closure17() {
5945                                                                 if let Some(pattern18_0) =
5946                                                                     C::lshl_from_imm64(
5947                                                                         ctx,
5948                                                                         pattern15_1,
5949                                                                         pattern17_0,
5950                                                                     )
5951                                                                 {
5952                                                                     // Rule at src/isa/aarch64/lower.isle line 62.
5953                                                                     let expr0_0 = C::put_in_reg(
5954                                                                         ctx, pattern7_1,
5955                                                                     );
5956                                                                     let expr1_0 = C::put_in_reg(
5957                                                                         ctx,
5958                                                                         pattern12_0,
5959                                                                     );
5960                                                                     let expr2_0 =
5961                                                                         constructor_add_shift(
5962                                                                             ctx,
5963                                                                             pattern3_0,
5964                                                                             expr0_0,
5965                                                                             expr1_0,
5966                                                                             pattern18_0,
5967                                                                         )?;
5968                                                                     let expr3_0 =
5969                                                                         constructor_output_reg(
5970                                                                             ctx, expr2_0,
5971                                                                         )?;
5972                                                                     return Some(expr3_0);
5973                                                                 }
5974                                                             }
5975                                                         }
5976                                                     }
5977                                                 }
5978                                             }
5979                                             _ => {}
5980                                         }
5981                                     }
5982                                     _ => {}
5983                                 }
5984                             }
5985                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0)
5986                             {
5987                                 // Rule at src/isa/aarch64/lower.isle line 53.
5988                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5989                                 let expr1_0 =
5990                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5991                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5992                                 return Some(expr2_0);
5993                             }
5994                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5995                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5996                                 match &pattern9_0 {
5997                                     &InstructionData::UnaryImm {
5998                                         opcode: ref pattern10_0,
5999                                         imm: pattern10_1,
6000                                     } => {
6001                                         if let &Opcode::Iconst = pattern10_0 {
6002                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
6003                                             if let Some(pattern13_0) =
6004                                                 C::imm12_from_u64(ctx, pattern12_0)
6005                                             {
6006                                                 // Rule at src/isa/aarch64/lower.isle line 34.
6007                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6008                                                 let expr1_0 = constructor_add_imm(
6009                                                     ctx,
6010                                                     pattern3_0,
6011                                                     expr0_0,
6012                                                     pattern13_0,
6013                                                 )?;
6014                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6015                                                 return Some(expr2_0);
6016                                             }
6017                                             if let Some(pattern13_0) =
6018                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
6019                                             {
6020                                                 // Rule at src/isa/aarch64/lower.isle line 42.
6021                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6022                                                 let expr1_0 = constructor_sub_imm(
6023                                                     ctx,
6024                                                     pattern3_0,
6025                                                     expr0_0,
6026                                                     pattern13_0,
6027                                                 )?;
6028                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6029                                                 return Some(expr2_0);
6030                                             }
6031                                         }
6032                                     }
6033                                     &InstructionData::Binary {
6034                                         opcode: ref pattern10_0,
6035                                         args: ref pattern10_1,
6036                                     } => {
6037                                         match pattern10_0 {
6038                                             &Opcode::Imul => {
6039                                                 let (pattern12_0, pattern12_1) =
6040                                                     C::unpack_value_array_2(ctx, pattern10_1);
6041                                                 // Rule at src/isa/aarch64/lower.isle line 67.
6042                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
6043                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
6044                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
6045                                                 let expr3_0 = constructor_madd(
6046                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
6047                                                 )?;
6048                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6049                                                 return Some(expr4_0);
6050                                             }
6051                                             &Opcode::Ishl => {
6052                                                 let (pattern12_0, pattern12_1) =
6053                                                     C::unpack_value_array_2(ctx, pattern10_1);
6054                                                 if let Some(pattern13_0) =
6055                                                     C::def_inst(ctx, pattern12_1)
6056                                                 {
6057                                                     let pattern14_0 =
6058                                                         C::inst_data(ctx, pattern13_0);
6059                                                     if let &InstructionData::UnaryImm {
6060                                                         opcode: ref pattern15_0,
6061                                                         imm: pattern15_1,
6062                                                     } = &pattern14_0
6063                                                     {
6064                                                         if let &Opcode::Iconst = pattern15_0 {
6065                                                             let closure17 = || {
6066                                                                 return Some(pattern3_0);
6067                                                             };
6068                                                             if let Some(pattern17_0) = closure17() {
6069                                                                 if let Some(pattern18_0) =
6070                                                                     C::lshl_from_imm64(
6071                                                                         ctx,
6072                                                                         pattern15_1,
6073                                                                         pattern17_0,
6074                                                                     )
6075                                                                 {
6076                                                                     // Rule at src/isa/aarch64/lower.isle line 58.
6077                                                                     let expr0_0 = C::put_in_reg(
6078                                                                         ctx, pattern7_0,
6079                                                                     );
6080                                                                     let expr1_0 = C::put_in_reg(
6081                                                                         ctx,
6082                                                                         pattern12_0,
6083                                                                     );
6084                                                                     let expr2_0 =
6085                                                                         constructor_add_shift(
6086                                                                             ctx,
6087                                                                             pattern3_0,
6088                                                                             expr0_0,
6089                                                                             expr1_0,
6090                                                                             pattern18_0,
6091                                                                         )?;
6092                                                                     let expr3_0 =
6093                                                                         constructor_output_reg(
6094                                                                             ctx, expr2_0,
6095                                                                         )?;
6096                                                                     return Some(expr3_0);
6097                                                                 }
6098                                                             }
6099                                                         }
6100                                                     }
6101                                                 }
6102                                             }
6103                                             _ => {}
6104                                         }
6105                                     }
6106                                     _ => {}
6107                                 }
6108                             }
6109                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
6110                             {
6111                                 // Rule at src/isa/aarch64/lower.isle line 50.
6112                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6113                                 let expr1_0 =
6114                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6115                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6116                                 return Some(expr2_0);
6117                             }
6118                             // Rule at src/isa/aarch64/lower.isle line 30.
6119                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6120                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6121                             let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, expr1_0)?;
6122                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6123                             return Some(expr3_0);
6124                         }
6125                         &Opcode::Isub => {
6126                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6127                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6128                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6129                                 match &pattern9_0 {
6130                                     &InstructionData::UnaryImm {
6131                                         opcode: ref pattern10_0,
6132                                         imm: pattern10_1,
6133                                     } => {
6134                                         if let &Opcode::Iconst = pattern10_0 {
6135                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
6136                                             if let Some(pattern13_0) =
6137                                                 C::imm12_from_u64(ctx, pattern12_0)
6138                                             {
6139                                                 // Rule at src/isa/aarch64/lower.isle line 109.
6140                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6141                                                 let expr1_0 = constructor_sub_imm(
6142                                                     ctx,
6143                                                     pattern3_0,
6144                                                     expr0_0,
6145                                                     pattern13_0,
6146                                                 )?;
6147                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6148                                                 return Some(expr2_0);
6149                                             }
6150                                             if let Some(pattern13_0) =
6151                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
6152                                             {
6153                                                 // Rule at src/isa/aarch64/lower.isle line 114.
6154                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6155                                                 let expr1_0 = constructor_add_imm(
6156                                                     ctx,
6157                                                     pattern3_0,
6158                                                     expr0_0,
6159                                                     pattern13_0,
6160                                                 )?;
6161                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6162                                                 return Some(expr2_0);
6163                                             }
6164                                         }
6165                                     }
6166                                     &InstructionData::Binary {
6167                                         opcode: ref pattern10_0,
6168                                         args: ref pattern10_1,
6169                                     } => {
6170                                         match pattern10_0 {
6171                                             &Opcode::Imul => {
6172                                                 let (pattern12_0, pattern12_1) =
6173                                                     C::unpack_value_array_2(ctx, pattern10_1);
6174                                                 // Rule at src/isa/aarch64/lower.isle line 74.
6175                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
6176                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
6177                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
6178                                                 let expr3_0 = constructor_msub(
6179                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
6180                                                 )?;
6181                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6182                                                 return Some(expr4_0);
6183                                             }
6184                                             &Opcode::Ishl => {
6185                                                 let (pattern12_0, pattern12_1) =
6186                                                     C::unpack_value_array_2(ctx, pattern10_1);
6187                                                 if let Some(pattern13_0) =
6188                                                     C::def_inst(ctx, pattern12_1)
6189                                                 {
6190                                                     let pattern14_0 =
6191                                                         C::inst_data(ctx, pattern13_0);
6192                                                     if let &InstructionData::UnaryImm {
6193                                                         opcode: ref pattern15_0,
6194                                                         imm: pattern15_1,
6195                                                     } = &pattern14_0
6196                                                     {
6197                                                         if let &Opcode::Iconst = pattern15_0 {
6198                                                             let closure17 = || {
6199                                                                 return Some(pattern3_0);
6200                                                             };
6201                                                             if let Some(pattern17_0) = closure17() {
6202                                                                 if let Some(pattern18_0) =
6203                                                                     C::lshl_from_imm64(
6204                                                                         ctx,
6205                                                                         pattern15_1,
6206                                                                         pattern17_0,
6207                                                                     )
6208                                                                 {
6209                                                                     // Rule at src/isa/aarch64/lower.isle line 124.
6210                                                                     let expr0_0 = C::put_in_reg(
6211                                                                         ctx, pattern7_0,
6212                                                                     );
6213                                                                     let expr1_0 = C::put_in_reg(
6214                                                                         ctx,
6215                                                                         pattern12_0,
6216                                                                     );
6217                                                                     let expr2_0 =
6218                                                                         constructor_sub_shift(
6219                                                                             ctx,
6220                                                                             pattern3_0,
6221                                                                             expr0_0,
6222                                                                             expr1_0,
6223                                                                             pattern18_0,
6224                                                                         )?;
6225                                                                     let expr3_0 =
6226                                                                         constructor_output_reg(
6227                                                                             ctx, expr2_0,
6228                                                                         )?;
6229                                                                     return Some(expr3_0);
6230                                                                 }
6231                                                             }
6232                                                         }
6233                                                     }
6234                                                 }
6235                                             }
6236                                             _ => {}
6237                                         }
6238                                     }
6239                                     _ => {}
6240                                 }
6241                             }
6242                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
6243                             {
6244                                 // Rule at src/isa/aarch64/lower.isle line 119.
6245                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6246                                 let expr1_0 =
6247                                     constructor_sub_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6248                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6249                                 return Some(expr2_0);
6250                             }
6251                             // Rule at src/isa/aarch64/lower.isle line 105.
6252                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6253                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6254                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
6255                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6256                             return Some(expr3_0);
6257                         }
6258                         &Opcode::Imul => {
6259                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6260                             // Rule at src/isa/aarch64/lower.isle line 183.
6261                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6262                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6263                             let expr2_0 = C::zero_reg(ctx);
6264                             let expr3_0 =
6265                                 constructor_madd(ctx, pattern3_0, expr0_0, expr1_0, expr2_0)?;
6266                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6267                             return Some(expr4_0);
6268                         }
6269                         &Opcode::Udiv => {
6270                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6271                             // Rule at src/isa/aarch64/lower.isle line 390.
6272                             let expr0_0: Type = I64;
6273                             let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
6274                             let expr2_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
6275                             let expr3_0 = constructor_a64_udiv(ctx, expr0_0, expr1_0, expr2_0)?;
6276                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6277                             return Some(expr4_0);
6278                         }
6279                         &Opcode::Sdiv => {
6280                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6281                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6282                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6283                                 if let &InstructionData::UnaryImm {
6284                                     opcode: ref pattern10_0,
6285                                     imm: pattern10_1,
6286                                 } = &pattern9_0
6287                                 {
6288                                     if let &Opcode::Iconst = pattern10_0 {
6289                                         if let Some(pattern12_0) =
6290                                             C::safe_divisor_from_imm64(ctx, pattern10_1)
6291                                         {
6292                                             // Rule at src/isa/aarch64/lower.isle line 436.
6293                                             let expr0_0: Type = I64;
6294                                             let expr1_0 =
6295                                                 constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6296                                             let expr2_0 =
6297                                                 constructor_imm(ctx, pattern3_0, pattern12_0)?;
6298                                             let expr3_0 = constructor_a64_sdiv(
6299                                                 ctx, expr0_0, expr1_0, expr2_0,
6300                                             )?;
6301                                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6302                                             return Some(expr4_0);
6303                                         }
6304                                     }
6305                                 }
6306                             }
6307                             // Rule at src/isa/aarch64/lower.isle line 423.
6308                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6309                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
6310                             let expr2_0 = constructor_trap_if_div_overflow(
6311                                 ctx, pattern3_0, expr0_0, expr1_0,
6312                             )?;
6313                             let expr3_0: Type = I64;
6314                             let expr4_0 = constructor_a64_sdiv(ctx, expr3_0, expr2_0, expr1_0)?;
6315                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6316                             return Some(expr5_0);
6317                         }
6318                         &Opcode::Urem => {
6319                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6320                             // Rule at src/isa/aarch64/lower.isle line 464.
6321                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
6322                             let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
6323                             let expr2_0: Type = I64;
6324                             let expr3_0 = constructor_a64_udiv(ctx, expr2_0, expr0_0, expr1_0)?;
6325                             let expr4_0: Type = I64;
6326                             let expr5_0 =
6327                                 constructor_msub(ctx, expr4_0, expr3_0, expr1_0, expr0_0)?;
6328                             let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
6329                             return Some(expr6_0);
6330                         }
6331                         &Opcode::Srem => {
6332                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6333                             // Rule at src/isa/aarch64/lower.isle line 471.
6334                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6335                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
6336                             let expr2_0: Type = I64;
6337                             let expr3_0 = constructor_a64_sdiv(ctx, expr2_0, expr0_0, expr1_0)?;
6338                             let expr4_0: Type = I64;
6339                             let expr5_0 =
6340                                 constructor_msub(ctx, expr4_0, expr3_0, expr1_0, expr0_0)?;
6341                             let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
6342                             return Some(expr6_0);
6343                         }
6344                         _ => {}
6345                     }
6346                 }
6347                 &InstructionData::Unary {
6348                     opcode: ref pattern5_0,
6349                     arg: pattern5_1,
6350                 } => {
6351                     match pattern5_0 {
6352                         &Opcode::Ineg => {
6353                             // Rule at src/isa/aarch64/lower.isle line 173.
6354                             let expr0_0 = C::zero_reg(ctx);
6355                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6356                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
6357                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6358                             return Some(expr3_0);
6359                         }
6360                         &Opcode::Bnot => {
6361                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6362                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6363                                 if let &InstructionData::Binary {
6364                                     opcode: ref pattern9_0,
6365                                     args: ref pattern9_1,
6366                                 } = &pattern8_0
6367                                 {
6368                                     if let &Opcode::Ishl = pattern9_0 {
6369                                         let (pattern11_0, pattern11_1) =
6370                                             C::unpack_value_array_2(ctx, pattern9_1);
6371                                         if let Some(pattern12_0) = C::def_inst(ctx, pattern11_1) {
6372                                             let pattern13_0 = C::inst_data(ctx, pattern12_0);
6373                                             if let &InstructionData::UnaryImm {
6374                                                 opcode: ref pattern14_0,
6375                                                 imm: pattern14_1,
6376                                             } = &pattern13_0
6377                                             {
6378                                                 if let &Opcode::Iconst = pattern14_0 {
6379                                                     let closure16 = || {
6380                                                         return Some(pattern3_0);
6381                                                     };
6382                                                     if let Some(pattern16_0) = closure16() {
6383                                                         if let Some(pattern17_0) =
6384                                                             C::lshl_from_imm64(
6385                                                                 ctx,
6386                                                                 pattern14_1,
6387                                                                 pattern16_0,
6388                                                             )
6389                                                         {
6390                                                             // Rule at src/isa/aarch64/lower.isle line 570.
6391                                                             let expr0_0 = C::zero_reg(ctx);
6392                                                             let expr1_0 =
6393                                                                 C::put_in_reg(ctx, pattern11_0);
6394                                                             let expr2_0 =
6395                                                                 constructor_orr_not_shift(
6396                                                                     ctx,
6397                                                                     pattern3_0,
6398                                                                     expr0_0,
6399                                                                     expr1_0,
6400                                                                     pattern17_0,
6401                                                                 )?;
6402                                                             let expr3_0 = constructor_output_reg(
6403                                                                 ctx, expr2_0,
6404                                                             )?;
6405                                                             return Some(expr3_0);
6406                                                         }
6407                                                     }
6408                                                 }
6409                                             }
6410                                         }
6411                                     }
6412                                 }
6413                             }
6414                             // Rule at src/isa/aarch64/lower.isle line 565.
6415                             let expr0_0 = C::zero_reg(ctx);
6416                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6417                             let expr2_0 = constructor_orr_not(ctx, pattern3_0, expr0_0, expr1_0)?;
6418                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6419                             return Some(expr3_0);
6420                         }
6421                         &Opcode::Uextend => {
6422                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6423                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6424                                 if let &InstructionData::BinaryImm8 {
6425                                     opcode: ref pattern9_0,
6426                                     arg: pattern9_1,
6427                                     imm: pattern9_2,
6428                                 } = &pattern8_0
6429                                 {
6430                                     if let &Opcode::Extractlane = pattern9_0 {
6431                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6432                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6433                                         // Rule at src/isa/aarch64/lower.isle line 487.
6434                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6435                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6436                                         let expr2_0 = constructor_mov_from_vec(
6437                                             ctx,
6438                                             expr0_0,
6439                                             pattern12_0,
6440                                             &expr1_0,
6441                                         )?;
6442                                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6443                                         return Some(expr3_0);
6444                                     }
6445                                 }
6446                             }
6447                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6448                             if let Some(pattern8_0) = C::sinkable_atomic_load(ctx, pattern5_1) {
6449                                 // Rule at src/isa/aarch64/lower.isle line 494.
6450                                 let expr0_0 = C::sink_atomic_load(ctx, &pattern8_0);
6451                                 let expr1_0 = constructor_load_acquire(ctx, pattern7_0, expr0_0)?;
6452                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6453                                 return Some(expr2_0);
6454                             }
6455                             // Rule at src/isa/aarch64/lower.isle line 482.
6456                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6457                             let expr1_0: bool = false;
6458                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6459                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6460                             let expr4_0 =
6461                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6462                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6463                             return Some(expr5_0);
6464                         }
6465                         &Opcode::Sextend => {
6466                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6467                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6468                                 if let &InstructionData::BinaryImm8 {
6469                                     opcode: ref pattern9_0,
6470                                     arg: pattern9_1,
6471                                     imm: pattern9_2,
6472                                 } = &pattern8_0
6473                                 {
6474                                     if let &Opcode::Extractlane = pattern9_0 {
6475                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6476                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6477                                         // Rule at src/isa/aarch64/lower.isle line 519.
6478                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6479                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6480                                         let expr2_0 = constructor_size_from_ty(ctx, pattern3_0)?;
6481                                         let expr3_0 = constructor_mov_from_vec_signed(
6482                                             ctx,
6483                                             expr0_0,
6484                                             pattern12_0,
6485                                             &expr1_0,
6486                                             &expr2_0,
6487                                         )?;
6488                                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6489                                         return Some(expr4_0);
6490                                     }
6491                                 }
6492                             }
6493                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6494                             // Rule at src/isa/aarch64/lower.isle line 514.
6495                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6496                             let expr1_0: bool = true;
6497                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6498                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6499                             let expr4_0 =
6500                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6501                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6502                             return Some(expr5_0);
6503                         }
6504                         _ => {}
6505                     }
6506                 }
6507                 _ => {}
6508             }
6509         }
6510         if let Some(pattern3_0) = C::ty_vec128(ctx, pattern2_0) {
6511             let pattern4_0 = C::inst_data(ctx, pattern0_0);
6512             match &pattern4_0 {
6513                 &InstructionData::Binary {
6514                     opcode: ref pattern5_0,
6515                     args: ref pattern5_1,
6516                 } => {
6517                     match pattern5_0 {
6518                         &Opcode::UaddSat => {
6519                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6520                             // Rule at src/isa/aarch64/lower.isle line 152.
6521                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6522                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6523                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6524                             let expr3_0 = constructor_uqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6525                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6526                             return Some(expr4_0);
6527                         }
6528                         &Opcode::SaddSat => {
6529                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6530                             // Rule at src/isa/aarch64/lower.isle line 157.
6531                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6532                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6533                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6534                             let expr3_0 = constructor_sqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6535                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6536                             return Some(expr4_0);
6537                         }
6538                         &Opcode::UsubSat => {
6539                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6540                             // Rule at src/isa/aarch64/lower.isle line 162.
6541                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6542                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6543                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6544                             let expr3_0 = constructor_uqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6545                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6546                             return Some(expr4_0);
6547                         }
6548                         &Opcode::SsubSat => {
6549                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6550                             // Rule at src/isa/aarch64/lower.isle line 167.
6551                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6552                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6553                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6554                             let expr3_0 = constructor_sqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6555                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6556                             return Some(expr4_0);
6557                         }
6558                         &Opcode::Band => {
6559                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6560                             // Rule at src/isa/aarch64/lower.isle line 597.
6561                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6562                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6563                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6564                             let expr3_0 = constructor_and_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6565                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6566                             return Some(expr4_0);
6567                         }
6568                         &Opcode::Bor => {
6569                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6570                             // Rule at src/isa/aarch64/lower.isle line 610.
6571                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6572                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6573                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6574                             let expr3_0 = constructor_orr_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6575                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6576                             return Some(expr4_0);
6577                         }
6578                         &Opcode::Bxor => {
6579                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6580                             // Rule at src/isa/aarch64/lower.isle line 623.
6581                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6582                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6583                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6584                             let expr3_0 = constructor_eor_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6585                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6586                             return Some(expr4_0);
6587                         }
6588                         &Opcode::BandNot => {
6589                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6590                             // Rule at src/isa/aarch64/lower.isle line 636.
6591                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6592                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6593                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6594                             let expr3_0 = constructor_bic_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6595                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6596                             return Some(expr4_0);
6597                         }
6598                         &Opcode::Ishl => {
6599                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6600                             // Rule at src/isa/aarch64/lower.isle line 700.
6601                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6602                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6603                             let expr2_0 = constructor_vec_dup(ctx, expr1_0, &expr0_0)?;
6604                             let expr3_0 = C::put_in_reg(ctx, pattern7_0);
6605                             let expr4_0 = constructor_sshl(ctx, expr3_0, expr2_0, &expr0_0)?;
6606                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6607                             return Some(expr5_0);
6608                         }
6609                         &Opcode::Ushr => {
6610                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6611                             // Rule at src/isa/aarch64/lower.isle line 758.
6612                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6613                             let expr1_0: Type = I32;
6614                             let expr2_0 = C::zero_reg(ctx);
6615                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6616                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6617                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6618                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6619                             let expr7_0 = constructor_ushl(ctx, expr6_0, expr5_0, &expr0_0)?;
6620                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6621                             return Some(expr8_0);
6622                         }
6623                         &Opcode::Sshr => {
6624                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6625                             // Rule at src/isa/aarch64/lower.isle line 807.
6626                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6627                             let expr1_0: Type = I32;
6628                             let expr2_0 = C::zero_reg(ctx);
6629                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6630                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6631                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6632                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6633                             let expr7_0 = constructor_sshl(ctx, expr6_0, expr5_0, &expr0_0)?;
6634                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6635                             return Some(expr8_0);
6636                         }
6637                         _ => {}
6638                     }
6639                 }
6640                 &InstructionData::Unary {
6641                     opcode: ref pattern5_0,
6642                     arg: pattern5_1,
6643                 } => {
6644                     match pattern5_0 {
6645                         &Opcode::Ineg => {
6646                             // Rule at src/isa/aarch64/lower.isle line 177.
6647                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6648                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6649                             let expr2_0 = constructor_neg(ctx, expr0_0, &expr1_0)?;
6650                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6651                             return Some(expr3_0);
6652                         }
6653                         &Opcode::Bnot => {
6654                             // Rule at src/isa/aarch64/lower.isle line 584.
6655                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6656                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6657                             let expr2_0 = constructor_not(ctx, expr0_0, &expr1_0)?;
6658                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6659                             return Some(expr3_0);
6660                         }
6661                         _ => {}
6662                     }
6663                 }
6664                 _ => {}
6665             }
6666             if let Some(()) = C::not_i64x2(ctx, pattern3_0) {
6667                 let pattern5_0 = C::inst_data(ctx, pattern0_0);
6668                 if let &InstructionData::Binary {
6669                     opcode: ref pattern6_0,
6670                     args: ref pattern6_1,
6671                 } = &pattern5_0
6672                 {
6673                     if let &Opcode::Imul = pattern6_0 {
6674                         let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
6675                         // Rule at src/isa/aarch64/lower.isle line 215.
6676                         let expr0_0 = C::put_in_reg(ctx, pattern8_0);
6677                         let expr1_0 = C::put_in_reg(ctx, pattern8_1);
6678                         let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6679                         let expr3_0 = constructor_mul(ctx, expr0_0, expr1_0, &expr2_0)?;
6680                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6681                         return Some(expr4_0);
6682                     }
6683                 }
6684             }
6685         }
6686     }
6687     return None;
6688 }
6689 
6690 // Generated as internal constructor for term put_nonzero_in_reg_zext64.
6691 pub fn constructor_put_nonzero_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6692     let pattern0_0 = arg0;
6693     let pattern1_0 = C::value_type(ctx, pattern0_0);
6694     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6695         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6696         if let &InstructionData::UnaryImm {
6697             opcode: ref pattern4_0,
6698             imm: pattern4_1,
6699         } = &pattern3_0
6700         {
6701             if let &Opcode::Iconst = pattern4_0 {
6702                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6703                     // Rule at src/isa/aarch64/lower.isle line 400.
6704                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6705                     return Some(expr0_0);
6706                 }
6707             }
6708         }
6709     }
6710     // Rule at src/isa/aarch64/lower.isle line 395.
6711     let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern0_0)?;
6712     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6713     return Some(expr1_0);
6714 }
6715 
6716 // Generated as internal constructor for term put_nonzero_in_reg_sext64.
6717 pub fn constructor_put_nonzero_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6718     let pattern0_0 = arg0;
6719     let pattern1_0 = C::value_type(ctx, pattern0_0);
6720     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6721         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6722         if let &InstructionData::UnaryImm {
6723             opcode: ref pattern4_0,
6724             imm: pattern4_1,
6725         } = &pattern3_0
6726         {
6727             if let &Opcode::Iconst = pattern4_0 {
6728                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6729                     // Rule at src/isa/aarch64/lower.isle line 446.
6730                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6731                     return Some(expr0_0);
6732                 }
6733             }
6734         }
6735     }
6736     // Rule at src/isa/aarch64/lower.isle line 441.
6737     let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern0_0)?;
6738     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6739     return Some(expr1_0);
6740 }
6741 
6742 // Generated as internal constructor for term lower_shl128.
6743 pub fn constructor_lower_shl128<C: Context>(
6744     ctx: &mut C,
6745     arg0: ValueRegs,
6746     arg1: Reg,
6747 ) -> Option<ValueRegs> {
6748     let pattern0_0 = arg0;
6749     let pattern1_0 = arg1;
6750     // Rule at src/isa/aarch64/lower.isle line 683.
6751     let expr0_0: usize = 0;
6752     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6753     let expr2_0: usize = 1;
6754     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6755     let expr4_0: Type = I64;
6756     let expr5_0 = constructor_lsl(ctx, expr4_0, expr1_0, pattern1_0)?;
6757     let expr6_0: Type = I64;
6758     let expr7_0 = constructor_lsl(ctx, expr6_0, expr3_0, pattern1_0)?;
6759     let expr8_0: Type = I32;
6760     let expr9_0 = C::zero_reg(ctx);
6761     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6762     let expr11_0: Type = I64;
6763     let expr12_0: Type = I64;
6764     let expr13_0: u8 = 1;
6765     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6766     let expr15_0 = constructor_lsr_imm(ctx, expr12_0, expr1_0, expr14_0)?;
6767     let expr16_0 = constructor_lsr(ctx, expr11_0, expr15_0, expr10_0)?;
6768     let expr17_0: Type = I64;
6769     let expr18_0 = constructor_orr(ctx, expr17_0, expr7_0, expr16_0)?;
6770     let expr19_0: Type = I64;
6771     let expr20_0: Type = I64;
6772     let expr21_0: u64 = 64;
6773     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6774     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6775     let expr24_0 = Cond::Ne;
6776     let expr25_0 = C::zero_reg(ctx);
6777     let expr26_0 = constructor_csel(ctx, &expr24_0, expr25_0, expr5_0)?;
6778     let expr27_0 = Cond::Ne;
6779     let expr28_0 = constructor_csel(ctx, &expr27_0, expr5_0, expr18_0)?;
6780     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr26_0, &expr28_0)?;
6781     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6782     return Some(expr30_0);
6783 }
6784 
6785 // Generated as internal constructor for term do_shift.
6786 pub fn constructor_do_shift<C: Context>(
6787     ctx: &mut C,
6788     arg0: &ALUOp,
6789     arg1: Type,
6790     arg2: Reg,
6791     arg3: Value,
6792 ) -> Option<Reg> {
6793     let pattern0_0 = arg0;
6794     let pattern1_0 = arg1;
6795     let pattern2_0 = arg2;
6796     let pattern3_0 = arg3;
6797     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
6798         let pattern5_0 = C::inst_data(ctx, pattern4_0);
6799         if let &InstructionData::UnaryImm {
6800             opcode: ref pattern6_0,
6801             imm: pattern6_1,
6802         } = &pattern5_0
6803         {
6804             if let &Opcode::Iconst = pattern6_0 {
6805                 let closure8 = || {
6806                     return Some(pattern1_0);
6807                 };
6808                 if let Some(pattern8_0) = closure8() {
6809                     if let Some(pattern9_0) = C::imm_shift_from_imm64(ctx, pattern6_1, pattern8_0) {
6810                         // Rule at src/isa/aarch64/lower.isle line 740.
6811                         let expr0_0 = constructor_alu_rr_imm_shift(
6812                             ctx, pattern0_0, pattern1_0, pattern2_0, pattern9_0,
6813                         )?;
6814                         return Some(expr0_0);
6815                     }
6816                 }
6817             }
6818         }
6819     }
6820     let pattern0_0 = arg0;
6821     let pattern1_0 = arg1;
6822     if pattern1_0 == I32 {
6823         let pattern3_0 = arg2;
6824         let pattern4_0 = arg3;
6825         // Rule at src/isa/aarch64/lower.isle line 731.
6826         let expr0_0: Type = I32;
6827         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6828         let expr2_0: usize = 0;
6829         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6830         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6831         return Some(expr4_0);
6832     }
6833     if pattern1_0 == I64 {
6834         let pattern3_0 = arg2;
6835         let pattern4_0 = arg3;
6836         // Rule at src/isa/aarch64/lower.isle line 732.
6837         let expr0_0: Type = I64;
6838         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6839         let expr2_0: usize = 0;
6840         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6841         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6842         return Some(expr4_0);
6843     }
6844     if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
6845         let pattern3_0 = arg2;
6846         let pattern4_0 = arg3;
6847         // Rule at src/isa/aarch64/lower.isle line 722.
6848         let expr0_0 = C::put_in_regs(ctx, pattern4_0);
6849         let expr1_0: usize = 0;
6850         let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
6851         let expr3_0: Type = I32;
6852         let expr4_0 = C::shift_mask(ctx, pattern2_0);
6853         let expr5_0 = constructor_and_imm(ctx, expr3_0, expr2_0, expr4_0)?;
6854         let expr6_0: Type = I32;
6855         let expr7_0 = constructor_alu_rrr(ctx, pattern0_0, expr6_0, pattern3_0, expr5_0)?;
6856         return Some(expr7_0);
6857     }
6858     return None;
6859 }
6860 
6861 // Generated as internal constructor for term lower_ushr128.
6862 pub fn constructor_lower_ushr128<C: Context>(
6863     ctx: &mut C,
6864     arg0: ValueRegs,
6865     arg1: Reg,
6866 ) -> Option<ValueRegs> {
6867     let pattern0_0 = arg0;
6868     let pattern1_0 = arg1;
6869     // Rule at src/isa/aarch64/lower.isle line 773.
6870     let expr0_0: usize = 0;
6871     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6872     let expr2_0: usize = 1;
6873     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6874     let expr4_0: Type = I64;
6875     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6876     let expr6_0: Type = I64;
6877     let expr7_0 = constructor_lsr(ctx, expr6_0, expr3_0, pattern1_0)?;
6878     let expr8_0: Type = I32;
6879     let expr9_0 = C::zero_reg(ctx);
6880     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6881     let expr11_0: Type = I64;
6882     let expr12_0: Type = I64;
6883     let expr13_0: u8 = 1;
6884     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6885     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6886     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6887     let expr17_0: Type = I64;
6888     let expr18_0 = constructor_orr(ctx, expr17_0, expr5_0, expr16_0)?;
6889     let expr19_0: Type = I64;
6890     let expr20_0: Type = I64;
6891     let expr21_0: u64 = 64;
6892     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6893     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6894     let expr24_0 = Cond::Ne;
6895     let expr25_0 = constructor_csel(ctx, &expr24_0, expr7_0, expr18_0)?;
6896     let expr26_0 = Cond::Ne;
6897     let expr27_0 = C::zero_reg(ctx);
6898     let expr28_0 = constructor_csel(ctx, &expr26_0, expr27_0, expr7_0)?;
6899     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr25_0, &expr28_0)?;
6900     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6901     return Some(expr30_0);
6902 }
6903 
6904 // Generated as internal constructor for term lower_sshr128.
6905 pub fn constructor_lower_sshr128<C: Context>(
6906     ctx: &mut C,
6907     arg0: ValueRegs,
6908     arg1: Reg,
6909 ) -> Option<ValueRegs> {
6910     let pattern0_0 = arg0;
6911     let pattern1_0 = arg1;
6912     // Rule at src/isa/aarch64/lower.isle line 823.
6913     let expr0_0: usize = 0;
6914     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6915     let expr2_0: usize = 1;
6916     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6917     let expr4_0: Type = I64;
6918     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6919     let expr6_0: Type = I64;
6920     let expr7_0 = constructor_asr(ctx, expr6_0, expr3_0, pattern1_0)?;
6921     let expr8_0: Type = I32;
6922     let expr9_0 = C::zero_reg(ctx);
6923     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6924     let expr11_0: Type = I64;
6925     let expr12_0: Type = I64;
6926     let expr13_0: u8 = 1;
6927     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6928     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6929     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6930     let expr17_0: Type = I64;
6931     let expr18_0: u8 = 63;
6932     let expr19_0 = C::imm_shift_from_u8(ctx, expr18_0);
6933     let expr20_0 = constructor_asr_imm(ctx, expr17_0, expr3_0, expr19_0)?;
6934     let expr21_0: Type = I64;
6935     let expr22_0 = constructor_orr(ctx, expr21_0, expr5_0, expr16_0)?;
6936     let expr23_0: Type = I64;
6937     let expr24_0: Type = I64;
6938     let expr25_0: u64 = 64;
6939     let expr26_0 = C::u64_into_imm_logic(ctx, expr24_0, expr25_0);
6940     let expr27_0 = constructor_tst_imm(ctx, expr23_0, pattern1_0, expr26_0)?;
6941     let expr28_0 = Cond::Ne;
6942     let expr29_0 = constructor_csel(ctx, &expr28_0, expr7_0, expr22_0)?;
6943     let expr30_0 = Cond::Ne;
6944     let expr31_0 = constructor_csel(ctx, &expr30_0, expr20_0, expr7_0)?;
6945     let expr32_0 = constructor_consumes_flags_concat(ctx, &expr29_0, &expr31_0)?;
6946     let expr33_0 = constructor_with_flags(ctx, &expr27_0, &expr32_0)?;
6947     return Some(expr33_0);
6948 }
6949 
6950 // Generated as internal constructor for term small_rotr.
6951 pub fn constructor_small_rotr<C: Context>(
6952     ctx: &mut C,
6953     arg0: Type,
6954     arg1: Reg,
6955     arg2: Reg,
6956 ) -> Option<Reg> {
6957     let pattern0_0 = arg0;
6958     let pattern1_0 = arg1;
6959     let pattern2_0 = arg2;
6960     // Rule at src/isa/aarch64/lower.isle line 933.
6961     let expr0_0: Type = I32;
6962     let expr1_0 = C::rotr_mask(ctx, pattern0_0);
6963     let expr2_0 = constructor_and_imm(ctx, expr0_0, pattern2_0, expr1_0)?;
6964     let expr3_0: Type = I32;
6965     let expr4_0 = C::ty_bits(ctx, pattern0_0);
6966     let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
6967     let expr6_0 = constructor_sub_imm(ctx, expr3_0, expr2_0, expr5_0)?;
6968     let expr7_0: Type = I32;
6969     let expr8_0 = C::zero_reg(ctx);
6970     let expr9_0 = constructor_sub(ctx, expr7_0, expr8_0, expr6_0)?;
6971     let expr10_0: Type = I32;
6972     let expr11_0 = constructor_lsr(ctx, expr10_0, pattern1_0, expr2_0)?;
6973     let expr12_0: Type = I32;
6974     let expr13_0 = constructor_lsl(ctx, expr12_0, pattern1_0, expr9_0)?;
6975     let expr14_0: Type = I32;
6976     let expr15_0 = constructor_orr(ctx, expr14_0, expr13_0, expr11_0)?;
6977     return Some(expr15_0);
6978 }
6979 
6980 // Generated as internal constructor for term small_rotr_imm.
6981 pub fn constructor_small_rotr_imm<C: Context>(
6982     ctx: &mut C,
6983     arg0: Type,
6984     arg1: Reg,
6985     arg2: ImmShift,
6986 ) -> Option<Reg> {
6987     let pattern0_0 = arg0;
6988     let pattern1_0 = arg1;
6989     let pattern2_0 = arg2;
6990     // Rule at src/isa/aarch64/lower.isle line 954.
6991     let expr0_0: Type = I32;
6992     let expr1_0 = constructor_lsr_imm(ctx, expr0_0, pattern1_0, pattern2_0)?;
6993     let expr2_0: Type = I32;
6994     let expr3_0 = C::rotr_opposite_amount(ctx, pattern0_0, pattern2_0);
6995     let expr4_0 = constructor_lsl_imm(ctx, expr2_0, pattern1_0, expr3_0)?;
6996     let expr5_0: Type = I32;
6997     let expr6_0 = constructor_orr(ctx, expr5_0, expr4_0, expr1_0)?;
6998     return Some(expr6_0);
6999 }
7000 
7001 // Generated as internal constructor for term lower_clz128.
7002 pub fn constructor_lower_clz128<C: Context>(ctx: &mut C, arg0: ValueRegs) -> Option<ValueRegs> {
7003     let pattern0_0 = arg0;
7004     // Rule at src/isa/aarch64/lower.isle line 1019.
7005     let expr0_0: Type = I64;
7006     let expr1_0: usize = 1;
7007     let expr2_0 = C::value_regs_get(ctx, pattern0_0, expr1_0);
7008     let expr3_0 = constructor_a64_clz(ctx, expr0_0, expr2_0)?;
7009     let expr4_0: Type = I64;
7010     let expr5_0: usize = 0;
7011     let expr6_0 = C::value_regs_get(ctx, pattern0_0, expr5_0);
7012     let expr7_0 = constructor_a64_clz(ctx, expr4_0, expr6_0)?;
7013     let expr8_0: Type = I64;
7014     let expr9_0: u8 = 6;
7015     let expr10_0 = C::imm_shift_from_u8(ctx, expr9_0);
7016     let expr11_0 = constructor_lsr_imm(ctx, expr8_0, expr3_0, expr10_0)?;
7017     let expr12_0: Type = I64;
7018     let expr13_0 = constructor_madd(ctx, expr12_0, expr7_0, expr11_0, expr3_0)?;
7019     let expr14_0: Type = I64;
7020     let expr15_0: u64 = 0;
7021     let expr16_0 = constructor_imm(ctx, expr14_0, expr15_0)?;
7022     let expr17_0 = C::value_regs(ctx, expr13_0, expr16_0);
7023     return Some(expr17_0);
7024 }
7025