1 // GENERATED BY ISLE. DO NOT EDIT!
2 //
3 // Generated automatically from the instruction-selection DSL code in:
4 // - src/clif.isle
5 // - src/prelude.isle
6 // - src/isa/aarch64/inst.isle
7 // - src/isa/aarch64/lower.isle
8 
9 #![allow(dead_code, unreachable_code, unreachable_patterns)]
10 #![allow(unused_imports, unused_variables, non_snake_case)]
11 #![allow(irrefutable_let_patterns)]
12 
13 use super::*; // Pulls in all external types.
14 
15 /// Context during lowering: an implementation of this trait
16 /// must be provided with all external constructors and extractors.
17 /// A mutable borrow is passed along through all lowering logic.
18 pub trait Context {
19     fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
20     fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
21     fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
22     fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
23     fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
24     fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
25     fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
26     fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
27     fn value_regs_invalid(&mut self) -> ValueRegs;
28     fn output_none(&mut self) -> InstOutput;
29     fn output(&mut self, arg0: ValueRegs) -> InstOutput;
30     fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput;
31     fn output_builder_new(&mut self) -> InstOutputBuilder;
32     fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit;
33     fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput;
34     fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
35     fn invalid_reg(&mut self) -> Reg;
36     fn put_in_reg(&mut self, arg0: Value) -> Reg;
37     fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
38     fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
39     fn u8_as_u64(&mut self, arg0: u8) -> u64;
40     fn u16_as_u64(&mut self, arg0: u16) -> u64;
41     fn u32_as_u64(&mut self, arg0: u32) -> u64;
42     fn i64_as_u64(&mut self, arg0: i64) -> u64;
43     fn u64_add(&mut self, arg0: u64, arg1: u64) -> u64;
44     fn u64_sub(&mut self, arg0: u64, arg1: u64) -> u64;
45     fn u64_and(&mut self, arg0: u64, arg1: u64) -> u64;
46     fn ty_bits(&mut self, arg0: Type) -> u8;
47     fn ty_bits_u16(&mut self, arg0: Type) -> u16;
48     fn ty_bits_u64(&mut self, arg0: Type) -> u64;
49     fn ty_mask(&mut self, arg0: Type) -> u64;
50     fn ty_bytes(&mut self, arg0: Type) -> u16;
51     fn lane_type(&mut self, arg0: Type) -> Type;
52     fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
53     fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
54     fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
55     fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
56     fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
57     fn ty_int_bool_64(&mut self, arg0: Type) -> Option<Type>;
58     fn ty_int_bool_ref_64(&mut self, arg0: Type) -> Option<Type>;
59     fn ty_int_bool_128(&mut self, arg0: Type) -> Option<Type>;
60     fn ty_scalar_float(&mut self, arg0: Type) -> Option<Type>;
61     fn ty_vec128(&mut self, arg0: Type) -> Option<Type>;
62     fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
63     fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
64     fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>;
65     fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>;
66     fn value_slice_len(&mut self, arg0: ValueSlice) -> usize;
67     fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value;
68     fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
69     fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
70     fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
71     fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
72     fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
73     fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
74     fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
75     fn first_result(&mut self, arg0: Inst) -> Option<Value>;
76     fn inst_data(&mut self, arg0: Inst) -> InstructionData;
77     fn value_type(&mut self, arg0: Value) -> Type;
78     fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
79     fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
80     fn offset32_to_u32(&mut self, arg0: Offset32) -> u32;
81     fn emit(&mut self, arg0: &MInst) -> Unit;
82     fn emit_safepoint(&mut self, arg0: &MInst) -> Unit;
83     fn trap_code_division_by_zero(&mut self) -> TrapCode;
84     fn trap_code_integer_overflow(&mut self) -> TrapCode;
85     fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
86     fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
87     fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
88     fn symbol_value_data(
89         &mut self,
90         arg0: GlobalValue,
91     ) -> Option<(ExternalName, RelocDistance, i64)>;
92     fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
93     fn move_wide_const_from_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
94     fn move_wide_const_from_negated_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
95     fn imm_logic_from_u64(&mut self, arg0: u64, arg1: Type) -> Option<ImmLogic>;
96     fn imm_logic_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmLogic>;
97     fn imm_shift_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmShift>;
98     fn imm_shift_from_u8(&mut self, arg0: u8) -> ImmShift;
99     fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12>;
100     fn u8_into_uimm5(&mut self, arg0: u8) -> UImm5;
101     fn u8_into_imm12(&mut self, arg0: u8) -> Imm12;
102     fn u64_into_imm_logic(&mut self, arg0: Type, arg1: u64) -> ImmLogic;
103     fn imm12_from_negated_u64(&mut self, arg0: u64) -> Option<Imm12>;
104     fn lshl_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ShiftOpAndAmt>;
105     fn integral_ty(&mut self, arg0: Type) -> Option<Type>;
106     fn extended_value_from_value(&mut self, arg0: Value) -> Option<ExtendedValue>;
107     fn put_extended_in_reg(&mut self, arg0: &ExtendedValue) -> Reg;
108     fn get_extended_op(&mut self, arg0: &ExtendedValue) -> ExtendOp;
109     fn nzcv(&mut self, arg0: bool, arg1: bool, arg2: bool, arg3: bool) -> NZCV;
110     fn cond_br_zero(&mut self, arg0: Reg) -> CondBrKind;
111     fn cond_br_cond(&mut self, arg0: &Cond) -> CondBrKind;
112     fn zero_reg(&mut self) -> Reg;
113     fn writable_zero_reg(&mut self) -> WritableReg;
114     fn load_constant64_full(&mut self, arg0: u64) -> Reg;
115     fn sinkable_atomic_load(&mut self, arg0: Value) -> Option<SinkableAtomicLoad>;
116     fn sink_atomic_load(&mut self, arg0: &SinkableAtomicLoad) -> Reg;
117     fn zero_value_f32(&mut self, arg0: Ieee32) -> Option<Ieee32>;
118     fn zero_value_f64(&mut self, arg0: Ieee64) -> Option<Ieee64>;
119     fn float_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &FloatCC) -> VecMisc2;
120     fn float_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &FloatCC) -> VecMisc2;
121     fn fcmp_zero_cond(&mut self, arg0: &FloatCC) -> Option<FloatCC>;
122     fn fcmp_zero_cond_not_eq(&mut self, arg0: &FloatCC) -> Option<FloatCC>;
123     fn zero_value(&mut self, arg0: Imm64) -> Option<Imm64>;
124     fn int_cc_cmp_zero_to_vec_misc_op(&mut self, arg0: &IntCC) -> VecMisc2;
125     fn int_cc_cmp_zero_to_vec_misc_op_swap(&mut self, arg0: &IntCC) -> VecMisc2;
126     fn icmp_zero_cond(&mut self, arg0: &IntCC) -> Option<IntCC>;
127     fn icmp_zero_cond_not_eq(&mut self, arg0: &IntCC) -> Option<IntCC>;
128     fn safe_divisor_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
129     fn shift_mask(&mut self, arg0: Type) -> ImmLogic;
130     fn negate_imm_shift(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
131     fn rotr_mask(&mut self, arg0: Type) -> ImmLogic;
132     fn rotr_opposite_amount(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
133 }
134 
135 /// Internal type SideEffectNoResult: defined at src/prelude.isle line 405.
136 #[derive(Clone, Debug)]
137 pub enum SideEffectNoResult {
138     Inst { inst: MInst },
139 }
140 
141 /// Internal type ProducesFlags: defined at src/prelude.isle line 427.
142 #[derive(Clone, Debug)]
143 pub enum ProducesFlags {
144     ProducesFlagsSideEffect { inst: MInst },
145     ProducesFlagsReturnsReg { inst: MInst, result: Reg },
146     ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg },
147 }
148 
149 /// Internal type ConsumesFlags: defined at src/prelude.isle line 438.
150 #[derive(Clone, Debug)]
151 pub enum ConsumesFlags {
152     ConsumesFlagsReturnsResultWithProducer {
153         inst: MInst,
154         result: Reg,
155     },
156     ConsumesFlagsReturnsReg {
157         inst: MInst,
158         result: Reg,
159     },
160     ConsumesFlagsTwiceReturnsValueRegs {
161         inst1: MInst,
162         inst2: MInst,
163         result: ValueRegs,
164     },
165     ConsumesFlagsFourTimesReturnsValueRegs {
166         inst1: MInst,
167         inst2: MInst,
168         inst3: MInst,
169         inst4: MInst,
170         result: ValueRegs,
171     },
172 }
173 
174 /// Internal type MInst: defined at src/isa/aarch64/inst.isle line 2.
175 #[derive(Clone, Debug)]
176 pub enum MInst {
177     Nop0,
178     Nop4,
179     AluRRR {
180         alu_op: ALUOp,
181         size: OperandSize,
182         rd: WritableReg,
183         rn: Reg,
184         rm: Reg,
185     },
186     AluRRRR {
187         alu_op: ALUOp3,
188         rd: WritableReg,
189         rn: Reg,
190         rm: Reg,
191         ra: Reg,
192     },
193     AluRRImm12 {
194         alu_op: ALUOp,
195         size: OperandSize,
196         rd: WritableReg,
197         rn: Reg,
198         imm12: Imm12,
199     },
200     AluRRImmLogic {
201         alu_op: ALUOp,
202         size: OperandSize,
203         rd: WritableReg,
204         rn: Reg,
205         imml: ImmLogic,
206     },
207     AluRRImmShift {
208         alu_op: ALUOp,
209         size: OperandSize,
210         rd: WritableReg,
211         rn: Reg,
212         immshift: ImmShift,
213     },
214     AluRRRShift {
215         alu_op: ALUOp,
216         size: OperandSize,
217         rd: WritableReg,
218         rn: Reg,
219         rm: Reg,
220         shiftop: ShiftOpAndAmt,
221     },
222     AluRRRExtend {
223         alu_op: ALUOp,
224         size: OperandSize,
225         rd: WritableReg,
226         rn: Reg,
227         rm: Reg,
228         extendop: ExtendOp,
229     },
230     BitRR {
231         op: BitOp,
232         size: OperandSize,
233         rd: WritableReg,
234         rn: Reg,
235     },
236     ULoad8 {
237         rd: WritableReg,
238         mem: AMode,
239         flags: MemFlags,
240     },
241     SLoad8 {
242         rd: WritableReg,
243         mem: AMode,
244         flags: MemFlags,
245     },
246     ULoad16 {
247         rd: WritableReg,
248         mem: AMode,
249         flags: MemFlags,
250     },
251     SLoad16 {
252         rd: WritableReg,
253         mem: AMode,
254         flags: MemFlags,
255     },
256     ULoad32 {
257         rd: WritableReg,
258         mem: AMode,
259         flags: MemFlags,
260     },
261     SLoad32 {
262         rd: WritableReg,
263         mem: AMode,
264         flags: MemFlags,
265     },
266     ULoad64 {
267         rd: WritableReg,
268         mem: AMode,
269         flags: MemFlags,
270     },
271     Store8 {
272         rd: Reg,
273         mem: AMode,
274         flags: MemFlags,
275     },
276     Store16 {
277         rd: Reg,
278         mem: AMode,
279         flags: MemFlags,
280     },
281     Store32 {
282         rd: Reg,
283         mem: AMode,
284         flags: MemFlags,
285     },
286     Store64 {
287         rd: Reg,
288         mem: AMode,
289         flags: MemFlags,
290     },
291     StoreP64 {
292         rt: Reg,
293         rt2: Reg,
294         mem: PairAMode,
295         flags: MemFlags,
296     },
297     LoadP64 {
298         rt: WritableReg,
299         rt2: WritableReg,
300         mem: PairAMode,
301         flags: MemFlags,
302     },
303     Mov64 {
304         rd: WritableReg,
305         rm: Reg,
306     },
307     Mov32 {
308         rd: WritableReg,
309         rm: Reg,
310     },
311     MovZ {
312         rd: WritableReg,
313         imm: MoveWideConst,
314         size: OperandSize,
315     },
316     MovN {
317         rd: WritableReg,
318         imm: MoveWideConst,
319         size: OperandSize,
320     },
321     MovK {
322         rd: WritableReg,
323         imm: MoveWideConst,
324         size: OperandSize,
325     },
326     Extend {
327         rd: WritableReg,
328         rn: Reg,
329         signed: bool,
330         from_bits: u8,
331         to_bits: u8,
332     },
333     CSel {
334         rd: WritableReg,
335         cond: Cond,
336         rn: Reg,
337         rm: Reg,
338     },
339     CSet {
340         rd: WritableReg,
341         cond: Cond,
342     },
343     CSetm {
344         rd: WritableReg,
345         cond: Cond,
346     },
347     CCmpImm {
348         size: OperandSize,
349         rn: Reg,
350         imm: UImm5,
351         nzcv: NZCV,
352         cond: Cond,
353     },
354     AtomicRMWLoop {
355         ty: Type,
356         op: AtomicRmwOp,
357     },
358     AtomicRMW {
359         op: AtomicRMWOp,
360         rs: Reg,
361         rt: WritableReg,
362         rn: Reg,
363         ty: Type,
364     },
365     AtomicCAS {
366         rs: WritableReg,
367         rt: Reg,
368         rn: Reg,
369         ty: Type,
370     },
371     AtomicCASLoop {
372         ty: Type,
373     },
374     LoadAcquire {
375         access_ty: Type,
376         rt: WritableReg,
377         rn: Reg,
378     },
379     StoreRelease {
380         access_ty: Type,
381         rt: Reg,
382         rn: Reg,
383     },
384     Fence,
385     FpuMove64 {
386         rd: WritableReg,
387         rn: Reg,
388     },
389     FpuMove128 {
390         rd: WritableReg,
391         rn: Reg,
392     },
393     FpuMoveFromVec {
394         rd: WritableReg,
395         rn: Reg,
396         idx: u8,
397         size: VectorSize,
398     },
399     FpuExtend {
400         rd: WritableReg,
401         rn: Reg,
402         size: ScalarSize,
403     },
404     FpuRR {
405         fpu_op: FPUOp1,
406         rd: WritableReg,
407         rn: Reg,
408     },
409     FpuRRR {
410         fpu_op: FPUOp2,
411         rd: WritableReg,
412         rn: Reg,
413         rm: Reg,
414     },
415     FpuRRI {
416         fpu_op: FPUOpRI,
417         rd: WritableReg,
418         rn: Reg,
419     },
420     FpuRRRR {
421         fpu_op: FPUOp3,
422         rd: WritableReg,
423         rn: Reg,
424         rm: Reg,
425         ra: Reg,
426     },
427     FpuCmp32 {
428         rn: Reg,
429         rm: Reg,
430     },
431     FpuCmp64 {
432         rn: Reg,
433         rm: Reg,
434     },
435     FpuLoad32 {
436         rd: WritableReg,
437         mem: AMode,
438         flags: MemFlags,
439     },
440     FpuStore32 {
441         rd: Reg,
442         mem: AMode,
443         flags: MemFlags,
444     },
445     FpuLoad64 {
446         rd: WritableReg,
447         mem: AMode,
448         flags: MemFlags,
449     },
450     FpuStore64 {
451         rd: Reg,
452         mem: AMode,
453         flags: MemFlags,
454     },
455     FpuLoad128 {
456         rd: WritableReg,
457         mem: AMode,
458         flags: MemFlags,
459     },
460     FpuStore128 {
461         rd: Reg,
462         mem: AMode,
463         flags: MemFlags,
464     },
465     FpuLoadP64 {
466         rt: WritableReg,
467         rt2: WritableReg,
468         mem: PairAMode,
469         flags: MemFlags,
470     },
471     FpuStoreP64 {
472         rt: Reg,
473         rt2: Reg,
474         mem: PairAMode,
475         flags: MemFlags,
476     },
477     FpuLoadP128 {
478         rt: WritableReg,
479         rt2: WritableReg,
480         mem: PairAMode,
481         flags: MemFlags,
482     },
483     FpuStoreP128 {
484         rt: Reg,
485         rt2: Reg,
486         mem: PairAMode,
487         flags: MemFlags,
488     },
489     LoadFpuConst64 {
490         rd: WritableReg,
491         const_data: u64,
492     },
493     LoadFpuConst128 {
494         rd: WritableReg,
495         const_data: u128,
496     },
497     FpuToInt {
498         op: FpuToIntOp,
499         rd: WritableReg,
500         rn: Reg,
501     },
502     IntToFpu {
503         op: IntToFpuOp,
504         rd: WritableReg,
505         rn: Reg,
506     },
507     FpuCSel32 {
508         rd: WritableReg,
509         rn: Reg,
510         rm: Reg,
511         cond: Cond,
512     },
513     FpuCSel64 {
514         rd: WritableReg,
515         rn: Reg,
516         rm: Reg,
517         cond: Cond,
518     },
519     FpuRound {
520         op: FpuRoundMode,
521         rd: WritableReg,
522         rn: Reg,
523     },
524     MovToFpu {
525         rd: WritableReg,
526         rn: Reg,
527         size: ScalarSize,
528     },
529     FpuMoveFPImm {
530         rd: WritableReg,
531         imm: ASIMDFPModImm,
532         size: ScalarSize,
533     },
534     MovToVec {
535         rd: WritableReg,
536         rn: Reg,
537         idx: u8,
538         size: VectorSize,
539     },
540     MovFromVec {
541         rd: WritableReg,
542         rn: Reg,
543         idx: u8,
544         size: VectorSize,
545     },
546     MovFromVecSigned {
547         rd: WritableReg,
548         rn: Reg,
549         idx: u8,
550         size: VectorSize,
551         scalar_size: OperandSize,
552     },
553     VecDup {
554         rd: WritableReg,
555         rn: Reg,
556         size: VectorSize,
557     },
558     VecDupFromFpu {
559         rd: WritableReg,
560         rn: Reg,
561         size: VectorSize,
562     },
563     VecDupFPImm {
564         rd: WritableReg,
565         imm: ASIMDFPModImm,
566         size: VectorSize,
567     },
568     VecDupImm {
569         rd: WritableReg,
570         imm: ASIMDMovModImm,
571         invert: bool,
572         size: VectorSize,
573     },
574     VecExtend {
575         t: VecExtendOp,
576         rd: WritableReg,
577         rn: Reg,
578         high_half: bool,
579     },
580     VecMovElement {
581         rd: WritableReg,
582         rn: Reg,
583         dest_idx: u8,
584         src_idx: u8,
585         size: VectorSize,
586     },
587     VecRRLong {
588         op: VecRRLongOp,
589         rd: WritableReg,
590         rn: Reg,
591         high_half: bool,
592     },
593     VecRRNarrow {
594         op: VecRRNarrowOp,
595         rd: WritableReg,
596         rn: Reg,
597         high_half: bool,
598     },
599     VecRRPair {
600         op: VecPairOp,
601         rd: WritableReg,
602         rn: Reg,
603     },
604     VecRRRLong {
605         alu_op: VecRRRLongOp,
606         rd: WritableReg,
607         rn: Reg,
608         rm: Reg,
609         high_half: bool,
610     },
611     VecRRPairLong {
612         op: VecRRPairLongOp,
613         rd: WritableReg,
614         rn: Reg,
615     },
616     VecRRR {
617         alu_op: VecALUOp,
618         rd: WritableReg,
619         rn: Reg,
620         rm: Reg,
621         size: VectorSize,
622     },
623     VecMisc {
624         op: VecMisc2,
625         rd: WritableReg,
626         rn: Reg,
627         size: VectorSize,
628     },
629     VecLanes {
630         op: VecLanesOp,
631         rd: WritableReg,
632         rn: Reg,
633         size: VectorSize,
634     },
635     VecShiftImm {
636         op: VecShiftImmOp,
637         rd: WritableReg,
638         rn: Reg,
639         size: VectorSize,
640         imm: u8,
641     },
642     VecExtract {
643         rd: WritableReg,
644         rn: Reg,
645         rm: Reg,
646         imm4: u8,
647     },
648     VecTbl {
649         rd: WritableReg,
650         rn: Reg,
651         rm: Reg,
652         is_extension: bool,
653     },
654     VecTbl2 {
655         rd: WritableReg,
656         rn: Reg,
657         rn2: Reg,
658         rm: Reg,
659         is_extension: bool,
660     },
661     VecLoadReplicate {
662         rd: WritableReg,
663         rn: Reg,
664         size: VectorSize,
665     },
666     VecCSel {
667         rd: WritableReg,
668         rn: Reg,
669         rm: Reg,
670         cond: Cond,
671     },
672     MovToNZCV {
673         rn: Reg,
674     },
675     MovFromNZCV {
676         rd: WritableReg,
677     },
678     Call {
679         info: BoxCallInfo,
680     },
681     CallInd {
682         info: BoxCallIndInfo,
683     },
684     Ret,
685     EpiloguePlaceholder,
686     Jump {
687         dest: BranchTarget,
688     },
689     CondBr {
690         taken: BranchTarget,
691         not_taken: BranchTarget,
692         kind: CondBrKind,
693     },
694     TrapIf {
695         kind: CondBrKind,
696         trap_code: TrapCode,
697     },
698     IndirectBr {
699         rn: Reg,
700         targets: VecMachLabel,
701     },
702     Brk,
703     Udf {
704         trap_code: TrapCode,
705     },
706     Adr {
707         rd: WritableReg,
708         off: i32,
709     },
710     Word4 {
711         data: u32,
712     },
713     Word8 {
714         data: u64,
715     },
716     JTSequence {
717         info: BoxJTSequenceInfo,
718         ridx: Reg,
719         rtmp1: WritableReg,
720         rtmp2: WritableReg,
721     },
722     LoadExtName {
723         rd: WritableReg,
724         name: BoxExternalName,
725         offset: i64,
726     },
727     LoadAddr {
728         rd: WritableReg,
729         mem: AMode,
730     },
731     VirtualSPOffsetAdj {
732         offset: i64,
733     },
734     EmitIsland {
735         needed_space: CodeOffset,
736     },
737     ElfTlsGetAddr {
738         symbol: ExternalName,
739     },
740     ValueLabelMarker {
741         reg: Reg,
742         label: ValueLabel,
743     },
744     Unwind {
745         inst: UnwindInst,
746     },
747 }
748 
749 /// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 796.
750 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
751 pub enum ALUOp {
752     Add,
753     Sub,
754     Orr,
755     OrrNot,
756     And,
757     AndS,
758     AndNot,
759     Eor,
760     EorNot,
761     AddS,
762     SubS,
763     SMulH,
764     UMulH,
765     SDiv,
766     UDiv,
767     RotR,
768     Lsr,
769     Asr,
770     Lsl,
771     Adc,
772     AdcS,
773     Sbc,
774     SbcS,
775 }
776 
777 /// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 834.
778 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
779 pub enum ALUOp3 {
780     MAdd32,
781     MAdd64,
782     MSub32,
783     MSub64,
784 }
785 
786 /// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 877.
787 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
788 pub enum BitOp {
789     RBit,
790     Clz,
791     Cls,
792 }
793 
794 /// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 944.
795 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
796 pub enum FPUOp1 {
797     Abs32,
798     Abs64,
799     Neg32,
800     Neg64,
801     Sqrt32,
802     Sqrt64,
803     Cvt32To64,
804     Cvt64To32,
805 }
806 
807 /// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 957.
808 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
809 pub enum FPUOp2 {
810     Add32,
811     Add64,
812     Sub32,
813     Sub64,
814     Mul32,
815     Mul64,
816     Div32,
817     Div64,
818     Max32,
819     Max64,
820     Min32,
821     Min64,
822     Sqadd64,
823     Uqadd64,
824     Sqsub64,
825     Uqsub64,
826 }
827 
828 /// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 982.
829 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
830 pub enum FPUOp3 {
831     MAdd32,
832     MAdd64,
833 }
834 
835 /// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 989.
836 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
837 pub enum FpuToIntOp {
838     F32ToU32,
839     F32ToI32,
840     F32ToU64,
841     F32ToI64,
842     F64ToU32,
843     F64ToI32,
844     F64ToU64,
845     F64ToI64,
846 }
847 
848 /// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 1002.
849 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
850 pub enum IntToFpuOp {
851     U32ToF32,
852     I32ToF32,
853     U32ToF64,
854     I32ToF64,
855     U64ToF32,
856     I64ToF32,
857     U64ToF64,
858     I64ToF64,
859 }
860 
861 /// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 1016.
862 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
863 pub enum FpuRoundMode {
864     Minus32,
865     Minus64,
866     Plus32,
867     Plus64,
868     Zero32,
869     Zero64,
870     Nearest32,
871     Nearest64,
872 }
873 
874 /// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 1029.
875 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
876 pub enum VecExtendOp {
877     Sxtl8,
878     Sxtl16,
879     Sxtl32,
880     Uxtl8,
881     Uxtl16,
882     Uxtl32,
883 }
884 
885 /// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1046.
886 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
887 pub enum VecALUOp {
888     Sqadd,
889     Uqadd,
890     Sqsub,
891     Uqsub,
892     Cmeq,
893     Cmge,
894     Cmgt,
895     Cmhs,
896     Cmhi,
897     Fcmeq,
898     Fcmgt,
899     Fcmge,
900     And,
901     Bic,
902     Orr,
903     Eor,
904     Bsl,
905     Umaxp,
906     Add,
907     Sub,
908     Mul,
909     Sshl,
910     Ushl,
911     Umin,
912     Smin,
913     Umax,
914     Smax,
915     Urhadd,
916     Fadd,
917     Fsub,
918     Fdiv,
919     Fmax,
920     Fmin,
921     Fmul,
922     Addp,
923     Zip1,
924     Sqrdmulh,
925 }
926 
927 /// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1125.
928 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
929 pub enum VecMisc2 {
930     Not,
931     Neg,
932     Abs,
933     Fabs,
934     Fneg,
935     Fsqrt,
936     Rev64,
937     Fcvtzs,
938     Fcvtzu,
939     Scvtf,
940     Ucvtf,
941     Frintn,
942     Frintz,
943     Frintm,
944     Frintp,
945     Cnt,
946     Cmeq0,
947     Cmge0,
948     Cmgt0,
949     Cmle0,
950     Cmlt0,
951     Fcmeq0,
952     Fcmge0,
953     Fcmgt0,
954     Fcmle0,
955     Fcmlt0,
956 }
957 
958 /// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1182.
959 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
960 pub enum VecRRLongOp {
961     Fcvtl16,
962     Fcvtl32,
963     Shll8,
964     Shll16,
965     Shll32,
966 }
967 
968 /// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1197.
969 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
970 pub enum VecRRNarrowOp {
971     Xtn16,
972     Xtn32,
973     Xtn64,
974     Sqxtn16,
975     Sqxtn32,
976     Sqxtn64,
977     Sqxtun16,
978     Sqxtun32,
979     Sqxtun64,
980     Uqxtn16,
981     Uqxtn32,
982     Uqxtn64,
983     Fcvtn32,
984     Fcvtn64,
985 }
986 
987 /// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1229.
988 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
989 pub enum VecRRRLongOp {
990     Smull8,
991     Smull16,
992     Smull32,
993     Umull8,
994     Umull16,
995     Umull32,
996     Umlal8,
997     Umlal16,
998     Umlal32,
999 }
1000 
1001 /// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1246.
1002 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1003 pub enum VecPairOp {
1004     Addp,
1005 }
1006 
1007 /// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1254.
1008 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1009 pub enum VecRRPairLongOp {
1010     Saddlp8,
1011     Saddlp16,
1012     Uaddlp8,
1013     Uaddlp16,
1014 }
1015 
1016 /// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1265.
1017 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1018 pub enum VecLanesOp {
1019     Addv,
1020     Uminv,
1021 }
1022 
1023 /// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1274.
1024 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1025 pub enum VecShiftImmOp {
1026     Shl,
1027     Ushr,
1028     Sshr,
1029 }
1030 
1031 /// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1285.
1032 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
1033 pub enum AtomicRMWOp {
1034     Add,
1035     Clr,
1036     Eor,
1037     Set,
1038     Smax,
1039     Smin,
1040     Umax,
1041     Umin,
1042 }
1043 
1044 // Generated as internal constructor for term output_reg.
1045 pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
1046     let pattern0_0 = arg0;
1047     // Rule at src/prelude.isle line 86.
1048     let expr0_0 = C::value_reg(ctx, pattern0_0);
1049     let expr1_0 = C::output(ctx, expr0_0);
1050     return Some(expr1_0);
1051 }
1052 
1053 // Generated as internal constructor for term output_value.
1054 pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> {
1055     let pattern0_0 = arg0;
1056     // Rule at src/prelude.isle line 90.
1057     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1058     let expr1_0 = C::output(ctx, expr0_0);
1059     return Some(expr1_0);
1060 }
1061 
1062 // Generated as internal constructor for term temp_reg.
1063 pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
1064     let pattern0_0 = arg0;
1065     // Rule at src/prelude.isle line 110.
1066     let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
1067     let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
1068     return Some(expr1_0);
1069 }
1070 
1071 // Generated as internal constructor for term lo_reg.
1072 pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
1073     let pattern0_0 = arg0;
1074     // Rule at src/prelude.isle line 145.
1075     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1076     let expr1_0: usize = 0;
1077     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1078     return Some(expr2_0);
1079 }
1080 
1081 // Generated as internal constructor for term side_effect.
1082 pub fn constructor_side_effect<C: Context>(
1083     ctx: &mut C,
1084     arg0: &SideEffectNoResult,
1085 ) -> Option<InstOutput> {
1086     let pattern0_0 = arg0;
1087     if let &SideEffectNoResult::Inst {
1088         inst: ref pattern1_0,
1089     } = pattern0_0
1090     {
1091         // Rule at src/prelude.isle line 410.
1092         let expr0_0 = C::emit(ctx, pattern1_0);
1093         let expr1_0 = C::output_none(ctx);
1094         return Some(expr1_0);
1095     }
1096     return None;
1097 }
1098 
1099 // Generated as internal constructor for term safepoint.
1100 pub fn constructor_safepoint<C: Context>(
1101     ctx: &mut C,
1102     arg0: &SideEffectNoResult,
1103 ) -> Option<InstOutput> {
1104     let pattern0_0 = arg0;
1105     if let &SideEffectNoResult::Inst {
1106         inst: ref pattern1_0,
1107     } = pattern0_0
1108     {
1109         // Rule at src/prelude.isle line 416.
1110         let expr0_0 = C::emit_safepoint(ctx, pattern1_0);
1111         let expr1_0 = C::output_none(ctx);
1112         return Some(expr1_0);
1113     }
1114     return None;
1115 }
1116 
1117 // Generated as internal constructor for term produces_flags_get_reg.
1118 pub fn constructor_produces_flags_get_reg<C: Context>(
1119     ctx: &mut C,
1120     arg0: &ProducesFlags,
1121 ) -> Option<Reg> {
1122     let pattern0_0 = arg0;
1123     if let &ProducesFlags::ProducesFlagsReturnsReg {
1124         inst: ref pattern1_0,
1125         result: pattern1_1,
1126     } = pattern0_0
1127     {
1128         // Rule at src/prelude.isle line 454.
1129         return Some(pattern1_1);
1130     }
1131     return None;
1132 }
1133 
1134 // Generated as internal constructor for term produces_flags_ignore.
1135 pub fn constructor_produces_flags_ignore<C: Context>(
1136     ctx: &mut C,
1137     arg0: &ProducesFlags,
1138 ) -> Option<ProducesFlags> {
1139     let pattern0_0 = arg0;
1140     match pattern0_0 {
1141         &ProducesFlags::ProducesFlagsReturnsReg {
1142             inst: ref pattern1_0,
1143             result: pattern1_1,
1144         } => {
1145             // Rule at src/prelude.isle line 459.
1146             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1147                 inst: pattern1_0.clone(),
1148             };
1149             return Some(expr0_0);
1150         }
1151         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1152             inst: ref pattern1_0,
1153             result: pattern1_1,
1154         } => {
1155             // Rule at src/prelude.isle line 461.
1156             let expr0_0 = ProducesFlags::ProducesFlagsSideEffect {
1157                 inst: pattern1_0.clone(),
1158             };
1159             return Some(expr0_0);
1160         }
1161         _ => {}
1162     }
1163     return None;
1164 }
1165 
1166 // Generated as internal constructor for term consumes_flags_concat.
1167 pub fn constructor_consumes_flags_concat<C: Context>(
1168     ctx: &mut C,
1169     arg0: &ConsumesFlags,
1170     arg1: &ConsumesFlags,
1171 ) -> Option<ConsumesFlags> {
1172     let pattern0_0 = arg0;
1173     if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1174         inst: ref pattern1_0,
1175         result: pattern1_1,
1176     } = pattern0_0
1177     {
1178         let pattern2_0 = arg1;
1179         if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1180             inst: ref pattern3_0,
1181             result: pattern3_1,
1182         } = pattern2_0
1183         {
1184             // Rule at src/prelude.isle line 468.
1185             let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1186             let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1187                 inst1: pattern1_0.clone(),
1188                 inst2: pattern3_0.clone(),
1189                 result: expr0_0,
1190             };
1191             return Some(expr1_0);
1192         }
1193     }
1194     return None;
1195 }
1196 
1197 // Generated as internal constructor for term with_flags.
1198 pub fn constructor_with_flags<C: Context>(
1199     ctx: &mut C,
1200     arg0: &ProducesFlags,
1201     arg1: &ConsumesFlags,
1202 ) -> Option<ValueRegs> {
1203     let pattern0_0 = arg0;
1204     match pattern0_0 {
1205         &ProducesFlags::ProducesFlagsSideEffect {
1206             inst: ref pattern1_0,
1207         } => {
1208             let pattern2_0 = arg1;
1209             match pattern2_0 {
1210                 &ConsumesFlags::ConsumesFlagsReturnsReg {
1211                     inst: ref pattern3_0,
1212                     result: pattern3_1,
1213                 } => {
1214                     // Rule at src/prelude.isle line 493.
1215                     let expr0_0 = C::emit(ctx, pattern1_0);
1216                     let expr1_0 = C::emit(ctx, pattern3_0);
1217                     let expr2_0 = C::value_reg(ctx, pattern3_1);
1218                     return Some(expr2_0);
1219                 }
1220                 &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1221                     inst1: ref pattern3_0,
1222                     inst2: ref pattern3_1,
1223                     result: pattern3_2,
1224                 } => {
1225                     // Rule at src/prelude.isle line 499.
1226                     let expr0_0 = C::emit(ctx, pattern1_0);
1227                     let expr1_0 = C::emit(ctx, pattern3_0);
1228                     let expr2_0 = C::emit(ctx, pattern3_1);
1229                     return Some(pattern3_2);
1230                 }
1231                 &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs {
1232                     inst1: ref pattern3_0,
1233                     inst2: ref pattern3_1,
1234                     inst3: ref pattern3_2,
1235                     inst4: ref pattern3_3,
1236                     result: pattern3_4,
1237                 } => {
1238                     // Rule at src/prelude.isle line 511.
1239                     let expr0_0 = C::emit(ctx, pattern1_0);
1240                     let expr1_0 = C::emit(ctx, pattern3_0);
1241                     let expr2_0 = C::emit(ctx, pattern3_1);
1242                     let expr3_0 = C::emit(ctx, pattern3_2);
1243                     let expr4_0 = C::emit(ctx, pattern3_3);
1244                     return Some(pattern3_4);
1245                 }
1246                 _ => {}
1247             }
1248         }
1249         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1250             inst: ref pattern1_0,
1251             result: pattern1_1,
1252         } => {
1253             let pattern2_0 = arg1;
1254             if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1255                 inst: ref pattern3_0,
1256                 result: pattern3_1,
1257             } = pattern2_0
1258             {
1259                 // Rule at src/prelude.isle line 487.
1260                 let expr0_0 = C::emit(ctx, pattern1_0);
1261                 let expr1_0 = C::emit(ctx, pattern3_0);
1262                 let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1263                 return Some(expr2_0);
1264             }
1265         }
1266         _ => {}
1267     }
1268     return None;
1269 }
1270 
1271 // Generated as internal constructor for term with_flags_reg.
1272 pub fn constructor_with_flags_reg<C: Context>(
1273     ctx: &mut C,
1274     arg0: &ProducesFlags,
1275     arg1: &ConsumesFlags,
1276 ) -> Option<Reg> {
1277     let pattern0_0 = arg0;
1278     let pattern1_0 = arg1;
1279     // Rule at src/prelude.isle line 528.
1280     let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?;
1281     let expr1_0: usize = 0;
1282     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1283     return Some(expr2_0);
1284 }
1285 
1286 // Generated as internal constructor for term operand_size.
1287 pub fn constructor_operand_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
1288     let pattern0_0 = arg0;
1289     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
1290         // Rule at src/isa/aarch64/inst.isle line 895.
1291         let expr0_0 = OperandSize::Size32;
1292         return Some(expr0_0);
1293     }
1294     if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
1295         // Rule at src/isa/aarch64/inst.isle line 896.
1296         let expr0_0 = OperandSize::Size64;
1297         return Some(expr0_0);
1298     }
1299     return None;
1300 }
1301 
1302 // Generated as internal constructor for term vector_size.
1303 pub fn constructor_vector_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<VectorSize> {
1304     let pattern0_0 = arg0;
1305     if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
1306         if pattern1_0 == 8 {
1307             if pattern1_1 == 16 {
1308                 // Rule at src/isa/aarch64/inst.isle line 938.
1309                 let expr0_0 = VectorSize::Size8x16;
1310                 return Some(expr0_0);
1311             }
1312         }
1313         if pattern1_0 == 16 {
1314             if pattern1_1 == 8 {
1315                 // Rule at src/isa/aarch64/inst.isle line 939.
1316                 let expr0_0 = VectorSize::Size16x8;
1317                 return Some(expr0_0);
1318             }
1319         }
1320         if pattern1_0 == 32 {
1321             if pattern1_1 == 4 {
1322                 // Rule at src/isa/aarch64/inst.isle line 940.
1323                 let expr0_0 = VectorSize::Size32x4;
1324                 return Some(expr0_0);
1325             }
1326         }
1327         if pattern1_0 == 64 {
1328             if pattern1_1 == 2 {
1329                 // Rule at src/isa/aarch64/inst.isle line 941.
1330                 let expr0_0 = VectorSize::Size64x2;
1331                 return Some(expr0_0);
1332             }
1333         }
1334     }
1335     return None;
1336 }
1337 
1338 // Generated as internal constructor for term movz.
1339 pub fn constructor_movz<C: Context>(
1340     ctx: &mut C,
1341     arg0: MoveWideConst,
1342     arg1: &OperandSize,
1343 ) -> Option<Reg> {
1344     let pattern0_0 = arg0;
1345     let pattern1_0 = arg1;
1346     // Rule at src/isa/aarch64/inst.isle line 1381.
1347     let expr0_0: Type = I64;
1348     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1349     let expr2_0 = MInst::MovZ {
1350         rd: expr1_0,
1351         imm: pattern0_0,
1352         size: pattern1_0.clone(),
1353     };
1354     let expr3_0 = C::emit(ctx, &expr2_0);
1355     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1356     return Some(expr4_0);
1357 }
1358 
1359 // Generated as internal constructor for term movn.
1360 pub fn constructor_movn<C: Context>(
1361     ctx: &mut C,
1362     arg0: MoveWideConst,
1363     arg1: &OperandSize,
1364 ) -> Option<Reg> {
1365     let pattern0_0 = arg0;
1366     let pattern1_0 = arg1;
1367     // Rule at src/isa/aarch64/inst.isle line 1388.
1368     let expr0_0: Type = I64;
1369     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1370     let expr2_0 = MInst::MovN {
1371         rd: expr1_0,
1372         imm: pattern0_0,
1373         size: pattern1_0.clone(),
1374     };
1375     let expr3_0 = C::emit(ctx, &expr2_0);
1376     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1377     return Some(expr4_0);
1378 }
1379 
1380 // Generated as internal constructor for term alu_rr_imm_logic.
1381 pub fn constructor_alu_rr_imm_logic<C: Context>(
1382     ctx: &mut C,
1383     arg0: &ALUOp,
1384     arg1: Type,
1385     arg2: Reg,
1386     arg3: ImmLogic,
1387 ) -> Option<Reg> {
1388     let pattern0_0 = arg0;
1389     let pattern1_0 = arg1;
1390     let pattern2_0 = arg2;
1391     let pattern3_0 = arg3;
1392     // Rule at src/isa/aarch64/inst.isle line 1395.
1393     let expr0_0: Type = I64;
1394     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1395     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1396     let expr3_0 = MInst::AluRRImmLogic {
1397         alu_op: pattern0_0.clone(),
1398         size: expr2_0,
1399         rd: expr1_0,
1400         rn: pattern2_0,
1401         imml: pattern3_0,
1402     };
1403     let expr4_0 = C::emit(ctx, &expr3_0);
1404     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1405     return Some(expr5_0);
1406 }
1407 
1408 // Generated as internal constructor for term alu_rr_imm_shift.
1409 pub fn constructor_alu_rr_imm_shift<C: Context>(
1410     ctx: &mut C,
1411     arg0: &ALUOp,
1412     arg1: Type,
1413     arg2: Reg,
1414     arg3: ImmShift,
1415 ) -> Option<Reg> {
1416     let pattern0_0 = arg0;
1417     let pattern1_0 = arg1;
1418     let pattern2_0 = arg2;
1419     let pattern3_0 = arg3;
1420     // Rule at src/isa/aarch64/inst.isle line 1402.
1421     let expr0_0: Type = I64;
1422     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1423     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1424     let expr3_0 = MInst::AluRRImmShift {
1425         alu_op: pattern0_0.clone(),
1426         size: expr2_0,
1427         rd: expr1_0,
1428         rn: pattern2_0,
1429         immshift: pattern3_0,
1430     };
1431     let expr4_0 = C::emit(ctx, &expr3_0);
1432     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1433     return Some(expr5_0);
1434 }
1435 
1436 // Generated as internal constructor for term alu_rrr.
1437 pub fn constructor_alu_rrr<C: Context>(
1438     ctx: &mut C,
1439     arg0: &ALUOp,
1440     arg1: Type,
1441     arg2: Reg,
1442     arg3: Reg,
1443 ) -> Option<Reg> {
1444     let pattern0_0 = arg0;
1445     let pattern1_0 = arg1;
1446     let pattern2_0 = arg2;
1447     let pattern3_0 = arg3;
1448     // Rule at src/isa/aarch64/inst.isle line 1409.
1449     let expr0_0: Type = I64;
1450     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1451     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1452     let expr3_0 = MInst::AluRRR {
1453         alu_op: pattern0_0.clone(),
1454         size: expr2_0,
1455         rd: expr1_0,
1456         rn: pattern2_0,
1457         rm: pattern3_0,
1458     };
1459     let expr4_0 = C::emit(ctx, &expr3_0);
1460     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1461     return Some(expr5_0);
1462 }
1463 
1464 // Generated as internal constructor for term vec_rrr.
1465 pub fn constructor_vec_rrr<C: Context>(
1466     ctx: &mut C,
1467     arg0: &VecALUOp,
1468     arg1: Reg,
1469     arg2: Reg,
1470     arg3: &VectorSize,
1471 ) -> Option<Reg> {
1472     let pattern0_0 = arg0;
1473     let pattern1_0 = arg1;
1474     let pattern2_0 = arg2;
1475     let pattern3_0 = arg3;
1476     // Rule at src/isa/aarch64/inst.isle line 1416.
1477     let expr0_0: Type = I8X16;
1478     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1479     let expr2_0 = MInst::VecRRR {
1480         alu_op: pattern0_0.clone(),
1481         rd: expr1_0,
1482         rn: pattern1_0,
1483         rm: pattern2_0,
1484         size: pattern3_0.clone(),
1485     };
1486     let expr3_0 = C::emit(ctx, &expr2_0);
1487     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1488     return Some(expr4_0);
1489 }
1490 
1491 // Generated as internal constructor for term vec_lanes.
1492 pub fn constructor_vec_lanes<C: Context>(
1493     ctx: &mut C,
1494     arg0: &VecLanesOp,
1495     arg1: Reg,
1496     arg2: &VectorSize,
1497 ) -> Option<Reg> {
1498     let pattern0_0 = arg0;
1499     let pattern1_0 = arg1;
1500     let pattern2_0 = arg2;
1501     // Rule at src/isa/aarch64/inst.isle line 1423.
1502     let expr0_0: Type = I8X16;
1503     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1504     let expr2_0 = MInst::VecLanes {
1505         op: pattern0_0.clone(),
1506         rd: expr1_0,
1507         rn: pattern1_0,
1508         size: pattern2_0.clone(),
1509     };
1510     let expr3_0 = C::emit(ctx, &expr2_0);
1511     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1512     return Some(expr4_0);
1513 }
1514 
1515 // Generated as internal constructor for term vec_dup.
1516 pub fn constructor_vec_dup<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
1517     let pattern0_0 = arg0;
1518     let pattern1_0 = arg1;
1519     // Rule at src/isa/aarch64/inst.isle line 1430.
1520     let expr0_0: Type = I8X16;
1521     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1522     let expr2_0 = MInst::VecDup {
1523         rd: expr1_0,
1524         rn: pattern0_0,
1525         size: pattern1_0.clone(),
1526     };
1527     let expr3_0 = C::emit(ctx, &expr2_0);
1528     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1529     return Some(expr4_0);
1530 }
1531 
1532 // Generated as internal constructor for term alu_rr_imm12.
1533 pub fn constructor_alu_rr_imm12<C: Context>(
1534     ctx: &mut C,
1535     arg0: &ALUOp,
1536     arg1: Type,
1537     arg2: Reg,
1538     arg3: Imm12,
1539 ) -> Option<Reg> {
1540     let pattern0_0 = arg0;
1541     let pattern1_0 = arg1;
1542     let pattern2_0 = arg2;
1543     let pattern3_0 = arg3;
1544     // Rule at src/isa/aarch64/inst.isle line 1437.
1545     let expr0_0: Type = I64;
1546     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1547     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1548     let expr3_0 = MInst::AluRRImm12 {
1549         alu_op: pattern0_0.clone(),
1550         size: expr2_0,
1551         rd: expr1_0,
1552         rn: pattern2_0,
1553         imm12: pattern3_0,
1554     };
1555     let expr4_0 = C::emit(ctx, &expr3_0);
1556     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1557     return Some(expr5_0);
1558 }
1559 
1560 // Generated as internal constructor for term alu_rrr_shift.
1561 pub fn constructor_alu_rrr_shift<C: Context>(
1562     ctx: &mut C,
1563     arg0: &ALUOp,
1564     arg1: Type,
1565     arg2: Reg,
1566     arg3: Reg,
1567     arg4: ShiftOpAndAmt,
1568 ) -> Option<Reg> {
1569     let pattern0_0 = arg0;
1570     let pattern1_0 = arg1;
1571     let pattern2_0 = arg2;
1572     let pattern3_0 = arg3;
1573     let pattern4_0 = arg4;
1574     // Rule at src/isa/aarch64/inst.isle line 1444.
1575     let expr0_0: Type = I64;
1576     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1577     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1578     let expr3_0 = MInst::AluRRRShift {
1579         alu_op: pattern0_0.clone(),
1580         size: expr2_0,
1581         rd: expr1_0,
1582         rn: pattern2_0,
1583         rm: pattern3_0,
1584         shiftop: pattern4_0,
1585     };
1586     let expr4_0 = C::emit(ctx, &expr3_0);
1587     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1588     return Some(expr5_0);
1589 }
1590 
1591 // Generated as internal constructor for term alu_rrr_extend.
1592 pub fn constructor_alu_rrr_extend<C: Context>(
1593     ctx: &mut C,
1594     arg0: &ALUOp,
1595     arg1: Type,
1596     arg2: Reg,
1597     arg3: Reg,
1598     arg4: &ExtendOp,
1599 ) -> Option<Reg> {
1600     let pattern0_0 = arg0;
1601     let pattern1_0 = arg1;
1602     let pattern2_0 = arg2;
1603     let pattern3_0 = arg3;
1604     let pattern4_0 = arg4;
1605     // Rule at src/isa/aarch64/inst.isle line 1451.
1606     let expr0_0: Type = I64;
1607     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1608     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1609     let expr3_0 = MInst::AluRRRExtend {
1610         alu_op: pattern0_0.clone(),
1611         size: expr2_0,
1612         rd: expr1_0,
1613         rn: pattern2_0,
1614         rm: pattern3_0,
1615         extendop: pattern4_0.clone(),
1616     };
1617     let expr4_0 = C::emit(ctx, &expr3_0);
1618     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1619     return Some(expr5_0);
1620 }
1621 
1622 // Generated as internal constructor for term alu_rr_extend_reg.
1623 pub fn constructor_alu_rr_extend_reg<C: Context>(
1624     ctx: &mut C,
1625     arg0: &ALUOp,
1626     arg1: Type,
1627     arg2: Reg,
1628     arg3: &ExtendedValue,
1629 ) -> Option<Reg> {
1630     let pattern0_0 = arg0;
1631     let pattern1_0 = arg1;
1632     let pattern2_0 = arg2;
1633     let pattern3_0 = arg3;
1634     // Rule at src/isa/aarch64/inst.isle line 1459.
1635     let expr0_0 = C::put_extended_in_reg(ctx, pattern3_0);
1636     let expr1_0 = C::get_extended_op(ctx, pattern3_0);
1637     let expr2_0 =
1638         constructor_alu_rrr_extend(ctx, pattern0_0, pattern1_0, pattern2_0, expr0_0, &expr1_0)?;
1639     return Some(expr2_0);
1640 }
1641 
1642 // Generated as internal constructor for term alu_rrrr.
1643 pub fn constructor_alu_rrrr<C: Context>(
1644     ctx: &mut C,
1645     arg0: &ALUOp3,
1646     arg1: Reg,
1647     arg2: Reg,
1648     arg3: Reg,
1649 ) -> Option<Reg> {
1650     let pattern0_0 = arg0;
1651     let pattern1_0 = arg1;
1652     let pattern2_0 = arg2;
1653     let pattern3_0 = arg3;
1654     // Rule at src/isa/aarch64/inst.isle line 1466.
1655     let expr0_0: Type = I64;
1656     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1657     let expr2_0 = MInst::AluRRRR {
1658         alu_op: pattern0_0.clone(),
1659         rd: expr1_0,
1660         rn: pattern1_0,
1661         rm: pattern2_0,
1662         ra: pattern3_0,
1663     };
1664     let expr3_0 = C::emit(ctx, &expr2_0);
1665     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1666     return Some(expr4_0);
1667 }
1668 
1669 // Generated as internal constructor for term bit_rr.
1670 pub fn constructor_bit_rr<C: Context>(
1671     ctx: &mut C,
1672     arg0: &BitOp,
1673     arg1: Type,
1674     arg2: Reg,
1675 ) -> Option<Reg> {
1676     let pattern0_0 = arg0;
1677     let pattern1_0 = arg1;
1678     let pattern2_0 = arg2;
1679     // Rule at src/isa/aarch64/inst.isle line 1473.
1680     let expr0_0: Type = I64;
1681     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1682     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1683     let expr3_0 = MInst::BitRR {
1684         op: pattern0_0.clone(),
1685         size: expr2_0,
1686         rd: expr1_0,
1687         rn: pattern2_0,
1688     };
1689     let expr4_0 = C::emit(ctx, &expr3_0);
1690     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1691     return Some(expr5_0);
1692 }
1693 
1694 // Generated as internal constructor for term add_with_flags_paired.
1695 pub fn constructor_add_with_flags_paired<C: Context>(
1696     ctx: &mut C,
1697     arg0: Type,
1698     arg1: Reg,
1699     arg2: Reg,
1700 ) -> Option<ProducesFlags> {
1701     let pattern0_0 = arg0;
1702     let pattern1_0 = arg1;
1703     let pattern2_0 = arg2;
1704     // Rule at src/isa/aarch64/inst.isle line 1480.
1705     let expr0_0: Type = I64;
1706     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1707     let expr2_0 = ALUOp::AddS;
1708     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1709     let expr4_0 = MInst::AluRRR {
1710         alu_op: expr2_0,
1711         size: expr3_0,
1712         rd: expr1_0,
1713         rn: pattern1_0,
1714         rm: pattern2_0,
1715     };
1716     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1717     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1718         inst: expr4_0,
1719         result: expr5_0,
1720     };
1721     return Some(expr6_0);
1722 }
1723 
1724 // Generated as internal constructor for term adc_paired.
1725 pub fn constructor_adc_paired<C: Context>(
1726     ctx: &mut C,
1727     arg0: Type,
1728     arg1: Reg,
1729     arg2: Reg,
1730 ) -> Option<ConsumesFlags> {
1731     let pattern0_0 = arg0;
1732     let pattern1_0 = arg1;
1733     let pattern2_0 = arg2;
1734     // Rule at src/isa/aarch64/inst.isle line 1488.
1735     let expr0_0: Type = I64;
1736     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1737     let expr2_0 = ALUOp::Adc;
1738     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1739     let expr4_0 = MInst::AluRRR {
1740         alu_op: expr2_0,
1741         size: expr3_0,
1742         rd: expr1_0,
1743         rn: pattern1_0,
1744         rm: pattern2_0,
1745     };
1746     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1747     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1748         inst: expr4_0,
1749         result: expr5_0,
1750     };
1751     return Some(expr6_0);
1752 }
1753 
1754 // Generated as internal constructor for term sub_with_flags_paired.
1755 pub fn constructor_sub_with_flags_paired<C: Context>(
1756     ctx: &mut C,
1757     arg0: Type,
1758     arg1: Reg,
1759     arg2: Reg,
1760 ) -> Option<ProducesFlags> {
1761     let pattern0_0 = arg0;
1762     let pattern1_0 = arg1;
1763     let pattern2_0 = arg2;
1764     // Rule at src/isa/aarch64/inst.isle line 1496.
1765     let expr0_0: Type = I64;
1766     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1767     let expr2_0 = ALUOp::SubS;
1768     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1769     let expr4_0 = MInst::AluRRR {
1770         alu_op: expr2_0,
1771         size: expr3_0,
1772         rd: expr1_0,
1773         rn: pattern1_0,
1774         rm: pattern2_0,
1775     };
1776     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1777     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1778         inst: expr4_0,
1779         result: expr5_0,
1780     };
1781     return Some(expr6_0);
1782 }
1783 
1784 // Generated as internal constructor for term cmp64_imm.
1785 pub fn constructor_cmp64_imm<C: Context>(
1786     ctx: &mut C,
1787     arg0: Reg,
1788     arg1: Imm12,
1789 ) -> Option<ProducesFlags> {
1790     let pattern0_0 = arg0;
1791     let pattern1_0 = arg1;
1792     // Rule at src/isa/aarch64/inst.isle line 1503.
1793     let expr0_0 = ALUOp::SubS;
1794     let expr1_0 = OperandSize::Size64;
1795     let expr2_0 = C::writable_zero_reg(ctx);
1796     let expr3_0 = MInst::AluRRImm12 {
1797         alu_op: expr0_0,
1798         size: expr1_0,
1799         rd: expr2_0,
1800         rn: pattern0_0,
1801         imm12: pattern1_0,
1802     };
1803     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
1804     return Some(expr4_0);
1805 }
1806 
1807 // Generated as internal constructor for term sbc_paired.
1808 pub fn constructor_sbc_paired<C: Context>(
1809     ctx: &mut C,
1810     arg0: Type,
1811     arg1: Reg,
1812     arg2: Reg,
1813 ) -> Option<ConsumesFlags> {
1814     let pattern0_0 = arg0;
1815     let pattern1_0 = arg1;
1816     let pattern2_0 = arg2;
1817     // Rule at src/isa/aarch64/inst.isle line 1510.
1818     let expr0_0: Type = I64;
1819     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1820     let expr2_0 = ALUOp::Sbc;
1821     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1822     let expr4_0 = MInst::AluRRR {
1823         alu_op: expr2_0,
1824         size: expr3_0,
1825         rd: expr1_0,
1826         rn: pattern1_0,
1827         rm: pattern2_0,
1828     };
1829     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1830     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1831         inst: expr4_0,
1832         result: expr5_0,
1833     };
1834     return Some(expr6_0);
1835 }
1836 
1837 // Generated as internal constructor for term vec_misc.
1838 pub fn constructor_vec_misc<C: Context>(
1839     ctx: &mut C,
1840     arg0: &VecMisc2,
1841     arg1: Reg,
1842     arg2: &VectorSize,
1843 ) -> Option<Reg> {
1844     let pattern0_0 = arg0;
1845     let pattern1_0 = arg1;
1846     let pattern2_0 = arg2;
1847     // Rule at src/isa/aarch64/inst.isle line 1518.
1848     let expr0_0: Type = I8X16;
1849     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1850     let expr2_0 = MInst::VecMisc {
1851         op: pattern0_0.clone(),
1852         rd: expr1_0,
1853         rn: pattern1_0,
1854         size: pattern2_0.clone(),
1855     };
1856     let expr3_0 = C::emit(ctx, &expr2_0);
1857     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1858     return Some(expr4_0);
1859 }
1860 
1861 // Generated as internal constructor for term vec_rrr_long.
1862 pub fn constructor_vec_rrr_long<C: Context>(
1863     ctx: &mut C,
1864     arg0: &VecRRRLongOp,
1865     arg1: Reg,
1866     arg2: Reg,
1867     arg3: bool,
1868 ) -> Option<Reg> {
1869     let pattern0_0 = arg0;
1870     let pattern1_0 = arg1;
1871     let pattern2_0 = arg2;
1872     let pattern3_0 = arg3;
1873     // Rule at src/isa/aarch64/inst.isle line 1525.
1874     let expr0_0: Type = I8X16;
1875     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1876     let expr2_0 = MInst::VecRRRLong {
1877         alu_op: pattern0_0.clone(),
1878         rd: expr1_0,
1879         rn: pattern1_0,
1880         rm: pattern2_0,
1881         high_half: pattern3_0,
1882     };
1883     let expr3_0 = C::emit(ctx, &expr2_0);
1884     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1885     return Some(expr4_0);
1886 }
1887 
1888 // Generated as internal constructor for term vec_rrrr_long.
1889 pub fn constructor_vec_rrrr_long<C: Context>(
1890     ctx: &mut C,
1891     arg0: &VecRRRLongOp,
1892     arg1: Reg,
1893     arg2: Reg,
1894     arg3: Reg,
1895     arg4: bool,
1896 ) -> Option<Reg> {
1897     let pattern0_0 = arg0;
1898     let pattern1_0 = arg1;
1899     let pattern2_0 = arg2;
1900     let pattern3_0 = arg3;
1901     let pattern4_0 = arg4;
1902     // Rule at src/isa/aarch64/inst.isle line 1535.
1903     let expr0_0: Type = I8X16;
1904     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1905     let expr2_0 = MInst::FpuMove128 {
1906         rd: expr1_0,
1907         rn: pattern1_0,
1908     };
1909     let expr3_0 = C::emit(ctx, &expr2_0);
1910     let expr4_0 = MInst::VecRRRLong {
1911         alu_op: pattern0_0.clone(),
1912         rd: expr1_0,
1913         rn: pattern2_0,
1914         rm: pattern3_0,
1915         high_half: pattern4_0,
1916     };
1917     let expr5_0 = C::emit(ctx, &expr4_0);
1918     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1919     return Some(expr6_0);
1920 }
1921 
1922 // Generated as internal constructor for term vec_rr_narrow.
1923 pub fn constructor_vec_rr_narrow<C: Context>(
1924     ctx: &mut C,
1925     arg0: &VecRRNarrowOp,
1926     arg1: Reg,
1927     arg2: bool,
1928 ) -> Option<Reg> {
1929     let pattern0_0 = arg0;
1930     let pattern1_0 = arg1;
1931     let pattern2_0 = arg2;
1932     // Rule at src/isa/aarch64/inst.isle line 1543.
1933     let expr0_0: Type = I8X16;
1934     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1935     let expr2_0 = MInst::VecRRNarrow {
1936         op: pattern0_0.clone(),
1937         rd: expr1_0,
1938         rn: pattern1_0,
1939         high_half: pattern2_0,
1940     };
1941     let expr3_0 = C::emit(ctx, &expr2_0);
1942     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1943     return Some(expr4_0);
1944 }
1945 
1946 // Generated as internal constructor for term vec_rr_long.
1947 pub fn constructor_vec_rr_long<C: Context>(
1948     ctx: &mut C,
1949     arg0: &VecRRLongOp,
1950     arg1: Reg,
1951     arg2: bool,
1952 ) -> Option<Reg> {
1953     let pattern0_0 = arg0;
1954     let pattern1_0 = arg1;
1955     let pattern2_0 = arg2;
1956     // Rule at src/isa/aarch64/inst.isle line 1550.
1957     let expr0_0: Type = I8X16;
1958     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1959     let expr2_0 = MInst::VecRRLong {
1960         op: pattern0_0.clone(),
1961         rd: expr1_0,
1962         rn: pattern1_0,
1963         high_half: pattern2_0,
1964     };
1965     let expr3_0 = C::emit(ctx, &expr2_0);
1966     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1967     return Some(expr4_0);
1968 }
1969 
1970 // Generated as internal constructor for term mov_to_fpu.
1971 pub fn constructor_mov_to_fpu<C: Context>(
1972     ctx: &mut C,
1973     arg0: Reg,
1974     arg1: &ScalarSize,
1975 ) -> Option<Reg> {
1976     let pattern0_0 = arg0;
1977     let pattern1_0 = arg1;
1978     // Rule at src/isa/aarch64/inst.isle line 1557.
1979     let expr0_0: Type = I8X16;
1980     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1981     let expr2_0 = MInst::MovToFpu {
1982         rd: expr1_0,
1983         rn: pattern0_0,
1984         size: pattern1_0.clone(),
1985     };
1986     let expr3_0 = C::emit(ctx, &expr2_0);
1987     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1988     return Some(expr4_0);
1989 }
1990 
1991 // Generated as internal constructor for term mov_to_vec.
1992 pub fn constructor_mov_to_vec<C: Context>(
1993     ctx: &mut C,
1994     arg0: Reg,
1995     arg1: Reg,
1996     arg2: u8,
1997     arg3: &VectorSize,
1998 ) -> Option<Reg> {
1999     let pattern0_0 = arg0;
2000     let pattern1_0 = arg1;
2001     let pattern2_0 = arg2;
2002     let pattern3_0 = arg3;
2003     // Rule at src/isa/aarch64/inst.isle line 1564.
2004     let expr0_0: Type = I8X16;
2005     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2006     let expr2_0 = MInst::FpuMove128 {
2007         rd: expr1_0,
2008         rn: pattern0_0,
2009     };
2010     let expr3_0 = C::emit(ctx, &expr2_0);
2011     let expr4_0 = MInst::MovToVec {
2012         rd: expr1_0,
2013         rn: pattern1_0,
2014         idx: pattern2_0,
2015         size: pattern3_0.clone(),
2016     };
2017     let expr5_0 = C::emit(ctx, &expr4_0);
2018     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
2019     return Some(expr6_0);
2020 }
2021 
2022 // Generated as internal constructor for term mov_from_vec.
2023 pub fn constructor_mov_from_vec<C: Context>(
2024     ctx: &mut C,
2025     arg0: Reg,
2026     arg1: u8,
2027     arg2: &VectorSize,
2028 ) -> Option<Reg> {
2029     let pattern0_0 = arg0;
2030     let pattern1_0 = arg1;
2031     let pattern2_0 = arg2;
2032     // Rule at src/isa/aarch64/inst.isle line 1572.
2033     let expr0_0: Type = I64;
2034     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2035     let expr2_0 = MInst::MovFromVec {
2036         rd: expr1_0,
2037         rn: pattern0_0,
2038         idx: pattern1_0,
2039         size: pattern2_0.clone(),
2040     };
2041     let expr3_0 = C::emit(ctx, &expr2_0);
2042     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2043     return Some(expr4_0);
2044 }
2045 
2046 // Generated as internal constructor for term mov_from_vec_signed.
2047 pub fn constructor_mov_from_vec_signed<C: Context>(
2048     ctx: &mut C,
2049     arg0: Reg,
2050     arg1: u8,
2051     arg2: &VectorSize,
2052     arg3: &OperandSize,
2053 ) -> Option<Reg> {
2054     let pattern0_0 = arg0;
2055     let pattern1_0 = arg1;
2056     let pattern2_0 = arg2;
2057     let pattern3_0 = arg3;
2058     // Rule at src/isa/aarch64/inst.isle line 1579.
2059     let expr0_0: Type = I64;
2060     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2061     let expr2_0 = MInst::MovFromVecSigned {
2062         rd: expr1_0,
2063         rn: pattern0_0,
2064         idx: pattern1_0,
2065         size: pattern2_0.clone(),
2066         scalar_size: pattern3_0.clone(),
2067     };
2068     let expr3_0 = C::emit(ctx, &expr2_0);
2069     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2070     return Some(expr4_0);
2071 }
2072 
2073 // Generated as internal constructor for term extend.
2074 pub fn constructor_extend<C: Context>(
2075     ctx: &mut C,
2076     arg0: Reg,
2077     arg1: bool,
2078     arg2: u8,
2079     arg3: u8,
2080 ) -> Option<Reg> {
2081     let pattern0_0 = arg0;
2082     let pattern1_0 = arg1;
2083     let pattern2_0 = arg2;
2084     let pattern3_0 = arg3;
2085     // Rule at src/isa/aarch64/inst.isle line 1586.
2086     let expr0_0: Type = I64;
2087     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2088     let expr2_0 = MInst::Extend {
2089         rd: expr1_0,
2090         rn: pattern0_0,
2091         signed: pattern1_0,
2092         from_bits: pattern2_0,
2093         to_bits: pattern3_0,
2094     };
2095     let expr3_0 = C::emit(ctx, &expr2_0);
2096     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2097     return Some(expr4_0);
2098 }
2099 
2100 // Generated as internal constructor for term load_acquire.
2101 pub fn constructor_load_acquire<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2102     let pattern0_0 = arg0;
2103     let pattern1_0 = arg1;
2104     // Rule at src/isa/aarch64/inst.isle line 1593.
2105     let expr0_0: Type = I64;
2106     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2107     let expr2_0 = MInst::LoadAcquire {
2108         access_ty: pattern0_0,
2109         rt: expr1_0,
2110         rn: pattern1_0,
2111     };
2112     let expr3_0 = C::emit(ctx, &expr2_0);
2113     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2114     return Some(expr4_0);
2115 }
2116 
2117 // Generated as internal constructor for term tst_imm.
2118 pub fn constructor_tst_imm<C: Context>(
2119     ctx: &mut C,
2120     arg0: Type,
2121     arg1: Reg,
2122     arg2: ImmLogic,
2123 ) -> Option<ProducesFlags> {
2124     let pattern0_0 = arg0;
2125     let pattern1_0 = arg1;
2126     let pattern2_0 = arg2;
2127     // Rule at src/isa/aarch64/inst.isle line 1603.
2128     let expr0_0 = ALUOp::AndS;
2129     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
2130     let expr2_0 = C::writable_zero_reg(ctx);
2131     let expr3_0 = MInst::AluRRImmLogic {
2132         alu_op: expr0_0,
2133         size: expr1_0,
2134         rd: expr2_0,
2135         rn: pattern1_0,
2136         imml: pattern2_0,
2137     };
2138     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
2139     return Some(expr4_0);
2140 }
2141 
2142 // Generated as internal constructor for term csel.
2143 pub fn constructor_csel<C: Context>(
2144     ctx: &mut C,
2145     arg0: &Cond,
2146     arg1: Reg,
2147     arg2: Reg,
2148 ) -> Option<ConsumesFlags> {
2149     let pattern0_0 = arg0;
2150     let pattern1_0 = arg1;
2151     let pattern2_0 = arg2;
2152     // Rule at src/isa/aarch64/inst.isle line 1617.
2153     let expr0_0: Type = I64;
2154     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2155     let expr2_0 = MInst::CSel {
2156         rd: expr1_0,
2157         cond: pattern0_0.clone(),
2158         rn: pattern1_0,
2159         rm: pattern2_0,
2160     };
2161     let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
2162     let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
2163         inst: expr2_0,
2164         result: expr3_0,
2165     };
2166     return Some(expr4_0);
2167 }
2168 
2169 // Generated as internal constructor for term add.
2170 pub fn constructor_add<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2171     let pattern0_0 = arg0;
2172     let pattern1_0 = arg1;
2173     let pattern2_0 = arg2;
2174     // Rule at src/isa/aarch64/inst.isle line 1626.
2175     let expr0_0 = ALUOp::Add;
2176     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2177     return Some(expr1_0);
2178 }
2179 
2180 // Generated as internal constructor for term add_imm.
2181 pub fn constructor_add_imm<C: Context>(
2182     ctx: &mut C,
2183     arg0: Type,
2184     arg1: Reg,
2185     arg2: Imm12,
2186 ) -> Option<Reg> {
2187     let pattern0_0 = arg0;
2188     let pattern1_0 = arg1;
2189     let pattern2_0 = arg2;
2190     // Rule at src/isa/aarch64/inst.isle line 1629.
2191     let expr0_0 = ALUOp::Add;
2192     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2193     return Some(expr1_0);
2194 }
2195 
2196 // Generated as internal constructor for term add_extend.
2197 pub fn constructor_add_extend<C: Context>(
2198     ctx: &mut C,
2199     arg0: Type,
2200     arg1: Reg,
2201     arg2: &ExtendedValue,
2202 ) -> Option<Reg> {
2203     let pattern0_0 = arg0;
2204     let pattern1_0 = arg1;
2205     let pattern2_0 = arg2;
2206     // Rule at src/isa/aarch64/inst.isle line 1632.
2207     let expr0_0 = ALUOp::Add;
2208     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2209     return Some(expr1_0);
2210 }
2211 
2212 // Generated as internal constructor for term add_shift.
2213 pub fn constructor_add_shift<C: Context>(
2214     ctx: &mut C,
2215     arg0: Type,
2216     arg1: Reg,
2217     arg2: Reg,
2218     arg3: ShiftOpAndAmt,
2219 ) -> Option<Reg> {
2220     let pattern0_0 = arg0;
2221     let pattern1_0 = arg1;
2222     let pattern2_0 = arg2;
2223     let pattern3_0 = arg3;
2224     // Rule at src/isa/aarch64/inst.isle line 1635.
2225     let expr0_0 = ALUOp::Add;
2226     let expr1_0 = constructor_alu_rrr_shift(
2227         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2228     )?;
2229     return Some(expr1_0);
2230 }
2231 
2232 // Generated as internal constructor for term add_vec.
2233 pub fn constructor_add_vec<C: Context>(
2234     ctx: &mut C,
2235     arg0: Reg,
2236     arg1: Reg,
2237     arg2: &VectorSize,
2238 ) -> Option<Reg> {
2239     let pattern0_0 = arg0;
2240     let pattern1_0 = arg1;
2241     let pattern2_0 = arg2;
2242     // Rule at src/isa/aarch64/inst.isle line 1638.
2243     let expr0_0 = VecALUOp::Add;
2244     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2245     return Some(expr1_0);
2246 }
2247 
2248 // Generated as internal constructor for term sub.
2249 pub fn constructor_sub<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2250     let pattern0_0 = arg0;
2251     let pattern1_0 = arg1;
2252     let pattern2_0 = arg2;
2253     // Rule at src/isa/aarch64/inst.isle line 1643.
2254     let expr0_0 = ALUOp::Sub;
2255     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2256     return Some(expr1_0);
2257 }
2258 
2259 // Generated as internal constructor for term sub_imm.
2260 pub fn constructor_sub_imm<C: Context>(
2261     ctx: &mut C,
2262     arg0: Type,
2263     arg1: Reg,
2264     arg2: Imm12,
2265 ) -> Option<Reg> {
2266     let pattern0_0 = arg0;
2267     let pattern1_0 = arg1;
2268     let pattern2_0 = arg2;
2269     // Rule at src/isa/aarch64/inst.isle line 1646.
2270     let expr0_0 = ALUOp::Sub;
2271     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2272     return Some(expr1_0);
2273 }
2274 
2275 // Generated as internal constructor for term sub_extend.
2276 pub fn constructor_sub_extend<C: Context>(
2277     ctx: &mut C,
2278     arg0: Type,
2279     arg1: Reg,
2280     arg2: &ExtendedValue,
2281 ) -> Option<Reg> {
2282     let pattern0_0 = arg0;
2283     let pattern1_0 = arg1;
2284     let pattern2_0 = arg2;
2285     // Rule at src/isa/aarch64/inst.isle line 1649.
2286     let expr0_0 = ALUOp::Sub;
2287     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2288     return Some(expr1_0);
2289 }
2290 
2291 // Generated as internal constructor for term sub_shift.
2292 pub fn constructor_sub_shift<C: Context>(
2293     ctx: &mut C,
2294     arg0: Type,
2295     arg1: Reg,
2296     arg2: Reg,
2297     arg3: ShiftOpAndAmt,
2298 ) -> Option<Reg> {
2299     let pattern0_0 = arg0;
2300     let pattern1_0 = arg1;
2301     let pattern2_0 = arg2;
2302     let pattern3_0 = arg3;
2303     // Rule at src/isa/aarch64/inst.isle line 1652.
2304     let expr0_0 = ALUOp::Sub;
2305     let expr1_0 = constructor_alu_rrr_shift(
2306         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2307     )?;
2308     return Some(expr1_0);
2309 }
2310 
2311 // Generated as internal constructor for term sub_vec.
2312 pub fn constructor_sub_vec<C: Context>(
2313     ctx: &mut C,
2314     arg0: Reg,
2315     arg1: Reg,
2316     arg2: &VectorSize,
2317 ) -> Option<Reg> {
2318     let pattern0_0 = arg0;
2319     let pattern1_0 = arg1;
2320     let pattern2_0 = arg2;
2321     // Rule at src/isa/aarch64/inst.isle line 1655.
2322     let expr0_0 = VecALUOp::Sub;
2323     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2324     return Some(expr1_0);
2325 }
2326 
2327 // Generated as internal constructor for term madd.
2328 pub fn constructor_madd<C: Context>(
2329     ctx: &mut C,
2330     arg0: Type,
2331     arg1: Reg,
2332     arg2: Reg,
2333     arg3: Reg,
2334 ) -> Option<Reg> {
2335     let pattern0_0 = arg0;
2336     if pattern0_0 == I64 {
2337         let pattern2_0 = arg1;
2338         let pattern3_0 = arg2;
2339         let pattern4_0 = arg3;
2340         // Rule at src/isa/aarch64/inst.isle line 1661.
2341         let expr0_0 = constructor_madd64(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2342         return Some(expr0_0);
2343     }
2344     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2345         let pattern2_0 = arg1;
2346         let pattern3_0 = arg2;
2347         let pattern4_0 = arg3;
2348         // Rule at src/isa/aarch64/inst.isle line 1660.
2349         let expr0_0 = constructor_madd32(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2350         return Some(expr0_0);
2351     }
2352     return None;
2353 }
2354 
2355 // Generated as internal constructor for term madd32.
2356 pub fn constructor_madd32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2357     let pattern0_0 = arg0;
2358     let pattern1_0 = arg1;
2359     let pattern2_0 = arg2;
2360     // Rule at src/isa/aarch64/inst.isle line 1664.
2361     let expr0_0 = ALUOp3::MAdd32;
2362     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2363     return Some(expr1_0);
2364 }
2365 
2366 // Generated as internal constructor for term madd64.
2367 pub fn constructor_madd64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2368     let pattern0_0 = arg0;
2369     let pattern1_0 = arg1;
2370     let pattern2_0 = arg2;
2371     // Rule at src/isa/aarch64/inst.isle line 1667.
2372     let expr0_0 = ALUOp3::MAdd64;
2373     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2374     return Some(expr1_0);
2375 }
2376 
2377 // Generated as internal constructor for term msub64.
2378 pub fn constructor_msub64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2379     let pattern0_0 = arg0;
2380     let pattern1_0 = arg1;
2381     let pattern2_0 = arg2;
2382     // Rule at src/isa/aarch64/inst.isle line 1672.
2383     let expr0_0 = ALUOp3::MSub64;
2384     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2385     return Some(expr1_0);
2386 }
2387 
2388 // Generated as internal constructor for term uqadd.
2389 pub fn constructor_uqadd<C: Context>(
2390     ctx: &mut C,
2391     arg0: Reg,
2392     arg1: Reg,
2393     arg2: &VectorSize,
2394 ) -> Option<Reg> {
2395     let pattern0_0 = arg0;
2396     let pattern1_0 = arg1;
2397     let pattern2_0 = arg2;
2398     // Rule at src/isa/aarch64/inst.isle line 1676.
2399     let expr0_0 = VecALUOp::Uqadd;
2400     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2401     return Some(expr1_0);
2402 }
2403 
2404 // Generated as internal constructor for term sqadd.
2405 pub fn constructor_sqadd<C: Context>(
2406     ctx: &mut C,
2407     arg0: Reg,
2408     arg1: Reg,
2409     arg2: &VectorSize,
2410 ) -> Option<Reg> {
2411     let pattern0_0 = arg0;
2412     let pattern1_0 = arg1;
2413     let pattern2_0 = arg2;
2414     // Rule at src/isa/aarch64/inst.isle line 1680.
2415     let expr0_0 = VecALUOp::Sqadd;
2416     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2417     return Some(expr1_0);
2418 }
2419 
2420 // Generated as internal constructor for term uqsub.
2421 pub fn constructor_uqsub<C: Context>(
2422     ctx: &mut C,
2423     arg0: Reg,
2424     arg1: Reg,
2425     arg2: &VectorSize,
2426 ) -> Option<Reg> {
2427     let pattern0_0 = arg0;
2428     let pattern1_0 = arg1;
2429     let pattern2_0 = arg2;
2430     // Rule at src/isa/aarch64/inst.isle line 1684.
2431     let expr0_0 = VecALUOp::Uqsub;
2432     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2433     return Some(expr1_0);
2434 }
2435 
2436 // Generated as internal constructor for term sqsub.
2437 pub fn constructor_sqsub<C: Context>(
2438     ctx: &mut C,
2439     arg0: Reg,
2440     arg1: Reg,
2441     arg2: &VectorSize,
2442 ) -> Option<Reg> {
2443     let pattern0_0 = arg0;
2444     let pattern1_0 = arg1;
2445     let pattern2_0 = arg2;
2446     // Rule at src/isa/aarch64/inst.isle line 1688.
2447     let expr0_0 = VecALUOp::Sqsub;
2448     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2449     return Some(expr1_0);
2450 }
2451 
2452 // Generated as internal constructor for term umulh.
2453 pub fn constructor_umulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2454     let pattern0_0 = arg0;
2455     let pattern1_0 = arg1;
2456     let pattern2_0 = arg2;
2457     // Rule at src/isa/aarch64/inst.isle line 1692.
2458     let expr0_0 = ALUOp::UMulH;
2459     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2460     return Some(expr1_0);
2461 }
2462 
2463 // Generated as internal constructor for term smulh.
2464 pub fn constructor_smulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2465     let pattern0_0 = arg0;
2466     let pattern1_0 = arg1;
2467     let pattern2_0 = arg2;
2468     // Rule at src/isa/aarch64/inst.isle line 1696.
2469     let expr0_0 = ALUOp::SMulH;
2470     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2471     return Some(expr1_0);
2472 }
2473 
2474 // Generated as internal constructor for term mul.
2475 pub fn constructor_mul<C: Context>(
2476     ctx: &mut C,
2477     arg0: Reg,
2478     arg1: Reg,
2479     arg2: &VectorSize,
2480 ) -> Option<Reg> {
2481     let pattern0_0 = arg0;
2482     let pattern1_0 = arg1;
2483     let pattern2_0 = arg2;
2484     // Rule at src/isa/aarch64/inst.isle line 1700.
2485     let expr0_0 = VecALUOp::Mul;
2486     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2487     return Some(expr1_0);
2488 }
2489 
2490 // Generated as internal constructor for term neg.
2491 pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2492     let pattern0_0 = arg0;
2493     let pattern1_0 = arg1;
2494     // Rule at src/isa/aarch64/inst.isle line 1704.
2495     let expr0_0 = VecMisc2::Neg;
2496     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2497     return Some(expr1_0);
2498 }
2499 
2500 // Generated as internal constructor for term rev64.
2501 pub fn constructor_rev64<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2502     let pattern0_0 = arg0;
2503     let pattern1_0 = arg1;
2504     // Rule at src/isa/aarch64/inst.isle line 1708.
2505     let expr0_0 = VecMisc2::Rev64;
2506     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2507     return Some(expr1_0);
2508 }
2509 
2510 // Generated as internal constructor for term xtn64.
2511 pub fn constructor_xtn64<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2512     let pattern0_0 = arg0;
2513     let pattern1_0 = arg1;
2514     // Rule at src/isa/aarch64/inst.isle line 1712.
2515     let expr0_0 = VecRRNarrowOp::Xtn64;
2516     let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2517     return Some(expr1_0);
2518 }
2519 
2520 // Generated as internal constructor for term addp.
2521 pub fn constructor_addp<C: Context>(
2522     ctx: &mut C,
2523     arg0: Reg,
2524     arg1: Reg,
2525     arg2: &VectorSize,
2526 ) -> Option<Reg> {
2527     let pattern0_0 = arg0;
2528     let pattern1_0 = arg1;
2529     let pattern2_0 = arg2;
2530     // Rule at src/isa/aarch64/inst.isle line 1716.
2531     let expr0_0 = VecALUOp::Addp;
2532     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2533     return Some(expr1_0);
2534 }
2535 
2536 // Generated as internal constructor for term addv.
2537 pub fn constructor_addv<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2538     let pattern0_0 = arg0;
2539     let pattern1_0 = arg1;
2540     // Rule at src/isa/aarch64/inst.isle line 1720.
2541     let expr0_0 = VecLanesOp::Addv;
2542     let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2543     return Some(expr1_0);
2544 }
2545 
2546 // Generated as internal constructor for term shll32.
2547 pub fn constructor_shll32<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2548     let pattern0_0 = arg0;
2549     let pattern1_0 = arg1;
2550     // Rule at src/isa/aarch64/inst.isle line 1724.
2551     let expr0_0 = VecRRLongOp::Shll32;
2552     let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2553     return Some(expr1_0);
2554 }
2555 
2556 // Generated as internal constructor for term umlal32.
2557 pub fn constructor_umlal32<C: Context>(
2558     ctx: &mut C,
2559     arg0: Reg,
2560     arg1: Reg,
2561     arg2: Reg,
2562     arg3: bool,
2563 ) -> Option<Reg> {
2564     let pattern0_0 = arg0;
2565     let pattern1_0 = arg1;
2566     let pattern2_0 = arg2;
2567     let pattern3_0 = arg3;
2568     // Rule at src/isa/aarch64/inst.isle line 1728.
2569     let expr0_0 = VecRRRLongOp::Umlal32;
2570     let expr1_0 = constructor_vec_rrrr_long(
2571         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2572     )?;
2573     return Some(expr1_0);
2574 }
2575 
2576 // Generated as internal constructor for term smull8.
2577 pub fn constructor_smull8<C: Context>(
2578     ctx: &mut C,
2579     arg0: Reg,
2580     arg1: Reg,
2581     arg2: bool,
2582 ) -> Option<Reg> {
2583     let pattern0_0 = arg0;
2584     let pattern1_0 = arg1;
2585     let pattern2_0 = arg2;
2586     // Rule at src/isa/aarch64/inst.isle line 1732.
2587     let expr0_0 = VecRRRLongOp::Smull8;
2588     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2589     return Some(expr1_0);
2590 }
2591 
2592 // Generated as internal constructor for term umull8.
2593 pub fn constructor_umull8<C: Context>(
2594     ctx: &mut C,
2595     arg0: Reg,
2596     arg1: Reg,
2597     arg2: bool,
2598 ) -> Option<Reg> {
2599     let pattern0_0 = arg0;
2600     let pattern1_0 = arg1;
2601     let pattern2_0 = arg2;
2602     // Rule at src/isa/aarch64/inst.isle line 1736.
2603     let expr0_0 = VecRRRLongOp::Umull8;
2604     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2605     return Some(expr1_0);
2606 }
2607 
2608 // Generated as internal constructor for term smull16.
2609 pub fn constructor_smull16<C: Context>(
2610     ctx: &mut C,
2611     arg0: Reg,
2612     arg1: Reg,
2613     arg2: bool,
2614 ) -> Option<Reg> {
2615     let pattern0_0 = arg0;
2616     let pattern1_0 = arg1;
2617     let pattern2_0 = arg2;
2618     // Rule at src/isa/aarch64/inst.isle line 1740.
2619     let expr0_0 = VecRRRLongOp::Smull16;
2620     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2621     return Some(expr1_0);
2622 }
2623 
2624 // Generated as internal constructor for term umull16.
2625 pub fn constructor_umull16<C: Context>(
2626     ctx: &mut C,
2627     arg0: Reg,
2628     arg1: Reg,
2629     arg2: bool,
2630 ) -> Option<Reg> {
2631     let pattern0_0 = arg0;
2632     let pattern1_0 = arg1;
2633     let pattern2_0 = arg2;
2634     // Rule at src/isa/aarch64/inst.isle line 1744.
2635     let expr0_0 = VecRRRLongOp::Umull16;
2636     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2637     return Some(expr1_0);
2638 }
2639 
2640 // Generated as internal constructor for term smull32.
2641 pub fn constructor_smull32<C: Context>(
2642     ctx: &mut C,
2643     arg0: Reg,
2644     arg1: Reg,
2645     arg2: bool,
2646 ) -> Option<Reg> {
2647     let pattern0_0 = arg0;
2648     let pattern1_0 = arg1;
2649     let pattern2_0 = arg2;
2650     // Rule at src/isa/aarch64/inst.isle line 1748.
2651     let expr0_0 = VecRRRLongOp::Smull32;
2652     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2653     return Some(expr1_0);
2654 }
2655 
2656 // Generated as internal constructor for term umull32.
2657 pub fn constructor_umull32<C: Context>(
2658     ctx: &mut C,
2659     arg0: Reg,
2660     arg1: Reg,
2661     arg2: bool,
2662 ) -> Option<Reg> {
2663     let pattern0_0 = arg0;
2664     let pattern1_0 = arg1;
2665     let pattern2_0 = arg2;
2666     // Rule at src/isa/aarch64/inst.isle line 1752.
2667     let expr0_0 = VecRRRLongOp::Umull32;
2668     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2669     return Some(expr1_0);
2670 }
2671 
2672 // Generated as internal constructor for term asr.
2673 pub fn constructor_asr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2674     let pattern0_0 = arg0;
2675     let pattern1_0 = arg1;
2676     let pattern2_0 = arg2;
2677     // Rule at src/isa/aarch64/inst.isle line 1756.
2678     let expr0_0 = ALUOp::Asr;
2679     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2680     return Some(expr1_0);
2681 }
2682 
2683 // Generated as internal constructor for term asr_imm.
2684 pub fn constructor_asr_imm<C: Context>(
2685     ctx: &mut C,
2686     arg0: Type,
2687     arg1: Reg,
2688     arg2: ImmShift,
2689 ) -> Option<Reg> {
2690     let pattern0_0 = arg0;
2691     let pattern1_0 = arg1;
2692     let pattern2_0 = arg2;
2693     // Rule at src/isa/aarch64/inst.isle line 1759.
2694     let expr0_0 = ALUOp::Asr;
2695     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2696     return Some(expr1_0);
2697 }
2698 
2699 // Generated as internal constructor for term lsr.
2700 pub fn constructor_lsr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2701     let pattern0_0 = arg0;
2702     let pattern1_0 = arg1;
2703     let pattern2_0 = arg2;
2704     // Rule at src/isa/aarch64/inst.isle line 1763.
2705     let expr0_0 = ALUOp::Lsr;
2706     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2707     return Some(expr1_0);
2708 }
2709 
2710 // Generated as internal constructor for term lsr_imm.
2711 pub fn constructor_lsr_imm<C: Context>(
2712     ctx: &mut C,
2713     arg0: Type,
2714     arg1: Reg,
2715     arg2: ImmShift,
2716 ) -> Option<Reg> {
2717     let pattern0_0 = arg0;
2718     let pattern1_0 = arg1;
2719     let pattern2_0 = arg2;
2720     // Rule at src/isa/aarch64/inst.isle line 1766.
2721     let expr0_0 = ALUOp::Lsr;
2722     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2723     return Some(expr1_0);
2724 }
2725 
2726 // Generated as internal constructor for term lsl.
2727 pub fn constructor_lsl<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2728     let pattern0_0 = arg0;
2729     let pattern1_0 = arg1;
2730     let pattern2_0 = arg2;
2731     // Rule at src/isa/aarch64/inst.isle line 1770.
2732     let expr0_0 = ALUOp::Lsl;
2733     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2734     return Some(expr1_0);
2735 }
2736 
2737 // Generated as internal constructor for term lsl_imm.
2738 pub fn constructor_lsl_imm<C: Context>(
2739     ctx: &mut C,
2740     arg0: Type,
2741     arg1: Reg,
2742     arg2: ImmShift,
2743 ) -> Option<Reg> {
2744     let pattern0_0 = arg0;
2745     let pattern1_0 = arg1;
2746     let pattern2_0 = arg2;
2747     // Rule at src/isa/aarch64/inst.isle line 1773.
2748     let expr0_0 = ALUOp::Lsl;
2749     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2750     return Some(expr1_0);
2751 }
2752 
2753 // Generated as internal constructor for term a64_udiv.
2754 pub fn constructor_a64_udiv<C: Context>(
2755     ctx: &mut C,
2756     arg0: Type,
2757     arg1: Reg,
2758     arg2: Reg,
2759 ) -> Option<Reg> {
2760     let pattern0_0 = arg0;
2761     let pattern1_0 = arg1;
2762     let pattern2_0 = arg2;
2763     // Rule at src/isa/aarch64/inst.isle line 1777.
2764     let expr0_0 = ALUOp::UDiv;
2765     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2766     return Some(expr1_0);
2767 }
2768 
2769 // Generated as internal constructor for term a64_sdiv.
2770 pub fn constructor_a64_sdiv<C: Context>(
2771     ctx: &mut C,
2772     arg0: Type,
2773     arg1: Reg,
2774     arg2: Reg,
2775 ) -> Option<Reg> {
2776     let pattern0_0 = arg0;
2777     let pattern1_0 = arg1;
2778     let pattern2_0 = arg2;
2779     // Rule at src/isa/aarch64/inst.isle line 1781.
2780     let expr0_0 = ALUOp::SDiv;
2781     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2782     return Some(expr1_0);
2783 }
2784 
2785 // Generated as internal constructor for term not.
2786 pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2787     let pattern0_0 = arg0;
2788     let pattern1_0 = arg1;
2789     // Rule at src/isa/aarch64/inst.isle line 1785.
2790     let expr0_0 = VecMisc2::Not;
2791     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2792     return Some(expr1_0);
2793 }
2794 
2795 // Generated as internal constructor for term orr_not.
2796 pub fn constructor_orr_not<C: Context>(
2797     ctx: &mut C,
2798     arg0: Type,
2799     arg1: Reg,
2800     arg2: Reg,
2801 ) -> Option<Reg> {
2802     let pattern0_0 = arg0;
2803     let pattern1_0 = arg1;
2804     let pattern2_0 = arg2;
2805     // Rule at src/isa/aarch64/inst.isle line 1790.
2806     let expr0_0 = ALUOp::OrrNot;
2807     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2808     return Some(expr1_0);
2809 }
2810 
2811 // Generated as internal constructor for term orr_not_shift.
2812 pub fn constructor_orr_not_shift<C: Context>(
2813     ctx: &mut C,
2814     arg0: Type,
2815     arg1: Reg,
2816     arg2: Reg,
2817     arg3: ShiftOpAndAmt,
2818 ) -> Option<Reg> {
2819     let pattern0_0 = arg0;
2820     let pattern1_0 = arg1;
2821     let pattern2_0 = arg2;
2822     let pattern3_0 = arg3;
2823     // Rule at src/isa/aarch64/inst.isle line 1793.
2824     let expr0_0 = ALUOp::OrrNot;
2825     let expr1_0 = constructor_alu_rrr_shift(
2826         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2827     )?;
2828     return Some(expr1_0);
2829 }
2830 
2831 // Generated as internal constructor for term orr.
2832 pub fn constructor_orr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2833     let pattern0_0 = arg0;
2834     let pattern1_0 = arg1;
2835     let pattern2_0 = arg2;
2836     // Rule at src/isa/aarch64/inst.isle line 1798.
2837     let expr0_0 = ALUOp::Orr;
2838     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2839     return Some(expr1_0);
2840 }
2841 
2842 // Generated as internal constructor for term orr_imm.
2843 pub fn constructor_orr_imm<C: Context>(
2844     ctx: &mut C,
2845     arg0: Type,
2846     arg1: Reg,
2847     arg2: ImmLogic,
2848 ) -> Option<Reg> {
2849     let pattern0_0 = arg0;
2850     let pattern1_0 = arg1;
2851     let pattern2_0 = arg2;
2852     // Rule at src/isa/aarch64/inst.isle line 1801.
2853     let expr0_0 = ALUOp::Orr;
2854     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2855     return Some(expr1_0);
2856 }
2857 
2858 // Generated as internal constructor for term orr_vec.
2859 pub fn constructor_orr_vec<C: Context>(
2860     ctx: &mut C,
2861     arg0: Reg,
2862     arg1: Reg,
2863     arg2: &VectorSize,
2864 ) -> Option<Reg> {
2865     let pattern0_0 = arg0;
2866     let pattern1_0 = arg1;
2867     let pattern2_0 = arg2;
2868     // Rule at src/isa/aarch64/inst.isle line 1804.
2869     let expr0_0 = VecALUOp::Orr;
2870     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2871     return Some(expr1_0);
2872 }
2873 
2874 // Generated as internal constructor for term and_imm.
2875 pub fn constructor_and_imm<C: Context>(
2876     ctx: &mut C,
2877     arg0: Type,
2878     arg1: Reg,
2879     arg2: ImmLogic,
2880 ) -> Option<Reg> {
2881     let pattern0_0 = arg0;
2882     let pattern1_0 = arg1;
2883     let pattern2_0 = arg2;
2884     // Rule at src/isa/aarch64/inst.isle line 1809.
2885     let expr0_0 = ALUOp::And;
2886     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2887     return Some(expr1_0);
2888 }
2889 
2890 // Generated as internal constructor for term and_vec.
2891 pub fn constructor_and_vec<C: Context>(
2892     ctx: &mut C,
2893     arg0: Reg,
2894     arg1: Reg,
2895     arg2: &VectorSize,
2896 ) -> Option<Reg> {
2897     let pattern0_0 = arg0;
2898     let pattern1_0 = arg1;
2899     let pattern2_0 = arg2;
2900     // Rule at src/isa/aarch64/inst.isle line 1812.
2901     let expr0_0 = VecALUOp::And;
2902     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2903     return Some(expr1_0);
2904 }
2905 
2906 // Generated as internal constructor for term eor_vec.
2907 pub fn constructor_eor_vec<C: Context>(
2908     ctx: &mut C,
2909     arg0: Reg,
2910     arg1: Reg,
2911     arg2: &VectorSize,
2912 ) -> Option<Reg> {
2913     let pattern0_0 = arg0;
2914     let pattern1_0 = arg1;
2915     let pattern2_0 = arg2;
2916     // Rule at src/isa/aarch64/inst.isle line 1816.
2917     let expr0_0 = VecALUOp::Eor;
2918     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2919     return Some(expr1_0);
2920 }
2921 
2922 // Generated as internal constructor for term bic_vec.
2923 pub fn constructor_bic_vec<C: Context>(
2924     ctx: &mut C,
2925     arg0: Reg,
2926     arg1: Reg,
2927     arg2: &VectorSize,
2928 ) -> Option<Reg> {
2929     let pattern0_0 = arg0;
2930     let pattern1_0 = arg1;
2931     let pattern2_0 = arg2;
2932     // Rule at src/isa/aarch64/inst.isle line 1820.
2933     let expr0_0 = VecALUOp::Bic;
2934     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2935     return Some(expr1_0);
2936 }
2937 
2938 // Generated as internal constructor for term sshl.
2939 pub fn constructor_sshl<C: Context>(
2940     ctx: &mut C,
2941     arg0: Reg,
2942     arg1: Reg,
2943     arg2: &VectorSize,
2944 ) -> Option<Reg> {
2945     let pattern0_0 = arg0;
2946     let pattern1_0 = arg1;
2947     let pattern2_0 = arg2;
2948     // Rule at src/isa/aarch64/inst.isle line 1824.
2949     let expr0_0 = VecALUOp::Sshl;
2950     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2951     return Some(expr1_0);
2952 }
2953 
2954 // Generated as internal constructor for term ushl.
2955 pub fn constructor_ushl<C: Context>(
2956     ctx: &mut C,
2957     arg0: Reg,
2958     arg1: Reg,
2959     arg2: &VectorSize,
2960 ) -> Option<Reg> {
2961     let pattern0_0 = arg0;
2962     let pattern1_0 = arg1;
2963     let pattern2_0 = arg2;
2964     // Rule at src/isa/aarch64/inst.isle line 1828.
2965     let expr0_0 = VecALUOp::Ushl;
2966     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2967     return Some(expr1_0);
2968 }
2969 
2970 // Generated as internal constructor for term a64_rotr.
2971 pub fn constructor_a64_rotr<C: Context>(
2972     ctx: &mut C,
2973     arg0: Type,
2974     arg1: Reg,
2975     arg2: Reg,
2976 ) -> Option<Reg> {
2977     let pattern0_0 = arg0;
2978     let pattern1_0 = arg1;
2979     let pattern2_0 = arg2;
2980     // Rule at src/isa/aarch64/inst.isle line 1833.
2981     let expr0_0 = ALUOp::RotR;
2982     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2983     return Some(expr1_0);
2984 }
2985 
2986 // Generated as internal constructor for term a64_rotr_imm.
2987 pub fn constructor_a64_rotr_imm<C: Context>(
2988     ctx: &mut C,
2989     arg0: Type,
2990     arg1: Reg,
2991     arg2: ImmShift,
2992 ) -> Option<Reg> {
2993     let pattern0_0 = arg0;
2994     let pattern1_0 = arg1;
2995     let pattern2_0 = arg2;
2996     // Rule at src/isa/aarch64/inst.isle line 1836.
2997     let expr0_0 = ALUOp::RotR;
2998     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2999     return Some(expr1_0);
3000 }
3001 
3002 // Generated as internal constructor for term rbit.
3003 pub fn constructor_rbit<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
3004     let pattern0_0 = arg0;
3005     let pattern1_0 = arg1;
3006     // Rule at src/isa/aarch64/inst.isle line 1841.
3007     let expr0_0 = BitOp::RBit;
3008     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3009     return Some(expr1_0);
3010 }
3011 
3012 // Generated as internal constructor for term a64_clz.
3013 pub fn constructor_a64_clz<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
3014     let pattern0_0 = arg0;
3015     let pattern1_0 = arg1;
3016     // Rule at src/isa/aarch64/inst.isle line 1846.
3017     let expr0_0 = BitOp::Clz;
3018     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3019     return Some(expr1_0);
3020 }
3021 
3022 // Generated as internal constructor for term a64_cls.
3023 pub fn constructor_a64_cls<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
3024     let pattern0_0 = arg0;
3025     let pattern1_0 = arg1;
3026     // Rule at src/isa/aarch64/inst.isle line 1851.
3027     let expr0_0 = BitOp::Cls;
3028     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3029     return Some(expr1_0);
3030 }
3031 
3032 // Generated as internal constructor for term eon.
3033 pub fn constructor_eon<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
3034     let pattern0_0 = arg0;
3035     let pattern1_0 = arg1;
3036     let pattern2_0 = arg2;
3037     // Rule at src/isa/aarch64/inst.isle line 1856.
3038     let expr0_0 = ALUOp::EorNot;
3039     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
3040     return Some(expr1_0);
3041 }
3042 
3043 // Generated as internal constructor for term vec_cnt.
3044 pub fn constructor_vec_cnt<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3045     let pattern0_0 = arg0;
3046     let pattern1_0 = arg1;
3047     // Rule at src/isa/aarch64/inst.isle line 1861.
3048     let expr0_0 = VecMisc2::Cnt;
3049     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3050     return Some(expr1_0);
3051 }
3052 
3053 // Generated as internal constructor for term imm.
3054 pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
3055     let pattern0_0 = arg0;
3056     if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) {
3057         let pattern2_0 = arg1;
3058         let closure3 = || {
3059             let expr0_0: Type = I64;
3060             return Some(expr0_0);
3061         };
3062         if let Some(pattern3_0) = closure3() {
3063             if let Some(pattern4_0) = C::imm_logic_from_u64(ctx, pattern2_0, pattern3_0) {
3064                 // Rule at src/isa/aarch64/inst.isle line 1876.
3065                 let expr0_0: Type = I64;
3066                 let expr1_0 = C::zero_reg(ctx);
3067                 let expr2_0 = constructor_orr_imm(ctx, expr0_0, expr1_0, pattern4_0)?;
3068                 return Some(expr2_0);
3069             }
3070         }
3071         if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) {
3072             // Rule at src/isa/aarch64/inst.isle line 1868.
3073             let expr0_0 = OperandSize::Size64;
3074             let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?;
3075             return Some(expr1_0);
3076         }
3077         if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) {
3078             // Rule at src/isa/aarch64/inst.isle line 1872.
3079             let expr0_0 = OperandSize::Size64;
3080             let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?;
3081             return Some(expr1_0);
3082         }
3083         // Rule at src/isa/aarch64/inst.isle line 1883.
3084         let expr0_0 = C::load_constant64_full(ctx, pattern2_0);
3085         return Some(expr0_0);
3086     }
3087     return None;
3088 }
3089 
3090 // Generated as internal constructor for term put_in_reg_sext32.
3091 pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3092     let pattern0_0 = arg0;
3093     let pattern1_0 = C::value_type(ctx, pattern0_0);
3094     if pattern1_0 == I32 {
3095         // Rule at src/isa/aarch64/inst.isle line 1894.
3096         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3097         return Some(expr0_0);
3098     }
3099     if pattern1_0 == I64 {
3100         // Rule at src/isa/aarch64/inst.isle line 1895.
3101         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3102         return Some(expr0_0);
3103     }
3104     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3105         // Rule at src/isa/aarch64/inst.isle line 1890.
3106         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3107         let expr1_0: bool = true;
3108         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3109         let expr3_0: u8 = 32;
3110         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3111         return Some(expr4_0);
3112     }
3113     return None;
3114 }
3115 
3116 // Generated as internal constructor for term put_in_reg_zext32.
3117 pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3118     let pattern0_0 = arg0;
3119     let pattern1_0 = C::value_type(ctx, pattern0_0);
3120     if pattern1_0 == I32 {
3121         // Rule at src/isa/aarch64/inst.isle line 1903.
3122         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3123         return Some(expr0_0);
3124     }
3125     if pattern1_0 == I64 {
3126         // Rule at src/isa/aarch64/inst.isle line 1904.
3127         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3128         return Some(expr0_0);
3129     }
3130     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3131         // Rule at src/isa/aarch64/inst.isle line 1899.
3132         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3133         let expr1_0: bool = false;
3134         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3135         let expr3_0: u8 = 32;
3136         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3137         return Some(expr4_0);
3138     }
3139     return None;
3140 }
3141 
3142 // Generated as internal constructor for term put_in_reg_sext64.
3143 pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3144     let pattern0_0 = arg0;
3145     let pattern1_0 = C::value_type(ctx, pattern0_0);
3146     if pattern1_0 == I64 {
3147         // Rule at src/isa/aarch64/inst.isle line 1912.
3148         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3149         return Some(expr0_0);
3150     }
3151     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3152         // Rule at src/isa/aarch64/inst.isle line 1908.
3153         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3154         let expr1_0: bool = true;
3155         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3156         let expr3_0: u8 = 64;
3157         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3158         return Some(expr4_0);
3159     }
3160     return None;
3161 }
3162 
3163 // Generated as internal constructor for term put_in_reg_zext64.
3164 pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3165     let pattern0_0 = arg0;
3166     let pattern1_0 = C::value_type(ctx, pattern0_0);
3167     if pattern1_0 == I64 {
3168         // Rule at src/isa/aarch64/inst.isle line 1920.
3169         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3170         return Some(expr0_0);
3171     }
3172     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3173         // Rule at src/isa/aarch64/inst.isle line 1916.
3174         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3175         let expr1_0: bool = false;
3176         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3177         let expr3_0: u8 = 64;
3178         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3179         return Some(expr4_0);
3180     }
3181     return None;
3182 }
3183 
3184 // Generated as internal constructor for term trap_if_zero_divisor.
3185 pub fn constructor_trap_if_zero_divisor<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3186     let pattern0_0 = arg0;
3187     // Rule at src/isa/aarch64/inst.isle line 1925.
3188     let expr0_0 = C::cond_br_zero(ctx, pattern0_0);
3189     let expr1_0 = C::trap_code_division_by_zero(ctx);
3190     let expr2_0 = MInst::TrapIf {
3191         kind: expr0_0,
3192         trap_code: expr1_0,
3193     };
3194     let expr3_0 = C::emit(ctx, &expr2_0);
3195     return Some(pattern0_0);
3196 }
3197 
3198 // Generated as internal constructor for term size_from_ty.
3199 pub fn constructor_size_from_ty<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
3200     let pattern0_0 = arg0;
3201     if pattern0_0 == I64 {
3202         // Rule at src/isa/aarch64/inst.isle line 1931.
3203         let expr0_0 = OperandSize::Size64;
3204         return Some(expr0_0);
3205     }
3206     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
3207         // Rule at src/isa/aarch64/inst.isle line 1930.
3208         let expr0_0 = OperandSize::Size32;
3209         return Some(expr0_0);
3210     }
3211     return None;
3212 }
3213 
3214 // Generated as internal constructor for term trap_if_div_overflow.
3215 pub fn constructor_trap_if_div_overflow<C: Context>(
3216     ctx: &mut C,
3217     arg0: Type,
3218     arg1: Reg,
3219     arg2: Reg,
3220 ) -> Option<Reg> {
3221     let pattern0_0 = arg0;
3222     let pattern1_0 = arg1;
3223     let pattern2_0 = arg2;
3224     // Rule at src/isa/aarch64/inst.isle line 1937.
3225     let expr0_0 = ALUOp::AddS;
3226     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
3227     let expr2_0 = C::writable_zero_reg(ctx);
3228     let expr3_0: u8 = 1;
3229     let expr4_0 = C::u8_into_imm12(ctx, expr3_0);
3230     let expr5_0 = MInst::AluRRImm12 {
3231         alu_op: expr0_0,
3232         size: expr1_0,
3233         rd: expr2_0,
3234         rn: pattern2_0,
3235         imm12: expr4_0,
3236     };
3237     let expr6_0 = C::emit(ctx, &expr5_0);
3238     let expr7_0 = constructor_size_from_ty(ctx, pattern0_0)?;
3239     let expr8_0: u8 = 1;
3240     let expr9_0 = C::u8_into_uimm5(ctx, expr8_0);
3241     let expr10_0: bool = false;
3242     let expr11_0: bool = false;
3243     let expr12_0: bool = false;
3244     let expr13_0: bool = false;
3245     let expr14_0 = C::nzcv(ctx, expr10_0, expr11_0, expr12_0, expr13_0);
3246     let expr15_0 = Cond::Eq;
3247     let expr16_0 = MInst::CCmpImm {
3248         size: expr7_0,
3249         rn: pattern1_0,
3250         imm: expr9_0,
3251         nzcv: expr14_0,
3252         cond: expr15_0,
3253     };
3254     let expr17_0 = C::emit(ctx, &expr16_0);
3255     let expr18_0 = Cond::Vs;
3256     let expr19_0 = C::cond_br_cond(ctx, &expr18_0);
3257     let expr20_0 = C::trap_code_integer_overflow(ctx);
3258     let expr21_0 = MInst::TrapIf {
3259         kind: expr19_0,
3260         trap_code: expr20_0,
3261     };
3262     let expr22_0 = C::emit(ctx, &expr21_0);
3263     return Some(pattern1_0);
3264 }
3265 
3266 // Generated as internal constructor for term alu_rs_imm_logic_commutative.
3267 pub fn constructor_alu_rs_imm_logic_commutative<C: Context>(
3268     ctx: &mut C,
3269     arg0: &ALUOp,
3270     arg1: Type,
3271     arg2: Value,
3272     arg3: Value,
3273 ) -> Option<Reg> {
3274     let pattern0_0 = arg0;
3275     let pattern1_0 = arg1;
3276     let pattern2_0 = arg2;
3277     if let Some(pattern3_0) = C::def_inst(ctx, pattern2_0) {
3278         let pattern4_0 = C::inst_data(ctx, pattern3_0);
3279         match &pattern4_0 {
3280             &InstructionData::UnaryImm {
3281                 opcode: ref pattern5_0,
3282                 imm: pattern5_1,
3283             } => {
3284                 if let &Opcode::Iconst = pattern5_0 {
3285                     let closure7 = || {
3286                         return Some(pattern1_0);
3287                     };
3288                     if let Some(pattern7_0) = closure7() {
3289                         if let Some(pattern8_0) =
3290                             C::imm_logic_from_imm64(ctx, pattern5_1, pattern7_0)
3291                         {
3292                             let pattern9_0 = arg3;
3293                             // Rule at src/isa/aarch64/inst.isle line 1982.
3294                             let expr0_0 = C::put_in_reg(ctx, pattern9_0);
3295                             let expr1_0 = constructor_alu_rr_imm_logic(
3296                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0,
3297                             )?;
3298                             return Some(expr1_0);
3299                         }
3300                     }
3301                 }
3302             }
3303             &InstructionData::Binary {
3304                 opcode: ref pattern5_0,
3305                 args: ref pattern5_1,
3306             } => {
3307                 if let &Opcode::Ishl = pattern5_0 {
3308                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3309                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3310                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
3311                         if let &InstructionData::UnaryImm {
3312                             opcode: ref pattern10_0,
3313                             imm: pattern10_1,
3314                         } = &pattern9_0
3315                         {
3316                             if let &Opcode::Iconst = pattern10_0 {
3317                                 let closure12 = || {
3318                                     return Some(pattern1_0);
3319                                 };
3320                                 if let Some(pattern12_0) = closure12() {
3321                                     if let Some(pattern13_0) =
3322                                         C::lshl_from_imm64(ctx, pattern10_1, pattern12_0)
3323                                     {
3324                                         let pattern14_0 = arg3;
3325                                         // Rule at src/isa/aarch64/inst.isle line 1988.
3326                                         let expr0_0 = C::put_in_reg(ctx, pattern14_0);
3327                                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3328                                         let expr2_0 = constructor_alu_rrr_shift(
3329                                             ctx,
3330                                             pattern0_0,
3331                                             pattern1_0,
3332                                             expr0_0,
3333                                             expr1_0,
3334                                             pattern13_0,
3335                                         )?;
3336                                         return Some(expr2_0);
3337                                     }
3338                                 }
3339                             }
3340                         }
3341                     }
3342                 }
3343             }
3344             _ => {}
3345         }
3346     }
3347     let pattern3_0 = arg3;
3348     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3349         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3350         match &pattern5_0 {
3351             &InstructionData::UnaryImm {
3352                 opcode: ref pattern6_0,
3353                 imm: pattern6_1,
3354             } => {
3355                 if let &Opcode::Iconst = pattern6_0 {
3356                     let closure8 = || {
3357                         return Some(pattern1_0);
3358                     };
3359                     if let Some(pattern8_0) = closure8() {
3360                         if let Some(pattern9_0) =
3361                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3362                         {
3363                             // Rule at src/isa/aarch64/inst.isle line 1980.
3364                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3365                             let expr1_0 = constructor_alu_rr_imm_logic(
3366                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3367                             )?;
3368                             return Some(expr1_0);
3369                         }
3370                     }
3371                 }
3372             }
3373             &InstructionData::Binary {
3374                 opcode: ref pattern6_0,
3375                 args: ref pattern6_1,
3376             } => {
3377                 if let &Opcode::Ishl = pattern6_0 {
3378                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3379                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3380                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3381                         if let &InstructionData::UnaryImm {
3382                             opcode: ref pattern11_0,
3383                             imm: pattern11_1,
3384                         } = &pattern10_0
3385                         {
3386                             if let &Opcode::Iconst = pattern11_0 {
3387                                 let closure13 = || {
3388                                     return Some(pattern1_0);
3389                                 };
3390                                 if let Some(pattern13_0) = closure13() {
3391                                     if let Some(pattern14_0) =
3392                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3393                                     {
3394                                         // Rule at src/isa/aarch64/inst.isle line 1986.
3395                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3396                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3397                                         let expr2_0 = constructor_alu_rrr_shift(
3398                                             ctx,
3399                                             pattern0_0,
3400                                             pattern1_0,
3401                                             expr0_0,
3402                                             expr1_0,
3403                                             pattern14_0,
3404                                         )?;
3405                                         return Some(expr2_0);
3406                                     }
3407                                 }
3408                             }
3409                         }
3410                     }
3411                 }
3412             }
3413             _ => {}
3414         }
3415     }
3416     // Rule at src/isa/aarch64/inst.isle line 1976.
3417     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3418     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3419     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3420     return Some(expr2_0);
3421 }
3422 
3423 // Generated as internal constructor for term alu_rs_imm_logic.
3424 pub fn constructor_alu_rs_imm_logic<C: Context>(
3425     ctx: &mut C,
3426     arg0: &ALUOp,
3427     arg1: Type,
3428     arg2: Value,
3429     arg3: Value,
3430 ) -> Option<Reg> {
3431     let pattern0_0 = arg0;
3432     let pattern1_0 = arg1;
3433     let pattern2_0 = arg2;
3434     let pattern3_0 = arg3;
3435     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3436         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3437         match &pattern5_0 {
3438             &InstructionData::UnaryImm {
3439                 opcode: ref pattern6_0,
3440                 imm: pattern6_1,
3441             } => {
3442                 if let &Opcode::Iconst = pattern6_0 {
3443                     let closure8 = || {
3444                         return Some(pattern1_0);
3445                     };
3446                     if let Some(pattern8_0) = closure8() {
3447                         if let Some(pattern9_0) =
3448                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3449                         {
3450                             // Rule at src/isa/aarch64/inst.isle line 1996.
3451                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3452                             let expr1_0 = constructor_alu_rr_imm_logic(
3453                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3454                             )?;
3455                             return Some(expr1_0);
3456                         }
3457                     }
3458                 }
3459             }
3460             &InstructionData::Binary {
3461                 opcode: ref pattern6_0,
3462                 args: ref pattern6_1,
3463             } => {
3464                 if let &Opcode::Ishl = pattern6_0 {
3465                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3466                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3467                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3468                         if let &InstructionData::UnaryImm {
3469                             opcode: ref pattern11_0,
3470                             imm: pattern11_1,
3471                         } = &pattern10_0
3472                         {
3473                             if let &Opcode::Iconst = pattern11_0 {
3474                                 let closure13 = || {
3475                                     return Some(pattern1_0);
3476                                 };
3477                                 if let Some(pattern13_0) = closure13() {
3478                                     if let Some(pattern14_0) =
3479                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3480                                     {
3481                                         // Rule at src/isa/aarch64/inst.isle line 1998.
3482                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3483                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3484                                         let expr2_0 = constructor_alu_rrr_shift(
3485                                             ctx,
3486                                             pattern0_0,
3487                                             pattern1_0,
3488                                             expr0_0,
3489                                             expr1_0,
3490                                             pattern14_0,
3491                                         )?;
3492                                         return Some(expr2_0);
3493                                     }
3494                                 }
3495                             }
3496                         }
3497                     }
3498                 }
3499             }
3500             _ => {}
3501         }
3502     }
3503     // Rule at src/isa/aarch64/inst.isle line 1994.
3504     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3505     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3506     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3507     return Some(expr2_0);
3508 }
3509 
3510 // Generated as internal constructor for term i128_alu_bitop.
3511 pub fn constructor_i128_alu_bitop<C: Context>(
3512     ctx: &mut C,
3513     arg0: &ALUOp,
3514     arg1: Type,
3515     arg2: Value,
3516     arg3: Value,
3517 ) -> Option<ValueRegs> {
3518     let pattern0_0 = arg0;
3519     let pattern1_0 = arg1;
3520     let pattern2_0 = arg2;
3521     let pattern3_0 = arg3;
3522     // Rule at src/isa/aarch64/inst.isle line 2006.
3523     let expr0_0 = C::put_in_regs(ctx, pattern2_0);
3524     let expr1_0: usize = 0;
3525     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3526     let expr3_0: usize = 1;
3527     let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
3528     let expr5_0 = C::put_in_regs(ctx, pattern3_0);
3529     let expr6_0: usize = 0;
3530     let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
3531     let expr8_0: usize = 1;
3532     let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
3533     let expr10_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr2_0, expr7_0)?;
3534     let expr11_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr4_0, expr9_0)?;
3535     let expr12_0 = C::value_regs(ctx, expr10_0, expr11_0);
3536     return Some(expr12_0);
3537 }
3538 
3539 // Generated as internal constructor for term float_cmp_zero.
3540 pub fn constructor_float_cmp_zero<C: Context>(
3541     ctx: &mut C,
3542     arg0: &FloatCC,
3543     arg1: Reg,
3544     arg2: &VectorSize,
3545 ) -> Option<Reg> {
3546     let pattern0_0 = arg0;
3547     let pattern1_0 = arg1;
3548     let pattern2_0 = arg2;
3549     // Rule at src/isa/aarch64/inst.isle line 2046.
3550     let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0);
3551     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3552     return Some(expr1_0);
3553 }
3554 
3555 // Generated as internal constructor for term float_cmp_zero_swap.
3556 pub fn constructor_float_cmp_zero_swap<C: Context>(
3557     ctx: &mut C,
3558     arg0: &FloatCC,
3559     arg1: Reg,
3560     arg2: &VectorSize,
3561 ) -> Option<Reg> {
3562     let pattern0_0 = arg0;
3563     let pattern1_0 = arg1;
3564     let pattern2_0 = arg2;
3565     // Rule at src/isa/aarch64/inst.isle line 2051.
3566     let expr0_0 = C::float_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0);
3567     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3568     return Some(expr1_0);
3569 }
3570 
3571 // Generated as internal constructor for term fcmeq0.
3572 pub fn constructor_fcmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3573     let pattern0_0 = arg0;
3574     let pattern1_0 = arg1;
3575     // Rule at src/isa/aarch64/inst.isle line 2056.
3576     let expr0_0 = VecMisc2::Fcmeq0;
3577     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3578     return Some(expr1_0);
3579 }
3580 
3581 // Generated as internal constructor for term int_cmp_zero.
3582 pub fn constructor_int_cmp_zero<C: Context>(
3583     ctx: &mut C,
3584     arg0: &IntCC,
3585     arg1: Reg,
3586     arg2: &VectorSize,
3587 ) -> Option<Reg> {
3588     let pattern0_0 = arg0;
3589     let pattern1_0 = arg1;
3590     let pattern2_0 = arg2;
3591     // Rule at src/isa/aarch64/inst.isle line 2082.
3592     let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op(ctx, pattern0_0);
3593     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3594     return Some(expr1_0);
3595 }
3596 
3597 // Generated as internal constructor for term int_cmp_zero_swap.
3598 pub fn constructor_int_cmp_zero_swap<C: Context>(
3599     ctx: &mut C,
3600     arg0: &IntCC,
3601     arg1: Reg,
3602     arg2: &VectorSize,
3603 ) -> Option<Reg> {
3604     let pattern0_0 = arg0;
3605     let pattern1_0 = arg1;
3606     let pattern2_0 = arg2;
3607     // Rule at src/isa/aarch64/inst.isle line 2087.
3608     let expr0_0 = C::int_cc_cmp_zero_to_vec_misc_op_swap(ctx, pattern0_0);
3609     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern1_0, pattern2_0)?;
3610     return Some(expr1_0);
3611 }
3612 
3613 // Generated as internal constructor for term cmeq0.
3614 pub fn constructor_cmeq0<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
3615     let pattern0_0 = arg0;
3616     let pattern1_0 = arg1;
3617     // Rule at src/isa/aarch64/inst.isle line 2092.
3618     let expr0_0 = VecMisc2::Cmeq0;
3619     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
3620     return Some(expr1_0);
3621 }
3622 
3623 // Generated as internal constructor for term lower.
3624 pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> {
3625     let pattern0_0 = arg0;
3626     if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
3627         let pattern2_0 = C::value_type(ctx, pattern1_0);
3628         if pattern2_0 == I8 {
3629             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3630             if let &InstructionData::Unary {
3631                 opcode: ref pattern5_0,
3632                 arg: pattern5_1,
3633             } = &pattern4_0
3634             {
3635                 match pattern5_0 {
3636                     &Opcode::Bitrev => {
3637                         // Rule at src/isa/aarch64/lower.isle line 974.
3638                         let expr0_0: Type = I32;
3639                         let expr1_0: Type = I32;
3640                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3641                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3642                         let expr4_0: u8 = 24;
3643                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3644                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3645                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3646                         return Some(expr7_0);
3647                     }
3648                     &Opcode::Clz => {
3649                         // Rule at src/isa/aarch64/lower.isle line 995.
3650                         let expr0_0: Type = I32;
3651                         let expr1_0: Type = I32;
3652                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3653                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3654                         let expr4_0: u8 = 24;
3655                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3656                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3657                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3658                         return Some(expr7_0);
3659                     }
3660                     &Opcode::Cls => {
3661                         // Rule at src/isa/aarch64/lower.isle line 1042.
3662                         let expr0_0: Type = I32;
3663                         let expr1_0: Type = I32;
3664                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3665                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3666                         let expr4_0: u8 = 24;
3667                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3668                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3669                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3670                         return Some(expr7_0);
3671                     }
3672                     &Opcode::Ctz => {
3673                         // Rule at src/isa/aarch64/lower.isle line 1025.
3674                         let expr0_0: Type = I32;
3675                         let expr1_0: Type = I32;
3676                         let expr2_0: Type = I32;
3677                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3678                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3679                         let expr5_0: Type = I32;
3680                         let expr6_0: u64 = 8388608;
3681                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3682                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3683                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3684                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3685                         return Some(expr10_0);
3686                     }
3687                     &Opcode::Popcnt => {
3688                         // Rule at src/isa/aarch64/lower.isle line 1093.
3689                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3690                         let expr1_0 = ScalarSize::Size32;
3691                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3692                         let expr3_0 = VectorSize::Size8x8;
3693                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3694                         let expr5_0: u8 = 0;
3695                         let expr6_0 = VectorSize::Size8x16;
3696                         let expr7_0 = constructor_mov_from_vec(ctx, expr4_0, expr5_0, &expr6_0)?;
3697                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
3698                         return Some(expr8_0);
3699                     }
3700                     _ => {}
3701                 }
3702             }
3703         }
3704         if pattern2_0 == I16 {
3705             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3706             if let &InstructionData::Unary {
3707                 opcode: ref pattern5_0,
3708                 arg: pattern5_1,
3709             } = &pattern4_0
3710             {
3711                 match pattern5_0 {
3712                     &Opcode::Bitrev => {
3713                         // Rule at src/isa/aarch64/lower.isle line 980.
3714                         let expr0_0: Type = I32;
3715                         let expr1_0: Type = I32;
3716                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3717                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3718                         let expr4_0: u8 = 16;
3719                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3720                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3721                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3722                         return Some(expr7_0);
3723                     }
3724                     &Opcode::Clz => {
3725                         // Rule at src/isa/aarch64/lower.isle line 998.
3726                         let expr0_0: Type = I32;
3727                         let expr1_0: Type = I32;
3728                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3729                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3730                         let expr4_0: u8 = 16;
3731                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3732                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3733                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3734                         return Some(expr7_0);
3735                     }
3736                     &Opcode::Cls => {
3737                         // Rule at src/isa/aarch64/lower.isle line 1045.
3738                         let expr0_0: Type = I32;
3739                         let expr1_0: Type = I32;
3740                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3741                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3742                         let expr4_0: u8 = 16;
3743                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3744                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3745                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3746                         return Some(expr7_0);
3747                     }
3748                     &Opcode::Ctz => {
3749                         // Rule at src/isa/aarch64/lower.isle line 1028.
3750                         let expr0_0: Type = I32;
3751                         let expr1_0: Type = I32;
3752                         let expr2_0: Type = I32;
3753                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3754                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3755                         let expr5_0: Type = I32;
3756                         let expr6_0: u64 = 32768;
3757                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3758                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3759                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3760                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3761                         return Some(expr10_0);
3762                     }
3763                     &Opcode::Popcnt => {
3764                         // Rule at src/isa/aarch64/lower.isle line 1099.
3765                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3766                         let expr1_0 = ScalarSize::Size32;
3767                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3768                         let expr3_0 = VectorSize::Size8x8;
3769                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3770                         let expr5_0 = VectorSize::Size8x8;
3771                         let expr6_0 = constructor_addp(ctx, expr4_0, expr4_0, &expr5_0)?;
3772                         let expr7_0: u8 = 0;
3773                         let expr8_0 = VectorSize::Size8x16;
3774                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3775                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3776                         return Some(expr10_0);
3777                     }
3778                     _ => {}
3779                 }
3780             }
3781         }
3782         if pattern2_0 == I32 {
3783             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3784             match &pattern4_0 {
3785                 &InstructionData::Binary {
3786                     opcode: ref pattern5_0,
3787                     args: ref pattern5_1,
3788                 } => {
3789                     match pattern5_0 {
3790                         &Opcode::Rotl => {
3791                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3792                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3793                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3794                                 if let &InstructionData::UnaryImm {
3795                                     opcode: ref pattern10_0,
3796                                     imm: pattern10_1,
3797                                 } = &pattern9_0
3798                                 {
3799                                     if let &Opcode::Iconst = pattern10_0 {
3800                                         let closure12 = || {
3801                                             let expr0_0: Type = I32;
3802                                             return Some(expr0_0);
3803                                         };
3804                                         if let Some(pattern12_0) = closure12() {
3805                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3806                                                 ctx,
3807                                                 pattern10_1,
3808                                                 pattern12_0,
3809                                             ) {
3810                                                 // Rule at src/isa/aarch64/lower.isle line 865.
3811                                                 let expr0_0: Type = I32;
3812                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3813                                                 let expr2_0: Type = I32;
3814                                                 let expr3_0 =
3815                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3816                                                 let expr4_0 = constructor_a64_rotr_imm(
3817                                                     ctx, expr0_0, expr1_0, expr3_0,
3818                                                 )?;
3819                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3820                                                 return Some(expr5_0);
3821                                             }
3822                                         }
3823                                     }
3824                                 }
3825                             }
3826                             // Rule at src/isa/aarch64/lower.isle line 855.
3827                             let expr0_0: Type = I32;
3828                             let expr1_0 = C::zero_reg(ctx);
3829                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3830                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3831                             let expr4_0: Type = I32;
3832                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3833                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3834                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3835                             return Some(expr7_0);
3836                         }
3837                         &Opcode::Rotr => {
3838                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3839                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3840                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3841                                 if let &InstructionData::UnaryImm {
3842                                     opcode: ref pattern10_0,
3843                                     imm: pattern10_1,
3844                                 } = &pattern9_0
3845                                 {
3846                                     if let &Opcode::Iconst = pattern10_0 {
3847                                         let closure12 = || {
3848                                             let expr0_0: Type = I32;
3849                                             return Some(expr0_0);
3850                                         };
3851                                         if let Some(pattern12_0) = closure12() {
3852                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3853                                                 ctx,
3854                                                 pattern10_1,
3855                                                 pattern12_0,
3856                                             ) {
3857                                                 // Rule at src/isa/aarch64/lower.isle line 907.
3858                                                 let expr0_0: Type = I32;
3859                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3860                                                 let expr2_0 = constructor_a64_rotr_imm(
3861                                                     ctx,
3862                                                     expr0_0,
3863                                                     expr1_0,
3864                                                     pattern13_0,
3865                                                 )?;
3866                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3867                                                 return Some(expr3_0);
3868                                             }
3869                                         }
3870                                     }
3871                                 }
3872                             }
3873                             // Rule at src/isa/aarch64/lower.isle line 895.
3874                             let expr0_0: Type = I32;
3875                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3876                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3877                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
3878                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3879                             return Some(expr4_0);
3880                         }
3881                         _ => {}
3882                     }
3883                 }
3884                 &InstructionData::Unary {
3885                     opcode: ref pattern5_0,
3886                     arg: pattern5_1,
3887                 } => {
3888                     if let &Opcode::Popcnt = pattern5_0 {
3889                         // Rule at src/isa/aarch64/lower.isle line 1105.
3890                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3891                         let expr1_0 = ScalarSize::Size32;
3892                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3893                         let expr3_0 = VectorSize::Size8x8;
3894                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3895                         let expr5_0 = VectorSize::Size8x8;
3896                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
3897                         let expr7_0: u8 = 0;
3898                         let expr8_0 = VectorSize::Size8x16;
3899                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3900                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3901                         return Some(expr10_0);
3902                     }
3903                 }
3904                 _ => {}
3905             }
3906         }
3907         if pattern2_0 == I64 {
3908             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3909             match &pattern4_0 {
3910                 &InstructionData::Binary {
3911                     opcode: ref pattern5_0,
3912                     args: ref pattern5_1,
3913                 } => {
3914                     match pattern5_0 {
3915                         &Opcode::Umulhi => {
3916                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3917                             // Rule at src/isa/aarch64/lower.isle line 367.
3918                             let expr0_0: Type = I64;
3919                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3920                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3921                             let expr3_0 = constructor_umulh(ctx, expr0_0, expr1_0, expr2_0)?;
3922                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3923                             return Some(expr4_0);
3924                         }
3925                         &Opcode::Smulhi => {
3926                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3927                             // Rule at src/isa/aarch64/lower.isle line 355.
3928                             let expr0_0: Type = I64;
3929                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3930                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3931                             let expr3_0 = constructor_smulh(ctx, expr0_0, expr1_0, expr2_0)?;
3932                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3933                             return Some(expr4_0);
3934                         }
3935                         &Opcode::Band => {
3936                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3937                             // Rule at src/isa/aarch64/lower.isle line 586.
3938                             let expr0_0 = ALUOp::And;
3939                             let expr1_0: Type = I64;
3940                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3941                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3942                             )?;
3943                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3944                             return Some(expr3_0);
3945                         }
3946                         &Opcode::Bor => {
3947                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3948                             // Rule at src/isa/aarch64/lower.isle line 599.
3949                             let expr0_0 = ALUOp::Orr;
3950                             let expr1_0: Type = I64;
3951                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3952                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3953                             )?;
3954                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3955                             return Some(expr3_0);
3956                         }
3957                         &Opcode::Bxor => {
3958                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3959                             // Rule at src/isa/aarch64/lower.isle line 612.
3960                             let expr0_0 = ALUOp::Eor;
3961                             let expr1_0: Type = I64;
3962                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3963                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3964                             )?;
3965                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3966                             return Some(expr3_0);
3967                         }
3968                         &Opcode::BandNot => {
3969                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3970                             // Rule at src/isa/aarch64/lower.isle line 625.
3971                             let expr0_0 = ALUOp::AndNot;
3972                             let expr1_0: Type = I64;
3973                             let expr2_0 = constructor_alu_rs_imm_logic(
3974                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3975                             )?;
3976                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3977                             return Some(expr3_0);
3978                         }
3979                         &Opcode::BorNot => {
3980                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3981                             // Rule at src/isa/aarch64/lower.isle line 638.
3982                             let expr0_0 = ALUOp::OrrNot;
3983                             let expr1_0: Type = I64;
3984                             let expr2_0 = constructor_alu_rs_imm_logic(
3985                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3986                             )?;
3987                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3988                             return Some(expr3_0);
3989                         }
3990                         &Opcode::BxorNot => {
3991                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3992                             // Rule at src/isa/aarch64/lower.isle line 648.
3993                             let expr0_0 = ALUOp::EorNot;
3994                             let expr1_0: Type = I64;
3995                             let expr2_0 = constructor_alu_rs_imm_logic(
3996                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3997                             )?;
3998                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3999                             return Some(expr3_0);
4000                         }
4001                         &Opcode::Rotl => {
4002                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4003                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
4004                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
4005                                 if let &InstructionData::UnaryImm {
4006                                     opcode: ref pattern10_0,
4007                                     imm: pattern10_1,
4008                                 } = &pattern9_0
4009                                 {
4010                                     if let &Opcode::Iconst = pattern10_0 {
4011                                         let closure12 = || {
4012                                             let expr0_0: Type = I64;
4013                                             return Some(expr0_0);
4014                                         };
4015                                         if let Some(pattern12_0) = closure12() {
4016                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4017                                                 ctx,
4018                                                 pattern10_1,
4019                                                 pattern12_0,
4020                                             ) {
4021                                                 // Rule at src/isa/aarch64/lower.isle line 869.
4022                                                 let expr0_0: Type = I64;
4023                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4024                                                 let expr2_0: Type = I64;
4025                                                 let expr3_0 =
4026                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
4027                                                 let expr4_0 = constructor_a64_rotr_imm(
4028                                                     ctx, expr0_0, expr1_0, expr3_0,
4029                                                 )?;
4030                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
4031                                                 return Some(expr5_0);
4032                                             }
4033                                         }
4034                                     }
4035                                 }
4036                             }
4037                             // Rule at src/isa/aarch64/lower.isle line 860.
4038                             let expr0_0: Type = I64;
4039                             let expr1_0 = C::zero_reg(ctx);
4040                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4041                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
4042                             let expr4_0: Type = I64;
4043                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
4044                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
4045                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
4046                             return Some(expr7_0);
4047                         }
4048                         &Opcode::Rotr => {
4049                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4050                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
4051                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
4052                                 if let &InstructionData::UnaryImm {
4053                                     opcode: ref pattern10_0,
4054                                     imm: pattern10_1,
4055                                 } = &pattern9_0
4056                                 {
4057                                     if let &Opcode::Iconst = pattern10_0 {
4058                                         let closure12 = || {
4059                                             let expr0_0: Type = I64;
4060                                             return Some(expr0_0);
4061                                         };
4062                                         if let Some(pattern12_0) = closure12() {
4063                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
4064                                                 ctx,
4065                                                 pattern10_1,
4066                                                 pattern12_0,
4067                                             ) {
4068                                                 // Rule at src/isa/aarch64/lower.isle line 911.
4069                                                 let expr0_0: Type = I64;
4070                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4071                                                 let expr2_0 = constructor_a64_rotr_imm(
4072                                                     ctx,
4073                                                     expr0_0,
4074                                                     expr1_0,
4075                                                     pattern13_0,
4076                                                 )?;
4077                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4078                                                 return Some(expr3_0);
4079                                             }
4080                                         }
4081                                     }
4082                                 }
4083                             }
4084                             // Rule at src/isa/aarch64/lower.isle line 899.
4085                             let expr0_0: Type = I64;
4086                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
4087                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
4088                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
4089                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4090                             return Some(expr4_0);
4091                         }
4092                         &Opcode::Ishl => {
4093                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4094                             // Rule at src/isa/aarch64/lower.isle line 660.
4095                             let expr0_0 = ALUOp::Lsl;
4096                             let expr1_0: Type = I64;
4097                             let expr2_0 = C::put_in_reg(ctx, pattern7_0);
4098                             let expr3_0 =
4099                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4100                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4101                             return Some(expr4_0);
4102                         }
4103                         &Opcode::Ushr => {
4104                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4105                             // Rule at src/isa/aarch64/lower.isle line 744.
4106                             let expr0_0 = ALUOp::Lsr;
4107                             let expr1_0: Type = I64;
4108                             let expr2_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
4109                             let expr3_0 =
4110                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4111                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4112                             return Some(expr4_0);
4113                         }
4114                         &Opcode::Sshr => {
4115                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4116                             // Rule at src/isa/aarch64/lower.isle line 791.
4117                             let expr0_0 = ALUOp::Asr;
4118                             let expr1_0: Type = I64;
4119                             let expr2_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
4120                             let expr3_0 =
4121                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
4122                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
4123                             return Some(expr4_0);
4124                         }
4125                         _ => {}
4126                     }
4127                 }
4128                 &InstructionData::Unary {
4129                     opcode: ref pattern5_0,
4130                     arg: pattern5_1,
4131                 } => {
4132                     if let &Opcode::Popcnt = pattern5_0 {
4133                         // Rule at src/isa/aarch64/lower.isle line 1111.
4134                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4135                         let expr1_0 = ScalarSize::Size64;
4136                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
4137                         let expr3_0 = VectorSize::Size8x8;
4138                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
4139                         let expr5_0 = VectorSize::Size8x8;
4140                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
4141                         let expr7_0: u8 = 0;
4142                         let expr8_0 = VectorSize::Size8x16;
4143                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
4144                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
4145                         return Some(expr10_0);
4146                     }
4147                 }
4148                 _ => {}
4149             }
4150         }
4151         if pattern2_0 == I128 {
4152             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4153             match &pattern4_0 {
4154                 &InstructionData::Binary {
4155                     opcode: ref pattern5_0,
4156                     args: ref pattern5_1,
4157                 } => {
4158                     match pattern5_0 {
4159                         &Opcode::Iadd => {
4160                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4161                             // Rule at src/isa/aarch64/lower.isle line 79.
4162                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4163                             let expr1_0: usize = 0;
4164                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4165                             let expr3_0: usize = 1;
4166                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4167                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4168                             let expr6_0: usize = 0;
4169                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4170                             let expr8_0: usize = 1;
4171                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4172                             let expr10_0: Type = I64;
4173                             let expr11_0 =
4174                                 constructor_add_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4175                             let expr12_0: Type = I64;
4176                             let expr13_0 = constructor_adc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4177                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4178                             let expr15_0 = C::output(ctx, expr14_0);
4179                             return Some(expr15_0);
4180                         }
4181                         &Opcode::Isub => {
4182                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4183                             // Rule at src/isa/aarch64/lower.isle line 129.
4184                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4185                             let expr1_0: usize = 0;
4186                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4187                             let expr3_0: usize = 1;
4188                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4189                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4190                             let expr6_0: usize = 0;
4191                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4192                             let expr8_0: usize = 1;
4193                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4194                             let expr10_0: Type = I64;
4195                             let expr11_0 =
4196                                 constructor_sub_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4197                             let expr12_0: Type = I64;
4198                             let expr13_0 = constructor_sbc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4199                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4200                             let expr15_0 = C::output(ctx, expr14_0);
4201                             return Some(expr15_0);
4202                         }
4203                         &Opcode::Imul => {
4204                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4205                             // Rule at src/isa/aarch64/lower.isle line 183.
4206                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4207                             let expr1_0: usize = 0;
4208                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4209                             let expr3_0: usize = 1;
4210                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4211                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4212                             let expr6_0: usize = 0;
4213                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4214                             let expr8_0: usize = 1;
4215                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4216                             let expr10_0: Type = I64;
4217                             let expr11_0 = constructor_umulh(ctx, expr10_0, expr2_0, expr7_0)?;
4218                             let expr12_0 = constructor_madd64(ctx, expr2_0, expr9_0, expr11_0)?;
4219                             let expr13_0 = constructor_madd64(ctx, expr4_0, expr7_0, expr12_0)?;
4220                             let expr14_0 = C::zero_reg(ctx);
4221                             let expr15_0 = constructor_madd64(ctx, expr2_0, expr7_0, expr14_0)?;
4222                             let expr16_0 = C::value_regs(ctx, expr15_0, expr13_0);
4223                             let expr17_0 = C::output(ctx, expr16_0);
4224                             return Some(expr17_0);
4225                         }
4226                         &Opcode::Band => {
4227                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4228                             // Rule at src/isa/aarch64/lower.isle line 589.
4229                             let expr0_0 = ALUOp::And;
4230                             let expr1_0: Type = I64;
4231                             let expr2_0 = constructor_i128_alu_bitop(
4232                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4233                             )?;
4234                             let expr3_0 = C::output(ctx, expr2_0);
4235                             return Some(expr3_0);
4236                         }
4237                         &Opcode::Bor => {
4238                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4239                             // Rule at src/isa/aarch64/lower.isle line 602.
4240                             let expr0_0 = ALUOp::Orr;
4241                             let expr1_0: Type = I64;
4242                             let expr2_0 = constructor_i128_alu_bitop(
4243                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4244                             )?;
4245                             let expr3_0 = C::output(ctx, expr2_0);
4246                             return Some(expr3_0);
4247                         }
4248                         &Opcode::Bxor => {
4249                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4250                             // Rule at src/isa/aarch64/lower.isle line 615.
4251                             let expr0_0 = ALUOp::Eor;
4252                             let expr1_0: Type = I64;
4253                             let expr2_0 = constructor_i128_alu_bitop(
4254                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4255                             )?;
4256                             let expr3_0 = C::output(ctx, expr2_0);
4257                             return Some(expr3_0);
4258                         }
4259                         &Opcode::BandNot => {
4260                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4261                             // Rule at src/isa/aarch64/lower.isle line 628.
4262                             let expr0_0 = ALUOp::AndNot;
4263                             let expr1_0: Type = I64;
4264                             let expr2_0 = constructor_i128_alu_bitop(
4265                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4266                             )?;
4267                             let expr3_0 = C::output(ctx, expr2_0);
4268                             return Some(expr3_0);
4269                         }
4270                         &Opcode::BorNot => {
4271                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4272                             // Rule at src/isa/aarch64/lower.isle line 641.
4273                             let expr0_0 = ALUOp::OrrNot;
4274                             let expr1_0: Type = I64;
4275                             let expr2_0 = constructor_i128_alu_bitop(
4276                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4277                             )?;
4278                             let expr3_0 = C::output(ctx, expr2_0);
4279                             return Some(expr3_0);
4280                         }
4281                         &Opcode::BxorNot => {
4282                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4283                             // Rule at src/isa/aarch64/lower.isle line 651.
4284                             let expr0_0 = ALUOp::EorNot;
4285                             let expr1_0: Type = I64;
4286                             let expr2_0 = constructor_i128_alu_bitop(
4287                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4288                             )?;
4289                             let expr3_0 = C::output(ctx, expr2_0);
4290                             return Some(expr3_0);
4291                         }
4292                         &Opcode::Rotl => {
4293                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4294                             // Rule at src/isa/aarch64/lower.isle line 878.
4295                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4296                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4297                             let expr2_0: usize = 0;
4298                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4299                             let expr4_0: Type = I64;
4300                             let expr5_0: Type = I64;
4301                             let expr6_0: u64 = 128;
4302                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4303                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4304                             let expr9_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4305                             let expr10_0 = constructor_lower_ushr128(ctx, expr0_0, expr8_0)?;
4306                             let expr11_0: Type = I64;
4307                             let expr12_0: usize = 0;
4308                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4309                             let expr14_0: usize = 0;
4310                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4311                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4312                             let expr17_0: Type = I64;
4313                             let expr18_0: usize = 1;
4314                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4315                             let expr20_0: usize = 1;
4316                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4317                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4318                             let expr23_0 = C::value_regs(ctx, expr16_0, expr22_0);
4319                             let expr24_0 = C::output(ctx, expr23_0);
4320                             return Some(expr24_0);
4321                         }
4322                         &Opcode::Rotr => {
4323                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4324                             // Rule at src/isa/aarch64/lower.isle line 959.
4325                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4326                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4327                             let expr2_0: usize = 0;
4328                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4329                             let expr4_0: Type = I64;
4330                             let expr5_0: Type = I64;
4331                             let expr6_0: u64 = 128;
4332                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4333                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4334                             let expr9_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4335                             let expr10_0 = constructor_lower_shl128(ctx, expr0_0, expr8_0)?;
4336                             let expr11_0: Type = I64;
4337                             let expr12_0: usize = 1;
4338                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4339                             let expr14_0: usize = 1;
4340                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4341                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4342                             let expr17_0: Type = I64;
4343                             let expr18_0: usize = 0;
4344                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4345                             let expr20_0: usize = 0;
4346                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4347                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4348                             let expr23_0 = C::value_regs(ctx, expr22_0, expr16_0);
4349                             let expr24_0 = C::output(ctx, expr23_0);
4350                             return Some(expr24_0);
4351                         }
4352                         &Opcode::Ishl => {
4353                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4354                             // Rule at src/isa/aarch64/lower.isle line 664.
4355                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4356                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4357                             let expr2_0: usize = 0;
4358                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4359                             let expr4_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4360                             let expr5_0 = C::output(ctx, expr4_0);
4361                             return Some(expr5_0);
4362                         }
4363                         &Opcode::Ushr => {
4364                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4365                             // Rule at src/isa/aarch64/lower.isle line 748.
4366                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4367                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4368                             let expr2_0: usize = 0;
4369                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4370                             let expr4_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4371                             let expr5_0 = C::output(ctx, expr4_0);
4372                             return Some(expr5_0);
4373                         }
4374                         &Opcode::Sshr => {
4375                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4376                             // Rule at src/isa/aarch64/lower.isle line 795.
4377                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4378                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4379                             let expr2_0: usize = 0;
4380                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4381                             let expr4_0 = constructor_lower_sshr128(ctx, expr0_0, expr3_0)?;
4382                             let expr5_0 = C::output(ctx, expr4_0);
4383                             return Some(expr5_0);
4384                         }
4385                         _ => {}
4386                     }
4387                 }
4388                 &InstructionData::Unary {
4389                     opcode: ref pattern5_0,
4390                     arg: pattern5_1,
4391                 } => {
4392                     match pattern5_0 {
4393                         &Opcode::Bnot => {
4394                             // Rule at src/isa/aarch64/lower.isle line 569.
4395                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4396                             let expr1_0: usize = 0;
4397                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4398                             let expr3_0: usize = 1;
4399                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4400                             let expr5_0: Type = I64;
4401                             let expr6_0 = C::zero_reg(ctx);
4402                             let expr7_0 = constructor_orr_not(ctx, expr5_0, expr6_0, expr2_0)?;
4403                             let expr8_0: Type = I64;
4404                             let expr9_0 = C::zero_reg(ctx);
4405                             let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, expr4_0)?;
4406                             let expr11_0 = C::value_regs(ctx, expr7_0, expr10_0);
4407                             let expr12_0 = C::output(ctx, expr11_0);
4408                             return Some(expr12_0);
4409                         }
4410                         &Opcode::Bitrev => {
4411                             // Rule at src/isa/aarch64/lower.isle line 983.
4412                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4413                             let expr1_0: Type = I64;
4414                             let expr2_0: usize = 0;
4415                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4416                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4417                             let expr5_0: Type = I64;
4418                             let expr6_0: usize = 1;
4419                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4420                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4421                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4422                             let expr10_0 = C::output(ctx, expr9_0);
4423                             return Some(expr10_0);
4424                         }
4425                         &Opcode::Clz => {
4426                             // Rule at src/isa/aarch64/lower.isle line 1001.
4427                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4428                             let expr1_0 = constructor_lower_clz128(ctx, expr0_0)?;
4429                             let expr2_0 = C::output(ctx, expr1_0);
4430                             return Some(expr2_0);
4431                         }
4432                         &Opcode::Cls => {
4433                             // Rule at src/isa/aarch64/lower.isle line 1057.
4434                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4435                             let expr1_0: usize = 0;
4436                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4437                             let expr3_0: usize = 1;
4438                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4439                             let expr5_0: Type = I64;
4440                             let expr6_0 = constructor_a64_cls(ctx, expr5_0, expr2_0)?;
4441                             let expr7_0: Type = I64;
4442                             let expr8_0 = constructor_a64_cls(ctx, expr7_0, expr4_0)?;
4443                             let expr9_0: Type = I64;
4444                             let expr10_0 = constructor_eon(ctx, expr9_0, expr4_0, expr2_0)?;
4445                             let expr11_0: Type = I64;
4446                             let expr12_0: u8 = 63;
4447                             let expr13_0 = C::imm_shift_from_u8(ctx, expr12_0);
4448                             let expr14_0 = constructor_lsr_imm(ctx, expr11_0, expr10_0, expr13_0)?;
4449                             let expr15_0 = constructor_madd64(ctx, expr6_0, expr14_0, expr14_0)?;
4450                             let expr16_0: u8 = 63;
4451                             let expr17_0 = C::u8_into_imm12(ctx, expr16_0);
4452                             let expr18_0 = constructor_cmp64_imm(ctx, expr8_0, expr17_0)?;
4453                             let expr19_0 = Cond::Eq;
4454                             let expr20_0 = C::zero_reg(ctx);
4455                             let expr21_0 = constructor_csel(ctx, &expr19_0, expr15_0, expr20_0)?;
4456                             let expr22_0 = constructor_with_flags_reg(ctx, &expr18_0, &expr21_0)?;
4457                             let expr23_0: Type = I64;
4458                             let expr24_0 = constructor_add(ctx, expr23_0, expr22_0, expr8_0)?;
4459                             let expr25_0: Type = I64;
4460                             let expr26_0: u64 = 0;
4461                             let expr27_0 = constructor_imm(ctx, expr25_0, expr26_0)?;
4462                             let expr28_0 = C::value_regs(ctx, expr24_0, expr27_0);
4463                             let expr29_0 = C::output(ctx, expr28_0);
4464                             return Some(expr29_0);
4465                         }
4466                         &Opcode::Ctz => {
4467                             // Rule at src/isa/aarch64/lower.isle line 1031.
4468                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4469                             let expr1_0: Type = I64;
4470                             let expr2_0: usize = 0;
4471                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4472                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4473                             let expr5_0: Type = I64;
4474                             let expr6_0: usize = 1;
4475                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4476                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4477                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4478                             let expr10_0 = constructor_lower_clz128(ctx, expr9_0)?;
4479                             let expr11_0 = C::output(ctx, expr10_0);
4480                             return Some(expr11_0);
4481                         }
4482                         &Opcode::Popcnt => {
4483                             // Rule at src/isa/aarch64/lower.isle line 1117.
4484                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4485                             let expr1_0: usize = 0;
4486                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4487                             let expr3_0 = ScalarSize::Size64;
4488                             let expr4_0 = constructor_mov_to_fpu(ctx, expr2_0, &expr3_0)?;
4489                             let expr5_0: usize = 1;
4490                             let expr6_0 = C::value_regs_get(ctx, expr0_0, expr5_0);
4491                             let expr7_0: u8 = 1;
4492                             let expr8_0 = VectorSize::Size64x2;
4493                             let expr9_0 =
4494                                 constructor_mov_to_vec(ctx, expr4_0, expr6_0, expr7_0, &expr8_0)?;
4495                             let expr10_0 = VectorSize::Size8x16;
4496                             let expr11_0 = constructor_vec_cnt(ctx, expr9_0, &expr10_0)?;
4497                             let expr12_0 = VectorSize::Size8x16;
4498                             let expr13_0 = constructor_addv(ctx, expr11_0, &expr12_0)?;
4499                             let expr14_0: u8 = 0;
4500                             let expr15_0 = VectorSize::Size8x16;
4501                             let expr16_0 =
4502                                 constructor_mov_from_vec(ctx, expr13_0, expr14_0, &expr15_0)?;
4503                             let expr17_0: Type = I64;
4504                             let expr18_0: u64 = 0;
4505                             let expr19_0 = constructor_imm(ctx, expr17_0, expr18_0)?;
4506                             let expr20_0 = C::value_regs(ctx, expr16_0, expr19_0);
4507                             let expr21_0 = C::output(ctx, expr20_0);
4508                             return Some(expr21_0);
4509                         }
4510                         &Opcode::Uextend => {
4511                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4512                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4513                                 if let &InstructionData::BinaryImm8 {
4514                                     opcode: ref pattern9_0,
4515                                     arg: pattern9_1,
4516                                     imm: pattern9_2,
4517                                 } = &pattern8_0
4518                                 {
4519                                     if let &Opcode::Extractlane = pattern9_0 {
4520                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4521                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
4522                                         // Rule at src/isa/aarch64/lower.isle line 499.
4523                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4524                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
4525                                         let expr2_0 = constructor_mov_from_vec(
4526                                             ctx,
4527                                             expr0_0,
4528                                             pattern12_0,
4529                                             &expr1_0,
4530                                         )?;
4531                                         let expr3_0: Type = I64;
4532                                         let expr4_0: u64 = 0;
4533                                         let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
4534                                         let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
4535                                         let expr7_0 = C::output(ctx, expr6_0);
4536                                         return Some(expr7_0);
4537                                     }
4538                                 }
4539                             }
4540                             // Rule at src/isa/aarch64/lower.isle line 494.
4541                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
4542                             let expr1_0: Type = I64;
4543                             let expr2_0: u64 = 0;
4544                             let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
4545                             let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
4546                             let expr5_0 = C::output(ctx, expr4_0);
4547                             return Some(expr5_0);
4548                         }
4549                         &Opcode::Sextend => {
4550                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4551                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4552                                 if let &InstructionData::BinaryImm8 {
4553                                     opcode: ref pattern9_0,
4554                                     arg: pattern9_1,
4555                                     imm: pattern9_2,
4556                                 } = &pattern8_0
4557                                 {
4558                                     if let &Opcode::Extractlane = pattern9_0 {
4559                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4560                                         if pattern11_0 == I64X2 {
4561                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4562                                             // Rule at src/isa/aarch64/lower.isle line 543.
4563                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4564                                             let expr1_0 = VectorSize::Size64x2;
4565                                             let expr2_0 = constructor_mov_from_vec(
4566                                                 ctx,
4567                                                 expr0_0,
4568                                                 pattern13_0,
4569                                                 &expr1_0,
4570                                             )?;
4571                                             let expr3_0: Type = I64;
4572                                             let expr4_0: u8 = 63;
4573                                             let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
4574                                             let expr6_0 = constructor_asr_imm(
4575                                                 ctx, expr3_0, expr2_0, expr5_0,
4576                                             )?;
4577                                             let expr7_0 = C::value_regs(ctx, expr2_0, expr6_0);
4578                                             let expr8_0 = C::output(ctx, expr7_0);
4579                                             return Some(expr8_0);
4580                                         }
4581                                         if let Some(()) = C::not_i64x2(ctx, pattern11_0) {
4582                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4583                                             // Rule at src/isa/aarch64/lower.isle line 532.
4584                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4585                                             let expr1_0 =
4586                                                 constructor_vector_size(ctx, pattern11_0)?;
4587                                             let expr2_0: Type = I64;
4588                                             let expr3_0 = constructor_size_from_ty(ctx, expr2_0)?;
4589                                             let expr4_0 = constructor_mov_from_vec_signed(
4590                                                 ctx,
4591                                                 expr0_0,
4592                                                 pattern13_0,
4593                                                 &expr1_0,
4594                                                 &expr3_0,
4595                                             )?;
4596                                             let expr5_0: Type = I64;
4597                                             let expr6_0: u8 = 63;
4598                                             let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
4599                                             let expr8_0 = constructor_asr_imm(
4600                                                 ctx, expr5_0, expr4_0, expr7_0,
4601                                             )?;
4602                                             let expr9_0 = C::value_regs(ctx, expr4_0, expr8_0);
4603                                             let expr10_0 = C::output(ctx, expr9_0);
4604                                             return Some(expr10_0);
4605                                         }
4606                                     }
4607                                 }
4608                             }
4609                             // Rule at src/isa/aarch64/lower.isle line 522.
4610                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
4611                             let expr1_0: Type = I64;
4612                             let expr2_0: u8 = 63;
4613                             let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0);
4614                             let expr4_0 = constructor_asr_imm(ctx, expr1_0, expr0_0, expr3_0)?;
4615                             let expr5_0 = C::value_regs(ctx, expr0_0, expr4_0);
4616                             let expr6_0 = C::output(ctx, expr5_0);
4617                             return Some(expr6_0);
4618                         }
4619                         _ => {}
4620                     }
4621                 }
4622                 _ => {}
4623             }
4624         }
4625         if pattern2_0 == I8X16 {
4626             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4627             if let &InstructionData::Unary {
4628                 opcode: ref pattern5_0,
4629                 arg: pattern5_1,
4630             } = &pattern4_0
4631             {
4632                 if let &Opcode::Popcnt = pattern5_0 {
4633                     // Rule at src/isa/aarch64/lower.isle line 1125.
4634                     let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4635                     let expr1_0 = VectorSize::Size8x16;
4636                     let expr2_0 = constructor_vec_cnt(ctx, expr0_0, &expr1_0)?;
4637                     let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4638                     return Some(expr3_0);
4639                 }
4640             }
4641         }
4642         if pattern2_0 == I16X8 {
4643             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4644             if let &InstructionData::Binary {
4645                 opcode: ref pattern5_0,
4646                 args: ref pattern5_1,
4647             } = &pattern4_0
4648             {
4649                 if let &Opcode::Imul = pattern5_0 {
4650                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4651                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4652                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4653                         if let &InstructionData::Unary {
4654                             opcode: ref pattern10_0,
4655                             arg: pattern10_1,
4656                         } = &pattern9_0
4657                         {
4658                             match pattern10_0 {
4659                                 &Opcode::SwidenLow => {
4660                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4661                                     if pattern12_0 == I8X16 {
4662                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4663                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4664                                             if let &InstructionData::Unary {
4665                                                 opcode: ref pattern16_0,
4666                                                 arg: pattern16_1,
4667                                             } = &pattern15_0
4668                                             {
4669                                                 if let &Opcode::SwidenLow = pattern16_0 {
4670                                                     let pattern18_0 =
4671                                                         C::value_type(ctx, pattern16_1);
4672                                                     if pattern18_0 == I8X16 {
4673                                                         // Rule at src/isa/aarch64/lower.isle line 282.
4674                                                         let expr0_0 =
4675                                                             C::put_in_reg(ctx, pattern10_1);
4676                                                         let expr1_0 =
4677                                                             C::put_in_reg(ctx, pattern16_1);
4678                                                         let expr2_0: bool = false;
4679                                                         let expr3_0 = constructor_smull8(
4680                                                             ctx, expr0_0, expr1_0, expr2_0,
4681                                                         )?;
4682                                                         let expr4_0 =
4683                                                             constructor_output_reg(ctx, expr3_0)?;
4684                                                         return Some(expr4_0);
4685                                                     }
4686                                                 }
4687                                             }
4688                                         }
4689                                     }
4690                                 }
4691                                 &Opcode::SwidenHigh => {
4692                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4693                                     if pattern12_0 == I8X16 {
4694                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4695                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4696                                             if let &InstructionData::Unary {
4697                                                 opcode: ref pattern16_0,
4698                                                 arg: pattern16_1,
4699                                             } = &pattern15_0
4700                                             {
4701                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4702                                                     let pattern18_0 =
4703                                                         C::value_type(ctx, pattern16_1);
4704                                                     if pattern18_0 == I8X16 {
4705                                                         // Rule at src/isa/aarch64/lower.isle line 288.
4706                                                         let expr0_0 =
4707                                                             C::put_in_reg(ctx, pattern10_1);
4708                                                         let expr1_0 =
4709                                                             C::put_in_reg(ctx, pattern16_1);
4710                                                         let expr2_0: bool = true;
4711                                                         let expr3_0 = constructor_smull8(
4712                                                             ctx, expr0_0, expr1_0, expr2_0,
4713                                                         )?;
4714                                                         let expr4_0 =
4715                                                             constructor_output_reg(ctx, expr3_0)?;
4716                                                         return Some(expr4_0);
4717                                                     }
4718                                                 }
4719                                             }
4720                                         }
4721                                     }
4722                                 }
4723                                 &Opcode::UwidenLow => {
4724                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4725                                     if pattern12_0 == I8X16 {
4726                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4727                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4728                                             if let &InstructionData::Unary {
4729                                                 opcode: ref pattern16_0,
4730                                                 arg: pattern16_1,
4731                                             } = &pattern15_0
4732                                             {
4733                                                 if let &Opcode::UwidenLow = pattern16_0 {
4734                                                     let pattern18_0 =
4735                                                         C::value_type(ctx, pattern16_1);
4736                                                     if pattern18_0 == I8X16 {
4737                                                         // Rule at src/isa/aarch64/lower.isle line 294.
4738                                                         let expr0_0 =
4739                                                             C::put_in_reg(ctx, pattern10_1);
4740                                                         let expr1_0 =
4741                                                             C::put_in_reg(ctx, pattern16_1);
4742                                                         let expr2_0: bool = false;
4743                                                         let expr3_0 = constructor_umull8(
4744                                                             ctx, expr0_0, expr1_0, expr2_0,
4745                                                         )?;
4746                                                         let expr4_0 =
4747                                                             constructor_output_reg(ctx, expr3_0)?;
4748                                                         return Some(expr4_0);
4749                                                     }
4750                                                 }
4751                                             }
4752                                         }
4753                                     }
4754                                 }
4755                                 &Opcode::UwidenHigh => {
4756                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4757                                     if pattern12_0 == I8X16 {
4758                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4759                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4760                                             if let &InstructionData::Unary {
4761                                                 opcode: ref pattern16_0,
4762                                                 arg: pattern16_1,
4763                                             } = &pattern15_0
4764                                             {
4765                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4766                                                     let pattern18_0 =
4767                                                         C::value_type(ctx, pattern16_1);
4768                                                     if pattern18_0 == I8X16 {
4769                                                         // Rule at src/isa/aarch64/lower.isle line 300.
4770                                                         let expr0_0 =
4771                                                             C::put_in_reg(ctx, pattern10_1);
4772                                                         let expr1_0 =
4773                                                             C::put_in_reg(ctx, pattern16_1);
4774                                                         let expr2_0: bool = true;
4775                                                         let expr3_0 = constructor_umull8(
4776                                                             ctx, expr0_0, expr1_0, expr2_0,
4777                                                         )?;
4778                                                         let expr4_0 =
4779                                                             constructor_output_reg(ctx, expr3_0)?;
4780                                                         return Some(expr4_0);
4781                                                     }
4782                                                 }
4783                                             }
4784                                         }
4785                                     }
4786                                 }
4787                                 _ => {}
4788                             }
4789                         }
4790                     }
4791                 }
4792             }
4793         }
4794         if pattern2_0 == I32X4 {
4795             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4796             if let &InstructionData::Binary {
4797                 opcode: ref pattern5_0,
4798                 args: ref pattern5_1,
4799             } = &pattern4_0
4800             {
4801                 if let &Opcode::Imul = pattern5_0 {
4802                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4803                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4804                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4805                         if let &InstructionData::Unary {
4806                             opcode: ref pattern10_0,
4807                             arg: pattern10_1,
4808                         } = &pattern9_0
4809                         {
4810                             match pattern10_0 {
4811                                 &Opcode::SwidenLow => {
4812                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4813                                     if pattern12_0 == I16X8 {
4814                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4815                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4816                                             if let &InstructionData::Unary {
4817                                                 opcode: ref pattern16_0,
4818                                                 arg: pattern16_1,
4819                                             } = &pattern15_0
4820                                             {
4821                                                 if let &Opcode::SwidenLow = pattern16_0 {
4822                                                     let pattern18_0 =
4823                                                         C::value_type(ctx, pattern16_1);
4824                                                     if pattern18_0 == I16X8 {
4825                                                         // Rule at src/isa/aarch64/lower.isle line 306.
4826                                                         let expr0_0 =
4827                                                             C::put_in_reg(ctx, pattern10_1);
4828                                                         let expr1_0 =
4829                                                             C::put_in_reg(ctx, pattern16_1);
4830                                                         let expr2_0: bool = false;
4831                                                         let expr3_0 = constructor_smull16(
4832                                                             ctx, expr0_0, expr1_0, expr2_0,
4833                                                         )?;
4834                                                         let expr4_0 =
4835                                                             constructor_output_reg(ctx, expr3_0)?;
4836                                                         return Some(expr4_0);
4837                                                     }
4838                                                 }
4839                                             }
4840                                         }
4841                                     }
4842                                 }
4843                                 &Opcode::SwidenHigh => {
4844                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4845                                     if pattern12_0 == I16X8 {
4846                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4847                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4848                                             if let &InstructionData::Unary {
4849                                                 opcode: ref pattern16_0,
4850                                                 arg: pattern16_1,
4851                                             } = &pattern15_0
4852                                             {
4853                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4854                                                     let pattern18_0 =
4855                                                         C::value_type(ctx, pattern16_1);
4856                                                     if pattern18_0 == I16X8 {
4857                                                         // Rule at src/isa/aarch64/lower.isle line 312.
4858                                                         let expr0_0 =
4859                                                             C::put_in_reg(ctx, pattern10_1);
4860                                                         let expr1_0 =
4861                                                             C::put_in_reg(ctx, pattern16_1);
4862                                                         let expr2_0: bool = true;
4863                                                         let expr3_0 = constructor_smull16(
4864                                                             ctx, expr0_0, expr1_0, expr2_0,
4865                                                         )?;
4866                                                         let expr4_0 =
4867                                                             constructor_output_reg(ctx, expr3_0)?;
4868                                                         return Some(expr4_0);
4869                                                     }
4870                                                 }
4871                                             }
4872                                         }
4873                                     }
4874                                 }
4875                                 &Opcode::UwidenLow => {
4876                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4877                                     if pattern12_0 == I16X8 {
4878                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4879                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4880                                             if let &InstructionData::Unary {
4881                                                 opcode: ref pattern16_0,
4882                                                 arg: pattern16_1,
4883                                             } = &pattern15_0
4884                                             {
4885                                                 if let &Opcode::UwidenLow = pattern16_0 {
4886                                                     let pattern18_0 =
4887                                                         C::value_type(ctx, pattern16_1);
4888                                                     if pattern18_0 == I16X8 {
4889                                                         // Rule at src/isa/aarch64/lower.isle line 318.
4890                                                         let expr0_0 =
4891                                                             C::put_in_reg(ctx, pattern10_1);
4892                                                         let expr1_0 =
4893                                                             C::put_in_reg(ctx, pattern16_1);
4894                                                         let expr2_0: bool = false;
4895                                                         let expr3_0 = constructor_umull16(
4896                                                             ctx, expr0_0, expr1_0, expr2_0,
4897                                                         )?;
4898                                                         let expr4_0 =
4899                                                             constructor_output_reg(ctx, expr3_0)?;
4900                                                         return Some(expr4_0);
4901                                                     }
4902                                                 }
4903                                             }
4904                                         }
4905                                     }
4906                                 }
4907                                 &Opcode::UwidenHigh => {
4908                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4909                                     if pattern12_0 == I16X8 {
4910                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4911                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4912                                             if let &InstructionData::Unary {
4913                                                 opcode: ref pattern16_0,
4914                                                 arg: pattern16_1,
4915                                             } = &pattern15_0
4916                                             {
4917                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4918                                                     let pattern18_0 =
4919                                                         C::value_type(ctx, pattern16_1);
4920                                                     if pattern18_0 == I16X8 {
4921                                                         // Rule at src/isa/aarch64/lower.isle line 324.
4922                                                         let expr0_0 =
4923                                                             C::put_in_reg(ctx, pattern10_1);
4924                                                         let expr1_0 =
4925                                                             C::put_in_reg(ctx, pattern16_1);
4926                                                         let expr2_0: bool = true;
4927                                                         let expr3_0 = constructor_umull16(
4928                                                             ctx, expr0_0, expr1_0, expr2_0,
4929                                                         )?;
4930                                                         let expr4_0 =
4931                                                             constructor_output_reg(ctx, expr3_0)?;
4932                                                         return Some(expr4_0);
4933                                                     }
4934                                                 }
4935                                             }
4936                                         }
4937                                     }
4938                                 }
4939                                 _ => {}
4940                             }
4941                         }
4942                     }
4943                 }
4944             }
4945         }
4946         if pattern2_0 == I64X2 {
4947             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4948             if let &InstructionData::Binary {
4949                 opcode: ref pattern5_0,
4950                 args: ref pattern5_1,
4951             } = &pattern4_0
4952             {
4953                 if let &Opcode::Imul = pattern5_0 {
4954                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4955                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4956                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4957                         if let &InstructionData::Unary {
4958                             opcode: ref pattern10_0,
4959                             arg: pattern10_1,
4960                         } = &pattern9_0
4961                         {
4962                             match pattern10_0 {
4963                                 &Opcode::SwidenLow => {
4964                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4965                                     if pattern12_0 == I32X4 {
4966                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4967                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4968                                             if let &InstructionData::Unary {
4969                                                 opcode: ref pattern16_0,
4970                                                 arg: pattern16_1,
4971                                             } = &pattern15_0
4972                                             {
4973                                                 if let &Opcode::SwidenLow = pattern16_0 {
4974                                                     let pattern18_0 =
4975                                                         C::value_type(ctx, pattern16_1);
4976                                                     if pattern18_0 == I32X4 {
4977                                                         // Rule at src/isa/aarch64/lower.isle line 330.
4978                                                         let expr0_0 =
4979                                                             C::put_in_reg(ctx, pattern10_1);
4980                                                         let expr1_0 =
4981                                                             C::put_in_reg(ctx, pattern16_1);
4982                                                         let expr2_0: bool = false;
4983                                                         let expr3_0 = constructor_smull32(
4984                                                             ctx, expr0_0, expr1_0, expr2_0,
4985                                                         )?;
4986                                                         let expr4_0 =
4987                                                             constructor_output_reg(ctx, expr3_0)?;
4988                                                         return Some(expr4_0);
4989                                                     }
4990                                                 }
4991                                             }
4992                                         }
4993                                     }
4994                                 }
4995                                 &Opcode::SwidenHigh => {
4996                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4997                                     if pattern12_0 == I32X4 {
4998                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4999                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5000                                             if let &InstructionData::Unary {
5001                                                 opcode: ref pattern16_0,
5002                                                 arg: pattern16_1,
5003                                             } = &pattern15_0
5004                                             {
5005                                                 if let &Opcode::SwidenHigh = pattern16_0 {
5006                                                     let pattern18_0 =
5007                                                         C::value_type(ctx, pattern16_1);
5008                                                     if pattern18_0 == I32X4 {
5009                                                         // Rule at src/isa/aarch64/lower.isle line 336.
5010                                                         let expr0_0 =
5011                                                             C::put_in_reg(ctx, pattern10_1);
5012                                                         let expr1_0 =
5013                                                             C::put_in_reg(ctx, pattern16_1);
5014                                                         let expr2_0: bool = true;
5015                                                         let expr3_0 = constructor_smull32(
5016                                                             ctx, expr0_0, expr1_0, expr2_0,
5017                                                         )?;
5018                                                         let expr4_0 =
5019                                                             constructor_output_reg(ctx, expr3_0)?;
5020                                                         return Some(expr4_0);
5021                                                     }
5022                                                 }
5023                                             }
5024                                         }
5025                                     }
5026                                 }
5027                                 &Opcode::UwidenLow => {
5028                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5029                                     if pattern12_0 == I32X4 {
5030                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5031                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5032                                             if let &InstructionData::Unary {
5033                                                 opcode: ref pattern16_0,
5034                                                 arg: pattern16_1,
5035                                             } = &pattern15_0
5036                                             {
5037                                                 if let &Opcode::UwidenLow = pattern16_0 {
5038                                                     let pattern18_0 =
5039                                                         C::value_type(ctx, pattern16_1);
5040                                                     if pattern18_0 == I32X4 {
5041                                                         // Rule at src/isa/aarch64/lower.isle line 342.
5042                                                         let expr0_0 =
5043                                                             C::put_in_reg(ctx, pattern10_1);
5044                                                         let expr1_0 =
5045                                                             C::put_in_reg(ctx, pattern16_1);
5046                                                         let expr2_0: bool = false;
5047                                                         let expr3_0 = constructor_umull32(
5048                                                             ctx, expr0_0, expr1_0, expr2_0,
5049                                                         )?;
5050                                                         let expr4_0 =
5051                                                             constructor_output_reg(ctx, expr3_0)?;
5052                                                         return Some(expr4_0);
5053                                                     }
5054                                                 }
5055                                             }
5056                                         }
5057                                     }
5058                                 }
5059                                 &Opcode::UwidenHigh => {
5060                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
5061                                     if pattern12_0 == I32X4 {
5062                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
5063                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
5064                                             if let &InstructionData::Unary {
5065                                                 opcode: ref pattern16_0,
5066                                                 arg: pattern16_1,
5067                                             } = &pattern15_0
5068                                             {
5069                                                 if let &Opcode::UwidenHigh = pattern16_0 {
5070                                                     let pattern18_0 =
5071                                                         C::value_type(ctx, pattern16_1);
5072                                                     if pattern18_0 == I32X4 {
5073                                                         // Rule at src/isa/aarch64/lower.isle line 348.
5074                                                         let expr0_0 =
5075                                                             C::put_in_reg(ctx, pattern10_1);
5076                                                         let expr1_0 =
5077                                                             C::put_in_reg(ctx, pattern16_1);
5078                                                         let expr2_0: bool = true;
5079                                                         let expr3_0 = constructor_umull32(
5080                                                             ctx, expr0_0, expr1_0, expr2_0,
5081                                                         )?;
5082                                                         let expr4_0 =
5083                                                             constructor_output_reg(ctx, expr3_0)?;
5084                                                         return Some(expr4_0);
5085                                                     }
5086                                                 }
5087                                             }
5088                                         }
5089                                     }
5090                                 }
5091                                 _ => {}
5092                             }
5093                         }
5094                     }
5095                     // Rule at src/isa/aarch64/lower.isle line 243.
5096                     let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5097                     let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5098                     let expr2_0 = VectorSize::Size32x4;
5099                     let expr3_0 = constructor_rev64(ctx, expr1_0, &expr2_0)?;
5100                     let expr4_0 = VectorSize::Size32x4;
5101                     let expr5_0 = constructor_mul(ctx, expr3_0, expr0_0, &expr4_0)?;
5102                     let expr6_0: bool = false;
5103                     let expr7_0 = constructor_xtn64(ctx, expr0_0, expr6_0)?;
5104                     let expr8_0 = VectorSize::Size32x4;
5105                     let expr9_0 = constructor_addp(ctx, expr5_0, expr5_0, &expr8_0)?;
5106                     let expr10_0: bool = false;
5107                     let expr11_0 = constructor_xtn64(ctx, expr1_0, expr10_0)?;
5108                     let expr12_0: bool = false;
5109                     let expr13_0 = constructor_shll32(ctx, expr9_0, expr12_0)?;
5110                     let expr14_0: bool = false;
5111                     let expr15_0 = constructor_umlal32(ctx, expr13_0, expr11_0, expr7_0, expr14_0)?;
5112                     let expr16_0 = constructor_output_reg(ctx, expr15_0)?;
5113                     return Some(expr16_0);
5114                 }
5115             }
5116         }
5117         let pattern3_0 = C::inst_data(ctx, pattern0_0);
5118         match &pattern3_0 {
5119             &InstructionData::NullAry {
5120                 opcode: ref pattern4_0,
5121             } => {
5122                 if let &Opcode::Null = pattern4_0 {
5123                     // Rule at src/isa/aarch64/lower.isle line 22.
5124                     let expr0_0: u64 = 0;
5125                     let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5126                     let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5127                     return Some(expr2_0);
5128                 }
5129             }
5130             &InstructionData::UnaryImm {
5131                 opcode: ref pattern4_0,
5132                 imm: pattern4_1,
5133             } => {
5134                 if let &Opcode::Iconst = pattern4_0 {
5135                     let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1);
5136                     // Rule at src/isa/aarch64/lower.isle line 9.
5137                     let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?;
5138                     let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
5139                     return Some(expr1_0);
5140                 }
5141             }
5142             &InstructionData::UnaryBool {
5143                 opcode: ref pattern4_0,
5144                 imm: pattern4_1,
5145             } => {
5146                 if let &Opcode::Bconst = pattern4_0 {
5147                     if pattern4_1 == true {
5148                         // Rule at src/isa/aarch64/lower.isle line 17.
5149                         let expr0_0: u64 = 1;
5150                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5151                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5152                         return Some(expr2_0);
5153                     }
5154                     if pattern4_1 == false {
5155                         // Rule at src/isa/aarch64/lower.isle line 14.
5156                         let expr0_0: u64 = 0;
5157                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
5158                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5159                         return Some(expr2_0);
5160                     }
5161                 }
5162             }
5163             &InstructionData::Unary {
5164                 opcode: ref pattern4_0,
5165                 arg: pattern4_1,
5166             } => {
5167                 match pattern4_0 {
5168                     &Opcode::Bitrev => {
5169                         // Rule at src/isa/aarch64/lower.isle line 989.
5170                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5171                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5172                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5173                         return Some(expr2_0);
5174                     }
5175                     &Opcode::Clz => {
5176                         // Rule at src/isa/aarch64/lower.isle line 1004.
5177                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5178                         let expr1_0 = constructor_a64_clz(ctx, pattern2_0, expr0_0)?;
5179                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5180                         return Some(expr2_0);
5181                     }
5182                     &Opcode::Cls => {
5183                         // Rule at src/isa/aarch64/lower.isle line 1071.
5184                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5185                         let expr1_0 = constructor_a64_cls(ctx, pattern2_0, expr0_0)?;
5186                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5187                         return Some(expr2_0);
5188                     }
5189                     &Opcode::Ctz => {
5190                         // Rule at src/isa/aarch64/lower.isle line 1037.
5191                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5192                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5193                         let expr2_0 = constructor_a64_clz(ctx, pattern2_0, expr1_0)?;
5194                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5195                         return Some(expr3_0);
5196                     }
5197                     _ => {}
5198                 }
5199             }
5200             _ => {}
5201         }
5202         if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) {
5203             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5204             match &pattern4_0 {
5205                 &InstructionData::Binary {
5206                     opcode: ref pattern5_0,
5207                     args: ref pattern5_1,
5208                 } => {
5209                     match pattern5_0 {
5210                         &Opcode::Iadd => {
5211                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5212                             // Rule at src/isa/aarch64/lower.isle line 75.
5213                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5214                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5215                             let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5216                             let expr3_0 = constructor_add_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5217                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5218                             return Some(expr4_0);
5219                         }
5220                         &Opcode::Isub => {
5221                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5222                             // Rule at src/isa/aarch64/lower.isle line 125.
5223                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5224                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5225                             let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5226                             let expr3_0 = constructor_sub_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5227                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5228                             return Some(expr4_0);
5229                         }
5230                         _ => {}
5231                     }
5232                 }
5233                 &InstructionData::FloatCompare {
5234                     opcode: ref pattern5_0,
5235                     args: ref pattern5_1,
5236                     cond: ref pattern5_2,
5237                 } => {
5238                     if let &Opcode::Fcmp = pattern5_0 {
5239                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5240                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5241                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5242                             if let &InstructionData::Unary {
5243                                 opcode: ref pattern10_0,
5244                                 arg: pattern10_1,
5245                             } = &pattern9_0
5246                             {
5247                                 if let &Opcode::Splat = pattern10_0 {
5248                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5249                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5250                                         match &pattern13_0 {
5251                                             &InstructionData::UnaryIeee32 {
5252                                                 opcode: ref pattern14_0,
5253                                                 imm: pattern14_1,
5254                                             } => {
5255                                                 if let &Opcode::F32const = pattern14_0 {
5256                                                     if let Some(pattern16_0) =
5257                                                         C::zero_value_f32(ctx, pattern14_1)
5258                                                     {
5259                                                         if let Some(pattern17_0) =
5260                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5261                                                         {
5262                                                             // Rule at src/isa/aarch64/lower.isle line 1145.
5263                                                             let expr0_0 =
5264                                                                 C::put_in_reg(ctx, pattern7_1);
5265                                                             let expr1_0 = constructor_vector_size(
5266                                                                 ctx, pattern2_0,
5267                                                             )?;
5268                                                             let expr2_0 =
5269                                                                 constructor_float_cmp_zero_swap(
5270                                                                     ctx,
5271                                                                     &pattern17_0,
5272                                                                     expr0_0,
5273                                                                     &expr1_0,
5274                                                                 )?;
5275                                                             let expr3_0 =
5276                                                                 C::value_reg(ctx, expr2_0);
5277                                                             let expr4_0 = C::output(ctx, expr3_0);
5278                                                             return Some(expr4_0);
5279                                                         }
5280                                                         if let Some(pattern17_0) =
5281                                                             C::fcmp_zero_cond_not_eq(
5282                                                                 ctx, pattern5_2,
5283                                                             )
5284                                                         {
5285                                                             // Rule at src/isa/aarch64/lower.isle line 1140.
5286                                                             let expr0_0 =
5287                                                                 C::put_in_reg(ctx, pattern7_1);
5288                                                             let expr1_0 = constructor_vector_size(
5289                                                                 ctx, pattern2_0,
5290                                                             )?;
5291                                                             let expr2_0 = constructor_fcmeq0(
5292                                                                 ctx, expr0_0, &expr1_0,
5293                                                             )?;
5294                                                             let expr3_0 = constructor_not(
5295                                                                 ctx, expr2_0, &expr1_0,
5296                                                             )?;
5297                                                             let expr4_0 =
5298                                                                 C::value_reg(ctx, expr3_0);
5299                                                             let expr5_0 = C::output(ctx, expr4_0);
5300                                                             return Some(expr5_0);
5301                                                         }
5302                                                     }
5303                                                 }
5304                                             }
5305                                             &InstructionData::UnaryIeee64 {
5306                                                 opcode: ref pattern14_0,
5307                                                 imm: pattern14_1,
5308                                             } => {
5309                                                 if let &Opcode::F64const = pattern14_0 {
5310                                                     if let Some(pattern16_0) =
5311                                                         C::zero_value_f64(ctx, pattern14_1)
5312                                                     {
5313                                                         if let Some(pattern17_0) =
5314                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5315                                                         {
5316                                                             // Rule at src/isa/aarch64/lower.isle line 1167.
5317                                                             let expr0_0 =
5318                                                                 C::put_in_reg(ctx, pattern7_1);
5319                                                             let expr1_0 = constructor_vector_size(
5320                                                                 ctx, pattern2_0,
5321                                                             )?;
5322                                                             let expr2_0 =
5323                                                                 constructor_float_cmp_zero_swap(
5324                                                                     ctx,
5325                                                                     &pattern17_0,
5326                                                                     expr0_0,
5327                                                                     &expr1_0,
5328                                                                 )?;
5329                                                             let expr3_0 =
5330                                                                 C::value_reg(ctx, expr2_0);
5331                                                             let expr4_0 = C::output(ctx, expr3_0);
5332                                                             return Some(expr4_0);
5333                                                         }
5334                                                         if let Some(pattern17_0) =
5335                                                             C::fcmp_zero_cond_not_eq(
5336                                                                 ctx, pattern5_2,
5337                                                             )
5338                                                         {
5339                                                             // Rule at src/isa/aarch64/lower.isle line 1162.
5340                                                             let expr0_0 =
5341                                                                 C::put_in_reg(ctx, pattern7_1);
5342                                                             let expr1_0 = constructor_vector_size(
5343                                                                 ctx, pattern2_0,
5344                                                             )?;
5345                                                             let expr2_0 = constructor_fcmeq0(
5346                                                                 ctx, expr0_0, &expr1_0,
5347                                                             )?;
5348                                                             let expr3_0 = constructor_not(
5349                                                                 ctx, expr2_0, &expr1_0,
5350                                                             )?;
5351                                                             let expr4_0 =
5352                                                                 C::value_reg(ctx, expr3_0);
5353                                                             let expr5_0 = C::output(ctx, expr4_0);
5354                                                             return Some(expr5_0);
5355                                                         }
5356                                                     }
5357                                                 }
5358                                             }
5359                                             _ => {}
5360                                         }
5361                                     }
5362                                 }
5363                             }
5364                         }
5365                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5366                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5367                             if let &InstructionData::Unary {
5368                                 opcode: ref pattern10_0,
5369                                 arg: pattern10_1,
5370                             } = &pattern9_0
5371                             {
5372                                 if let &Opcode::Splat = pattern10_0 {
5373                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5374                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5375                                         match &pattern13_0 {
5376                                             &InstructionData::UnaryIeee32 {
5377                                                 opcode: ref pattern14_0,
5378                                                 imm: pattern14_1,
5379                                             } => {
5380                                                 if let &Opcode::F32const = pattern14_0 {
5381                                                     if let Some(pattern16_0) =
5382                                                         C::zero_value_f32(ctx, pattern14_1)
5383                                                     {
5384                                                         if let Some(pattern17_0) =
5385                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5386                                                         {
5387                                                             // Rule at src/isa/aarch64/lower.isle line 1135.
5388                                                             let expr0_0 =
5389                                                                 C::put_in_reg(ctx, pattern7_0);
5390                                                             let expr1_0 = constructor_vector_size(
5391                                                                 ctx, pattern2_0,
5392                                                             )?;
5393                                                             let expr2_0 =
5394                                                                 constructor_float_cmp_zero(
5395                                                                     ctx,
5396                                                                     &pattern17_0,
5397                                                                     expr0_0,
5398                                                                     &expr1_0,
5399                                                                 )?;
5400                                                             let expr3_0 =
5401                                                                 C::value_reg(ctx, expr2_0);
5402                                                             let expr4_0 = C::output(ctx, expr3_0);
5403                                                             return Some(expr4_0);
5404                                                         }
5405                                                         if let Some(pattern17_0) =
5406                                                             C::fcmp_zero_cond_not_eq(
5407                                                                 ctx, pattern5_2,
5408                                                             )
5409                                                         {
5410                                                             // Rule at src/isa/aarch64/lower.isle line 1130.
5411                                                             let expr0_0 =
5412                                                                 C::put_in_reg(ctx, pattern7_0);
5413                                                             let expr1_0 = constructor_vector_size(
5414                                                                 ctx, pattern2_0,
5415                                                             )?;
5416                                                             let expr2_0 = constructor_fcmeq0(
5417                                                                 ctx, expr0_0, &expr1_0,
5418                                                             )?;
5419                                                             let expr3_0 = constructor_not(
5420                                                                 ctx, expr2_0, &expr1_0,
5421                                                             )?;
5422                                                             let expr4_0 =
5423                                                                 C::value_reg(ctx, expr3_0);
5424                                                             let expr5_0 = C::output(ctx, expr4_0);
5425                                                             return Some(expr5_0);
5426                                                         }
5427                                                     }
5428                                                 }
5429                                             }
5430                                             &InstructionData::UnaryIeee64 {
5431                                                 opcode: ref pattern14_0,
5432                                                 imm: pattern14_1,
5433                                             } => {
5434                                                 if let &Opcode::F64const = pattern14_0 {
5435                                                     if let Some(pattern16_0) =
5436                                                         C::zero_value_f64(ctx, pattern14_1)
5437                                                     {
5438                                                         if let Some(pattern17_0) =
5439                                                             C::fcmp_zero_cond(ctx, pattern5_2)
5440                                                         {
5441                                                             // Rule at src/isa/aarch64/lower.isle line 1157.
5442                                                             let expr0_0 =
5443                                                                 C::put_in_reg(ctx, pattern7_0);
5444                                                             let expr1_0 = constructor_vector_size(
5445                                                                 ctx, pattern2_0,
5446                                                             )?;
5447                                                             let expr2_0 =
5448                                                                 constructor_float_cmp_zero(
5449                                                                     ctx,
5450                                                                     &pattern17_0,
5451                                                                     expr0_0,
5452                                                                     &expr1_0,
5453                                                                 )?;
5454                                                             let expr3_0 =
5455                                                                 C::value_reg(ctx, expr2_0);
5456                                                             let expr4_0 = C::output(ctx, expr3_0);
5457                                                             return Some(expr4_0);
5458                                                         }
5459                                                         if let Some(pattern17_0) =
5460                                                             C::fcmp_zero_cond_not_eq(
5461                                                                 ctx, pattern5_2,
5462                                                             )
5463                                                         {
5464                                                             // Rule at src/isa/aarch64/lower.isle line 1152.
5465                                                             let expr0_0 =
5466                                                                 C::put_in_reg(ctx, pattern7_0);
5467                                                             let expr1_0 = constructor_vector_size(
5468                                                                 ctx, pattern2_0,
5469                                                             )?;
5470                                                             let expr2_0 = constructor_fcmeq0(
5471                                                                 ctx, expr0_0, &expr1_0,
5472                                                             )?;
5473                                                             let expr3_0 = constructor_not(
5474                                                                 ctx, expr2_0, &expr1_0,
5475                                                             )?;
5476                                                             let expr4_0 =
5477                                                                 C::value_reg(ctx, expr3_0);
5478                                                             let expr5_0 = C::output(ctx, expr4_0);
5479                                                             return Some(expr5_0);
5480                                                         }
5481                                                     }
5482                                                 }
5483                                             }
5484                                             _ => {}
5485                                         }
5486                                     }
5487                                 }
5488                             }
5489                         }
5490                     }
5491                 }
5492                 &InstructionData::IntCompare {
5493                     opcode: ref pattern5_0,
5494                     args: ref pattern5_1,
5495                     cond: ref pattern5_2,
5496                 } => {
5497                     if let &Opcode::Icmp = pattern5_0 {
5498                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5499                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5500                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5501                             if let &InstructionData::Unary {
5502                                 opcode: ref pattern10_0,
5503                                 arg: pattern10_1,
5504                             } = &pattern9_0
5505                             {
5506                                 if let &Opcode::Splat = pattern10_0 {
5507                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5508                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5509                                         if let &InstructionData::UnaryImm {
5510                                             opcode: ref pattern14_0,
5511                                             imm: pattern14_1,
5512                                         } = &pattern13_0
5513                                         {
5514                                             if let &Opcode::Iconst = pattern14_0 {
5515                                                 if let Some(pattern16_0) =
5516                                                     C::zero_value(ctx, pattern14_1)
5517                                                 {
5518                                                     if let Some(pattern17_0) =
5519                                                         C::icmp_zero_cond(ctx, pattern5_2)
5520                                                     {
5521                                                         // Rule at src/isa/aarch64/lower.isle line 1189.
5522                                                         let expr0_0 =
5523                                                             C::put_in_reg(ctx, pattern7_1);
5524                                                         let expr1_0 = constructor_vector_size(
5525                                                             ctx, pattern2_0,
5526                                                         )?;
5527                                                         let expr2_0 =
5528                                                             constructor_int_cmp_zero_swap(
5529                                                                 ctx,
5530                                                                 &pattern17_0,
5531                                                                 expr0_0,
5532                                                                 &expr1_0,
5533                                                             )?;
5534                                                         let expr3_0 = C::value_reg(ctx, expr2_0);
5535                                                         let expr4_0 = C::output(ctx, expr3_0);
5536                                                         return Some(expr4_0);
5537                                                     }
5538                                                     if let Some(pattern17_0) =
5539                                                         C::icmp_zero_cond_not_eq(ctx, pattern5_2)
5540                                                     {
5541                                                         // Rule at src/isa/aarch64/lower.isle line 1184.
5542                                                         let expr0_0 =
5543                                                             C::put_in_reg(ctx, pattern7_1);
5544                                                         let expr1_0 = constructor_vector_size(
5545                                                             ctx, pattern2_0,
5546                                                         )?;
5547                                                         let expr2_0 = constructor_cmeq0(
5548                                                             ctx, expr0_0, &expr1_0,
5549                                                         )?;
5550                                                         let expr3_0 = constructor_not(
5551                                                             ctx, expr2_0, &expr1_0,
5552                                                         )?;
5553                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5554                                                         let expr5_0 = C::output(ctx, expr4_0);
5555                                                         return Some(expr5_0);
5556                                                     }
5557                                                 }
5558                                             }
5559                                         }
5560                                     }
5561                                 }
5562                             }
5563                         }
5564                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5565                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5566                             if let &InstructionData::Unary {
5567                                 opcode: ref pattern10_0,
5568                                 arg: pattern10_1,
5569                             } = &pattern9_0
5570                             {
5571                                 if let &Opcode::Splat = pattern10_0 {
5572                                     if let Some(pattern12_0) = C::def_inst(ctx, pattern10_1) {
5573                                         let pattern13_0 = C::inst_data(ctx, pattern12_0);
5574                                         if let &InstructionData::UnaryImm {
5575                                             opcode: ref pattern14_0,
5576                                             imm: pattern14_1,
5577                                         } = &pattern13_0
5578                                         {
5579                                             if let &Opcode::Iconst = pattern14_0 {
5580                                                 if let Some(pattern16_0) =
5581                                                     C::zero_value(ctx, pattern14_1)
5582                                                 {
5583                                                     if let Some(pattern17_0) =
5584                                                         C::icmp_zero_cond(ctx, pattern5_2)
5585                                                     {
5586                                                         // Rule at src/isa/aarch64/lower.isle line 1179.
5587                                                         let expr0_0 =
5588                                                             C::put_in_reg(ctx, pattern7_0);
5589                                                         let expr1_0 = constructor_vector_size(
5590                                                             ctx, pattern2_0,
5591                                                         )?;
5592                                                         let expr2_0 = constructor_int_cmp_zero(
5593                                                             ctx,
5594                                                             &pattern17_0,
5595                                                             expr0_0,
5596                                                             &expr1_0,
5597                                                         )?;
5598                                                         let expr3_0 = C::value_reg(ctx, expr2_0);
5599                                                         let expr4_0 = C::output(ctx, expr3_0);
5600                                                         return Some(expr4_0);
5601                                                     }
5602                                                     if let Some(pattern17_0) =
5603                                                         C::icmp_zero_cond_not_eq(ctx, pattern5_2)
5604                                                     {
5605                                                         // Rule at src/isa/aarch64/lower.isle line 1174.
5606                                                         let expr0_0 =
5607                                                             C::put_in_reg(ctx, pattern7_0);
5608                                                         let expr1_0 = constructor_vector_size(
5609                                                             ctx, pattern2_0,
5610                                                         )?;
5611                                                         let expr2_0 = constructor_cmeq0(
5612                                                             ctx, expr0_0, &expr1_0,
5613                                                         )?;
5614                                                         let expr3_0 = constructor_not(
5615                                                             ctx, expr2_0, &expr1_0,
5616                                                         )?;
5617                                                         let expr4_0 = C::value_reg(ctx, expr3_0);
5618                                                         let expr5_0 = C::output(ctx, expr4_0);
5619                                                         return Some(expr5_0);
5620                                                     }
5621                                                 }
5622                                             }
5623                                         }
5624                                     }
5625                                 }
5626                             }
5627                         }
5628                     }
5629                 }
5630                 _ => {}
5631             }
5632         }
5633         if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
5634             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5635             if let &InstructionData::Binary {
5636                 opcode: ref pattern5_0,
5637                 args: ref pattern5_1,
5638             } = &pattern4_0
5639             {
5640                 match pattern5_0 {
5641                     &Opcode::Rotl => {
5642                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5643                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5644                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5645                             if let &InstructionData::UnaryImm {
5646                                 opcode: ref pattern10_0,
5647                                 imm: pattern10_1,
5648                             } = &pattern9_0
5649                             {
5650                                 if let &Opcode::Iconst = pattern10_0 {
5651                                     let closure12 = || {
5652                                         return Some(pattern3_0);
5653                                     };
5654                                     if let Some(pattern12_0) = closure12() {
5655                                         if let Some(pattern13_0) =
5656                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5657                                         {
5658                                             // Rule at src/isa/aarch64/lower.isle line 843.
5659                                             let expr0_0 =
5660                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5661                                             let expr1_0 =
5662                                                 C::negate_imm_shift(ctx, pattern3_0, pattern13_0);
5663                                             let expr2_0 = constructor_small_rotr_imm(
5664                                                 ctx, pattern3_0, expr0_0, expr1_0,
5665                                             )?;
5666                                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5667                                             return Some(expr3_0);
5668                                         }
5669                                     }
5670                                 }
5671                             }
5672                         }
5673                         // Rule at src/isa/aarch64/lower.isle line 838.
5674                         let expr0_0: Type = I32;
5675                         let expr1_0 = C::zero_reg(ctx);
5676                         let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5677                         let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
5678                         let expr4_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5679                         let expr5_0 = constructor_small_rotr(ctx, pattern3_0, expr4_0, expr3_0)?;
5680                         let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
5681                         return Some(expr6_0);
5682                     }
5683                     &Opcode::Rotr => {
5684                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5685                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5686                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5687                             if let &InstructionData::UnaryImm {
5688                                 opcode: ref pattern10_0,
5689                                 imm: pattern10_1,
5690                             } = &pattern9_0
5691                             {
5692                                 if let &Opcode::Iconst = pattern10_0 {
5693                                     let closure12 = || {
5694                                         return Some(pattern3_0);
5695                                     };
5696                                     if let Some(pattern12_0) = closure12() {
5697                                         if let Some(pattern13_0) =
5698                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5699                                         {
5700                                             // Rule at src/isa/aarch64/lower.isle line 903.
5701                                             let expr0_0 =
5702                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5703                                             let expr1_0 = constructor_small_rotr_imm(
5704                                                 ctx,
5705                                                 pattern3_0,
5706                                                 expr0_0,
5707                                                 pattern13_0,
5708                                             )?;
5709                                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5710                                             return Some(expr2_0);
5711                                         }
5712                                     }
5713                                 }
5714                             }
5715                         }
5716                         // Rule at src/isa/aarch64/lower.isle line 891.
5717                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5718                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5719                         let expr2_0 = constructor_small_rotr(ctx, pattern3_0, expr0_0, expr1_0)?;
5720                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5721                         return Some(expr3_0);
5722                     }
5723                     _ => {}
5724                 }
5725             }
5726         }
5727         if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
5728             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5729             if let &InstructionData::Binary {
5730                 opcode: ref pattern5_0,
5731                 args: ref pattern5_1,
5732             } = &pattern4_0
5733             {
5734                 match pattern5_0 {
5735                     &Opcode::Umulhi => {
5736                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5737                         // Rule at src/isa/aarch64/lower.isle line 370.
5738                         let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5739                         let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?;
5740                         let expr2_0 = C::zero_reg(ctx);
5741                         let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
5742                         let expr4_0: Type = I64;
5743                         let expr5_0 = C::ty_bits(ctx, pattern3_0);
5744                         let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
5745                         let expr7_0 = constructor_lsr_imm(ctx, expr4_0, expr3_0, expr6_0)?;
5746                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
5747                         return Some(expr8_0);
5748                     }
5749                     &Opcode::Smulhi => {
5750                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5751                         // Rule at src/isa/aarch64/lower.isle line 358.
5752                         let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5753                         let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?;
5754                         let expr2_0 = C::zero_reg(ctx);
5755                         let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
5756                         let expr4_0: Type = I64;
5757                         let expr5_0 = C::ty_bits(ctx, pattern3_0);
5758                         let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
5759                         let expr7_0 = constructor_asr_imm(ctx, expr4_0, expr3_0, expr6_0)?;
5760                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
5761                         return Some(expr8_0);
5762                     }
5763                     &Opcode::Band => {
5764                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5765                         // Rule at src/isa/aarch64/lower.isle line 583.
5766                         let expr0_0 = ALUOp::And;
5767                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5768                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5769                         )?;
5770                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5771                         return Some(expr2_0);
5772                     }
5773                     &Opcode::Bor => {
5774                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5775                         // Rule at src/isa/aarch64/lower.isle line 596.
5776                         let expr0_0 = ALUOp::Orr;
5777                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5778                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5779                         )?;
5780                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5781                         return Some(expr2_0);
5782                     }
5783                     &Opcode::Bxor => {
5784                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5785                         // Rule at src/isa/aarch64/lower.isle line 609.
5786                         let expr0_0 = ALUOp::Eor;
5787                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5788                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5789                         )?;
5790                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5791                         return Some(expr2_0);
5792                     }
5793                     &Opcode::BandNot => {
5794                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5795                         // Rule at src/isa/aarch64/lower.isle line 622.
5796                         let expr0_0 = ALUOp::AndNot;
5797                         let expr1_0 = constructor_alu_rs_imm_logic(
5798                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5799                         )?;
5800                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5801                         return Some(expr2_0);
5802                     }
5803                     &Opcode::BorNot => {
5804                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5805                         // Rule at src/isa/aarch64/lower.isle line 635.
5806                         let expr0_0 = ALUOp::OrrNot;
5807                         let expr1_0 = constructor_alu_rs_imm_logic(
5808                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5809                         )?;
5810                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5811                         return Some(expr2_0);
5812                     }
5813                     &Opcode::BxorNot => {
5814                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5815                         // Rule at src/isa/aarch64/lower.isle line 645.
5816                         let expr0_0 = ALUOp::EorNot;
5817                         let expr1_0: Type = I32;
5818                         let expr2_0 = constructor_alu_rs_imm_logic(
5819                             ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
5820                         )?;
5821                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5822                         return Some(expr3_0);
5823                     }
5824                     &Opcode::Ishl => {
5825                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5826                         // Rule at src/isa/aarch64/lower.isle line 656.
5827                         let expr0_0 = ALUOp::Lsl;
5828                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
5829                         let expr2_0 =
5830                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5831                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5832                         return Some(expr3_0);
5833                     }
5834                     &Opcode::Ushr => {
5835                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5836                         // Rule at src/isa/aarch64/lower.isle line 740.
5837                         let expr0_0 = ALUOp::Lsr;
5838                         let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5839                         let expr2_0 =
5840                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5841                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5842                         return Some(expr3_0);
5843                     }
5844                     &Opcode::Sshr => {
5845                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5846                         // Rule at src/isa/aarch64/lower.isle line 787.
5847                         let expr0_0 = ALUOp::Asr;
5848                         let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
5849                         let expr2_0 =
5850                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5851                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5852                         return Some(expr3_0);
5853                     }
5854                     _ => {}
5855                 }
5856             }
5857         }
5858         if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
5859             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5860             match &pattern4_0 {
5861                 &InstructionData::Binary {
5862                     opcode: ref pattern5_0,
5863                     args: ref pattern5_1,
5864                 } => {
5865                     match pattern5_0 {
5866                         &Opcode::Iadd => {
5867                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5868                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5869                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5870                                 match &pattern9_0 {
5871                                     &InstructionData::UnaryImm {
5872                                         opcode: ref pattern10_0,
5873                                         imm: pattern10_1,
5874                                     } => {
5875                                         if let &Opcode::Iconst = pattern10_0 {
5876                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5877                                             if let Some(pattern13_0) =
5878                                                 C::imm12_from_u64(ctx, pattern12_0)
5879                                             {
5880                                                 // Rule at src/isa/aarch64/lower.isle line 37.
5881                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5882                                                 let expr1_0 = constructor_add_imm(
5883                                                     ctx,
5884                                                     pattern3_0,
5885                                                     expr0_0,
5886                                                     pattern13_0,
5887                                                 )?;
5888                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5889                                                 return Some(expr2_0);
5890                                             }
5891                                             if let Some(pattern13_0) =
5892                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5893                                             {
5894                                                 // Rule at src/isa/aarch64/lower.isle line 45.
5895                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5896                                                 let expr1_0 = constructor_sub_imm(
5897                                                     ctx,
5898                                                     pattern3_0,
5899                                                     expr0_0,
5900                                                     pattern13_0,
5901                                                 )?;
5902                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5903                                                 return Some(expr2_0);
5904                                             }
5905                                         }
5906                                     }
5907                                     &InstructionData::Binary {
5908                                         opcode: ref pattern10_0,
5909                                         args: ref pattern10_1,
5910                                     } => {
5911                                         match pattern10_0 {
5912                                             &Opcode::Imul => {
5913                                                 let (pattern12_0, pattern12_1) =
5914                                                     C::unpack_value_array_2(ctx, pattern10_1);
5915                                                 // Rule at src/isa/aarch64/lower.isle line 70.
5916                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5917                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5918                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5919                                                 let expr3_0 = constructor_madd(
5920                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5921                                                 )?;
5922                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5923                                                 return Some(expr4_0);
5924                                             }
5925                                             &Opcode::Ishl => {
5926                                                 let (pattern12_0, pattern12_1) =
5927                                                     C::unpack_value_array_2(ctx, pattern10_1);
5928                                                 if let Some(pattern13_0) =
5929                                                     C::def_inst(ctx, pattern12_1)
5930                                                 {
5931                                                     let pattern14_0 =
5932                                                         C::inst_data(ctx, pattern13_0);
5933                                                     if let &InstructionData::UnaryImm {
5934                                                         opcode: ref pattern15_0,
5935                                                         imm: pattern15_1,
5936                                                     } = &pattern14_0
5937                                                     {
5938                                                         if let &Opcode::Iconst = pattern15_0 {
5939                                                             let closure17 = || {
5940                                                                 return Some(pattern3_0);
5941                                                             };
5942                                                             if let Some(pattern17_0) = closure17() {
5943                                                                 if let Some(pattern18_0) =
5944                                                                     C::lshl_from_imm64(
5945                                                                         ctx,
5946                                                                         pattern15_1,
5947                                                                         pattern17_0,
5948                                                                     )
5949                                                                 {
5950                                                                     // Rule at src/isa/aarch64/lower.isle line 62.
5951                                                                     let expr0_0 = C::put_in_reg(
5952                                                                         ctx, pattern7_1,
5953                                                                     );
5954                                                                     let expr1_0 = C::put_in_reg(
5955                                                                         ctx,
5956                                                                         pattern12_0,
5957                                                                     );
5958                                                                     let expr2_0 =
5959                                                                         constructor_add_shift(
5960                                                                             ctx,
5961                                                                             pattern3_0,
5962                                                                             expr0_0,
5963                                                                             expr1_0,
5964                                                                             pattern18_0,
5965                                                                         )?;
5966                                                                     let expr3_0 =
5967                                                                         constructor_output_reg(
5968                                                                             ctx, expr2_0,
5969                                                                         )?;
5970                                                                     return Some(expr3_0);
5971                                                                 }
5972                                                             }
5973                                                         }
5974                                                     }
5975                                                 }
5976                                             }
5977                                             _ => {}
5978                                         }
5979                                     }
5980                                     _ => {}
5981                                 }
5982                             }
5983                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0)
5984                             {
5985                                 // Rule at src/isa/aarch64/lower.isle line 53.
5986                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5987                                 let expr1_0 =
5988                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5989                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5990                                 return Some(expr2_0);
5991                             }
5992                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5993                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5994                                 match &pattern9_0 {
5995                                     &InstructionData::UnaryImm {
5996                                         opcode: ref pattern10_0,
5997                                         imm: pattern10_1,
5998                                     } => {
5999                                         if let &Opcode::Iconst = pattern10_0 {
6000                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
6001                                             if let Some(pattern13_0) =
6002                                                 C::imm12_from_u64(ctx, pattern12_0)
6003                                             {
6004                                                 // Rule at src/isa/aarch64/lower.isle line 34.
6005                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6006                                                 let expr1_0 = constructor_add_imm(
6007                                                     ctx,
6008                                                     pattern3_0,
6009                                                     expr0_0,
6010                                                     pattern13_0,
6011                                                 )?;
6012                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6013                                                 return Some(expr2_0);
6014                                             }
6015                                             if let Some(pattern13_0) =
6016                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
6017                                             {
6018                                                 // Rule at src/isa/aarch64/lower.isle line 42.
6019                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6020                                                 let expr1_0 = constructor_sub_imm(
6021                                                     ctx,
6022                                                     pattern3_0,
6023                                                     expr0_0,
6024                                                     pattern13_0,
6025                                                 )?;
6026                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6027                                                 return Some(expr2_0);
6028                                             }
6029                                         }
6030                                     }
6031                                     &InstructionData::Binary {
6032                                         opcode: ref pattern10_0,
6033                                         args: ref pattern10_1,
6034                                     } => {
6035                                         match pattern10_0 {
6036                                             &Opcode::Imul => {
6037                                                 let (pattern12_0, pattern12_1) =
6038                                                     C::unpack_value_array_2(ctx, pattern10_1);
6039                                                 // Rule at src/isa/aarch64/lower.isle line 67.
6040                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
6041                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
6042                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
6043                                                 let expr3_0 = constructor_madd(
6044                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
6045                                                 )?;
6046                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6047                                                 return Some(expr4_0);
6048                                             }
6049                                             &Opcode::Ishl => {
6050                                                 let (pattern12_0, pattern12_1) =
6051                                                     C::unpack_value_array_2(ctx, pattern10_1);
6052                                                 if let Some(pattern13_0) =
6053                                                     C::def_inst(ctx, pattern12_1)
6054                                                 {
6055                                                     let pattern14_0 =
6056                                                         C::inst_data(ctx, pattern13_0);
6057                                                     if let &InstructionData::UnaryImm {
6058                                                         opcode: ref pattern15_0,
6059                                                         imm: pattern15_1,
6060                                                     } = &pattern14_0
6061                                                     {
6062                                                         if let &Opcode::Iconst = pattern15_0 {
6063                                                             let closure17 = || {
6064                                                                 return Some(pattern3_0);
6065                                                             };
6066                                                             if let Some(pattern17_0) = closure17() {
6067                                                                 if let Some(pattern18_0) =
6068                                                                     C::lshl_from_imm64(
6069                                                                         ctx,
6070                                                                         pattern15_1,
6071                                                                         pattern17_0,
6072                                                                     )
6073                                                                 {
6074                                                                     // Rule at src/isa/aarch64/lower.isle line 58.
6075                                                                     let expr0_0 = C::put_in_reg(
6076                                                                         ctx, pattern7_0,
6077                                                                     );
6078                                                                     let expr1_0 = C::put_in_reg(
6079                                                                         ctx,
6080                                                                         pattern12_0,
6081                                                                     );
6082                                                                     let expr2_0 =
6083                                                                         constructor_add_shift(
6084                                                                             ctx,
6085                                                                             pattern3_0,
6086                                                                             expr0_0,
6087                                                                             expr1_0,
6088                                                                             pattern18_0,
6089                                                                         )?;
6090                                                                     let expr3_0 =
6091                                                                         constructor_output_reg(
6092                                                                             ctx, expr2_0,
6093                                                                         )?;
6094                                                                     return Some(expr3_0);
6095                                                                 }
6096                                                             }
6097                                                         }
6098                                                     }
6099                                                 }
6100                                             }
6101                                             _ => {}
6102                                         }
6103                                     }
6104                                     _ => {}
6105                                 }
6106                             }
6107                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
6108                             {
6109                                 // Rule at src/isa/aarch64/lower.isle line 50.
6110                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6111                                 let expr1_0 =
6112                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6113                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6114                                 return Some(expr2_0);
6115                             }
6116                             // Rule at src/isa/aarch64/lower.isle line 30.
6117                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6118                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6119                             let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, expr1_0)?;
6120                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6121                             return Some(expr3_0);
6122                         }
6123                         &Opcode::Isub => {
6124                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6125                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6126                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6127                                 match &pattern9_0 {
6128                                     &InstructionData::UnaryImm {
6129                                         opcode: ref pattern10_0,
6130                                         imm: pattern10_1,
6131                                     } => {
6132                                         if let &Opcode::Iconst = pattern10_0 {
6133                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
6134                                             if let Some(pattern13_0) =
6135                                                 C::imm12_from_u64(ctx, pattern12_0)
6136                                             {
6137                                                 // Rule at src/isa/aarch64/lower.isle line 105.
6138                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6139                                                 let expr1_0 = constructor_sub_imm(
6140                                                     ctx,
6141                                                     pattern3_0,
6142                                                     expr0_0,
6143                                                     pattern13_0,
6144                                                 )?;
6145                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6146                                                 return Some(expr2_0);
6147                                             }
6148                                             if let Some(pattern13_0) =
6149                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
6150                                             {
6151                                                 // Rule at src/isa/aarch64/lower.isle line 110.
6152                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6153                                                 let expr1_0 = constructor_add_imm(
6154                                                     ctx,
6155                                                     pattern3_0,
6156                                                     expr0_0,
6157                                                     pattern13_0,
6158                                                 )?;
6159                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6160                                                 return Some(expr2_0);
6161                                             }
6162                                         }
6163                                     }
6164                                     &InstructionData::Binary {
6165                                         opcode: ref pattern10_0,
6166                                         args: ref pattern10_1,
6167                                     } => {
6168                                         if let &Opcode::Ishl = pattern10_0 {
6169                                             let (pattern12_0, pattern12_1) =
6170                                                 C::unpack_value_array_2(ctx, pattern10_1);
6171                                             if let Some(pattern13_0) = C::def_inst(ctx, pattern12_1)
6172                                             {
6173                                                 let pattern14_0 = C::inst_data(ctx, pattern13_0);
6174                                                 if let &InstructionData::UnaryImm {
6175                                                     opcode: ref pattern15_0,
6176                                                     imm: pattern15_1,
6177                                                 } = &pattern14_0
6178                                                 {
6179                                                     if let &Opcode::Iconst = pattern15_0 {
6180                                                         let closure17 = || {
6181                                                             return Some(pattern3_0);
6182                                                         };
6183                                                         if let Some(pattern17_0) = closure17() {
6184                                                             if let Some(pattern18_0) =
6185                                                                 C::lshl_from_imm64(
6186                                                                     ctx,
6187                                                                     pattern15_1,
6188                                                                     pattern17_0,
6189                                                                 )
6190                                                             {
6191                                                                 // Rule at src/isa/aarch64/lower.isle line 120.
6192                                                                 let expr0_0 =
6193                                                                     C::put_in_reg(ctx, pattern7_0);
6194                                                                 let expr1_0 =
6195                                                                     C::put_in_reg(ctx, pattern12_0);
6196                                                                 let expr2_0 =
6197                                                                     constructor_sub_shift(
6198                                                                         ctx,
6199                                                                         pattern3_0,
6200                                                                         expr0_0,
6201                                                                         expr1_0,
6202                                                                         pattern18_0,
6203                                                                     )?;
6204                                                                 let expr3_0 =
6205                                                                     constructor_output_reg(
6206                                                                         ctx, expr2_0,
6207                                                                     )?;
6208                                                                 return Some(expr3_0);
6209                                                             }
6210                                                         }
6211                                                     }
6212                                                 }
6213                                             }
6214                                         }
6215                                     }
6216                                     _ => {}
6217                                 }
6218                             }
6219                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
6220                             {
6221                                 // Rule at src/isa/aarch64/lower.isle line 115.
6222                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6223                                 let expr1_0 =
6224                                     constructor_sub_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
6225                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6226                                 return Some(expr2_0);
6227                             }
6228                             // Rule at src/isa/aarch64/lower.isle line 101.
6229                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6230                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6231                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
6232                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6233                             return Some(expr3_0);
6234                         }
6235                         &Opcode::Imul => {
6236                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6237                             // Rule at src/isa/aarch64/lower.isle line 179.
6238                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6239                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6240                             let expr2_0 = C::zero_reg(ctx);
6241                             let expr3_0 =
6242                                 constructor_madd(ctx, pattern3_0, expr0_0, expr1_0, expr2_0)?;
6243                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6244                             return Some(expr4_0);
6245                         }
6246                         &Opcode::Udiv => {
6247                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6248                             // Rule at src/isa/aarch64/lower.isle line 384.
6249                             let expr0_0: Type = I64;
6250                             let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
6251                             let expr2_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
6252                             let expr3_0 = constructor_a64_udiv(ctx, expr0_0, expr1_0, expr2_0)?;
6253                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6254                             return Some(expr4_0);
6255                         }
6256                         &Opcode::Sdiv => {
6257                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6258                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
6259                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
6260                                 if let &InstructionData::UnaryImm {
6261                                     opcode: ref pattern10_0,
6262                                     imm: pattern10_1,
6263                                 } = &pattern9_0
6264                                 {
6265                                     if let &Opcode::Iconst = pattern10_0 {
6266                                         if let Some(pattern12_0) =
6267                                             C::safe_divisor_from_imm64(ctx, pattern10_1)
6268                                         {
6269                                             // Rule at src/isa/aarch64/lower.isle line 430.
6270                                             let expr0_0: Type = I64;
6271                                             let expr1_0 =
6272                                                 constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6273                                             let expr2_0 =
6274                                                 constructor_imm(ctx, pattern3_0, pattern12_0)?;
6275                                             let expr3_0 = constructor_a64_sdiv(
6276                                                 ctx, expr0_0, expr1_0, expr2_0,
6277                                             )?;
6278                                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6279                                             return Some(expr4_0);
6280                                         }
6281                                     }
6282                                 }
6283                             }
6284                             // Rule at src/isa/aarch64/lower.isle line 417.
6285                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6286                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
6287                             let expr2_0 = constructor_trap_if_div_overflow(
6288                                 ctx, pattern3_0, expr0_0, expr1_0,
6289                             )?;
6290                             let expr3_0: Type = I64;
6291                             let expr4_0 = constructor_a64_sdiv(ctx, expr3_0, expr2_0, expr1_0)?;
6292                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6293                             return Some(expr5_0);
6294                         }
6295                         &Opcode::Urem => {
6296                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6297                             // Rule at src/isa/aarch64/lower.isle line 458.
6298                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
6299                             let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
6300                             let expr2_0: Type = I64;
6301                             let expr3_0 = constructor_a64_udiv(ctx, expr2_0, expr0_0, expr1_0)?;
6302                             let expr4_0 = constructor_msub64(ctx, expr3_0, expr1_0, expr0_0)?;
6303                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6304                             return Some(expr5_0);
6305                         }
6306                         &Opcode::Srem => {
6307                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6308                             // Rule at src/isa/aarch64/lower.isle line 465.
6309                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
6310                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
6311                             let expr2_0: Type = I64;
6312                             let expr3_0 = constructor_a64_sdiv(ctx, expr2_0, expr0_0, expr1_0)?;
6313                             let expr4_0 = constructor_msub64(ctx, expr3_0, expr1_0, expr0_0)?;
6314                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6315                             return Some(expr5_0);
6316                         }
6317                         _ => {}
6318                     }
6319                 }
6320                 &InstructionData::Unary {
6321                     opcode: ref pattern5_0,
6322                     arg: pattern5_1,
6323                 } => {
6324                     match pattern5_0 {
6325                         &Opcode::Ineg => {
6326                             // Rule at src/isa/aarch64/lower.isle line 169.
6327                             let expr0_0 = C::zero_reg(ctx);
6328                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6329                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
6330                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6331                             return Some(expr3_0);
6332                         }
6333                         &Opcode::Bnot => {
6334                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6335                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6336                                 if let &InstructionData::Binary {
6337                                     opcode: ref pattern9_0,
6338                                     args: ref pattern9_1,
6339                                 } = &pattern8_0
6340                                 {
6341                                     if let &Opcode::Ishl = pattern9_0 {
6342                                         let (pattern11_0, pattern11_1) =
6343                                             C::unpack_value_array_2(ctx, pattern9_1);
6344                                         if let Some(pattern12_0) = C::def_inst(ctx, pattern11_1) {
6345                                             let pattern13_0 = C::inst_data(ctx, pattern12_0);
6346                                             if let &InstructionData::UnaryImm {
6347                                                 opcode: ref pattern14_0,
6348                                                 imm: pattern14_1,
6349                                             } = &pattern13_0
6350                                             {
6351                                                 if let &Opcode::Iconst = pattern14_0 {
6352                                                     let closure16 = || {
6353                                                         return Some(pattern3_0);
6354                                                     };
6355                                                     if let Some(pattern16_0) = closure16() {
6356                                                         if let Some(pattern17_0) =
6357                                                             C::lshl_from_imm64(
6358                                                                 ctx,
6359                                                                 pattern14_1,
6360                                                                 pattern16_0,
6361                                                             )
6362                                                         {
6363                                                             // Rule at src/isa/aarch64/lower.isle line 564.
6364                                                             let expr0_0 = C::zero_reg(ctx);
6365                                                             let expr1_0 =
6366                                                                 C::put_in_reg(ctx, pattern11_0);
6367                                                             let expr2_0 =
6368                                                                 constructor_orr_not_shift(
6369                                                                     ctx,
6370                                                                     pattern3_0,
6371                                                                     expr0_0,
6372                                                                     expr1_0,
6373                                                                     pattern17_0,
6374                                                                 )?;
6375                                                             let expr3_0 = constructor_output_reg(
6376                                                                 ctx, expr2_0,
6377                                                             )?;
6378                                                             return Some(expr3_0);
6379                                                         }
6380                                                     }
6381                                                 }
6382                                             }
6383                                         }
6384                                     }
6385                                 }
6386                             }
6387                             // Rule at src/isa/aarch64/lower.isle line 559.
6388                             let expr0_0 = C::zero_reg(ctx);
6389                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
6390                             let expr2_0 = constructor_orr_not(ctx, pattern3_0, expr0_0, expr1_0)?;
6391                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6392                             return Some(expr3_0);
6393                         }
6394                         &Opcode::Uextend => {
6395                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6396                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6397                                 if let &InstructionData::BinaryImm8 {
6398                                     opcode: ref pattern9_0,
6399                                     arg: pattern9_1,
6400                                     imm: pattern9_2,
6401                                 } = &pattern8_0
6402                                 {
6403                                     if let &Opcode::Extractlane = pattern9_0 {
6404                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6405                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6406                                         // Rule at src/isa/aarch64/lower.isle line 481.
6407                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6408                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6409                                         let expr2_0 = constructor_mov_from_vec(
6410                                             ctx,
6411                                             expr0_0,
6412                                             pattern12_0,
6413                                             &expr1_0,
6414                                         )?;
6415                                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6416                                         return Some(expr3_0);
6417                                     }
6418                                 }
6419                             }
6420                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6421                             if let Some(pattern8_0) = C::sinkable_atomic_load(ctx, pattern5_1) {
6422                                 // Rule at src/isa/aarch64/lower.isle line 488.
6423                                 let expr0_0 = C::sink_atomic_load(ctx, &pattern8_0);
6424                                 let expr1_0 = constructor_load_acquire(ctx, pattern7_0, expr0_0)?;
6425                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
6426                                 return Some(expr2_0);
6427                             }
6428                             // Rule at src/isa/aarch64/lower.isle line 476.
6429                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6430                             let expr1_0: bool = false;
6431                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6432                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6433                             let expr4_0 =
6434                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6435                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6436                             return Some(expr5_0);
6437                         }
6438                         &Opcode::Sextend => {
6439                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
6440                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
6441                                 if let &InstructionData::BinaryImm8 {
6442                                     opcode: ref pattern9_0,
6443                                     arg: pattern9_1,
6444                                     imm: pattern9_2,
6445                                 } = &pattern8_0
6446                                 {
6447                                     if let &Opcode::Extractlane = pattern9_0 {
6448                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
6449                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
6450                                         // Rule at src/isa/aarch64/lower.isle line 513.
6451                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
6452                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
6453                                         let expr2_0 = constructor_size_from_ty(ctx, pattern3_0)?;
6454                                         let expr3_0 = constructor_mov_from_vec_signed(
6455                                             ctx,
6456                                             expr0_0,
6457                                             pattern12_0,
6458                                             &expr1_0,
6459                                             &expr2_0,
6460                                         )?;
6461                                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6462                                         return Some(expr4_0);
6463                                     }
6464                                 }
6465                             }
6466                             let pattern7_0 = C::value_type(ctx, pattern5_1);
6467                             // Rule at src/isa/aarch64/lower.isle line 508.
6468                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6469                             let expr1_0: bool = true;
6470                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
6471                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
6472                             let expr4_0 =
6473                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
6474                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6475                             return Some(expr5_0);
6476                         }
6477                         _ => {}
6478                     }
6479                 }
6480                 _ => {}
6481             }
6482         }
6483         if let Some(pattern3_0) = C::ty_vec128(ctx, pattern2_0) {
6484             let pattern4_0 = C::inst_data(ctx, pattern0_0);
6485             match &pattern4_0 {
6486                 &InstructionData::Binary {
6487                     opcode: ref pattern5_0,
6488                     args: ref pattern5_1,
6489                 } => {
6490                     match pattern5_0 {
6491                         &Opcode::UaddSat => {
6492                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6493                             // Rule at src/isa/aarch64/lower.isle line 148.
6494                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6495                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6496                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6497                             let expr3_0 = constructor_uqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6498                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6499                             return Some(expr4_0);
6500                         }
6501                         &Opcode::SaddSat => {
6502                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6503                             // Rule at src/isa/aarch64/lower.isle line 153.
6504                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6505                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6506                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6507                             let expr3_0 = constructor_sqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
6508                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6509                             return Some(expr4_0);
6510                         }
6511                         &Opcode::UsubSat => {
6512                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6513                             // Rule at src/isa/aarch64/lower.isle line 158.
6514                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6515                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6516                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6517                             let expr3_0 = constructor_uqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6518                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6519                             return Some(expr4_0);
6520                         }
6521                         &Opcode::SsubSat => {
6522                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6523                             // Rule at src/isa/aarch64/lower.isle line 163.
6524                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6525                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6526                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6527                             let expr3_0 = constructor_sqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
6528                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6529                             return Some(expr4_0);
6530                         }
6531                         &Opcode::Band => {
6532                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6533                             // Rule at src/isa/aarch64/lower.isle line 591.
6534                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6535                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6536                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6537                             let expr3_0 = constructor_and_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6538                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6539                             return Some(expr4_0);
6540                         }
6541                         &Opcode::Bor => {
6542                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6543                             // Rule at src/isa/aarch64/lower.isle line 604.
6544                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6545                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6546                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6547                             let expr3_0 = constructor_orr_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6548                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6549                             return Some(expr4_0);
6550                         }
6551                         &Opcode::Bxor => {
6552                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6553                             // Rule at src/isa/aarch64/lower.isle line 617.
6554                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6555                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6556                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6557                             let expr3_0 = constructor_eor_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6558                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6559                             return Some(expr4_0);
6560                         }
6561                         &Opcode::BandNot => {
6562                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6563                             // Rule at src/isa/aarch64/lower.isle line 630.
6564                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
6565                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6566                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6567                             let expr3_0 = constructor_bic_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
6568                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6569                             return Some(expr4_0);
6570                         }
6571                         &Opcode::Ishl => {
6572                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6573                             // Rule at src/isa/aarch64/lower.isle line 694.
6574                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6575                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
6576                             let expr2_0 = constructor_vec_dup(ctx, expr1_0, &expr0_0)?;
6577                             let expr3_0 = C::put_in_reg(ctx, pattern7_0);
6578                             let expr4_0 = constructor_sshl(ctx, expr3_0, expr2_0, &expr0_0)?;
6579                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
6580                             return Some(expr5_0);
6581                         }
6582                         &Opcode::Ushr => {
6583                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6584                             // Rule at src/isa/aarch64/lower.isle line 752.
6585                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6586                             let expr1_0: Type = I32;
6587                             let expr2_0 = C::zero_reg(ctx);
6588                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6589                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6590                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6591                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6592                             let expr7_0 = constructor_ushl(ctx, expr6_0, expr5_0, &expr0_0)?;
6593                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6594                             return Some(expr8_0);
6595                         }
6596                         &Opcode::Sshr => {
6597                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6598                             // Rule at src/isa/aarch64/lower.isle line 801.
6599                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6600                             let expr1_0: Type = I32;
6601                             let expr2_0 = C::zero_reg(ctx);
6602                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6603                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6604                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6605                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6606                             let expr7_0 = constructor_sshl(ctx, expr6_0, expr5_0, &expr0_0)?;
6607                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6608                             return Some(expr8_0);
6609                         }
6610                         _ => {}
6611                     }
6612                 }
6613                 &InstructionData::Unary {
6614                     opcode: ref pattern5_0,
6615                     arg: pattern5_1,
6616                 } => {
6617                     match pattern5_0 {
6618                         &Opcode::Ineg => {
6619                             // Rule at src/isa/aarch64/lower.isle line 173.
6620                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6621                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6622                             let expr2_0 = constructor_neg(ctx, expr0_0, &expr1_0)?;
6623                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6624                             return Some(expr3_0);
6625                         }
6626                         &Opcode::Bnot => {
6627                             // Rule at src/isa/aarch64/lower.isle line 578.
6628                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6629                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6630                             let expr2_0 = constructor_not(ctx, expr0_0, &expr1_0)?;
6631                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6632                             return Some(expr3_0);
6633                         }
6634                         _ => {}
6635                     }
6636                 }
6637                 _ => {}
6638             }
6639             if let Some(()) = C::not_i64x2(ctx, pattern3_0) {
6640                 let pattern5_0 = C::inst_data(ctx, pattern0_0);
6641                 if let &InstructionData::Binary {
6642                     opcode: ref pattern6_0,
6643                     args: ref pattern6_1,
6644                 } = &pattern5_0
6645                 {
6646                     if let &Opcode::Imul = pattern6_0 {
6647                         let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
6648                         // Rule at src/isa/aarch64/lower.isle line 211.
6649                         let expr0_0 = C::put_in_reg(ctx, pattern8_0);
6650                         let expr1_0 = C::put_in_reg(ctx, pattern8_1);
6651                         let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6652                         let expr3_0 = constructor_mul(ctx, expr0_0, expr1_0, &expr2_0)?;
6653                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6654                         return Some(expr4_0);
6655                     }
6656                 }
6657             }
6658         }
6659     }
6660     return None;
6661 }
6662 
6663 // Generated as internal constructor for term put_nonzero_in_reg_zext64.
6664 pub fn constructor_put_nonzero_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6665     let pattern0_0 = arg0;
6666     let pattern1_0 = C::value_type(ctx, pattern0_0);
6667     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6668         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6669         if let &InstructionData::UnaryImm {
6670             opcode: ref pattern4_0,
6671             imm: pattern4_1,
6672         } = &pattern3_0
6673         {
6674             if let &Opcode::Iconst = pattern4_0 {
6675                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6676                     // Rule at src/isa/aarch64/lower.isle line 394.
6677                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6678                     return Some(expr0_0);
6679                 }
6680             }
6681         }
6682     }
6683     // Rule at src/isa/aarch64/lower.isle line 389.
6684     let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern0_0)?;
6685     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6686     return Some(expr1_0);
6687 }
6688 
6689 // Generated as internal constructor for term put_nonzero_in_reg_sext64.
6690 pub fn constructor_put_nonzero_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6691     let pattern0_0 = arg0;
6692     let pattern1_0 = C::value_type(ctx, pattern0_0);
6693     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6694         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6695         if let &InstructionData::UnaryImm {
6696             opcode: ref pattern4_0,
6697             imm: pattern4_1,
6698         } = &pattern3_0
6699         {
6700             if let &Opcode::Iconst = pattern4_0 {
6701                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6702                     // Rule at src/isa/aarch64/lower.isle line 440.
6703                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6704                     return Some(expr0_0);
6705                 }
6706             }
6707         }
6708     }
6709     // Rule at src/isa/aarch64/lower.isle line 435.
6710     let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern0_0)?;
6711     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6712     return Some(expr1_0);
6713 }
6714 
6715 // Generated as internal constructor for term lower_shl128.
6716 pub fn constructor_lower_shl128<C: Context>(
6717     ctx: &mut C,
6718     arg0: ValueRegs,
6719     arg1: Reg,
6720 ) -> Option<ValueRegs> {
6721     let pattern0_0 = arg0;
6722     let pattern1_0 = arg1;
6723     // Rule at src/isa/aarch64/lower.isle line 677.
6724     let expr0_0: usize = 0;
6725     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6726     let expr2_0: usize = 1;
6727     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6728     let expr4_0: Type = I64;
6729     let expr5_0 = constructor_lsl(ctx, expr4_0, expr1_0, pattern1_0)?;
6730     let expr6_0: Type = I64;
6731     let expr7_0 = constructor_lsl(ctx, expr6_0, expr3_0, pattern1_0)?;
6732     let expr8_0: Type = I32;
6733     let expr9_0 = C::zero_reg(ctx);
6734     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6735     let expr11_0: Type = I64;
6736     let expr12_0: Type = I64;
6737     let expr13_0: u8 = 1;
6738     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6739     let expr15_0 = constructor_lsr_imm(ctx, expr12_0, expr1_0, expr14_0)?;
6740     let expr16_0 = constructor_lsr(ctx, expr11_0, expr15_0, expr10_0)?;
6741     let expr17_0: Type = I64;
6742     let expr18_0 = constructor_orr(ctx, expr17_0, expr7_0, expr16_0)?;
6743     let expr19_0: Type = I64;
6744     let expr20_0: Type = I64;
6745     let expr21_0: u64 = 64;
6746     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6747     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6748     let expr24_0 = Cond::Ne;
6749     let expr25_0 = C::zero_reg(ctx);
6750     let expr26_0 = constructor_csel(ctx, &expr24_0, expr25_0, expr5_0)?;
6751     let expr27_0 = Cond::Ne;
6752     let expr28_0 = constructor_csel(ctx, &expr27_0, expr5_0, expr18_0)?;
6753     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr26_0, &expr28_0)?;
6754     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6755     return Some(expr30_0);
6756 }
6757 
6758 // Generated as internal constructor for term do_shift.
6759 pub fn constructor_do_shift<C: Context>(
6760     ctx: &mut C,
6761     arg0: &ALUOp,
6762     arg1: Type,
6763     arg2: Reg,
6764     arg3: Value,
6765 ) -> Option<Reg> {
6766     let pattern0_0 = arg0;
6767     let pattern1_0 = arg1;
6768     let pattern2_0 = arg2;
6769     let pattern3_0 = arg3;
6770     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
6771         let pattern5_0 = C::inst_data(ctx, pattern4_0);
6772         if let &InstructionData::UnaryImm {
6773             opcode: ref pattern6_0,
6774             imm: pattern6_1,
6775         } = &pattern5_0
6776         {
6777             if let &Opcode::Iconst = pattern6_0 {
6778                 let closure8 = || {
6779                     return Some(pattern1_0);
6780                 };
6781                 if let Some(pattern8_0) = closure8() {
6782                     if let Some(pattern9_0) = C::imm_shift_from_imm64(ctx, pattern6_1, pattern8_0) {
6783                         // Rule at src/isa/aarch64/lower.isle line 734.
6784                         let expr0_0 = constructor_alu_rr_imm_shift(
6785                             ctx, pattern0_0, pattern1_0, pattern2_0, pattern9_0,
6786                         )?;
6787                         return Some(expr0_0);
6788                     }
6789                 }
6790             }
6791         }
6792     }
6793     let pattern0_0 = arg0;
6794     let pattern1_0 = arg1;
6795     if pattern1_0 == I32 {
6796         let pattern3_0 = arg2;
6797         let pattern4_0 = arg3;
6798         // Rule at src/isa/aarch64/lower.isle line 725.
6799         let expr0_0: Type = I32;
6800         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6801         let expr2_0: usize = 0;
6802         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6803         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6804         return Some(expr4_0);
6805     }
6806     if pattern1_0 == I64 {
6807         let pattern3_0 = arg2;
6808         let pattern4_0 = arg3;
6809         // Rule at src/isa/aarch64/lower.isle line 726.
6810         let expr0_0: Type = I64;
6811         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6812         let expr2_0: usize = 0;
6813         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6814         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6815         return Some(expr4_0);
6816     }
6817     if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
6818         let pattern3_0 = arg2;
6819         let pattern4_0 = arg3;
6820         // Rule at src/isa/aarch64/lower.isle line 716.
6821         let expr0_0 = C::put_in_regs(ctx, pattern4_0);
6822         let expr1_0: usize = 0;
6823         let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
6824         let expr3_0: Type = I32;
6825         let expr4_0 = C::shift_mask(ctx, pattern2_0);
6826         let expr5_0 = constructor_and_imm(ctx, expr3_0, expr2_0, expr4_0)?;
6827         let expr6_0: Type = I32;
6828         let expr7_0 = constructor_alu_rrr(ctx, pattern0_0, expr6_0, pattern3_0, expr5_0)?;
6829         return Some(expr7_0);
6830     }
6831     return None;
6832 }
6833 
6834 // Generated as internal constructor for term lower_ushr128.
6835 pub fn constructor_lower_ushr128<C: Context>(
6836     ctx: &mut C,
6837     arg0: ValueRegs,
6838     arg1: Reg,
6839 ) -> Option<ValueRegs> {
6840     let pattern0_0 = arg0;
6841     let pattern1_0 = arg1;
6842     // Rule at src/isa/aarch64/lower.isle line 767.
6843     let expr0_0: usize = 0;
6844     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6845     let expr2_0: usize = 1;
6846     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6847     let expr4_0: Type = I64;
6848     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6849     let expr6_0: Type = I64;
6850     let expr7_0 = constructor_lsr(ctx, expr6_0, expr3_0, pattern1_0)?;
6851     let expr8_0: Type = I32;
6852     let expr9_0 = C::zero_reg(ctx);
6853     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6854     let expr11_0: Type = I64;
6855     let expr12_0: Type = I64;
6856     let expr13_0: u8 = 1;
6857     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6858     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6859     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6860     let expr17_0: Type = I64;
6861     let expr18_0 = constructor_orr(ctx, expr17_0, expr5_0, expr16_0)?;
6862     let expr19_0: Type = I64;
6863     let expr20_0: Type = I64;
6864     let expr21_0: u64 = 64;
6865     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6866     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6867     let expr24_0 = Cond::Ne;
6868     let expr25_0 = constructor_csel(ctx, &expr24_0, expr7_0, expr18_0)?;
6869     let expr26_0 = Cond::Ne;
6870     let expr27_0 = C::zero_reg(ctx);
6871     let expr28_0 = constructor_csel(ctx, &expr26_0, expr27_0, expr7_0)?;
6872     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr25_0, &expr28_0)?;
6873     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6874     return Some(expr30_0);
6875 }
6876 
6877 // Generated as internal constructor for term lower_sshr128.
6878 pub fn constructor_lower_sshr128<C: Context>(
6879     ctx: &mut C,
6880     arg0: ValueRegs,
6881     arg1: Reg,
6882 ) -> Option<ValueRegs> {
6883     let pattern0_0 = arg0;
6884     let pattern1_0 = arg1;
6885     // Rule at src/isa/aarch64/lower.isle line 817.
6886     let expr0_0: usize = 0;
6887     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6888     let expr2_0: usize = 1;
6889     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6890     let expr4_0: Type = I64;
6891     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6892     let expr6_0: Type = I64;
6893     let expr7_0 = constructor_asr(ctx, expr6_0, expr3_0, pattern1_0)?;
6894     let expr8_0: Type = I32;
6895     let expr9_0 = C::zero_reg(ctx);
6896     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6897     let expr11_0: Type = I64;
6898     let expr12_0: Type = I64;
6899     let expr13_0: u8 = 1;
6900     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6901     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6902     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6903     let expr17_0: Type = I64;
6904     let expr18_0: u8 = 63;
6905     let expr19_0 = C::imm_shift_from_u8(ctx, expr18_0);
6906     let expr20_0 = constructor_asr_imm(ctx, expr17_0, expr3_0, expr19_0)?;
6907     let expr21_0: Type = I64;
6908     let expr22_0 = constructor_orr(ctx, expr21_0, expr5_0, expr16_0)?;
6909     let expr23_0: Type = I64;
6910     let expr24_0: Type = I64;
6911     let expr25_0: u64 = 64;
6912     let expr26_0 = C::u64_into_imm_logic(ctx, expr24_0, expr25_0);
6913     let expr27_0 = constructor_tst_imm(ctx, expr23_0, pattern1_0, expr26_0)?;
6914     let expr28_0 = Cond::Ne;
6915     let expr29_0 = constructor_csel(ctx, &expr28_0, expr7_0, expr22_0)?;
6916     let expr30_0 = Cond::Ne;
6917     let expr31_0 = constructor_csel(ctx, &expr30_0, expr20_0, expr7_0)?;
6918     let expr32_0 = constructor_consumes_flags_concat(ctx, &expr29_0, &expr31_0)?;
6919     let expr33_0 = constructor_with_flags(ctx, &expr27_0, &expr32_0)?;
6920     return Some(expr33_0);
6921 }
6922 
6923 // Generated as internal constructor for term small_rotr.
6924 pub fn constructor_small_rotr<C: Context>(
6925     ctx: &mut C,
6926     arg0: Type,
6927     arg1: Reg,
6928     arg2: Reg,
6929 ) -> Option<Reg> {
6930     let pattern0_0 = arg0;
6931     let pattern1_0 = arg1;
6932     let pattern2_0 = arg2;
6933     // Rule at src/isa/aarch64/lower.isle line 927.
6934     let expr0_0: Type = I32;
6935     let expr1_0 = C::rotr_mask(ctx, pattern0_0);
6936     let expr2_0 = constructor_and_imm(ctx, expr0_0, pattern2_0, expr1_0)?;
6937     let expr3_0: Type = I32;
6938     let expr4_0 = C::ty_bits(ctx, pattern0_0);
6939     let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
6940     let expr6_0 = constructor_sub_imm(ctx, expr3_0, expr2_0, expr5_0)?;
6941     let expr7_0: Type = I32;
6942     let expr8_0 = C::zero_reg(ctx);
6943     let expr9_0 = constructor_sub(ctx, expr7_0, expr8_0, expr6_0)?;
6944     let expr10_0: Type = I32;
6945     let expr11_0 = constructor_lsr(ctx, expr10_0, pattern1_0, expr2_0)?;
6946     let expr12_0: Type = I32;
6947     let expr13_0 = constructor_lsl(ctx, expr12_0, pattern1_0, expr9_0)?;
6948     let expr14_0: Type = I32;
6949     let expr15_0 = constructor_orr(ctx, expr14_0, expr13_0, expr11_0)?;
6950     return Some(expr15_0);
6951 }
6952 
6953 // Generated as internal constructor for term small_rotr_imm.
6954 pub fn constructor_small_rotr_imm<C: Context>(
6955     ctx: &mut C,
6956     arg0: Type,
6957     arg1: Reg,
6958     arg2: ImmShift,
6959 ) -> Option<Reg> {
6960     let pattern0_0 = arg0;
6961     let pattern1_0 = arg1;
6962     let pattern2_0 = arg2;
6963     // Rule at src/isa/aarch64/lower.isle line 948.
6964     let expr0_0: Type = I32;
6965     let expr1_0 = constructor_lsr_imm(ctx, expr0_0, pattern1_0, pattern2_0)?;
6966     let expr2_0: Type = I32;
6967     let expr3_0 = C::rotr_opposite_amount(ctx, pattern0_0, pattern2_0);
6968     let expr4_0 = constructor_lsl_imm(ctx, expr2_0, pattern1_0, expr3_0)?;
6969     let expr5_0: Type = I32;
6970     let expr6_0 = constructor_orr(ctx, expr5_0, expr4_0, expr1_0)?;
6971     return Some(expr6_0);
6972 }
6973 
6974 // Generated as internal constructor for term lower_clz128.
6975 pub fn constructor_lower_clz128<C: Context>(ctx: &mut C, arg0: ValueRegs) -> Option<ValueRegs> {
6976     let pattern0_0 = arg0;
6977     // Rule at src/isa/aarch64/lower.isle line 1013.
6978     let expr0_0: Type = I64;
6979     let expr1_0: usize = 1;
6980     let expr2_0 = C::value_regs_get(ctx, pattern0_0, expr1_0);
6981     let expr3_0 = constructor_a64_clz(ctx, expr0_0, expr2_0)?;
6982     let expr4_0: Type = I64;
6983     let expr5_0: usize = 0;
6984     let expr6_0 = C::value_regs_get(ctx, pattern0_0, expr5_0);
6985     let expr7_0 = constructor_a64_clz(ctx, expr4_0, expr6_0)?;
6986     let expr8_0: Type = I64;
6987     let expr9_0: u8 = 6;
6988     let expr10_0 = C::imm_shift_from_u8(ctx, expr9_0);
6989     let expr11_0 = constructor_lsr_imm(ctx, expr8_0, expr3_0, expr10_0)?;
6990     let expr12_0 = constructor_madd64(ctx, expr7_0, expr11_0, expr3_0)?;
6991     let expr13_0: Type = I64;
6992     let expr14_0: u64 = 0;
6993     let expr15_0 = constructor_imm(ctx, expr13_0, expr14_0)?;
6994     let expr16_0 = C::value_regs(ctx, expr12_0, expr15_0);
6995     return Some(expr16_0);
6996 }
6997