1 // GENERATED BY ISLE. DO NOT EDIT!
2 //
3 // Generated automatically from the instruction-selection DSL code in:
4 // - src/clif.isle
5 // - src/prelude.isle
6 // - src/isa/aarch64/inst.isle
7 // - src/isa/aarch64/lower.isle
8 
9 #![allow(dead_code, unreachable_code, unreachable_patterns)]
10 #![allow(unused_imports, unused_variables, non_snake_case)]
11 #![allow(irrefutable_let_patterns)]
12 
13 use super::*; // Pulls in all external types.
14 
15 /// Context during lowering: an implementation of this trait
16 /// must be provided with all external constructors and extractors.
17 /// A mutable borrow is passed along through all lowering logic.
18 pub trait Context {
19     fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value);
20     fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2;
21     fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value);
22     fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3;
23     fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32;
24     fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8;
25     fn value_reg(&mut self, arg0: Reg) -> ValueRegs;
26     fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs;
27     fn value_regs_invalid(&mut self) -> ValueRegs;
28     fn output_none(&mut self) -> InstOutput;
29     fn output(&mut self, arg0: ValueRegs) -> InstOutput;
30     fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput;
31     fn output_builder_new(&mut self) -> InstOutputBuilder;
32     fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit;
33     fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput;
34     fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg;
35     fn invalid_reg(&mut self) -> Reg;
36     fn put_in_reg(&mut self, arg0: Value) -> Reg;
37     fn put_in_regs(&mut self, arg0: Value) -> ValueRegs;
38     fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg;
39     fn u8_as_u64(&mut self, arg0: u8) -> u64;
40     fn u16_as_u64(&mut self, arg0: u16) -> u64;
41     fn u32_as_u64(&mut self, arg0: u32) -> u64;
42     fn ty_bits(&mut self, arg0: Type) -> u8;
43     fn ty_bits_u16(&mut self, arg0: Type) -> u16;
44     fn ty_bytes(&mut self, arg0: Type) -> u16;
45     fn lane_type(&mut self, arg0: Type) -> Type;
46     fn fits_in_16(&mut self, arg0: Type) -> Option<Type>;
47     fn fits_in_32(&mut self, arg0: Type) -> Option<Type>;
48     fn fits_in_64(&mut self, arg0: Type) -> Option<Type>;
49     fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>;
50     fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>;
51     fn vec128(&mut self, arg0: Type) -> Option<Type>;
52     fn not_i64x2(&mut self, arg0: Type) -> Option<()>;
53     fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice;
54     fn unwrap_head_value_list_1(&mut self, arg0: ValueList) -> (Value, ValueSlice);
55     fn unwrap_head_value_list_2(&mut self, arg0: ValueList) -> (Value, Value, ValueSlice);
56     fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg;
57     fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8;
58     fn u64_from_imm64(&mut self, arg0: Imm64) -> u64;
59     fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
60     fn u64_from_ieee32(&mut self, arg0: Ieee32) -> u64;
61     fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64;
62     fn inst_results(&mut self, arg0: Inst) -> ValueSlice;
63     fn first_result(&mut self, arg0: Inst) -> Option<Value>;
64     fn inst_data(&mut self, arg0: Inst) -> InstructionData;
65     fn value_type(&mut self, arg0: Value) -> Type;
66     fn multi_lane(&mut self, arg0: Type) -> Option<(u8, u16)>;
67     fn def_inst(&mut self, arg0: Value) -> Option<Inst>;
68     fn emit(&mut self, arg0: &MInst) -> Unit;
69     fn emit_safepoint(&mut self, arg0: &MInst) -> Unit;
70     fn trap_code_division_by_zero(&mut self) -> TrapCode;
71     fn trap_code_integer_overflow(&mut self) -> TrapCode;
72     fn trap_code_bad_conversion_to_integer(&mut self) -> TrapCode;
73     fn avoid_div_traps(&mut self, arg0: Type) -> Option<()>;
74     fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance);
75     fn symbol_value_data(
76         &mut self,
77         arg0: GlobalValue,
78     ) -> Option<(ExternalName, RelocDistance, i64)>;
79     fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>;
80     fn move_wide_const_from_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
81     fn move_wide_const_from_negated_u64(&mut self, arg0: u64) -> Option<MoveWideConst>;
82     fn imm_logic_from_u64(&mut self, arg0: u64, arg1: Type) -> Option<ImmLogic>;
83     fn imm_logic_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmLogic>;
84     fn imm_shift_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ImmShift>;
85     fn imm_shift_from_u8(&mut self, arg0: u8) -> ImmShift;
86     fn imm12_from_u64(&mut self, arg0: u64) -> Option<Imm12>;
87     fn u8_into_uimm5(&mut self, arg0: u8) -> UImm5;
88     fn u8_into_imm12(&mut self, arg0: u8) -> Imm12;
89     fn u64_into_imm_logic(&mut self, arg0: Type, arg1: u64) -> ImmLogic;
90     fn imm12_from_negated_u64(&mut self, arg0: u64) -> Option<Imm12>;
91     fn lshl_from_imm64(&mut self, arg0: Imm64, arg1: Type) -> Option<ShiftOpAndAmt>;
92     fn integral_ty(&mut self, arg0: Type) -> Option<Type>;
93     fn extended_value_from_value(&mut self, arg0: Value) -> Option<ExtendedValue>;
94     fn put_extended_in_reg(&mut self, arg0: &ExtendedValue) -> Reg;
95     fn get_extended_op(&mut self, arg0: &ExtendedValue) -> ExtendOp;
96     fn nzcv(&mut self, arg0: bool, arg1: bool, arg2: bool, arg3: bool) -> NZCV;
97     fn cond_br_zero(&mut self, arg0: Reg) -> CondBrKind;
98     fn cond_br_cond(&mut self, arg0: &Cond) -> CondBrKind;
99     fn zero_reg(&mut self) -> Reg;
100     fn writable_zero_reg(&mut self) -> WritableReg;
101     fn load_constant64_full(&mut self, arg0: u64) -> Reg;
102     fn sinkable_atomic_load(&mut self, arg0: Value) -> Option<SinkableAtomicLoad>;
103     fn sink_atomic_load(&mut self, arg0: &SinkableAtomicLoad) -> Reg;
104     fn safe_divisor_from_imm64(&mut self, arg0: Imm64) -> Option<u64>;
105     fn shift_mask(&mut self, arg0: Type) -> ImmLogic;
106     fn negate_imm_shift(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
107     fn rotr_mask(&mut self, arg0: Type) -> ImmLogic;
108     fn rotr_opposite_amount(&mut self, arg0: Type, arg1: ImmShift) -> ImmShift;
109 }
110 
111 /// Internal type SideEffectNoResult: defined at src/prelude.isle line 345.
112 #[derive(Clone, Debug)]
113 pub enum SideEffectNoResult {
114     Inst { inst: MInst },
115 }
116 
117 /// Internal type ProducesFlags: defined at src/prelude.isle line 367.
118 #[derive(Clone, Debug)]
119 pub enum ProducesFlags {
120     ProducesFlagsSideEffect { inst: MInst },
121     ProducesFlagsReturnsReg { inst: MInst, result: Reg },
122     ProducesFlagsReturnsResultWithConsumer { inst: MInst, result: Reg },
123 }
124 
125 /// Internal type ConsumesFlags: defined at src/prelude.isle line 378.
126 #[derive(Clone, Debug)]
127 pub enum ConsumesFlags {
128     ConsumesFlagsReturnsResultWithProducer {
129         inst: MInst,
130         result: Reg,
131     },
132     ConsumesFlagsReturnsReg {
133         inst: MInst,
134         result: Reg,
135     },
136     ConsumesFlagsTwiceReturnsValueRegs {
137         inst1: MInst,
138         inst2: MInst,
139         result: ValueRegs,
140     },
141 }
142 
143 /// Internal type MInst: defined at src/isa/aarch64/inst.isle line 2.
144 #[derive(Clone, Debug)]
145 pub enum MInst {
146     Nop0,
147     Nop4,
148     AluRRR {
149         alu_op: ALUOp,
150         size: OperandSize,
151         rd: WritableReg,
152         rn: Reg,
153         rm: Reg,
154     },
155     AluRRRR {
156         alu_op: ALUOp3,
157         rd: WritableReg,
158         rn: Reg,
159         rm: Reg,
160         ra: Reg,
161     },
162     AluRRImm12 {
163         alu_op: ALUOp,
164         size: OperandSize,
165         rd: WritableReg,
166         rn: Reg,
167         imm12: Imm12,
168     },
169     AluRRImmLogic {
170         alu_op: ALUOp,
171         size: OperandSize,
172         rd: WritableReg,
173         rn: Reg,
174         imml: ImmLogic,
175     },
176     AluRRImmShift {
177         alu_op: ALUOp,
178         size: OperandSize,
179         rd: WritableReg,
180         rn: Reg,
181         immshift: ImmShift,
182     },
183     AluRRRShift {
184         alu_op: ALUOp,
185         size: OperandSize,
186         rd: WritableReg,
187         rn: Reg,
188         rm: Reg,
189         shiftop: ShiftOpAndAmt,
190     },
191     AluRRRExtend {
192         alu_op: ALUOp,
193         size: OperandSize,
194         rd: WritableReg,
195         rn: Reg,
196         rm: Reg,
197         extendop: ExtendOp,
198     },
199     BitRR {
200         op: BitOp,
201         size: OperandSize,
202         rd: WritableReg,
203         rn: Reg,
204     },
205     ULoad8 {
206         rd: WritableReg,
207         mem: AMode,
208         flags: MemFlags,
209     },
210     SLoad8 {
211         rd: WritableReg,
212         mem: AMode,
213         flags: MemFlags,
214     },
215     ULoad16 {
216         rd: WritableReg,
217         mem: AMode,
218         flags: MemFlags,
219     },
220     SLoad16 {
221         rd: WritableReg,
222         mem: AMode,
223         flags: MemFlags,
224     },
225     ULoad32 {
226         rd: WritableReg,
227         mem: AMode,
228         flags: MemFlags,
229     },
230     SLoad32 {
231         rd: WritableReg,
232         mem: AMode,
233         flags: MemFlags,
234     },
235     ULoad64 {
236         rd: WritableReg,
237         mem: AMode,
238         flags: MemFlags,
239     },
240     Store8 {
241         rd: Reg,
242         mem: AMode,
243         flags: MemFlags,
244     },
245     Store16 {
246         rd: Reg,
247         mem: AMode,
248         flags: MemFlags,
249     },
250     Store32 {
251         rd: Reg,
252         mem: AMode,
253         flags: MemFlags,
254     },
255     Store64 {
256         rd: Reg,
257         mem: AMode,
258         flags: MemFlags,
259     },
260     StoreP64 {
261         rt: Reg,
262         rt2: Reg,
263         mem: PairAMode,
264         flags: MemFlags,
265     },
266     LoadP64 {
267         rt: WritableReg,
268         rt2: WritableReg,
269         mem: PairAMode,
270         flags: MemFlags,
271     },
272     Mov64 {
273         rd: WritableReg,
274         rm: Reg,
275     },
276     Mov32 {
277         rd: WritableReg,
278         rm: Reg,
279     },
280     MovZ {
281         rd: WritableReg,
282         imm: MoveWideConst,
283         size: OperandSize,
284     },
285     MovN {
286         rd: WritableReg,
287         imm: MoveWideConst,
288         size: OperandSize,
289     },
290     MovK {
291         rd: WritableReg,
292         imm: MoveWideConst,
293         size: OperandSize,
294     },
295     Extend {
296         rd: WritableReg,
297         rn: Reg,
298         signed: bool,
299         from_bits: u8,
300         to_bits: u8,
301     },
302     CSel {
303         rd: WritableReg,
304         cond: Cond,
305         rn: Reg,
306         rm: Reg,
307     },
308     CSet {
309         rd: WritableReg,
310         cond: Cond,
311     },
312     CSetm {
313         rd: WritableReg,
314         cond: Cond,
315     },
316     CCmpImm {
317         size: OperandSize,
318         rn: Reg,
319         imm: UImm5,
320         nzcv: NZCV,
321         cond: Cond,
322     },
323     AtomicRMWLoop {
324         ty: Type,
325         op: AtomicRmwOp,
326     },
327     AtomicRMW {
328         op: AtomicRMWOp,
329         rs: Reg,
330         rt: WritableReg,
331         rn: Reg,
332         ty: Type,
333     },
334     AtomicCAS {
335         rs: WritableReg,
336         rt: Reg,
337         rn: Reg,
338         ty: Type,
339     },
340     AtomicCASLoop {
341         ty: Type,
342     },
343     LoadAcquire {
344         access_ty: Type,
345         rt: WritableReg,
346         rn: Reg,
347     },
348     StoreRelease {
349         access_ty: Type,
350         rt: Reg,
351         rn: Reg,
352     },
353     Fence,
354     FpuMove64 {
355         rd: WritableReg,
356         rn: Reg,
357     },
358     FpuMove128 {
359         rd: WritableReg,
360         rn: Reg,
361     },
362     FpuMoveFromVec {
363         rd: WritableReg,
364         rn: Reg,
365         idx: u8,
366         size: VectorSize,
367     },
368     FpuExtend {
369         rd: WritableReg,
370         rn: Reg,
371         size: ScalarSize,
372     },
373     FpuRR {
374         fpu_op: FPUOp1,
375         rd: WritableReg,
376         rn: Reg,
377     },
378     FpuRRR {
379         fpu_op: FPUOp2,
380         rd: WritableReg,
381         rn: Reg,
382         rm: Reg,
383     },
384     FpuRRI {
385         fpu_op: FPUOpRI,
386         rd: WritableReg,
387         rn: Reg,
388     },
389     FpuRRRR {
390         fpu_op: FPUOp3,
391         rd: WritableReg,
392         rn: Reg,
393         rm: Reg,
394         ra: Reg,
395     },
396     FpuCmp32 {
397         rn: Reg,
398         rm: Reg,
399     },
400     FpuCmp64 {
401         rn: Reg,
402         rm: Reg,
403     },
404     FpuLoad32 {
405         rd: WritableReg,
406         mem: AMode,
407         flags: MemFlags,
408     },
409     FpuStore32 {
410         rd: Reg,
411         mem: AMode,
412         flags: MemFlags,
413     },
414     FpuLoad64 {
415         rd: WritableReg,
416         mem: AMode,
417         flags: MemFlags,
418     },
419     FpuStore64 {
420         rd: Reg,
421         mem: AMode,
422         flags: MemFlags,
423     },
424     FpuLoad128 {
425         rd: WritableReg,
426         mem: AMode,
427         flags: MemFlags,
428     },
429     FpuStore128 {
430         rd: Reg,
431         mem: AMode,
432         flags: MemFlags,
433     },
434     FpuLoadP64 {
435         rt: WritableReg,
436         rt2: WritableReg,
437         mem: PairAMode,
438         flags: MemFlags,
439     },
440     FpuStoreP64 {
441         rt: Reg,
442         rt2: Reg,
443         mem: PairAMode,
444         flags: MemFlags,
445     },
446     FpuLoadP128 {
447         rt: WritableReg,
448         rt2: WritableReg,
449         mem: PairAMode,
450         flags: MemFlags,
451     },
452     FpuStoreP128 {
453         rt: Reg,
454         rt2: Reg,
455         mem: PairAMode,
456         flags: MemFlags,
457     },
458     LoadFpuConst64 {
459         rd: WritableReg,
460         const_data: u64,
461     },
462     LoadFpuConst128 {
463         rd: WritableReg,
464         const_data: u128,
465     },
466     FpuToInt {
467         op: FpuToIntOp,
468         rd: WritableReg,
469         rn: Reg,
470     },
471     IntToFpu {
472         op: IntToFpuOp,
473         rd: WritableReg,
474         rn: Reg,
475     },
476     FpuCSel32 {
477         rd: WritableReg,
478         rn: Reg,
479         rm: Reg,
480         cond: Cond,
481     },
482     FpuCSel64 {
483         rd: WritableReg,
484         rn: Reg,
485         rm: Reg,
486         cond: Cond,
487     },
488     FpuRound {
489         op: FpuRoundMode,
490         rd: WritableReg,
491         rn: Reg,
492     },
493     MovToFpu {
494         rd: WritableReg,
495         rn: Reg,
496         size: ScalarSize,
497     },
498     FpuMoveFPImm {
499         rd: WritableReg,
500         imm: ASIMDFPModImm,
501         size: ScalarSize,
502     },
503     MovToVec {
504         rd: WritableReg,
505         rn: Reg,
506         idx: u8,
507         size: VectorSize,
508     },
509     MovFromVec {
510         rd: WritableReg,
511         rn: Reg,
512         idx: u8,
513         size: VectorSize,
514     },
515     MovFromVecSigned {
516         rd: WritableReg,
517         rn: Reg,
518         idx: u8,
519         size: VectorSize,
520         scalar_size: OperandSize,
521     },
522     VecDup {
523         rd: WritableReg,
524         rn: Reg,
525         size: VectorSize,
526     },
527     VecDupFromFpu {
528         rd: WritableReg,
529         rn: Reg,
530         size: VectorSize,
531     },
532     VecDupFPImm {
533         rd: WritableReg,
534         imm: ASIMDFPModImm,
535         size: VectorSize,
536     },
537     VecDupImm {
538         rd: WritableReg,
539         imm: ASIMDMovModImm,
540         invert: bool,
541         size: VectorSize,
542     },
543     VecExtend {
544         t: VecExtendOp,
545         rd: WritableReg,
546         rn: Reg,
547         high_half: bool,
548     },
549     VecMovElement {
550         rd: WritableReg,
551         rn: Reg,
552         dest_idx: u8,
553         src_idx: u8,
554         size: VectorSize,
555     },
556     VecRRLong {
557         op: VecRRLongOp,
558         rd: WritableReg,
559         rn: Reg,
560         high_half: bool,
561     },
562     VecRRNarrow {
563         op: VecRRNarrowOp,
564         rd: WritableReg,
565         rn: Reg,
566         high_half: bool,
567     },
568     VecRRPair {
569         op: VecPairOp,
570         rd: WritableReg,
571         rn: Reg,
572     },
573     VecRRRLong {
574         alu_op: VecRRRLongOp,
575         rd: WritableReg,
576         rn: Reg,
577         rm: Reg,
578         high_half: bool,
579     },
580     VecRRPairLong {
581         op: VecRRPairLongOp,
582         rd: WritableReg,
583         rn: Reg,
584     },
585     VecRRR {
586         alu_op: VecALUOp,
587         rd: WritableReg,
588         rn: Reg,
589         rm: Reg,
590         size: VectorSize,
591     },
592     VecMisc {
593         op: VecMisc2,
594         rd: WritableReg,
595         rn: Reg,
596         size: VectorSize,
597     },
598     VecLanes {
599         op: VecLanesOp,
600         rd: WritableReg,
601         rn: Reg,
602         size: VectorSize,
603     },
604     VecShiftImm {
605         op: VecShiftImmOp,
606         rd: WritableReg,
607         rn: Reg,
608         size: VectorSize,
609         imm: u8,
610     },
611     VecExtract {
612         rd: WritableReg,
613         rn: Reg,
614         rm: Reg,
615         imm4: u8,
616     },
617     VecTbl {
618         rd: WritableReg,
619         rn: Reg,
620         rm: Reg,
621         is_extension: bool,
622     },
623     VecTbl2 {
624         rd: WritableReg,
625         rn: Reg,
626         rn2: Reg,
627         rm: Reg,
628         is_extension: bool,
629     },
630     VecLoadReplicate {
631         rd: WritableReg,
632         rn: Reg,
633         size: VectorSize,
634     },
635     VecCSel {
636         rd: WritableReg,
637         rn: Reg,
638         rm: Reg,
639         cond: Cond,
640     },
641     MovToNZCV {
642         rn: Reg,
643     },
644     MovFromNZCV {
645         rd: WritableReg,
646     },
647     Call {
648         info: BoxCallInfo,
649     },
650     CallInd {
651         info: BoxCallIndInfo,
652     },
653     Ret,
654     EpiloguePlaceholder,
655     Jump {
656         dest: BranchTarget,
657     },
658     CondBr {
659         taken: BranchTarget,
660         not_taken: BranchTarget,
661         kind: CondBrKind,
662     },
663     TrapIf {
664         kind: CondBrKind,
665         trap_code: TrapCode,
666     },
667     IndirectBr {
668         rn: Reg,
669         targets: VecMachLabel,
670     },
671     Brk,
672     Udf {
673         trap_code: TrapCode,
674     },
675     Adr {
676         rd: WritableReg,
677         off: i32,
678     },
679     Word4 {
680         data: u32,
681     },
682     Word8 {
683         data: u64,
684     },
685     JTSequence {
686         info: BoxJTSequenceInfo,
687         ridx: Reg,
688         rtmp1: WritableReg,
689         rtmp2: WritableReg,
690     },
691     LoadExtName {
692         rd: WritableReg,
693         name: BoxExternalName,
694         offset: i64,
695     },
696     LoadAddr {
697         rd: WritableReg,
698         mem: AMode,
699     },
700     VirtualSPOffsetAdj {
701         offset: i64,
702     },
703     EmitIsland {
704         needed_space: CodeOffset,
705     },
706     ElfTlsGetAddr {
707         symbol: ExternalName,
708     },
709     ValueLabelMarker {
710         reg: Reg,
711         label: ValueLabel,
712     },
713     Unwind {
714         inst: UnwindInst,
715     },
716 }
717 
718 /// Internal type ALUOp: defined at src/isa/aarch64/inst.isle line 796.
719 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
720 pub enum ALUOp {
721     Add,
722     Sub,
723     Orr,
724     OrrNot,
725     And,
726     AndS,
727     AndNot,
728     Eor,
729     EorNot,
730     AddS,
731     SubS,
732     SMulH,
733     UMulH,
734     SDiv,
735     UDiv,
736     RotR,
737     Lsr,
738     Asr,
739     Lsl,
740     Adc,
741     AdcS,
742     Sbc,
743     SbcS,
744 }
745 
746 /// Internal type ALUOp3: defined at src/isa/aarch64/inst.isle line 834.
747 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
748 pub enum ALUOp3 {
749     MAdd32,
750     MAdd64,
751     MSub32,
752     MSub64,
753 }
754 
755 /// Internal type BitOp: defined at src/isa/aarch64/inst.isle line 877.
756 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
757 pub enum BitOp {
758     RBit,
759     Clz,
760     Cls,
761 }
762 
763 /// Internal type FPUOp1: defined at src/isa/aarch64/inst.isle line 944.
764 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
765 pub enum FPUOp1 {
766     Abs32,
767     Abs64,
768     Neg32,
769     Neg64,
770     Sqrt32,
771     Sqrt64,
772     Cvt32To64,
773     Cvt64To32,
774 }
775 
776 /// Internal type FPUOp2: defined at src/isa/aarch64/inst.isle line 957.
777 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
778 pub enum FPUOp2 {
779     Add32,
780     Add64,
781     Sub32,
782     Sub64,
783     Mul32,
784     Mul64,
785     Div32,
786     Div64,
787     Max32,
788     Max64,
789     Min32,
790     Min64,
791     Sqadd64,
792     Uqadd64,
793     Sqsub64,
794     Uqsub64,
795 }
796 
797 /// Internal type FPUOp3: defined at src/isa/aarch64/inst.isle line 982.
798 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
799 pub enum FPUOp3 {
800     MAdd32,
801     MAdd64,
802 }
803 
804 /// Internal type FpuToIntOp: defined at src/isa/aarch64/inst.isle line 989.
805 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
806 pub enum FpuToIntOp {
807     F32ToU32,
808     F32ToI32,
809     F32ToU64,
810     F32ToI64,
811     F64ToU32,
812     F64ToI32,
813     F64ToU64,
814     F64ToI64,
815 }
816 
817 /// Internal type IntToFpuOp: defined at src/isa/aarch64/inst.isle line 1002.
818 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
819 pub enum IntToFpuOp {
820     U32ToF32,
821     I32ToF32,
822     U32ToF64,
823     I32ToF64,
824     U64ToF32,
825     I64ToF32,
826     U64ToF64,
827     I64ToF64,
828 }
829 
830 /// Internal type FpuRoundMode: defined at src/isa/aarch64/inst.isle line 1016.
831 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
832 pub enum FpuRoundMode {
833     Minus32,
834     Minus64,
835     Plus32,
836     Plus64,
837     Zero32,
838     Zero64,
839     Nearest32,
840     Nearest64,
841 }
842 
843 /// Internal type VecExtendOp: defined at src/isa/aarch64/inst.isle line 1029.
844 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
845 pub enum VecExtendOp {
846     Sxtl8,
847     Sxtl16,
848     Sxtl32,
849     Uxtl8,
850     Uxtl16,
851     Uxtl32,
852 }
853 
854 /// Internal type VecALUOp: defined at src/isa/aarch64/inst.isle line 1046.
855 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
856 pub enum VecALUOp {
857     Sqadd,
858     Uqadd,
859     Sqsub,
860     Uqsub,
861     Cmeq,
862     Cmge,
863     Cmgt,
864     Cmhs,
865     Cmhi,
866     Fcmeq,
867     Fcmgt,
868     Fcmge,
869     And,
870     Bic,
871     Orr,
872     Eor,
873     Bsl,
874     Umaxp,
875     Add,
876     Sub,
877     Mul,
878     Sshl,
879     Ushl,
880     Umin,
881     Smin,
882     Umax,
883     Smax,
884     Urhadd,
885     Fadd,
886     Fsub,
887     Fdiv,
888     Fmax,
889     Fmin,
890     Fmul,
891     Addp,
892     Zip1,
893     Sqrdmulh,
894 }
895 
896 /// Internal type VecMisc2: defined at src/isa/aarch64/inst.isle line 1125.
897 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
898 pub enum VecMisc2 {
899     Not,
900     Neg,
901     Abs,
902     Fabs,
903     Fneg,
904     Fsqrt,
905     Rev64,
906     Fcvtzs,
907     Fcvtzu,
908     Scvtf,
909     Ucvtf,
910     Frintn,
911     Frintz,
912     Frintm,
913     Frintp,
914     Cnt,
915     Cmeq0,
916 }
917 
918 /// Internal type VecRRLongOp: defined at src/isa/aarch64/inst.isle line 1164.
919 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
920 pub enum VecRRLongOp {
921     Fcvtl16,
922     Fcvtl32,
923     Shll8,
924     Shll16,
925     Shll32,
926 }
927 
928 /// Internal type VecRRNarrowOp: defined at src/isa/aarch64/inst.isle line 1179.
929 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
930 pub enum VecRRNarrowOp {
931     Xtn16,
932     Xtn32,
933     Xtn64,
934     Sqxtn16,
935     Sqxtn32,
936     Sqxtn64,
937     Sqxtun16,
938     Sqxtun32,
939     Sqxtun64,
940     Uqxtn16,
941     Uqxtn32,
942     Uqxtn64,
943     Fcvtn32,
944     Fcvtn64,
945 }
946 
947 /// Internal type VecRRRLongOp: defined at src/isa/aarch64/inst.isle line 1211.
948 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
949 pub enum VecRRRLongOp {
950     Smull8,
951     Smull16,
952     Smull32,
953     Umull8,
954     Umull16,
955     Umull32,
956     Umlal8,
957     Umlal16,
958     Umlal32,
959 }
960 
961 /// Internal type VecPairOp: defined at src/isa/aarch64/inst.isle line 1228.
962 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
963 pub enum VecPairOp {
964     Addp,
965 }
966 
967 /// Internal type VecRRPairLongOp: defined at src/isa/aarch64/inst.isle line 1236.
968 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
969 pub enum VecRRPairLongOp {
970     Saddlp8,
971     Saddlp16,
972     Uaddlp8,
973     Uaddlp16,
974 }
975 
976 /// Internal type VecLanesOp: defined at src/isa/aarch64/inst.isle line 1247.
977 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
978 pub enum VecLanesOp {
979     Addv,
980     Uminv,
981 }
982 
983 /// Internal type VecShiftImmOp: defined at src/isa/aarch64/inst.isle line 1256.
984 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
985 pub enum VecShiftImmOp {
986     Shl,
987     Ushr,
988     Sshr,
989 }
990 
991 /// Internal type AtomicRMWOp: defined at src/isa/aarch64/inst.isle line 1267.
992 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
993 pub enum AtomicRMWOp {
994     Add,
995     Clr,
996     Eor,
997     Set,
998     Smax,
999     Smin,
1000     Umax,
1001     Umin,
1002 }
1003 
1004 // Generated as internal constructor for term output_reg.
1005 pub fn constructor_output_reg<C: Context>(ctx: &mut C, arg0: Reg) -> Option<InstOutput> {
1006     let pattern0_0 = arg0;
1007     // Rule at src/prelude.isle line 86.
1008     let expr0_0 = C::value_reg(ctx, pattern0_0);
1009     let expr1_0 = C::output(ctx, expr0_0);
1010     return Some(expr1_0);
1011 }
1012 
1013 // Generated as internal constructor for term output_value.
1014 pub fn constructor_output_value<C: Context>(ctx: &mut C, arg0: Value) -> Option<InstOutput> {
1015     let pattern0_0 = arg0;
1016     // Rule at src/prelude.isle line 90.
1017     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1018     let expr1_0 = C::output(ctx, expr0_0);
1019     return Some(expr1_0);
1020 }
1021 
1022 // Generated as internal constructor for term temp_reg.
1023 pub fn constructor_temp_reg<C: Context>(ctx: &mut C, arg0: Type) -> Option<Reg> {
1024     let pattern0_0 = arg0;
1025     // Rule at src/prelude.isle line 110.
1026     let expr0_0 = C::temp_writable_reg(ctx, pattern0_0);
1027     let expr1_0 = C::writable_reg_to_reg(ctx, expr0_0);
1028     return Some(expr1_0);
1029 }
1030 
1031 // Generated as internal constructor for term lo_reg.
1032 pub fn constructor_lo_reg<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
1033     let pattern0_0 = arg0;
1034     // Rule at src/prelude.isle line 145.
1035     let expr0_0 = C::put_in_regs(ctx, pattern0_0);
1036     let expr1_0: usize = 0;
1037     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1038     return Some(expr2_0);
1039 }
1040 
1041 // Generated as internal constructor for term side_effect.
1042 pub fn constructor_side_effect<C: Context>(
1043     ctx: &mut C,
1044     arg0: &SideEffectNoResult,
1045 ) -> Option<InstOutput> {
1046     let pattern0_0 = arg0;
1047     if let &SideEffectNoResult::Inst {
1048         inst: ref pattern1_0,
1049     } = pattern0_0
1050     {
1051         // Rule at src/prelude.isle line 350.
1052         let expr0_0 = C::emit(ctx, pattern1_0);
1053         let expr1_0 = C::output_none(ctx);
1054         return Some(expr1_0);
1055     }
1056     return None;
1057 }
1058 
1059 // Generated as internal constructor for term safepoint.
1060 pub fn constructor_safepoint<C: Context>(
1061     ctx: &mut C,
1062     arg0: &SideEffectNoResult,
1063 ) -> Option<InstOutput> {
1064     let pattern0_0 = arg0;
1065     if let &SideEffectNoResult::Inst {
1066         inst: ref pattern1_0,
1067     } = pattern0_0
1068     {
1069         // Rule at src/prelude.isle line 356.
1070         let expr0_0 = C::emit_safepoint(ctx, pattern1_0);
1071         let expr1_0 = C::output_none(ctx);
1072         return Some(expr1_0);
1073     }
1074     return None;
1075 }
1076 
1077 // Generated as internal constructor for term consumes_flags_concat.
1078 pub fn constructor_consumes_flags_concat<C: Context>(
1079     ctx: &mut C,
1080     arg0: &ConsumesFlags,
1081     arg1: &ConsumesFlags,
1082 ) -> Option<ConsumesFlags> {
1083     let pattern0_0 = arg0;
1084     if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1085         inst: ref pattern1_0,
1086         result: pattern1_1,
1087     } = pattern0_0
1088     {
1089         let pattern2_0 = arg1;
1090         if let &ConsumesFlags::ConsumesFlagsReturnsReg {
1091             inst: ref pattern3_0,
1092             result: pattern3_1,
1093         } = pattern2_0
1094         {
1095             // Rule at src/prelude.isle line 390.
1096             let expr0_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1097             let expr1_0 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1098                 inst1: pattern1_0.clone(),
1099                 inst2: pattern3_0.clone(),
1100                 result: expr0_0,
1101             };
1102             return Some(expr1_0);
1103         }
1104     }
1105     return None;
1106 }
1107 
1108 // Generated as internal constructor for term with_flags.
1109 pub fn constructor_with_flags<C: Context>(
1110     ctx: &mut C,
1111     arg0: &ProducesFlags,
1112     arg1: &ConsumesFlags,
1113 ) -> Option<ValueRegs> {
1114     let pattern0_0 = arg0;
1115     match pattern0_0 {
1116         &ProducesFlags::ProducesFlagsSideEffect {
1117             inst: ref pattern1_0,
1118         } => {
1119             let pattern2_0 = arg1;
1120             match pattern2_0 {
1121                 &ConsumesFlags::ConsumesFlagsReturnsReg {
1122                     inst: ref pattern3_0,
1123                     result: pattern3_1,
1124                 } => {
1125                     // Rule at src/prelude.isle line 415.
1126                     let expr0_0 = C::emit(ctx, pattern1_0);
1127                     let expr1_0 = C::emit(ctx, pattern3_0);
1128                     let expr2_0 = C::value_reg(ctx, pattern3_1);
1129                     return Some(expr2_0);
1130                 }
1131                 &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs {
1132                     inst1: ref pattern3_0,
1133                     inst2: ref pattern3_1,
1134                     result: pattern3_2,
1135                 } => {
1136                     // Rule at src/prelude.isle line 421.
1137                     let expr0_0 = C::emit(ctx, pattern1_0);
1138                     let expr1_0 = C::emit(ctx, pattern3_1);
1139                     let expr2_0 = C::emit(ctx, pattern3_0);
1140                     return Some(pattern3_2);
1141                 }
1142                 _ => {}
1143             }
1144         }
1145         &ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1146             inst: ref pattern1_0,
1147             result: pattern1_1,
1148         } => {
1149             let pattern2_0 = arg1;
1150             if let &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1151                 inst: ref pattern3_0,
1152                 result: pattern3_1,
1153             } = pattern2_0
1154             {
1155                 // Rule at src/prelude.isle line 409.
1156                 let expr0_0 = C::emit(ctx, pattern1_0);
1157                 let expr1_0 = C::emit(ctx, pattern3_0);
1158                 let expr2_0 = C::value_regs(ctx, pattern1_1, pattern3_1);
1159                 return Some(expr2_0);
1160             }
1161         }
1162         _ => {}
1163     }
1164     return None;
1165 }
1166 
1167 // Generated as internal constructor for term with_flags_reg.
1168 pub fn constructor_with_flags_reg<C: Context>(
1169     ctx: &mut C,
1170     arg0: &ProducesFlags,
1171     arg1: &ConsumesFlags,
1172 ) -> Option<Reg> {
1173     let pattern0_0 = arg0;
1174     let pattern1_0 = arg1;
1175     // Rule at src/prelude.isle line 434.
1176     let expr0_0 = constructor_with_flags(ctx, pattern0_0, pattern1_0)?;
1177     let expr1_0: usize = 0;
1178     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
1179     return Some(expr2_0);
1180 }
1181 
1182 // Generated as internal constructor for term operand_size.
1183 pub fn constructor_operand_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
1184     let pattern0_0 = arg0;
1185     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
1186         // Rule at src/isa/aarch64/inst.isle line 895.
1187         let expr0_0 = OperandSize::Size32;
1188         return Some(expr0_0);
1189     }
1190     if let Some(pattern1_0) = C::fits_in_64(ctx, pattern0_0) {
1191         // Rule at src/isa/aarch64/inst.isle line 896.
1192         let expr0_0 = OperandSize::Size64;
1193         return Some(expr0_0);
1194     }
1195     return None;
1196 }
1197 
1198 // Generated as internal constructor for term vector_size.
1199 pub fn constructor_vector_size<C: Context>(ctx: &mut C, arg0: Type) -> Option<VectorSize> {
1200     let pattern0_0 = arg0;
1201     if let Some((pattern1_0, pattern1_1)) = C::multi_lane(ctx, pattern0_0) {
1202         if pattern1_0 == 8 {
1203             if pattern1_1 == 16 {
1204                 // Rule at src/isa/aarch64/inst.isle line 938.
1205                 let expr0_0 = VectorSize::Size8x16;
1206                 return Some(expr0_0);
1207             }
1208         }
1209         if pattern1_0 == 16 {
1210             if pattern1_1 == 8 {
1211                 // Rule at src/isa/aarch64/inst.isle line 939.
1212                 let expr0_0 = VectorSize::Size16x8;
1213                 return Some(expr0_0);
1214             }
1215         }
1216         if pattern1_0 == 32 {
1217             if pattern1_1 == 4 {
1218                 // Rule at src/isa/aarch64/inst.isle line 940.
1219                 let expr0_0 = VectorSize::Size32x4;
1220                 return Some(expr0_0);
1221             }
1222         }
1223         if pattern1_0 == 64 {
1224             if pattern1_1 == 2 {
1225                 // Rule at src/isa/aarch64/inst.isle line 941.
1226                 let expr0_0 = VectorSize::Size64x2;
1227                 return Some(expr0_0);
1228             }
1229         }
1230     }
1231     return None;
1232 }
1233 
1234 // Generated as internal constructor for term movz.
1235 pub fn constructor_movz<C: Context>(
1236     ctx: &mut C,
1237     arg0: MoveWideConst,
1238     arg1: &OperandSize,
1239 ) -> Option<Reg> {
1240     let pattern0_0 = arg0;
1241     let pattern1_0 = arg1;
1242     // Rule at src/isa/aarch64/inst.isle line 1363.
1243     let expr0_0: Type = I64;
1244     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1245     let expr2_0 = MInst::MovZ {
1246         rd: expr1_0,
1247         imm: pattern0_0,
1248         size: pattern1_0.clone(),
1249     };
1250     let expr3_0 = C::emit(ctx, &expr2_0);
1251     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1252     return Some(expr4_0);
1253 }
1254 
1255 // Generated as internal constructor for term movn.
1256 pub fn constructor_movn<C: Context>(
1257     ctx: &mut C,
1258     arg0: MoveWideConst,
1259     arg1: &OperandSize,
1260 ) -> Option<Reg> {
1261     let pattern0_0 = arg0;
1262     let pattern1_0 = arg1;
1263     // Rule at src/isa/aarch64/inst.isle line 1370.
1264     let expr0_0: Type = I64;
1265     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1266     let expr2_0 = MInst::MovN {
1267         rd: expr1_0,
1268         imm: pattern0_0,
1269         size: pattern1_0.clone(),
1270     };
1271     let expr3_0 = C::emit(ctx, &expr2_0);
1272     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1273     return Some(expr4_0);
1274 }
1275 
1276 // Generated as internal constructor for term alu_rr_imm_logic.
1277 pub fn constructor_alu_rr_imm_logic<C: Context>(
1278     ctx: &mut C,
1279     arg0: &ALUOp,
1280     arg1: Type,
1281     arg2: Reg,
1282     arg3: ImmLogic,
1283 ) -> Option<Reg> {
1284     let pattern0_0 = arg0;
1285     let pattern1_0 = arg1;
1286     let pattern2_0 = arg2;
1287     let pattern3_0 = arg3;
1288     // Rule at src/isa/aarch64/inst.isle line 1377.
1289     let expr0_0: Type = I64;
1290     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1291     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1292     let expr3_0 = MInst::AluRRImmLogic {
1293         alu_op: pattern0_0.clone(),
1294         size: expr2_0,
1295         rd: expr1_0,
1296         rn: pattern2_0,
1297         imml: pattern3_0,
1298     };
1299     let expr4_0 = C::emit(ctx, &expr3_0);
1300     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1301     return Some(expr5_0);
1302 }
1303 
1304 // Generated as internal constructor for term alu_rr_imm_shift.
1305 pub fn constructor_alu_rr_imm_shift<C: Context>(
1306     ctx: &mut C,
1307     arg0: &ALUOp,
1308     arg1: Type,
1309     arg2: Reg,
1310     arg3: ImmShift,
1311 ) -> Option<Reg> {
1312     let pattern0_0 = arg0;
1313     let pattern1_0 = arg1;
1314     let pattern2_0 = arg2;
1315     let pattern3_0 = arg3;
1316     // Rule at src/isa/aarch64/inst.isle line 1384.
1317     let expr0_0: Type = I64;
1318     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1319     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1320     let expr3_0 = MInst::AluRRImmShift {
1321         alu_op: pattern0_0.clone(),
1322         size: expr2_0,
1323         rd: expr1_0,
1324         rn: pattern2_0,
1325         immshift: pattern3_0,
1326     };
1327     let expr4_0 = C::emit(ctx, &expr3_0);
1328     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1329     return Some(expr5_0);
1330 }
1331 
1332 // Generated as internal constructor for term alu_rrr.
1333 pub fn constructor_alu_rrr<C: Context>(
1334     ctx: &mut C,
1335     arg0: &ALUOp,
1336     arg1: Type,
1337     arg2: Reg,
1338     arg3: Reg,
1339 ) -> Option<Reg> {
1340     let pattern0_0 = arg0;
1341     let pattern1_0 = arg1;
1342     let pattern2_0 = arg2;
1343     let pattern3_0 = arg3;
1344     // Rule at src/isa/aarch64/inst.isle line 1391.
1345     let expr0_0: Type = I64;
1346     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1347     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1348     let expr3_0 = MInst::AluRRR {
1349         alu_op: pattern0_0.clone(),
1350         size: expr2_0,
1351         rd: expr1_0,
1352         rn: pattern2_0,
1353         rm: pattern3_0,
1354     };
1355     let expr4_0 = C::emit(ctx, &expr3_0);
1356     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1357     return Some(expr5_0);
1358 }
1359 
1360 // Generated as internal constructor for term vec_rrr.
1361 pub fn constructor_vec_rrr<C: Context>(
1362     ctx: &mut C,
1363     arg0: &VecALUOp,
1364     arg1: Reg,
1365     arg2: Reg,
1366     arg3: &VectorSize,
1367 ) -> Option<Reg> {
1368     let pattern0_0 = arg0;
1369     let pattern1_0 = arg1;
1370     let pattern2_0 = arg2;
1371     let pattern3_0 = arg3;
1372     // Rule at src/isa/aarch64/inst.isle line 1398.
1373     let expr0_0: Type = I8X16;
1374     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1375     let expr2_0 = MInst::VecRRR {
1376         alu_op: pattern0_0.clone(),
1377         rd: expr1_0,
1378         rn: pattern1_0,
1379         rm: pattern2_0,
1380         size: pattern3_0.clone(),
1381     };
1382     let expr3_0 = C::emit(ctx, &expr2_0);
1383     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1384     return Some(expr4_0);
1385 }
1386 
1387 // Generated as internal constructor for term vec_lanes.
1388 pub fn constructor_vec_lanes<C: Context>(
1389     ctx: &mut C,
1390     arg0: &VecLanesOp,
1391     arg1: Reg,
1392     arg2: &VectorSize,
1393 ) -> Option<Reg> {
1394     let pattern0_0 = arg0;
1395     let pattern1_0 = arg1;
1396     let pattern2_0 = arg2;
1397     // Rule at src/isa/aarch64/inst.isle line 1405.
1398     let expr0_0: Type = I8X16;
1399     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1400     let expr2_0 = MInst::VecLanes {
1401         op: pattern0_0.clone(),
1402         rd: expr1_0,
1403         rn: pattern1_0,
1404         size: pattern2_0.clone(),
1405     };
1406     let expr3_0 = C::emit(ctx, &expr2_0);
1407     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1408     return Some(expr4_0);
1409 }
1410 
1411 // Generated as internal constructor for term vec_dup.
1412 pub fn constructor_vec_dup<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
1413     let pattern0_0 = arg0;
1414     let pattern1_0 = arg1;
1415     // Rule at src/isa/aarch64/inst.isle line 1412.
1416     let expr0_0: Type = I8X16;
1417     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1418     let expr2_0 = MInst::VecDup {
1419         rd: expr1_0,
1420         rn: pattern0_0,
1421         size: pattern1_0.clone(),
1422     };
1423     let expr3_0 = C::emit(ctx, &expr2_0);
1424     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1425     return Some(expr4_0);
1426 }
1427 
1428 // Generated as internal constructor for term alu_rr_imm12.
1429 pub fn constructor_alu_rr_imm12<C: Context>(
1430     ctx: &mut C,
1431     arg0: &ALUOp,
1432     arg1: Type,
1433     arg2: Reg,
1434     arg3: Imm12,
1435 ) -> Option<Reg> {
1436     let pattern0_0 = arg0;
1437     let pattern1_0 = arg1;
1438     let pattern2_0 = arg2;
1439     let pattern3_0 = arg3;
1440     // Rule at src/isa/aarch64/inst.isle line 1419.
1441     let expr0_0: Type = I64;
1442     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1443     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1444     let expr3_0 = MInst::AluRRImm12 {
1445         alu_op: pattern0_0.clone(),
1446         size: expr2_0,
1447         rd: expr1_0,
1448         rn: pattern2_0,
1449         imm12: pattern3_0,
1450     };
1451     let expr4_0 = C::emit(ctx, &expr3_0);
1452     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1453     return Some(expr5_0);
1454 }
1455 
1456 // Generated as internal constructor for term alu_rrr_shift.
1457 pub fn constructor_alu_rrr_shift<C: Context>(
1458     ctx: &mut C,
1459     arg0: &ALUOp,
1460     arg1: Type,
1461     arg2: Reg,
1462     arg3: Reg,
1463     arg4: ShiftOpAndAmt,
1464 ) -> Option<Reg> {
1465     let pattern0_0 = arg0;
1466     let pattern1_0 = arg1;
1467     let pattern2_0 = arg2;
1468     let pattern3_0 = arg3;
1469     let pattern4_0 = arg4;
1470     // Rule at src/isa/aarch64/inst.isle line 1426.
1471     let expr0_0: Type = I64;
1472     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1473     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1474     let expr3_0 = MInst::AluRRRShift {
1475         alu_op: pattern0_0.clone(),
1476         size: expr2_0,
1477         rd: expr1_0,
1478         rn: pattern2_0,
1479         rm: pattern3_0,
1480         shiftop: pattern4_0,
1481     };
1482     let expr4_0 = C::emit(ctx, &expr3_0);
1483     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1484     return Some(expr5_0);
1485 }
1486 
1487 // Generated as internal constructor for term alu_rrr_extend.
1488 pub fn constructor_alu_rrr_extend<C: Context>(
1489     ctx: &mut C,
1490     arg0: &ALUOp,
1491     arg1: Type,
1492     arg2: Reg,
1493     arg3: Reg,
1494     arg4: &ExtendOp,
1495 ) -> Option<Reg> {
1496     let pattern0_0 = arg0;
1497     let pattern1_0 = arg1;
1498     let pattern2_0 = arg2;
1499     let pattern3_0 = arg3;
1500     let pattern4_0 = arg4;
1501     // Rule at src/isa/aarch64/inst.isle line 1433.
1502     let expr0_0: Type = I64;
1503     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1504     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1505     let expr3_0 = MInst::AluRRRExtend {
1506         alu_op: pattern0_0.clone(),
1507         size: expr2_0,
1508         rd: expr1_0,
1509         rn: pattern2_0,
1510         rm: pattern3_0,
1511         extendop: pattern4_0.clone(),
1512     };
1513     let expr4_0 = C::emit(ctx, &expr3_0);
1514     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1515     return Some(expr5_0);
1516 }
1517 
1518 // Generated as internal constructor for term alu_rr_extend_reg.
1519 pub fn constructor_alu_rr_extend_reg<C: Context>(
1520     ctx: &mut C,
1521     arg0: &ALUOp,
1522     arg1: Type,
1523     arg2: Reg,
1524     arg3: &ExtendedValue,
1525 ) -> Option<Reg> {
1526     let pattern0_0 = arg0;
1527     let pattern1_0 = arg1;
1528     let pattern2_0 = arg2;
1529     let pattern3_0 = arg3;
1530     // Rule at src/isa/aarch64/inst.isle line 1441.
1531     let expr0_0 = C::put_extended_in_reg(ctx, pattern3_0);
1532     let expr1_0 = C::get_extended_op(ctx, pattern3_0);
1533     let expr2_0 =
1534         constructor_alu_rrr_extend(ctx, pattern0_0, pattern1_0, pattern2_0, expr0_0, &expr1_0)?;
1535     return Some(expr2_0);
1536 }
1537 
1538 // Generated as internal constructor for term alu_rrrr.
1539 pub fn constructor_alu_rrrr<C: Context>(
1540     ctx: &mut C,
1541     arg0: &ALUOp3,
1542     arg1: Reg,
1543     arg2: Reg,
1544     arg3: Reg,
1545 ) -> Option<Reg> {
1546     let pattern0_0 = arg0;
1547     let pattern1_0 = arg1;
1548     let pattern2_0 = arg2;
1549     let pattern3_0 = arg3;
1550     // Rule at src/isa/aarch64/inst.isle line 1448.
1551     let expr0_0: Type = I64;
1552     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1553     let expr2_0 = MInst::AluRRRR {
1554         alu_op: pattern0_0.clone(),
1555         rd: expr1_0,
1556         rn: pattern1_0,
1557         rm: pattern2_0,
1558         ra: pattern3_0,
1559     };
1560     let expr3_0 = C::emit(ctx, &expr2_0);
1561     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1562     return Some(expr4_0);
1563 }
1564 
1565 // Generated as internal constructor for term bit_rr.
1566 pub fn constructor_bit_rr<C: Context>(
1567     ctx: &mut C,
1568     arg0: &BitOp,
1569     arg1: Type,
1570     arg2: Reg,
1571 ) -> Option<Reg> {
1572     let pattern0_0 = arg0;
1573     let pattern1_0 = arg1;
1574     let pattern2_0 = arg2;
1575     // Rule at src/isa/aarch64/inst.isle line 1455.
1576     let expr0_0: Type = I64;
1577     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1578     let expr2_0 = constructor_operand_size(ctx, pattern1_0)?;
1579     let expr3_0 = MInst::BitRR {
1580         op: pattern0_0.clone(),
1581         size: expr2_0,
1582         rd: expr1_0,
1583         rn: pattern2_0,
1584     };
1585     let expr4_0 = C::emit(ctx, &expr3_0);
1586     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1587     return Some(expr5_0);
1588 }
1589 
1590 // Generated as internal constructor for term add_with_flags_paired.
1591 pub fn constructor_add_with_flags_paired<C: Context>(
1592     ctx: &mut C,
1593     arg0: Type,
1594     arg1: Reg,
1595     arg2: Reg,
1596 ) -> Option<ProducesFlags> {
1597     let pattern0_0 = arg0;
1598     let pattern1_0 = arg1;
1599     let pattern2_0 = arg2;
1600     // Rule at src/isa/aarch64/inst.isle line 1462.
1601     let expr0_0: Type = I64;
1602     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1603     let expr2_0 = ALUOp::AddS;
1604     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1605     let expr4_0 = MInst::AluRRR {
1606         alu_op: expr2_0,
1607         size: expr3_0,
1608         rd: expr1_0,
1609         rn: pattern1_0,
1610         rm: pattern2_0,
1611     };
1612     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1613     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1614         inst: expr4_0,
1615         result: expr5_0,
1616     };
1617     return Some(expr6_0);
1618 }
1619 
1620 // Generated as internal constructor for term adc_paired.
1621 pub fn constructor_adc_paired<C: Context>(
1622     ctx: &mut C,
1623     arg0: Type,
1624     arg1: Reg,
1625     arg2: Reg,
1626 ) -> Option<ConsumesFlags> {
1627     let pattern0_0 = arg0;
1628     let pattern1_0 = arg1;
1629     let pattern2_0 = arg2;
1630     // Rule at src/isa/aarch64/inst.isle line 1470.
1631     let expr0_0: Type = I64;
1632     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1633     let expr2_0 = ALUOp::Adc;
1634     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1635     let expr4_0 = MInst::AluRRR {
1636         alu_op: expr2_0,
1637         size: expr3_0,
1638         rd: expr1_0,
1639         rn: pattern1_0,
1640         rm: pattern2_0,
1641     };
1642     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1643     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1644         inst: expr4_0,
1645         result: expr5_0,
1646     };
1647     return Some(expr6_0);
1648 }
1649 
1650 // Generated as internal constructor for term sub_with_flags_paired.
1651 pub fn constructor_sub_with_flags_paired<C: Context>(
1652     ctx: &mut C,
1653     arg0: Type,
1654     arg1: Reg,
1655     arg2: Reg,
1656 ) -> Option<ProducesFlags> {
1657     let pattern0_0 = arg0;
1658     let pattern1_0 = arg1;
1659     let pattern2_0 = arg2;
1660     // Rule at src/isa/aarch64/inst.isle line 1478.
1661     let expr0_0: Type = I64;
1662     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1663     let expr2_0 = ALUOp::SubS;
1664     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1665     let expr4_0 = MInst::AluRRR {
1666         alu_op: expr2_0,
1667         size: expr3_0,
1668         rd: expr1_0,
1669         rn: pattern1_0,
1670         rm: pattern2_0,
1671     };
1672     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1673     let expr6_0 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer {
1674         inst: expr4_0,
1675         result: expr5_0,
1676     };
1677     return Some(expr6_0);
1678 }
1679 
1680 // Generated as internal constructor for term cmp64_imm.
1681 pub fn constructor_cmp64_imm<C: Context>(
1682     ctx: &mut C,
1683     arg0: Reg,
1684     arg1: Imm12,
1685 ) -> Option<ProducesFlags> {
1686     let pattern0_0 = arg0;
1687     let pattern1_0 = arg1;
1688     // Rule at src/isa/aarch64/inst.isle line 1485.
1689     let expr0_0 = ALUOp::SubS;
1690     let expr1_0 = OperandSize::Size64;
1691     let expr2_0 = C::writable_zero_reg(ctx);
1692     let expr3_0 = MInst::AluRRImm12 {
1693         alu_op: expr0_0,
1694         size: expr1_0,
1695         rd: expr2_0,
1696         rn: pattern0_0,
1697         imm12: pattern1_0,
1698     };
1699     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
1700     return Some(expr4_0);
1701 }
1702 
1703 // Generated as internal constructor for term sbc_paired.
1704 pub fn constructor_sbc_paired<C: Context>(
1705     ctx: &mut C,
1706     arg0: Type,
1707     arg1: Reg,
1708     arg2: Reg,
1709 ) -> Option<ConsumesFlags> {
1710     let pattern0_0 = arg0;
1711     let pattern1_0 = arg1;
1712     let pattern2_0 = arg2;
1713     // Rule at src/isa/aarch64/inst.isle line 1492.
1714     let expr0_0: Type = I64;
1715     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1716     let expr2_0 = ALUOp::Sbc;
1717     let expr3_0 = constructor_operand_size(ctx, pattern0_0)?;
1718     let expr4_0 = MInst::AluRRR {
1719         alu_op: expr2_0,
1720         size: expr3_0,
1721         rd: expr1_0,
1722         rn: pattern1_0,
1723         rm: pattern2_0,
1724     };
1725     let expr5_0 = C::writable_reg_to_reg(ctx, expr1_0);
1726     let expr6_0 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer {
1727         inst: expr4_0,
1728         result: expr5_0,
1729     };
1730     return Some(expr6_0);
1731 }
1732 
1733 // Generated as internal constructor for term vec_misc.
1734 pub fn constructor_vec_misc<C: Context>(
1735     ctx: &mut C,
1736     arg0: &VecMisc2,
1737     arg1: Reg,
1738     arg2: &VectorSize,
1739 ) -> Option<Reg> {
1740     let pattern0_0 = arg0;
1741     let pattern1_0 = arg1;
1742     let pattern2_0 = arg2;
1743     // Rule at src/isa/aarch64/inst.isle line 1500.
1744     let expr0_0: Type = I8X16;
1745     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1746     let expr2_0 = MInst::VecMisc {
1747         op: pattern0_0.clone(),
1748         rd: expr1_0,
1749         rn: pattern1_0,
1750         size: pattern2_0.clone(),
1751     };
1752     let expr3_0 = C::emit(ctx, &expr2_0);
1753     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1754     return Some(expr4_0);
1755 }
1756 
1757 // Generated as internal constructor for term vec_rrr_long.
1758 pub fn constructor_vec_rrr_long<C: Context>(
1759     ctx: &mut C,
1760     arg0: &VecRRRLongOp,
1761     arg1: Reg,
1762     arg2: Reg,
1763     arg3: bool,
1764 ) -> Option<Reg> {
1765     let pattern0_0 = arg0;
1766     let pattern1_0 = arg1;
1767     let pattern2_0 = arg2;
1768     let pattern3_0 = arg3;
1769     // Rule at src/isa/aarch64/inst.isle line 1507.
1770     let expr0_0: Type = I8X16;
1771     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1772     let expr2_0 = MInst::VecRRRLong {
1773         alu_op: pattern0_0.clone(),
1774         rd: expr1_0,
1775         rn: pattern1_0,
1776         rm: pattern2_0,
1777         high_half: pattern3_0,
1778     };
1779     let expr3_0 = C::emit(ctx, &expr2_0);
1780     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1781     return Some(expr4_0);
1782 }
1783 
1784 // Generated as internal constructor for term vec_rrrr_long.
1785 pub fn constructor_vec_rrrr_long<C: Context>(
1786     ctx: &mut C,
1787     arg0: &VecRRRLongOp,
1788     arg1: Reg,
1789     arg2: Reg,
1790     arg3: Reg,
1791     arg4: bool,
1792 ) -> Option<Reg> {
1793     let pattern0_0 = arg0;
1794     let pattern1_0 = arg1;
1795     let pattern2_0 = arg2;
1796     let pattern3_0 = arg3;
1797     let pattern4_0 = arg4;
1798     // Rule at src/isa/aarch64/inst.isle line 1517.
1799     let expr0_0: Type = I8X16;
1800     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1801     let expr2_0 = MInst::FpuMove128 {
1802         rd: expr1_0,
1803         rn: pattern1_0,
1804     };
1805     let expr3_0 = C::emit(ctx, &expr2_0);
1806     let expr4_0 = MInst::VecRRRLong {
1807         alu_op: pattern0_0.clone(),
1808         rd: expr1_0,
1809         rn: pattern2_0,
1810         rm: pattern3_0,
1811         high_half: pattern4_0,
1812     };
1813     let expr5_0 = C::emit(ctx, &expr4_0);
1814     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1815     return Some(expr6_0);
1816 }
1817 
1818 // Generated as internal constructor for term vec_rr_narrow.
1819 pub fn constructor_vec_rr_narrow<C: Context>(
1820     ctx: &mut C,
1821     arg0: &VecRRNarrowOp,
1822     arg1: Reg,
1823     arg2: bool,
1824 ) -> Option<Reg> {
1825     let pattern0_0 = arg0;
1826     let pattern1_0 = arg1;
1827     let pattern2_0 = arg2;
1828     // Rule at src/isa/aarch64/inst.isle line 1525.
1829     let expr0_0: Type = I8X16;
1830     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1831     let expr2_0 = MInst::VecRRNarrow {
1832         op: pattern0_0.clone(),
1833         rd: expr1_0,
1834         rn: pattern1_0,
1835         high_half: pattern2_0,
1836     };
1837     let expr3_0 = C::emit(ctx, &expr2_0);
1838     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1839     return Some(expr4_0);
1840 }
1841 
1842 // Generated as internal constructor for term vec_rr_long.
1843 pub fn constructor_vec_rr_long<C: Context>(
1844     ctx: &mut C,
1845     arg0: &VecRRLongOp,
1846     arg1: Reg,
1847     arg2: bool,
1848 ) -> Option<Reg> {
1849     let pattern0_0 = arg0;
1850     let pattern1_0 = arg1;
1851     let pattern2_0 = arg2;
1852     // Rule at src/isa/aarch64/inst.isle line 1532.
1853     let expr0_0: Type = I8X16;
1854     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1855     let expr2_0 = MInst::VecRRLong {
1856         op: pattern0_0.clone(),
1857         rd: expr1_0,
1858         rn: pattern1_0,
1859         high_half: pattern2_0,
1860     };
1861     let expr3_0 = C::emit(ctx, &expr2_0);
1862     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1863     return Some(expr4_0);
1864 }
1865 
1866 // Generated as internal constructor for term mov_to_fpu.
1867 pub fn constructor_mov_to_fpu<C: Context>(
1868     ctx: &mut C,
1869     arg0: Reg,
1870     arg1: &ScalarSize,
1871 ) -> Option<Reg> {
1872     let pattern0_0 = arg0;
1873     let pattern1_0 = arg1;
1874     // Rule at src/isa/aarch64/inst.isle line 1539.
1875     let expr0_0: Type = I8X16;
1876     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1877     let expr2_0 = MInst::MovToFpu {
1878         rd: expr1_0,
1879         rn: pattern0_0,
1880         size: pattern1_0.clone(),
1881     };
1882     let expr3_0 = C::emit(ctx, &expr2_0);
1883     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1884     return Some(expr4_0);
1885 }
1886 
1887 // Generated as internal constructor for term mov_to_vec.
1888 pub fn constructor_mov_to_vec<C: Context>(
1889     ctx: &mut C,
1890     arg0: Reg,
1891     arg1: Reg,
1892     arg2: u8,
1893     arg3: &VectorSize,
1894 ) -> Option<Reg> {
1895     let pattern0_0 = arg0;
1896     let pattern1_0 = arg1;
1897     let pattern2_0 = arg2;
1898     let pattern3_0 = arg3;
1899     // Rule at src/isa/aarch64/inst.isle line 1546.
1900     let expr0_0: Type = I8X16;
1901     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1902     let expr2_0 = MInst::FpuMove128 {
1903         rd: expr1_0,
1904         rn: pattern0_0,
1905     };
1906     let expr3_0 = C::emit(ctx, &expr2_0);
1907     let expr4_0 = MInst::MovToVec {
1908         rd: expr1_0,
1909         rn: pattern1_0,
1910         idx: pattern2_0,
1911         size: pattern3_0.clone(),
1912     };
1913     let expr5_0 = C::emit(ctx, &expr4_0);
1914     let expr6_0 = C::writable_reg_to_reg(ctx, expr1_0);
1915     return Some(expr6_0);
1916 }
1917 
1918 // Generated as internal constructor for term mov_from_vec.
1919 pub fn constructor_mov_from_vec<C: Context>(
1920     ctx: &mut C,
1921     arg0: Reg,
1922     arg1: u8,
1923     arg2: &VectorSize,
1924 ) -> Option<Reg> {
1925     let pattern0_0 = arg0;
1926     let pattern1_0 = arg1;
1927     let pattern2_0 = arg2;
1928     // Rule at src/isa/aarch64/inst.isle line 1554.
1929     let expr0_0: Type = I64;
1930     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1931     let expr2_0 = MInst::MovFromVec {
1932         rd: expr1_0,
1933         rn: pattern0_0,
1934         idx: pattern1_0,
1935         size: pattern2_0.clone(),
1936     };
1937     let expr3_0 = C::emit(ctx, &expr2_0);
1938     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1939     return Some(expr4_0);
1940 }
1941 
1942 // Generated as internal constructor for term mov_from_vec_signed.
1943 pub fn constructor_mov_from_vec_signed<C: Context>(
1944     ctx: &mut C,
1945     arg0: Reg,
1946     arg1: u8,
1947     arg2: &VectorSize,
1948     arg3: &OperandSize,
1949 ) -> Option<Reg> {
1950     let pattern0_0 = arg0;
1951     let pattern1_0 = arg1;
1952     let pattern2_0 = arg2;
1953     let pattern3_0 = arg3;
1954     // Rule at src/isa/aarch64/inst.isle line 1561.
1955     let expr0_0: Type = I64;
1956     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1957     let expr2_0 = MInst::MovFromVecSigned {
1958         rd: expr1_0,
1959         rn: pattern0_0,
1960         idx: pattern1_0,
1961         size: pattern2_0.clone(),
1962         scalar_size: pattern3_0.clone(),
1963     };
1964     let expr3_0 = C::emit(ctx, &expr2_0);
1965     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1966     return Some(expr4_0);
1967 }
1968 
1969 // Generated as internal constructor for term extend.
1970 pub fn constructor_extend<C: Context>(
1971     ctx: &mut C,
1972     arg0: Reg,
1973     arg1: bool,
1974     arg2: u8,
1975     arg3: u8,
1976 ) -> Option<Reg> {
1977     let pattern0_0 = arg0;
1978     let pattern1_0 = arg1;
1979     let pattern2_0 = arg2;
1980     let pattern3_0 = arg3;
1981     // Rule at src/isa/aarch64/inst.isle line 1568.
1982     let expr0_0: Type = I64;
1983     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
1984     let expr2_0 = MInst::Extend {
1985         rd: expr1_0,
1986         rn: pattern0_0,
1987         signed: pattern1_0,
1988         from_bits: pattern2_0,
1989         to_bits: pattern3_0,
1990     };
1991     let expr3_0 = C::emit(ctx, &expr2_0);
1992     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
1993     return Some(expr4_0);
1994 }
1995 
1996 // Generated as internal constructor for term load_acquire.
1997 pub fn constructor_load_acquire<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
1998     let pattern0_0 = arg0;
1999     let pattern1_0 = arg1;
2000     // Rule at src/isa/aarch64/inst.isle line 1575.
2001     let expr0_0: Type = I64;
2002     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2003     let expr2_0 = MInst::LoadAcquire {
2004         access_ty: pattern0_0,
2005         rt: expr1_0,
2006         rn: pattern1_0,
2007     };
2008     let expr3_0 = C::emit(ctx, &expr2_0);
2009     let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0);
2010     return Some(expr4_0);
2011 }
2012 
2013 // Generated as internal constructor for term tst_imm.
2014 pub fn constructor_tst_imm<C: Context>(
2015     ctx: &mut C,
2016     arg0: Type,
2017     arg1: Reg,
2018     arg2: ImmLogic,
2019 ) -> Option<ProducesFlags> {
2020     let pattern0_0 = arg0;
2021     let pattern1_0 = arg1;
2022     let pattern2_0 = arg2;
2023     // Rule at src/isa/aarch64/inst.isle line 1585.
2024     let expr0_0 = ALUOp::AndS;
2025     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
2026     let expr2_0 = C::writable_zero_reg(ctx);
2027     let expr3_0 = MInst::AluRRImmLogic {
2028         alu_op: expr0_0,
2029         size: expr1_0,
2030         rd: expr2_0,
2031         rn: pattern1_0,
2032         imml: pattern2_0,
2033     };
2034     let expr4_0 = ProducesFlags::ProducesFlagsSideEffect { inst: expr3_0 };
2035     return Some(expr4_0);
2036 }
2037 
2038 // Generated as internal constructor for term csel.
2039 pub fn constructor_csel<C: Context>(
2040     ctx: &mut C,
2041     arg0: &Cond,
2042     arg1: Reg,
2043     arg2: Reg,
2044 ) -> Option<ConsumesFlags> {
2045     let pattern0_0 = arg0;
2046     let pattern1_0 = arg1;
2047     let pattern2_0 = arg2;
2048     // Rule at src/isa/aarch64/inst.isle line 1599.
2049     let expr0_0: Type = I64;
2050     let expr1_0 = C::temp_writable_reg(ctx, expr0_0);
2051     let expr2_0 = MInst::CSel {
2052         rd: expr1_0,
2053         cond: pattern0_0.clone(),
2054         rn: pattern1_0,
2055         rm: pattern2_0,
2056     };
2057     let expr3_0 = C::writable_reg_to_reg(ctx, expr1_0);
2058     let expr4_0 = ConsumesFlags::ConsumesFlagsReturnsReg {
2059         inst: expr2_0,
2060         result: expr3_0,
2061     };
2062     return Some(expr4_0);
2063 }
2064 
2065 // Generated as internal constructor for term add.
2066 pub fn constructor_add<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2067     let pattern0_0 = arg0;
2068     let pattern1_0 = arg1;
2069     let pattern2_0 = arg2;
2070     // Rule at src/isa/aarch64/inst.isle line 1608.
2071     let expr0_0 = ALUOp::Add;
2072     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2073     return Some(expr1_0);
2074 }
2075 
2076 // Generated as internal constructor for term add_imm.
2077 pub fn constructor_add_imm<C: Context>(
2078     ctx: &mut C,
2079     arg0: Type,
2080     arg1: Reg,
2081     arg2: Imm12,
2082 ) -> Option<Reg> {
2083     let pattern0_0 = arg0;
2084     let pattern1_0 = arg1;
2085     let pattern2_0 = arg2;
2086     // Rule at src/isa/aarch64/inst.isle line 1611.
2087     let expr0_0 = ALUOp::Add;
2088     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2089     return Some(expr1_0);
2090 }
2091 
2092 // Generated as internal constructor for term add_extend.
2093 pub fn constructor_add_extend<C: Context>(
2094     ctx: &mut C,
2095     arg0: Type,
2096     arg1: Reg,
2097     arg2: &ExtendedValue,
2098 ) -> Option<Reg> {
2099     let pattern0_0 = arg0;
2100     let pattern1_0 = arg1;
2101     let pattern2_0 = arg2;
2102     // Rule at src/isa/aarch64/inst.isle line 1614.
2103     let expr0_0 = ALUOp::Add;
2104     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2105     return Some(expr1_0);
2106 }
2107 
2108 // Generated as internal constructor for term add_shift.
2109 pub fn constructor_add_shift<C: Context>(
2110     ctx: &mut C,
2111     arg0: Type,
2112     arg1: Reg,
2113     arg2: Reg,
2114     arg3: ShiftOpAndAmt,
2115 ) -> Option<Reg> {
2116     let pattern0_0 = arg0;
2117     let pattern1_0 = arg1;
2118     let pattern2_0 = arg2;
2119     let pattern3_0 = arg3;
2120     // Rule at src/isa/aarch64/inst.isle line 1617.
2121     let expr0_0 = ALUOp::Add;
2122     let expr1_0 = constructor_alu_rrr_shift(
2123         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2124     )?;
2125     return Some(expr1_0);
2126 }
2127 
2128 // Generated as internal constructor for term add_vec.
2129 pub fn constructor_add_vec<C: Context>(
2130     ctx: &mut C,
2131     arg0: Reg,
2132     arg1: Reg,
2133     arg2: &VectorSize,
2134 ) -> Option<Reg> {
2135     let pattern0_0 = arg0;
2136     let pattern1_0 = arg1;
2137     let pattern2_0 = arg2;
2138     // Rule at src/isa/aarch64/inst.isle line 1620.
2139     let expr0_0 = VecALUOp::Add;
2140     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2141     return Some(expr1_0);
2142 }
2143 
2144 // Generated as internal constructor for term sub.
2145 pub fn constructor_sub<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2146     let pattern0_0 = arg0;
2147     let pattern1_0 = arg1;
2148     let pattern2_0 = arg2;
2149     // Rule at src/isa/aarch64/inst.isle line 1625.
2150     let expr0_0 = ALUOp::Sub;
2151     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2152     return Some(expr1_0);
2153 }
2154 
2155 // Generated as internal constructor for term sub_imm.
2156 pub fn constructor_sub_imm<C: Context>(
2157     ctx: &mut C,
2158     arg0: Type,
2159     arg1: Reg,
2160     arg2: Imm12,
2161 ) -> Option<Reg> {
2162     let pattern0_0 = arg0;
2163     let pattern1_0 = arg1;
2164     let pattern2_0 = arg2;
2165     // Rule at src/isa/aarch64/inst.isle line 1628.
2166     let expr0_0 = ALUOp::Sub;
2167     let expr1_0 = constructor_alu_rr_imm12(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2168     return Some(expr1_0);
2169 }
2170 
2171 // Generated as internal constructor for term sub_extend.
2172 pub fn constructor_sub_extend<C: Context>(
2173     ctx: &mut C,
2174     arg0: Type,
2175     arg1: Reg,
2176     arg2: &ExtendedValue,
2177 ) -> Option<Reg> {
2178     let pattern0_0 = arg0;
2179     let pattern1_0 = arg1;
2180     let pattern2_0 = arg2;
2181     // Rule at src/isa/aarch64/inst.isle line 1631.
2182     let expr0_0 = ALUOp::Sub;
2183     let expr1_0 = constructor_alu_rr_extend_reg(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2184     return Some(expr1_0);
2185 }
2186 
2187 // Generated as internal constructor for term sub_shift.
2188 pub fn constructor_sub_shift<C: Context>(
2189     ctx: &mut C,
2190     arg0: Type,
2191     arg1: Reg,
2192     arg2: Reg,
2193     arg3: ShiftOpAndAmt,
2194 ) -> Option<Reg> {
2195     let pattern0_0 = arg0;
2196     let pattern1_0 = arg1;
2197     let pattern2_0 = arg2;
2198     let pattern3_0 = arg3;
2199     // Rule at src/isa/aarch64/inst.isle line 1634.
2200     let expr0_0 = ALUOp::Sub;
2201     let expr1_0 = constructor_alu_rrr_shift(
2202         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2203     )?;
2204     return Some(expr1_0);
2205 }
2206 
2207 // Generated as internal constructor for term sub_vec.
2208 pub fn constructor_sub_vec<C: Context>(
2209     ctx: &mut C,
2210     arg0: Reg,
2211     arg1: Reg,
2212     arg2: &VectorSize,
2213 ) -> Option<Reg> {
2214     let pattern0_0 = arg0;
2215     let pattern1_0 = arg1;
2216     let pattern2_0 = arg2;
2217     // Rule at src/isa/aarch64/inst.isle line 1637.
2218     let expr0_0 = VecALUOp::Sub;
2219     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2220     return Some(expr1_0);
2221 }
2222 
2223 // Generated as internal constructor for term madd.
2224 pub fn constructor_madd<C: Context>(
2225     ctx: &mut C,
2226     arg0: Type,
2227     arg1: Reg,
2228     arg2: Reg,
2229     arg3: Reg,
2230 ) -> Option<Reg> {
2231     let pattern0_0 = arg0;
2232     if pattern0_0 == I64 {
2233         let pattern2_0 = arg1;
2234         let pattern3_0 = arg2;
2235         let pattern4_0 = arg3;
2236         // Rule at src/isa/aarch64/inst.isle line 1643.
2237         let expr0_0 = constructor_madd64(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2238         return Some(expr0_0);
2239     }
2240     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
2241         let pattern2_0 = arg1;
2242         let pattern3_0 = arg2;
2243         let pattern4_0 = arg3;
2244         // Rule at src/isa/aarch64/inst.isle line 1642.
2245         let expr0_0 = constructor_madd32(ctx, pattern2_0, pattern3_0, pattern4_0)?;
2246         return Some(expr0_0);
2247     }
2248     return None;
2249 }
2250 
2251 // Generated as internal constructor for term madd32.
2252 pub fn constructor_madd32<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2253     let pattern0_0 = arg0;
2254     let pattern1_0 = arg1;
2255     let pattern2_0 = arg2;
2256     // Rule at src/isa/aarch64/inst.isle line 1646.
2257     let expr0_0 = ALUOp3::MAdd32;
2258     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2259     return Some(expr1_0);
2260 }
2261 
2262 // Generated as internal constructor for term madd64.
2263 pub fn constructor_madd64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2264     let pattern0_0 = arg0;
2265     let pattern1_0 = arg1;
2266     let pattern2_0 = arg2;
2267     // Rule at src/isa/aarch64/inst.isle line 1649.
2268     let expr0_0 = ALUOp3::MAdd64;
2269     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2270     return Some(expr1_0);
2271 }
2272 
2273 // Generated as internal constructor for term msub64.
2274 pub fn constructor_msub64<C: Context>(ctx: &mut C, arg0: Reg, arg1: Reg, arg2: Reg) -> Option<Reg> {
2275     let pattern0_0 = arg0;
2276     let pattern1_0 = arg1;
2277     let pattern2_0 = arg2;
2278     // Rule at src/isa/aarch64/inst.isle line 1654.
2279     let expr0_0 = ALUOp3::MSub64;
2280     let expr1_0 = constructor_alu_rrrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2281     return Some(expr1_0);
2282 }
2283 
2284 // Generated as internal constructor for term uqadd.
2285 pub fn constructor_uqadd<C: Context>(
2286     ctx: &mut C,
2287     arg0: Reg,
2288     arg1: Reg,
2289     arg2: &VectorSize,
2290 ) -> Option<Reg> {
2291     let pattern0_0 = arg0;
2292     let pattern1_0 = arg1;
2293     let pattern2_0 = arg2;
2294     // Rule at src/isa/aarch64/inst.isle line 1658.
2295     let expr0_0 = VecALUOp::Uqadd;
2296     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2297     return Some(expr1_0);
2298 }
2299 
2300 // Generated as internal constructor for term sqadd.
2301 pub fn constructor_sqadd<C: Context>(
2302     ctx: &mut C,
2303     arg0: Reg,
2304     arg1: Reg,
2305     arg2: &VectorSize,
2306 ) -> Option<Reg> {
2307     let pattern0_0 = arg0;
2308     let pattern1_0 = arg1;
2309     let pattern2_0 = arg2;
2310     // Rule at src/isa/aarch64/inst.isle line 1662.
2311     let expr0_0 = VecALUOp::Sqadd;
2312     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2313     return Some(expr1_0);
2314 }
2315 
2316 // Generated as internal constructor for term uqsub.
2317 pub fn constructor_uqsub<C: Context>(
2318     ctx: &mut C,
2319     arg0: Reg,
2320     arg1: Reg,
2321     arg2: &VectorSize,
2322 ) -> Option<Reg> {
2323     let pattern0_0 = arg0;
2324     let pattern1_0 = arg1;
2325     let pattern2_0 = arg2;
2326     // Rule at src/isa/aarch64/inst.isle line 1666.
2327     let expr0_0 = VecALUOp::Uqsub;
2328     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2329     return Some(expr1_0);
2330 }
2331 
2332 // Generated as internal constructor for term sqsub.
2333 pub fn constructor_sqsub<C: Context>(
2334     ctx: &mut C,
2335     arg0: Reg,
2336     arg1: Reg,
2337     arg2: &VectorSize,
2338 ) -> Option<Reg> {
2339     let pattern0_0 = arg0;
2340     let pattern1_0 = arg1;
2341     let pattern2_0 = arg2;
2342     // Rule at src/isa/aarch64/inst.isle line 1670.
2343     let expr0_0 = VecALUOp::Sqsub;
2344     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2345     return Some(expr1_0);
2346 }
2347 
2348 // Generated as internal constructor for term umulh.
2349 pub fn constructor_umulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2350     let pattern0_0 = arg0;
2351     let pattern1_0 = arg1;
2352     let pattern2_0 = arg2;
2353     // Rule at src/isa/aarch64/inst.isle line 1674.
2354     let expr0_0 = ALUOp::UMulH;
2355     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2356     return Some(expr1_0);
2357 }
2358 
2359 // Generated as internal constructor for term smulh.
2360 pub fn constructor_smulh<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2361     let pattern0_0 = arg0;
2362     let pattern1_0 = arg1;
2363     let pattern2_0 = arg2;
2364     // Rule at src/isa/aarch64/inst.isle line 1678.
2365     let expr0_0 = ALUOp::SMulH;
2366     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2367     return Some(expr1_0);
2368 }
2369 
2370 // Generated as internal constructor for term mul.
2371 pub fn constructor_mul<C: Context>(
2372     ctx: &mut C,
2373     arg0: Reg,
2374     arg1: Reg,
2375     arg2: &VectorSize,
2376 ) -> Option<Reg> {
2377     let pattern0_0 = arg0;
2378     let pattern1_0 = arg1;
2379     let pattern2_0 = arg2;
2380     // Rule at src/isa/aarch64/inst.isle line 1682.
2381     let expr0_0 = VecALUOp::Mul;
2382     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2383     return Some(expr1_0);
2384 }
2385 
2386 // Generated as internal constructor for term neg.
2387 pub fn constructor_neg<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2388     let pattern0_0 = arg0;
2389     let pattern1_0 = arg1;
2390     // Rule at src/isa/aarch64/inst.isle line 1686.
2391     let expr0_0 = VecMisc2::Neg;
2392     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2393     return Some(expr1_0);
2394 }
2395 
2396 // Generated as internal constructor for term rev64.
2397 pub fn constructor_rev64<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2398     let pattern0_0 = arg0;
2399     let pattern1_0 = arg1;
2400     // Rule at src/isa/aarch64/inst.isle line 1690.
2401     let expr0_0 = VecMisc2::Rev64;
2402     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2403     return Some(expr1_0);
2404 }
2405 
2406 // Generated as internal constructor for term xtn64.
2407 pub fn constructor_xtn64<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2408     let pattern0_0 = arg0;
2409     let pattern1_0 = arg1;
2410     // Rule at src/isa/aarch64/inst.isle line 1694.
2411     let expr0_0 = VecRRNarrowOp::Xtn64;
2412     let expr1_0 = constructor_vec_rr_narrow(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2413     return Some(expr1_0);
2414 }
2415 
2416 // Generated as internal constructor for term addp.
2417 pub fn constructor_addp<C: Context>(
2418     ctx: &mut C,
2419     arg0: Reg,
2420     arg1: Reg,
2421     arg2: &VectorSize,
2422 ) -> Option<Reg> {
2423     let pattern0_0 = arg0;
2424     let pattern1_0 = arg1;
2425     let pattern2_0 = arg2;
2426     // Rule at src/isa/aarch64/inst.isle line 1698.
2427     let expr0_0 = VecALUOp::Addp;
2428     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2429     return Some(expr1_0);
2430 }
2431 
2432 // Generated as internal constructor for term addv.
2433 pub fn constructor_addv<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2434     let pattern0_0 = arg0;
2435     let pattern1_0 = arg1;
2436     // Rule at src/isa/aarch64/inst.isle line 1702.
2437     let expr0_0 = VecLanesOp::Addv;
2438     let expr1_0 = constructor_vec_lanes(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2439     return Some(expr1_0);
2440 }
2441 
2442 // Generated as internal constructor for term shll32.
2443 pub fn constructor_shll32<C: Context>(ctx: &mut C, arg0: Reg, arg1: bool) -> Option<Reg> {
2444     let pattern0_0 = arg0;
2445     let pattern1_0 = arg1;
2446     // Rule at src/isa/aarch64/inst.isle line 1706.
2447     let expr0_0 = VecRRLongOp::Shll32;
2448     let expr1_0 = constructor_vec_rr_long(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2449     return Some(expr1_0);
2450 }
2451 
2452 // Generated as internal constructor for term umlal32.
2453 pub fn constructor_umlal32<C: Context>(
2454     ctx: &mut C,
2455     arg0: Reg,
2456     arg1: Reg,
2457     arg2: Reg,
2458     arg3: bool,
2459 ) -> Option<Reg> {
2460     let pattern0_0 = arg0;
2461     let pattern1_0 = arg1;
2462     let pattern2_0 = arg2;
2463     let pattern3_0 = arg3;
2464     // Rule at src/isa/aarch64/inst.isle line 1710.
2465     let expr0_0 = VecRRRLongOp::Umlal32;
2466     let expr1_0 = constructor_vec_rrrr_long(
2467         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2468     )?;
2469     return Some(expr1_0);
2470 }
2471 
2472 // Generated as internal constructor for term smull8.
2473 pub fn constructor_smull8<C: Context>(
2474     ctx: &mut C,
2475     arg0: Reg,
2476     arg1: Reg,
2477     arg2: bool,
2478 ) -> Option<Reg> {
2479     let pattern0_0 = arg0;
2480     let pattern1_0 = arg1;
2481     let pattern2_0 = arg2;
2482     // Rule at src/isa/aarch64/inst.isle line 1714.
2483     let expr0_0 = VecRRRLongOp::Smull8;
2484     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2485     return Some(expr1_0);
2486 }
2487 
2488 // Generated as internal constructor for term umull8.
2489 pub fn constructor_umull8<C: Context>(
2490     ctx: &mut C,
2491     arg0: Reg,
2492     arg1: Reg,
2493     arg2: bool,
2494 ) -> Option<Reg> {
2495     let pattern0_0 = arg0;
2496     let pattern1_0 = arg1;
2497     let pattern2_0 = arg2;
2498     // Rule at src/isa/aarch64/inst.isle line 1718.
2499     let expr0_0 = VecRRRLongOp::Umull8;
2500     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2501     return Some(expr1_0);
2502 }
2503 
2504 // Generated as internal constructor for term smull16.
2505 pub fn constructor_smull16<C: Context>(
2506     ctx: &mut C,
2507     arg0: Reg,
2508     arg1: Reg,
2509     arg2: bool,
2510 ) -> Option<Reg> {
2511     let pattern0_0 = arg0;
2512     let pattern1_0 = arg1;
2513     let pattern2_0 = arg2;
2514     // Rule at src/isa/aarch64/inst.isle line 1722.
2515     let expr0_0 = VecRRRLongOp::Smull16;
2516     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2517     return Some(expr1_0);
2518 }
2519 
2520 // Generated as internal constructor for term umull16.
2521 pub fn constructor_umull16<C: Context>(
2522     ctx: &mut C,
2523     arg0: Reg,
2524     arg1: Reg,
2525     arg2: bool,
2526 ) -> Option<Reg> {
2527     let pattern0_0 = arg0;
2528     let pattern1_0 = arg1;
2529     let pattern2_0 = arg2;
2530     // Rule at src/isa/aarch64/inst.isle line 1726.
2531     let expr0_0 = VecRRRLongOp::Umull16;
2532     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2533     return Some(expr1_0);
2534 }
2535 
2536 // Generated as internal constructor for term smull32.
2537 pub fn constructor_smull32<C: Context>(
2538     ctx: &mut C,
2539     arg0: Reg,
2540     arg1: Reg,
2541     arg2: bool,
2542 ) -> Option<Reg> {
2543     let pattern0_0 = arg0;
2544     let pattern1_0 = arg1;
2545     let pattern2_0 = arg2;
2546     // Rule at src/isa/aarch64/inst.isle line 1730.
2547     let expr0_0 = VecRRRLongOp::Smull32;
2548     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2549     return Some(expr1_0);
2550 }
2551 
2552 // Generated as internal constructor for term umull32.
2553 pub fn constructor_umull32<C: Context>(
2554     ctx: &mut C,
2555     arg0: Reg,
2556     arg1: Reg,
2557     arg2: bool,
2558 ) -> Option<Reg> {
2559     let pattern0_0 = arg0;
2560     let pattern1_0 = arg1;
2561     let pattern2_0 = arg2;
2562     // Rule at src/isa/aarch64/inst.isle line 1734.
2563     let expr0_0 = VecRRRLongOp::Umull32;
2564     let expr1_0 = constructor_vec_rrr_long(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2565     return Some(expr1_0);
2566 }
2567 
2568 // Generated as internal constructor for term asr.
2569 pub fn constructor_asr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2570     let pattern0_0 = arg0;
2571     let pattern1_0 = arg1;
2572     let pattern2_0 = arg2;
2573     // Rule at src/isa/aarch64/inst.isle line 1738.
2574     let expr0_0 = ALUOp::Asr;
2575     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2576     return Some(expr1_0);
2577 }
2578 
2579 // Generated as internal constructor for term asr_imm.
2580 pub fn constructor_asr_imm<C: Context>(
2581     ctx: &mut C,
2582     arg0: Type,
2583     arg1: Reg,
2584     arg2: ImmShift,
2585 ) -> Option<Reg> {
2586     let pattern0_0 = arg0;
2587     let pattern1_0 = arg1;
2588     let pattern2_0 = arg2;
2589     // Rule at src/isa/aarch64/inst.isle line 1741.
2590     let expr0_0 = ALUOp::Asr;
2591     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2592     return Some(expr1_0);
2593 }
2594 
2595 // Generated as internal constructor for term lsr.
2596 pub fn constructor_lsr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2597     let pattern0_0 = arg0;
2598     let pattern1_0 = arg1;
2599     let pattern2_0 = arg2;
2600     // Rule at src/isa/aarch64/inst.isle line 1745.
2601     let expr0_0 = ALUOp::Lsr;
2602     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2603     return Some(expr1_0);
2604 }
2605 
2606 // Generated as internal constructor for term lsr_imm.
2607 pub fn constructor_lsr_imm<C: Context>(
2608     ctx: &mut C,
2609     arg0: Type,
2610     arg1: Reg,
2611     arg2: ImmShift,
2612 ) -> Option<Reg> {
2613     let pattern0_0 = arg0;
2614     let pattern1_0 = arg1;
2615     let pattern2_0 = arg2;
2616     // Rule at src/isa/aarch64/inst.isle line 1748.
2617     let expr0_0 = ALUOp::Lsr;
2618     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2619     return Some(expr1_0);
2620 }
2621 
2622 // Generated as internal constructor for term lsl.
2623 pub fn constructor_lsl<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2624     let pattern0_0 = arg0;
2625     let pattern1_0 = arg1;
2626     let pattern2_0 = arg2;
2627     // Rule at src/isa/aarch64/inst.isle line 1752.
2628     let expr0_0 = ALUOp::Lsl;
2629     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2630     return Some(expr1_0);
2631 }
2632 
2633 // Generated as internal constructor for term lsl_imm.
2634 pub fn constructor_lsl_imm<C: Context>(
2635     ctx: &mut C,
2636     arg0: Type,
2637     arg1: Reg,
2638     arg2: ImmShift,
2639 ) -> Option<Reg> {
2640     let pattern0_0 = arg0;
2641     let pattern1_0 = arg1;
2642     let pattern2_0 = arg2;
2643     // Rule at src/isa/aarch64/inst.isle line 1755.
2644     let expr0_0 = ALUOp::Lsl;
2645     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2646     return Some(expr1_0);
2647 }
2648 
2649 // Generated as internal constructor for term a64_udiv.
2650 pub fn constructor_a64_udiv<C: Context>(
2651     ctx: &mut C,
2652     arg0: Type,
2653     arg1: Reg,
2654     arg2: Reg,
2655 ) -> Option<Reg> {
2656     let pattern0_0 = arg0;
2657     let pattern1_0 = arg1;
2658     let pattern2_0 = arg2;
2659     // Rule at src/isa/aarch64/inst.isle line 1759.
2660     let expr0_0 = ALUOp::UDiv;
2661     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2662     return Some(expr1_0);
2663 }
2664 
2665 // Generated as internal constructor for term a64_sdiv.
2666 pub fn constructor_a64_sdiv<C: Context>(
2667     ctx: &mut C,
2668     arg0: Type,
2669     arg1: Reg,
2670     arg2: Reg,
2671 ) -> Option<Reg> {
2672     let pattern0_0 = arg0;
2673     let pattern1_0 = arg1;
2674     let pattern2_0 = arg2;
2675     // Rule at src/isa/aarch64/inst.isle line 1763.
2676     let expr0_0 = ALUOp::SDiv;
2677     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2678     return Some(expr1_0);
2679 }
2680 
2681 // Generated as internal constructor for term not.
2682 pub fn constructor_not<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2683     let pattern0_0 = arg0;
2684     let pattern1_0 = arg1;
2685     // Rule at src/isa/aarch64/inst.isle line 1767.
2686     let expr0_0 = VecMisc2::Not;
2687     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2688     return Some(expr1_0);
2689 }
2690 
2691 // Generated as internal constructor for term orr_not.
2692 pub fn constructor_orr_not<C: Context>(
2693     ctx: &mut C,
2694     arg0: Type,
2695     arg1: Reg,
2696     arg2: Reg,
2697 ) -> Option<Reg> {
2698     let pattern0_0 = arg0;
2699     let pattern1_0 = arg1;
2700     let pattern2_0 = arg2;
2701     // Rule at src/isa/aarch64/inst.isle line 1772.
2702     let expr0_0 = ALUOp::OrrNot;
2703     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2704     return Some(expr1_0);
2705 }
2706 
2707 // Generated as internal constructor for term orr_not_shift.
2708 pub fn constructor_orr_not_shift<C: Context>(
2709     ctx: &mut C,
2710     arg0: Type,
2711     arg1: Reg,
2712     arg2: Reg,
2713     arg3: ShiftOpAndAmt,
2714 ) -> Option<Reg> {
2715     let pattern0_0 = arg0;
2716     let pattern1_0 = arg1;
2717     let pattern2_0 = arg2;
2718     let pattern3_0 = arg3;
2719     // Rule at src/isa/aarch64/inst.isle line 1775.
2720     let expr0_0 = ALUOp::OrrNot;
2721     let expr1_0 = constructor_alu_rrr_shift(
2722         ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0, pattern3_0,
2723     )?;
2724     return Some(expr1_0);
2725 }
2726 
2727 // Generated as internal constructor for term orr.
2728 pub fn constructor_orr<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2729     let pattern0_0 = arg0;
2730     let pattern1_0 = arg1;
2731     let pattern2_0 = arg2;
2732     // Rule at src/isa/aarch64/inst.isle line 1780.
2733     let expr0_0 = ALUOp::Orr;
2734     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2735     return Some(expr1_0);
2736 }
2737 
2738 // Generated as internal constructor for term orr_imm.
2739 pub fn constructor_orr_imm<C: Context>(
2740     ctx: &mut C,
2741     arg0: Type,
2742     arg1: Reg,
2743     arg2: ImmLogic,
2744 ) -> Option<Reg> {
2745     let pattern0_0 = arg0;
2746     let pattern1_0 = arg1;
2747     let pattern2_0 = arg2;
2748     // Rule at src/isa/aarch64/inst.isle line 1783.
2749     let expr0_0 = ALUOp::Orr;
2750     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2751     return Some(expr1_0);
2752 }
2753 
2754 // Generated as internal constructor for term orr_vec.
2755 pub fn constructor_orr_vec<C: Context>(
2756     ctx: &mut C,
2757     arg0: Reg,
2758     arg1: Reg,
2759     arg2: &VectorSize,
2760 ) -> Option<Reg> {
2761     let pattern0_0 = arg0;
2762     let pattern1_0 = arg1;
2763     let pattern2_0 = arg2;
2764     // Rule at src/isa/aarch64/inst.isle line 1786.
2765     let expr0_0 = VecALUOp::Orr;
2766     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2767     return Some(expr1_0);
2768 }
2769 
2770 // Generated as internal constructor for term and_imm.
2771 pub fn constructor_and_imm<C: Context>(
2772     ctx: &mut C,
2773     arg0: Type,
2774     arg1: Reg,
2775     arg2: ImmLogic,
2776 ) -> Option<Reg> {
2777     let pattern0_0 = arg0;
2778     let pattern1_0 = arg1;
2779     let pattern2_0 = arg2;
2780     // Rule at src/isa/aarch64/inst.isle line 1791.
2781     let expr0_0 = ALUOp::And;
2782     let expr1_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2783     return Some(expr1_0);
2784 }
2785 
2786 // Generated as internal constructor for term and_vec.
2787 pub fn constructor_and_vec<C: Context>(
2788     ctx: &mut C,
2789     arg0: Reg,
2790     arg1: Reg,
2791     arg2: &VectorSize,
2792 ) -> Option<Reg> {
2793     let pattern0_0 = arg0;
2794     let pattern1_0 = arg1;
2795     let pattern2_0 = arg2;
2796     // Rule at src/isa/aarch64/inst.isle line 1794.
2797     let expr0_0 = VecALUOp::And;
2798     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2799     return Some(expr1_0);
2800 }
2801 
2802 // Generated as internal constructor for term eor_vec.
2803 pub fn constructor_eor_vec<C: Context>(
2804     ctx: &mut C,
2805     arg0: Reg,
2806     arg1: Reg,
2807     arg2: &VectorSize,
2808 ) -> Option<Reg> {
2809     let pattern0_0 = arg0;
2810     let pattern1_0 = arg1;
2811     let pattern2_0 = arg2;
2812     // Rule at src/isa/aarch64/inst.isle line 1798.
2813     let expr0_0 = VecALUOp::Eor;
2814     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2815     return Some(expr1_0);
2816 }
2817 
2818 // Generated as internal constructor for term bic_vec.
2819 pub fn constructor_bic_vec<C: Context>(
2820     ctx: &mut C,
2821     arg0: Reg,
2822     arg1: Reg,
2823     arg2: &VectorSize,
2824 ) -> Option<Reg> {
2825     let pattern0_0 = arg0;
2826     let pattern1_0 = arg1;
2827     let pattern2_0 = arg2;
2828     // Rule at src/isa/aarch64/inst.isle line 1802.
2829     let expr0_0 = VecALUOp::Bic;
2830     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2831     return Some(expr1_0);
2832 }
2833 
2834 // Generated as internal constructor for term sshl.
2835 pub fn constructor_sshl<C: Context>(
2836     ctx: &mut C,
2837     arg0: Reg,
2838     arg1: Reg,
2839     arg2: &VectorSize,
2840 ) -> Option<Reg> {
2841     let pattern0_0 = arg0;
2842     let pattern1_0 = arg1;
2843     let pattern2_0 = arg2;
2844     // Rule at src/isa/aarch64/inst.isle line 1806.
2845     let expr0_0 = VecALUOp::Sshl;
2846     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2847     return Some(expr1_0);
2848 }
2849 
2850 // Generated as internal constructor for term ushl.
2851 pub fn constructor_ushl<C: Context>(
2852     ctx: &mut C,
2853     arg0: Reg,
2854     arg1: Reg,
2855     arg2: &VectorSize,
2856 ) -> Option<Reg> {
2857     let pattern0_0 = arg0;
2858     let pattern1_0 = arg1;
2859     let pattern2_0 = arg2;
2860     // Rule at src/isa/aarch64/inst.isle line 1810.
2861     let expr0_0 = VecALUOp::Ushl;
2862     let expr1_0 = constructor_vec_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2863     return Some(expr1_0);
2864 }
2865 
2866 // Generated as internal constructor for term a64_rotr.
2867 pub fn constructor_a64_rotr<C: Context>(
2868     ctx: &mut C,
2869     arg0: Type,
2870     arg1: Reg,
2871     arg2: Reg,
2872 ) -> Option<Reg> {
2873     let pattern0_0 = arg0;
2874     let pattern1_0 = arg1;
2875     let pattern2_0 = arg2;
2876     // Rule at src/isa/aarch64/inst.isle line 1815.
2877     let expr0_0 = ALUOp::RotR;
2878     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2879     return Some(expr1_0);
2880 }
2881 
2882 // Generated as internal constructor for term a64_rotr_imm.
2883 pub fn constructor_a64_rotr_imm<C: Context>(
2884     ctx: &mut C,
2885     arg0: Type,
2886     arg1: Reg,
2887     arg2: ImmShift,
2888 ) -> Option<Reg> {
2889     let pattern0_0 = arg0;
2890     let pattern1_0 = arg1;
2891     let pattern2_0 = arg2;
2892     // Rule at src/isa/aarch64/inst.isle line 1818.
2893     let expr0_0 = ALUOp::RotR;
2894     let expr1_0 = constructor_alu_rr_imm_shift(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2895     return Some(expr1_0);
2896 }
2897 
2898 // Generated as internal constructor for term rbit.
2899 pub fn constructor_rbit<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2900     let pattern0_0 = arg0;
2901     let pattern1_0 = arg1;
2902     // Rule at src/isa/aarch64/inst.isle line 1823.
2903     let expr0_0 = BitOp::RBit;
2904     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2905     return Some(expr1_0);
2906 }
2907 
2908 // Generated as internal constructor for term a64_clz.
2909 pub fn constructor_a64_clz<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2910     let pattern0_0 = arg0;
2911     let pattern1_0 = arg1;
2912     // Rule at src/isa/aarch64/inst.isle line 1828.
2913     let expr0_0 = BitOp::Clz;
2914     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2915     return Some(expr1_0);
2916 }
2917 
2918 // Generated as internal constructor for term a64_cls.
2919 pub fn constructor_a64_cls<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg) -> Option<Reg> {
2920     let pattern0_0 = arg0;
2921     let pattern1_0 = arg1;
2922     // Rule at src/isa/aarch64/inst.isle line 1833.
2923     let expr0_0 = BitOp::Cls;
2924     let expr1_0 = constructor_bit_rr(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2925     return Some(expr1_0);
2926 }
2927 
2928 // Generated as internal constructor for term eon.
2929 pub fn constructor_eon<C: Context>(ctx: &mut C, arg0: Type, arg1: Reg, arg2: Reg) -> Option<Reg> {
2930     let pattern0_0 = arg0;
2931     let pattern1_0 = arg1;
2932     let pattern2_0 = arg2;
2933     // Rule at src/isa/aarch64/inst.isle line 1838.
2934     let expr0_0 = ALUOp::EorNot;
2935     let expr1_0 = constructor_alu_rrr(ctx, &expr0_0, pattern0_0, pattern1_0, pattern2_0)?;
2936     return Some(expr1_0);
2937 }
2938 
2939 // Generated as internal constructor for term vec_cnt.
2940 pub fn constructor_vec_cnt<C: Context>(ctx: &mut C, arg0: Reg, arg1: &VectorSize) -> Option<Reg> {
2941     let pattern0_0 = arg0;
2942     let pattern1_0 = arg1;
2943     // Rule at src/isa/aarch64/inst.isle line 1843.
2944     let expr0_0 = VecMisc2::Cnt;
2945     let expr1_0 = constructor_vec_misc(ctx, &expr0_0, pattern0_0, pattern1_0)?;
2946     return Some(expr1_0);
2947 }
2948 
2949 // Generated as internal constructor for term imm.
2950 pub fn constructor_imm<C: Context>(ctx: &mut C, arg0: Type, arg1: u64) -> Option<Reg> {
2951     let pattern0_0 = arg0;
2952     if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) {
2953         let pattern2_0 = arg1;
2954         let closure3 = || {
2955             let expr0_0: Type = I64;
2956             return Some(expr0_0);
2957         };
2958         if let Some(pattern3_0) = closure3() {
2959             if let Some(pattern4_0) = C::imm_logic_from_u64(ctx, pattern2_0, pattern3_0) {
2960                 // Rule at src/isa/aarch64/inst.isle line 1858.
2961                 let expr0_0: Type = I64;
2962                 let expr1_0 = C::zero_reg(ctx);
2963                 let expr2_0 = constructor_orr_imm(ctx, expr0_0, expr1_0, pattern4_0)?;
2964                 return Some(expr2_0);
2965             }
2966         }
2967         if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) {
2968             // Rule at src/isa/aarch64/inst.isle line 1850.
2969             let expr0_0 = OperandSize::Size64;
2970             let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?;
2971             return Some(expr1_0);
2972         }
2973         if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) {
2974             // Rule at src/isa/aarch64/inst.isle line 1854.
2975             let expr0_0 = OperandSize::Size64;
2976             let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?;
2977             return Some(expr1_0);
2978         }
2979         // Rule at src/isa/aarch64/inst.isle line 1865.
2980         let expr0_0 = C::load_constant64_full(ctx, pattern2_0);
2981         return Some(expr0_0);
2982     }
2983     return None;
2984 }
2985 
2986 // Generated as internal constructor for term put_in_reg_sext32.
2987 pub fn constructor_put_in_reg_sext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
2988     let pattern0_0 = arg0;
2989     let pattern1_0 = C::value_type(ctx, pattern0_0);
2990     if pattern1_0 == I32 {
2991         // Rule at src/isa/aarch64/inst.isle line 1876.
2992         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
2993         return Some(expr0_0);
2994     }
2995     if pattern1_0 == I64 {
2996         // Rule at src/isa/aarch64/inst.isle line 1877.
2997         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
2998         return Some(expr0_0);
2999     }
3000     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3001         // Rule at src/isa/aarch64/inst.isle line 1872.
3002         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3003         let expr1_0: bool = true;
3004         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3005         let expr3_0: u8 = 32;
3006         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3007         return Some(expr4_0);
3008     }
3009     return None;
3010 }
3011 
3012 // Generated as internal constructor for term put_in_reg_zext32.
3013 pub fn constructor_put_in_reg_zext32<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3014     let pattern0_0 = arg0;
3015     let pattern1_0 = C::value_type(ctx, pattern0_0);
3016     if pattern1_0 == I32 {
3017         // Rule at src/isa/aarch64/inst.isle line 1885.
3018         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3019         return Some(expr0_0);
3020     }
3021     if pattern1_0 == I64 {
3022         // Rule at src/isa/aarch64/inst.isle line 1886.
3023         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3024         return Some(expr0_0);
3025     }
3026     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3027         // Rule at src/isa/aarch64/inst.isle line 1881.
3028         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3029         let expr1_0: bool = false;
3030         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3031         let expr3_0: u8 = 32;
3032         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3033         return Some(expr4_0);
3034     }
3035     return None;
3036 }
3037 
3038 // Generated as internal constructor for term put_in_reg_sext64.
3039 pub fn constructor_put_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3040     let pattern0_0 = arg0;
3041     let pattern1_0 = C::value_type(ctx, pattern0_0);
3042     if pattern1_0 == I64 {
3043         // Rule at src/isa/aarch64/inst.isle line 1894.
3044         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3045         return Some(expr0_0);
3046     }
3047     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3048         // Rule at src/isa/aarch64/inst.isle line 1890.
3049         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3050         let expr1_0: bool = true;
3051         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3052         let expr3_0: u8 = 64;
3053         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3054         return Some(expr4_0);
3055     }
3056     return None;
3057 }
3058 
3059 // Generated as internal constructor for term put_in_reg_zext64.
3060 pub fn constructor_put_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
3061     let pattern0_0 = arg0;
3062     let pattern1_0 = C::value_type(ctx, pattern0_0);
3063     if pattern1_0 == I64 {
3064         // Rule at src/isa/aarch64/inst.isle line 1902.
3065         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3066         return Some(expr0_0);
3067     }
3068     if let Some(pattern2_0) = C::fits_in_32(ctx, pattern1_0) {
3069         // Rule at src/isa/aarch64/inst.isle line 1898.
3070         let expr0_0 = C::put_in_reg(ctx, pattern0_0);
3071         let expr1_0: bool = false;
3072         let expr2_0 = C::ty_bits(ctx, pattern2_0);
3073         let expr3_0: u8 = 64;
3074         let expr4_0 = constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
3075         return Some(expr4_0);
3076     }
3077     return None;
3078 }
3079 
3080 // Generated as internal constructor for term trap_if_zero_divisor.
3081 pub fn constructor_trap_if_zero_divisor<C: Context>(ctx: &mut C, arg0: Reg) -> Option<Reg> {
3082     let pattern0_0 = arg0;
3083     // Rule at src/isa/aarch64/inst.isle line 1907.
3084     let expr0_0 = C::cond_br_zero(ctx, pattern0_0);
3085     let expr1_0 = C::trap_code_division_by_zero(ctx);
3086     let expr2_0 = MInst::TrapIf {
3087         kind: expr0_0,
3088         trap_code: expr1_0,
3089     };
3090     let expr3_0 = C::emit(ctx, &expr2_0);
3091     return Some(pattern0_0);
3092 }
3093 
3094 // Generated as internal constructor for term size_from_ty.
3095 pub fn constructor_size_from_ty<C: Context>(ctx: &mut C, arg0: Type) -> Option<OperandSize> {
3096     let pattern0_0 = arg0;
3097     if pattern0_0 == I64 {
3098         // Rule at src/isa/aarch64/inst.isle line 1913.
3099         let expr0_0 = OperandSize::Size64;
3100         return Some(expr0_0);
3101     }
3102     if let Some(pattern1_0) = C::fits_in_32(ctx, pattern0_0) {
3103         // Rule at src/isa/aarch64/inst.isle line 1912.
3104         let expr0_0 = OperandSize::Size32;
3105         return Some(expr0_0);
3106     }
3107     return None;
3108 }
3109 
3110 // Generated as internal constructor for term trap_if_div_overflow.
3111 pub fn constructor_trap_if_div_overflow<C: Context>(
3112     ctx: &mut C,
3113     arg0: Type,
3114     arg1: Reg,
3115     arg2: Reg,
3116 ) -> Option<Reg> {
3117     let pattern0_0 = arg0;
3118     let pattern1_0 = arg1;
3119     let pattern2_0 = arg2;
3120     // Rule at src/isa/aarch64/inst.isle line 1919.
3121     let expr0_0 = ALUOp::AddS;
3122     let expr1_0 = constructor_operand_size(ctx, pattern0_0)?;
3123     let expr2_0 = C::writable_zero_reg(ctx);
3124     let expr3_0: u8 = 1;
3125     let expr4_0 = C::u8_into_imm12(ctx, expr3_0);
3126     let expr5_0 = MInst::AluRRImm12 {
3127         alu_op: expr0_0,
3128         size: expr1_0,
3129         rd: expr2_0,
3130         rn: pattern2_0,
3131         imm12: expr4_0,
3132     };
3133     let expr6_0 = C::emit(ctx, &expr5_0);
3134     let expr7_0 = constructor_size_from_ty(ctx, pattern0_0)?;
3135     let expr8_0: u8 = 1;
3136     let expr9_0 = C::u8_into_uimm5(ctx, expr8_0);
3137     let expr10_0: bool = false;
3138     let expr11_0: bool = false;
3139     let expr12_0: bool = false;
3140     let expr13_0: bool = false;
3141     let expr14_0 = C::nzcv(ctx, expr10_0, expr11_0, expr12_0, expr13_0);
3142     let expr15_0 = Cond::Eq;
3143     let expr16_0 = MInst::CCmpImm {
3144         size: expr7_0,
3145         rn: pattern1_0,
3146         imm: expr9_0,
3147         nzcv: expr14_0,
3148         cond: expr15_0,
3149     };
3150     let expr17_0 = C::emit(ctx, &expr16_0);
3151     let expr18_0 = Cond::Vs;
3152     let expr19_0 = C::cond_br_cond(ctx, &expr18_0);
3153     let expr20_0 = C::trap_code_integer_overflow(ctx);
3154     let expr21_0 = MInst::TrapIf {
3155         kind: expr19_0,
3156         trap_code: expr20_0,
3157     };
3158     let expr22_0 = C::emit(ctx, &expr21_0);
3159     return Some(pattern1_0);
3160 }
3161 
3162 // Generated as internal constructor for term alu_rs_imm_logic_commutative.
3163 pub fn constructor_alu_rs_imm_logic_commutative<C: Context>(
3164     ctx: &mut C,
3165     arg0: &ALUOp,
3166     arg1: Type,
3167     arg2: Value,
3168     arg3: Value,
3169 ) -> Option<Reg> {
3170     let pattern0_0 = arg0;
3171     let pattern1_0 = arg1;
3172     let pattern2_0 = arg2;
3173     if let Some(pattern3_0) = C::def_inst(ctx, pattern2_0) {
3174         let pattern4_0 = C::inst_data(ctx, pattern3_0);
3175         match &pattern4_0 {
3176             &InstructionData::UnaryImm {
3177                 opcode: ref pattern5_0,
3178                 imm: pattern5_1,
3179             } => {
3180                 if let &Opcode::Iconst = pattern5_0 {
3181                     let closure7 = || {
3182                         return Some(pattern1_0);
3183                     };
3184                     if let Some(pattern7_0) = closure7() {
3185                         if let Some(pattern8_0) =
3186                             C::imm_logic_from_imm64(ctx, pattern5_1, pattern7_0)
3187                         {
3188                             let pattern9_0 = arg3;
3189                             // Rule at src/isa/aarch64/inst.isle line 1964.
3190                             let expr0_0 = C::put_in_reg(ctx, pattern9_0);
3191                             let expr1_0 = constructor_alu_rr_imm_logic(
3192                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern8_0,
3193                             )?;
3194                             return Some(expr1_0);
3195                         }
3196                     }
3197                 }
3198             }
3199             &InstructionData::Binary {
3200                 opcode: ref pattern5_0,
3201                 args: ref pattern5_1,
3202             } => {
3203                 if let &Opcode::Ishl = pattern5_0 {
3204                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3205                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3206                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
3207                         if let &InstructionData::UnaryImm {
3208                             opcode: ref pattern10_0,
3209                             imm: pattern10_1,
3210                         } = &pattern9_0
3211                         {
3212                             if let &Opcode::Iconst = pattern10_0 {
3213                                 let closure12 = || {
3214                                     return Some(pattern1_0);
3215                                 };
3216                                 if let Some(pattern12_0) = closure12() {
3217                                     if let Some(pattern13_0) =
3218                                         C::lshl_from_imm64(ctx, pattern10_1, pattern12_0)
3219                                     {
3220                                         let pattern14_0 = arg3;
3221                                         // Rule at src/isa/aarch64/inst.isle line 1970.
3222                                         let expr0_0 = C::put_in_reg(ctx, pattern14_0);
3223                                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3224                                         let expr2_0 = constructor_alu_rrr_shift(
3225                                             ctx,
3226                                             pattern0_0,
3227                                             pattern1_0,
3228                                             expr0_0,
3229                                             expr1_0,
3230                                             pattern13_0,
3231                                         )?;
3232                                         return Some(expr2_0);
3233                                     }
3234                                 }
3235                             }
3236                         }
3237                     }
3238                 }
3239             }
3240             _ => {}
3241         }
3242     }
3243     let pattern3_0 = arg3;
3244     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3245         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3246         match &pattern5_0 {
3247             &InstructionData::UnaryImm {
3248                 opcode: ref pattern6_0,
3249                 imm: pattern6_1,
3250             } => {
3251                 if let &Opcode::Iconst = pattern6_0 {
3252                     let closure8 = || {
3253                         return Some(pattern1_0);
3254                     };
3255                     if let Some(pattern8_0) = closure8() {
3256                         if let Some(pattern9_0) =
3257                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3258                         {
3259                             // Rule at src/isa/aarch64/inst.isle line 1962.
3260                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3261                             let expr1_0 = constructor_alu_rr_imm_logic(
3262                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3263                             )?;
3264                             return Some(expr1_0);
3265                         }
3266                     }
3267                 }
3268             }
3269             &InstructionData::Binary {
3270                 opcode: ref pattern6_0,
3271                 args: ref pattern6_1,
3272             } => {
3273                 if let &Opcode::Ishl = pattern6_0 {
3274                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3275                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3276                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3277                         if let &InstructionData::UnaryImm {
3278                             opcode: ref pattern11_0,
3279                             imm: pattern11_1,
3280                         } = &pattern10_0
3281                         {
3282                             if let &Opcode::Iconst = pattern11_0 {
3283                                 let closure13 = || {
3284                                     return Some(pattern1_0);
3285                                 };
3286                                 if let Some(pattern13_0) = closure13() {
3287                                     if let Some(pattern14_0) =
3288                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3289                                     {
3290                                         // Rule at src/isa/aarch64/inst.isle line 1968.
3291                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3292                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3293                                         let expr2_0 = constructor_alu_rrr_shift(
3294                                             ctx,
3295                                             pattern0_0,
3296                                             pattern1_0,
3297                                             expr0_0,
3298                                             expr1_0,
3299                                             pattern14_0,
3300                                         )?;
3301                                         return Some(expr2_0);
3302                                     }
3303                                 }
3304                             }
3305                         }
3306                     }
3307                 }
3308             }
3309             _ => {}
3310         }
3311     }
3312     // Rule at src/isa/aarch64/inst.isle line 1958.
3313     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3314     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3315     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3316     return Some(expr2_0);
3317 }
3318 
3319 // Generated as internal constructor for term alu_rs_imm_logic.
3320 pub fn constructor_alu_rs_imm_logic<C: Context>(
3321     ctx: &mut C,
3322     arg0: &ALUOp,
3323     arg1: Type,
3324     arg2: Value,
3325     arg3: Value,
3326 ) -> Option<Reg> {
3327     let pattern0_0 = arg0;
3328     let pattern1_0 = arg1;
3329     let pattern2_0 = arg2;
3330     let pattern3_0 = arg3;
3331     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
3332         let pattern5_0 = C::inst_data(ctx, pattern4_0);
3333         match &pattern5_0 {
3334             &InstructionData::UnaryImm {
3335                 opcode: ref pattern6_0,
3336                 imm: pattern6_1,
3337             } => {
3338                 if let &Opcode::Iconst = pattern6_0 {
3339                     let closure8 = || {
3340                         return Some(pattern1_0);
3341                     };
3342                     if let Some(pattern8_0) = closure8() {
3343                         if let Some(pattern9_0) =
3344                             C::imm_logic_from_imm64(ctx, pattern6_1, pattern8_0)
3345                         {
3346                             // Rule at src/isa/aarch64/inst.isle line 1978.
3347                             let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3348                             let expr1_0 = constructor_alu_rr_imm_logic(
3349                                 ctx, pattern0_0, pattern1_0, expr0_0, pattern9_0,
3350                             )?;
3351                             return Some(expr1_0);
3352                         }
3353                     }
3354                 }
3355             }
3356             &InstructionData::Binary {
3357                 opcode: ref pattern6_0,
3358                 args: ref pattern6_1,
3359             } => {
3360                 if let &Opcode::Ishl = pattern6_0 {
3361                     let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
3362                     if let Some(pattern9_0) = C::def_inst(ctx, pattern8_1) {
3363                         let pattern10_0 = C::inst_data(ctx, pattern9_0);
3364                         if let &InstructionData::UnaryImm {
3365                             opcode: ref pattern11_0,
3366                             imm: pattern11_1,
3367                         } = &pattern10_0
3368                         {
3369                             if let &Opcode::Iconst = pattern11_0 {
3370                                 let closure13 = || {
3371                                     return Some(pattern1_0);
3372                                 };
3373                                 if let Some(pattern13_0) = closure13() {
3374                                     if let Some(pattern14_0) =
3375                                         C::lshl_from_imm64(ctx, pattern11_1, pattern13_0)
3376                                     {
3377                                         // Rule at src/isa/aarch64/inst.isle line 1980.
3378                                         let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3379                                         let expr1_0 = C::put_in_reg(ctx, pattern8_0);
3380                                         let expr2_0 = constructor_alu_rrr_shift(
3381                                             ctx,
3382                                             pattern0_0,
3383                                             pattern1_0,
3384                                             expr0_0,
3385                                             expr1_0,
3386                                             pattern14_0,
3387                                         )?;
3388                                         return Some(expr2_0);
3389                                     }
3390                                 }
3391                             }
3392                         }
3393                     }
3394                 }
3395             }
3396             _ => {}
3397         }
3398     }
3399     // Rule at src/isa/aarch64/inst.isle line 1976.
3400     let expr0_0 = C::put_in_reg(ctx, pattern2_0);
3401     let expr1_0 = C::put_in_reg(ctx, pattern3_0);
3402     let expr2_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr0_0, expr1_0)?;
3403     return Some(expr2_0);
3404 }
3405 
3406 // Generated as internal constructor for term i128_alu_bitop.
3407 pub fn constructor_i128_alu_bitop<C: Context>(
3408     ctx: &mut C,
3409     arg0: &ALUOp,
3410     arg1: Type,
3411     arg2: Value,
3412     arg3: Value,
3413 ) -> Option<ValueRegs> {
3414     let pattern0_0 = arg0;
3415     let pattern1_0 = arg1;
3416     let pattern2_0 = arg2;
3417     let pattern3_0 = arg3;
3418     // Rule at src/isa/aarch64/inst.isle line 1988.
3419     let expr0_0 = C::put_in_regs(ctx, pattern2_0);
3420     let expr1_0: usize = 0;
3421     let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3422     let expr3_0: usize = 1;
3423     let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
3424     let expr5_0 = C::put_in_regs(ctx, pattern3_0);
3425     let expr6_0: usize = 0;
3426     let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
3427     let expr8_0: usize = 1;
3428     let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
3429     let expr10_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr2_0, expr7_0)?;
3430     let expr11_0 = constructor_alu_rrr(ctx, pattern0_0, pattern1_0, expr4_0, expr9_0)?;
3431     let expr12_0 = C::value_regs(ctx, expr10_0, expr11_0);
3432     return Some(expr12_0);
3433 }
3434 
3435 // Generated as internal constructor for term lower.
3436 pub fn constructor_lower<C: Context>(ctx: &mut C, arg0: Inst) -> Option<InstOutput> {
3437     let pattern0_0 = arg0;
3438     if let Some(pattern1_0) = C::first_result(ctx, pattern0_0) {
3439         let pattern2_0 = C::value_type(ctx, pattern1_0);
3440         if pattern2_0 == I8 {
3441             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3442             if let &InstructionData::Unary {
3443                 opcode: ref pattern5_0,
3444                 arg: pattern5_1,
3445             } = &pattern4_0
3446             {
3447                 match pattern5_0 {
3448                     &Opcode::Bitrev => {
3449                         // Rule at src/isa/aarch64/lower.isle line 974.
3450                         let expr0_0: Type = I32;
3451                         let expr1_0: Type = I32;
3452                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3453                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3454                         let expr4_0: u8 = 24;
3455                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3456                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3457                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3458                         return Some(expr7_0);
3459                     }
3460                     &Opcode::Clz => {
3461                         // Rule at src/isa/aarch64/lower.isle line 995.
3462                         let expr0_0: Type = I32;
3463                         let expr1_0: Type = I32;
3464                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3465                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3466                         let expr4_0: u8 = 24;
3467                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3468                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3469                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3470                         return Some(expr7_0);
3471                     }
3472                     &Opcode::Cls => {
3473                         // Rule at src/isa/aarch64/lower.isle line 1042.
3474                         let expr0_0: Type = I32;
3475                         let expr1_0: Type = I32;
3476                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3477                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3478                         let expr4_0: u8 = 24;
3479                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3480                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3481                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3482                         return Some(expr7_0);
3483                     }
3484                     &Opcode::Ctz => {
3485                         // Rule at src/isa/aarch64/lower.isle line 1025.
3486                         let expr0_0: Type = I32;
3487                         let expr1_0: Type = I32;
3488                         let expr2_0: Type = I32;
3489                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3490                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3491                         let expr5_0: Type = I32;
3492                         let expr6_0: u64 = 8388608;
3493                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3494                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3495                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3496                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3497                         return Some(expr10_0);
3498                     }
3499                     &Opcode::Popcnt => {
3500                         // Rule at src/isa/aarch64/lower.isle line 1093.
3501                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3502                         let expr1_0 = ScalarSize::Size32;
3503                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3504                         let expr3_0 = VectorSize::Size8x8;
3505                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3506                         let expr5_0: u8 = 0;
3507                         let expr6_0 = VectorSize::Size8x16;
3508                         let expr7_0 = constructor_mov_from_vec(ctx, expr4_0, expr5_0, &expr6_0)?;
3509                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
3510                         return Some(expr8_0);
3511                     }
3512                     _ => {}
3513                 }
3514             }
3515         }
3516         if pattern2_0 == I16 {
3517             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3518             if let &InstructionData::Unary {
3519                 opcode: ref pattern5_0,
3520                 arg: pattern5_1,
3521             } = &pattern4_0
3522             {
3523                 match pattern5_0 {
3524                     &Opcode::Bitrev => {
3525                         // Rule at src/isa/aarch64/lower.isle line 980.
3526                         let expr0_0: Type = I32;
3527                         let expr1_0: Type = I32;
3528                         let expr2_0 = C::put_in_reg(ctx, pattern5_1);
3529                         let expr3_0 = constructor_rbit(ctx, expr1_0, expr2_0)?;
3530                         let expr4_0: u8 = 16;
3531                         let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
3532                         let expr6_0 = constructor_lsr_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3533                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3534                         return Some(expr7_0);
3535                     }
3536                     &Opcode::Clz => {
3537                         // Rule at src/isa/aarch64/lower.isle line 998.
3538                         let expr0_0: Type = I32;
3539                         let expr1_0: Type = I32;
3540                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3541                         let expr3_0 = constructor_a64_clz(ctx, expr1_0, expr2_0)?;
3542                         let expr4_0: u8 = 16;
3543                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3544                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3545                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3546                         return Some(expr7_0);
3547                     }
3548                     &Opcode::Cls => {
3549                         // Rule at src/isa/aarch64/lower.isle line 1045.
3550                         let expr0_0: Type = I32;
3551                         let expr1_0: Type = I32;
3552                         let expr2_0 = constructor_put_in_reg_zext32(ctx, pattern5_1)?;
3553                         let expr3_0 = constructor_a64_cls(ctx, expr1_0, expr2_0)?;
3554                         let expr4_0: u8 = 16;
3555                         let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
3556                         let expr6_0 = constructor_sub_imm(ctx, expr0_0, expr3_0, expr5_0)?;
3557                         let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3558                         return Some(expr7_0);
3559                     }
3560                     &Opcode::Ctz => {
3561                         // Rule at src/isa/aarch64/lower.isle line 1028.
3562                         let expr0_0: Type = I32;
3563                         let expr1_0: Type = I32;
3564                         let expr2_0: Type = I32;
3565                         let expr3_0 = C::put_in_reg(ctx, pattern5_1);
3566                         let expr4_0 = constructor_rbit(ctx, expr2_0, expr3_0)?;
3567                         let expr5_0: Type = I32;
3568                         let expr6_0: u64 = 32768;
3569                         let expr7_0 = C::u64_into_imm_logic(ctx, expr5_0, expr6_0);
3570                         let expr8_0 = constructor_orr_imm(ctx, expr1_0, expr4_0, expr7_0)?;
3571                         let expr9_0 = constructor_a64_clz(ctx, expr0_0, expr8_0)?;
3572                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3573                         return Some(expr10_0);
3574                     }
3575                     &Opcode::Popcnt => {
3576                         // Rule at src/isa/aarch64/lower.isle line 1099.
3577                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3578                         let expr1_0 = ScalarSize::Size32;
3579                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3580                         let expr3_0 = VectorSize::Size8x8;
3581                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3582                         let expr5_0 = VectorSize::Size8x8;
3583                         let expr6_0 = constructor_addp(ctx, expr4_0, expr4_0, &expr5_0)?;
3584                         let expr7_0: u8 = 0;
3585                         let expr8_0 = VectorSize::Size8x16;
3586                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3587                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3588                         return Some(expr10_0);
3589                     }
3590                     _ => {}
3591                 }
3592             }
3593         }
3594         if pattern2_0 == I32 {
3595             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3596             match &pattern4_0 {
3597                 &InstructionData::Binary {
3598                     opcode: ref pattern5_0,
3599                     args: ref pattern5_1,
3600                 } => {
3601                     match pattern5_0 {
3602                         &Opcode::Rotl => {
3603                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3604                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3605                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3606                                 if let &InstructionData::UnaryImm {
3607                                     opcode: ref pattern10_0,
3608                                     imm: pattern10_1,
3609                                 } = &pattern9_0
3610                                 {
3611                                     if let &Opcode::Iconst = pattern10_0 {
3612                                         let closure12 = || {
3613                                             let expr0_0: Type = I32;
3614                                             return Some(expr0_0);
3615                                         };
3616                                         if let Some(pattern12_0) = closure12() {
3617                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3618                                                 ctx,
3619                                                 pattern10_1,
3620                                                 pattern12_0,
3621                                             ) {
3622                                                 // Rule at src/isa/aarch64/lower.isle line 865.
3623                                                 let expr0_0: Type = I32;
3624                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3625                                                 let expr2_0: Type = I32;
3626                                                 let expr3_0 =
3627                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3628                                                 let expr4_0 = constructor_a64_rotr_imm(
3629                                                     ctx, expr0_0, expr1_0, expr3_0,
3630                                                 )?;
3631                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3632                                                 return Some(expr5_0);
3633                                             }
3634                                         }
3635                                     }
3636                                 }
3637                             }
3638                             // Rule at src/isa/aarch64/lower.isle line 855.
3639                             let expr0_0: Type = I32;
3640                             let expr1_0 = C::zero_reg(ctx);
3641                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3642                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3643                             let expr4_0: Type = I32;
3644                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3645                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3646                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3647                             return Some(expr7_0);
3648                         }
3649                         &Opcode::Rotr => {
3650                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3651                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3652                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3653                                 if let &InstructionData::UnaryImm {
3654                                     opcode: ref pattern10_0,
3655                                     imm: pattern10_1,
3656                                 } = &pattern9_0
3657                                 {
3658                                     if let &Opcode::Iconst = pattern10_0 {
3659                                         let closure12 = || {
3660                                             let expr0_0: Type = I32;
3661                                             return Some(expr0_0);
3662                                         };
3663                                         if let Some(pattern12_0) = closure12() {
3664                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3665                                                 ctx,
3666                                                 pattern10_1,
3667                                                 pattern12_0,
3668                                             ) {
3669                                                 // Rule at src/isa/aarch64/lower.isle line 907.
3670                                                 let expr0_0: Type = I32;
3671                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3672                                                 let expr2_0 = constructor_a64_rotr_imm(
3673                                                     ctx,
3674                                                     expr0_0,
3675                                                     expr1_0,
3676                                                     pattern13_0,
3677                                                 )?;
3678                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3679                                                 return Some(expr3_0);
3680                                             }
3681                                         }
3682                                     }
3683                                 }
3684                             }
3685                             // Rule at src/isa/aarch64/lower.isle line 895.
3686                             let expr0_0: Type = I32;
3687                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3688                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3689                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
3690                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3691                             return Some(expr4_0);
3692                         }
3693                         _ => {}
3694                     }
3695                 }
3696                 &InstructionData::Unary {
3697                     opcode: ref pattern5_0,
3698                     arg: pattern5_1,
3699                 } => {
3700                     if let &Opcode::Popcnt = pattern5_0 {
3701                         // Rule at src/isa/aarch64/lower.isle line 1105.
3702                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3703                         let expr1_0 = ScalarSize::Size32;
3704                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3705                         let expr3_0 = VectorSize::Size8x8;
3706                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3707                         let expr5_0 = VectorSize::Size8x8;
3708                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
3709                         let expr7_0: u8 = 0;
3710                         let expr8_0 = VectorSize::Size8x16;
3711                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3712                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3713                         return Some(expr10_0);
3714                     }
3715                 }
3716                 _ => {}
3717             }
3718         }
3719         if pattern2_0 == I64 {
3720             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3721             match &pattern4_0 {
3722                 &InstructionData::Binary {
3723                     opcode: ref pattern5_0,
3724                     args: ref pattern5_1,
3725                 } => {
3726                     match pattern5_0 {
3727                         &Opcode::Umulhi => {
3728                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3729                             // Rule at src/isa/aarch64/lower.isle line 367.
3730                             let expr0_0: Type = I64;
3731                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3732                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3733                             let expr3_0 = constructor_umulh(ctx, expr0_0, expr1_0, expr2_0)?;
3734                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3735                             return Some(expr4_0);
3736                         }
3737                         &Opcode::Smulhi => {
3738                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3739                             // Rule at src/isa/aarch64/lower.isle line 355.
3740                             let expr0_0: Type = I64;
3741                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3742                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3743                             let expr3_0 = constructor_smulh(ctx, expr0_0, expr1_0, expr2_0)?;
3744                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3745                             return Some(expr4_0);
3746                         }
3747                         &Opcode::Band => {
3748                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3749                             // Rule at src/isa/aarch64/lower.isle line 586.
3750                             let expr0_0 = ALUOp::And;
3751                             let expr1_0: Type = I64;
3752                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3753                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3754                             )?;
3755                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3756                             return Some(expr3_0);
3757                         }
3758                         &Opcode::Bor => {
3759                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3760                             // Rule at src/isa/aarch64/lower.isle line 599.
3761                             let expr0_0 = ALUOp::Orr;
3762                             let expr1_0: Type = I64;
3763                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3764                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3765                             )?;
3766                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3767                             return Some(expr3_0);
3768                         }
3769                         &Opcode::Bxor => {
3770                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3771                             // Rule at src/isa/aarch64/lower.isle line 612.
3772                             let expr0_0 = ALUOp::Eor;
3773                             let expr1_0: Type = I64;
3774                             let expr2_0 = constructor_alu_rs_imm_logic_commutative(
3775                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3776                             )?;
3777                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3778                             return Some(expr3_0);
3779                         }
3780                         &Opcode::BandNot => {
3781                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3782                             // Rule at src/isa/aarch64/lower.isle line 625.
3783                             let expr0_0 = ALUOp::AndNot;
3784                             let expr1_0: Type = I64;
3785                             let expr2_0 = constructor_alu_rs_imm_logic(
3786                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3787                             )?;
3788                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3789                             return Some(expr3_0);
3790                         }
3791                         &Opcode::BorNot => {
3792                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3793                             // Rule at src/isa/aarch64/lower.isle line 638.
3794                             let expr0_0 = ALUOp::OrrNot;
3795                             let expr1_0: Type = I64;
3796                             let expr2_0 = constructor_alu_rs_imm_logic(
3797                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3798                             )?;
3799                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3800                             return Some(expr3_0);
3801                         }
3802                         &Opcode::BxorNot => {
3803                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3804                             // Rule at src/isa/aarch64/lower.isle line 648.
3805                             let expr0_0 = ALUOp::EorNot;
3806                             let expr1_0: Type = I64;
3807                             let expr2_0 = constructor_alu_rs_imm_logic(
3808                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
3809                             )?;
3810                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3811                             return Some(expr3_0);
3812                         }
3813                         &Opcode::Rotl => {
3814                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3815                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3816                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3817                                 if let &InstructionData::UnaryImm {
3818                                     opcode: ref pattern10_0,
3819                                     imm: pattern10_1,
3820                                 } = &pattern9_0
3821                                 {
3822                                     if let &Opcode::Iconst = pattern10_0 {
3823                                         let closure12 = || {
3824                                             let expr0_0: Type = I64;
3825                                             return Some(expr0_0);
3826                                         };
3827                                         if let Some(pattern12_0) = closure12() {
3828                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3829                                                 ctx,
3830                                                 pattern10_1,
3831                                                 pattern12_0,
3832                                             ) {
3833                                                 // Rule at src/isa/aarch64/lower.isle line 869.
3834                                                 let expr0_0: Type = I64;
3835                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3836                                                 let expr2_0: Type = I64;
3837                                                 let expr3_0 =
3838                                                     C::negate_imm_shift(ctx, expr2_0, pattern13_0);
3839                                                 let expr4_0 = constructor_a64_rotr_imm(
3840                                                     ctx, expr0_0, expr1_0, expr3_0,
3841                                                 )?;
3842                                                 let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
3843                                                 return Some(expr5_0);
3844                                             }
3845                                         }
3846                                     }
3847                                 }
3848                             }
3849                             // Rule at src/isa/aarch64/lower.isle line 860.
3850                             let expr0_0: Type = I64;
3851                             let expr1_0 = C::zero_reg(ctx);
3852                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3853                             let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
3854                             let expr4_0: Type = I64;
3855                             let expr5_0 = C::put_in_reg(ctx, pattern7_0);
3856                             let expr6_0 = constructor_a64_rotr(ctx, expr4_0, expr5_0, expr3_0)?;
3857                             let expr7_0 = constructor_output_reg(ctx, expr6_0)?;
3858                             return Some(expr7_0);
3859                         }
3860                         &Opcode::Rotr => {
3861                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3862                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
3863                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
3864                                 if let &InstructionData::UnaryImm {
3865                                     opcode: ref pattern10_0,
3866                                     imm: pattern10_1,
3867                                 } = &pattern9_0
3868                                 {
3869                                     if let &Opcode::Iconst = pattern10_0 {
3870                                         let closure12 = || {
3871                                             let expr0_0: Type = I64;
3872                                             return Some(expr0_0);
3873                                         };
3874                                         if let Some(pattern12_0) = closure12() {
3875                                             if let Some(pattern13_0) = C::imm_shift_from_imm64(
3876                                                 ctx,
3877                                                 pattern10_1,
3878                                                 pattern12_0,
3879                                             ) {
3880                                                 // Rule at src/isa/aarch64/lower.isle line 911.
3881                                                 let expr0_0: Type = I64;
3882                                                 let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3883                                                 let expr2_0 = constructor_a64_rotr_imm(
3884                                                     ctx,
3885                                                     expr0_0,
3886                                                     expr1_0,
3887                                                     pattern13_0,
3888                                                 )?;
3889                                                 let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
3890                                                 return Some(expr3_0);
3891                                             }
3892                                         }
3893                                     }
3894                                 }
3895                             }
3896                             // Rule at src/isa/aarch64/lower.isle line 899.
3897                             let expr0_0: Type = I64;
3898                             let expr1_0 = C::put_in_reg(ctx, pattern7_0);
3899                             let expr2_0 = C::put_in_reg(ctx, pattern7_1);
3900                             let expr3_0 = constructor_a64_rotr(ctx, expr0_0, expr1_0, expr2_0)?;
3901                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3902                             return Some(expr4_0);
3903                         }
3904                         &Opcode::Ishl => {
3905                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3906                             // Rule at src/isa/aarch64/lower.isle line 660.
3907                             let expr0_0 = ALUOp::Lsl;
3908                             let expr1_0: Type = I64;
3909                             let expr2_0 = C::put_in_reg(ctx, pattern7_0);
3910                             let expr3_0 =
3911                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
3912                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3913                             return Some(expr4_0);
3914                         }
3915                         &Opcode::Ushr => {
3916                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3917                             // Rule at src/isa/aarch64/lower.isle line 744.
3918                             let expr0_0 = ALUOp::Lsr;
3919                             let expr1_0: Type = I64;
3920                             let expr2_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
3921                             let expr3_0 =
3922                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
3923                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3924                             return Some(expr4_0);
3925                         }
3926                         &Opcode::Sshr => {
3927                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3928                             // Rule at src/isa/aarch64/lower.isle line 791.
3929                             let expr0_0 = ALUOp::Asr;
3930                             let expr1_0: Type = I64;
3931                             let expr2_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
3932                             let expr3_0 =
3933                                 constructor_do_shift(ctx, &expr0_0, expr1_0, expr2_0, pattern7_1)?;
3934                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
3935                             return Some(expr4_0);
3936                         }
3937                         _ => {}
3938                     }
3939                 }
3940                 &InstructionData::Unary {
3941                     opcode: ref pattern5_0,
3942                     arg: pattern5_1,
3943                 } => {
3944                     if let &Opcode::Popcnt = pattern5_0 {
3945                         // Rule at src/isa/aarch64/lower.isle line 1111.
3946                         let expr0_0 = C::put_in_reg(ctx, pattern5_1);
3947                         let expr1_0 = ScalarSize::Size64;
3948                         let expr2_0 = constructor_mov_to_fpu(ctx, expr0_0, &expr1_0)?;
3949                         let expr3_0 = VectorSize::Size8x8;
3950                         let expr4_0 = constructor_vec_cnt(ctx, expr2_0, &expr3_0)?;
3951                         let expr5_0 = VectorSize::Size8x8;
3952                         let expr6_0 = constructor_addv(ctx, expr4_0, &expr5_0)?;
3953                         let expr7_0: u8 = 0;
3954                         let expr8_0 = VectorSize::Size8x16;
3955                         let expr9_0 = constructor_mov_from_vec(ctx, expr6_0, expr7_0, &expr8_0)?;
3956                         let expr10_0 = constructor_output_reg(ctx, expr9_0)?;
3957                         return Some(expr10_0);
3958                     }
3959                 }
3960                 _ => {}
3961             }
3962         }
3963         if pattern2_0 == I128 {
3964             let pattern4_0 = C::inst_data(ctx, pattern0_0);
3965             match &pattern4_0 {
3966                 &InstructionData::Binary {
3967                     opcode: ref pattern5_0,
3968                     args: ref pattern5_1,
3969                 } => {
3970                     match pattern5_0 {
3971                         &Opcode::Iadd => {
3972                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3973                             // Rule at src/isa/aarch64/lower.isle line 79.
3974                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
3975                             let expr1_0: usize = 0;
3976                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3977                             let expr3_0: usize = 1;
3978                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
3979                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
3980                             let expr6_0: usize = 0;
3981                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
3982                             let expr8_0: usize = 1;
3983                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
3984                             let expr10_0: Type = I64;
3985                             let expr11_0 =
3986                                 constructor_add_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
3987                             let expr12_0: Type = I64;
3988                             let expr13_0 = constructor_adc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
3989                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
3990                             let expr15_0 = C::output(ctx, expr14_0);
3991                             return Some(expr15_0);
3992                         }
3993                         &Opcode::Isub => {
3994                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
3995                             // Rule at src/isa/aarch64/lower.isle line 129.
3996                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
3997                             let expr1_0: usize = 0;
3998                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
3999                             let expr3_0: usize = 1;
4000                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4001                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4002                             let expr6_0: usize = 0;
4003                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4004                             let expr8_0: usize = 1;
4005                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4006                             let expr10_0: Type = I64;
4007                             let expr11_0 =
4008                                 constructor_sub_with_flags_paired(ctx, expr10_0, expr2_0, expr7_0)?;
4009                             let expr12_0: Type = I64;
4010                             let expr13_0 = constructor_sbc_paired(ctx, expr12_0, expr4_0, expr9_0)?;
4011                             let expr14_0 = constructor_with_flags(ctx, &expr11_0, &expr13_0)?;
4012                             let expr15_0 = C::output(ctx, expr14_0);
4013                             return Some(expr15_0);
4014                         }
4015                         &Opcode::Imul => {
4016                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4017                             // Rule at src/isa/aarch64/lower.isle line 183.
4018                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4019                             let expr1_0: usize = 0;
4020                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4021                             let expr3_0: usize = 1;
4022                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4023                             let expr5_0 = C::put_in_regs(ctx, pattern7_1);
4024                             let expr6_0: usize = 0;
4025                             let expr7_0 = C::value_regs_get(ctx, expr5_0, expr6_0);
4026                             let expr8_0: usize = 1;
4027                             let expr9_0 = C::value_regs_get(ctx, expr5_0, expr8_0);
4028                             let expr10_0: Type = I64;
4029                             let expr11_0 = constructor_umulh(ctx, expr10_0, expr2_0, expr7_0)?;
4030                             let expr12_0 = constructor_madd64(ctx, expr2_0, expr9_0, expr11_0)?;
4031                             let expr13_0 = constructor_madd64(ctx, expr4_0, expr7_0, expr12_0)?;
4032                             let expr14_0 = C::zero_reg(ctx);
4033                             let expr15_0 = constructor_madd64(ctx, expr2_0, expr7_0, expr14_0)?;
4034                             let expr16_0 = C::value_regs(ctx, expr15_0, expr13_0);
4035                             let expr17_0 = C::output(ctx, expr16_0);
4036                             return Some(expr17_0);
4037                         }
4038                         &Opcode::Band => {
4039                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4040                             // Rule at src/isa/aarch64/lower.isle line 589.
4041                             let expr0_0 = ALUOp::And;
4042                             let expr1_0: Type = I64;
4043                             let expr2_0 = constructor_i128_alu_bitop(
4044                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4045                             )?;
4046                             let expr3_0 = C::output(ctx, expr2_0);
4047                             return Some(expr3_0);
4048                         }
4049                         &Opcode::Bor => {
4050                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4051                             // Rule at src/isa/aarch64/lower.isle line 602.
4052                             let expr0_0 = ALUOp::Orr;
4053                             let expr1_0: Type = I64;
4054                             let expr2_0 = constructor_i128_alu_bitop(
4055                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4056                             )?;
4057                             let expr3_0 = C::output(ctx, expr2_0);
4058                             return Some(expr3_0);
4059                         }
4060                         &Opcode::Bxor => {
4061                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4062                             // Rule at src/isa/aarch64/lower.isle line 615.
4063                             let expr0_0 = ALUOp::Eor;
4064                             let expr1_0: Type = I64;
4065                             let expr2_0 = constructor_i128_alu_bitop(
4066                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4067                             )?;
4068                             let expr3_0 = C::output(ctx, expr2_0);
4069                             return Some(expr3_0);
4070                         }
4071                         &Opcode::BandNot => {
4072                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4073                             // Rule at src/isa/aarch64/lower.isle line 628.
4074                             let expr0_0 = ALUOp::AndNot;
4075                             let expr1_0: Type = I64;
4076                             let expr2_0 = constructor_i128_alu_bitop(
4077                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4078                             )?;
4079                             let expr3_0 = C::output(ctx, expr2_0);
4080                             return Some(expr3_0);
4081                         }
4082                         &Opcode::BorNot => {
4083                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4084                             // Rule at src/isa/aarch64/lower.isle line 641.
4085                             let expr0_0 = ALUOp::OrrNot;
4086                             let expr1_0: Type = I64;
4087                             let expr2_0 = constructor_i128_alu_bitop(
4088                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4089                             )?;
4090                             let expr3_0 = C::output(ctx, expr2_0);
4091                             return Some(expr3_0);
4092                         }
4093                         &Opcode::BxorNot => {
4094                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4095                             // Rule at src/isa/aarch64/lower.isle line 651.
4096                             let expr0_0 = ALUOp::EorNot;
4097                             let expr1_0: Type = I64;
4098                             let expr2_0 = constructor_i128_alu_bitop(
4099                                 ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
4100                             )?;
4101                             let expr3_0 = C::output(ctx, expr2_0);
4102                             return Some(expr3_0);
4103                         }
4104                         &Opcode::Rotl => {
4105                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4106                             // Rule at src/isa/aarch64/lower.isle line 878.
4107                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4108                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4109                             let expr2_0: usize = 0;
4110                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4111                             let expr4_0: Type = I64;
4112                             let expr5_0: Type = I64;
4113                             let expr6_0: u64 = 128;
4114                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4115                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4116                             let expr9_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4117                             let expr10_0 = constructor_lower_ushr128(ctx, expr0_0, expr8_0)?;
4118                             let expr11_0: Type = I64;
4119                             let expr12_0: usize = 0;
4120                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4121                             let expr14_0: usize = 0;
4122                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4123                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4124                             let expr17_0: Type = I64;
4125                             let expr18_0: usize = 1;
4126                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4127                             let expr20_0: usize = 1;
4128                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4129                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4130                             let expr23_0 = C::value_regs(ctx, expr16_0, expr22_0);
4131                             let expr24_0 = C::output(ctx, expr23_0);
4132                             return Some(expr24_0);
4133                         }
4134                         &Opcode::Rotr => {
4135                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4136                             // Rule at src/isa/aarch64/lower.isle line 959.
4137                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4138                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4139                             let expr2_0: usize = 0;
4140                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4141                             let expr4_0: Type = I64;
4142                             let expr5_0: Type = I64;
4143                             let expr6_0: u64 = 128;
4144                             let expr7_0 = constructor_imm(ctx, expr5_0, expr6_0)?;
4145                             let expr8_0 = constructor_sub(ctx, expr4_0, expr7_0, expr3_0)?;
4146                             let expr9_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4147                             let expr10_0 = constructor_lower_shl128(ctx, expr0_0, expr8_0)?;
4148                             let expr11_0: Type = I64;
4149                             let expr12_0: usize = 1;
4150                             let expr13_0 = C::value_regs_get(ctx, expr9_0, expr12_0);
4151                             let expr14_0: usize = 1;
4152                             let expr15_0 = C::value_regs_get(ctx, expr10_0, expr14_0);
4153                             let expr16_0 = constructor_orr(ctx, expr11_0, expr13_0, expr15_0)?;
4154                             let expr17_0: Type = I64;
4155                             let expr18_0: usize = 0;
4156                             let expr19_0 = C::value_regs_get(ctx, expr9_0, expr18_0);
4157                             let expr20_0: usize = 0;
4158                             let expr21_0 = C::value_regs_get(ctx, expr10_0, expr20_0);
4159                             let expr22_0 = constructor_orr(ctx, expr17_0, expr19_0, expr21_0)?;
4160                             let expr23_0 = C::value_regs(ctx, expr22_0, expr16_0);
4161                             let expr24_0 = C::output(ctx, expr23_0);
4162                             return Some(expr24_0);
4163                         }
4164                         &Opcode::Ishl => {
4165                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4166                             // Rule at src/isa/aarch64/lower.isle line 664.
4167                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4168                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4169                             let expr2_0: usize = 0;
4170                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4171                             let expr4_0 = constructor_lower_shl128(ctx, expr0_0, expr3_0)?;
4172                             let expr5_0 = C::output(ctx, expr4_0);
4173                             return Some(expr5_0);
4174                         }
4175                         &Opcode::Ushr => {
4176                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4177                             // Rule at src/isa/aarch64/lower.isle line 748.
4178                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4179                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4180                             let expr2_0: usize = 0;
4181                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4182                             let expr4_0 = constructor_lower_ushr128(ctx, expr0_0, expr3_0)?;
4183                             let expr5_0 = C::output(ctx, expr4_0);
4184                             return Some(expr5_0);
4185                         }
4186                         &Opcode::Sshr => {
4187                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4188                             // Rule at src/isa/aarch64/lower.isle line 795.
4189                             let expr0_0 = C::put_in_regs(ctx, pattern7_0);
4190                             let expr1_0 = C::put_in_regs(ctx, pattern7_1);
4191                             let expr2_0: usize = 0;
4192                             let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
4193                             let expr4_0 = constructor_lower_sshr128(ctx, expr0_0, expr3_0)?;
4194                             let expr5_0 = C::output(ctx, expr4_0);
4195                             return Some(expr5_0);
4196                         }
4197                         _ => {}
4198                     }
4199                 }
4200                 &InstructionData::Unary {
4201                     opcode: ref pattern5_0,
4202                     arg: pattern5_1,
4203                 } => {
4204                     match pattern5_0 {
4205                         &Opcode::Bnot => {
4206                             // Rule at src/isa/aarch64/lower.isle line 569.
4207                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4208                             let expr1_0: usize = 0;
4209                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4210                             let expr3_0: usize = 1;
4211                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4212                             let expr5_0: Type = I64;
4213                             let expr6_0 = C::zero_reg(ctx);
4214                             let expr7_0 = constructor_orr_not(ctx, expr5_0, expr6_0, expr2_0)?;
4215                             let expr8_0: Type = I64;
4216                             let expr9_0 = C::zero_reg(ctx);
4217                             let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, expr4_0)?;
4218                             let expr11_0 = C::value_regs(ctx, expr7_0, expr10_0);
4219                             let expr12_0 = C::output(ctx, expr11_0);
4220                             return Some(expr12_0);
4221                         }
4222                         &Opcode::Bitrev => {
4223                             // Rule at src/isa/aarch64/lower.isle line 983.
4224                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4225                             let expr1_0: Type = I64;
4226                             let expr2_0: usize = 0;
4227                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4228                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4229                             let expr5_0: Type = I64;
4230                             let expr6_0: usize = 1;
4231                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4232                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4233                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4234                             let expr10_0 = C::output(ctx, expr9_0);
4235                             return Some(expr10_0);
4236                         }
4237                         &Opcode::Clz => {
4238                             // Rule at src/isa/aarch64/lower.isle line 1001.
4239                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4240                             let expr1_0 = constructor_lower_clz128(ctx, expr0_0)?;
4241                             let expr2_0 = C::output(ctx, expr1_0);
4242                             return Some(expr2_0);
4243                         }
4244                         &Opcode::Cls => {
4245                             // Rule at src/isa/aarch64/lower.isle line 1057.
4246                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4247                             let expr1_0: usize = 0;
4248                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4249                             let expr3_0: usize = 1;
4250                             let expr4_0 = C::value_regs_get(ctx, expr0_0, expr3_0);
4251                             let expr5_0: Type = I64;
4252                             let expr6_0 = constructor_a64_cls(ctx, expr5_0, expr2_0)?;
4253                             let expr7_0: Type = I64;
4254                             let expr8_0 = constructor_a64_cls(ctx, expr7_0, expr4_0)?;
4255                             let expr9_0: Type = I64;
4256                             let expr10_0 = constructor_eon(ctx, expr9_0, expr4_0, expr2_0)?;
4257                             let expr11_0: Type = I64;
4258                             let expr12_0: u8 = 63;
4259                             let expr13_0 = C::imm_shift_from_u8(ctx, expr12_0);
4260                             let expr14_0 = constructor_lsr_imm(ctx, expr11_0, expr10_0, expr13_0)?;
4261                             let expr15_0 = constructor_madd64(ctx, expr6_0, expr14_0, expr14_0)?;
4262                             let expr16_0: u8 = 63;
4263                             let expr17_0 = C::u8_into_imm12(ctx, expr16_0);
4264                             let expr18_0 = constructor_cmp64_imm(ctx, expr8_0, expr17_0)?;
4265                             let expr19_0 = Cond::Eq;
4266                             let expr20_0 = C::zero_reg(ctx);
4267                             let expr21_0 = constructor_csel(ctx, &expr19_0, expr15_0, expr20_0)?;
4268                             let expr22_0 = constructor_with_flags_reg(ctx, &expr18_0, &expr21_0)?;
4269                             let expr23_0: Type = I64;
4270                             let expr24_0 = constructor_add(ctx, expr23_0, expr22_0, expr8_0)?;
4271                             let expr25_0: Type = I64;
4272                             let expr26_0: u64 = 0;
4273                             let expr27_0 = constructor_imm(ctx, expr25_0, expr26_0)?;
4274                             let expr28_0 = C::value_regs(ctx, expr24_0, expr27_0);
4275                             let expr29_0 = C::output(ctx, expr28_0);
4276                             return Some(expr29_0);
4277                         }
4278                         &Opcode::Ctz => {
4279                             // Rule at src/isa/aarch64/lower.isle line 1031.
4280                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4281                             let expr1_0: Type = I64;
4282                             let expr2_0: usize = 0;
4283                             let expr3_0 = C::value_regs_get(ctx, expr0_0, expr2_0);
4284                             let expr4_0 = constructor_rbit(ctx, expr1_0, expr3_0)?;
4285                             let expr5_0: Type = I64;
4286                             let expr6_0: usize = 1;
4287                             let expr7_0 = C::value_regs_get(ctx, expr0_0, expr6_0);
4288                             let expr8_0 = constructor_rbit(ctx, expr5_0, expr7_0)?;
4289                             let expr9_0 = C::value_regs(ctx, expr8_0, expr4_0);
4290                             let expr10_0 = constructor_lower_clz128(ctx, expr9_0)?;
4291                             let expr11_0 = C::output(ctx, expr10_0);
4292                             return Some(expr11_0);
4293                         }
4294                         &Opcode::Popcnt => {
4295                             // Rule at src/isa/aarch64/lower.isle line 1117.
4296                             let expr0_0 = C::put_in_regs(ctx, pattern5_1);
4297                             let expr1_0: usize = 0;
4298                             let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
4299                             let expr3_0 = ScalarSize::Size64;
4300                             let expr4_0 = constructor_mov_to_fpu(ctx, expr2_0, &expr3_0)?;
4301                             let expr5_0: usize = 1;
4302                             let expr6_0 = C::value_regs_get(ctx, expr0_0, expr5_0);
4303                             let expr7_0: u8 = 1;
4304                             let expr8_0 = VectorSize::Size64x2;
4305                             let expr9_0 =
4306                                 constructor_mov_to_vec(ctx, expr4_0, expr6_0, expr7_0, &expr8_0)?;
4307                             let expr10_0 = VectorSize::Size8x16;
4308                             let expr11_0 = constructor_vec_cnt(ctx, expr9_0, &expr10_0)?;
4309                             let expr12_0 = VectorSize::Size8x16;
4310                             let expr13_0 = constructor_addv(ctx, expr11_0, &expr12_0)?;
4311                             let expr14_0: u8 = 0;
4312                             let expr15_0 = VectorSize::Size8x16;
4313                             let expr16_0 =
4314                                 constructor_mov_from_vec(ctx, expr13_0, expr14_0, &expr15_0)?;
4315                             let expr17_0: Type = I64;
4316                             let expr18_0: u64 = 0;
4317                             let expr19_0 = constructor_imm(ctx, expr17_0, expr18_0)?;
4318                             let expr20_0 = C::value_regs(ctx, expr16_0, expr19_0);
4319                             let expr21_0 = C::output(ctx, expr20_0);
4320                             return Some(expr21_0);
4321                         }
4322                         &Opcode::Uextend => {
4323                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4324                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4325                                 if let &InstructionData::BinaryImm8 {
4326                                     opcode: ref pattern9_0,
4327                                     arg: pattern9_1,
4328                                     imm: pattern9_2,
4329                                 } = &pattern8_0
4330                                 {
4331                                     if let &Opcode::Extractlane = pattern9_0 {
4332                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4333                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
4334                                         // Rule at src/isa/aarch64/lower.isle line 499.
4335                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4336                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
4337                                         let expr2_0 = constructor_mov_from_vec(
4338                                             ctx,
4339                                             expr0_0,
4340                                             pattern12_0,
4341                                             &expr1_0,
4342                                         )?;
4343                                         let expr3_0: Type = I64;
4344                                         let expr4_0: u64 = 0;
4345                                         let expr5_0 = constructor_imm(ctx, expr3_0, expr4_0)?;
4346                                         let expr6_0 = C::value_regs(ctx, expr2_0, expr5_0);
4347                                         let expr7_0 = C::output(ctx, expr6_0);
4348                                         return Some(expr7_0);
4349                                     }
4350                                 }
4351                             }
4352                             // Rule at src/isa/aarch64/lower.isle line 494.
4353                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern5_1)?;
4354                             let expr1_0: Type = I64;
4355                             let expr2_0: u64 = 0;
4356                             let expr3_0 = constructor_imm(ctx, expr1_0, expr2_0)?;
4357                             let expr4_0 = C::value_regs(ctx, expr0_0, expr3_0);
4358                             let expr5_0 = C::output(ctx, expr4_0);
4359                             return Some(expr5_0);
4360                         }
4361                         &Opcode::Sextend => {
4362                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
4363                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
4364                                 if let &InstructionData::BinaryImm8 {
4365                                     opcode: ref pattern9_0,
4366                                     arg: pattern9_1,
4367                                     imm: pattern9_2,
4368                                 } = &pattern8_0
4369                                 {
4370                                     if let &Opcode::Extractlane = pattern9_0 {
4371                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
4372                                         if pattern11_0 == I64X2 {
4373                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4374                                             // Rule at src/isa/aarch64/lower.isle line 543.
4375                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4376                                             let expr1_0 = VectorSize::Size64x2;
4377                                             let expr2_0 = constructor_mov_from_vec(
4378                                                 ctx,
4379                                                 expr0_0,
4380                                                 pattern13_0,
4381                                                 &expr1_0,
4382                                             )?;
4383                                             let expr3_0: Type = I64;
4384                                             let expr4_0: u8 = 63;
4385                                             let expr5_0 = C::imm_shift_from_u8(ctx, expr4_0);
4386                                             let expr6_0 = constructor_asr_imm(
4387                                                 ctx, expr3_0, expr2_0, expr5_0,
4388                                             )?;
4389                                             let expr7_0 = C::value_regs(ctx, expr2_0, expr6_0);
4390                                             let expr8_0 = C::output(ctx, expr7_0);
4391                                             return Some(expr8_0);
4392                                         }
4393                                         if let Some(()) = C::not_i64x2(ctx, pattern11_0) {
4394                                             let pattern13_0 = C::u8_from_uimm8(ctx, pattern9_2);
4395                                             // Rule at src/isa/aarch64/lower.isle line 532.
4396                                             let expr0_0 = C::put_in_reg(ctx, pattern9_1);
4397                                             let expr1_0 =
4398                                                 constructor_vector_size(ctx, pattern11_0)?;
4399                                             let expr2_0: Type = I64;
4400                                             let expr3_0 = constructor_size_from_ty(ctx, expr2_0)?;
4401                                             let expr4_0 = constructor_mov_from_vec_signed(
4402                                                 ctx,
4403                                                 expr0_0,
4404                                                 pattern13_0,
4405                                                 &expr1_0,
4406                                                 &expr3_0,
4407                                             )?;
4408                                             let expr5_0: Type = I64;
4409                                             let expr6_0: u8 = 63;
4410                                             let expr7_0 = C::imm_shift_from_u8(ctx, expr6_0);
4411                                             let expr8_0 = constructor_asr_imm(
4412                                                 ctx, expr5_0, expr4_0, expr7_0,
4413                                             )?;
4414                                             let expr9_0 = C::value_regs(ctx, expr4_0, expr8_0);
4415                                             let expr10_0 = C::output(ctx, expr9_0);
4416                                             return Some(expr10_0);
4417                                         }
4418                                     }
4419                                 }
4420                             }
4421                             // Rule at src/isa/aarch64/lower.isle line 522.
4422                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern5_1)?;
4423                             let expr1_0: Type = I64;
4424                             let expr2_0: u8 = 63;
4425                             let expr3_0 = C::imm_shift_from_u8(ctx, expr2_0);
4426                             let expr4_0 = constructor_asr_imm(ctx, expr1_0, expr0_0, expr3_0)?;
4427                             let expr5_0 = C::value_regs(ctx, expr0_0, expr4_0);
4428                             let expr6_0 = C::output(ctx, expr5_0);
4429                             return Some(expr6_0);
4430                         }
4431                         _ => {}
4432                     }
4433                 }
4434                 _ => {}
4435             }
4436         }
4437         if pattern2_0 == I8X16 {
4438             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4439             if let &InstructionData::Unary {
4440                 opcode: ref pattern5_0,
4441                 arg: pattern5_1,
4442             } = &pattern4_0
4443             {
4444                 if let &Opcode::Popcnt = pattern5_0 {
4445                     // Rule at src/isa/aarch64/lower.isle line 1125.
4446                     let expr0_0 = C::put_in_reg(ctx, pattern5_1);
4447                     let expr1_0 = VectorSize::Size8x16;
4448                     let expr2_0 = constructor_vec_cnt(ctx, expr0_0, &expr1_0)?;
4449                     let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
4450                     return Some(expr3_0);
4451                 }
4452             }
4453         }
4454         if pattern2_0 == I16X8 {
4455             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4456             if let &InstructionData::Binary {
4457                 opcode: ref pattern5_0,
4458                 args: ref pattern5_1,
4459             } = &pattern4_0
4460             {
4461                 if let &Opcode::Imul = pattern5_0 {
4462                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4463                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4464                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4465                         if let &InstructionData::Unary {
4466                             opcode: ref pattern10_0,
4467                             arg: pattern10_1,
4468                         } = &pattern9_0
4469                         {
4470                             match pattern10_0 {
4471                                 &Opcode::SwidenLow => {
4472                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4473                                     if pattern12_0 == I8X16 {
4474                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4475                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4476                                             if let &InstructionData::Unary {
4477                                                 opcode: ref pattern16_0,
4478                                                 arg: pattern16_1,
4479                                             } = &pattern15_0
4480                                             {
4481                                                 if let &Opcode::SwidenLow = pattern16_0 {
4482                                                     let pattern18_0 =
4483                                                         C::value_type(ctx, pattern16_1);
4484                                                     if pattern18_0 == I8X16 {
4485                                                         // Rule at src/isa/aarch64/lower.isle line 282.
4486                                                         let expr0_0 =
4487                                                             C::put_in_reg(ctx, pattern10_1);
4488                                                         let expr1_0 =
4489                                                             C::put_in_reg(ctx, pattern16_1);
4490                                                         let expr2_0: bool = false;
4491                                                         let expr3_0 = constructor_smull8(
4492                                                             ctx, expr0_0, expr1_0, expr2_0,
4493                                                         )?;
4494                                                         let expr4_0 =
4495                                                             constructor_output_reg(ctx, expr3_0)?;
4496                                                         return Some(expr4_0);
4497                                                     }
4498                                                 }
4499                                             }
4500                                         }
4501                                     }
4502                                 }
4503                                 &Opcode::SwidenHigh => {
4504                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4505                                     if pattern12_0 == I8X16 {
4506                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4507                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4508                                             if let &InstructionData::Unary {
4509                                                 opcode: ref pattern16_0,
4510                                                 arg: pattern16_1,
4511                                             } = &pattern15_0
4512                                             {
4513                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4514                                                     let pattern18_0 =
4515                                                         C::value_type(ctx, pattern16_1);
4516                                                     if pattern18_0 == I8X16 {
4517                                                         // Rule at src/isa/aarch64/lower.isle line 288.
4518                                                         let expr0_0 =
4519                                                             C::put_in_reg(ctx, pattern10_1);
4520                                                         let expr1_0 =
4521                                                             C::put_in_reg(ctx, pattern16_1);
4522                                                         let expr2_0: bool = true;
4523                                                         let expr3_0 = constructor_smull8(
4524                                                             ctx, expr0_0, expr1_0, expr2_0,
4525                                                         )?;
4526                                                         let expr4_0 =
4527                                                             constructor_output_reg(ctx, expr3_0)?;
4528                                                         return Some(expr4_0);
4529                                                     }
4530                                                 }
4531                                             }
4532                                         }
4533                                     }
4534                                 }
4535                                 &Opcode::UwidenLow => {
4536                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4537                                     if pattern12_0 == I8X16 {
4538                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4539                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4540                                             if let &InstructionData::Unary {
4541                                                 opcode: ref pattern16_0,
4542                                                 arg: pattern16_1,
4543                                             } = &pattern15_0
4544                                             {
4545                                                 if let &Opcode::UwidenLow = pattern16_0 {
4546                                                     let pattern18_0 =
4547                                                         C::value_type(ctx, pattern16_1);
4548                                                     if pattern18_0 == I8X16 {
4549                                                         // Rule at src/isa/aarch64/lower.isle line 294.
4550                                                         let expr0_0 =
4551                                                             C::put_in_reg(ctx, pattern10_1);
4552                                                         let expr1_0 =
4553                                                             C::put_in_reg(ctx, pattern16_1);
4554                                                         let expr2_0: bool = false;
4555                                                         let expr3_0 = constructor_umull8(
4556                                                             ctx, expr0_0, expr1_0, expr2_0,
4557                                                         )?;
4558                                                         let expr4_0 =
4559                                                             constructor_output_reg(ctx, expr3_0)?;
4560                                                         return Some(expr4_0);
4561                                                     }
4562                                                 }
4563                                             }
4564                                         }
4565                                     }
4566                                 }
4567                                 &Opcode::UwidenHigh => {
4568                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4569                                     if pattern12_0 == I8X16 {
4570                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4571                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4572                                             if let &InstructionData::Unary {
4573                                                 opcode: ref pattern16_0,
4574                                                 arg: pattern16_1,
4575                                             } = &pattern15_0
4576                                             {
4577                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4578                                                     let pattern18_0 =
4579                                                         C::value_type(ctx, pattern16_1);
4580                                                     if pattern18_0 == I8X16 {
4581                                                         // Rule at src/isa/aarch64/lower.isle line 300.
4582                                                         let expr0_0 =
4583                                                             C::put_in_reg(ctx, pattern10_1);
4584                                                         let expr1_0 =
4585                                                             C::put_in_reg(ctx, pattern16_1);
4586                                                         let expr2_0: bool = true;
4587                                                         let expr3_0 = constructor_umull8(
4588                                                             ctx, expr0_0, expr1_0, expr2_0,
4589                                                         )?;
4590                                                         let expr4_0 =
4591                                                             constructor_output_reg(ctx, expr3_0)?;
4592                                                         return Some(expr4_0);
4593                                                     }
4594                                                 }
4595                                             }
4596                                         }
4597                                     }
4598                                 }
4599                                 _ => {}
4600                             }
4601                         }
4602                     }
4603                 }
4604             }
4605         }
4606         if pattern2_0 == I32X4 {
4607             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4608             if let &InstructionData::Binary {
4609                 opcode: ref pattern5_0,
4610                 args: ref pattern5_1,
4611             } = &pattern4_0
4612             {
4613                 if let &Opcode::Imul = pattern5_0 {
4614                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4615                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4616                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4617                         if let &InstructionData::Unary {
4618                             opcode: ref pattern10_0,
4619                             arg: pattern10_1,
4620                         } = &pattern9_0
4621                         {
4622                             match pattern10_0 {
4623                                 &Opcode::SwidenLow => {
4624                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4625                                     if pattern12_0 == I16X8 {
4626                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4627                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4628                                             if let &InstructionData::Unary {
4629                                                 opcode: ref pattern16_0,
4630                                                 arg: pattern16_1,
4631                                             } = &pattern15_0
4632                                             {
4633                                                 if let &Opcode::SwidenLow = pattern16_0 {
4634                                                     let pattern18_0 =
4635                                                         C::value_type(ctx, pattern16_1);
4636                                                     if pattern18_0 == I16X8 {
4637                                                         // Rule at src/isa/aarch64/lower.isle line 306.
4638                                                         let expr0_0 =
4639                                                             C::put_in_reg(ctx, pattern10_1);
4640                                                         let expr1_0 =
4641                                                             C::put_in_reg(ctx, pattern16_1);
4642                                                         let expr2_0: bool = false;
4643                                                         let expr3_0 = constructor_smull16(
4644                                                             ctx, expr0_0, expr1_0, expr2_0,
4645                                                         )?;
4646                                                         let expr4_0 =
4647                                                             constructor_output_reg(ctx, expr3_0)?;
4648                                                         return Some(expr4_0);
4649                                                     }
4650                                                 }
4651                                             }
4652                                         }
4653                                     }
4654                                 }
4655                                 &Opcode::SwidenHigh => {
4656                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4657                                     if pattern12_0 == I16X8 {
4658                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4659                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4660                                             if let &InstructionData::Unary {
4661                                                 opcode: ref pattern16_0,
4662                                                 arg: pattern16_1,
4663                                             } = &pattern15_0
4664                                             {
4665                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4666                                                     let pattern18_0 =
4667                                                         C::value_type(ctx, pattern16_1);
4668                                                     if pattern18_0 == I16X8 {
4669                                                         // Rule at src/isa/aarch64/lower.isle line 312.
4670                                                         let expr0_0 =
4671                                                             C::put_in_reg(ctx, pattern10_1);
4672                                                         let expr1_0 =
4673                                                             C::put_in_reg(ctx, pattern16_1);
4674                                                         let expr2_0: bool = true;
4675                                                         let expr3_0 = constructor_smull16(
4676                                                             ctx, expr0_0, expr1_0, expr2_0,
4677                                                         )?;
4678                                                         let expr4_0 =
4679                                                             constructor_output_reg(ctx, expr3_0)?;
4680                                                         return Some(expr4_0);
4681                                                     }
4682                                                 }
4683                                             }
4684                                         }
4685                                     }
4686                                 }
4687                                 &Opcode::UwidenLow => {
4688                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4689                                     if pattern12_0 == I16X8 {
4690                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4691                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4692                                             if let &InstructionData::Unary {
4693                                                 opcode: ref pattern16_0,
4694                                                 arg: pattern16_1,
4695                                             } = &pattern15_0
4696                                             {
4697                                                 if let &Opcode::UwidenLow = pattern16_0 {
4698                                                     let pattern18_0 =
4699                                                         C::value_type(ctx, pattern16_1);
4700                                                     if pattern18_0 == I16X8 {
4701                                                         // Rule at src/isa/aarch64/lower.isle line 318.
4702                                                         let expr0_0 =
4703                                                             C::put_in_reg(ctx, pattern10_1);
4704                                                         let expr1_0 =
4705                                                             C::put_in_reg(ctx, pattern16_1);
4706                                                         let expr2_0: bool = false;
4707                                                         let expr3_0 = constructor_umull16(
4708                                                             ctx, expr0_0, expr1_0, expr2_0,
4709                                                         )?;
4710                                                         let expr4_0 =
4711                                                             constructor_output_reg(ctx, expr3_0)?;
4712                                                         return Some(expr4_0);
4713                                                     }
4714                                                 }
4715                                             }
4716                                         }
4717                                     }
4718                                 }
4719                                 &Opcode::UwidenHigh => {
4720                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4721                                     if pattern12_0 == I16X8 {
4722                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4723                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4724                                             if let &InstructionData::Unary {
4725                                                 opcode: ref pattern16_0,
4726                                                 arg: pattern16_1,
4727                                             } = &pattern15_0
4728                                             {
4729                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4730                                                     let pattern18_0 =
4731                                                         C::value_type(ctx, pattern16_1);
4732                                                     if pattern18_0 == I16X8 {
4733                                                         // Rule at src/isa/aarch64/lower.isle line 324.
4734                                                         let expr0_0 =
4735                                                             C::put_in_reg(ctx, pattern10_1);
4736                                                         let expr1_0 =
4737                                                             C::put_in_reg(ctx, pattern16_1);
4738                                                         let expr2_0: bool = true;
4739                                                         let expr3_0 = constructor_umull16(
4740                                                             ctx, expr0_0, expr1_0, expr2_0,
4741                                                         )?;
4742                                                         let expr4_0 =
4743                                                             constructor_output_reg(ctx, expr3_0)?;
4744                                                         return Some(expr4_0);
4745                                                     }
4746                                                 }
4747                                             }
4748                                         }
4749                                     }
4750                                 }
4751                                 _ => {}
4752                             }
4753                         }
4754                     }
4755                 }
4756             }
4757         }
4758         if pattern2_0 == I64X2 {
4759             let pattern4_0 = C::inst_data(ctx, pattern0_0);
4760             if let &InstructionData::Binary {
4761                 opcode: ref pattern5_0,
4762                 args: ref pattern5_1,
4763             } = &pattern4_0
4764             {
4765                 if let &Opcode::Imul = pattern5_0 {
4766                     let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
4767                     if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
4768                         let pattern9_0 = C::inst_data(ctx, pattern8_0);
4769                         if let &InstructionData::Unary {
4770                             opcode: ref pattern10_0,
4771                             arg: pattern10_1,
4772                         } = &pattern9_0
4773                         {
4774                             match pattern10_0 {
4775                                 &Opcode::SwidenLow => {
4776                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4777                                     if pattern12_0 == I32X4 {
4778                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4779                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4780                                             if let &InstructionData::Unary {
4781                                                 opcode: ref pattern16_0,
4782                                                 arg: pattern16_1,
4783                                             } = &pattern15_0
4784                                             {
4785                                                 if let &Opcode::SwidenLow = pattern16_0 {
4786                                                     let pattern18_0 =
4787                                                         C::value_type(ctx, pattern16_1);
4788                                                     if pattern18_0 == I32X4 {
4789                                                         // Rule at src/isa/aarch64/lower.isle line 330.
4790                                                         let expr0_0 =
4791                                                             C::put_in_reg(ctx, pattern10_1);
4792                                                         let expr1_0 =
4793                                                             C::put_in_reg(ctx, pattern16_1);
4794                                                         let expr2_0: bool = false;
4795                                                         let expr3_0 = constructor_smull32(
4796                                                             ctx, expr0_0, expr1_0, expr2_0,
4797                                                         )?;
4798                                                         let expr4_0 =
4799                                                             constructor_output_reg(ctx, expr3_0)?;
4800                                                         return Some(expr4_0);
4801                                                     }
4802                                                 }
4803                                             }
4804                                         }
4805                                     }
4806                                 }
4807                                 &Opcode::SwidenHigh => {
4808                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4809                                     if pattern12_0 == I32X4 {
4810                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4811                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4812                                             if let &InstructionData::Unary {
4813                                                 opcode: ref pattern16_0,
4814                                                 arg: pattern16_1,
4815                                             } = &pattern15_0
4816                                             {
4817                                                 if let &Opcode::SwidenHigh = pattern16_0 {
4818                                                     let pattern18_0 =
4819                                                         C::value_type(ctx, pattern16_1);
4820                                                     if pattern18_0 == I32X4 {
4821                                                         // Rule at src/isa/aarch64/lower.isle line 336.
4822                                                         let expr0_0 =
4823                                                             C::put_in_reg(ctx, pattern10_1);
4824                                                         let expr1_0 =
4825                                                             C::put_in_reg(ctx, pattern16_1);
4826                                                         let expr2_0: bool = true;
4827                                                         let expr3_0 = constructor_smull32(
4828                                                             ctx, expr0_0, expr1_0, expr2_0,
4829                                                         )?;
4830                                                         let expr4_0 =
4831                                                             constructor_output_reg(ctx, expr3_0)?;
4832                                                         return Some(expr4_0);
4833                                                     }
4834                                                 }
4835                                             }
4836                                         }
4837                                     }
4838                                 }
4839                                 &Opcode::UwidenLow => {
4840                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4841                                     if pattern12_0 == I32X4 {
4842                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4843                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4844                                             if let &InstructionData::Unary {
4845                                                 opcode: ref pattern16_0,
4846                                                 arg: pattern16_1,
4847                                             } = &pattern15_0
4848                                             {
4849                                                 if let &Opcode::UwidenLow = pattern16_0 {
4850                                                     let pattern18_0 =
4851                                                         C::value_type(ctx, pattern16_1);
4852                                                     if pattern18_0 == I32X4 {
4853                                                         // Rule at src/isa/aarch64/lower.isle line 342.
4854                                                         let expr0_0 =
4855                                                             C::put_in_reg(ctx, pattern10_1);
4856                                                         let expr1_0 =
4857                                                             C::put_in_reg(ctx, pattern16_1);
4858                                                         let expr2_0: bool = false;
4859                                                         let expr3_0 = constructor_umull32(
4860                                                             ctx, expr0_0, expr1_0, expr2_0,
4861                                                         )?;
4862                                                         let expr4_0 =
4863                                                             constructor_output_reg(ctx, expr3_0)?;
4864                                                         return Some(expr4_0);
4865                                                     }
4866                                                 }
4867                                             }
4868                                         }
4869                                     }
4870                                 }
4871                                 &Opcode::UwidenHigh => {
4872                                     let pattern12_0 = C::value_type(ctx, pattern10_1);
4873                                     if pattern12_0 == I32X4 {
4874                                         if let Some(pattern14_0) = C::def_inst(ctx, pattern7_1) {
4875                                             let pattern15_0 = C::inst_data(ctx, pattern14_0);
4876                                             if let &InstructionData::Unary {
4877                                                 opcode: ref pattern16_0,
4878                                                 arg: pattern16_1,
4879                                             } = &pattern15_0
4880                                             {
4881                                                 if let &Opcode::UwidenHigh = pattern16_0 {
4882                                                     let pattern18_0 =
4883                                                         C::value_type(ctx, pattern16_1);
4884                                                     if pattern18_0 == I32X4 {
4885                                                         // Rule at src/isa/aarch64/lower.isle line 348.
4886                                                         let expr0_0 =
4887                                                             C::put_in_reg(ctx, pattern10_1);
4888                                                         let expr1_0 =
4889                                                             C::put_in_reg(ctx, pattern16_1);
4890                                                         let expr2_0: bool = true;
4891                                                         let expr3_0 = constructor_umull32(
4892                                                             ctx, expr0_0, expr1_0, expr2_0,
4893                                                         )?;
4894                                                         let expr4_0 =
4895                                                             constructor_output_reg(ctx, expr3_0)?;
4896                                                         return Some(expr4_0);
4897                                                     }
4898                                                 }
4899                                             }
4900                                         }
4901                                     }
4902                                 }
4903                                 _ => {}
4904                             }
4905                         }
4906                     }
4907                     // Rule at src/isa/aarch64/lower.isle line 243.
4908                     let expr0_0 = C::put_in_reg(ctx, pattern7_0);
4909                     let expr1_0 = C::put_in_reg(ctx, pattern7_1);
4910                     let expr2_0 = VectorSize::Size32x4;
4911                     let expr3_0 = constructor_rev64(ctx, expr1_0, &expr2_0)?;
4912                     let expr4_0 = VectorSize::Size32x4;
4913                     let expr5_0 = constructor_mul(ctx, expr3_0, expr0_0, &expr4_0)?;
4914                     let expr6_0: bool = false;
4915                     let expr7_0 = constructor_xtn64(ctx, expr0_0, expr6_0)?;
4916                     let expr8_0 = VectorSize::Size32x4;
4917                     let expr9_0 = constructor_addp(ctx, expr5_0, expr5_0, &expr8_0)?;
4918                     let expr10_0: bool = false;
4919                     let expr11_0 = constructor_xtn64(ctx, expr1_0, expr10_0)?;
4920                     let expr12_0: bool = false;
4921                     let expr13_0 = constructor_shll32(ctx, expr9_0, expr12_0)?;
4922                     let expr14_0: bool = false;
4923                     let expr15_0 = constructor_umlal32(ctx, expr13_0, expr11_0, expr7_0, expr14_0)?;
4924                     let expr16_0 = constructor_output_reg(ctx, expr15_0)?;
4925                     return Some(expr16_0);
4926                 }
4927             }
4928         }
4929         let pattern3_0 = C::inst_data(ctx, pattern0_0);
4930         match &pattern3_0 {
4931             &InstructionData::NullAry {
4932                 opcode: ref pattern4_0,
4933             } => {
4934                 if let &Opcode::Null = pattern4_0 {
4935                     // Rule at src/isa/aarch64/lower.isle line 22.
4936                     let expr0_0: u64 = 0;
4937                     let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
4938                     let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
4939                     return Some(expr2_0);
4940                 }
4941             }
4942             &InstructionData::UnaryImm {
4943                 opcode: ref pattern4_0,
4944                 imm: pattern4_1,
4945             } => {
4946                 if let &Opcode::Iconst = pattern4_0 {
4947                     let pattern6_0 = C::u64_from_imm64(ctx, pattern4_1);
4948                     // Rule at src/isa/aarch64/lower.isle line 9.
4949                     let expr0_0 = constructor_imm(ctx, pattern2_0, pattern6_0)?;
4950                     let expr1_0 = constructor_output_reg(ctx, expr0_0)?;
4951                     return Some(expr1_0);
4952                 }
4953             }
4954             &InstructionData::UnaryBool {
4955                 opcode: ref pattern4_0,
4956                 imm: pattern4_1,
4957             } => {
4958                 if let &Opcode::Bconst = pattern4_0 {
4959                     if pattern4_1 == true {
4960                         // Rule at src/isa/aarch64/lower.isle line 17.
4961                         let expr0_0: u64 = 1;
4962                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
4963                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
4964                         return Some(expr2_0);
4965                     }
4966                     if pattern4_1 == false {
4967                         // Rule at src/isa/aarch64/lower.isle line 14.
4968                         let expr0_0: u64 = 0;
4969                         let expr1_0 = constructor_imm(ctx, pattern2_0, expr0_0)?;
4970                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
4971                         return Some(expr2_0);
4972                     }
4973                 }
4974             }
4975             &InstructionData::Unary {
4976                 opcode: ref pattern4_0,
4977                 arg: pattern4_1,
4978             } => {
4979                 match pattern4_0 {
4980                     &Opcode::Bitrev => {
4981                         // Rule at src/isa/aarch64/lower.isle line 989.
4982                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
4983                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
4984                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
4985                         return Some(expr2_0);
4986                     }
4987                     &Opcode::Clz => {
4988                         // Rule at src/isa/aarch64/lower.isle line 1004.
4989                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
4990                         let expr1_0 = constructor_a64_clz(ctx, pattern2_0, expr0_0)?;
4991                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
4992                         return Some(expr2_0);
4993                     }
4994                     &Opcode::Cls => {
4995                         // Rule at src/isa/aarch64/lower.isle line 1071.
4996                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
4997                         let expr1_0 = constructor_a64_cls(ctx, pattern2_0, expr0_0)?;
4998                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
4999                         return Some(expr2_0);
5000                     }
5001                     &Opcode::Ctz => {
5002                         // Rule at src/isa/aarch64/lower.isle line 1037.
5003                         let expr0_0 = C::put_in_reg(ctx, pattern4_1);
5004                         let expr1_0 = constructor_rbit(ctx, pattern2_0, expr0_0)?;
5005                         let expr2_0 = constructor_a64_clz(ctx, pattern2_0, expr1_0)?;
5006                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5007                         return Some(expr3_0);
5008                     }
5009                     _ => {}
5010                 }
5011             }
5012             _ => {}
5013         }
5014         if let Some((pattern3_0, pattern3_1)) = C::multi_lane(ctx, pattern2_0) {
5015             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5016             if let &InstructionData::Binary {
5017                 opcode: ref pattern5_0,
5018                 args: ref pattern5_1,
5019             } = &pattern4_0
5020             {
5021                 match pattern5_0 {
5022                     &Opcode::Iadd => {
5023                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5024                         // Rule at src/isa/aarch64/lower.isle line 75.
5025                         let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5026                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5027                         let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5028                         let expr3_0 = constructor_add_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5029                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5030                         return Some(expr4_0);
5031                     }
5032                     &Opcode::Isub => {
5033                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5034                         // Rule at src/isa/aarch64/lower.isle line 125.
5035                         let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5036                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5037                         let expr2_0 = constructor_vector_size(ctx, pattern2_0)?;
5038                         let expr3_0 = constructor_sub_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5039                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5040                         return Some(expr4_0);
5041                     }
5042                     _ => {}
5043                 }
5044             }
5045         }
5046         if let Some(pattern3_0) = C::fits_in_16(ctx, pattern2_0) {
5047             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5048             if let &InstructionData::Binary {
5049                 opcode: ref pattern5_0,
5050                 args: ref pattern5_1,
5051             } = &pattern4_0
5052             {
5053                 match pattern5_0 {
5054                     &Opcode::Rotl => {
5055                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5056                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5057                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5058                             if let &InstructionData::UnaryImm {
5059                                 opcode: ref pattern10_0,
5060                                 imm: pattern10_1,
5061                             } = &pattern9_0
5062                             {
5063                                 if let &Opcode::Iconst = pattern10_0 {
5064                                     let closure12 = || {
5065                                         return Some(pattern3_0);
5066                                     };
5067                                     if let Some(pattern12_0) = closure12() {
5068                                         if let Some(pattern13_0) =
5069                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5070                                         {
5071                                             // Rule at src/isa/aarch64/lower.isle line 843.
5072                                             let expr0_0 =
5073                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5074                                             let expr1_0 =
5075                                                 C::negate_imm_shift(ctx, pattern3_0, pattern13_0);
5076                                             let expr2_0 = constructor_small_rotr_imm(
5077                                                 ctx, pattern3_0, expr0_0, expr1_0,
5078                                             )?;
5079                                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5080                                             return Some(expr3_0);
5081                                         }
5082                                     }
5083                                 }
5084                             }
5085                         }
5086                         // Rule at src/isa/aarch64/lower.isle line 838.
5087                         let expr0_0: Type = I32;
5088                         let expr1_0 = C::zero_reg(ctx);
5089                         let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5090                         let expr3_0 = constructor_sub(ctx, expr0_0, expr1_0, expr2_0)?;
5091                         let expr4_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5092                         let expr5_0 = constructor_small_rotr(ctx, pattern3_0, expr4_0, expr3_0)?;
5093                         let expr6_0 = constructor_output_reg(ctx, expr5_0)?;
5094                         return Some(expr6_0);
5095                     }
5096                     &Opcode::Rotr => {
5097                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5098                         if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5099                             let pattern9_0 = C::inst_data(ctx, pattern8_0);
5100                             if let &InstructionData::UnaryImm {
5101                                 opcode: ref pattern10_0,
5102                                 imm: pattern10_1,
5103                             } = &pattern9_0
5104                             {
5105                                 if let &Opcode::Iconst = pattern10_0 {
5106                                     let closure12 = || {
5107                                         return Some(pattern3_0);
5108                                     };
5109                                     if let Some(pattern12_0) = closure12() {
5110                                         if let Some(pattern13_0) =
5111                                             C::imm_shift_from_imm64(ctx, pattern10_1, pattern12_0)
5112                                         {
5113                                             // Rule at src/isa/aarch64/lower.isle line 903.
5114                                             let expr0_0 =
5115                                                 constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5116                                             let expr1_0 = constructor_small_rotr_imm(
5117                                                 ctx,
5118                                                 pattern3_0,
5119                                                 expr0_0,
5120                                                 pattern13_0,
5121                                             )?;
5122                                             let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5123                                             return Some(expr2_0);
5124                                         }
5125                                     }
5126                                 }
5127                             }
5128                         }
5129                         // Rule at src/isa/aarch64/lower.isle line 891.
5130                         let expr0_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5131                         let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5132                         let expr2_0 = constructor_small_rotr(ctx, pattern3_0, expr0_0, expr1_0)?;
5133                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5134                         return Some(expr3_0);
5135                     }
5136                     _ => {}
5137                 }
5138             }
5139         }
5140         if let Some(pattern3_0) = C::fits_in_32(ctx, pattern2_0) {
5141             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5142             if let &InstructionData::Binary {
5143                 opcode: ref pattern5_0,
5144                 args: ref pattern5_1,
5145             } = &pattern4_0
5146             {
5147                 match pattern5_0 {
5148                     &Opcode::Umulhi => {
5149                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5150                         // Rule at src/isa/aarch64/lower.isle line 370.
5151                         let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5152                         let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_1)?;
5153                         let expr2_0 = C::zero_reg(ctx);
5154                         let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
5155                         let expr4_0: Type = I64;
5156                         let expr5_0 = C::ty_bits(ctx, pattern3_0);
5157                         let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
5158                         let expr7_0 = constructor_lsr_imm(ctx, expr4_0, expr3_0, expr6_0)?;
5159                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
5160                         return Some(expr8_0);
5161                     }
5162                     &Opcode::Smulhi => {
5163                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5164                         // Rule at src/isa/aarch64/lower.isle line 358.
5165                         let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5166                         let expr1_0 = constructor_put_in_reg_sext64(ctx, pattern7_1)?;
5167                         let expr2_0 = C::zero_reg(ctx);
5168                         let expr3_0 = constructor_madd64(ctx, expr0_0, expr1_0, expr2_0)?;
5169                         let expr4_0: Type = I64;
5170                         let expr5_0 = C::ty_bits(ctx, pattern3_0);
5171                         let expr6_0 = C::imm_shift_from_u8(ctx, expr5_0);
5172                         let expr7_0 = constructor_asr_imm(ctx, expr4_0, expr3_0, expr6_0)?;
5173                         let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
5174                         return Some(expr8_0);
5175                     }
5176                     &Opcode::Band => {
5177                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5178                         // Rule at src/isa/aarch64/lower.isle line 583.
5179                         let expr0_0 = ALUOp::And;
5180                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5181                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5182                         )?;
5183                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5184                         return Some(expr2_0);
5185                     }
5186                     &Opcode::Bor => {
5187                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5188                         // Rule at src/isa/aarch64/lower.isle line 596.
5189                         let expr0_0 = ALUOp::Orr;
5190                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5191                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5192                         )?;
5193                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5194                         return Some(expr2_0);
5195                     }
5196                     &Opcode::Bxor => {
5197                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5198                         // Rule at src/isa/aarch64/lower.isle line 609.
5199                         let expr0_0 = ALUOp::Eor;
5200                         let expr1_0 = constructor_alu_rs_imm_logic_commutative(
5201                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5202                         )?;
5203                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5204                         return Some(expr2_0);
5205                     }
5206                     &Opcode::BandNot => {
5207                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5208                         // Rule at src/isa/aarch64/lower.isle line 622.
5209                         let expr0_0 = ALUOp::AndNot;
5210                         let expr1_0 = constructor_alu_rs_imm_logic(
5211                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5212                         )?;
5213                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5214                         return Some(expr2_0);
5215                     }
5216                     &Opcode::BorNot => {
5217                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5218                         // Rule at src/isa/aarch64/lower.isle line 635.
5219                         let expr0_0 = ALUOp::OrrNot;
5220                         let expr1_0 = constructor_alu_rs_imm_logic(
5221                             ctx, &expr0_0, pattern3_0, pattern7_0, pattern7_1,
5222                         )?;
5223                         let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5224                         return Some(expr2_0);
5225                     }
5226                     &Opcode::BxorNot => {
5227                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5228                         // Rule at src/isa/aarch64/lower.isle line 645.
5229                         let expr0_0 = ALUOp::EorNot;
5230                         let expr1_0: Type = I32;
5231                         let expr2_0 = constructor_alu_rs_imm_logic(
5232                             ctx, &expr0_0, expr1_0, pattern7_0, pattern7_1,
5233                         )?;
5234                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5235                         return Some(expr3_0);
5236                     }
5237                     &Opcode::Ishl => {
5238                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5239                         // Rule at src/isa/aarch64/lower.isle line 656.
5240                         let expr0_0 = ALUOp::Lsl;
5241                         let expr1_0 = C::put_in_reg(ctx, pattern7_0);
5242                         let expr2_0 =
5243                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5244                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5245                         return Some(expr3_0);
5246                     }
5247                     &Opcode::Ushr => {
5248                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5249                         // Rule at src/isa/aarch64/lower.isle line 740.
5250                         let expr0_0 = ALUOp::Lsr;
5251                         let expr1_0 = constructor_put_in_reg_zext32(ctx, pattern7_0)?;
5252                         let expr2_0 =
5253                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5254                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5255                         return Some(expr3_0);
5256                     }
5257                     &Opcode::Sshr => {
5258                         let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5259                         // Rule at src/isa/aarch64/lower.isle line 787.
5260                         let expr0_0 = ALUOp::Asr;
5261                         let expr1_0 = constructor_put_in_reg_sext32(ctx, pattern7_0)?;
5262                         let expr2_0 =
5263                             constructor_do_shift(ctx, &expr0_0, pattern3_0, expr1_0, pattern7_1)?;
5264                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5265                         return Some(expr3_0);
5266                     }
5267                     _ => {}
5268                 }
5269             }
5270         }
5271         if let Some(pattern3_0) = C::fits_in_64(ctx, pattern2_0) {
5272             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5273             match &pattern4_0 {
5274                 &InstructionData::Binary {
5275                     opcode: ref pattern5_0,
5276                     args: ref pattern5_1,
5277                 } => {
5278                     match pattern5_0 {
5279                         &Opcode::Iadd => {
5280                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5281                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) {
5282                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5283                                 match &pattern9_0 {
5284                                     &InstructionData::UnaryImm {
5285                                         opcode: ref pattern10_0,
5286                                         imm: pattern10_1,
5287                                     } => {
5288                                         if let &Opcode::Iconst = pattern10_0 {
5289                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5290                                             if let Some(pattern13_0) =
5291                                                 C::imm12_from_u64(ctx, pattern12_0)
5292                                             {
5293                                                 // Rule at src/isa/aarch64/lower.isle line 37.
5294                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5295                                                 let expr1_0 = constructor_add_imm(
5296                                                     ctx,
5297                                                     pattern3_0,
5298                                                     expr0_0,
5299                                                     pattern13_0,
5300                                                 )?;
5301                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5302                                                 return Some(expr2_0);
5303                                             }
5304                                             if let Some(pattern13_0) =
5305                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5306                                             {
5307                                                 // Rule at src/isa/aarch64/lower.isle line 45.
5308                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5309                                                 let expr1_0 = constructor_sub_imm(
5310                                                     ctx,
5311                                                     pattern3_0,
5312                                                     expr0_0,
5313                                                     pattern13_0,
5314                                                 )?;
5315                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5316                                                 return Some(expr2_0);
5317                                             }
5318                                         }
5319                                     }
5320                                     &InstructionData::Binary {
5321                                         opcode: ref pattern10_0,
5322                                         args: ref pattern10_1,
5323                                     } => {
5324                                         match pattern10_0 {
5325                                             &Opcode::Imul => {
5326                                                 let (pattern12_0, pattern12_1) =
5327                                                     C::unpack_value_array_2(ctx, pattern10_1);
5328                                                 // Rule at src/isa/aarch64/lower.isle line 70.
5329                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5330                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5331                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_1);
5332                                                 let expr3_0 = constructor_madd(
5333                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5334                                                 )?;
5335                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5336                                                 return Some(expr4_0);
5337                                             }
5338                                             &Opcode::Ishl => {
5339                                                 let (pattern12_0, pattern12_1) =
5340                                                     C::unpack_value_array_2(ctx, pattern10_1);
5341                                                 if let Some(pattern13_0) =
5342                                                     C::def_inst(ctx, pattern12_1)
5343                                                 {
5344                                                     let pattern14_0 =
5345                                                         C::inst_data(ctx, pattern13_0);
5346                                                     if let &InstructionData::UnaryImm {
5347                                                         opcode: ref pattern15_0,
5348                                                         imm: pattern15_1,
5349                                                     } = &pattern14_0
5350                                                     {
5351                                                         if let &Opcode::Iconst = pattern15_0 {
5352                                                             let closure17 = || {
5353                                                                 return Some(pattern3_0);
5354                                                             };
5355                                                             if let Some(pattern17_0) = closure17() {
5356                                                                 if let Some(pattern18_0) =
5357                                                                     C::lshl_from_imm64(
5358                                                                         ctx,
5359                                                                         pattern15_1,
5360                                                                         pattern17_0,
5361                                                                     )
5362                                                                 {
5363                                                                     // Rule at src/isa/aarch64/lower.isle line 62.
5364                                                                     let expr0_0 = C::put_in_reg(
5365                                                                         ctx, pattern7_1,
5366                                                                     );
5367                                                                     let expr1_0 = C::put_in_reg(
5368                                                                         ctx,
5369                                                                         pattern12_0,
5370                                                                     );
5371                                                                     let expr2_0 =
5372                                                                         constructor_add_shift(
5373                                                                             ctx,
5374                                                                             pattern3_0,
5375                                                                             expr0_0,
5376                                                                             expr1_0,
5377                                                                             pattern18_0,
5378                                                                         )?;
5379                                                                     let expr3_0 =
5380                                                                         constructor_output_reg(
5381                                                                             ctx, expr2_0,
5382                                                                         )?;
5383                                                                     return Some(expr3_0);
5384                                                                 }
5385                                                             }
5386                                                         }
5387                                                     }
5388                                                 }
5389                                             }
5390                                             _ => {}
5391                                         }
5392                                     }
5393                                     _ => {}
5394                                 }
5395                             }
5396                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0)
5397                             {
5398                                 // Rule at src/isa/aarch64/lower.isle line 53.
5399                                 let expr0_0 = C::put_in_reg(ctx, pattern7_1);
5400                                 let expr1_0 =
5401                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5402                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5403                                 return Some(expr2_0);
5404                             }
5405                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5406                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5407                                 match &pattern9_0 {
5408                                     &InstructionData::UnaryImm {
5409                                         opcode: ref pattern10_0,
5410                                         imm: pattern10_1,
5411                                     } => {
5412                                         if let &Opcode::Iconst = pattern10_0 {
5413                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5414                                             if let Some(pattern13_0) =
5415                                                 C::imm12_from_u64(ctx, pattern12_0)
5416                                             {
5417                                                 // Rule at src/isa/aarch64/lower.isle line 34.
5418                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5419                                                 let expr1_0 = constructor_add_imm(
5420                                                     ctx,
5421                                                     pattern3_0,
5422                                                     expr0_0,
5423                                                     pattern13_0,
5424                                                 )?;
5425                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5426                                                 return Some(expr2_0);
5427                                             }
5428                                             if let Some(pattern13_0) =
5429                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5430                                             {
5431                                                 // Rule at src/isa/aarch64/lower.isle line 42.
5432                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5433                                                 let expr1_0 = constructor_sub_imm(
5434                                                     ctx,
5435                                                     pattern3_0,
5436                                                     expr0_0,
5437                                                     pattern13_0,
5438                                                 )?;
5439                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5440                                                 return Some(expr2_0);
5441                                             }
5442                                         }
5443                                     }
5444                                     &InstructionData::Binary {
5445                                         opcode: ref pattern10_0,
5446                                         args: ref pattern10_1,
5447                                     } => {
5448                                         match pattern10_0 {
5449                                             &Opcode::Imul => {
5450                                                 let (pattern12_0, pattern12_1) =
5451                                                     C::unpack_value_array_2(ctx, pattern10_1);
5452                                                 // Rule at src/isa/aarch64/lower.isle line 67.
5453                                                 let expr0_0 = C::put_in_reg(ctx, pattern12_0);
5454                                                 let expr1_0 = C::put_in_reg(ctx, pattern12_1);
5455                                                 let expr2_0 = C::put_in_reg(ctx, pattern7_0);
5456                                                 let expr3_0 = constructor_madd(
5457                                                     ctx, pattern3_0, expr0_0, expr1_0, expr2_0,
5458                                                 )?;
5459                                                 let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5460                                                 return Some(expr4_0);
5461                                             }
5462                                             &Opcode::Ishl => {
5463                                                 let (pattern12_0, pattern12_1) =
5464                                                     C::unpack_value_array_2(ctx, pattern10_1);
5465                                                 if let Some(pattern13_0) =
5466                                                     C::def_inst(ctx, pattern12_1)
5467                                                 {
5468                                                     let pattern14_0 =
5469                                                         C::inst_data(ctx, pattern13_0);
5470                                                     if let &InstructionData::UnaryImm {
5471                                                         opcode: ref pattern15_0,
5472                                                         imm: pattern15_1,
5473                                                     } = &pattern14_0
5474                                                     {
5475                                                         if let &Opcode::Iconst = pattern15_0 {
5476                                                             let closure17 = || {
5477                                                                 return Some(pattern3_0);
5478                                                             };
5479                                                             if let Some(pattern17_0) = closure17() {
5480                                                                 if let Some(pattern18_0) =
5481                                                                     C::lshl_from_imm64(
5482                                                                         ctx,
5483                                                                         pattern15_1,
5484                                                                         pattern17_0,
5485                                                                     )
5486                                                                 {
5487                                                                     // Rule at src/isa/aarch64/lower.isle line 58.
5488                                                                     let expr0_0 = C::put_in_reg(
5489                                                                         ctx, pattern7_0,
5490                                                                     );
5491                                                                     let expr1_0 = C::put_in_reg(
5492                                                                         ctx,
5493                                                                         pattern12_0,
5494                                                                     );
5495                                                                     let expr2_0 =
5496                                                                         constructor_add_shift(
5497                                                                             ctx,
5498                                                                             pattern3_0,
5499                                                                             expr0_0,
5500                                                                             expr1_0,
5501                                                                             pattern18_0,
5502                                                                         )?;
5503                                                                     let expr3_0 =
5504                                                                         constructor_output_reg(
5505                                                                             ctx, expr2_0,
5506                                                                         )?;
5507                                                                     return Some(expr3_0);
5508                                                                 }
5509                                                             }
5510                                                         }
5511                                                     }
5512                                                 }
5513                                             }
5514                                             _ => {}
5515                                         }
5516                                     }
5517                                     _ => {}
5518                                 }
5519                             }
5520                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
5521                             {
5522                                 // Rule at src/isa/aarch64/lower.isle line 50.
5523                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5524                                 let expr1_0 =
5525                                     constructor_add_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5526                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5527                                 return Some(expr2_0);
5528                             }
5529                             // Rule at src/isa/aarch64/lower.isle line 30.
5530                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5531                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5532                             let expr2_0 = constructor_add(ctx, pattern3_0, expr0_0, expr1_0)?;
5533                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5534                             return Some(expr3_0);
5535                         }
5536                         &Opcode::Isub => {
5537                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5538                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5539                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5540                                 match &pattern9_0 {
5541                                     &InstructionData::UnaryImm {
5542                                         opcode: ref pattern10_0,
5543                                         imm: pattern10_1,
5544                                     } => {
5545                                         if let &Opcode::Iconst = pattern10_0 {
5546                                             let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1);
5547                                             if let Some(pattern13_0) =
5548                                                 C::imm12_from_u64(ctx, pattern12_0)
5549                                             {
5550                                                 // Rule at src/isa/aarch64/lower.isle line 105.
5551                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5552                                                 let expr1_0 = constructor_sub_imm(
5553                                                     ctx,
5554                                                     pattern3_0,
5555                                                     expr0_0,
5556                                                     pattern13_0,
5557                                                 )?;
5558                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5559                                                 return Some(expr2_0);
5560                                             }
5561                                             if let Some(pattern13_0) =
5562                                                 C::imm12_from_negated_u64(ctx, pattern12_0)
5563                                             {
5564                                                 // Rule at src/isa/aarch64/lower.isle line 110.
5565                                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5566                                                 let expr1_0 = constructor_add_imm(
5567                                                     ctx,
5568                                                     pattern3_0,
5569                                                     expr0_0,
5570                                                     pattern13_0,
5571                                                 )?;
5572                                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5573                                                 return Some(expr2_0);
5574                                             }
5575                                         }
5576                                     }
5577                                     &InstructionData::Binary {
5578                                         opcode: ref pattern10_0,
5579                                         args: ref pattern10_1,
5580                                     } => {
5581                                         if let &Opcode::Ishl = pattern10_0 {
5582                                             let (pattern12_0, pattern12_1) =
5583                                                 C::unpack_value_array_2(ctx, pattern10_1);
5584                                             if let Some(pattern13_0) = C::def_inst(ctx, pattern12_1)
5585                                             {
5586                                                 let pattern14_0 = C::inst_data(ctx, pattern13_0);
5587                                                 if let &InstructionData::UnaryImm {
5588                                                     opcode: ref pattern15_0,
5589                                                     imm: pattern15_1,
5590                                                 } = &pattern14_0
5591                                                 {
5592                                                     if let &Opcode::Iconst = pattern15_0 {
5593                                                         let closure17 = || {
5594                                                             return Some(pattern3_0);
5595                                                         };
5596                                                         if let Some(pattern17_0) = closure17() {
5597                                                             if let Some(pattern18_0) =
5598                                                                 C::lshl_from_imm64(
5599                                                                     ctx,
5600                                                                     pattern15_1,
5601                                                                     pattern17_0,
5602                                                                 )
5603                                                             {
5604                                                                 // Rule at src/isa/aarch64/lower.isle line 120.
5605                                                                 let expr0_0 =
5606                                                                     C::put_in_reg(ctx, pattern7_0);
5607                                                                 let expr1_0 =
5608                                                                     C::put_in_reg(ctx, pattern12_0);
5609                                                                 let expr2_0 =
5610                                                                     constructor_sub_shift(
5611                                                                         ctx,
5612                                                                         pattern3_0,
5613                                                                         expr0_0,
5614                                                                         expr1_0,
5615                                                                         pattern18_0,
5616                                                                     )?;
5617                                                                 let expr3_0 =
5618                                                                     constructor_output_reg(
5619                                                                         ctx, expr2_0,
5620                                                                     )?;
5621                                                                 return Some(expr3_0);
5622                                                             }
5623                                                         }
5624                                                     }
5625                                                 }
5626                                             }
5627                                         }
5628                                     }
5629                                     _ => {}
5630                                 }
5631                             }
5632                             if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1)
5633                             {
5634                                 // Rule at src/isa/aarch64/lower.isle line 115.
5635                                 let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5636                                 let expr1_0 =
5637                                     constructor_sub_extend(ctx, pattern3_0, expr0_0, &pattern8_0)?;
5638                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5639                                 return Some(expr2_0);
5640                             }
5641                             // Rule at src/isa/aarch64/lower.isle line 101.
5642                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5643                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5644                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
5645                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5646                             return Some(expr3_0);
5647                         }
5648                         &Opcode::Imul => {
5649                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5650                             // Rule at src/isa/aarch64/lower.isle line 179.
5651                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5652                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5653                             let expr2_0 = C::zero_reg(ctx);
5654                             let expr3_0 =
5655                                 constructor_madd(ctx, pattern3_0, expr0_0, expr1_0, expr2_0)?;
5656                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5657                             return Some(expr4_0);
5658                         }
5659                         &Opcode::Udiv => {
5660                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5661                             // Rule at src/isa/aarch64/lower.isle line 384.
5662                             let expr0_0: Type = I64;
5663                             let expr1_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5664                             let expr2_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
5665                             let expr3_0 = constructor_a64_udiv(ctx, expr0_0, expr1_0, expr2_0)?;
5666                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5667                             return Some(expr4_0);
5668                         }
5669                         &Opcode::Sdiv => {
5670                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5671                             if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) {
5672                                 let pattern9_0 = C::inst_data(ctx, pattern8_0);
5673                                 if let &InstructionData::UnaryImm {
5674                                     opcode: ref pattern10_0,
5675                                     imm: pattern10_1,
5676                                 } = &pattern9_0
5677                                 {
5678                                     if let &Opcode::Iconst = pattern10_0 {
5679                                         if let Some(pattern12_0) =
5680                                             C::safe_divisor_from_imm64(ctx, pattern10_1)
5681                                         {
5682                                             // Rule at src/isa/aarch64/lower.isle line 430.
5683                                             let expr0_0: Type = I64;
5684                                             let expr1_0 =
5685                                                 constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5686                                             let expr2_0 =
5687                                                 constructor_imm(ctx, pattern3_0, pattern12_0)?;
5688                                             let expr3_0 = constructor_a64_sdiv(
5689                                                 ctx, expr0_0, expr1_0, expr2_0,
5690                                             )?;
5691                                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5692                                             return Some(expr4_0);
5693                                         }
5694                                     }
5695                                 }
5696                             }
5697                             // Rule at src/isa/aarch64/lower.isle line 417.
5698                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5699                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
5700                             let expr2_0 = constructor_trap_if_div_overflow(
5701                                 ctx, pattern3_0, expr0_0, expr1_0,
5702                             )?;
5703                             let expr3_0: Type = I64;
5704                             let expr4_0 = constructor_a64_sdiv(ctx, expr3_0, expr2_0, expr1_0)?;
5705                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5706                             return Some(expr5_0);
5707                         }
5708                         &Opcode::Urem => {
5709                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5710                             // Rule at src/isa/aarch64/lower.isle line 458.
5711                             let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern7_0)?;
5712                             let expr1_0 = constructor_put_nonzero_in_reg_zext64(ctx, pattern7_1)?;
5713                             let expr2_0: Type = I64;
5714                             let expr3_0 = constructor_a64_udiv(ctx, expr2_0, expr0_0, expr1_0)?;
5715                             let expr4_0 = constructor_msub64(ctx, expr3_0, expr1_0, expr0_0)?;
5716                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5717                             return Some(expr5_0);
5718                         }
5719                         &Opcode::Srem => {
5720                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5721                             // Rule at src/isa/aarch64/lower.isle line 465.
5722                             let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern7_0)?;
5723                             let expr1_0 = constructor_put_nonzero_in_reg_sext64(ctx, pattern7_1)?;
5724                             let expr2_0: Type = I64;
5725                             let expr3_0 = constructor_a64_sdiv(ctx, expr2_0, expr0_0, expr1_0)?;
5726                             let expr4_0 = constructor_msub64(ctx, expr3_0, expr1_0, expr0_0)?;
5727                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5728                             return Some(expr5_0);
5729                         }
5730                         _ => {}
5731                     }
5732                 }
5733                 &InstructionData::Unary {
5734                     opcode: ref pattern5_0,
5735                     arg: pattern5_1,
5736                 } => {
5737                     match pattern5_0 {
5738                         &Opcode::Ineg => {
5739                             // Rule at src/isa/aarch64/lower.isle line 169.
5740                             let expr0_0 = C::zero_reg(ctx);
5741                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
5742                             let expr2_0 = constructor_sub(ctx, pattern3_0, expr0_0, expr1_0)?;
5743                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5744                             return Some(expr3_0);
5745                         }
5746                         &Opcode::Bnot => {
5747                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
5748                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
5749                                 if let &InstructionData::Binary {
5750                                     opcode: ref pattern9_0,
5751                                     args: ref pattern9_1,
5752                                 } = &pattern8_0
5753                                 {
5754                                     if let &Opcode::Ishl = pattern9_0 {
5755                                         let (pattern11_0, pattern11_1) =
5756                                             C::unpack_value_array_2(ctx, pattern9_1);
5757                                         if let Some(pattern12_0) = C::def_inst(ctx, pattern11_1) {
5758                                             let pattern13_0 = C::inst_data(ctx, pattern12_0);
5759                                             if let &InstructionData::UnaryImm {
5760                                                 opcode: ref pattern14_0,
5761                                                 imm: pattern14_1,
5762                                             } = &pattern13_0
5763                                             {
5764                                                 if let &Opcode::Iconst = pattern14_0 {
5765                                                     let closure16 = || {
5766                                                         return Some(pattern3_0);
5767                                                     };
5768                                                     if let Some(pattern16_0) = closure16() {
5769                                                         if let Some(pattern17_0) =
5770                                                             C::lshl_from_imm64(
5771                                                                 ctx,
5772                                                                 pattern14_1,
5773                                                                 pattern16_0,
5774                                                             )
5775                                                         {
5776                                                             // Rule at src/isa/aarch64/lower.isle line 564.
5777                                                             let expr0_0 = C::zero_reg(ctx);
5778                                                             let expr1_0 =
5779                                                                 C::put_in_reg(ctx, pattern11_0);
5780                                                             let expr2_0 =
5781                                                                 constructor_orr_not_shift(
5782                                                                     ctx,
5783                                                                     pattern3_0,
5784                                                                     expr0_0,
5785                                                                     expr1_0,
5786                                                                     pattern17_0,
5787                                                                 )?;
5788                                                             let expr3_0 = constructor_output_reg(
5789                                                                 ctx, expr2_0,
5790                                                             )?;
5791                                                             return Some(expr3_0);
5792                                                         }
5793                                                     }
5794                                                 }
5795                                             }
5796                                         }
5797                                     }
5798                                 }
5799                             }
5800                             // Rule at src/isa/aarch64/lower.isle line 559.
5801                             let expr0_0 = C::zero_reg(ctx);
5802                             let expr1_0 = C::put_in_reg(ctx, pattern5_1);
5803                             let expr2_0 = constructor_orr_not(ctx, pattern3_0, expr0_0, expr1_0)?;
5804                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5805                             return Some(expr3_0);
5806                         }
5807                         &Opcode::Uextend => {
5808                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
5809                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
5810                                 if let &InstructionData::BinaryImm8 {
5811                                     opcode: ref pattern9_0,
5812                                     arg: pattern9_1,
5813                                     imm: pattern9_2,
5814                                 } = &pattern8_0
5815                                 {
5816                                     if let &Opcode::Extractlane = pattern9_0 {
5817                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
5818                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
5819                                         // Rule at src/isa/aarch64/lower.isle line 481.
5820                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
5821                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
5822                                         let expr2_0 = constructor_mov_from_vec(
5823                                             ctx,
5824                                             expr0_0,
5825                                             pattern12_0,
5826                                             &expr1_0,
5827                                         )?;
5828                                         let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
5829                                         return Some(expr3_0);
5830                                     }
5831                                 }
5832                             }
5833                             let pattern7_0 = C::value_type(ctx, pattern5_1);
5834                             if let Some(pattern8_0) = C::sinkable_atomic_load(ctx, pattern5_1) {
5835                                 // Rule at src/isa/aarch64/lower.isle line 488.
5836                                 let expr0_0 = C::sink_atomic_load(ctx, &pattern8_0);
5837                                 let expr1_0 = constructor_load_acquire(ctx, pattern7_0, expr0_0)?;
5838                                 let expr2_0 = constructor_output_reg(ctx, expr1_0)?;
5839                                 return Some(expr2_0);
5840                             }
5841                             // Rule at src/isa/aarch64/lower.isle line 476.
5842                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
5843                             let expr1_0: bool = false;
5844                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
5845                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
5846                             let expr4_0 =
5847                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
5848                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5849                             return Some(expr5_0);
5850                         }
5851                         &Opcode::Sextend => {
5852                             if let Some(pattern7_0) = C::def_inst(ctx, pattern5_1) {
5853                                 let pattern8_0 = C::inst_data(ctx, pattern7_0);
5854                                 if let &InstructionData::BinaryImm8 {
5855                                     opcode: ref pattern9_0,
5856                                     arg: pattern9_1,
5857                                     imm: pattern9_2,
5858                                 } = &pattern8_0
5859                                 {
5860                                     if let &Opcode::Extractlane = pattern9_0 {
5861                                         let pattern11_0 = C::value_type(ctx, pattern9_1);
5862                                         let pattern12_0 = C::u8_from_uimm8(ctx, pattern9_2);
5863                                         // Rule at src/isa/aarch64/lower.isle line 513.
5864                                         let expr0_0 = C::put_in_reg(ctx, pattern9_1);
5865                                         let expr1_0 = constructor_vector_size(ctx, pattern11_0)?;
5866                                         let expr2_0 = constructor_size_from_ty(ctx, pattern3_0)?;
5867                                         let expr3_0 = constructor_mov_from_vec_signed(
5868                                             ctx,
5869                                             expr0_0,
5870                                             pattern12_0,
5871                                             &expr1_0,
5872                                             &expr2_0,
5873                                         )?;
5874                                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5875                                         return Some(expr4_0);
5876                                     }
5877                                 }
5878                             }
5879                             let pattern7_0 = C::value_type(ctx, pattern5_1);
5880                             // Rule at src/isa/aarch64/lower.isle line 508.
5881                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
5882                             let expr1_0: bool = true;
5883                             let expr2_0 = C::ty_bits(ctx, pattern7_0);
5884                             let expr3_0 = C::ty_bits(ctx, pattern3_0);
5885                             let expr4_0 =
5886                                 constructor_extend(ctx, expr0_0, expr1_0, expr2_0, expr3_0)?;
5887                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5888                             return Some(expr5_0);
5889                         }
5890                         _ => {}
5891                     }
5892                 }
5893                 _ => {}
5894             }
5895         }
5896         if let Some(pattern3_0) = C::vec128(ctx, pattern2_0) {
5897             let pattern4_0 = C::inst_data(ctx, pattern0_0);
5898             match &pattern4_0 {
5899                 &InstructionData::Binary {
5900                     opcode: ref pattern5_0,
5901                     args: ref pattern5_1,
5902                 } => {
5903                     match pattern5_0 {
5904                         &Opcode::UaddSat => {
5905                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5906                             // Rule at src/isa/aarch64/lower.isle line 148.
5907                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5908                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5909                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5910                             let expr3_0 = constructor_uqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
5911                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5912                             return Some(expr4_0);
5913                         }
5914                         &Opcode::SaddSat => {
5915                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5916                             // Rule at src/isa/aarch64/lower.isle line 153.
5917                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5918                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5919                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5920                             let expr3_0 = constructor_sqadd(ctx, expr0_0, expr1_0, &expr2_0)?;
5921                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5922                             return Some(expr4_0);
5923                         }
5924                         &Opcode::UsubSat => {
5925                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5926                             // Rule at src/isa/aarch64/lower.isle line 158.
5927                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5928                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5929                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5930                             let expr3_0 = constructor_uqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
5931                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5932                             return Some(expr4_0);
5933                         }
5934                         &Opcode::SsubSat => {
5935                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5936                             // Rule at src/isa/aarch64/lower.isle line 163.
5937                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5938                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5939                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5940                             let expr3_0 = constructor_sqsub(ctx, expr0_0, expr1_0, &expr2_0)?;
5941                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5942                             return Some(expr4_0);
5943                         }
5944                         &Opcode::Band => {
5945                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5946                             // Rule at src/isa/aarch64/lower.isle line 591.
5947                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5948                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5949                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5950                             let expr3_0 = constructor_and_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5951                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5952                             return Some(expr4_0);
5953                         }
5954                         &Opcode::Bor => {
5955                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5956                             // Rule at src/isa/aarch64/lower.isle line 604.
5957                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5958                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5959                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5960                             let expr3_0 = constructor_orr_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5961                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5962                             return Some(expr4_0);
5963                         }
5964                         &Opcode::Bxor => {
5965                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5966                             // Rule at src/isa/aarch64/lower.isle line 617.
5967                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5968                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5969                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5970                             let expr3_0 = constructor_eor_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5971                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5972                             return Some(expr4_0);
5973                         }
5974                         &Opcode::BandNot => {
5975                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5976                             // Rule at src/isa/aarch64/lower.isle line 630.
5977                             let expr0_0 = C::put_in_reg(ctx, pattern7_0);
5978                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5979                             let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
5980                             let expr3_0 = constructor_bic_vec(ctx, expr0_0, expr1_0, &expr2_0)?;
5981                             let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
5982                             return Some(expr4_0);
5983                         }
5984                         &Opcode::Ishl => {
5985                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5986                             // Rule at src/isa/aarch64/lower.isle line 694.
5987                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
5988                             let expr1_0 = C::put_in_reg(ctx, pattern7_1);
5989                             let expr2_0 = constructor_vec_dup(ctx, expr1_0, &expr0_0)?;
5990                             let expr3_0 = C::put_in_reg(ctx, pattern7_0);
5991                             let expr4_0 = constructor_sshl(ctx, expr3_0, expr2_0, &expr0_0)?;
5992                             let expr5_0 = constructor_output_reg(ctx, expr4_0)?;
5993                             return Some(expr5_0);
5994                         }
5995                         &Opcode::Ushr => {
5996                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
5997                             // Rule at src/isa/aarch64/lower.isle line 752.
5998                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
5999                             let expr1_0: Type = I32;
6000                             let expr2_0 = C::zero_reg(ctx);
6001                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6002                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6003                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6004                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6005                             let expr7_0 = constructor_ushl(ctx, expr6_0, expr5_0, &expr0_0)?;
6006                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6007                             return Some(expr8_0);
6008                         }
6009                         &Opcode::Sshr => {
6010                             let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, pattern5_1);
6011                             // Rule at src/isa/aarch64/lower.isle line 801.
6012                             let expr0_0 = constructor_vector_size(ctx, pattern3_0)?;
6013                             let expr1_0: Type = I32;
6014                             let expr2_0 = C::zero_reg(ctx);
6015                             let expr3_0 = C::put_in_reg(ctx, pattern7_1);
6016                             let expr4_0 = constructor_sub(ctx, expr1_0, expr2_0, expr3_0)?;
6017                             let expr5_0 = constructor_vec_dup(ctx, expr4_0, &expr0_0)?;
6018                             let expr6_0 = C::put_in_reg(ctx, pattern7_0);
6019                             let expr7_0 = constructor_sshl(ctx, expr6_0, expr5_0, &expr0_0)?;
6020                             let expr8_0 = constructor_output_reg(ctx, expr7_0)?;
6021                             return Some(expr8_0);
6022                         }
6023                         _ => {}
6024                     }
6025                 }
6026                 &InstructionData::Unary {
6027                     opcode: ref pattern5_0,
6028                     arg: pattern5_1,
6029                 } => {
6030                     match pattern5_0 {
6031                         &Opcode::Ineg => {
6032                             // Rule at src/isa/aarch64/lower.isle line 173.
6033                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6034                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6035                             let expr2_0 = constructor_neg(ctx, expr0_0, &expr1_0)?;
6036                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6037                             return Some(expr3_0);
6038                         }
6039                         &Opcode::Bnot => {
6040                             // Rule at src/isa/aarch64/lower.isle line 578.
6041                             let expr0_0 = C::put_in_reg(ctx, pattern5_1);
6042                             let expr1_0 = constructor_vector_size(ctx, pattern3_0)?;
6043                             let expr2_0 = constructor_not(ctx, expr0_0, &expr1_0)?;
6044                             let expr3_0 = constructor_output_reg(ctx, expr2_0)?;
6045                             return Some(expr3_0);
6046                         }
6047                         _ => {}
6048                     }
6049                 }
6050                 _ => {}
6051             }
6052             if let Some(()) = C::not_i64x2(ctx, pattern3_0) {
6053                 let pattern5_0 = C::inst_data(ctx, pattern0_0);
6054                 if let &InstructionData::Binary {
6055                     opcode: ref pattern6_0,
6056                     args: ref pattern6_1,
6057                 } = &pattern5_0
6058                 {
6059                     if let &Opcode::Imul = pattern6_0 {
6060                         let (pattern8_0, pattern8_1) = C::unpack_value_array_2(ctx, pattern6_1);
6061                         // Rule at src/isa/aarch64/lower.isle line 211.
6062                         let expr0_0 = C::put_in_reg(ctx, pattern8_0);
6063                         let expr1_0 = C::put_in_reg(ctx, pattern8_1);
6064                         let expr2_0 = constructor_vector_size(ctx, pattern3_0)?;
6065                         let expr3_0 = constructor_mul(ctx, expr0_0, expr1_0, &expr2_0)?;
6066                         let expr4_0 = constructor_output_reg(ctx, expr3_0)?;
6067                         return Some(expr4_0);
6068                     }
6069                 }
6070             }
6071         }
6072     }
6073     return None;
6074 }
6075 
6076 // Generated as internal constructor for term put_nonzero_in_reg_zext64.
6077 pub fn constructor_put_nonzero_in_reg_zext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6078     let pattern0_0 = arg0;
6079     let pattern1_0 = C::value_type(ctx, pattern0_0);
6080     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6081         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6082         if let &InstructionData::UnaryImm {
6083             opcode: ref pattern4_0,
6084             imm: pattern4_1,
6085         } = &pattern3_0
6086         {
6087             if let &Opcode::Iconst = pattern4_0 {
6088                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6089                     // Rule at src/isa/aarch64/lower.isle line 394.
6090                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6091                     return Some(expr0_0);
6092                 }
6093             }
6094         }
6095     }
6096     // Rule at src/isa/aarch64/lower.isle line 389.
6097     let expr0_0 = constructor_put_in_reg_zext64(ctx, pattern0_0)?;
6098     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6099     return Some(expr1_0);
6100 }
6101 
6102 // Generated as internal constructor for term put_nonzero_in_reg_sext64.
6103 pub fn constructor_put_nonzero_in_reg_sext64<C: Context>(ctx: &mut C, arg0: Value) -> Option<Reg> {
6104     let pattern0_0 = arg0;
6105     let pattern1_0 = C::value_type(ctx, pattern0_0);
6106     if let Some(pattern2_0) = C::def_inst(ctx, pattern0_0) {
6107         let pattern3_0 = C::inst_data(ctx, pattern2_0);
6108         if let &InstructionData::UnaryImm {
6109             opcode: ref pattern4_0,
6110             imm: pattern4_1,
6111         } = &pattern3_0
6112         {
6113             if let &Opcode::Iconst = pattern4_0 {
6114                 if let Some(pattern6_0) = C::nonzero_u64_from_imm64(ctx, pattern4_1) {
6115                     // Rule at src/isa/aarch64/lower.isle line 440.
6116                     let expr0_0 = constructor_imm(ctx, pattern1_0, pattern6_0)?;
6117                     return Some(expr0_0);
6118                 }
6119             }
6120         }
6121     }
6122     // Rule at src/isa/aarch64/lower.isle line 435.
6123     let expr0_0 = constructor_put_in_reg_sext64(ctx, pattern0_0)?;
6124     let expr1_0 = constructor_trap_if_zero_divisor(ctx, expr0_0)?;
6125     return Some(expr1_0);
6126 }
6127 
6128 // Generated as internal constructor for term lower_shl128.
6129 pub fn constructor_lower_shl128<C: Context>(
6130     ctx: &mut C,
6131     arg0: ValueRegs,
6132     arg1: Reg,
6133 ) -> Option<ValueRegs> {
6134     let pattern0_0 = arg0;
6135     let pattern1_0 = arg1;
6136     // Rule at src/isa/aarch64/lower.isle line 677.
6137     let expr0_0: usize = 0;
6138     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6139     let expr2_0: usize = 1;
6140     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6141     let expr4_0: Type = I64;
6142     let expr5_0 = constructor_lsl(ctx, expr4_0, expr1_0, pattern1_0)?;
6143     let expr6_0: Type = I64;
6144     let expr7_0 = constructor_lsl(ctx, expr6_0, expr3_0, pattern1_0)?;
6145     let expr8_0: Type = I32;
6146     let expr9_0 = C::zero_reg(ctx);
6147     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6148     let expr11_0: Type = I64;
6149     let expr12_0: Type = I64;
6150     let expr13_0: u8 = 1;
6151     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6152     let expr15_0 = constructor_lsr_imm(ctx, expr12_0, expr1_0, expr14_0)?;
6153     let expr16_0 = constructor_lsr(ctx, expr11_0, expr15_0, expr10_0)?;
6154     let expr17_0: Type = I64;
6155     let expr18_0 = constructor_orr(ctx, expr17_0, expr7_0, expr16_0)?;
6156     let expr19_0: Type = I64;
6157     let expr20_0: Type = I64;
6158     let expr21_0: u64 = 64;
6159     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6160     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6161     let expr24_0 = Cond::Ne;
6162     let expr25_0 = C::zero_reg(ctx);
6163     let expr26_0 = constructor_csel(ctx, &expr24_0, expr25_0, expr5_0)?;
6164     let expr27_0 = Cond::Ne;
6165     let expr28_0 = constructor_csel(ctx, &expr27_0, expr5_0, expr18_0)?;
6166     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr26_0, &expr28_0)?;
6167     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6168     return Some(expr30_0);
6169 }
6170 
6171 // Generated as internal constructor for term do_shift.
6172 pub fn constructor_do_shift<C: Context>(
6173     ctx: &mut C,
6174     arg0: &ALUOp,
6175     arg1: Type,
6176     arg2: Reg,
6177     arg3: Value,
6178 ) -> Option<Reg> {
6179     let pattern0_0 = arg0;
6180     let pattern1_0 = arg1;
6181     let pattern2_0 = arg2;
6182     let pattern3_0 = arg3;
6183     if let Some(pattern4_0) = C::def_inst(ctx, pattern3_0) {
6184         let pattern5_0 = C::inst_data(ctx, pattern4_0);
6185         if let &InstructionData::UnaryImm {
6186             opcode: ref pattern6_0,
6187             imm: pattern6_1,
6188         } = &pattern5_0
6189         {
6190             if let &Opcode::Iconst = pattern6_0 {
6191                 let closure8 = || {
6192                     return Some(pattern1_0);
6193                 };
6194                 if let Some(pattern8_0) = closure8() {
6195                     if let Some(pattern9_0) = C::imm_shift_from_imm64(ctx, pattern6_1, pattern8_0) {
6196                         // Rule at src/isa/aarch64/lower.isle line 734.
6197                         let expr0_0 = constructor_alu_rr_imm_shift(
6198                             ctx, pattern0_0, pattern1_0, pattern2_0, pattern9_0,
6199                         )?;
6200                         return Some(expr0_0);
6201                     }
6202                 }
6203             }
6204         }
6205     }
6206     let pattern0_0 = arg0;
6207     let pattern1_0 = arg1;
6208     if pattern1_0 == I32 {
6209         let pattern3_0 = arg2;
6210         let pattern4_0 = arg3;
6211         // Rule at src/isa/aarch64/lower.isle line 725.
6212         let expr0_0: Type = I32;
6213         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6214         let expr2_0: usize = 0;
6215         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6216         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6217         return Some(expr4_0);
6218     }
6219     if pattern1_0 == I64 {
6220         let pattern3_0 = arg2;
6221         let pattern4_0 = arg3;
6222         // Rule at src/isa/aarch64/lower.isle line 726.
6223         let expr0_0: Type = I64;
6224         let expr1_0 = C::put_in_regs(ctx, pattern4_0);
6225         let expr2_0: usize = 0;
6226         let expr3_0 = C::value_regs_get(ctx, expr1_0, expr2_0);
6227         let expr4_0 = constructor_alu_rrr(ctx, pattern0_0, expr0_0, pattern3_0, expr3_0)?;
6228         return Some(expr4_0);
6229     }
6230     if let Some(pattern2_0) = C::fits_in_16(ctx, pattern1_0) {
6231         let pattern3_0 = arg2;
6232         let pattern4_0 = arg3;
6233         // Rule at src/isa/aarch64/lower.isle line 716.
6234         let expr0_0 = C::put_in_regs(ctx, pattern4_0);
6235         let expr1_0: usize = 0;
6236         let expr2_0 = C::value_regs_get(ctx, expr0_0, expr1_0);
6237         let expr3_0: Type = I32;
6238         let expr4_0 = C::shift_mask(ctx, pattern2_0);
6239         let expr5_0 = constructor_and_imm(ctx, expr3_0, expr2_0, expr4_0)?;
6240         let expr6_0: Type = I32;
6241         let expr7_0 = constructor_alu_rrr(ctx, pattern0_0, expr6_0, pattern3_0, expr5_0)?;
6242         return Some(expr7_0);
6243     }
6244     return None;
6245 }
6246 
6247 // Generated as internal constructor for term lower_ushr128.
6248 pub fn constructor_lower_ushr128<C: Context>(
6249     ctx: &mut C,
6250     arg0: ValueRegs,
6251     arg1: Reg,
6252 ) -> Option<ValueRegs> {
6253     let pattern0_0 = arg0;
6254     let pattern1_0 = arg1;
6255     // Rule at src/isa/aarch64/lower.isle line 767.
6256     let expr0_0: usize = 0;
6257     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6258     let expr2_0: usize = 1;
6259     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6260     let expr4_0: Type = I64;
6261     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6262     let expr6_0: Type = I64;
6263     let expr7_0 = constructor_lsr(ctx, expr6_0, expr3_0, pattern1_0)?;
6264     let expr8_0: Type = I32;
6265     let expr9_0 = C::zero_reg(ctx);
6266     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6267     let expr11_0: Type = I64;
6268     let expr12_0: Type = I64;
6269     let expr13_0: u8 = 1;
6270     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6271     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6272     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6273     let expr17_0: Type = I64;
6274     let expr18_0 = constructor_orr(ctx, expr17_0, expr5_0, expr16_0)?;
6275     let expr19_0: Type = I64;
6276     let expr20_0: Type = I64;
6277     let expr21_0: u64 = 64;
6278     let expr22_0 = C::u64_into_imm_logic(ctx, expr20_0, expr21_0);
6279     let expr23_0 = constructor_tst_imm(ctx, expr19_0, pattern1_0, expr22_0)?;
6280     let expr24_0 = Cond::Ne;
6281     let expr25_0 = constructor_csel(ctx, &expr24_0, expr7_0, expr18_0)?;
6282     let expr26_0 = Cond::Ne;
6283     let expr27_0 = C::zero_reg(ctx);
6284     let expr28_0 = constructor_csel(ctx, &expr26_0, expr27_0, expr7_0)?;
6285     let expr29_0 = constructor_consumes_flags_concat(ctx, &expr25_0, &expr28_0)?;
6286     let expr30_0 = constructor_with_flags(ctx, &expr23_0, &expr29_0)?;
6287     return Some(expr30_0);
6288 }
6289 
6290 // Generated as internal constructor for term lower_sshr128.
6291 pub fn constructor_lower_sshr128<C: Context>(
6292     ctx: &mut C,
6293     arg0: ValueRegs,
6294     arg1: Reg,
6295 ) -> Option<ValueRegs> {
6296     let pattern0_0 = arg0;
6297     let pattern1_0 = arg1;
6298     // Rule at src/isa/aarch64/lower.isle line 817.
6299     let expr0_0: usize = 0;
6300     let expr1_0 = C::value_regs_get(ctx, pattern0_0, expr0_0);
6301     let expr2_0: usize = 1;
6302     let expr3_0 = C::value_regs_get(ctx, pattern0_0, expr2_0);
6303     let expr4_0: Type = I64;
6304     let expr5_0 = constructor_lsr(ctx, expr4_0, expr1_0, pattern1_0)?;
6305     let expr6_0: Type = I64;
6306     let expr7_0 = constructor_asr(ctx, expr6_0, expr3_0, pattern1_0)?;
6307     let expr8_0: Type = I32;
6308     let expr9_0 = C::zero_reg(ctx);
6309     let expr10_0 = constructor_orr_not(ctx, expr8_0, expr9_0, pattern1_0)?;
6310     let expr11_0: Type = I64;
6311     let expr12_0: Type = I64;
6312     let expr13_0: u8 = 1;
6313     let expr14_0 = C::imm_shift_from_u8(ctx, expr13_0);
6314     let expr15_0 = constructor_lsl_imm(ctx, expr12_0, expr3_0, expr14_0)?;
6315     let expr16_0 = constructor_lsl(ctx, expr11_0, expr15_0, expr10_0)?;
6316     let expr17_0: Type = I64;
6317     let expr18_0: u8 = 63;
6318     let expr19_0 = C::imm_shift_from_u8(ctx, expr18_0);
6319     let expr20_0 = constructor_asr_imm(ctx, expr17_0, expr3_0, expr19_0)?;
6320     let expr21_0: Type = I64;
6321     let expr22_0 = constructor_orr(ctx, expr21_0, expr5_0, expr16_0)?;
6322     let expr23_0: Type = I64;
6323     let expr24_0: Type = I64;
6324     let expr25_0: u64 = 64;
6325     let expr26_0 = C::u64_into_imm_logic(ctx, expr24_0, expr25_0);
6326     let expr27_0 = constructor_tst_imm(ctx, expr23_0, pattern1_0, expr26_0)?;
6327     let expr28_0 = Cond::Ne;
6328     let expr29_0 = constructor_csel(ctx, &expr28_0, expr7_0, expr22_0)?;
6329     let expr30_0 = Cond::Ne;
6330     let expr31_0 = constructor_csel(ctx, &expr30_0, expr20_0, expr7_0)?;
6331     let expr32_0 = constructor_consumes_flags_concat(ctx, &expr29_0, &expr31_0)?;
6332     let expr33_0 = constructor_with_flags(ctx, &expr27_0, &expr32_0)?;
6333     return Some(expr33_0);
6334 }
6335 
6336 // Generated as internal constructor for term small_rotr.
6337 pub fn constructor_small_rotr<C: Context>(
6338     ctx: &mut C,
6339     arg0: Type,
6340     arg1: Reg,
6341     arg2: Reg,
6342 ) -> Option<Reg> {
6343     let pattern0_0 = arg0;
6344     let pattern1_0 = arg1;
6345     let pattern2_0 = arg2;
6346     // Rule at src/isa/aarch64/lower.isle line 927.
6347     let expr0_0: Type = I32;
6348     let expr1_0 = C::rotr_mask(ctx, pattern0_0);
6349     let expr2_0 = constructor_and_imm(ctx, expr0_0, pattern2_0, expr1_0)?;
6350     let expr3_0: Type = I32;
6351     let expr4_0 = C::ty_bits(ctx, pattern0_0);
6352     let expr5_0 = C::u8_into_imm12(ctx, expr4_0);
6353     let expr6_0 = constructor_sub_imm(ctx, expr3_0, expr2_0, expr5_0)?;
6354     let expr7_0: Type = I32;
6355     let expr8_0 = C::zero_reg(ctx);
6356     let expr9_0 = constructor_sub(ctx, expr7_0, expr8_0, expr6_0)?;
6357     let expr10_0: Type = I32;
6358     let expr11_0 = constructor_lsr(ctx, expr10_0, pattern1_0, expr2_0)?;
6359     let expr12_0: Type = I32;
6360     let expr13_0 = constructor_lsl(ctx, expr12_0, pattern1_0, expr9_0)?;
6361     let expr14_0: Type = I32;
6362     let expr15_0 = constructor_orr(ctx, expr14_0, expr13_0, expr11_0)?;
6363     return Some(expr15_0);
6364 }
6365 
6366 // Generated as internal constructor for term small_rotr_imm.
6367 pub fn constructor_small_rotr_imm<C: Context>(
6368     ctx: &mut C,
6369     arg0: Type,
6370     arg1: Reg,
6371     arg2: ImmShift,
6372 ) -> Option<Reg> {
6373     let pattern0_0 = arg0;
6374     let pattern1_0 = arg1;
6375     let pattern2_0 = arg2;
6376     // Rule at src/isa/aarch64/lower.isle line 948.
6377     let expr0_0: Type = I32;
6378     let expr1_0 = constructor_lsr_imm(ctx, expr0_0, pattern1_0, pattern2_0)?;
6379     let expr2_0: Type = I32;
6380     let expr3_0 = C::rotr_opposite_amount(ctx, pattern0_0, pattern2_0);
6381     let expr4_0 = constructor_lsl_imm(ctx, expr2_0, pattern1_0, expr3_0)?;
6382     let expr5_0: Type = I32;
6383     let expr6_0 = constructor_orr(ctx, expr5_0, expr4_0, expr1_0)?;
6384     return Some(expr6_0);
6385 }
6386 
6387 // Generated as internal constructor for term lower_clz128.
6388 pub fn constructor_lower_clz128<C: Context>(ctx: &mut C, arg0: ValueRegs) -> Option<ValueRegs> {
6389     let pattern0_0 = arg0;
6390     // Rule at src/isa/aarch64/lower.isle line 1013.
6391     let expr0_0: Type = I64;
6392     let expr1_0: usize = 1;
6393     let expr2_0 = C::value_regs_get(ctx, pattern0_0, expr1_0);
6394     let expr3_0 = constructor_a64_clz(ctx, expr0_0, expr2_0)?;
6395     let expr4_0: Type = I64;
6396     let expr5_0: usize = 0;
6397     let expr6_0 = C::value_regs_get(ctx, pattern0_0, expr5_0);
6398     let expr7_0 = constructor_a64_clz(ctx, expr4_0, expr6_0)?;
6399     let expr8_0: Type = I64;
6400     let expr9_0: u8 = 6;
6401     let expr10_0 = C::imm_shift_from_u8(ctx, expr9_0);
6402     let expr11_0 = constructor_lsr_imm(ctx, expr8_0, expr3_0, expr10_0)?;
6403     let expr12_0 = constructor_madd64(ctx, expr7_0, expr11_0, expr3_0)?;
6404     let expr13_0: Type = I64;
6405     let expr14_0: u64 = 0;
6406     let expr15_0 = constructor_imm(ctx, expr13_0, expr14_0)?;
6407     let expr16_0 = C::value_regs(ctx, expr12_0, expr15_0);
6408     return Some(expr16_0);
6409 }
6410