1 use crate::cdsl::settings::{SettingGroup, SettingGroupBuilder}; 2 3 pub(crate) fn define() -> SettingGroup { 4 let mut settings = SettingGroupBuilder::new("shared"); 5 6 settings.add_enum( 7 "regalloc", 8 r#"Register allocator to use with the MachInst backend. 9 10 This selects the register allocator as an option among those offered by the `regalloc.rs` 11 crate. Please report register allocation bugs to the maintainers of this crate whenever 12 possible. 13 14 Note: this only applies to target that use the MachInst backend. As of 2020-04-17, this 15 means the x86_64 backend doesn't use this yet. 16 17 Possible values: 18 19 - `backtracking` is a greedy, backtracking register allocator as implemented in 20 Spidermonkey's optimizing tier IonMonkey. It may take more time to allocate registers, but 21 it should generate better code in general, resulting in better throughput of generated 22 code. 23 - `backtracking_checked` is the backtracking allocator with additional self checks that may 24 take some time to run, and thus these checks are disabled by default. 25 - `experimental_linear_scan` is an experimental linear scan allocator. It may take less 26 time to allocate registers, but generated code's quality may be inferior. As of 27 2020-04-17, it is still experimental and it should not be used in production settings. 28 - `experimental_linear_scan_checked` is the linear scan allocator with additional self 29 checks that may take some time to run, and thus these checks are disabled by default. 30 "#, 31 vec![ 32 "backtracking", 33 "backtracking_checked", 34 "experimental_linear_scan", 35 "experimental_linear_scan_checked", 36 ], 37 ); 38 39 settings.add_enum( 40 "opt_level", 41 r#" 42 Optimization level: 43 44 - none: Minimise compile time by disabling most optimizations. 45 - speed: Generate the fastest possible code 46 - speed_and_size: like "speed", but also perform transformations 47 aimed at reducing code size. 48 "#, 49 vec!["none", "speed", "speed_and_size"], 50 ); 51 52 settings.add_bool( 53 "enable_verifier", 54 r#" 55 Run the Cranelift IR verifier at strategic times during compilation. 56 57 This makes compilation slower but catches many bugs. The verifier is always enabled by 58 default, which is useful during development. 59 "#, 60 true, 61 ); 62 63 // Note that Cranelift doesn't currently need an is_pie flag, because PIE is 64 // just PIC where symbols can't be pre-empted, which can be expressed with the 65 // `colocated` flag on external functions and global values. 66 settings.add_bool( 67 "is_pic", 68 "Enable Position-Independent Code generation", 69 false, 70 ); 71 72 settings.add_bool( 73 "use_colocated_libcalls", 74 r#" 75 Use colocated libcalls. 76 77 Generate code that assumes that libcalls can be declared "colocated", 78 meaning they will be defined along with the current function, such that 79 they can use more efficient addressing. 80 "#, 81 false, 82 ); 83 84 settings.add_bool( 85 "avoid_div_traps", 86 r#" 87 Generate explicit checks around native division instructions to avoid 88 their trapping. 89 90 This is primarily used by SpiderMonkey which doesn't install a signal 91 handler for SIGFPE, but expects a SIGILL trap for division by zero. 92 93 On ISAs like ARM where the native division instructions don't trap, 94 this setting has no effect - explicit checks are always inserted. 95 "#, 96 false, 97 ); 98 99 settings.add_bool( 100 "enable_float", 101 r#" 102 Enable the use of floating-point instructions 103 104 Disabling use of floating-point instructions is not yet implemented. 105 "#, 106 true, 107 ); 108 109 settings.add_bool( 110 "enable_nan_canonicalization", 111 r#" 112 Enable NaN canonicalization 113 114 This replaces NaNs with a single canonical value, for users requiring 115 entirely deterministic WebAssembly computation. This is not required 116 by the WebAssembly spec, so it is not enabled by default. 117 "#, 118 false, 119 ); 120 121 settings.add_bool( 122 "enable_pinned_reg", 123 r#"Enable the use of the pinned register. 124 125 This register is excluded from register allocation, and is completely under the control of 126 the end-user. It is possible to read it via the get_pinned_reg instruction, and to set it 127 with the set_pinned_reg instruction. 128 "#, 129 false, 130 ); 131 132 settings.add_bool( 133 "use_pinned_reg_as_heap_base", 134 r#"Use the pinned register as the heap base. 135 136 Enabling this requires the enable_pinned_reg setting to be set to true. It enables a custom 137 legalization of the `heap_addr` instruction so it will use the pinned register as the heap 138 base, instead of fetching it from a global value. 139 140 Warning! Enabling this means that the pinned register *must* be maintained to contain the 141 heap base address at all times, during the lifetime of a function. Using the pinned 142 register for other purposes when this is set is very likely to cause crashes. 143 "#, 144 false, 145 ); 146 147 settings.add_bool("enable_simd", "Enable the use of SIMD instructions.", false); 148 149 settings.add_bool( 150 "enable_atomics", 151 "Enable the use of atomic instructions", 152 true, 153 ); 154 155 settings.add_bool( 156 "enable_safepoints", 157 r#" 158 Enable safepoint instruction insertions. 159 160 This will allow the emit_stackmaps() function to insert the safepoint 161 instruction on top of calls and interrupt traps in order to display the 162 live reference values at that point in the program. 163 "#, 164 false, 165 ); 166 167 settings.add_enum( 168 "tls_model", 169 r#" 170 Defines the model used to perform TLS accesses. 171 "#, 172 vec!["none", "elf_gd", "macho", "coff"], 173 ); 174 175 // Settings specific to the `baldrdash` calling convention. 176 177 settings.add_enum( 178 "libcall_call_conv", 179 r#" 180 Defines the calling convention to use for LibCalls call expansion, 181 since it may be different from the ISA default calling convention. 182 183 The default value is to use the same calling convention as the ISA 184 default calling convention. 185 186 This list should be kept in sync with the list of calling 187 conventions available in isa/call_conv.rs. 188 "#, 189 vec![ 190 "isa_default", 191 "fast", 192 "cold", 193 "system_v", 194 "windows_fastcall", 195 "baldrdash_system_v", 196 "baldrdash_windows", 197 "probestack", 198 ], 199 ); 200 201 settings.add_num( 202 "baldrdash_prologue_words", 203 r#" 204 Number of pointer-sized words pushed by the baldrdash prologue. 205 206 Functions with the `baldrdash` calling convention don't generate their 207 own prologue and epilogue. They depend on externally generated code 208 that pushes a fixed number of words in the prologue and restores them 209 in the epilogue. 210 211 This setting configures the number of pointer-sized words pushed on the 212 stack when the Cranelift-generated code is entered. This includes the 213 pushed return address on x86. 214 "#, 215 0, 216 ); 217 218 // BaldrMonkey requires that not-yet-relocated function addresses be encoded 219 // as all-ones bitpatterns. 220 settings.add_bool( 221 "emit_all_ones_funcaddrs", 222 "Emit not-yet-relocated function addresses as all-ones bit patterns.", 223 false, 224 ); 225 226 // Stack probing options. 227 228 settings.add_bool( 229 "enable_probestack", 230 r#" 231 Enable the use of stack probes, for calling conventions which support this 232 functionality. 233 "#, 234 true, 235 ); 236 237 settings.add_bool( 238 "probestack_func_adjusts_sp", 239 r#" 240 Set this to true of the stack probe function modifies the stack pointer 241 itself. 242 "#, 243 false, 244 ); 245 246 settings.add_num( 247 "probestack_size_log2", 248 r#" 249 The log2 of the size of the stack guard region. 250 251 Stack frames larger than this size will have stack overflow checked 252 by calling the probestack function. 253 254 The default is 12, which translates to a size of 4096. 255 "#, 256 12, 257 ); 258 259 // Jump table options. 260 261 settings.add_bool( 262 "enable_jump_tables", 263 "Enable the use of jump tables in generated machine code.", 264 true, 265 ); 266 267 settings.build() 268 } 269