1" Vim syntax file 2" Language: VHDL 3" Maintainer: Czo <[email protected]> 4" Credits: Stephan Hegel <[email protected]> 5" Last Change: 2012 Jun 01 6" (Dominique Pelle added @Spell) 7 8" VHSIC Hardware Description Language 9" Very High Scale Integrated Circuit 10 11" For version 5.x: Clear all syntax items 12" For version 6.x: Quit when a syntax file was already loaded 13if version < 600 14 syntax clear 15elseif exists("b:current_syntax") 16 finish 17endif 18 19let s:cpo_save = &cpo 20set cpo&vim 21 22" This is not VHDL. I use the C-Preprocessor cpp to generate different binaries 23" from one VHDL source file. Unfortunately there is no preprocessor for VHDL 24" available. If you don't like this, please remove the following lines. 25syn match cDefine "^#ifdef[ ]\+[A-Za-z_]\+" 26syn match cDefine "^#endif" 27 28" case is not significant 29syn case ignore 30 31" VHDL keywords 32syn keyword vhdlStatement access after alias all assert 33syn keyword vhdlStatement architecture array attribute 34syn keyword vhdlStatement begin block body buffer bus 35syn keyword vhdlStatement case component configuration constant 36syn keyword vhdlStatement disconnect downto 37syn keyword vhdlStatement elsif end entity exit 38syn keyword vhdlStatement file for function 39syn keyword vhdlStatement generate generic group guarded 40syn keyword vhdlStatement impure in inertial inout is 41syn keyword vhdlStatement label library linkage literal loop 42syn keyword vhdlStatement map 43syn keyword vhdlStatement new next null 44syn keyword vhdlStatement of on open others out 45syn keyword vhdlStatement package port postponed procedure process pure 46syn keyword vhdlStatement range record register reject report return 47syn keyword vhdlStatement select severity signal shared 48syn keyword vhdlStatement subtype 49syn keyword vhdlStatement then to transport type 50syn keyword vhdlStatement unaffected units until use 51syn keyword vhdlStatement variable wait when while with 52syn keyword vhdlStatement note warning error failure 53 54" Special match for "if" and "else" since "else if" shouldn't be highlighted. 55" The right keyword is "elsif" 56syn match vhdlStatement "\<\(if\|else\)\>" 57syn match vhdlNone "\<else\s\+if\>$" 58syn match vhdlNone "\<else\s\+if\>\s" 59 60" Predefined VHDL types 61syn keyword vhdlType bit bit_vector 62syn keyword vhdlType character boolean integer real time 63syn keyword vhdlType string severity_level 64" Predefined standard ieee VHDL types 65syn keyword vhdlType positive natural signed unsigned 66syn keyword vhdlType line text 67syn keyword vhdlType std_logic std_logic_vector 68syn keyword vhdlType std_ulogic std_ulogic_vector 69" Predefined non standard VHDL types for Mentor Graphics Sys1076/QuickHDL 70syn keyword vhdlType qsim_state qsim_state_vector 71syn keyword vhdlType qsim_12state qsim_12state_vector 72syn keyword vhdlType qsim_strength 73" Predefined non standard VHDL types for Alliance VLSI CAD 74syn keyword vhdlType mux_bit mux_vector reg_bit reg_vector wor_bit wor_vector 75 76" array attributes 77syn match vhdlAttribute "\'high" 78syn match vhdlAttribute "\'left" 79syn match vhdlAttribute "\'length" 80syn match vhdlAttribute "\'low" 81syn match vhdlAttribute "\'range" 82syn match vhdlAttribute "\'reverse_range" 83syn match vhdlAttribute "\'right" 84syn match vhdlAttribute "\'ascending" 85" block attributes 86syn match vhdlAttribute "\'behaviour" 87syn match vhdlAttribute "\'structure" 88syn match vhdlAttribute "\'simple_name" 89syn match vhdlAttribute "\'instance_name" 90syn match vhdlAttribute "\'path_name" 91syn match vhdlAttribute "\'foreign" 92" signal attribute 93syn match vhdlAttribute "\'active" 94syn match vhdlAttribute "\'delayed" 95syn match vhdlAttribute "\'event" 96syn match vhdlAttribute "\'last_active" 97syn match vhdlAttribute "\'last_event" 98syn match vhdlAttribute "\'last_value" 99syn match vhdlAttribute "\'quiet" 100syn match vhdlAttribute "\'stable" 101syn match vhdlAttribute "\'transaction" 102syn match vhdlAttribute "\'driving" 103syn match vhdlAttribute "\'driving_value" 104" type attributes 105syn match vhdlAttribute "\'base" 106syn match vhdlAttribute "\'high" 107syn match vhdlAttribute "\'left" 108syn match vhdlAttribute "\'leftof" 109syn match vhdlAttribute "\'low" 110syn match vhdlAttribute "\'pos" 111syn match vhdlAttribute "\'pred" 112syn match vhdlAttribute "\'rightof" 113syn match vhdlAttribute "\'succ" 114syn match vhdlAttribute "\'val" 115syn match vhdlAttribute "\'image" 116syn match vhdlAttribute "\'value" 117 118syn keyword vhdlBoolean true false 119 120" for this vector values case is significant 121syn case match 122" Values for standard VHDL types 123syn match vhdlVector "\'[0L1HXWZU\-\?]\'" 124" Values for non standard VHDL types qsim_12state for Mentor Graphics Sys1076/QuickHDL 125syn keyword vhdlVector S0S S1S SXS S0R S1R SXR S0Z S1Z SXZ S0I S1I SXI 126syn case ignore 127 128syn match vhdlVector "B\"[01_]\+\"" 129syn match vhdlVector "O\"[0-7_]\+\"" 130syn match vhdlVector "X\"[0-9a-f_]\+\"" 131syn match vhdlCharacter "'.'" 132syn region vhdlString start=+"+ end=+"+ contains=@Spell 133 134" floating numbers 135syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>" 136syn match vhdlNumber "-\=\<\d\+\.\d\+\>" 137syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\=" 138syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 139" integer numbers 140syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>" 141syn match vhdlNumber "-\=\<\d\+\>" 142syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\=" 143syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 144" operators 145syn keyword vhdlOperator and nand or nor xor xnor 146syn keyword vhdlOperator rol ror sla sll sra srl 147syn keyword vhdlOperator mod rem abs not 148syn match vhdlOperator "[&><=:+\-*\/|]" 149syn match vhdlSpecial "[().,;]" 150" time 151syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 152syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 153 154syn match vhdlComment "--.*$" contains=@Spell 155" syn match vhdlGlobal "[\'$#~!%@?\^\[\]{}\\]" 156 157" Define the default highlighting. 158" For version 5.7 and earlier: only when not done already 159" For version 5.8 and later: only when an item doesn't have highlighting yet 160if version >= 508 || !exists("did_vhdl_syntax_inits") 161 if version < 508 162 let did_vhdl_syntax_inits = 1 163 command -nargs=+ HiLink hi link <args> 164 else 165 command -nargs=+ HiLink hi def link <args> 166 endif 167 168 HiLink cDefine PreProc 169 HiLink vhdlSpecial Special 170 HiLink vhdlStatement Statement 171 HiLink vhdlCharacter String 172 HiLink vhdlString String 173 HiLink vhdlVector String 174 HiLink vhdlBoolean String 175 HiLink vhdlComment Comment 176 HiLink vhdlNumber String 177 HiLink vhdlTime String 178 HiLink vhdlType Type 179 HiLink vhdlOperator Type 180 HiLink vhdlGlobal Error 181 HiLink vhdlAttribute Type 182 183 delcommand HiLink 184endif 185 186let b:current_syntax = "vhdl" 187 188let &cpo = s:cpo_save 189unlet s:cpo_save 190" vim: ts=8 191