1" Vim syntax file 2" Language: VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language] 3" Maintainer: Daniel Kho <[email protected]> 4" Previous Maintainer: Czo <[email protected]> 5" Credits: Stephan Hegel <[email protected]> 6" Last Changed: 2016 Mar 05 by Daniel Kho 7 8if version < 600 9 syntax clear 10elseif exists("b:current_syntax") 11 finish 12endif 13 14let s:cpo_save = &cpo 15set cpo&vim 16 17" case is not significant 18syn case ignore 19 20" VHDL keywords 21syn keyword vhdlStatement access after alias all assert 22syn keyword vhdlStatement architecture array attribute 23syn keyword vhdlStatement assume assume_guarantee 24syn keyword vhdlStatement begin block body buffer bus 25syn keyword vhdlStatement case component configuration constant 26syn keyword vhdlStatement context cover 27syn keyword vhdlStatement default disconnect downto 28syn keyword vhdlStatement elsif end entity exit 29syn keyword vhdlStatement file for function 30syn keyword vhdlStatement fairness force 31syn keyword vhdlStatement generate generic group guarded 32syn keyword vhdlStatement impure in inertial inout is 33syn keyword vhdlStatement label library linkage literal loop 34syn keyword vhdlStatement map 35syn keyword vhdlStatement new next null 36syn keyword vhdlStatement of on open others out 37syn keyword vhdlStatement package port postponed procedure process pure 38syn keyword vhdlStatement parameter property protected 39syn keyword vhdlStatement range record register reject report return 40syn keyword vhdlStatement release restrict restrict_guarantee 41syn keyword vhdlStatement select severity signal shared 42syn keyword vhdlStatement subtype 43syn keyword vhdlStatement sequence strong 44syn keyword vhdlStatement then to transport type 45syn keyword vhdlStatement unaffected units until use 46syn keyword vhdlStatement variable 47syn keyword vhdlStatement vmode vprop vunit 48syn keyword vhdlStatement wait when while with 49syn keyword vhdlStatement note warning error failure 50 51" Linting of conditionals. 52syn match vhdlStatement "\<\(if\|else\)\>" 53syn match vhdlError "\<else\s\+if\>" 54 55" Types and type qualifiers 56" Predefined standard VHDL types 57syn match vhdlType "\<bit\>\'\=" 58syn match vhdlType "\<boolean\>\'\=" 59syn match vhdlType "\<natural\>\'\=" 60syn match vhdlType "\<positive\>\'\=" 61syn match vhdlType "\<integer\>\'\=" 62syn match vhdlType "\<real\>\'\=" 63syn match vhdlType "\<time\>\'\=" 64 65syn match vhdlType "\<bit_vector\>\'\=" 66syn match vhdlType "\<boolean_vector\>\'\=" 67syn match vhdlType "\<integer_vector\>\'\=" 68syn match vhdlType "\<real_vector\>\'\=" 69syn match vhdlType "\<time_vector\>\'\=" 70 71syn match vhdlType "\<character\>\'\=" 72syn match vhdlType "\<string\>\'\=" 73"syn keyword vhdlType severity_level 74syn keyword vhdlType line 75syn keyword vhdlType text 76 77" Predefined standard IEEE VHDL types 78syn match vhdlType "\<std_ulogic\>\'\=" 79syn match vhdlType "\<std_logic\>\'\=" 80syn match vhdlType "\<std_ulogic_vector\>\'\=" 81syn match vhdlType "\<std_logic_vector\>\'\=" 82syn match vhdlType "\<unresolved_signed\>\'\=" 83syn match vhdlType "\<unresolved_unsigned\>\'\=" 84syn match vhdlType "\<u_signed\>\'\=" 85syn match vhdlType "\<u_unsigned\>\'\=" 86syn match vhdlType "\<signed\>\'\=" 87syn match vhdlType "\<unsigned\>\'\=" 88 89 90" array attributes 91syn match vhdlAttribute "\'high" 92syn match vhdlAttribute "\'left" 93syn match vhdlAttribute "\'length" 94syn match vhdlAttribute "\'low" 95syn match vhdlAttribute "\'range" 96syn match vhdlAttribute "\'reverse_range" 97syn match vhdlAttribute "\'right" 98syn match vhdlAttribute "\'ascending" 99" block attributes 100syn match vhdlAttribute "\'simple_name" 101syn match vhdlAttribute "\'instance_name" 102syn match vhdlAttribute "\'path_name" 103syn match vhdlAttribute "\'foreign" " VHPI 104" signal attribute 105syn match vhdlAttribute "\'active" 106syn match vhdlAttribute "\'delayed" 107syn match vhdlAttribute "\'event" 108syn match vhdlAttribute "\'last_active" 109syn match vhdlAttribute "\'last_event" 110syn match vhdlAttribute "\'last_value" 111syn match vhdlAttribute "\'quiet" 112syn match vhdlAttribute "\'stable" 113syn match vhdlAttribute "\'transaction" 114syn match vhdlAttribute "\'driving" 115syn match vhdlAttribute "\'driving_value" 116" type attributes 117syn match vhdlAttribute "\'base" 118syn match vhdlAttribute "\'subtype" 119syn match vhdlAttribute "\'element" 120syn match vhdlAttribute "\'leftof" 121syn match vhdlAttribute "\'pos" 122syn match vhdlAttribute "\'pred" 123syn match vhdlAttribute "\'rightof" 124syn match vhdlAttribute "\'succ" 125syn match vhdlAttribute "\'val" 126syn match vhdlAttribute "\'image" 127syn match vhdlAttribute "\'value" 128 129syn keyword vhdlBoolean true false 130 131" for this vector values case is significant 132syn case match 133" Values for standard VHDL types 134syn match vhdlVector "\'[0L1HXWZU\-\?]\'" 135syn case ignore 136 137syn match vhdlVector "B\"[01_]\+\"" 138syn match vhdlVector "O\"[0-7_]\+\"" 139syn match vhdlVector "X\"[0-9a-f_]\+\"" 140syn match vhdlCharacter "'.'" 141syn region vhdlString start=+"+ end=+"+ 142 143" floating numbers 144syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>" 145syn match vhdlNumber "-\=\<\d\+\.\d\+\>" 146syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\=" 147syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 148" integer numbers 149syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>" 150syn match vhdlNumber "-\=\<\d\+\>" 151syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\=" 152syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 153 154" operators 155syn keyword vhdlOperator and nand or nor xor xnor 156syn keyword vhdlOperator rol ror sla sll sra srl 157syn keyword vhdlOperator mod rem abs not 158 159" Concatenation and math operators 160syn match vhdlOperator "&\|+\|-\|\*\|\/" 161 162" Equality and comparison operators 163syn match vhdlOperator "=\|\/=\|>\|<\|>=" 164 165" Assignment operators 166syn match vhdlOperator "<=\|:=" 167syn match vhdlOperator "=>" 168 169" VHDL-2008 conversion, matching equality/non-equality operators 170syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>=" 171 172" VHDL-2008 external names 173syn match vhdlOperator "<<\|>>" 174 175" Linting for illegal operators 176" '=' 177syn match vhdlError "\(=\)[<=&+\-\*\/\\]\+" 178syn match vhdlError "[=&+\-\*\\]\+\(=\)" 179" '>', '<' 180" Allow external names: '<< ... >>' 181syn match vhdlError "\(>\)[<&+\-\/\\]\+" 182syn match vhdlError "[&+\-\/\\]\+\(>\)" 183syn match vhdlError "\(<\)[&+\-\/\\]\+" 184syn match vhdlError "[>=&+\-\/\\]\+\(<\)" 185" Covers most operators 186" support negative sign after operators. E.g. q<=-b; 187syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|<=\|:=\|=>\)[<>=&+\*\\?:]\+" 188syn match vhdlError "[<>=&+\-\*\\:]\+\(&\|+\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\|=>\)" 189syn match vhdlError "\(?<\|?>\)[<>&+\*\/\\?:]\+" 190syn match vhdlError "\(<<\|>>\)[<>&+\*\/\\?:]\+" 191 192"syn match vhdlError "[?]\+\(&\|+\|\-\|\*\*\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|:=\|=>\)" 193" '/' 194syn match vhdlError "\(\/\)[<>&+\-\*\/\\?:]\+" 195syn match vhdlError "[<>=&+\-\*\/\\:]\+\(\/\)" 196 197syn match vhdlSpecial "<>" 198syn match vhdlSpecial "[().,;]" 199 200 201" time 202syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 203syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 204 205syn case match 206syn keyword vhdlTodo contained TODO NOTE 207syn keyword vhdlFixme contained FIXME 208syn case ignore 209 210syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell 211syn match vhdlComment "\(^\|\s\)--.*" contains=vhdlTodo,vhdlFixme,@Spell 212 213" Standard IEEE P1076.6 preprocessor directives (metacomments). 214syn match vhdlPreProc "/\*\s*rtl_synthesis\s\+\(on\|off\)\s*\*/" 215syn match vhdlPreProc "\(^\|\s\)--\s*rtl_synthesis\s\+\(on\|off\)\s*" 216syn match vhdlPreProc "/\*\s*rtl_syn\s\+\(on\|off\)\s*\*/" 217syn match vhdlPreProc "\(^\|\s\)--\s*rtl_syn\s\+\(on\|off\)\s*" 218 219" Industry-standard directives. These are not standard VHDL, but are commonly 220" used in the industry. 221syn match vhdlPreProc "/\*\s*synthesis\s\+translate_\(on\|off\)\s*\*/" 222"syn match vhdlPreProc "/\*\s*simulation\s\+translate_\(on\|off\)\s*\*/" 223syn match vhdlPreProc "/\*\s*pragma\s\+translate_\(on\|off\)\s*\*/" 224syn match vhdlPreProc "/\*\s*pragma\s\+synthesis_\(on\|off\)\s*\*/" 225syn match vhdlPreProc "/\*\s*synopsys\s\+translate_\(on\|off\)\s*\*/" 226 227syn match vhdlPreProc "\(^\|\s\)--\s*synthesis\s\+translate_\(on\|off\)\s*" 228"syn match vhdlPreProc "\(^\|\s\)--\s*simulation\s\+translate_\(on\|off\)\s*" 229syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+translate_\(on\|off\)\s*" 230syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+synthesis_\(on\|off\)\s*" 231syn match vhdlPreProc "\(^\|\s\)--\s*synopsys\s\+translate_\(on\|off\)\s*" 232 233"Modify the following as needed. The trade-off is performance versus functionality. 234syn sync minlines=600 235 236" Define the default highlighting. 237" For version 5.7 and earlier: only when not done already 238" For version 5.8 and later: only when an item doesn't have highlighting yet 239if version >= 508 || !exists("did_vhdl_syntax_inits") 240 if version < 508 241 let did_vhdl_syntax_inits = 1 242 command -nargs=+ HiLink hi link <args> 243 else 244 command -nargs=+ HiLink hi def link <args> 245 endif 246 247 HiLink vhdlSpecial Special 248 HiLink vhdlStatement Statement 249 HiLink vhdlCharacter Character 250 HiLink vhdlString String 251 HiLink vhdlVector Number 252 HiLink vhdlBoolean Number 253 HiLink vhdlTodo Todo 254 HiLink vhdlFixme Fixme 255 HiLink vhdlComment Comment 256 HiLink vhdlNumber Number 257 HiLink vhdlTime Number 258 HiLink vhdlType Type 259 HiLink vhdlOperator Operator 260 HiLink vhdlError Error 261 HiLink vhdlAttribute Special 262 HiLink vhdlPreProc PreProc 263 264 delcommand HiLink 265endif 266 267let b:current_syntax = "vhdl" 268 269let &cpo = s:cpo_save 270unlet s:cpo_save 271" vim: ts=8 272