1" Vim syntax file 2" Language: VHDL 3" Maintainer: Daniel Kho <[email protected]> 4" Previous Maintainer: Czo <[email protected]> 5" Credits: Stephan Hegel <[email protected]> 6" Last Changed: 2015 Dec 4 by Daniel Kho 7 8" VHSIC (Very High Speed Integrated Circuit) Hardware Description Language 9 10" For version 5.x: Clear all syntax items 11" For version 6.x: Quit when a syntax file was already loaded 12if version < 600 13 syntax clear 14elseif exists("b:current_syntax") 15 finish 16endif 17 18let s:cpo_save = &cpo 19set cpo&vim 20 21" case is not significant 22syn case ignore 23 24" VHDL keywords 25syn keyword vhdlStatement access after alias all assert 26syn keyword vhdlStatement architecture array attribute 27syn keyword vhdlStatement assume assume_guarantee 28syn keyword vhdlStatement begin block body buffer bus 29syn keyword vhdlStatement case component configuration constant 30syn keyword vhdlStatement context cover 31syn keyword vhdlStatement default disconnect downto 32syn keyword vhdlStatement elsif end entity exit 33syn keyword vhdlStatement file for function 34syn keyword vhdlStatement fairness force 35syn keyword vhdlStatement generate generic group guarded 36syn keyword vhdlStatement impure in inertial inout is 37syn keyword vhdlStatement label library linkage literal loop 38syn keyword vhdlStatement map 39syn keyword vhdlStatement new next null 40syn keyword vhdlStatement of on open others out 41syn keyword vhdlStatement package port postponed procedure process pure 42syn keyword vhdlStatement parameter property protected 43syn keyword vhdlStatement range record register reject report return 44syn keyword vhdlStatement release restrict restrict_guarantee 45syn keyword vhdlStatement select severity signal shared 46syn keyword vhdlStatement subtype 47syn keyword vhdlStatement sequence strong 48syn keyword vhdlStatement then to transport type 49syn keyword vhdlStatement unaffected units until use 50syn keyword vhdlStatement variable 51syn keyword vhdlStatement vmode vprop vunit 52syn keyword vhdlStatement wait when while with 53syn keyword vhdlStatement note warning error failure 54 55" Linting of conditionals. 56syn match vhdlStatement "\<\(if\|else\)\>" 57syn match vhdlError "\<else\s\+if\>" 58 59" Predefined VHDL types 60syn keyword vhdlType bit bit_vector 61syn keyword vhdlType character boolean integer real time 62syn keyword vhdlType boolean_vector integer_vector real_vector time_vector 63syn keyword vhdlType string severity_level 64" Predefined standard ieee VHDL types 65syn keyword vhdlType positive natural signed unsigned 66syn keyword vhdlType unresolved_signed unresolved_unsigned u_signed u_unsigned 67syn keyword vhdlType line text 68syn keyword vhdlType std_logic std_logic_vector 69syn keyword vhdlType std_ulogic std_ulogic_vector 70 71" array attributes 72syn match vhdlAttribute "\'high" 73syn match vhdlAttribute "\'left" 74syn match vhdlAttribute "\'length" 75syn match vhdlAttribute "\'low" 76syn match vhdlAttribute "\'range" 77syn match vhdlAttribute "\'reverse_range" 78syn match vhdlAttribute "\'right" 79syn match vhdlAttribute "\'ascending" 80" block attributes 81syn match vhdlAttribute "\'simple_name" 82syn match vhdlAttribute "\'instance_name" 83syn match vhdlAttribute "\'path_name" 84syn match vhdlAttribute "\'foreign" " VHPI 85" signal attribute 86syn match vhdlAttribute "\'active" 87syn match vhdlAttribute "\'delayed" 88syn match vhdlAttribute "\'event" 89syn match vhdlAttribute "\'last_active" 90syn match vhdlAttribute "\'last_event" 91syn match vhdlAttribute "\'last_value" 92syn match vhdlAttribute "\'quiet" 93syn match vhdlAttribute "\'stable" 94syn match vhdlAttribute "\'transaction" 95syn match vhdlAttribute "\'driving" 96syn match vhdlAttribute "\'driving_value" 97" type attributes 98syn match vhdlAttribute "\'base" 99syn match vhdlAttribute "\'subtype" 100syn match vhdlAttribute "\'element" 101syn match vhdlAttribute "\'leftof" 102syn match vhdlAttribute "\'pos" 103syn match vhdlAttribute "\'pred" 104syn match vhdlAttribute "\'rightof" 105syn match vhdlAttribute "\'succ" 106syn match vhdlAttribute "\'val" 107syn match vhdlAttribute "\'image" 108syn match vhdlAttribute "\'value" 109 110syn keyword vhdlBoolean true false 111 112" for this vector values case is significant 113syn case match 114" Values for standard VHDL types 115syn match vhdlVector "\'[0L1HXWZU\-\?]\'" 116syn case ignore 117 118syn match vhdlVector "B\"[01_]\+\"" 119syn match vhdlVector "O\"[0-7_]\+\"" 120syn match vhdlVector "X\"[0-9a-f_]\+\"" 121syn match vhdlCharacter "'.'" 122syn region vhdlString start=+"+ end=+"+ 123 124" floating numbers 125syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>" 126syn match vhdlNumber "-\=\<\d\+\.\d\+\>" 127syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\=" 128syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 129" integer numbers 130syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>" 131syn match vhdlNumber "-\=\<\d\+\>" 132syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\=" 133syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 134 135" operators 136syn keyword vhdlOperator and nand or nor xor xnor 137syn keyword vhdlOperator rol ror sla sll sra srl 138syn keyword vhdlOperator mod rem abs not 139 140" Concatenation and math operators 141syn match vhdlOperator "&\|+\|-\|\*\|\/" 142 143" Equality and comparison operators 144syn match vhdlOperator "=\|\/=\|>\|<\|>=" 145 146" Assignment operators 147syn match vhdlOperator "<=\|:=" 148syn match vhdlOperator "=>" 149 150" VHDL-2008 conversion, matching equality/non-equality operators 151syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>=" 152 153" VHDL-2008 external names 154syn match vhdlOperator "<<\|>>" 155 156" Linting for illegal operators 157" '=' 158syn match vhdlError "\(=\)[<=&+\-\*\/\\]\+" 159syn match vhdlError "[=&+\-\*\\]\+\(=\)" 160" '>', '<' 161" Allow external names: '<< ... >>' 162syn match vhdlError "\(>\)[<&+\-\/\\]\+" 163syn match vhdlError "[&+\-\/\\]\+\(>\)" 164syn match vhdlError "\(<\)[&+\-\/\\]\+" 165syn match vhdlError "[>=&+\-\/\\]\+\(<\)" 166" Covers most operators 167" support negative sign after operators. E.g. q<=-b; 168syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|<=\|:=\|=>\)[<>=&+\*\\?:]\+" 169syn match vhdlError "[<>=&+\-\*\\:]\+\(&\|+\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\|=>\)" 170syn match vhdlError "\(?<\|?>\)[<>&+\*\/\\?:]\+" 171syn match vhdlError "\(<<\|>>\)[<>&+\*\/\\?:]\+" 172 173"syn match vhdlError "[?]\+\(&\|+\|\-\|\*\*\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|:=\|=>\)" 174" '/' 175syn match vhdlError "\(\/\)[<>&+\-\*\/\\?:]\+" 176syn match vhdlError "[<>=&+\-\*\/\\:]\+\(\/\)" 177 178syn match vhdlSpecial "<>" 179syn match vhdlSpecial "[().,;]" 180 181 182" time 183syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 184syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 185 186syn case match 187syn keyword vhdlTodo contained TODO NOTE 188syn keyword vhdlFixme contained FIXME 189syn case ignore 190 191syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell 192syn match vhdlComment "\(^\|\s\)--.*" contains=vhdlTodo,vhdlFixme,@Spell 193 194" Industry-standard directives. These are not standard VHDL, but are commonly 195" used in the industry. 196syn match vhdlPreProc "/\*\s*synthesis\s\+translate_\(on\|off\)\s*\*/" 197"syn match vhdlPreProc "/\*\s*simulation\s\+translate_\(on\|off\)\s*\*/" 198syn match vhdlPreProc "/\*\s*pragma\s\+synthesis_\(on\|off\)\s*\*/" 199syn match vhdlPreProc "/\*\s*synopsys\s\+translate_\(on\|off\)\s*\*/" 200 201syn match vhdlPreProc "\(^\|\s\)--\s*synthesis\s\+translate_\(on\|off\)\s*" 202"syn match vhdlPreProc "\(^\|\s\)--\s*simulation\s\+translate_\(on\|off\)\s*" 203syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+synthesis_\(on\|off\)\s*" 204syn match vhdlPreProc "\(^\|\s\)--\s*synopsys\s\+translate_\(on\|off\)\s*" 205 206"Modify the following as needed. The trade-off is performance versus functionality. 207syn sync minlines=600 208 209" Define the default highlighting. 210" For version 5.7 and earlier: only when not done already 211" For version 5.8 and later: only when an item doesn't have highlighting yet 212if version >= 508 || !exists("did_vhdl_syntax_inits") 213 if version < 508 214 let did_vhdl_syntax_inits = 1 215 command -nargs=+ HiLink hi link <args> 216 else 217 command -nargs=+ HiLink hi def link <args> 218 endif 219 220 HiLink vhdlSpecial Special 221 HiLink vhdlStatement Statement 222 HiLink vhdlCharacter Character 223 HiLink vhdlString String 224 HiLink vhdlVector Number 225 HiLink vhdlBoolean Number 226 HiLink vhdlTodo Todo 227 HiLink vhdlFixme Fixme 228 HiLink vhdlComment Comment 229 HiLink vhdlNumber Number 230 HiLink vhdlTime Number 231 HiLink vhdlType Type 232 HiLink vhdlOperator Operator 233 HiLink vhdlError Error 234 HiLink vhdlAttribute Special 235 HiLink vhdlPreProc PreProc 236 237 delcommand HiLink 238endif 239 240let b:current_syntax = "vhdl" 241 242let &cpo = s:cpo_save 243unlet s:cpo_save 244" vim: ts=8 245