1" Vim syntax file 2" Language: VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language] 3" Maintainer: Daniel Kho <[email protected]> 4" Previous Maintainer: Czo <[email protected]> 5" Credits: Stephan Hegel <[email protected]> 6" Last Changed: 2016 Mar 05 by Daniel Kho 7 8" quit when a syntax file was already loaded 9if exists("b:current_syntax") 10 finish 11endif 12 13let s:cpo_save = &cpo 14set cpo&vim 15 16" case is not significant 17syn case ignore 18 19" VHDL keywords 20syn keyword vhdlStatement access after alias all assert 21syn keyword vhdlStatement architecture array attribute 22syn keyword vhdlStatement assume assume_guarantee 23syn keyword vhdlStatement begin block body buffer bus 24syn keyword vhdlStatement case component configuration constant 25syn keyword vhdlStatement context cover 26syn keyword vhdlStatement default disconnect downto 27syn keyword vhdlStatement elsif end entity exit 28syn keyword vhdlStatement file for function 29syn keyword vhdlStatement fairness force 30syn keyword vhdlStatement generate generic group guarded 31syn keyword vhdlStatement impure in inertial inout is 32syn keyword vhdlStatement label library linkage literal loop 33syn keyword vhdlStatement map 34syn keyword vhdlStatement new next null 35syn keyword vhdlStatement of on open others out 36syn keyword vhdlStatement package port postponed procedure process pure 37syn keyword vhdlStatement parameter property protected 38syn keyword vhdlStatement range record register reject report return 39syn keyword vhdlStatement release restrict restrict_guarantee 40syn keyword vhdlStatement select severity signal shared 41syn keyword vhdlStatement subtype 42syn keyword vhdlStatement sequence strong 43syn keyword vhdlStatement then to transport type 44syn keyword vhdlStatement unaffected units until use 45syn keyword vhdlStatement variable 46syn keyword vhdlStatement vmode vprop vunit 47syn keyword vhdlStatement wait when while with 48syn keyword vhdlStatement note warning error failure 49 50" Linting of conditionals. 51syn match vhdlStatement "\<\(if\|else\)\>" 52syn match vhdlError "\<else\s\+if\>" 53 54" Types and type qualifiers 55" Predefined standard VHDL types 56syn match vhdlType "\<bit\>\'\=" 57syn match vhdlType "\<boolean\>\'\=" 58syn match vhdlType "\<natural\>\'\=" 59syn match vhdlType "\<positive\>\'\=" 60syn match vhdlType "\<integer\>\'\=" 61syn match vhdlType "\<real\>\'\=" 62syn match vhdlType "\<time\>\'\=" 63 64syn match vhdlType "\<bit_vector\>\'\=" 65syn match vhdlType "\<boolean_vector\>\'\=" 66syn match vhdlType "\<integer_vector\>\'\=" 67syn match vhdlType "\<real_vector\>\'\=" 68syn match vhdlType "\<time_vector\>\'\=" 69 70syn match vhdlType "\<character\>\'\=" 71syn match vhdlType "\<string\>\'\=" 72"syn keyword vhdlType severity_level 73syn keyword vhdlType line 74syn keyword vhdlType text 75 76" Predefined standard IEEE VHDL types 77syn match vhdlType "\<std_ulogic\>\'\=" 78syn match vhdlType "\<std_logic\>\'\=" 79syn match vhdlType "\<std_ulogic_vector\>\'\=" 80syn match vhdlType "\<std_logic_vector\>\'\=" 81syn match vhdlType "\<unresolved_signed\>\'\=" 82syn match vhdlType "\<unresolved_unsigned\>\'\=" 83syn match vhdlType "\<u_signed\>\'\=" 84syn match vhdlType "\<u_unsigned\>\'\=" 85syn match vhdlType "\<signed\>\'\=" 86syn match vhdlType "\<unsigned\>\'\=" 87 88 89" array attributes 90syn match vhdlAttribute "\'high" 91syn match vhdlAttribute "\'left" 92syn match vhdlAttribute "\'length" 93syn match vhdlAttribute "\'low" 94syn match vhdlAttribute "\'range" 95syn match vhdlAttribute "\'reverse_range" 96syn match vhdlAttribute "\'right" 97syn match vhdlAttribute "\'ascending" 98" block attributes 99syn match vhdlAttribute "\'simple_name" 100syn match vhdlAttribute "\'instance_name" 101syn match vhdlAttribute "\'path_name" 102syn match vhdlAttribute "\'foreign" " VHPI 103" signal attribute 104syn match vhdlAttribute "\'active" 105syn match vhdlAttribute "\'delayed" 106syn match vhdlAttribute "\'event" 107syn match vhdlAttribute "\'last_active" 108syn match vhdlAttribute "\'last_event" 109syn match vhdlAttribute "\'last_value" 110syn match vhdlAttribute "\'quiet" 111syn match vhdlAttribute "\'stable" 112syn match vhdlAttribute "\'transaction" 113syn match vhdlAttribute "\'driving" 114syn match vhdlAttribute "\'driving_value" 115" type attributes 116syn match vhdlAttribute "\'base" 117syn match vhdlAttribute "\'subtype" 118syn match vhdlAttribute "\'element" 119syn match vhdlAttribute "\'leftof" 120syn match vhdlAttribute "\'pos" 121syn match vhdlAttribute "\'pred" 122syn match vhdlAttribute "\'rightof" 123syn match vhdlAttribute "\'succ" 124syn match vhdlAttribute "\'val" 125syn match vhdlAttribute "\'image" 126syn match vhdlAttribute "\'value" 127 128syn keyword vhdlBoolean true false 129 130" for this vector values case is significant 131syn case match 132" Values for standard VHDL types 133syn match vhdlVector "\'[0L1HXWZU\-\?]\'" 134syn case ignore 135 136syn match vhdlVector "B\"[01_]\+\"" 137syn match vhdlVector "O\"[0-7_]\+\"" 138syn match vhdlVector "X\"[0-9a-f_]\+\"" 139syn match vhdlCharacter "'.'" 140syn region vhdlString start=+"+ end=+"+ 141 142" floating numbers 143syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>" 144syn match vhdlNumber "-\=\<\d\+\.\d\+\>" 145syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\=" 146syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 147" integer numbers 148syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>" 149syn match vhdlNumber "-\=\<\d\+\>" 150syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\=" 151syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 152 153" operators 154syn keyword vhdlOperator and nand or nor xor xnor 155syn keyword vhdlOperator rol ror sla sll sra srl 156syn keyword vhdlOperator mod rem abs not 157 158" Concatenation and math operators 159syn match vhdlOperator "&\|+\|-\|\*\|\/" 160 161" Equality and comparison operators 162syn match vhdlOperator "=\|\/=\|>\|<\|>=" 163 164" Assignment operators 165syn match vhdlOperator "<=\|:=" 166syn match vhdlOperator "=>" 167 168" VHDL-2008 conversion, matching equality/non-equality operators 169syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>=" 170 171" VHDL-2008 external names 172syn match vhdlOperator "<<\|>>" 173 174" Linting for illegal operators 175" '=' 176syn match vhdlError "\(=\)[<=&+\-\*\/\\]\+" 177syn match vhdlError "[=&+\-\*\\]\+\(=\)" 178" '>', '<' 179" Allow external names: '<< ... >>' 180syn match vhdlError "\(>\)[<&+\-\/\\]\+" 181syn match vhdlError "[&+\-\/\\]\+\(>\)" 182syn match vhdlError "\(<\)[&+\-\/\\]\+" 183syn match vhdlError "[>=&+\-\/\\]\+\(<\)" 184" Covers most operators 185" support negative sign after operators. E.g. q<=-b; 186syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|<=\|:=\|=>\)[<>=&+\*\\?:]\+" 187syn match vhdlError "[<>=&+\-\*\\:]\+\(&\|+\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\|=>\)" 188syn match vhdlError "\(?<\|?>\)[<>&+\*\/\\?:]\+" 189syn match vhdlError "\(<<\|>>\)[<>&+\*\/\\?:]\+" 190 191"syn match vhdlError "[?]\+\(&\|+\|\-\|\*\*\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|:=\|=>\)" 192" '/' 193syn match vhdlError "\(\/\)[<>&+\-\*\/\\?:]\+" 194syn match vhdlError "[<>=&+\-\*\/\\:]\+\(\/\)" 195 196syn match vhdlSpecial "<>" 197syn match vhdlSpecial "[().,;]" 198 199 200" time 201syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 202syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 203 204syn case match 205syn keyword vhdlTodo contained TODO NOTE 206syn keyword vhdlFixme contained FIXME 207syn case ignore 208 209syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell 210syn match vhdlComment "\(^\|\s\)--.*" contains=vhdlTodo,vhdlFixme,@Spell 211 212" Standard IEEE P1076.6 preprocessor directives (metacomments). 213syn match vhdlPreProc "/\*\s*rtl_synthesis\s\+\(on\|off\)\s*\*/" 214syn match vhdlPreProc "\(^\|\s\)--\s*rtl_synthesis\s\+\(on\|off\)\s*" 215syn match vhdlPreProc "/\*\s*rtl_syn\s\+\(on\|off\)\s*\*/" 216syn match vhdlPreProc "\(^\|\s\)--\s*rtl_syn\s\+\(on\|off\)\s*" 217 218" Industry-standard directives. These are not standard VHDL, but are commonly 219" used in the industry. 220syn match vhdlPreProc "/\*\s*synthesis\s\+translate_\(on\|off\)\s*\*/" 221"syn match vhdlPreProc "/\*\s*simulation\s\+translate_\(on\|off\)\s*\*/" 222syn match vhdlPreProc "/\*\s*pragma\s\+translate_\(on\|off\)\s*\*/" 223syn match vhdlPreProc "/\*\s*pragma\s\+synthesis_\(on\|off\)\s*\*/" 224syn match vhdlPreProc "/\*\s*synopsys\s\+translate_\(on\|off\)\s*\*/" 225 226syn match vhdlPreProc "\(^\|\s\)--\s*synthesis\s\+translate_\(on\|off\)\s*" 227"syn match vhdlPreProc "\(^\|\s\)--\s*simulation\s\+translate_\(on\|off\)\s*" 228syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+translate_\(on\|off\)\s*" 229syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+synthesis_\(on\|off\)\s*" 230syn match vhdlPreProc "\(^\|\s\)--\s*synopsys\s\+translate_\(on\|off\)\s*" 231 232"Modify the following as needed. The trade-off is performance versus functionality. 233syn sync minlines=600 234 235" Define the default highlighting. 236" Only when an item doesn't have highlighting yet 237 238hi def link vhdlSpecial Special 239hi def link vhdlStatement Statement 240hi def link vhdlCharacter Character 241hi def link vhdlString String 242hi def link vhdlVector Number 243hi def link vhdlBoolean Number 244hi def link vhdlTodo Todo 245hi def link vhdlFixme Fixme 246hi def link vhdlComment Comment 247hi def link vhdlNumber Number 248hi def link vhdlTime Number 249hi def link vhdlType Type 250hi def link vhdlOperator Operator 251hi def link vhdlError Error 252hi def link vhdlAttribute Special 253hi def link vhdlPreProc PreProc 254 255 256let b:current_syntax = "vhdl" 257 258let &cpo = s:cpo_save 259unlet s:cpo_save 260" vim: ts=8 261