1" Vim syntax file 2" Language: VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language] 3" Maintainer: Daniel Kho <[email protected]> 4" Previous Maintainer: Czo <[email protected]> 5" Credits: Stephan Hegel <[email protected]> 6" Last Changed: 2020 Apr 04 by Daniel Kho 7 8" quit when a syntax file was already loaded 9if exists("b:current_syntax") 10 finish 11endif 12 13let s:cpo_save = &cpo 14set cpo&vim 15 16" case is not significant 17syn case ignore 18 19" VHDL 1076-2019 keywords 20syn keyword vhdlStatement access after alias all 21syn keyword vhdlStatement architecture array attribute 22syn keyword vhdlStatement assert assume 23syn keyword vhdlStatement begin block body buffer bus 24syn keyword vhdlStatement case component configuration constant 25syn keyword vhdlStatement context cover 26syn keyword vhdlStatement default disconnect downto 27syn keyword vhdlStatement elsif end entity exit 28syn keyword vhdlStatement file for function 29syn keyword vhdlStatement fairness force 30syn keyword vhdlStatement generate generic group guarded 31syn keyword vhdlStatement impure in inertial inout is 32syn keyword vhdlStatement label library linkage literal loop 33syn keyword vhdlStatement map 34syn keyword vhdlStatement new next null 35syn keyword vhdlStatement of on open others out 36syn keyword vhdlStatement package port postponed procedure process pure 37syn keyword vhdlStatement parameter property protected private 38syn keyword vhdlStatement range record register reject report return 39syn keyword vhdlStatement release restrict 40syn keyword vhdlStatement select severity signal shared subtype 41syn keyword vhdlStatement sequence strong 42syn keyword vhdlStatement then to transport type 43syn keyword vhdlStatement unaffected units until use 44syn keyword vhdlStatement variable view 45syn keyword vhdlStatement vpkg vmode vprop vunit 46syn keyword vhdlStatement wait when while with 47 48" VHDL predefined severity levels 49syn keyword vhdlAttribute note warning error failure 50 51" Linting of conditionals. 52syn match vhdlStatement "\<\(if\|else\)\>" 53syn match vhdlError "\<else\s\+if\>" 54 55" Types and type qualifiers 56" Predefined standard VHDL types 57syn match vhdlType "\<bit\>\'\=" 58syn match vhdlType "\<boolean\>\'\=" 59syn match vhdlType "\<natural\>\'\=" 60syn match vhdlType "\<positive\>\'\=" 61syn match vhdlType "\<integer\>\'\=" 62syn match vhdlType "\<real\>\'\=" 63syn match vhdlType "\<time\>\'\=" 64 65syn match vhdlType "\<bit_vector\>\'\=" 66syn match vhdlType "\<boolean_vector\>\'\=" 67syn match vhdlType "\<integer_vector\>\'\=" 68syn match vhdlType "\<real_vector\>\'\=" 69syn match vhdlType "\<time_vector\>\'\=" 70 71syn match vhdlType "\<character\>\'\=" 72syn match vhdlType "\<string\>\'\=" 73syn keyword vhdlType line text side width 74 75" Predefined standard IEEE VHDL types 76syn match vhdlType "\<std_ulogic\>\'\=" 77syn match vhdlType "\<std_logic\>\'\=" 78syn match vhdlType "\<std_ulogic_vector\>\'\=" 79syn match vhdlType "\<std_logic_vector\>\'\=" 80syn match vhdlType "\<unresolved_signed\>\'\=" 81syn match vhdlType "\<unresolved_unsigned\>\'\=" 82syn match vhdlType "\<u_signed\>\'\=" 83syn match vhdlType "\<u_unsigned\>\'\=" 84syn match vhdlType "\<signed\>\'\=" 85syn match vhdlType "\<unsigned\>\'\=" 86 87 88" array attributes 89syn match vhdlAttribute "\'high" 90syn match vhdlAttribute "\'left" 91syn match vhdlAttribute "\'length" 92syn match vhdlAttribute "\'low" 93syn match vhdlAttribute "\'range" 94syn match vhdlAttribute "\'reverse_range" 95syn match vhdlAttribute "\'right" 96syn match vhdlAttribute "\'ascending" 97" block attributes 98syn match vhdlAttribute "\'simple_name" 99syn match vhdlAttribute "\'instance_name" 100syn match vhdlAttribute "\'path_name" 101syn match vhdlAttribute "\'foreign" " VHPI 102" signal attribute 103syn match vhdlAttribute "\'active" 104syn match vhdlAttribute "\'delayed" 105syn match vhdlAttribute "\'event" 106syn match vhdlAttribute "\'last_active" 107syn match vhdlAttribute "\'last_event" 108syn match vhdlAttribute "\'last_value" 109syn match vhdlAttribute "\'quiet" 110syn match vhdlAttribute "\'stable" 111syn match vhdlAttribute "\'transaction" 112syn match vhdlAttribute "\'driving" 113syn match vhdlAttribute "\'driving_value" 114" type attributes 115syn match vhdlAttribute "\'base" 116syn match vhdlAttribute "\'subtype" 117syn match vhdlAttribute "\'element" 118syn match vhdlAttribute "\'leftof" 119syn match vhdlAttribute "\'pos" 120syn match vhdlAttribute "\'pred" 121syn match vhdlAttribute "\'rightof" 122syn match vhdlAttribute "\'succ" 123syn match vhdlAttribute "\'val" 124syn match vhdlAttribute "\'image" 125syn match vhdlAttribute "\'value" 126" VHDL-2019 interface attribute 127syn match vhdlAttribute "\'converse" 128 129syn keyword vhdlBoolean true false 130 131" for this vector values case is significant 132syn case match 133" Values for standard VHDL types 134syn match vhdlVector "\'[0L1HXWZU\-\?]\'" 135syn case ignore 136 137syn match vhdlVector "B\"[01_]\+\"" 138syn match vhdlVector "O\"[0-7_]\+\"" 139syn match vhdlVector "X\"[0-9a-f_]\+\"" 140syn match vhdlCharacter "'.'" 141syn region vhdlString start=+"+ end=+"+ 142 143" floating numbers 144syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>" 145syn match vhdlNumber "-\=\<\d\+\.\d\+\>" 146syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\=" 147syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 148" integer numbers 149syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>" 150syn match vhdlNumber "-\=\<\d\+\>" 151syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\=" 152syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 153 154" operators 155syn keyword vhdlOperator and nand or nor xor xnor 156syn keyword vhdlOperator rol ror sla sll sra srl 157syn keyword vhdlOperator mod rem abs not 158 159" Concatenation and math operators 160syn match vhdlOperator "&\|+\|-\|\*\|\/" 161 162" Equality and comparison operators 163syn match vhdlOperator "=\|\/=\|>\|<\|>=" 164 165" Assignment operators 166syn match vhdlOperator "<=\|:=" 167syn match vhdlOperator "=>" 168 169" VHDL-202x concurrent signal association (spaceship) operator 170syn match vhdlOperator "<=>" 171 172" VHDL-2008 conversion, matching equality/non-equality operators 173syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>=" 174 175" VHDL-2008 external names 176syn match vhdlOperator "<<\|>>" 177 178" Linting for illegal operators 179" '=' 180syn match vhdlError "\(=\)[<=&+\-\*\/\\]\+" 181syn match vhdlError "[=&+\-\*\\]\+\(=\)" 182" '>', '<' 183" Allow external names: '<< ... >>' 184syn match vhdlError "\(>\)[<&+\-\/\\]\+" 185syn match vhdlError "[&+\-\/\\]\+\(>\)" 186syn match vhdlError "\(<\)[&+\-\/\\]\+" 187syn match vhdlError "[>=&+\-\/\\]\+\(<\)" 188" Covers most operators 189" support negative sign after operators. E.g. q<=-b; 190" Supports VHDL-202x spaceship (concurrent simple signal association). 191syn match vhdlError "\(<=\)[<=&+\*\\?:]\+" 192syn match vhdlError "[>=&+\-\*\\:]\+\(=>\)" 193syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|:=\|=>\)[<>=&+\*\\?:]\+" 194syn match vhdlError "[<>=&+\-\*\\:]\+\(&\|+\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\)" 195syn match vhdlError "\(?<\|?>\)[<>&+\*\/\\?:]\+" 196syn match vhdlError "\(<<\|>>\)[<>&+\*\/\\?:]\+" 197 198"syn match vhdlError "[?]\+\(&\|+\|\-\|\*\*\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|:=\|=>\)" 199" '/' 200syn match vhdlError "\(\/\)[<>&+\-\*\/\\?:]\+" 201syn match vhdlError "[<>=&+\-\*\/\\:]\+\(\/\)" 202 203syn match vhdlSpecial "<>" 204syn match vhdlSpecial "[().,;]" 205 206 207" time 208syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 209syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 210 211syn case match 212syn keyword vhdlTodo contained TODO NOTE 213syn keyword vhdlFixme contained FIXME 214syn case ignore 215 216syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell 217syn match vhdlComment "\(^\|\s\)--.*" contains=vhdlTodo,vhdlFixme,@Spell 218 219" Standard IEEE P1076.6 preprocessor directives (metacomments). 220syn match vhdlPreProc "/\*\s*rtl_synthesis\s\+\(on\|off\)\s*\*/" 221syn match vhdlPreProc "\(^\|\s\)--\s*rtl_synthesis\s\+\(on\|off\)\s*" 222syn match vhdlPreProc "/\*\s*rtl_syn\s\+\(on\|off\)\s*\*/" 223syn match vhdlPreProc "\(^\|\s\)--\s*rtl_syn\s\+\(on\|off\)\s*" 224 225" Industry-standard directives. These are not standard VHDL, but are commonly 226" used in the industry. 227syn match vhdlPreProc "/\*\s*synthesis\s\+translate_\(on\|off\)\s*\*/" 228"syn match vhdlPreProc "/\*\s*simulation\s\+translate_\(on\|off\)\s*\*/" 229syn match vhdlPreProc "/\*\s*pragma\s\+translate_\(on\|off\)\s*\*/" 230syn match vhdlPreProc "/\*\s*pragma\s\+synthesis_\(on\|off\)\s*\*/" 231syn match vhdlPreProc "/\*\s*synopsys\s\+translate_\(on\|off\)\s*\*/" 232 233syn match vhdlPreProc "\(^\|\s\)--\s*synthesis\s\+translate_\(on\|off\)\s*" 234"syn match vhdlPreProc "\(^\|\s\)--\s*simulation\s\+translate_\(on\|off\)\s*" 235syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+translate_\(on\|off\)\s*" 236syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+synthesis_\(on\|off\)\s*" 237syn match vhdlPreProc "\(^\|\s\)--\s*synopsys\s\+translate_\(on\|off\)\s*" 238 239"Modify the following as needed. The trade-off is performance versus functionality. 240syn sync minlines=600 241 242" Define the default highlighting. 243" Only when an item doesn't have highlighting yet 244 245hi def link vhdlSpecial Special 246hi def link vhdlStatement Statement 247hi def link vhdlCharacter Character 248hi def link vhdlString String 249hi def link vhdlVector Number 250hi def link vhdlBoolean Number 251hi def link vhdlTodo Todo 252hi def link vhdlFixme Fixme 253hi def link vhdlComment Comment 254hi def link vhdlNumber Number 255hi def link vhdlTime Number 256hi def link vhdlType Type 257hi def link vhdlOperator Operator 258hi def link vhdlError Error 259hi def link vhdlAttribute Special 260hi def link vhdlPreProc PreProc 261 262 263let b:current_syntax = "vhdl" 264 265let &cpo = s:cpo_save 266unlet s:cpo_save 267 268" vim: ts=8 269