1" Vim syntax file 2" Language: VHDL 3" Maintainer: Daniel Kho <[email protected]> 4" Previous Maintainer: Czo <[email protected]> 5" Credits: Stephan Hegel <[email protected]> 6" Last Changed: 2015 Oct 13 by Daniel Kho 7" $Id: vhdl.vim,v 1.1 2004/06/13 15:34:56 vimboss Exp $ 8 9" VHSIC (Very High Speed Integrated Circuit) Hardware Description Language 10 11" For version 5.x: Clear all syntax items 12" For version 6.x: Quit when a syntax file was already loaded 13if version < 600 14 syntax clear 15elseif exists("b:current_syntax") 16 finish 17endif 18 19let s:cpo_save = &cpo 20set cpo&vim 21 22" This is not VHDL. I use the C-Preprocessor cpp to generate different binaries 23" from one VHDL source file. Unfortunately there is no preprocessor for VHDL 24" available. If you don't like this, please remove the following lines. 25"syn match cDefine "^#ifdef[ ]\+[A-Za-z_]\+" 26"syn match cDefine "^#endif" 27 28" case is not significant 29syn case ignore 30 31" VHDL keywords 32syn keyword vhdlStatement access after alias all assert 33syn keyword vhdlStatement architecture array attribute 34syn keyword vhdlStatement assume assume_guarantee 35syn keyword vhdlStatement begin block body buffer bus 36syn keyword vhdlStatement case component configuration constant 37syn keyword vhdlStatement context cover 38syn keyword vhdlStatement default disconnect downto 39syn keyword vhdlStatement elsif end entity exit 40syn keyword vhdlStatement file for function 41syn keyword vhdlStatement fairness force 42syn keyword vhdlStatement generate generic group guarded 43syn keyword vhdlStatement impure in inertial inout is 44syn keyword vhdlStatement label library linkage literal loop 45syn keyword vhdlStatement map 46syn keyword vhdlStatement new next null 47syn keyword vhdlStatement of on open others out 48syn keyword vhdlStatement package port postponed procedure process pure 49syn keyword vhdlStatement parameter property protected 50syn keyword vhdlStatement range record register reject report return 51syn keyword vhdlStatement release restrict restrict_guarantee 52syn keyword vhdlStatement select severity signal shared 53syn keyword vhdlStatement subtype 54syn keyword vhdlStatement sequence strong 55syn keyword vhdlStatement then to transport type 56syn keyword vhdlStatement unaffected units until use 57syn keyword vhdlStatement variable 58syn keyword vhdlStatement vmode vprop vunit 59syn keyword vhdlStatement wait when while with 60syn keyword vhdlStatement note warning error failure 61 62" Special match for "if" and "else" since "else if" shouldn't be highlighted. 63" The right keyword is "elsif" 64syn match vhdlStatement "\<\(if\|else\)\>" 65syn match vhdlNone "\<else\s\+if\>$" 66syn match vhdlNone "\<else\s\+if\>\s" 67 68" Predefined VHDL types 69syn keyword vhdlType bit bit_vector 70syn keyword vhdlType character boolean integer real time 71syn keyword vhdlType boolean_vector integer_vector real_vector time_vector 72syn keyword vhdlType string severity_level 73" Predefined standard ieee VHDL types 74syn keyword vhdlType positive natural signed unsigned 75syn keyword vhdlType unresolved_signed unresolved_unsigned u_signed u_unsigned 76syn keyword vhdlType line text 77syn keyword vhdlType std_logic std_logic_vector 78syn keyword vhdlType std_ulogic std_ulogic_vector 79" Predefined non standard VHDL types for Mentor Graphics Sys1076/QuickHDL 80"syn keyword vhdlType qsim_state qsim_state_vector 81"syn keyword vhdlType qsim_12state qsim_12state_vector 82"syn keyword vhdlType qsim_strength 83" Predefined non standard VHDL types for Alliance VLSI CAD 84"syn keyword vhdlType mux_bit mux_vector reg_bit reg_vector wor_bit wor_vector 85 86" array attributes 87syn match vhdlAttribute "\'high" 88syn match vhdlAttribute "\'left" 89syn match vhdlAttribute "\'length" 90syn match vhdlAttribute "\'low" 91syn match vhdlAttribute "\'range" 92syn match vhdlAttribute "\'reverse_range" 93syn match vhdlAttribute "\'right" 94syn match vhdlAttribute "\'ascending" 95" block attributes 96"syn match vhdlAttribute "\'behaviour" " Non-standard VHDL 97"syn match vhdlAttribute "\'structure" " Non-standard VHDL 98syn match vhdlAttribute "\'simple_name" 99syn match vhdlAttribute "\'instance_name" 100syn match vhdlAttribute "\'path_name" 101syn match vhdlAttribute "\'foreign" " VHPI 102" signal attribute 103syn match vhdlAttribute "\'active" 104syn match vhdlAttribute "\'delayed" 105syn match vhdlAttribute "\'event" 106syn match vhdlAttribute "\'last_active" 107syn match vhdlAttribute "\'last_event" 108syn match vhdlAttribute "\'last_value" 109syn match vhdlAttribute "\'quiet" 110syn match vhdlAttribute "\'stable" 111syn match vhdlAttribute "\'transaction" 112syn match vhdlAttribute "\'driving" 113syn match vhdlAttribute "\'driving_value" 114" type attributes 115syn match vhdlAttribute "\'base" 116syn match vhdlAttribute "\'subtype" 117syn match vhdlAttribute "\'element" 118syn match vhdlAttribute "\'leftof" 119syn match vhdlAttribute "\'pos" 120syn match vhdlAttribute "\'pred" 121syn match vhdlAttribute "\'rightof" 122syn match vhdlAttribute "\'succ" 123syn match vhdlAttribute "\'val" 124syn match vhdlAttribute "\'image" 125syn match vhdlAttribute "\'value" 126 127syn keyword vhdlBoolean true false 128 129" for this vector values case is significant 130syn case match 131" Values for standard VHDL types 132syn match vhdlVector "\'[0L1HXWZU\-\?]\'" 133" Values for non standard VHDL types qsim_12state for Mentor Graphics Sys1076/QuickHDL 134"syn keyword vhdlVector S0S S1S SXS S0R S1R SXR S0Z S1Z SXZ S0I S1I SXI 135syn case ignore 136 137syn match vhdlVector "B\"[01_]\+\"" 138syn match vhdlVector "O\"[0-7_]\+\"" 139syn match vhdlVector "X\"[0-9a-f_]\+\"" 140syn match vhdlCharacter "'.'" 141syn region vhdlString start=+"+ end=+"+ 142 143" floating numbers 144syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>" 145syn match vhdlNumber "-\=\<\d\+\.\d\+\>" 146syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\=" 147syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 148" integer numbers 149syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>" 150syn match vhdlNumber "-\=\<\d\+\>" 151syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\=" 152syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 153 154" operators 155syn keyword vhdlOperator and nand or nor xor xnor 156syn keyword vhdlOperator rol ror sla sll sra srl 157syn keyword vhdlOperator mod rem abs not 158" TODO remove the following line. You can't have a sequence of */=+ as an operator for example. 159"syn match vhdlOperator "[&><=:+\-*\/|]" 160" The following lines match valid and invalid operators. 161 162" Concatenation and math operators 163syn match vhdlOperator "&\|+\|-\|\*\|\/" 164 165" Equality and comparison operators 166syn match vhdlOperator "=\|\/=\|>\|<\|>=" 167 168" Assignment operators 169syn match vhdlOperator "<=\|:=" 170syn match vhdlOperator "=>" 171 172" VHDL-2008 conversion, matching equality/non-equality operators 173syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>=" 174 175" Linting for illegal operators 176" '=' 177syn match vhdlError "\(=\)[<=&+\-\*\/\\]\+" 178syn match vhdlError "[=&+\-\*\\]\+\(=\)" 179" '>', '<' 180syn match vhdlError "\(>\)[<>&+\-\/\\]\+" 181syn match vhdlError "[>&+\-\/\\]\+\(>\)" 182syn match vhdlError "\(<\)[<&+\-\/\\]\+" 183syn match vhdlError "[<>=&+\-\/\\]\+\(<\)" 184" Covers most operators 185syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|<=\|:=\|=>\)[<>=&+\-\*\\?:]\+" 186syn match vhdlError "[<>=&+\-\*\\:]\+\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\|=>\)" 187syn match vhdlError "\(?<\|?>\)[<>&+\-\*\/\\?:]\+" 188 189"syn match vhdlError "[?]\+\(&\|+\|\-\|\*\*\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|:=\|=>\)" 190" '/' 191syn match vhdlError "\(\/\)[<>&+\-\*\/\\?:]\+" 192syn match vhdlError "[<>=&+\-\*\/\\:]\+\(\/\)" 193 194syn match vhdlSpecial "<>" 195syn match vhdlSpecial "[().,;]" 196 197 198" time 199syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 200syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 201 202syn case match 203syn keyword vhdlTodo contained TODO NOTE 204syn keyword vhdlFixme contained FIXME 205syn case ignore 206 207syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell 208syn match vhdlComment "\(^\|\s\)--.*" contains=vhdlTodo,vhdlFixme,@Spell 209 210" Industry-standard directives. These are not standard VHDL, but are commonly 211" used in the industry. 212syn match vhdlPreProc "/\* synthesis .* \*/" 213"syn match vhdlPreProc "/\* simulation .* \*/" 214syn match vhdlPreProc "/\* pragma .* \*/" 215syn match vhdlPreProc "/\* synopsys .* \*/" 216syn match vhdlPreProc "--\s*synthesis .*" 217"syn match vhdlPreProc "--\s*simulation .*" 218syn match vhdlPreProc "--\s*pragma .*" 219syn match vhdlPreProc "--\s*synopsys .*" 220 221"Modify the following as needed. The trade-off is performance versus functionality. 222syn sync minlines=600 223 224" Define the default highlighting. 225" For version 5.7 and earlier: only when not done already 226" For version 5.8 and later: only when an item doesn't have highlighting yet 227if version >= 508 || !exists("did_vhdl_syntax_inits") 228 if version < 508 229 let did_vhdl_syntax_inits = 1 230 command -nargs=+ HiLink hi link <args> 231 else 232 command -nargs=+ HiLink hi def link <args> 233 endif 234 235 HiLink vhdlSpecial Special 236 HiLink vhdlStatement Statement 237 HiLink vhdlCharacter Character 238 HiLink vhdlString String 239 HiLink vhdlVector Number 240 HiLink vhdlBoolean Number 241 HiLink vhdlTodo Todo 242 HiLink vhdlFixme Fixme 243 HiLink vhdlComment Comment 244 HiLink vhdlNumber Number 245 HiLink vhdlTime Number 246 HiLink vhdlType Type 247 HiLink vhdlOperator Operator 248 HiLink vhdlError Error 249 HiLink vhdlAttribute Special 250 HiLink vhdlPreProc PreProc 251 252 delcommand HiLink 253endif 254 255let b:current_syntax = "vhdl" 256 257let &cpo = s:cpo_save 258unlet s:cpo_save 259" vim: ts=8 260