1" Vim syntax file 2" Language: VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language] 3" Maintainer: Daniel Kho <[email protected]> 4" Previous Maintainer: Czo <[email protected]> 5" Credits: Stephan Hegel <[email protected]> 6" Last Changed: 2018 May 06 by Daniel Kho 7 8" quit when a syntax file was already loaded 9if exists("b:current_syntax") 10 finish 11endif 12 13let s:cpo_save = &cpo 14set cpo&vim 15 16" case is not significant 17syn case ignore 18 19" VHDL keywords 20syn keyword vhdlStatement access after alias all assert 21syn keyword vhdlStatement architecture array attribute 22syn keyword vhdlStatement assume assume_guarantee 23syn keyword vhdlStatement begin block body buffer bus 24syn keyword vhdlStatement case component configuration constant 25syn keyword vhdlStatement context cover 26syn keyword vhdlStatement default disconnect downto 27syn keyword vhdlStatement elsif end entity exit 28syn keyword vhdlStatement file for function 29syn keyword vhdlStatement fairness force 30syn keyword vhdlStatement generate generic group guarded 31syn keyword vhdlStatement impure in inertial inout is 32syn keyword vhdlStatement label library linkage literal loop 33syn keyword vhdlStatement map 34syn keyword vhdlStatement new next null 35syn keyword vhdlStatement of on open others out 36syn keyword vhdlStatement package port postponed procedure process pure 37syn keyword vhdlStatement parameter property protected 38syn keyword vhdlStatement range record register reject report return 39syn keyword vhdlStatement release restrict restrict_guarantee 40syn keyword vhdlStatement select severity signal shared 41syn keyword vhdlStatement subtype 42syn keyword vhdlStatement sequence strong 43syn keyword vhdlStatement then to transport type 44syn keyword vhdlStatement unaffected units until use 45syn keyword vhdlStatement variable 46" VHDL-2017 interface 47syn keyword vhdlStatement view 48syn keyword vhdlStatement vmode vprop vunit 49syn keyword vhdlStatement wait when while with 50syn keyword vhdlStatement note warning error failure 51 52" Linting of conditionals. 53syn match vhdlStatement "\<\(if\|else\)\>" 54syn match vhdlError "\<else\s\+if\>" 55 56" Types and type qualifiers 57" Predefined standard VHDL types 58syn match vhdlType "\<bit\>\'\=" 59syn match vhdlType "\<boolean\>\'\=" 60syn match vhdlType "\<natural\>\'\=" 61syn match vhdlType "\<positive\>\'\=" 62syn match vhdlType "\<integer\>\'\=" 63syn match vhdlType "\<real\>\'\=" 64syn match vhdlType "\<time\>\'\=" 65 66syn match vhdlType "\<bit_vector\>\'\=" 67syn match vhdlType "\<boolean_vector\>\'\=" 68syn match vhdlType "\<integer_vector\>\'\=" 69syn match vhdlType "\<real_vector\>\'\=" 70syn match vhdlType "\<time_vector\>\'\=" 71 72syn match vhdlType "\<character\>\'\=" 73syn match vhdlType "\<string\>\'\=" 74syn keyword vhdlType line text side width 75 76" Predefined standard IEEE VHDL types 77syn match vhdlType "\<std_ulogic\>\'\=" 78syn match vhdlType "\<std_logic\>\'\=" 79syn match vhdlType "\<std_ulogic_vector\>\'\=" 80syn match vhdlType "\<std_logic_vector\>\'\=" 81syn match vhdlType "\<unresolved_signed\>\'\=" 82syn match vhdlType "\<unresolved_unsigned\>\'\=" 83syn match vhdlType "\<u_signed\>\'\=" 84syn match vhdlType "\<u_unsigned\>\'\=" 85syn match vhdlType "\<signed\>\'\=" 86syn match vhdlType "\<unsigned\>\'\=" 87 88 89" array attributes 90syn match vhdlAttribute "\'high" 91syn match vhdlAttribute "\'left" 92syn match vhdlAttribute "\'length" 93syn match vhdlAttribute "\'low" 94syn match vhdlAttribute "\'range" 95syn match vhdlAttribute "\'reverse_range" 96syn match vhdlAttribute "\'right" 97syn match vhdlAttribute "\'ascending" 98" block attributes 99syn match vhdlAttribute "\'simple_name" 100syn match vhdlAttribute "\'instance_name" 101syn match vhdlAttribute "\'path_name" 102syn match vhdlAttribute "\'foreign" " VHPI 103" signal attribute 104syn match vhdlAttribute "\'active" 105syn match vhdlAttribute "\'delayed" 106syn match vhdlAttribute "\'event" 107syn match vhdlAttribute "\'last_active" 108syn match vhdlAttribute "\'last_event" 109syn match vhdlAttribute "\'last_value" 110syn match vhdlAttribute "\'quiet" 111syn match vhdlAttribute "\'stable" 112syn match vhdlAttribute "\'transaction" 113syn match vhdlAttribute "\'driving" 114syn match vhdlAttribute "\'driving_value" 115" type attributes 116syn match vhdlAttribute "\'base" 117syn match vhdlAttribute "\'subtype" 118syn match vhdlAttribute "\'element" 119syn match vhdlAttribute "\'leftof" 120syn match vhdlAttribute "\'pos" 121syn match vhdlAttribute "\'pred" 122syn match vhdlAttribute "\'rightof" 123syn match vhdlAttribute "\'succ" 124syn match vhdlAttribute "\'val" 125syn match vhdlAttribute "\'image" 126syn match vhdlAttribute "\'value" 127" VHDL-2017 interface attribute 128syn match vhdlAttribute "\'converse" 129 130syn keyword vhdlBoolean true false 131 132" for this vector values case is significant 133syn case match 134" Values for standard VHDL types 135syn match vhdlVector "\'[0L1HXWZU\-\?]\'" 136syn case ignore 137 138syn match vhdlVector "B\"[01_]\+\"" 139syn match vhdlVector "O\"[0-7_]\+\"" 140syn match vhdlVector "X\"[0-9a-f_]\+\"" 141syn match vhdlCharacter "'.'" 142syn region vhdlString start=+"+ end=+"+ 143 144" floating numbers 145syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>" 146syn match vhdlNumber "-\=\<\d\+\.\d\+\>" 147syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\=" 148syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 149" integer numbers 150syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>" 151syn match vhdlNumber "-\=\<\d\+\>" 152syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\=" 153syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 154 155" operators 156syn keyword vhdlOperator and nand or nor xor xnor 157syn keyword vhdlOperator rol ror sla sll sra srl 158syn keyword vhdlOperator mod rem abs not 159 160" Concatenation and math operators 161syn match vhdlOperator "&\|+\|-\|\*\|\/" 162 163" Equality and comparison operators 164syn match vhdlOperator "=\|\/=\|>\|<\|>=" 165 166" Assignment operators 167syn match vhdlOperator "<=\|:=" 168syn match vhdlOperator "=>" 169 170" VHDL-2017 concurrent signal association (spaceship) operator 171syn match vhdlOperator "<=>" 172 173" VHDL-2008 conversion, matching equality/non-equality operators 174syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>=" 175 176" VHDL-2008 external names 177syn match vhdlOperator "<<\|>>" 178 179" Linting for illegal operators 180" '=' 181syn match vhdlError "\(=\)[<=&+\-\*\/\\]\+" 182syn match vhdlError "[=&+\-\*\\]\+\(=\)" 183" '>', '<' 184" Allow external names: '<< ... >>' 185syn match vhdlError "\(>\)[<&+\-\/\\]\+" 186syn match vhdlError "[&+\-\/\\]\+\(>\)" 187syn match vhdlError "\(<\)[&+\-\/\\]\+" 188syn match vhdlError "[>=&+\-\/\\]\+\(<\)" 189" Covers most operators 190" support negative sign after operators. E.g. q<=-b; 191" Supports VHDL-2017 spaceship (concurrent simple signal association). 192syn match vhdlError "\(<=\)[<=&+\*\\?:]\+" 193syn match vhdlError "[>=&+\-\*\\:]\+\(=>\)" 194syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|:=\|=>\)[<>=&+\*\\?:]\+" 195syn match vhdlError "[<>=&+\-\*\\:]\+\(&\|+\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\)" 196syn match vhdlError "\(?<\|?>\)[<>&+\*\/\\?:]\+" 197syn match vhdlError "\(<<\|>>\)[<>&+\*\/\\?:]\+" 198 199"syn match vhdlError "[?]\+\(&\|+\|\-\|\*\*\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|:=\|=>\)" 200" '/' 201syn match vhdlError "\(\/\)[<>&+\-\*\/\\?:]\+" 202syn match vhdlError "[<>=&+\-\*\/\\:]\+\(\/\)" 203 204syn match vhdlSpecial "<>" 205syn match vhdlSpecial "[().,;]" 206 207 208" time 209syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 210syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 211 212syn case match 213syn keyword vhdlTodo contained TODO NOTE 214syn keyword vhdlFixme contained FIXME 215syn case ignore 216 217syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell 218syn match vhdlComment "\(^\|\s\)--.*" contains=vhdlTodo,vhdlFixme,@Spell 219 220" Standard IEEE P1076.6 preprocessor directives (metacomments). 221syn match vhdlPreProc "/\*\s*rtl_synthesis\s\+\(on\|off\)\s*\*/" 222syn match vhdlPreProc "\(^\|\s\)--\s*rtl_synthesis\s\+\(on\|off\)\s*" 223syn match vhdlPreProc "/\*\s*rtl_syn\s\+\(on\|off\)\s*\*/" 224syn match vhdlPreProc "\(^\|\s\)--\s*rtl_syn\s\+\(on\|off\)\s*" 225 226" Industry-standard directives. These are not standard VHDL, but are commonly 227" used in the industry. 228syn match vhdlPreProc "/\*\s*synthesis\s\+translate_\(on\|off\)\s*\*/" 229"syn match vhdlPreProc "/\*\s*simulation\s\+translate_\(on\|off\)\s*\*/" 230syn match vhdlPreProc "/\*\s*pragma\s\+translate_\(on\|off\)\s*\*/" 231syn match vhdlPreProc "/\*\s*pragma\s\+synthesis_\(on\|off\)\s*\*/" 232syn match vhdlPreProc "/\*\s*synopsys\s\+translate_\(on\|off\)\s*\*/" 233 234syn match vhdlPreProc "\(^\|\s\)--\s*synthesis\s\+translate_\(on\|off\)\s*" 235"syn match vhdlPreProc "\(^\|\s\)--\s*simulation\s\+translate_\(on\|off\)\s*" 236syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+translate_\(on\|off\)\s*" 237syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+synthesis_\(on\|off\)\s*" 238syn match vhdlPreProc "\(^\|\s\)--\s*synopsys\s\+translate_\(on\|off\)\s*" 239 240"Modify the following as needed. The trade-off is performance versus functionality. 241syn sync minlines=600 242 243" Define the default highlighting. 244" Only when an item doesn't have highlighting yet 245 246hi def link vhdlSpecial Special 247hi def link vhdlStatement Statement 248hi def link vhdlCharacter Character 249hi def link vhdlString String 250hi def link vhdlVector Number 251hi def link vhdlBoolean Number 252hi def link vhdlTodo Todo 253hi def link vhdlFixme Fixme 254hi def link vhdlComment Comment 255hi def link vhdlNumber Number 256hi def link vhdlTime Number 257hi def link vhdlType Type 258hi def link vhdlOperator Operator 259hi def link vhdlError Error 260hi def link vhdlAttribute Special 261hi def link vhdlPreProc PreProc 262 263 264let b:current_syntax = "vhdl" 265 266let &cpo = s:cpo_save 267unlet s:cpo_save 268" vim: ts=8 269